[libcpu][asm9260t] Add new BSP for AlphaScale ASM9260T

16 files changed, 1869 insertions, 0 deletions

diff --git a/bsp/asm9260t/platform/SConscript b/bsp/asm9260t/platform/SConscript
new file mode 100644
index 0000000000..5df4a5fc63
--- /dev/null
+++ b/bsp/asm9260t/platform/SConscript
@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+# The set of source files associated with this SConscript file.
+src = Glob('*.c')
+
+group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
diff --git a/bsp/asm9260t/platform/asm9260t.h b/bsp/asm9260t/platform/asm9260t.h
new file mode 100644
index 0000000000..440375ce9a
--- /dev/null
+++ b/bsp/asm9260t/platform/asm9260t.h
@@ -0,0 +1,670 @@
+#ifndef __ASM9260T_REGS_H__
+#define __ASM9260T_REGS_H__
+////////////////////////////////////////////////////////////////////////////////
+
+typedef volatile unsigned char *VP8;
+typedef volatile unsigned short *VP16;
+typedef volatile unsigned long *VP32;
+
+#define __I  volatile const   /*!< Defines 'read only' permissions    */
+#define __O  volatile         /*!< Defines 'write only' permissions   */
+#define __IO volatile         /*!< Defines 'read / write' permissions */
+
+#define outb(v, r)      do{*((VP8)(r))=(v);}while(0)
+#define outw(v, r)      do{*((VP16)(r))=(v);}while(0)
+#define outl(v, r)      do{*((VP32)(r))=(v);}while(0)
+
+#define inb(r)          (*((VP8)(r)))
+#define inw(r)          (*((VP16)(r)))
+#define inl(r)          (*((VP32)(r)))
+
+#define REG_VAL(r)      (((unsigned long)(r))+0x00)
+#define REG_SET(r)      (((unsigned long)(r))+0x04)
+#define REG_CLR(r)      (((unsigned long)(r))+0x08)
+#define REG_TOG(r)      (((unsigned long)(r))+0x0C)
+
+////////////////////////////////////////////////////////////////////////////////
+// SYSTEM CONFIG
+#define HW_PRESETCTRL0        0x80040000
+#define HW_PRESETCTRL1        0x80040010
+#define HW_AHBCLKCTRL0        0x80040020
+#define HW_AHBCLKCTRL1        0x80040030
+#define HW_SYSTCKCAL          0x80040040
+#define HW_SYSPLLCTRL         0x80040100
+#define HW_SYSPLLSTAT         0x80040104
+#define HW_SYSRSTSTAT         0x80040110
+#define HW_MAINCLKSEL         0x80040120
+#define HW_MAINCLKUEN         0x80040124
+#define HW_UARTCLKSEL         0x80040128
+#define HW_UARTCLKUEN         0x8004012C
+#define HW_I2S0CLKSEL         0x80040130
+#define HW_I2S0CLKUEN         0x80040134
+#define HW_I2S1CLKSEL         0x80040138
+#define HW_I2S1CLKUEN         0x8004013C
+#define HW_USBCLKSEL          0x80040140
+#define HW_USBCLKUEN          0x80040144
+#define HW_WDTCLKSEL          0x80040160
+#define HW_WDTCLKUEN          0x80040164
+#define HW_OUTCLKSEL          0x80040170
+#define HW_OUTCLKUEN          0x80040174
+#define HW_CPUCLKDIV          0x8004017C
+#define HW_SYSAHBCLKDIV       0x80040180
+#define HW_I2S1_MCLKDIV       0x80040188
+#define HW_I2S1_SCLKDIV       0x8004018C
+#define HW_I2S0_MCLKDIV       0x80040190
+#define HW_I2S0_SCLKDIV       0x80040194
+#define HW_UART0CLKDIV        0x80040198
+#define HW_UART1CLKDIV        0x8004019C
+#define HW_UART2CLKDIV        0x800401A0
+#define HW_UART3CLKDIV        0x800401A4
+#define HW_UART4CLKDIV        0x800401A8
+#define HW_UART5CLKDIV        0x800401AC
+#define HW_UART6CLKDIV        0x800401B0
+#define HW_UART7CLKDIV        0x800401B4
+#define HW_UART8CLKDIV        0x800401B8
+#define HW_UART9CLKDIV        0x800401BC
+#define HW_SPI0CLKDIV         0x800401C0
+#define HW_SPI1CLKDIV         0x800401C4
+#define HW_QUADSPI0CLKDIV     0x800401C8
+#define HW_SSP0CLKDIV         0x800401D0
+#define HW_NANDCLKDIV         0x800401D4
+#define HW_TRACECLKDIV        0x800401E0
+#define HW_CAMMCLKDIV         0x800401E8
+#define HW_WDTCLKDIV          0x800401EC
+#define HW_USBCLKDIV          0x800401F0
+#define HW_OUTCLKDIV          0x800401F4
+#define HW_MACCLKDIV          0x800401F8
+#define HW_LCDCLKDIV          0x800401FC
+#define HW_ADCCLKDIV          0x80040200
+#define HW_PDRUNCFG           0x80040238
+#define HW_MATRIXPRI0         0x80040300
+#define HW_MATRIXPRI1         0x80040304
+#define HW_MATRIXPRI2         0x80040308
+#define HW_MATRIXPRI3         0x8004030C
+#define HW_MATRIXPRI4         0x80040310
+#define HW_MATRIXPRI5         0x80040314
+#define HW_MATRIXPRI6         0x80040318
+#define HW_MATRIXPRI7         0x8004031C
+#define HW_MATRIXPRI8         0x80040320
+#define HW_MATRIXPRI9         0x80040324
+#define HW_MATRIXPRI10        0x80040328
+#define HW_MATRIXPRI11        0x8004032C
+#define HW_MATRIXPRI12        0x80040330
+#define HW_MATRIXPRI13        0x80040334
+#define HW_MATRIXPRI14        0x80040338
+#define HW_MATRIXPRI15        0x8004033C
+#define HW_EMI_CTRL           0x8004034C
+#define HW_RISC_CTRL          0x80040350
+#define HW_DMA_CTRL           0x80040354
+#define HW_MACPHY_SEL         0x80040360
+#define HW_USB_CTRL           0x80040368
+#define HW_ANA_CTRL           0x80040370
+#define HW_USB0_TEST          0x80040380
+#define HW_USB1_TEST          0x80040390
+#define HW_USB0_RSTPARA       0x800403A0
+#define HW_USB1_RSTPARA       0x800403B0
+#define HW_DEVICEID           0x80040400
+#define HW_PCON_ADDR          0x80040500
+
+////////////////////////////////////////////////////////////////////////////////
+// EMI
+#define HW_EMI_SCONR          0x80700000    
+#define HW_EMI_STMG0R         0x80700004
+#define HW_EMI_STMG1R         0x80700008
+#define HW_EMI_SCTLR          0x8070000C
+#define HW_EMI_SREFR          0x80700010
+#define HW_EMI_SCSLR0_LOW     0x80700014
+#define HW_EMI_SCSLR1_LOW     0x80700018
+#define HW_EMI_SCSLR2_LOW     0x8070001c
+#define HW_EMI_SCSLR3_LOW     0x80700020
+#define HW_EMI_SCSLR4_LOW     0x80700024
+#define HW_EMI_SCSLR5_LOW     0x80700028
+#define HW_EMI_SCSLR6_LOW     0x8070002c
+#define HW_EMI_SCSLR7_LOW     0x80700030
+
+#define HW_EMI_SMSKR0         0x80700054
+#define HW_EMI_SMSKR1         0x80700058
+#define HW_EMI_SMSKR2         0x8070005c
+#define HW_EMI_SMSKR3         0x80700060
+#define HW_EMI_SMSKR4         0x80700064
+#define HW_EMI_SMSKR5         0x80700068
+#define HW_EMI_SMSKR6         0x8070006c
+#define HW_EMI_SMSKR7         0x80700070
+
+#define HW_EMI_CSALIAS0_LOW   0x80700074
+#define HW_EMI_CSALIAS1_LOW   0x80700078
+
+#define HW_EMI_CSREMAP0_LOW   0x80700084
+#define HW_EMI_CSREMAP1_LOW   0x80700088
+
+#define HW_EMI_SMTMGR_SET0    0x80700094
+#define HW_EMI_SMTMGR_SET1    0x80700098
+#define HW_EMI_SMTMGR_SET2    0x8070009c
+
+#define HW_EMI_FLASH_TRPDR    0x807000a0
+#define HW_EMI_SMCTLR         0x807000a4
+#define HW_EMI_EXN_MODE_REG   0x807000ac
+
+////////////////////////////////////////////////////////////////////////////////
+// IOCON
+#define HW_IOCON_PIO_BASE     0x80044000
+#define HW_IOCON_SCKLOC       0x800442c0
+#define HW_IOCON(port,pin)    (HW_IOCON_PIO_BASE|(((port)<<5)|((pin)<<2)))
+
+////////////////////////////////////////////////////////////////////////////////
+// GPIO
+#define HW_GPIO_DATA_BASE     0x50000000
+
+#define HW_GPIO_DMA_CTRL      0x50000010
+#define HW_GPIO_DMA_DATA      0x50000020
+#define HW_GPIO_DMA_PADCTRL0  0x50000030
+#define HW_GPIO_DMA_PADCTRL1  0x50000040
+#define HW_GPIO_DMA_PADCTRL2  0x50000050
+#define HW_GPIO_DMA_PADCTRL3  0x50000060
+#define HW_GPIO_DMA_CTRL1     0x50000070
+#define HW_GPIO_DMA_CTRL2     0x50000080
+#define HW_GPIO_DMA_CTRL3     0x50000090
+#define HW_GPIO_DMA_CTRL4     0x500000a0
+
+#define HW_GPIO_DATA0         0x50000000
+#define HW_GPIO_DATA1         0x50010000
+#define HW_GPIO_DATA2         0x50020000
+#define HW_GPIO_DATA3         0x50030000
+#define HW_GPIO_DATA4         0x50040000
+
+#define HW_GPIO_DIR0          0x50008000
+#define HW_GPIO_DIR1          0x50018000
+#define HW_GPIO_DIR2          0x50028000
+#define HW_GPIO_DIR3          0x50038000
+#define HW_GPIO_DIR4          0x50048000
+
+#define HW_GPIO_IS0           0x50008010
+#define HW_GPIO_IS1           0x50018010
+#define HW_GPIO_IS2           0x50028010
+#define HW_GPIO_IS3           0x50038010
+#define HW_GPIO_IS4           0x50048010
+
+#define HW_GPIO_IBE0          0x50008020
+#define HW_GPIO_IBE1          0x50018020
+#define HW_GPIO_IBE2          0x50028020
+#define HW_GPIO_IBE3          0x50038020
+#define HW_GPIO_IBE4          0x50048020
+
+#define HW_GPIO_IEV0          0x50008030
+#define HW_GPIO_IEV1          0x50018030
+#define HW_GPIO_IEV2          0x50028030
+#define HW_GPIO_IEV3          0x50038030
+#define HW_GPIO_IEV4          0x50048030
+
+#define HW_GPIO_IE0           0x50008040
+#define HW_GPIO_IE1           0x50018040
+#define HW_GPIO_IE2           0x50028040
+#define HW_GPIO_IE3           0x50038040
+#define HW_GPIO_IE4           0x50048040
+
+#define HW_GPIO_RIS0          0x50008050
+#define HW_GPIO_RIS1          0x50018050
+#define HW_GPIO_RIS2          0x50028050
+#define HW_GPIO_RIS3          0x50038050
+#define HW_GPIO_RIS4          0x50048050
+
+#define HW_GPIO_MIS0          0x50008060
+#define HW_GPIO_MIS1          0x50018060
+#define HW_GPIO_MIS2          0x50028060
+#define HW_GPIO_MIS3          0x50038060
+#define HW_GPIO_MIS4          0x50048060
+
+#define HW_GPIO_IC0           0x50008070
+#define HW_GPIO_IC1           0x50018070
+#define HW_GPIO_IC2           0x50028070
+#define HW_GPIO_IC3           0x50038070
+#define HW_GPIO_IC4           0x50048070 
+
+#define HW_GPIO_DATAMASK0     0x50008080
+#define HW_GPIO_DATAMASK1     0x50018080
+#define HW_GPIO_DATAMASK2     0x50028080
+#define HW_GPIO_DATAMASK3     0x50038080
+#define HW_GPIO_DATAMASK4     0x50048080 
+
+////////////////////////////////////////////////////////////////////////////////
+// Quad-SPI0
+#define QSPI0_BASE_ADDRESS    0x80068000
+#define HW_QSPI0_CTRL0        0x80068000
+#define HW_QSPI0_CTRL1        0x80068010
+#define HW_QSPI0_CMD          0x80068020
+#define HW_QSPI0_TIMING       0x80068030
+#define HW_QSPI0_DATA         0x80068040
+#define HW_QSPI0_STATUS       0x80068050
+#define HW_QSPI0_DEBUG0       0x80068060
+#define HW_QSPI0_XFER         0x80068070
+
+/////////////////////////////////////////////////////////
+//DMA0
+#define HW_DMA0_SAR0           0x80100000
+#define HW_DMA0_DAR0           0x80100008
+#define HW_DMA0_LLP0           0x80100010
+#define HW_DMA0_CTL0           0x80100018
+#define HW_DMA0_SSTAT0         0x80100020
+#define HW_DMA0_DSTAT0         0x80100028
+#define HW_DMA0_SSTATAR0       0x80100030      
+#define HW_DMA0_DSTATAR0       0x80100038 
+#define HW_DMA0_CFG0           0x80100040
+#define HW_DMA0_SGR0           0x80100048
+#define HW_DMA0_DSR0           0x80100050
+
+#define HW_DMA0_SAR1           0x80100058
+#define HW_DMA0_DAR1           0x80100060
+#define HW_DMA0_LLP1           0x80100068
+#define HW_DMA0_CTL1           0x80100070
+#define HW_DMA0_SSTAT1         0x80100078
+#define HW_DMA0_DSTAT1         0x80100080
+#define HW_DMA0_SSTATAR1       0x80100088      
+#define HW_DMA0_DSTATAR1       0x80100090 
+#define HW_DMA0_CFG1           0x80100098
+#define HW_DMA0_SGR1           0x801000a0
+#define HW_DMA0_DSR1           0x801000a8
+
+#define HW_DMA0_SAR2           0x801000b0
+#define HW_DMA0_DAR2           0x801000b8
+#define HW_DMA0_LLP2           0x801000c0
+#define HW_DMA0_CTL2           0x801000c8
+#define HW_DMA0_SSTAT2         0x801000d0
+#define HW_DMA0_DSTAT2         0x801000d8
+#define HW_DMA0_SSTATAR2       0x801000e0      
+#define HW_DMA0_DSTATAR2       0x801000e8 
+#define HW_DMA0_CFG2           0x801000f0
+#define HW_DMA0_SGR2           0x801000f8
+#define HW_DMA0_DSR2           0x80100100
+
+#define HW_DMA0_SAR3           0x80100108
+#define HW_DMA0_DAR3           0x80100110
+#define HW_DMA0_LLP3           0x80100118
+#define HW_DMA0_CTL3           0x80100120
+#define HW_DMA0_SSTAT3         0x80100128
+#define HW_DMA0_DSTAT3         0x80100130
+#define HW_DMA0_SSTATAR3       0x80100138      
+#define HW_DMA0_DSTATAR3       0x80100140 
+#define HW_DMA0_CFG3           0x80100148
+#define HW_DMA0_SGR3           0x80100150
+#define HW_DMA0_DSR3           0x80100158
+
+#define HW_DMA0_SAR4           0x80100160
+#define HW_DMA0_DAR4           0x80100168
+#define HW_DMA0_LLP4           0x80100170
+#define HW_DMA0_CTL4           0x80100178
+#define HW_DMA0_SSTAT4         0x80100180
+#define HW_DMA0_DSTAT4         0x80100188
+#define HW_DMA0_SSTATAR4       0x80100190      
+#define HW_DMA0_DSTATAR4       0x80100198 
+#define HW_DMA0_CFG4           0x801001a0
+#define HW_DMA0_SGR4           0x801001a8
+#define HW_DMA0_DSR4           0x801001b0
+
+#define HW_DMA0_SAR5           0x801001b8
+#define HW_DMA0_DAR5           0x801001c0
+#define HW_DMA0_LLP5           0x801001c8
+#define HW_DMA0_CTL5           0x801001d0
+#define HW_DMA0_SSTAT5         0x801001d8
+#define HW_DMA0_DSTAT5         0x801001e0
+#define HW_DMA0_SSTATAR5       0x801001e8      
+#define HW_DMA0_DSTATAR5       0x801001f0 
+#define HW_DMA0_CFG5           0x801001f8
+#define HW_DMA0_SGR5           0x80100200
+#define HW_DMA0_DSR5           0x80100208
+
+#define HW_DMA0_SAR6           0x80100210
+#define HW_DMA0_DAR6           0x80100218
+#define HW_DMA0_LLP6           0x80100220
+#define HW_DMA0_CTL6           0x80100228
+#define HW_DMA0_SSTAT6         0x80100230
+#define HW_DMA0_DSTAT6         0x80100238
+#define HW_DMA0_SSTATAR6       0x80100240      
+#define HW_DMA0_DSTATAR6       0x80100248 
+#define HW_DMA0_CFG6           0x80100250
+#define HW_DMA0_SGR6           0x80100258
+#define HW_DMA0_DSR6           0x80100260
+
+#define HW_DMA0_SAR7           0x80100268
+#define HW_DMA0_DAR7           0x80100270
+#define HW_DMA0_LLP7           0x80100278
+#define HW_DMA0_CTL7           0x80100280
+#define HW_DMA0_SSTAT7         0x80100288
+#define HW_DMA0_DSTAT7         0x80100290
+#define HW_DMA0_SSTATAR7       0x80100298      
+#define HW_DMA0_DSTATAR7       0x801002a0 
+#define HW_DMA0_CFG7           0x801002a8
+#define HW_DMA0_SGR7           0x801002b0
+#define HW_DMA0_DSR7           0x801002b8
+
+#define HW_DMA0_RawTFR         0x801002c0
+#define HW_DMA0_RawBLOCK       0x801002c8
+#define HW_DMA0_RawSRCTRAN     0x801002d0
+#define HW_DMA0_RawDSTTRAN     0x801002d8
+#define HW_DMA0_RawERR         0x801002e0
+
+#define HW_DMA0_StatusTFR      0x801002e8
+#define HW_DMA0_StatusBLOCK    0x801002f0
+#define HW_DMA0_StatusSRCTRAN  0x801002f8
+#define HW_DMA0_StatusDSTTRAN  0x80100300
+#define HW_DMA0_StatusERR      0x80100308
+
+#define HW_DMA0_MaskTFR        0x80100310
+#define HW_DMA0_MaskBLOCK      0x80100318
+#define HW_DMA0_MaskSRCTRAN    0x80100320
+#define HW_DMA0_MaskDSTTRAN    0x80100328
+#define HW_DMA0_MaskERR        0x80100330
+
+#define HW_DMA0_ClearTFR       0x80100338
+#define HW_DMA0_ClearBLOCK     0x80100340
+#define HW_DMA0_ClearSRCTRAN   0x80100348
+#define HW_DMA0_ClearDSTTRAN   0x80100350
+#define HW_DMA0_ClearERR       0x80100358
+
+#define HW_DMA0_STATUSINT      0x80100360
+
+#define HW_DMA0_ReqSrcReg      0x80100368
+#define HW_DMA0_ReqDstReg      0x80100370
+#define HW_DMA0_SglReqSrcReg   0x80100378
+#define HW_DMA0_SglReqDstReg   0x80100380
+#define HW_DMA0_LstSrcReg      0x80100388
+#define HW_DMA0_LstDstReg      0x80100390
+
+#define HW_DMA0_DMACFGREG      0x80100398
+#define HW_DMA0_CHENREG        0x801003a0
+
+////////////////////////////////////////////////////////////////////////////////
+// DMA1
+#define HW_DMA1_SAR0          0x80200000
+#define HW_DMA1_DAR0          0x80200008
+#define HW_DMA1_LLP0          0x80200010
+#define HW_DMA1_CTL0          0x80200018
+#define HW_DMA1_SSTAT0        0x80200020
+#define HW_DMA1_DSTAT0        0x80200028
+#define HW_DMA1_SSTATAR0      0x80200030
+#define HW_DMA1_DSTATAR0      0x80200038
+#define HW_DMA1_CFG0          0x80200040
+#define HW_DMA1_SGR0          0x80200048
+#define HW_DMA1_DSR0          0x80200050
+
+#define HW_DMA1_SAR1          0x80200058
+#define HW_DMA1_DAR1          0x80200060
+#define HW_DMA1_LLP1          0x80200068
+#define HW_DMA1_CTL1          0x80200070
+#define HW_DMA1_SSTAT1        0x80200078
+#define HW_DMA1_DSTAT1        0x80200080
+#define HW_DMA1_SSTATAR1      0x80200088
+#define HW_DMA1_DSTATAR1      0x80200090
+#define HW_DMA1_CFG1          0x80200098
+#define HW_DMA1_SGR1          0x802000a0
+#define HW_DMA1_DSR1          0x802000a8
+
+#define HW_DMA1_SAR2          0x802000b0
+#define HW_DMA1_DAR2          0x802000b8
+#define HW_DMA1_LLP2          0x802000c0
+#define HW_DMA1_CTL2          0x802000c8
+#define HW_DMA1_SSTAT2        0x802000d0
+#define HW_DMA1_DSTAT2        0x802000d8
+#define HW_DMA1_SSTATAR2      0x802000e0
+#define HW_DMA1_DSTATAR2      0x802000e8
+#define HW_DMA1_CFG2          0x802000f0
+#define HW_DMA1_SGR2          0x802000f8
+#define HW_DMA1_DSR2          0x80200100
+
+#define HW_DMA1_SAR3          0x80200108
+#define HW_DMA1_DAR3          0x80200110
+#define HW_DMA1_LLP3          0x80200118
+#define HW_DMA1_CTL3          0x80200120
+#define HW_DMA1_SSTAT3        0x80200128
+#define HW_DMA1_DSTAT3        0x80200130
+#define HW_DMA1_SSTATAR3      0x80200138
+#define HW_DMA1_DSTATAR3      0x80200140
+#define HW_DMA1_CFG3          0x80200148
+#define HW_DMA1_SGR3          0x80200150
+#define HW_DMA1_DSR3          0x80200158
+
+#define HW_DMA1_SAR4          0x80200160
+#define HW_DMA1_DAR4          0x80200168
+#define HW_DMA1_LLP4          0x80200170
+#define HW_DMA1_CTL4          0x80200178
+#define HW_DMA1_SSTAT4        0x80200180
+#define HW_DMA1_DSTAT4        0x80200188
+#define HW_DMA1_SSTATAR4      0x80200190
+#define HW_DMA1_DSTATAR4      0x80200198
+#define HW_DMA1_CFG4          0x802001a0
+#define HW_DMA1_SGR4          0x802001a8
+#define HW_DMA1_DSR4          0x802001b0
+
+#define HW_DMA1_SAR5          0x802001b8
+#define HW_DMA1_DAR5          0x802001c0
+#define HW_DMA1_LLP5          0x802001c8
+#define HW_DMA1_CTL5          0x802001d0
+#define HW_DMA1_SSTAT5        0x802001d8
+#define HW_DMA1_DSTAT5        0x802001e0
+#define HW_DMA1_SSTATAR5      0x802001e8
+#define HW_DMA1_DSTATAR5      0x802001f0
+#define HW_DMA1_CFG5          0x802001f8
+#define HW_DMA1_SGR5          0x80200200
+#define HW_DMA1_DSR5          0x80200208
+
+#define HW_DMA1_SAR6          0x80200210
+#define HW_DMA1_DAR6          0x80200218
+#define HW_DMA1_LLP6          0x80200220
+#define HW_DMA1_CTL6          0x80200228
+#define HW_DMA1_SSTAT6        0x80200230
+#define HW_DMA1_DSTAT6        0x80200238
+#define HW_DMA1_SSTATAR6      0x80200240
+#define HW_DMA1_DSTATAR6      0x80200248
+#define HW_DMA1_CFG6          0x80200250
+#define HW_DMA1_SGR6          0x80200258
+#define HW_DMA1_DSR6          0x80200260
+
+#define HW_DMA1_SAR7          0x80200268
+#define HW_DMA1_DAR7          0x80200270
+#define HW_DMA1_LLP7          0x80200278
+#define HW_DMA1_CTL7          0x80200280
+#define HW_DMA1_SSTAT7        0x80200288
+#define HW_DMA1_DSTAT7        0x80200290
+#define HW_DMA1_SSTATAR7      0x80200298
+#define HW_DMA1_DSTATAR7      0x802002a0
+#define HW_DMA1_CFG7          0x802002a8
+#define HW_DMA1_SGR7          0x802002b0
+#define HW_DMA1_DSR7          0x802002b8
+
+#define HW_DMA1_RawTFR        0x802002c0
+#define HW_DMA1_RawBLOCK      0x802002c8
+#define HW_DMA1_RawSRCTRAN    0x802002d0
+#define HW_DMA1_RawDSTTRAN    0x802002d8
+#define HW_DMA1_RawERR        0x802002e0
+
+#define HW_DMA1_StatusTFR     0x802002e8
+#define HW_DMA1_StatusBLOCK   0x802002f0
+#define HW_DMA1_StatusSRCTRAN 0x802002f8
+#define HW_DMA1_StatusDSTTRAN 0x80200300
+#define HW_DMA1_StatusERR     0x80200308
+
+#define HW_DMA1_MaskTFR       0x80200310
+#define HW_DMA1_MaskBLOCK     0x80200318
+#define HW_DMA1_MaskSRCTRAN   0x80200320
+#define HW_DMA1_MaskDSTTRAN   0x80200328
+#define HW_DMA1_MaskERR       0x80200330
+
+#define HW_DMA1_ClearTFR      0x80200338
+#define HW_DMA1_ClearBLOCK    0x80200340
+#define HW_DMA1_ClearSRCTRAN  0x80200348
+#define HW_DMA1_ClearDSTTRAN  0x80200350
+#define HW_DMA1_ClearERR      0x80200358
+
+#define HW_DMA1_STATUSINT     0x80200360
+
+#define HW_DMA1_ReqSrcReg     0x80200368
+#define HW_DMA1_ReqDstReg     0x80200370
+#define HW_DMA1_SglReqSrcReg  0x80200378
+#define HW_DMA1_SglReqDstReg  0x80200380
+#define HW_DMA1_LstSrcReg     0x80200388
+#define HW_DMA1_LstDstReg     0x80200390
+
+#define HW_DMA1_DMACFGREG     0x80200398
+#define HW_DMA1_CHENREG       0x802003a0
+
+////////////////////////////////////////////////////////////////////////////////
+// ICOLL
+#define HW_ICOLL_VECTOR       0x80054000
+#define HW_ICOLL_LEVELACK     0x80054010
+#define HW_ICOLL_CTRL         0x80054020
+#define HW_ICOLL_STAT         0x80054030
+#define HW_ICOLL_RAW0         0x80054040
+#define HW_ICOLL_RAW1         0x80054050
+#define HW_ICOLL_PRIORITY0    0x80054060
+#define HW_ICOLL_PRIORITY1    0x80054070
+#define HW_ICOLL_PRIORITY2    0x80054080
+#define HW_ICOLL_PRIORITY3    0x80054090
+#define HW_ICOLL_PRIORITY4    0x800540A0
+#define HW_ICOLL_PRIORITY5    0x800540B0
+#define HW_ICOLL_PRIORITY6    0x800540C0
+#define HW_ICOLL_PRIORITY7    0x800540D0
+#define HW_ICOLL_PRIORITY8    0x800540E0
+#define HW_ICOLL_PRIORITY9    0x800540F0
+#define HW_ICOLL_PRIORITY10   0x80054100
+#define HW_ICOLL_PRIORITY11   0x80054110
+#define HW_ICOLL_PRIORITY12   0x80054120
+#define HW_ICOLL_PRIORITY13   0x80054130
+#define HW_ICOLL_PRIORITY14   0x80054140
+#define HW_ICOLL_PRIORITY15   0x80054150
+#define HW_ICOLL_VBASE        0x80054160
+#define HW_ICOLL_DEBUG        0x80054170
+#define HW_ICOLL_DBGREAD0     0x80054180
+#define HW_ICOLL_DBGREAD1     0x80054190
+#define HW_ICOLL_DBGFLAG      0x800541A0
+#define HW_ICOLL_DBGREQUEST0  0x800541B0
+#define HW_ICOLL_DBGREQUEST1  0x800541C0
+#define HW_ICOLL_CLEAR0       0x800541D0
+#define HW_ICOLL_CLEAR1       0x800541E0
+#define HW_ICOLL_UNDEF_VECTOR 0x800541F0
+
+////////////////////////////////////////////////////////////////////////////////
+// TIMER0
+#define HW_TIMER0_IR          0x80088000
+#define HW_TIMER0_TCR         0x80088010
+#define HW_TIMER0_DIR         0x80088020
+#define HW_TIMER0_TC0         0x80088030
+#define HW_TIMER0_TC1         0x80088040
+#define HW_TIMER0_TC2         0x80088050
+#define HW_TIMER0_TC3         0x80088060
+#define HW_TIMER0_PR          0x80088070
+#define HW_TIMER0_PC          0x80088080
+#define HW_TIMER0_MCR         0x80088090
+#define HW_TIMER0_MR0         0x800880a0
+#define HW_TIMER0_MR1         0x800880b0
+#define HW_TIMER0_MR2         0x800880C0
+#define HW_TIMER0_MR3         0x800880D0
+#define HW_TIMER0_CCR         0x800880E0
+#define HW_TIMER0_CR0         0x800880F0
+#define HW_TIMER0_CR1         0x80088100
+#define HW_TIMER0_CR2         0x80088110
+#define HW_TIMER0_CR3         0x80088120
+#define HW_TIMER0_EMR         0x80088130
+#define HW_TIMER0_PWMTH0      0x80088140
+#define HW_TIMER0_PWMTH1      0x80088150
+#define HW_TIMER0_PWMTH2      0x80088160
+#define HW_TIMER0_PWMTH3      0x80088170
+#define HW_TIMER0_CTCR        0x80088180
+#define HW_TIMER0_PWMC        0x80088190
+
+////////////////////////////////////////////////////////////////////////////////
+// USART
+
+typedef struct {
+  __IO unsigned long CTRL0[4];
+  __IO unsigned long CTRL1[4];
+  __IO unsigned long CTRL2[4];
+  __IO unsigned long LINECTRL[4];
+  __IO unsigned long INTR[4];
+  __IO unsigned long DATA[4];
+  __IO unsigned long STAT[4];
+  __I  unsigned long DEBUG[4];
+  __IO unsigned long ILPR[4];
+  __IO unsigned long RS485CTRL[4];
+  __IO unsigned long RS485ADRMATCH[4];
+  __IO unsigned long RS485DLY[4];
+  __IO unsigned long AUTOBAUD[4];
+  __IO unsigned long CTRL3[4];
+} ASM_USART_TypeDef;
+
+#define UART0_BASE            0x80000000
+#define UART1_BASE            0x80004000
+#define UART2_BASE            0x80008000
+#define UART3_BASE            0x8000C000
+#define UART4_BASE            0x80010000
+#define UART5_BASE            0x80014000
+#define UART6_BASE            0x80018000
+#define UART7_BASE            0x8001C000
+#define UART8_BASE            0x80020000
+#define UART9_BASE            0x80024000
+
+////////////////////////////////////////////////////////////////////////////////
+// MAC
+#define HW_ETH_BASE_ADDR      0x80500000
+#define HW_ETH_MACCR          (HW_ETH_BASE_ADDR + 0x0000)
+#define HW_ETH_MACFFR         (HW_ETH_BASE_ADDR + 0x0004)
+#define HW_ETH_MACHTHR        (HW_ETH_BASE_ADDR + 0x0008)
+#define HW_ETH_MACHTLR        (HW_ETH_BASE_ADDR + 0x000C)
+#define HW_ETH_MACMIIAR       (HW_ETH_BASE_ADDR + 0x0010)
+#define HW_ETH_MACMIIDR       (HW_ETH_BASE_ADDR + 0x0014)
+#define HW_ETH_MACFCR         (HW_ETH_BASE_ADDR + 0x0018)
+#define HW_ETH_MACVLANTR      (HW_ETH_BASE_ADDR + 0x001C)
+#define HW_ETH_MACVR          (HW_ETH_BASE_ADDR + 0x0020)
+#define HW_ETH_MACRWUFFR      (HW_ETH_BASE_ADDR + 0x0028)
+#define HW_ETH_MACPMTCSR      (HW_ETH_BASE_ADDR + 0x002C)
+#define HW_ETH_MACDBGR        (HW_ETH_BASE_ADDR + 0x0034)
+#define HW_ETH_MACISR         (HW_ETH_BASE_ADDR + 0x0038)
+#define HW_ETH_MACIMR         (HW_ETH_BASE_ADDR + 0x003C)
+#define HW_ETH_MACA0HR        (HW_ETH_BASE_ADDR + 0x0040)
+#define HW_ETH_MACA0LR        (HW_ETH_BASE_ADDR + 0x0044)
+#define HW_ETH_MACA1HR        (HW_ETH_BASE_ADDR + 0x0048)
+#define HW_ETH_MACA1LR        (HW_ETH_BASE_ADDR + 0x004C)
+#define HW_ETH_MACA2HR        (HW_ETH_BASE_ADDR + 0x0050)
+#define HW_ETH_MACA2LR        (HW_ETH_BASE_ADDR + 0x0054)
+#define HW_ETH_MACA3HR        (HW_ETH_BASE_ADDR + 0x0058)
+#define HW_ETH_MACA3LR        (HW_ETH_BASE_ADDR + 0x005C)
+#define HW_ETH_MACA4HR        (HW_ETH_BASE_ADDR + 0x0060)
+#define HW_ETH_MACA4LR        (HW_ETH_BASE_ADDR + 0x0064)
+#define HW_ETH_MMCCR          (HW_ETH_BASE_ADDR + 0x0100)
+#define HW_ETH_MMCRIR         (HW_ETH_BASE_ADDR + 0x0104)
+#define HW_ETH_MMCTIR         (HW_ETH_BASE_ADDR + 0x0108)
+#define HW_ETH_MMCRIMR        (HW_ETH_BASE_ADDR + 0x010C)
+#define HW_ETH_MMCTIMR        (HW_ETH_BASE_ADDR + 0x0110)
+#define HW_ETH_MMCTGFSCCR     (HW_ETH_BASE_ADDR + 0x014C)
+#define HW_ETH_MMCTGFMSCCR    (HW_ETH_BASE_ADDR + 0x0150)
+#define HW_ETH_MMCTGFCR       (HW_ETH_BASE_ADDR + 0x0168)
+#define HW_ETH_MMCRFCECR      (HW_ETH_BASE_ADDR + 0x0194)
+#define HW_ETH_MMCRFAECR      (HW_ETH_BASE_ADDR + 0x0198)
+#define HW_ETH_MMCRGUFCR      (HW_ETH_BASE_ADDR + 0x01C4)
+#define HW_ETH_PTPTSCR        (HW_ETH_BASE_ADDR + 0x0700)
+#define HW_ETH_PTPSSIR        (HW_ETH_BASE_ADDR + 0x0704)
+#define HW_ETH_PTPTSHR        (HW_ETH_BASE_ADDR + 0x0708)
+#define HW_ETH_PTPTSLR        (HW_ETH_BASE_ADDR + 0x070C)
+#define HW_ETH_PTPTSHUR       (HW_ETH_BASE_ADDR + 0x0710)
+#define HW_ETH_PTPTSLUR       (HW_ETH_BASE_ADDR + 0x0714)
+#define HW_ETH_PTPTSAR        (HW_ETH_BASE_ADDR + 0x0718)
+#define HW_ETH_PTPTTHR        (HW_ETH_BASE_ADDR + 0x071C)
+#define HW_ETH_PTPTTLR        (HW_ETH_BASE_ADDR + 0x0720)
+#define HW_ETH_PTPTSSR        (HW_ETH_BASE_ADDR + 0x0728)
+#define HW_ETH_PTPPPSCR       (HW_ETH_BASE_ADDR + 0x072C)
+#define HW_ETH_DMABMR         (HW_ETH_BASE_ADDR + 0x1000)
+#define HW_ETH_DMATPDR        (HW_ETH_BASE_ADDR + 0x1004)
+#define HW_ETH_DMARPDR        (HW_ETH_BASE_ADDR + 0x1008)
+#define HW_ETH_DMARDLAR       (HW_ETH_BASE_ADDR + 0x100C)
+#define HW_ETH_DMATDLAR       (HW_ETH_BASE_ADDR + 0x1010)
+#define HW_ETH_DMASR          (HW_ETH_BASE_ADDR + 0x1014)
+#define HW_ETH_DMAOMR         (HW_ETH_BASE_ADDR + 0x1018)
+#define HW_ETH_DMAIER         (HW_ETH_BASE_ADDR + 0x101C)
+#define HW_ETH_DMAMFBOCR      (HW_ETH_BASE_ADDR + 0x1020)
+#define HW_ETH_DMARSWTR       (HW_ETH_BASE_ADDR + 0x1024)
+#define HW_ETH_DMACHTDR       (HW_ETH_BASE_ADDR + 0x1048)
+#define HW_ETH_DMACHRDR       (HW_ETH_BASE_ADDR + 0x104C)
+#define HW_ETH_DMACHTBAR      (HW_ETH_BASE_ADDR + 0x1050)
+#define HW_ETH_DMACHRBAR      (HW_ETH_BASE_ADDR + 0x1054)
+
+////////////////////////////////////////////////////////////////////////////////
+#endif /* __ASM9260T_REGS_H__ */
+
diff --git a/bsp/asm9260t/platform/gpio.c b/bsp/asm9260t/platform/gpio.c
new file mode 100644
index 0000000000..26407f835a
--- /dev/null
+++ b/bsp/asm9260t/platform/gpio.c
@@ -0,0 +1,62 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+ 
+#include "ASM9260T.h"
+#include "rtthread.h"
+
+void HW_SetPinMux(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t mux_type)
+{
+    rt_uint32_t addr = HW_IOCON(port, pin);
+    rt_uint32_t val = inl(addr);   // read origin value
+
+    val &= ~7UL;     // clear MUX field
+    val |= mux_type; // set MUX field with new value
+
+    outl(val ,addr);   // Set new value
+}
+
+void HW_GpioSetDir(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t isOut)
+{
+    rt_uint32_t addr = HW_GPIO_DATA_BASE | ((port>>2)<<16) | 0x8000;
+    rt_uint32_t val;
+    addr = isOut? REG_SET(addr) : REG_CLR(addr);
+    val = (1 << ((port%4)*8+pin));
+    outl(val, addr);
+}
+
+void HW_GpioSetVal(rt_uint8_t port, rt_uint8_t pin)
+{
+    rt_uint32_t addr, val;
+    addr = REG_SET(HW_GPIO_DATA_BASE | ((port>>2)<<16));
+    val  = (1 << ((port%4)*8+pin));
+    outl(val, addr);
+}
+
+void HW_GpioClrVal(rt_uint8_t port, rt_uint8_t pin)
+{
+    rt_uint32_t addr, val;
+    addr = REG_CLR(HW_GPIO_DATA_BASE | ((port>>2)<<16));
+    val  = (1 << ((port%4)*8+pin));
+    outl(val, addr);
+}
diff --git a/bsp/asm9260t/platform/gpio.h b/bsp/asm9260t/platform/gpio.h
new file mode 100644
index 0000000000..26fccff477
--- /dev/null
+++ b/bsp/asm9260t/platform/gpio.h
@@ -0,0 +1,31 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+extern void HW_SetPinMux(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t mux_type);
+extern void HW_GpioSetDir(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t isOut);
+extern void HW_GpioSetVal(rt_uint8_t port, rt_uint8_t pin);
+extern void HW_GpioClrVal(rt_uint8_t port, rt_uint8_t pin);
+#endif
diff --git a/bsp/asm9260t/platform/interrupt.c b/bsp/asm9260t/platform/interrupt.c
new file mode 100644
index 0000000000..20b8b62e00
--- /dev/null
+++ b/bsp/asm9260t/platform/interrupt.c
@@ -0,0 +1,221 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      first version
+ * 2015-04-27     ArdaFu     Port bsp from at91sam9260 to asm9260t
+ */
+
+#include <rthw.h>
+#include "asm9260t.h"
+#include "interrupt.h"
+
+#define MAX_HANDLERS    (64)
+
+extern rt_uint32_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 3 = highest).
+ */
+static rt_uint32_t default_irq_priority[MAX_HANDLERS/4] =
+{
+    0x00000000UL, /* INT3 - INT0 */
+    0x00000000UL, /* INT7 - INT4 */
+    0x00000000UL, /* INT11 - INT8 */
+    0x02000000UL, /* INT15 - INT12 */
+    0x02020202UL, /* INT19 - INT16 */
+    0x02020202UL, /* INT23 - INT20 */
+    0x00000002UL, /* INT27 - INT24 */
+    0x01010100UL, /* INT31 - INT28 */
+    0x00000001UL, /* INT35 - INT32 */
+    0x00000000UL, /* INT39 - INT36 */
+    0x00000000UL, /* INT43 - INT40 */
+    0x00000000UL, /* INT47 - INT44 */
+    0x00000000UL, /* INT51 - INT48 */
+    0x00000000UL, /* INT55 - INT52 */
+    0x00000000UL, /* INT59 - INT56 */
+    0x00000000UL, /* INT63 - INT60 */
+};
+
+
+void rt_hw_interrupt_mask(int irq);
+void rt_hw_interrupt_umask(int irq);
+
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
+{
+    rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
+    return RT_NULL;
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    register rt_uint32_t idx;
+    /* Initialize the ICOLL interrupt controller */
+    outl((1<<8), REG_SET(HW_AHBCLKCTRL1)); // Enable ICOLL clock
+    outl((1<<8), REG_CLR(HW_PRESETCTRL1)); // Reset ICOLL start
+    outl((1<<8), REG_SET(HW_PRESETCTRL1)); // Reset ICOLL stop
+
+    for(idx = 0; idx < (MAX_HANDLERS/4); idx++)
+    {
+        rt_uint32_t reg = (HW_ICOLL_PRIORITY0 + 0x10*idx);
+        outl(default_irq_priority[idx], REG_VAL(reg));
+    }
+
+    /* init exceptions table */
+    for(idx=0; idx < MAX_HANDLERS; idx++)
+    {
+        irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+        irq_desc[idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
+#endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+
+    outl(0x00000000, REG_CLR(HW_ICOLL_VBASE)); //todo: fix this bug
+
+    outl(0x00020000, REG_CLR(HW_ICOLL_CTRL)); // Clear CTRL REG
+    outl(0x00050000, REG_SET(HW_ICOLL_CTRL));
+    outl(0x00000004, HW_ICOLL_UNDEF_VECTOR);
+    outl(~0UL, REG_CLR(HW_ICOLL_CLEAR0));
+    outl(~0UL, REG_CLR(HW_ICOLL_CLEAR1));
+}
+
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int irq)
+{
+    rt_uint32_t reg = HW_ICOLL_PRIORITY0 + ((irq & 0x3CUL) << 2);
+    rt_uint32_t bit = 4UL << ((irq & 3UL)<<3);
+    outl(bit, REG_CLR(reg));
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int irq)
+{
+    rt_uint32_t reg = HW_ICOLL_PRIORITY0 + ((irq & 0x3CUL) << 2);
+    rt_uint32_t bit = 4UL << ((irq & 3UL)<<3);
+    outl(bit, REG_SET(reg));
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param handler the interrupt service routine to be installed
+ * @param param the interrupt service function parameter
+ * @param name the interrupt name
+ * @return old handler
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+            irq_desc[vector].counter = 0;
+#endif
+        }
+    }
+
+    return old_handler;
+}
+
+
+
+rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
+{
+    //volatile rt_uint32_t irqstat;
+    rt_uint32_t id;
+    /* AIC need this dummy read */
+    inl(HW_ICOLL_VECTOR);
+    /* get irq number */
+    id = inl(HW_ICOLL_STAT);
+    /* clear pending register */
+    //irqstat = inl(HW_ICOLL_VECTOR);
+    return id;
+}
+
+void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
+{
+    rt_uint32_t reg = HW_ICOLL_PRIORITY0 + ((id & 0x3CUL) << 2);
+    rt_uint32_t level = 1UL << (0x3 & (inl(REG_VAL(reg)) >>((id & 3UL)<<3)));
+
+    if(id & 0x20)
+        outl((1UL<<(id&0x1F)), REG_SET(HW_ICOLL_CLEAR1));
+    else
+        outl((1UL<<id), REG_SET(HW_ICOLL_CLEAR0));
+
+    outl(level, HW_ICOLL_LEVELACK);
+}
+
+#ifdef RT_USING_FINSH
+void list_irq(void)
+{
+    int irq;
+    rt_kprintf("number\tcount\tname\n");
+    for (irq = 0; irq < MAX_HANDLERS; irq++)
+    {
+        if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+        {
+            rt_kprintf("%02ld: %10ld  %s\n",
+                       irq, irq_desc[irq].counter, irq_desc[irq].name);
+        }
+    }
+}
+
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT(list_irq, list system irq);
+
+#endif
diff --git a/bsp/asm9260t/platform/interrupt.h b/bsp/asm9260t/platform/interrupt.h
new file mode 100644
index 0000000000..85aa48f371
--- /dev/null
+++ b/bsp/asm9260t/platform/interrupt.h
@@ -0,0 +1,97 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+
+// IRQ Source
+#define INT_ARM_COMMRX                    0 
+#define INT_ARM_COMMTX                    1 
+#define INT_RTC                           2 
+#define INT_GPIO0                         3 
+#define INT_GPIO1                         4 
+#define INT_GPIO2                         5 
+#define INT_GPIO3                         6 
+#define INT_GPIO4_IIS1                    7 
+#define INT_USB0                          8 
+#define INT_USB1                          9 
+#define INT_USB0_DMA                      10  
+#define INT_USB1_DMA                      11  
+#define INT_MAC                           12  
+#define INT_MAC_PMT                       13  
+#define INT_NAND                          14  
+#define INT_UART0                         15  
+#define INT_UART1                         16  
+#define INT_UART2                         17  
+#define INT_UART3                         18  
+#define INT_UART4                         19  
+#define INT_UART5                         20  
+#define INT_UART6                         21  
+#define INT_UART7                         22  
+#define INT_UART8                         23  
+#define INT_UART9                         24  
+#define INT_I2S0                          25  
+#define INT_I2C0                          26  
+#define INT_I2C1                          27  
+#define INT_CAMIF                         28  
+#define INT_TIMER0                        29  
+#define INT_TIMER1                        30  
+#define INT_TIMER2                        31  
+#define INT_TIMER3                        32  
+#define INT_ADC0                          33  
+#define INT_DAC0                          34  
+#define INT_USB0_RESUME_HOSTDISCONNECT    35    
+#define INT_USB0_VBUSVALID                36    
+#define INT_USB1_RESUME_HOSTDISCONNECT    37    
+#define INT_USB1_VBUSVALID                38    
+#define INT_DMA0_CH0                      39  
+#define INT_DMA0_CH1                      40  
+#define INT_DMA0_CH2                      41  
+#define INT_DMA0_CH3                      42  
+#define INT_DMA0_CH4                      43  
+#define INT_DMA0_CH5                      44  
+#define INT_DMA0_CH6                      45  
+#define INT_DMA0_CH7                      46  
+#define INT_DMA1_CH0                      47  
+#define INT_DMA1_CH1                      48  
+#define INT_DMA1_CH2                      49  
+#define INT_DMA1_CH3                      50  
+#define INT_DMA1_CH4                      51  
+#define INT_DMA1_CH5                      52  
+#define INT_DMA1_CH6                      53  
+#define INT_DMA1_CH7                      54  
+#define INT_WATCHDOG                      55  
+#define INT_CAN0                          56  
+#define INT_CAN1                          57  
+#define INT_QEI                           58  
+#define INT_MCPWM                         59  
+#define INT_SPI0                          60  
+#define INT_SPI1                          61  
+#define INT_QUADSPI0                      62  
+#define INT_SSP0                          63
+
+#endif
diff --git a/bsp/asm9260t/platform/reset.c b/bsp/asm9260t/platform/reset.c
new file mode 100644
index 0000000000..2f5adc6231
--- /dev/null
+++ b/bsp/asm9260t/platform/reset.c
@@ -0,0 +1,37 @@
+/*
+ * File      : reset.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      modified from mini2440
+ * 2015-04-27     ArdaFu      Port bsp from at91sam9260 to asm9260t
+ */
+
+#include <rtthread.h>
+
+void machine_reset(void)
+{
+
+}
+
+void machine_shutdown(void)
+{
+
+}
+
diff --git a/bsp/asm9260t/platform/rt_low_level_gcc.inc b/bsp/asm9260t/platform/rt_low_level_gcc.inc
new file mode 100644
index 0000000000..c6edd3787c
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_gcc.inc
@@ -0,0 +1,31 @@
+/*
+ * File      : rt_low_level_gcc.inc
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+
+/*--------- Stack size of CPU modes ------------------------------------------*/
+.equ UND_STK_SIZE,    2048
+.equ SVC_STK_SIZE,    4096
+.equ ABT_STK_SIZE,    2048
+.equ IRQ_STK_SIZE,    4096
+.equ FIQ_STK_SIZE,    4096
+.equ SYS_STK_SIZE,    2048
diff --git a/bsp/asm9260t/platform/rt_low_level_iar.inc b/bsp/asm9260t/platform/rt_low_level_iar.inc
new file mode 100644
index 0000000000..3046253d07
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_iar.inc
@@ -0,0 +1,31 @@
+/*
+ * File      : rt_low_level_iar.inc
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+ 
+/*-------- Stack size of CPU modes -------------------------------------------*/
+#define UND_STK_SIZE 512
+#define SVC_STK_SIZE 4096
+#define ABT_STK_SIZE 512
+#define IRQ_STK_SIZE 1024
+#define FIQ_STK_SIZE 1024
+#define SYS_STK_SIZE 512
diff --git a/bsp/asm9260t/platform/rt_low_level_init.c b/bsp/asm9260t/platform/rt_low_level_init.c
new file mode 100644
index 0000000000..926c1af6fa
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_init.c
@@ -0,0 +1,30 @@
+/*
+ * File      : rt_low_level_init.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ * 2015-04-27     ArdaFu      Port bsp from at91sam9260 to asm9260t
+ */
+
+void rt_low_level_init(void)
+{
+
+}
+
diff --git a/bsp/asm9260t/platform/rt_low_level_keil.inc b/bsp/asm9260t/platform/rt_low_level_keil.inc
new file mode 100644
index 0000000000..c3cde15ded
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_keil.inc
@@ -0,0 +1,32 @@
+;/*
+; * File      : rt_low_level_keil.inc
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+; *
+; *  This program is free software; you can redistribute it and/or modify
+; *  it under the terms of the GNU General Public License as published by
+; *  the Free Software Foundation; either version 2 of the License, or
+; *  (at your option) any later version.
+; *
+; *  This program is distributed in the hope that it will be useful,
+; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; *  GNU General Public License for more details.
+; *
+; *  You should have received a copy of the GNU General Public License along
+; *  with this program; if not, write to the Free Software Foundation, Inc.,
+; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2015-04-14     ArdaFu      first version
+; */
+
+;/*-------- Stack size of CPU modes ------------------------------------------*/
+UND_STK_SIZE EQU 512
+SVC_STK_SIZE EQU 4096
+ABT_STK_SIZE EQU 512
+IRQ_STK_SIZE EQU 1024
+FIQ_STK_SIZE EQU 1024
+SYS_STK_SIZE EQU 512
+    END
diff --git a/bsp/asm9260t/platform/system_clock.c b/bsp/asm9260t/platform/system_clock.c
new file mode 100644
index 0000000000..e51cf7c892
--- /dev/null
+++ b/bsp/asm9260t/platform/system_clock.c
@@ -0,0 +1,303 @@
+/*
+ * File      : clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety       first version
+ */
+
+#include <rtthread.h>
+
+/*
+static rt_list_t clocks;
+
+struct clk {
+	char name[32];
+	rt_uint32_t rate_hz;
+	struct clk *parent;
+	rt_list_t  node;
+};
+
+static struct clk clk32k = {
+	"clk32k",
+	AT91_SLOW_CLOCK,
+	RT_NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk main_clk = {
+	"main",
+	0,
+	RT_NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk plla = {
+	"plla",
+	0,
+	RT_NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk mck = {
+	"mck",
+	0,
+	RT_NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk uhpck = {
+	"uhpck",
+	0,
+	RT_NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk pllb = {
+	"pllb",
+	0,
+	&main_clk,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk udpck = {
+	"udpck",
+	0,
+	&pllb,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk *const standard_pmc_clocks[] = {
+	// four primary clocks 
+	&clk32k,
+	&main_clk,
+	&plla,
+
+	// MCK 
+	&mck
+};
+
+// clocks cannot be de-registered no refcounting necessary
+struct clk *clk_get(const char *id)
+{
+	struct clk *clk;
+	rt_list_t *list;
+	
+	for (list = (&clocks)->next; list != &clocks; list = list->next)
+	{
+		clk = (struct clk *)rt_list_entry(list, struct clk, node);
+		if (rt_strcmp(id, clk->name) == 0)
+			return clk;
+	}
+
+	return RT_NULL;
+}
+
+rt_uint32_t clk_get_rate(struct clk *clk)
+{
+	rt_uint32_t	rate;
+
+	for (;;) {
+		rate = clk->rate_hz;
+		if (rate || !clk->parent)
+			break;
+		clk = clk->parent;
+	}
+	return rate;
+}
+
+static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
+{
+	unsigned mul, div;
+
+	div = reg & 0xff;
+	mul = (reg >> 16) & 0x7ff;
+	if (div && mul) {
+		freq /= div;
+		freq *= mul + 1;
+	} else
+		freq = 0;
+
+	return freq;
+}
+
+static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
+{
+	unsigned i, div = 0, mul = 0, diff = 1 << 30;
+	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+	//PLL output max 240 MHz (or 180 MHz per errata)
+	if (out_freq > 240000000)
+		goto fail;
+
+	for (i = 1; i < 256; i++) {
+		int diff1;
+		unsigned input, mul1;
+
+		//
+		// PLL input between 1MHz and 32MHz per spec, but lower
+		// frequences seem necessary in some cases so allow 100K.
+		// Warning: some newer products need 2MHz min.
+		//
+		input = main_freq / i;
+		if (input < 100000)
+			continue;
+		if (input > 32000000)
+			continue;
+
+		mul1 = out_freq / input;
+		if (mul1 > 2048)
+			continue;
+		if (mul1 < 2)
+			goto fail;
+
+		diff1 = out_freq - input * mul1;
+		if (diff1 < 0)
+			diff1 = -diff1;
+		if (diff > diff1) {
+			diff = diff1;
+			div = i;
+			mul = mul1;
+			if (diff == 0)
+				break;
+		}
+	}
+	if (i == 256 && diff > (out_freq >> 5))
+		goto fail;
+	return ret | ((mul - 1) << 16) | div;
+fail:
+	return 0;
+}
+
+static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
+{
+	if (pll == &pllb && (reg & AT91_PMC_USB96M))
+		return freq / 2;
+	else
+		return freq;
+}
+
+
+// PLLB generated USB full speed clock init
+static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
+{
+	rt_uint32_t at91_pllb_usb_init;
+	//
+	// USB clock init:  choose 48 MHz PLLB value,
+	// disable 48MHz clock during usb peripheral suspend.
+	//
+	// REVISIT:  assumes MCK doesn't derive from PLLB!
+	//
+	uhpck.parent = &pllb;
+
+	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+	
+	at91_sys_write(AT91_CKGR_PLLBR, 0);
+
+	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+}
+
+static struct clk *at91_css_to_clk(unsigned long css)
+{
+	switch (css) {
+		case AT91_PMC_CSS_SLOW:
+			return &clk32k;
+		case AT91_PMC_CSS_MAIN:
+			return &main_clk;
+		case AT91_PMC_CSS_PLLA:
+			return &plla;
+		case AT91_PMC_CSS_PLLB:
+			return &pllb;
+	}
+
+	return RT_NULL;
+}
+
+#define false 0
+#define true  1
+int at91_clock_init(rt_uint32_t main_clock)
+{
+	unsigned tmp, freq, mckr;
+	int i;
+	int pll_overclock = false;
+
+	//
+	// When the bootloader initialized the main oscillator correctly,
+	// there's no problem using the cycle counter.  But if it didn't,
+	// or when using oscillator bypass mode, we must be told the speed
+	 // of the main clock.
+	//
+	if (!main_clock) {
+		do {
+			tmp = at91_sys_read(AT91_CKGR_MCFR);
+		} while (!(tmp & AT91_PMC_MAINRDY));
+		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+	}
+	main_clk.rate_hz = main_clock;
+
+	// report if PLLA is more than mildly overclocked 
+	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+	if (plla.rate_hz > 209000000)
+		pll_overclock = true;
+	if (pll_overclock)
+		;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+
+	at91_pllb_usbfs_clock_init(main_clock);
+
+	//
+	 // MCK and CPU derive from one of those primary clocks.
+	 // For now, assume this parentage won't change.
+	 //
+	mckr = at91_sys_read(AT91_PMC_MCKR);
+	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+	freq = mck.parent->rate_hz;
+	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				// prescale 
+	
+	mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      // mdiv 
+
+	// Register the PMC's standard clocks 
+	rt_list_init(&clocks);
+	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+	rt_list_insert_after(&clocks, &pllb.node);
+	rt_list_insert_after(&clocks, &uhpck.node);
+	rt_list_insert_after(&clocks, &udpck.node);
+
+	// MCK and CPU clock are "always on" 
+	//clk_enable(&mck);
+
+	//rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+	//	freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+	//	(unsigned) main_clock / 1000000,
+	//	((unsigned) main_clock % 1000000) / 1000); //cause blocked
+
+	return 0;
+}
+*/
+
+ // @brief System Clock Configuration
+
+void rt_hw_clock_init(void)
+{
+	//at91_clock_init(18432000);
+}
+
diff --git a/bsp/asm9260t/platform/timer0.c b/bsp/asm9260t/platform/timer0.c
new file mode 100644
index 0000000000..38c6d3ef31
--- /dev/null
+++ b/bsp/asm9260t/platform/timer0.c
@@ -0,0 +1,55 @@
+/*
+ * File      : timer0.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-29     ArdaFu       first version
+ */
+
+#include "timer0.h"
+#include "ASM9260T.h"
+#include "rtthread.h"
+void hw_timer0_init(void)
+{
+    uint32_t pclk;
+
+    // enable timer0's clock, reset timer0
+    outl((1<<4), REG_SET(HW_AHBCLKCTRL1));
+    outl((1<<4), REG_CLR(HW_PRESETCTRL1));
+    outl((1<<4), REG_SET(HW_PRESETCTRL1));
+
+    outl((1<<0), REG_CLR(HW_TIMER0_TCR));
+
+    outl((3<<0), REG_CLR(HW_TIMER0_CTCR));
+
+    outl((3<<0), REG_CLR(HW_TIMER0_DIR));
+
+    outl(0, REG_CLR(HW_TIMER0_PR));
+    outl(0, REG_CLR(HW_TIMER0_PC));
+
+    outl((7<<0), REG_CLR(HW_TIMER0_MCR));
+    outl((3<<0), REG_SET(HW_TIMER0_MCR));
+
+    pclk = (inl(HW_SYSPLLCTRL)&0x1FF)*1000000u/4u;
+    outl(pclk/RT_TICK_PER_SECOND, HW_TIMER0_MR0);
+
+    outl((1<<4), REG_SET(HW_TIMER0_TCR));
+    outl((1<<4), REG_CLR(HW_TIMER0_TCR));
+    outl((1<<0), REG_SET(HW_TIMER0_TCR));
+}
diff --git a/bsp/asm9260t/platform/timer0.h b/bsp/asm9260t/platform/timer0.h
new file mode 100644
index 0000000000..338ef05816
--- /dev/null
+++ b/bsp/asm9260t/platform/timer0.h
@@ -0,0 +1,34 @@
+/*
+ * File      : timer0.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-29     ArdaFu       first version
+ */
+
+#ifndef __HW_TIMER0_H__
+#define __HW_TIMER0_H__
+////////////////////////////////////////////////////////////////////////////////
+#include "stdint.h"
+
+extern void hw_timer0_init(void);
+
+////////////////////////////////////////////////////////////////////////////////
+#endif /* __HW_TIMER0_H__ */
+
diff --git a/bsp/asm9260t/platform/uart.c b/bsp/asm9260t/platform/uart.c
new file mode 100644
index 0000000000..f6e3a89ad6
--- /dev/null
+++ b/bsp/asm9260t/platform/uart.c
@@ -0,0 +1,112 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+ 
+#include "ASM9260T.h"
+#include "rtthread.h"
+#include "uart.h"
+
+void Hw_UartDisable(HW_USART_TypeDef* uartBase)
+{
+    uartBase->INTR[R_CLR] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_TXIEN | ASM_UART_INTR_RTIS;
+    uartBase->CTRL2[R_CLR] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE;
+}
+
+void Hw_UartEnable(HW_USART_TypeDef* uartBase)
+{
+    uartBase->CTRL2[R_CLR] = 0x0000C000UL; //clear CTSEN and RTSEN
+    uartBase->CTRL2[R_SET] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE | ASM_UART_CTRL2_USARTEN;
+    uartBase->INTR[R_SET] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_RTIEN;
+}
+
+void Hw_UartReset(HW_USART_TypeDef* uartBase)
+{
+    uartBase->CTRL0[R_CLR] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
+    uartBase->CTRL0[R_SET] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
+}
+
+void Hw_UartConfig(HW_USART_TypeDef* uartBase,int baudRate, int dataBits, int stopBits,int parity)
+{
+    rt_uint32_t mode = ASM_UART_LINECTRL_FEN;
+
+    switch (dataBits)
+    {
+    case 8:
+        mode |= ASM_UART_LINECTRL_WLEN8;
+        break;
+    case 7:
+        mode |= ASM_UART_LINECTRL_WLEN7;
+        break;
+    case 6:
+        mode |= ASM_UART_LINECTRL_WLEN6;
+        break;
+    case 5:
+        mode |= ASM_UART_LINECTRL_WLEN5;
+        break;
+    default:
+        mode |= ASM_UART_LINECTRL_WLEN8;
+        break;
+    }
+
+    switch (stopBits)
+    {
+    case 2:
+        mode |= ASM_UART_LINECTRL_STP2;
+        break;
+    case 1:
+    default:
+        break;
+    }
+
+    switch (parity)
+    {
+    case 1:
+        mode |= ASM_UART_LINECTRL_PEN;
+        break;
+    case 2:
+        mode |= ASM_UART_LINECTRL_PEN | ASM_UART_LINECTRL_EPS;
+        break;
+    case 0:
+    default:
+        break;
+    }
+    //16bit nBaudDivint
+    mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVINT_MASK) << 10;
+    //6bit nNaudDivfrac
+    mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVFRAC_MASK) << 8;
+
+
+    uartBase->LINECTRL[R_VAL] = mode;
+}
+
+void Hw_UartInit(int index)
+{
+    // uart0 = bit11, uart9 = bit20
+    int ctrl_bit = index + 11;
+    outl(1UL<<ctrl_bit,REG_SET(HW_AHBCLKCTRL0));    //UART4 ENABLE bit15
+    outl(0x1, HW_UART0CLKDIV + index*4);            //UART4 div 2
+    outl(1UL<<ctrl_bit,REG_CLR(HW_AHBCLKCTRL0));    //UART4 clk gate
+    outl(1UL<<ctrl_bit,REG_SET(HW_AHBCLKCTRL0));    //UART4 clk gate
+    outl(1UL<<ctrl_bit,REG_CLR(HW_PRESETCTRL0));    //UART4 reset
+    outl(1UL<<ctrl_bit,REG_SET(HW_PRESETCTRL0));    //UART4 reset
+}
diff --git a/bsp/asm9260t/platform/uart.h b/bsp/asm9260t/platform/uart.h
new file mode 100644
index 0000000000..b1645e2ec5
--- /dev/null
+++ b/bsp/asm9260t/platform/uart.h
@@ -0,0 +1,111 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+#ifndef __UART_H__
+#define __UART_H__
+
+#define R_VAL 0
+#define R_SET 1
+#define R_CLR 2
+#define R_TOG 3
+
+typedef struct
+{
+    volatile rt_uint32_t CTRL0[4];
+    volatile rt_uint32_t CTRL1[4];
+    volatile rt_uint32_t CTRL2[4];
+    volatile rt_uint32_t LINECTRL[4];
+    volatile rt_uint32_t INTR[4];
+    volatile rt_uint32_t DATA[4];
+    volatile rt_uint32_t STAT[4];
+    volatile const rt_uint32_t DEBUG[4];
+    volatile rt_uint32_t ILPR[4];
+    volatile rt_uint32_t RS485CTRL[4];
+    volatile rt_uint32_t RS485ADRMATCH[4];
+    volatile rt_uint32_t RS485DLY[4];
+    volatile rt_uint32_t AUTOBAUD[4];
+    volatile rt_uint32_t CTRL3[4];
+    volatile rt_uint32_t ISO7816CTRL[4];
+    volatile rt_uint32_t ISO7816ERRCNT[4];
+    volatile rt_uint32_t ISO7816STATUS[4];
+} HW_USART_TypeDef;
+
+#define USART0	((HW_USART_TypeDef *)UART0_BASE)
+#define USART1	((HW_USART_TypeDef *)UART1_BASE)
+#define USART2	((HW_USART_TypeDef *)UART2_BASE)
+#define USART3	((HW_USART_TypeDef *)UART3_BASE)
+#define USART4	((HW_USART_TypeDef *)UART4_BASE)
+#define USART5	((HW_USART_TypeDef *)UART5_BASE)
+#define USART6	((HW_USART_TypeDef *)UART6_BASE)
+#define USART7	((HW_USART_TypeDef *)UART7_BASE)
+#define USART8	((HW_USART_TypeDef *)UART8_BASE)
+#define USART9	((HW_USART_TypeDef *)UART9_BASE)
+
+
+#define ASM_UART_INTR_RXIS   (1UL << 4)
+#define ASM_UART_INTR_TXIS   (1UL << 5)
+#define ASM_UART_INTR_RTIS   (1UL << 6)
+#define ASM_UART_INTR_RXIEN  (1UL << 20)
+#define ASM_UART_INTR_TXIEN  (1UL << 21)
+#define ASM_UART_INTR_RTIEN  (1UL << 22)
+
+
+#define UART_BAUD_DIVINT_MASK       0x003FFFC0UL
+#define UART_BAUD_DIVFRAC_MASK      0x0000003FUL
+#define UART_FIFO_ENABLE            0x00000010UL
+#define MAIN_CLOCK_EXT12M           0
+#define MAIN_CLOCK_SYSPLL           1
+#define UART_INT_FIFO_LV_SEL_MASK   0x00770000UL
+#define RXTIMEOUT_ENABLE            0x01000000UL
+#define RXTIMEOUT_MASK              0x00FF0000UL
+
+
+#define ASM_UART_CTRL0_SFTRST       (1UL << 31)
+#define ASM_UART_CTRL0_CLKGATE      (1UL << 30)
+#define ASM_UART_CTRL0_RXTO_ENABLE  (1UL << 24)
+
+#define ASM_UART_CTRL2_USARTEN      (1UL << 0)
+#define ASM_UART_CTRL2_TXE          (1UL << 8)
+#define ASM_UART_CTRL2_RXE          (1UL << 9)
+
+
+#define ASM_UART_LINECTRL_PEN       (1UL << 1)
+#define ASM_UART_LINECTRL_EPS       (1UL << 2)
+#define ASM_UART_LINECTRL_STP2      (1UL << 3)
+#define ASM_UART_LINECTRL_FEN       (1UL << 4)
+#define ASM_UART_LINECTRL_WLEN5     (0UL << 5)
+#define ASM_UART_LINECTRL_WLEN6     (1UL << 5)
+#define ASM_UART_LINECTRL_WLEN7     (2UL << 5)
+#define ASM_UART_LINECTRL_WLEN8     (3UL << 5)
+#define ASM_UART_LINECTRL_SPS       (1UL << 7)
+
+#define ASM_UART_STAT_TXFF (1UL << 25)
+#define ASM_UART_STAT_RXFE (1UL << 24)
+
+extern void Hw_UartDisable(HW_USART_TypeDef* uartBase);
+extern void Hw_UartEnable(HW_USART_TypeDef* uartBase);
+extern void Hw_UartReset(HW_USART_TypeDef* uartBase);
+extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, 
+                          int dataBits, int stopBits, int parity);
+extern void Hw_UartInit(int index);
+#endif