将at91系列BSP并入一个文件夹中

3 files changed, 0 insertions, 730 deletions

diff --git a/bsp/at91sam9260/debug_scripts/at91sam9260.gdb b/bsp/at91sam9260/debug_scripts/at91sam9260.gdb
deleted file mode 100644
index fef3264f3e..0000000000
--- a/bsp/at91sam9260/debug_scripts/at91sam9260.gdb
+++ /dev/null
@@ -1,230 +0,0 @@
-#------------------------------------------------
-# SDRAM initialization script for the AT91SAM9260
-#------------------------------------------------
-
-#----------------------------------------------------------------------------
-# _InitRSTC()
-# Function description
-#   Initializes the RSTC (Reset controller).
-#   This makes sense since the default is to not allow user resets, which makes it impossible to
-#   apply a second RESET via J-Link
-#----------------------------------------------------------------------------
-
-define _InitRSTC
-	# Allow user reset
-    set *0xFFFFFD08=0xA5000001    
-end
-
-#----------------------------------------------------------------------------
-# _MapRAMAt0()
-# Function description: Maps RAM at 0.
-#----------------------------------------------------------------------------
-define _MapRAMAt0
-    echo "---------- SRAM remapped to 0 --------" \n
-    # Test and set Remap
-    set $__mac_i = *0xFFFFEF00
-    if ( (($__mac_i & 0x01) == 0) || (($__mac_i & 0x02) == 0))
-		#toggle remap bits
-		set *0xFFFFEF00 = 0x03 
-    else
-        echo "---------- The Remap is done ---------" \n
-	end
-end
-
-#----------------------------------------------------------------------------
-#
-#  _PllSetting()
-#  Function description
-#  Initializes the PMC.
-#  1. Enable the Main Oscillator
-#  2. Configure PLL
-#  3. Switch Master
-#----------------------------------------------------------------------------
-
-define __PllSetting
-    if ((*(0xFFFFFC30)&0x3) != 0 ) 
-		# Disable all PMC interrupt ( $$ JPP)
-		# AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) #(PMC) Interrupt Disable Register
-		# pPmc->PMC_IDR = 0xFFFFFFFF;
-	    set *0xFFFFFC64 = 0xFFFFFFFF
-		# AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) #(PMC) Peripheral Clock Disable Register
-	    set *0xFFFFFC14 = 0xFFFFFFFF
-		# Disable all clock only Processor clock is enabled.
-	    set *0xFFFFFC04 = 0xFFFFFFFE
-		# AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) # (PMC) Master Clock Register
-	    set *0xFFFFFC30 = 0x00000001
-
-		while ((*0xFFFFFC68 & 0x8) == 0)
-		end
-
-	    
-		# write reset value to PLLA and PLLB
-	    # AT91C_PMC_PLLAR ((AT91_REG *) 	0xFFFFFC28) # (PMC) PLL A Register
-	    set *0xFFFFFC28 = 0x00003F00
-	
-	    # AT91C_PMC_PLLBR ((AT91_REG *) 	0xFFFFFC2C) # (PMC) PLL B Register
-	    set *0xFFFFFC2C 0x00003F00
-	    while ((*0xFFFFFC68 & 0x2) == 0)
-		end
-		while ((*0xFFFFFC68 & 0x4) == 0)
-		end
-	
-	    echo "---------- PLL  Enable ---------------" \n
-    
-    else 
-   		echo "---------- Core in SLOW CLOCK mode ---" \n
-	end
-end
-
-
-#----------------------------------------------------------------------------
-#
-#      __PllSetting100MHz()
-# Function description
-#  Set core at 200 MHz and MCK at 100 MHz 
-#----------------------------------------------------------------------------
-
-define __PllSetting100MHz
-	echo "---------- PLL Set at 100 MHz --------" \n
-
-	#* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
-    set *0xFFFFFC20=0x00004001
-	    while ((*0xFFFFFC68 & 0x1) == 0)
-		end
-	# AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) # (PMC) Master Clock Register
-    set *0xFFFFFC30=0x00000001
-	    while ((*0xFFFFFC68 & 0x8) == 0)
-		end
-	#*   AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) | 
-	#    (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
-    set *0xFFFFFC28=0x2060BF09
-	    while ((*0xFFFFFC68 & 0x2) == 0)
-		end
-    # Configure PLLB
-    set *0xFFFFFC2C=0x207C3F0C
-	    while ((*0xFFFFFC68 & 0x4) == 0)
-		end
-	#*   AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
-    set *0xFFFFFC30=0x00000102
-     	while ((*0xFFFFFC68 & 0x8) == 0)
-		end
-end
-
-
-#----------------------------------------------------------------------------
-#      __initSDRAM()
-#  Function description
-#  Set SDRAM for works at 100 MHz
-#----------------------------------------------------------------------------
-
-define __initSDRAM
-
-    # Configure EBI Chip select	
-    # pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
-    # AT91C_CCFG_EBICSA ((AT91_REG *) 	0xFFFFEF1C) # (CCFG)  EBI Chip Select Assignement Register
-    set *0xFFFFEF1C=0x0001003A
-    
-    # Configure PIOs
-    # AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
-    # pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) # (PIOC) Select A Register
-    # pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR  ((AT91_REG *) 0xFFFFF874) # (PIOC) Select B Register
-    # pPio->PIO_PDR = (periphAEnable | periphBEnable # Set in Periph mode
-    set *0xFFFFF870=0xFFFF0000
-    set *0xFFFFF874=0x00000000
-    set *0xFFFFF804=0xFFFF0000
-    
-    # psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
-    # AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
-    # AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
-    set *0xFFFFEA08=0x85227259
-	set $i = 0
-	while $i != 100
-	  set $i += 1
-	end
-    # psdrc->SDRAMC_MR	= 0x00000002;		# Set PRCHG AL
-    set *0xFFFFEA00=0x00000002
-    # *AT91C_SDRAM	= 0x00000000;			# Perform PRCHG
-    set *0x20000000=0x00000000
-	set $i = 0
-	while $i != 100
-	  set $i += 1
-	end
-
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		# Set 1st CBR
-    set *0xFFFFEA00=0x00000004
-    
-    # *(AT91C_SDRAM+4)	= 0x00000001;	# Perform CBR
-    set *0x20000010=0x00000001
-    
-    # psdrc->SDRAMC_MR	= 0x00000004;		# Set 2 CBR
-    set *0xFFFFEA00=0x00000004
-    # *(AT91C_SDRAM+8)	= 0x00000002;	# Perform CBR
-    set *0x20000020=0x00000002
-    
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		# Set 3 CBR
-    set *0xFFFFEA00=0x00000004
-    # *(AT91C_SDRAM+0xc)	= 0x00000003;	# Perform CBR
-    set *0x20000030=0x00000003
-       
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		# Set 4 CBR
-    set *0xFFFFEA00=0x00000004
-    # *(AT91C_SDRAM+0x10)	= 0x00000004;	# Perform CBR
-    set *0x20000040=0x00000004
-       
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		# Set 5 CBR
-    set *0xFFFFEA00=0x00000004
-    # *(AT91C_SDRAM+0x14)	= 0x00000005;	# Perform CBR
-    set *0x20000050=0x00000005
-       
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		# Set 6 CBR
-    set *0xFFFFEA00=0x00000004
-    # *(AT91C_SDRAM+0x18)	= 0x00000006;	# Perform CBR
-    set *0x20000060=0x00000006
-       
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		# Set 7 CBR
-    set *0xFFFFEA00=0x00000004
-    # *(AT91C_SDRAM+0x1c)	= 0x00000007;	# Perform CBR
-    set *0x20000070=0x00000007
-       
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		# Set 8 CBR
-    set *0xFFFFEA00=0x00000004
-    # *(AT91C_SDRAM+0x20)	= 0x00000008;	# Perform CBR
-    set *0x20000080=0x00000008
-       
-    # psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_LMR_CMD;		# Set LMR operation
-    set *0xFFFFEA00=0x00000003
-    # *(AT91C_SDRAM+0x24)	= 0xcafedede;		# Perform LMR burst=1, lat=2
-    set *0x20000090=0xCAFEDEDE
-       
-    # psdrc->SDRAMC_TR	= (AT91C_MASTER_CLOCK * 7)/1000000;				# Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
-    set *0xFFFFEA04=0x000002B9
-    
-    #*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_NORMAL_CMD;		# Set Normal mode
-    set *0xFFFFEA00=0x00000000
-    
-    #*	*AT91C_SDRAM	= 0x00000000;	# Perform Normal mode
-    set *0x20000000=0x00000000
-    echo "---------- SDRAM Done at 100 MHz -----" \n
-end
-
-# Step1: Connect to the J-Link gdb server
-define reset
-	#target remote localhost:2331
-	monitor reset
-
-	# Step2: Reset peripheral  (RSTC_CR)
-	#Init PLL
-	__PllSetting
-	__PllSetting100MHz    
-	__initSDRAM
-	#* Set the RAM memory at 0x0020 0000 & 0x0000 0000
-	_MapRAMAt0                     
-	_InitRSTC
-	
-	# Step3: Load file(eg. getting-started project)
-	load
-
-	mon reg pc=0x20000000
-	#info reg
-
-end
\ No newline at end of file
diff --git a/bsp/at91sam9260/debug_scripts/at91sam9260.ini b/bsp/at91sam9260/debug_scripts/at91sam9260.ini
deleted file mode 100644
index 7101955498..0000000000
--- a/bsp/at91sam9260/debug_scripts/at91sam9260.ini
+++ /dev/null
@@ -1,248 +0,0 @@
-// ----------------------------------------------------------------------------

-//         ATMEL Microcontroller Software Support 

-// ----------------------------------------------------------------------------

-// Copyright (c) 2008, Atmel Corporation

-//

-// All rights reserved.

-//

-// Redistribution and use in source and binary forms, with or without

-// modification, are permitted provided that the following conditions are met:

-//

-// - Redistributions of source code must retain the above copyright notice,

-// this list of conditions and the disclaimer below.

-//

-// Atmel's name may not be used to endorse or promote products derived from

-// this software without specific prior written permission.

-//

-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR

-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE

-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,

-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,

-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-// ----------------------------------------------------------------------------

-

-//----------------------------------------------------------------------------

-//  File Name           : at91sam9260-ek-sdram.ini

-//  Object              : Generic Macro File for KEIL

-//----------------------------------------------------------------------------

-

-//----------------------------------------------------------------------------

-// _MapRAMAt0()

-// Function description: Maps RAM at 0.

-//----------------------------------------------------------------------------

-

-DEFINE INT  __mac_i;

-

-FUNC void _MapRAMAt0(){

-

-	

-    printf ("Changing mapping: RAM mapped to 0 \n");

-    // Test and set Remap

-    __mac_i = _RDWORD(0xFFFFEF00);

-    if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0))

-	{

-		_WDWORD(0xFFFFEF00,0x03);    // toggle remap bits

-	}

-    else

-    {

-        printf ("------------------------------- The Remap is done -----------------------------------\n");

-	}

-}

-

-

-//----------------------------------------------------------------------------

-// _InitRSTC()

-// Function description

-//   Initializes the RSTC (Reset controller).

-//   This makes sense since the default is to not allow user resets, which makes it impossible to

-//   apply a second RESET via J-Link

-//----------------------------------------------------------------------------

-

-FUNC void _InitRSTC() {

-

-    _WDWORD(0xFFFFFD08,0xA5000001);    // Allow user reset

-

-}

-

-//----------------------------------------------------------------------------

-//

-//  _PllSetting()

-//  Function description

-//  Initializes the PMC.

-//  1. Enable the Main Oscillator

-//  2. Configure PLL

-//  3. Switch Master

-//----------------------------------------------------------------------------

-

-FUNC void __PllSetting() 

-{

-

-    if ((_RDWORD(0xFFFFFC30)&0x3) != 0 ) 

-	{

-		// Disable all PMC interrupt ( $$ JPP)

-		// AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register

-		// pPmc->PMC_IDR = 0xFFFFFFFF;

-	    _WDWORD(0xFFFFFC64,0xFFFFFFFF);

-		// AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register

-	    _WDWORD(0xFFFFFC14,0xFFFFFFFF);

-		// Disable all clock only Processor clock is enabled.

-	    _WDWORD(0xFFFFFC04,0xFFFFFFFE);

-		// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register

-	    _WDWORD(0xFFFFFC30,0x00000001);

-	    _sleep_(10);

-	    // write reset value to PLLA and PLLB

-	    // AT91C_PMC_PLLAR ((AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register

-	    _WDWORD(0xFFFFFC28,0x00003F00);

-	

-	    // AT91C_PMC_PLLBR ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register

-	    _WDWORD(0xFFFFFC2C,0x00003F00);

-	    _sleep_(10);

-	

-	    printf ( "------------------------------- PLL  Enable -----------------------------------------");

-    

-	} 

-    else {

-   		printf( " ********* Core in SLOW CLOCK mode ********* "); 

-	}

-}

-

-

-//----------------------------------------------------------------------------

-//

-//      __PllSetting100MHz()

-// Function description

-//  Set core at 200 MHz and MCK at 100 MHz 

-//----------------------------------------------------------------------------

-

-FUNC void __PllSetting100MHz()

-{

-

-	printf( "------------------------------- PLL Set at 100 MHz ----------------------------------");

-

-	//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));

-    _WDWORD(0xFFFFFC20,0x00004001);

-    _sleep_(10);

-	// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register

-    _WDWORD(0xFFFFFC30,0x00000001);

-    _sleep_(10);

-	//*   AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) | 

-	//    (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);

-    _WDWORD(0xFFFFFC28,0x2060BF09);

-    _sleep_(10);

-    // Configure PLLB

-    _WDWORD(0xFFFFFC2C,0x207C3F0C);

-    _sleep_(10);

-	//*   AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;

-    _WDWORD(0xFFFFFC30,0x00000102);

-     _sleep_(10);

-

-}

-

-//----------------------------------------------------------------------------

-//      __initSDRAM()

-//  Function description

-//  Set SDRAM for works at 100 MHz

-//----------------------------------------------------------------------------

-

-FUNC void __initSDRAM()

-{

-

-    // Configure EBI Chip select	

-    // pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;

-    // AT91C_CCFG_EBICSA ((AT91_REG *) 	0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register

-    _WDWORD(0xFFFFEF1C,0x0001003A);

-    

-    // Configure PIOs

-    // AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31

-    // pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register

-    // pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR  ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register

-    // pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode

-    _WDWORD(0xFFFFF870,0xFFFF0000);

-    _WDWORD(0xFFFFF874,0x00000000);

-    _WDWORD(0xFFFFF804,0xFFFF0000);

-    

-    // psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |

-    // AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |

-    // AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;

-    _WDWORD(0xFFFFEA08,0x85227259);

-    _sleep_(10);

-    // psdrc->SDRAMC_MR	= 0x00000002;		// Set PRCHG AL

-    _WDWORD(0xFFFFEA00,0x00000002);

-    // *AT91C_SDRAM	= 0x00000000;			// Perform PRCHG

-    _WDWORD(0x20000000,0x00000000);

-    _sleep_(10);

-

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    

-    // *(AT91C_SDRAM+4)	= 0x00000001;	// Perform CBR

-    _WDWORD(0x20000010,0x00000001);

-    

-    // psdrc->SDRAMC_MR	= 0x00000004;		// Set 2 CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    // *(AT91C_SDRAM+8)	= 0x00000002;	// Perform CBR

-    _WDWORD(0x20000020,0x00000002);

-    

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 3 CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    // *(AT91C_SDRAM+0xc)	= 0x00000003;	// Perform CBR

-    _WDWORD(0x20000030,0x00000003);

-       

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 4 CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    // *(AT91C_SDRAM+0x10)	= 0x00000004;	// Perform CBR

-    _WDWORD(0x20000040,0x00000004);

-       

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 5 CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    // *(AT91C_SDRAM+0x14)	= 0x00000005;	// Perform CBR

-    _WDWORD(0x20000050,0x00000005);

-       

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 6 CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    // *(AT91C_SDRAM+0x18)	= 0x00000006;	// Perform CBR

-    _WDWORD(0x20000060,0x00000006);

-       

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 7 CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    // *(AT91C_SDRAM+0x1c)	= 0x00000007;	// Perform CBR

-    _WDWORD(0x20000070,0x00000007);

-       

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 8 CBR

-    _WDWORD(0xFFFFEA00,0x00000004);

-    // *(AT91C_SDRAM+0x20)	= 0x00000008;	// Perform CBR

-    _WDWORD(0x20000080,0x00000008);

-       

-    // psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_LMR_CMD;		// Set LMR operation

-    _WDWORD(0xFFFFEA00,0x00000003);

-    // *(AT91C_SDRAM+0x24)	= 0xcafedede;		// Perform LMR burst=1, lat=2

-    _WDWORD(0x20000090,0xCAFEDEDE);

-       

-    // psdrc->SDRAMC_TR	= (AT91C_MASTER_CLOCK * 7)/1000000;				// Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )

-    _WDWORD(0xFFFFEA04,0x000002B9);

-    

-    //*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_NORMAL_CMD;		// Set Normal mode

-    _WDWORD(0xFFFFEA00,0x00000000);

-    

-    //*	*AT91C_SDRAM	= 0x00000000;	// Perform Normal mode

-    _WDWORD(0x20000000,0x00000000);

-    printf( "------------------------------- SDRAM Done at 100 MHz -------------------------------");

-

-

-}

-

-

-__PllSetting();                   //* Init PLL

-__PllSetting100MHz();    

-__initSDRAM();

-_MapRAMAt0();                     //* Set the RAM memory at 0x0020 0000 & 0x0000 0000

-_InitRSTC(); 

-DEBUG_CLOCK = 2000000;

-LOAD Objects\\template.axf INCREMENTAL

-PC = 0x20000000;

-//g,main
\ No newline at end of file
diff --git a/bsp/at91sam9260/debug_scripts/at91sam9260.mac b/bsp/at91sam9260/debug_scripts/at91sam9260.mac
deleted file mode 100644
index 4745aafd37..0000000000
--- a/bsp/at91sam9260/debug_scripts/at91sam9260.mac
+++ /dev/null
@@ -1,252 +0,0 @@
-// ---------------------------------------------------------
-//   ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ---------------------------------------------------------
-// The software is delivered "AS IS" without warranty or
-// condition of any  kind, either express, implied or
-// statutory. This includes without limitation any warranty
-// or condition with respect to merchantability or fitness
-// for any particular purpose, or against the infringements of
-// intellectual property rights of others.
-// ---------------------------------------------------------
-//  File: SAM9_SDRAM.mac
-//  User setup file for CSPY debugger.
-//  1.1 08/Aug/06 jpp    : Creation
-//
-//  $Revision: 1.1.2.1 $
-//
-// ---------------------------------------------------------
-__var __mac_i;
-__var __mac_pt;
-
-/*********************************************************************
-*
-*       execUserReset() : JTAG set initially to Full Speed
-*/
-execUserReset()
-{
-    __message "------------------------------ execUserReset ---------------------------------";
-    _MapRAMAt0();                          //* Set the RAM memory at 0x00200000 & 0x00000000
-    __PllSetting();                        //* Init PLL
-    __PllSetting100MHz();              
-    __message "-------------------------------Set PC Reset ----------------------------------";
-}
-
-/*********************************************************************
-*
-*       execUserPreload() : JTAG set initially to 32kHz
-*/
-execUserPreload()
-{
-    __message "------------------------------ execUserPreload ---------------------------------";
-    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
-    __writeMemory32(0xD3,0x98,"Register"); //*  Set CPSR
-    __PllSetting();                        //* Init PLL
-    __PllSetting100MHz();    
-    __initSDRAM();                         //* Init SDRAM before load          
-    _MapRAMAt0();                          //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
-    _InitRSTC();                           //* Enable User Reset to allow execUserReset() execution
-}
-
-
-
-/*********************************************************************
-*
-*       _InitRSTC()
-*
-* Function description
-*   Initializes the RSTC (Reset controller).
-*   This makes sense since the default is to not allow user resets, which makes it impossible to
-*   apply a second RESET via J-Link
-*/
-_InitRSTC() {
-    __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory");    // Allow user reset
-}
-
-
-/*********************************************************************
-*
-*       __initSDRAM()
-* Function description
-* Set SDRAM for works at 100 MHz
-*/
-__initSDRAM()
-{
-//* Configure EBI Chip select	
-//    pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC | (1 << 16);
-// AT91C_CCFG_EBICSA ((AT91_REG *) 	0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
-    __writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");
-
-
-//*  Configure PIOs
-//*	AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
-// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
-// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR  ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
-// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-    __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
-    __writeMemory32(0x00000000,0xFFFFF874,"Memory");
-    __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
-
-//* psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
-//  AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
-//  AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
-    __writeMemory32(0x85227259,0xFFFFEA08,"Memory");
- __delay(1); //100
-//*	psdrc->SDRAMC_MR	= 0x00000002;		// Set PRCHG AL
-    __writeMemory32(0x00000002,0xFFFFEA00,"Memory");
-//*	*AT91C_SDRAM	= 0x00000000;			// Perform PRCHG
-    __writeMemory32(0x00000000,0x20000000,"Memory");
- __delay(1); //100
-
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
-      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
-
-//*	*(AT91C_SDRAM+4)	= 0x00000001;	// Perform CBR
-    __writeMemory32(0x00000001,0x20000010,"Memory");
-
-//*	psdrc->SDRAMC_MR	= 0x00000004;		// Set 2 CBR
-     __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
-//*	*(AT91C_SDRAM+8)	= 0x00000002;	// Perform CBR
-     __writeMemory32(0x00000002,0x20000020,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 3 CBR
-      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
-//*	*(AT91C_SDRAM+0xc)	= 0x00000003;	// Perform CBR
-     __writeMemory32(0x00000003,0x20000030,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 4 CBR
-      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
-//*	*(AT91C_SDRAM+0x10)	= 0x00000004;	// Perform CBR
-     __writeMemory32(0x00000004,0x20000040,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 5 CBR
-      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
-//*	*(AT91C_SDRAM+0x14)	= 0x00000005;	// Perform CBR
-     __writeMemory32(0x00000005,0x20000050,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 6 CBR
-      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
-//*	*(AT91C_SDRAM+0x18)	= 0x00000006;	// Perform CBR
-     __writeMemory32(0x00000006,0x20000060,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 7 CBR
-      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");	
-//*	*(AT91C_SDRAM+0x1c)	= 0x00000007;	// Perform CBR
-     __writeMemory32(0x00000007,0x20000070,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 8 CBR
-      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
-//*	*(AT91C_SDRAM+0x20)	= 0x00000008;	// Perform CBR
-     __writeMemory32(0x00000008,0x20000080,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_LMR_CMD;		// Set LMR operation
-      __writeMemory32(0x00000003,0xFFFFEA00,"Memory");
-//*	*(AT91C_SDRAM+0x24)	= 0xcafedede;		// Perform LMR burst=1, lat=2
-     __writeMemory32(0xCAFEDEDE,0x20000090,"Memory");
-
-//*	psdrc->SDRAMC_TR	= (AT91C_MASTER_CLOCK * 7)/1000000;				// Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
-//									               // (F : system clock freq. MHz
-
-      __writeMemory32(0x000002B7,0xFFFFEA04,"Memory");
-
-//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_NORMAL_CMD;		// Set Normal mode
-      __writeMemory32(0x00000000,0xFFFFEA00,"Memory");
-
-//*	*AT91C_SDRAM	= 0x00000000;	// Perform Normal mode
-      __writeMemory32(0x00000000,0x20000000,"Memory");
-   __message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
-
-}
-
-/*********************************************************************
-*
-*       _MapRAMAt0()
-* Function description
-* Remap RAM at 0
-*/
-_MapRAMAt0()
-{
-// AT91C_MATRIX_MRCR ((AT91_REG *) 	0xFFFFEF00) // (MATRIX)  Master Remp Control Register
-    __mac_i=__readMemory32(0xFFFFEF00,"Memory");
-    __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
-
-    if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
-        __message "------------------------------- The Remap is NOT & REMAP ----------------------------";
-        __writeMemory32(0x00000003,0xFFFFEF00,"Memory");
-        __mac_i=__readMemory32(0xFFFFEF00,"Memory");
-        __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
-    } else {
-        __message "------------------------------- The Remap is done -----------------------------------";
-    }
-}
-
-
-/*********************************************************************
-*
-*       __PllSetting()
-* Function description
-*   Initializes the PMC.
-*   1. Enable the Main Oscillator
-*   2. Configure PLL
-*   3. Switch Master
-*/
-__PllSetting()
-{
-     if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
-//* Disable all PMC interrupt ( $$ JPP)
-//* AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
-//*    pPmc->PMC_IDR = 0xFFFFFFFF;
-    __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
-//* AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
-    __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
-// Disable all clock only Processor clock is enabled.
-    __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
-
-// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
-    __delay(10); //10000
-
-// write reset value to PLLA and PLLB
-// AT91C_PMC_PLLAR ((AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
-    __writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
-
-// AT91C_PMC_PLLBR ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register
-    __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
-    __delay(10); //10000
-
-   __message "------------------------------- PLL  Enable -----------------------------------------";
-   } else {
-   __message " ********* Core in SLOW CLOCK mode ********* "; }
-}
-
-
-/*********************************************************************
-*
-*       __PllSetting100MHz()
-* Function description
-*   Set core at 200 MHz and MCK at 100 MHz 
-*/
-__PllSetting100MHz()
-{
-
-   __message "------------------------------- PLL Set at 100 MHz ----------------------------------";
-
-//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
-    __writeMemory32(0x00004001,0xFFFFFC20,"Memory");
-    __delay(10); //10000
-// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
-    __delay(10); //10000
-//*   AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) | 
-//    (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
-    __writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
-    __delay(10); //10000
-// AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV| BOARD_CKGR_PLLB | BOARD_PLLBCOUNT | BOARD_MULB| BOARD_DIVB;
-    __writeMemory32(0x207C3F0C,0xFFFFFC2C,"Memory");
-    __delay(10); //10000    
-//*   AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
-    __writeMemory32(0x00000102,0xFFFFFC30,"Memory");
-     __delay(10); //10000
-
-}
-