support milkv-duo rt-smart

1. switches memory management to SLA

2. use ioremap modification driver

Signed-off-by: flyingcys [email protected]

7 files changed, 273 insertions, 236 deletions

diff --git a/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h
index 0e5c3c911c..8d0b45dfa8 100755
--- a/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h
+++ b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h
@@ -10,6 +10,7 @@
 
 #include "cv180x_pinlist_swconfig.h"
 #include "cv180x_reg_fmux_gpio.h"
+#include "drv_ioremap.h"
 
 #define  PAD_MIPI_TXM4__MIPI_TXM4 0
 #define  PAD_MIPI_TXP4__MIPI_TXP4 0
@@ -22,7 +23,8 @@
 #define  PAD_MIPI_TXM0__MIPI_TXM0 0
 #define  PAD_MIPI_TXP0__MIPI_TXP0 0
 
-#define PINMUX_BASE 0x03001000
+#define PINMUX_BASE (uintptr_t)DRV_IOREMAP((void *)0x3001000, 0x1000)
+
 #define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
 #define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
 #define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
diff --git a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h
index 7bec2f2dfb..262704c680 100644
--- a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h
+++ b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h
@@ -8,9 +8,9 @@
 #ifndef __PINCTRL_CV181X_H__
 #define __PINCTRL_CV181X_H__
 
-//#include "../core.h"
 #include "cv181x_pinlist_swconfig.h"
 #include "cv181x_reg_fmux_gpio.h"
+#include "drv_ioremap.h"
 
 #define  PAD_MIPI_TXM4__MIPI_TXM4 0
 #define  PAD_MIPI_TXP4__MIPI_TXP4 0
@@ -23,12 +23,8 @@
 #define  PAD_MIPI_TXM0__MIPI_TXM0 0
 #define  PAD_MIPI_TXP0__MIPI_TXP0 0
 
-#if defined(ARCH_ARM)
-extern rt_ubase_t pinmux_base_ioremap(void);
-#define PINMUX_BASE pinmux_base_ioremap()
-#else
-#define PINMUX_BASE 0x03001000
-#endif /* defined(ARCH_ARM) */
+#define PINMUX_BASE (uintptr_t)DRV_IOREMAP((void *)0x3001000, 0x1000)
+
 #define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
 #define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
 #define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
diff --git a/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h b/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h
index 4494ac9d7f..9272476052 100644
--- a/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h
+++ b/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h
@@ -28,6 +28,7 @@ extern "C" {
 
 #include <stdint.h>
 #include "mmio.h"
+#include "drv_ioremap.h"
 
 /**
 \brief Ethernet link speed
@@ -200,8 +201,8 @@ typedef enum eth_link_state
 /* 1000BASE-T Control register */
 #define CVI_ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
 #define CVI_ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */
-#define CTL1000_AS_MASTER       0x0800
-#define CTL1000_ENABLE_MASTER   0x1000
+#define CTL1000_AS_MASTER           0x0800
+#define CTL1000_ENABLE_MASTER       0x1000
 
 /* 1000BASE-T Status register */
 #define CVI_LPA_1000LOCALRXOK   0x2000  /* Link partner local receiver status */
@@ -210,8 +211,8 @@ typedef enum eth_link_state
 #define CVI_LPA_1000HALF        0x0400  /* Link partner 1000BASE-T half duplex */
 
 /* Flow control flags */
-#define CVI_FLOW_CTRL_TX    0x01
-#define CVI_FLOW_CTRL_RX    0x02
+#define CVI_FLOW_CTRL_TX        0x01
+#define CVI_FLOW_CTRL_RX        0x02
 
 /* MMD Access Control register fields */
 #define CVI_MII_MMD_CTRL_DEVAD_MASK 0x1f    /* Mask MMD DEVAD*/
@@ -348,13 +349,13 @@ typedef struct {
 } eth_phy_dev_t;
 
 /* ethernet phy config */
-#define ETH_PHY_BASE 0x03009000
-#define ETH_PHY_INIT_MASK 0xFFFFFFF9
-#define ETH_PHY_SHUTDOWN (1 << 1)
-#define ETH_PHY_POWERUP 0xFFFFFFFD
-#define ETH_PHY_RESET 0xFFFFFFFB
-#define ETH_PHY_RESET_N (1 << 2)
-#define ETH_PHY_LED_LOW_ACTIVE (1 << 3)
+#define ETH_PHY_BASE            (uintptr_t)DRV_IOREMAP((void *)0x03009000, 0x1000)
+#define ETH_PHY_INIT_MASK       0xFFFFFFF9
+#define ETH_PHY_SHUTDOWN        (1 << 1)
+#define ETH_PHY_POWERUP         0xFFFFFFFD
+#define ETH_PHY_RESET           0xFFFFFFFB
+#define ETH_PHY_RESET_N         (1 << 2)
+#define ETH_PHY_LED_LOW_ACTIVE  (1 << 3)
 
 int generic_phy_config_aneg(eth_phy_dev_t *dev);
 int generic_phy_restart_aneg(eth_phy_dev_t *dev);
diff --git a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c
index dad7fb3ff3..bbe4c1176a 100644
--- a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c
+++ b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c
@@ -14,10 +14,13 @@
  * limitations under the License.
  */
 #include <rtthread.h>
+#include <mmu.h>
 
 #include "dw_eth_mac.h"
 #include "cache.h"
 #include "string.h"
+#include "drv_ioremap.h"
+
 
 #define roundup(x, y) (                 \
 {                           \
@@ -80,10 +83,15 @@ static void tx_descs_init(eth_mac_handle_t handle)
     struct dmamacdescr *desc_p;
     uint32_t idx;
 
-    for (idx = 0; idx < CVI_CONFIG_TX_DESCR_NUM; idx++) {
+    for (idx = 0; idx < CVI_CONFIG_TX_DESCR_NUM; idx ++) {
         desc_p = &desc_table_p[idx];
+#ifdef RT_USING_SMART
+        desc_p->dmamac_addr = (unsigned long)rt_kmem_v2p((void *)&txbuffs[idx * CVI_CONFIG_ETH_BUFSIZE]);
+        desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[idx + 1]);
+#else
         desc_p->dmamac_addr = (unsigned long)&txbuffs[idx * CVI_CONFIG_ETH_BUFSIZE];
         desc_p->dmamac_next = (unsigned long)&desc_table_p[idx + 1];
+#endif
 
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
         desc_p->txrx_status &= ~(CVI_DESC_TXSTS_TXINT | CVI_DESC_TXSTS_TXLAST |
@@ -101,12 +109,20 @@ static void tx_descs_init(eth_mac_handle_t handle)
     }
 
     /* Correcting the last pointer of the chain */
+    #ifdef RT_USING_SMART
+    desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[0]);
+    #else
     desc_p->dmamac_next = (unsigned long)&desc_table_p[0];
+    #endif
 
     /* Flush all Tx buffer descriptors at once */
     rt_hw_cpu_dcache_clean((void *)priv->tx_mac_descrtable, sizeof(priv->tx_mac_descrtable));
 
-    dma_reg->txdesclistaddr = (unsigned long)&desc_table_p[0];
+#ifdef RT_USING_SMART
+    dma_reg->txdesclistaddr = (rt_ubase_t)rt_kmem_v2p((void *)&desc_table_p[0]);
+#else
+    dma_reg->txdesclistaddr = (reg_type)&desc_table_p[0];
+#endif
 
     priv->tx_currdescnum = 0;
 }
@@ -131,23 +147,34 @@ static void rx_descs_init(eth_mac_handle_t handle)
 
     for (idx = 0; idx < CVI_CONFIG_RX_DESCR_NUM; idx++) {
         desc_p = &desc_table_p[idx];
+#ifdef RT_USING_SMART
+        desc_p->dmamac_addr = (unsigned long)rt_kmem_v2p((void *)&rxbuffs[idx * CVI_CONFIG_ETH_BUFSIZE]);
+        desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[idx + 1]);
+#else
         desc_p->dmamac_addr = (unsigned long)&rxbuffs[idx * CVI_CONFIG_ETH_BUFSIZE];
         desc_p->dmamac_next = (unsigned long)&desc_table_p[idx + 1];
+#endif
 
-        desc_p->dmamac_cntl =
-            (CVI_MAC_MAX_FRAME_SZ & CVI_DESC_RXCTRL_SIZE1MASK) |
-                      CVI_DESC_RXCTRL_RXCHAIN;
+        desc_p->dmamac_cntl = (CVI_MAC_MAX_FRAME_SZ & CVI_DESC_RXCTRL_SIZE1MASK) | CVI_DESC_RXCTRL_RXCHAIN;
 
         desc_p->txrx_status = CVI_DESC_RXSTS_OWNBYDMA;
     }
 
     /* Correcting the last pointer of the chain */
+#ifdef RT_USING_SMART
+    desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[0]);
+#else
     desc_p->dmamac_next = (unsigned long)&desc_table_p[0];
+#endif
 
     /* Flush all Rx buffer descriptors at once */
     rt_hw_cpu_dcache_clean((void *)priv->rx_mac_descrtable, sizeof(priv->rx_mac_descrtable));
 
-    dma_reg->rxdesclistaddr = (unsigned long)&desc_table_p[0];
+#ifdef RT_USING_SMART
+    dma_reg->rxdesclistaddr = (rt_ubase_t)rt_kmem_v2p((void *)&desc_table_p[0]);
+#else
+    dma_reg->rxdesclistaddr = (reg_type)&desc_table_p[0];
+#endif
 
     priv->rx_currdescnum = 0;
 }
@@ -318,7 +345,7 @@ static int32_t designware_eth_send(eth_mac_handle_t handle, const uint8_t *frame
     struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
     uint64_t desc_start = (uint64_t)desc_p;
     uint64_t desc_end = desc_start + roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN);
-    uint64_t data_start = desc_p->dmamac_addr;
+    uint64_t data_start = (uint64_t)DRV_IOREMAP((void *)desc_p->dmamac_addr, 0x1000);
     uint64_t data_end = data_start + roundup(length, DW_GMAC_DMA_ALIGN);
     uint32_t count = 0;
 
@@ -332,12 +359,16 @@ static int32_t designware_eth_send(eth_mac_handle_t handle, const uint8_t *frame
      */
 
     /* Check if the descriptor is owned by CPU */
-    while (1) {
+    while (1)
+    {
         rt_hw_cpu_dcache_invalidate((void *)desc_start, desc_end - desc_start);
-        if (!(desc_p->txrx_status & CVI_DESC_TXSTS_OWNBYDMA)) {
+        if (!(desc_p->txrx_status & CVI_DESC_TXSTS_OWNBYDMA))
+        {
             break;
         }
-        if (count > 1000) {
+
+        if (count > 1000)
+        {
             rt_kprintf("desc onwer is DMA\n");
             return -1;
         }
@@ -390,22 +421,23 @@ static int32_t designware_eth_recv(eth_mac_handle_t handle, uint8_t **packetp)
     struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
     int32_t length = -1;
     uint64_t desc_start = (uint64_t)desc_p;
-    uint64_t desc_end = desc_start +
-        roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN);
-    uint64_t data_start = desc_p->dmamac_addr;
+    uint64_t desc_end = desc_start + roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN);
+    uint64_t data_start = (uint64_t)DRV_IOREMAP((void *)desc_p->dmamac_addr, 0x1000);
     uint64_t data_end;
 
     /* Invalidate entire buffer descriptor */
     rt_hw_cpu_dcache_invalidate((void *)desc_start, desc_end - desc_start);
     status = desc_p->txrx_status;
     /* Check  if the owner is the CPU */
-    if (!(status & CVI_DESC_RXSTS_OWNBYDMA)) {
-        length = (status & CVI_DESC_RXSTS_FRMLENMSK) >>
-             CVI_DESC_RXSTS_FRMLENSHFT;
+    if (!(status & CVI_DESC_RXSTS_OWNBYDMA))
+    {
+        length = (status & CVI_DESC_RXSTS_FRMLENMSK) >> CVI_DESC_RXSTS_FRMLENSHFT;
+
         /* Invalidate received data */
         data_end = data_start + roundup(length, DW_GMAC_DMA_ALIGN);
+
         rt_hw_cpu_dcache_invalidate((void *)data_start, data_end - data_start);
-        *packetp = (uint8_t *)((uint64_t)desc_p->dmamac_addr);
+        *packetp = (uint8_t *)data_start;
     }
 
     return length;
@@ -418,8 +450,7 @@ static int32_t designware_free_pkt(eth_mac_handle_t handle)
     uint32_t desc_num = priv->rx_currdescnum;
     struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
     uint64_t desc_start = (uint64_t)desc_p;
-    uint64_t desc_end = desc_start +
-        roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN);
+    uint64_t desc_end = desc_start + roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN);
 
     /*
      * Make the current descriptor valid again and go to
@@ -471,14 +502,15 @@ int32_t dw_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t r
     uint16_t miiaddr;
     int32_t start;
 
-    miiaddr = ((phy_addr << CVI_MIIADDRSHIFT) & CVI_MII_ADDRMSK) |
-          ((reg_addr << CVI_MIIREGSHIFT) & CVI_MII_REGMSK);
+    miiaddr = ((phy_addr << CVI_MIIADDRSHIFT) & CVI_MII_ADDRMSK) | ((reg_addr << CVI_MIIREGSHIFT) & CVI_MII_REGMSK);
 
     mac_reg->miiaddr = (miiaddr | CVI_MII_CLKRANGE_150_250M | CVI_MII_BUSY);
 
     start = rt_tick_get_millisecond();
-    while ((rt_tick_get_millisecond() - start) < CVI_CONFIG_MDIO_TIMEOUT) {
-        if (!(mac_reg->miiaddr & CVI_MII_BUSY)) {
+    while ((rt_tick_get_millisecond() - start) < CVI_CONFIG_MDIO_TIMEOUT)
+    {
+        if (!(mac_reg->miiaddr & CVI_MII_BUSY))
+        {
             *data = mac_reg->miidata;
             return 0;
         }
@@ -684,14 +716,12 @@ int32_t cvi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t
   \param[in]   cb  callback to handle ethernet event
   \return      return ethernet handle if success
  */
-eth_mac_handle_t cvi_eth_mac_init(unsigned int *base)
+eth_mac_handle_t cvi_eth_mac_init(rt_ubase_t base)
 {
     gmac_dev_t *mac_dev = &gmac_instance[0];
     struct dw_gmac_priv *priv, *priv_unalign;
 
-    mac_dev->base = (unsigned long)base;
-    // mac_dev->irq = (uint8_t)DW_MAC_IRQ;
-    // mac_dev->cb_event = cb_event;
+    mac_dev->base = base;
 
     priv = memalign(DW_GMAC_DMA_ALIGN, sizeof(struct dw_gmac_priv), (void **)&priv_unalign);
     if (!priv)
diff --git a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h
index 275159ea9f..2f361ea78b 100644
--- a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h
+++ b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h
@@ -37,23 +37,20 @@ typedef void *eth_mac_handle_t;
 #define DRV_ETH_MAC_ADJUST_LINK         (0x07)      ///< Adjust MAC link state according to phy state; arg: phy handle
 #define DRV_ETH_MAC_CONTROL_IRQ         (0x08)      ///< Interrupt request; arg: 0=disable, 1=enable
 
-#define DW_GMAC_DMA_ALIGN 128
+#define DW_GMAC_DMA_ALIGN               128
 
 #ifndef _DW_ETH_H
 #define _DW_ETH_H
 
-#define GMAC_NULL_PARAM_CHK(para)   CSI_PARAM_CHK(para, -1)
-#define GMAC_NULL_PARAM_CHK_NORETVAL(para)   CSI_PARAM_CHK_NORETVAL(para)
-
-#define CVI_CONFIG_SYS_HZ 1000
-#define CVI_CONFIG_TX_DESCR_NUM 16
-#define CVI_CONFIG_RX_DESCR_NUM 16
-#define CVI_CONFIG_ETH_BUFSIZE  2048
-#define CVI_TX_TOTAL_BUFSIZE    (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_TX_DESCR_NUM)
-#define CVI_RX_TOTAL_BUFSIZE    (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_RX_DESCR_NUM)
+#define CVI_CONFIG_SYS_HZ               1000
+#define CVI_CONFIG_TX_DESCR_NUM         16
+#define CVI_CONFIG_RX_DESCR_NUM         16
+#define CVI_CONFIG_ETH_BUFSIZE          2048
+#define CVI_TX_TOTAL_BUFSIZE            (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_TX_DESCR_NUM)
+#define CVI_RX_TOTAL_BUFSIZE            (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_RX_DESCR_NUM)
 
 #define CVI_CONFIG_MACRESET_TIMEOUT (3 * CVI_CONFIG_SYS_HZ)
-#define CVI_CONFIG_MDIO_TIMEOUT (3 * CVI_CONFIG_SYS_HZ)
+#define CVI_CONFIG_MDIO_TIMEOUT     (3 * CVI_CONFIG_SYS_HZ)
 
 struct dw_gmac_mac_regs {
     volatile uint32_t conf;     /* 0x00 */
@@ -97,7 +94,8 @@ struct dw_gmac_mac_regs {
 #define CVI_MII_ADDRMSK     (0x1F << 11)
 
 typedef uint32_t  reg_type;
-struct dw_gmac_dma_regs {
+struct dw_gmac_dma_regs
+{
     volatile reg_type busmode;      /* 0x00 */
     volatile reg_type txpolldemand; /* 0x04 */
     volatile reg_type rxpolldemand; /* 0x08 */
@@ -118,10 +116,10 @@ struct dw_gmac_dma_regs {
 };
 
 /* Operation mode definitions */
-#define CVI_RXSTART         (1 << 1)
+#define CVI_RXSTART             (1 << 1)
 #define CVI_TXSECONDFRAME       (1 << 2)
-#define CVI_TXSTART         (1 << 13)
-#define CVI_FLUSHTXFIFO     (1 << 20)
+#define CVI_TXSTART             (1 << 13)
+#define CVI_FLUSHTXFIFO         (1 << 20)
 #define CVI_STOREFORWARD        (1 << 21)
 #define CVI_DW_DMA_BASE_OFFSET  (0x1000)
 
@@ -152,7 +150,8 @@ struct dw_gmac_dma_regs {
 /* Descriptior related definitions */
 #define CVI_MAC_MAX_FRAME_SZ    (1600)
 
-struct dmamacdescr {
+struct dmamacdescr
+{
     unsigned int txrx_status;
     unsigned int dmamac_cntl;
     unsigned int dmamac_addr;
@@ -166,46 +165,46 @@ struct dmamacdescr {
 /* tx status bits definitions */
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 
-#define CVI_DESC_TXSTS_OWNBYDMA     (1 << 31)
-#define CVI_DESC_TXSTS_TXINT        (1 << 30)
-#define CVI_DESC_TXSTS_TXLAST       (1 << 29)
-#define CVI_DESC_TXSTS_TXFIRST      (1 << 28)
-#define CVI_DESC_TXSTS_TXCRCDIS     (1 << 27)
+#define CVI_DESC_TXSTS_OWNBYDMA         (1 << 31)
+#define CVI_DESC_TXSTS_TXINT            (1 << 30)
+#define CVI_DESC_TXSTS_TXLAST           (1 << 29)
+#define CVI_DESC_TXSTS_TXFIRST          (1 << 28)
+#define CVI_DESC_TXSTS_TXCRCDIS         (1 << 27)
 
-#define CVI_DESC_TXSTS_TXPADDIS     (1 << 26)
+#define CVI_DESC_TXSTS_TXPADDIS         (1 << 26)
 #define CVI_DESC_TXSTS_TXCHECKINSCTRL   (3 << 22)
 #define CVI_DESC_TXSTS_TXRINGEND        (1 << 21)
-#define CVI_DESC_TXSTS_TXCHAIN      (1 << 20)
-#define CVI_DESC_TXSTS_MSK          (0x1FFFF << 0)
+#define CVI_DESC_TXSTS_TXCHAIN          (1 << 20)
+#define CVI_DESC_TXSTS_MSK              (0x1FFFF << 0)
 
 #else
 
-#define CVI_DESC_TXSTS_OWNBYDMA     (1 << 31)
-#define CVI_DESC_TXSTS_MSK          (0x1FFFF << 0)
+#define CVI_DESC_TXSTS_OWNBYDMA         (1 << 31)
+#define CVI_DESC_TXSTS_MSK              (0x1FFFF << 0)
 
 #endif
 
 /* rx status bits definitions */
-#define CVI_DESC_RXSTS_OWNBYDMA     (1 << 31)
+#define CVI_DESC_RXSTS_OWNBYDMA         (1 << 31)
 #define CVI_DESC_RXSTS_DAFILTERFAIL     (1 << 30)
 #define CVI_DESC_RXSTS_FRMLENMSK        (0x3FFF << 16)
 #define CVI_DESC_RXSTS_FRMLENSHFT       (16)
 
-#define CVI_DESC_RXSTS_ERROR        (1 << 15)
+#define CVI_DESC_RXSTS_ERROR            (1 << 15)
 #define CVI_DESC_RXSTS_RXTRUNCATED      (1 << 14)
 #define CVI_DESC_RXSTS_SAFILTERFAIL     (1 << 13)
 #define CVI_DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
 #define CVI_DESC_RXSTS_RXDAMAGED        (1 << 11)
 #define CVI_DESC_RXSTS_RXVLANTAG        (1 << 10)
-#define CVI_DESC_RXSTS_RXFIRST      (1 << 9)
-#define CVI_DESC_RXSTS_RXLAST       (1 << 8)
+#define CVI_DESC_RXSTS_RXFIRST          (1 << 9)
+#define CVI_DESC_RXSTS_RXLAST           (1 << 8)
 #define CVI_DESC_RXSTS_RXIPC_GIANT      (1 << 7)
 #define CVI_DESC_RXSTS_RXCOLLISION      (1 << 6)
 #define CVI_DESC_RXSTS_RXFRAMEETHER     (1 << 5)
 #define CVI_DESC_RXSTS_RXWATCHDOG       (1 << 4)
 #define CVI_DESC_RXSTS_RXMIIERROR       (1 << 3)
 #define CVI_DESC_RXSTS_RXDRIBBLING      (1 << 2)
-#define CVI_DESC_RXSTS_RXCRC        (1 << 1)
+#define CVI_DESC_RXSTS_RXCRC            (1 << 1)
 
 /*
  * dmamac_cntl definitions
@@ -221,13 +220,13 @@ struct dmamacdescr {
 
 #else
 
-#define CVI_DESC_TXCTRL_TXINT       (1 << 31)
-#define CVI_DESC_TXCTRL_TXLAST      (1 << 30)
-#define CVI_DESC_TXCTRL_TXFIRST     (1 << 29)
+#define CVI_DESC_TXCTRL_TXINT           (1 << 31)
+#define CVI_DESC_TXCTRL_TXLAST          (1 << 30)
+#define CVI_DESC_TXCTRL_TXFIRST         (1 << 29)
 #define CVI_DESC_TXCTRL_TXCHECKINSCTRL  (3 << 27)
 #define CVI_DESC_TXCTRL_TXCRCDIS        (1 << 26)
 #define CVI_DESC_TXCTRL_TXRINGEND       (1 << 25)
-#define CVI_DESC_TXCTRL_TXCHAIN     (1 << 24)
+#define CVI_DESC_TXCTRL_TXCHAIN         (1 << 24)
 
 #define CVI_DESC_TXCTRL_SIZE1MASK       (0x7FF << 0)
 #define CVI_DESC_TXCTRL_SIZE1SHFT       (0)
@@ -241,7 +240,7 @@ struct dmamacdescr {
 
 #define CVI_DESC_RXCTRL_RXINTDIS        (1 << 31)
 #define CVI_DESC_RXCTRL_RXRINGEND       (1 << 15)
-#define CVI_DESC_RXCTRL_RXCHAIN     (1 << 14)
+#define CVI_DESC_RXCTRL_RXCHAIN         (1 << 14)
 
 #define CVI_DESC_RXCTRL_SIZE1MASK       (0x1FFF << 0)
 #define CVI_DESC_RXCTRL_SIZE1SHFT       (0)
@@ -252,7 +251,7 @@ struct dmamacdescr {
 
 #define CVI_DESC_RXCTRL_RXINTDIS        (1 << 31)
 #define CVI_DESC_RXCTRL_RXRINGEND       (1 << 25)
-#define CVI_DESC_RXCTRL_RXCHAIN     (1 << 24)
+#define CVI_DESC_RXCTRL_RXCHAIN         (1 << 24)
 
 #define CVI_DESC_RXCTRL_SIZE1MASK       (0x7FF << 0)
 #define CVI_DESC_RXCTRL_SIZE1SHFT       (0)
@@ -261,7 +260,8 @@ struct dmamacdescr {
 
 #endif
 
-struct dw_gmac_priv {
+struct dw_gmac_priv
+{
     struct dmamacdescr tx_mac_descrtable[CVI_CONFIG_TX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN);
     struct dmamacdescr rx_mac_descrtable[CVI_CONFIG_RX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN);
     char txbuffs[CVI_TX_TOTAL_BUFSIZE] __aligned(DW_GMAC_DMA_ALIGN);
@@ -274,8 +274,6 @@ struct dw_gmac_priv {
 
     struct dw_gmac_mac_regs *mac_regs_p;
     struct dw_gmac_dma_regs *dma_regs_p;
-
-    //struct gpio_desc reset_gpio;
 };
 
 #ifdef CONFIG_DM_ETH
@@ -283,7 +281,8 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev);
 int designware_eth_probe(struct udevice *dev);
 extern const struct eth_ops designware_eth_ops;
 
-struct dw_eth_pdata {
+struct dw_eth_pdata
+{
     struct eth_pdata eth_pdata;
     u32 reset_delays[3];
 };
@@ -300,12 +299,11 @@ int designware_eth_write_hwaddr(struct udevice *dev);
 
 #endif
 
-typedef struct {
-    // csi_dev_t            dev;
+typedef struct
+{
     eth_phy_dev_t       *phy_dev;
-    unsigned long       base;
+    rt_ubase_t          base;
     uint8_t             irq;
-    // eth_event_cb_t      cb_event;
     uint8_t             mac_addr[6];
     struct dw_gmac_priv *priv_unalign;
     struct dw_gmac_priv *priv;
@@ -314,7 +312,8 @@ typedef struct {
 /**
 \brief Ethernet MAC Address
 */
-typedef struct eth_mac_addr {
+typedef struct eth_mac_addr
+{
   uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first
 } eth_mac_addr_t;
 
@@ -415,7 +414,7 @@ int32_t cvi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t
   \param[in]   cb  callback to handle ethernet event
   \return      return ethernet handle if success
  */
-eth_mac_handle_t cvi_eth_mac_init(unsigned int *base);
+eth_mac_handle_t cvi_eth_mac_init(rt_ubase_t base);
 
 #ifdef __cplusplus
 }
diff --git a/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c b/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c
index 0d6383b006..898eab808f 100644
--- a/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c
+++ b/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c
@@ -20,6 +20,7 @@
 
 #include "cvi_eth_phy.h"
 #include "mii.h"
+#include "drv_pinmux.h"
 
 // #define CVI_ETH_PHY_LOOPBACK
 #define LOOPBACK_XMII2MAC       0x8000
@@ -27,10 +28,11 @@
 #define LOOPBACK_PMA2MAC        0x1000
 #define LOOPBACK_RMII2PHY       0x0080
 
-#define EPHY_EFUSE_VALID_BIT_BASE 0x03050120
-#define EPHY_EFUSE_TXECHORC_FLAG 0x00000100 // bit 8
-#define EPHY_EFUSE_TXITUNE_FLAG 0x00000200 // bit 9
-#define EPHY_EFUSE_TXRXTERM_FLAG 0x00000800 // bit 11
+#define CVITEK_EFUSE_BASE           (uintptr_t)DRV_IOREMAP((void *)0x03050000, 0x2000)
+#define EPHY_EFUSE_VALID_BIT_BASE   (CVITEK_EFUSE_BASE + 0x120)
+#define EPHY_EFUSE_TXECHORC_FLAG    0x00000100 // bit 8
+#define EPHY_EFUSE_TXITUNE_FLAG     0x00000200 // bit 9
+#define EPHY_EFUSE_TXRXTERM_FLAG    0x00000800 // bit 11
 
 static inline bool phy_if_mode_is_rgmii(phy_if_mode_t interface)
 {
@@ -59,236 +61,242 @@ int32_t cv181x_config(eth_phy_handle_t handle)
     // eth_phy_reset(dev);
 
     // set rg_ephy_apb_rw_sel 0x0804@[0]=1/APB by using APB interface
-    mmio_write_32(0x03009804, 0x0001);
+    mmio_write_32(ETH_PHY_BASE + 0x804, 0x0001);
 
     // Release 0x0800[0]=0/shutdown
-    // mmio_write_32(0x03009800, 0x0900);
+    // mmio_write_32(ETH_PHY_BASE + 0x800, 0x0900);
 
     // Release 0x0800[2]=1/dig_rst_n, Let mii_reg can be accessabile
-    // mmio_write_32(0x03009800, 0x0904);
+    // mmio_write_32(ETH_PHY_BASE + 0x800, 0x0904);
 
     //mdelay(10);
 
     // ANA INIT (PD/EN), switch to MII-page5
-    mmio_write_32(0x0300907c, 0x0500);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500);
+
     // Release ANA_PD p5.0x10@[13:8] = 6'b001100
-    mmio_write_32(0x03009040, 0x0c00);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c00);
+
     // Release ANA_EN p5.0x10@[7:0] = 8'b01111110
-    mmio_write_32(0x03009040, 0x0c7e);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c7e);
 
     // Wait PLL_Lock, Lock_Status p5.0x12@[15] = 1
     //mdelay(1);
 
     // Release 0x0800[1] = 1/ana_rst_n
-    mmio_write_32(0x03009800, 0x0906);
+    mmio_write_32(ETH_PHY_BASE + 0x800, 0x0906);
 
     // ANA INIT
     // @Switch to MII-page5
-    mmio_write_32(0x0300907c, 0x0500);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500);
 
 // Efuse register
     // Set Double Bias Current
     //Set rg_eth_txitune1  0x03009064 [15:8]
     //Set rg_eth_txitune0  0x03009064 [7:0]
-    if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXITUNE_FLAG) ==
-        EPHY_EFUSE_TXITUNE_FLAG) {
-        val = ((mmio_read_32(0x03051024) >> 24) & 0xFF) |
-                (((mmio_read_32(0x03051024) >> 16) & 0xFF) << 8);
-        mmio_clrsetbits_32(0x03009064, 0xFFFF, val);
-    } else
-        mmio_write_32(0x03009064, 0x5a5a);
+    if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXITUNE_FLAG) == EPHY_EFUSE_TXITUNE_FLAG)
+    {
+        val = ((mmio_read_32(CVITEK_EFUSE_BASE + 0x1024) >> 24) & 0xFF) | (((mmio_read_32(CVITEK_EFUSE_BASE + 0x1024) >> 16) & 0xFF) << 8);
+        mmio_clrsetbits_32(ETH_PHY_BASE + 0x064, 0xFFFF, val);
+    }
+    else
+        mmio_write_32(ETH_PHY_BASE + 0x064, 0x5a5a);
 
     // Set Echo_I
     // Set rg_eth_txechoiadj 0x03009054  [15:8]
-    if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXECHORC_FLAG) ==
-        EPHY_EFUSE_TXECHORC_FLAG) {
-        mmio_clrsetbits_32(0x03009054, 0xFF00, ((mmio_read_32(0x03051024) >> 8) & 0xFF) << 8);
-    } else
-        mmio_write_32(0x03009054, 0x0000);
+    if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXECHORC_FLAG) == EPHY_EFUSE_TXECHORC_FLAG)
+    {
+        mmio_clrsetbits_32(ETH_PHY_BASE + 0x054, 0xFF00, ((mmio_read_32(CVITEK_EFUSE_BASE + 0x1024) >> 8) & 0xFF) << 8);
+    }
+    else
+        mmio_write_32(ETH_PHY_BASE + 0x054, 0x0000);
 
     //Set TX_Rterm & Echo_RC_Delay
     // Set rg_eth_txrterm_p1  0x03009058 [11:8]
     // Set rg_eth_txrterm     0x03009058  [7:4]
     // Set rg_eth_txechorcadj 0x03009058  [3:0]
-    if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXRXTERM_FLAG) ==
-        EPHY_EFUSE_TXRXTERM_FLAG) {
-        val = (((mmio_read_32(0x03051020) >> 28) & 0xF) << 4) |
-                (((mmio_read_32(0x03051020) >> 24) & 0xF) << 8);
-        mmio_clrsetbits_32(0x03009058, 0xFF0, val);
-    } else
-        mmio_write_32(0x03009058, 0x0bb0);
+    if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXRXTERM_FLAG) == EPHY_EFUSE_TXRXTERM_FLAG)
+    {
+        val = (((mmio_read_32(CVITEK_EFUSE_BASE + 0x1020) >> 28) & 0xF) << 4) | (((mmio_read_32(CVITEK_EFUSE_BASE + 0x1020) >> 24) & 0xF) << 8);
+        mmio_clrsetbits_32(ETH_PHY_BASE + 0x058, 0xFF0, val);
+    }
+    else
+        mmio_write_32(ETH_PHY_BASE + 0x058, 0x0bb0);
 
-// ETH_100BaseT
+    // ETH_100BaseT
     // Set Rise update
-    mmio_write_32(0x0300905c, 0x0c10);
+    mmio_write_32(ETH_PHY_BASE + 0x05c, 0x0c10);
 
     // Set Falling phase
-    mmio_write_32(0x03009068, 0x0003);
+    mmio_write_32(ETH_PHY_BASE + 0x068, 0x0003);
 
     // Set Double TX Bias Current
-    mmio_write_32(0x03009054, 0x0000);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0x0000);
 
     // Switch to MII-page16
-    mmio_write_32(0x0300907c, 0x1000);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1000);
 
     // Set MLT3 Positive phase code, Set MLT3 +0
-    mmio_write_32(0x03009068, 0x1000);
-    mmio_write_32(0x0300906c, 0x3020);
-    mmio_write_32(0x03009070, 0x5040);
-    mmio_write_32(0x03009074, 0x7060);
+    mmio_write_32(ETH_PHY_BASE + 0x068, 0x1000);
+    mmio_write_32(ETH_PHY_BASE + 0x06c, 0x3020);
+    mmio_write_32(ETH_PHY_BASE + 0x070, 0x5040);
+    mmio_write_32(ETH_PHY_BASE + 0x074, 0x7060);
 
     // Set MLT3 +I
-    mmio_write_32(0x03009058, 0x1708);
-    mmio_write_32(0x0300905c, 0x3827);
-    mmio_write_32(0x03009060, 0x5748);
-    mmio_write_32(0x03009064, 0x7867);
+    mmio_write_32(ETH_PHY_BASE + 0x058, 0x1708);
+    mmio_write_32(ETH_PHY_BASE + 0x05c, 0x3827);
+    mmio_write_32(ETH_PHY_BASE + 0x060, 0x5748);
+    mmio_write_32(ETH_PHY_BASE + 0x064, 0x7867);
 
     // Switch to MII-page17
-    mmio_write_32(0x0300907c, 0x1100);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1100);
 
     // Set MLT3 Negative phase code, Set MLT3 -0
-    mmio_write_32(0x03009040, 0x9080);
-    mmio_write_32(0x03009044, 0xb0a0);
-    mmio_write_32(0x03009048, 0xd0c0);
-    mmio_write_32(0x0300904c, 0xf0e0);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x9080);
+    mmio_write_32(ETH_PHY_BASE + 0x044, 0xb0a0);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0xd0c0);
+    mmio_write_32(ETH_PHY_BASE + 0x04c, 0xf0e0);
 
     // Set MLT3 -I
-    mmio_write_32(0x03009050, 0x9788);
-    mmio_write_32(0x03009054, 0xb8a7);
-    mmio_write_32(0x03009058, 0xd7c8);
-    mmio_write_32(0x0300905c, 0xf8e7);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0x9788);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0xb8a7);
+    mmio_write_32(ETH_PHY_BASE + 0x058, 0xd7c8);
+    mmio_write_32(ETH_PHY_BASE + 0x05c, 0xf8e7);
 
     // @Switch to MII-page5
-    mmio_write_32(0x0300907c, 0x0500);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500);
 
     // En TX_Rterm
-    mmio_write_32(0x03009040, (0x0001 | mmio_read_32(0x03009040)));
+    mmio_write_32(ETH_PHY_BASE + 0x040, (0x0001 | mmio_read_32(ETH_PHY_BASE + 0x040)));
 
 //  Link Pulse
     // Switch to MII-page10
-    mmio_write_32(0x0300907c, 0x0a00);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0a00);
 
     // Set Link Pulse
-    mmio_write_32(0x03009040, 0x2000);
-    mmio_write_32(0x03009044, 0x3832);
-    mmio_write_32(0x03009048, 0x3132);
-    mmio_write_32(0x0300904c, 0x2d2f);
-    mmio_write_32(0x03009050, 0x2c2d);
-    mmio_write_32(0x03009054, 0x1b2b);
-    mmio_write_32(0x03009058, 0x94a0);
-    mmio_write_32(0x0300905c, 0x8990);
-    mmio_write_32(0x03009060, 0x8788);
-    mmio_write_32(0x03009064, 0x8485);
-    mmio_write_32(0x03009068, 0x8283);
-    mmio_write_32(0x0300906c, 0x8182);
-    mmio_write_32(0x03009070, 0x0081);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x2000);
+    mmio_write_32(ETH_PHY_BASE + 0x044, 0x3832);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0x3132);
+    mmio_write_32(ETH_PHY_BASE + 0x04c, 0x2d2f);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0x2c2d);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0x1b2b);
+    mmio_write_32(ETH_PHY_BASE + 0x058, 0x94a0);
+    mmio_write_32(ETH_PHY_BASE + 0x05c, 0x8990);
+    mmio_write_32(ETH_PHY_BASE + 0x060, 0x8788);
+    mmio_write_32(ETH_PHY_BASE + 0x064, 0x8485);
+    mmio_write_32(ETH_PHY_BASE + 0x068, 0x8283);
+    mmio_write_32(ETH_PHY_BASE + 0x06c, 0x8182);
+    mmio_write_32(ETH_PHY_BASE + 0x070, 0x0081);
 
 // TP_IDLE
     // Switch to MII-page11
-    mmio_write_32(0x0300907c, 0x0b00);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0b00);
 
 // Set TP_IDLE
-    mmio_write_32(0x03009040, 0x5252);
-    mmio_write_32(0x03009044, 0x5252);
-    mmio_write_32(0x03009048, 0x4B52);
-    mmio_write_32(0x0300904c, 0x3D47);
-    mmio_write_32(0x03009050, 0xAA99);
-    mmio_write_32(0x03009054, 0x989E);
-    mmio_write_32(0x03009058, 0x9395);
-    mmio_write_32(0x0300905C, 0x9091);
-    mmio_write_32(0x03009060, 0x8E8F);
-    mmio_write_32(0x03009064, 0x8D8E);
-    mmio_write_32(0x03009068, 0x8C8C);
-    mmio_write_32(0x0300906C, 0x8B8B);
-    mmio_write_32(0x03009070, 0x008A);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x5252);
+    mmio_write_32(ETH_PHY_BASE + 0x044, 0x5252);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0x4B52);
+    mmio_write_32(ETH_PHY_BASE + 0x04c, 0x3D47);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0xAA99);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0x989E);
+    mmio_write_32(ETH_PHY_BASE + 0x058, 0x9395);
+    mmio_write_32(ETH_PHY_BASE + 0x05C, 0x9091);
+    mmio_write_32(ETH_PHY_BASE + 0x060, 0x8E8F);
+    mmio_write_32(ETH_PHY_BASE + 0x064, 0x8D8E);
+    mmio_write_32(ETH_PHY_BASE + 0x068, 0x8C8C);
+    mmio_write_32(ETH_PHY_BASE + 0x06C, 0x8B8B);
+    mmio_write_32(ETH_PHY_BASE + 0x070, 0x008A);
 
 // ETH 10BaseT Data
     // Switch to MII-page13
-    mmio_write_32(0x0300907c, 0x0d00);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0d00);
 
-    mmio_write_32(0x03009040, 0x1E0A);
-    mmio_write_32(0x03009044, 0x3862);
-    mmio_write_32(0x03009048, 0x1E62);
-    mmio_write_32(0x0300904c, 0x2A08);
-    mmio_write_32(0x03009050, 0x244C);
-    mmio_write_32(0x03009054, 0x1A44);
-    mmio_write_32(0x03009058, 0x061C);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x1E0A);
+    mmio_write_32(ETH_PHY_BASE + 0x044, 0x3862);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0x1E62);
+    mmio_write_32(ETH_PHY_BASE + 0x04c, 0x2A08);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0x244C);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0x1A44);
+    mmio_write_32(ETH_PHY_BASE + 0x058, 0x061C);
 
     // Switch to MII-page14
-    mmio_write_32(0x0300907c, 0x0e00);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0e00);
 
-    mmio_write_32(0x03009040, 0x2D30);
-    mmio_write_32(0x03009044, 0x3470);
-    mmio_write_32(0x03009048, 0x0648);
-    mmio_write_32(0x0300904c, 0x261C);
-    mmio_write_32(0x03009050, 0x3160);
-    mmio_write_32(0x03009054, 0x2D5E);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x2D30);
+    mmio_write_32(ETH_PHY_BASE + 0x044, 0x3470);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0x0648);
+    mmio_write_32(ETH_PHY_BASE + 0x04c, 0x261C);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0x3160);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0x2D5E);
 
     // Switch to MII-page15
-    mmio_write_32(0x0300907c, 0x0f00);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0f00);
 
-    mmio_write_32(0x03009040, 0x2922);
-    mmio_write_32(0x03009044, 0x366E);
-    mmio_write_32(0x03009048, 0x0752);
-    mmio_write_32(0x0300904c, 0x2556);
-    mmio_write_32(0x03009050, 0x2348);
-    mmio_write_32(0x03009054, 0x0C30);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x2922);
+    mmio_write_32(ETH_PHY_BASE + 0x044, 0x366E);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0x0752);
+    mmio_write_32(ETH_PHY_BASE + 0x04c, 0x2556);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0x2348);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0x0C30);
 
     // Switch to MII-page16
-    mmio_write_32(0x0300907c, 0x1000);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1000);
 
-    mmio_write_32(0x03009040, 0x1E08);
-    mmio_write_32(0x03009044, 0x3868);
-    mmio_write_32(0x03009048, 0x1462);
-    mmio_write_32(0x0300904c, 0x1A0E);
-    mmio_write_32(0x03009050, 0x305E);
-    mmio_write_32(0x03009054, 0x2F62);
+    mmio_write_32(ETH_PHY_BASE + 0x040, 0x1E08);
+    mmio_write_32(ETH_PHY_BASE + 0x044, 0x3868);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0x1462);
+    mmio_write_32(ETH_PHY_BASE + 0x04c, 0x1A0E);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0x305E);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0x2F62);
 
 // LED PAD MUX
-    mmio_write_32(0x030010e0, 0x05);
-    mmio_write_32(0x030010e4, 0x05);
+    uintptr_t addr = (uintptr_t)DRV_IOREMAP((void *)0x03001000, 0x1000);
+    mmio_write_32((uintptr_t)(addr + 0xe0), 0x05);
+    mmio_write_32((uintptr_t)(addr + 0xe4), 0x05);
+
     //(SD1_CLK selphy)
-    mmio_write_32(0x050270b0, 0x11111111);
+    addr = (uintptr_t)DRV_IOREMAP((void *)0x05027000, 0x1000);
+    mmio_write_32((intptr_t)(addr + 0xb0), 0x11111111);
     //(SD1_CMD selphy)
-    mmio_write_32(0x050270b4, 0x11111111);
+    mmio_write_32((intptr_t)(addr + 0xb4), 0x11111111);
 
 // LED
     // Switch to MII-page1
-    mmio_write_32(0x0300907c, 0x0100);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0100);
 
     // select LED_LNK/SPD/DPX out to LED_PAD
-    mmio_write_32(0x03009068, (mmio_read_32(0x03009068) & ~0x0f00));
+    mmio_write_32(ETH_PHY_BASE + 0x068, (mmio_read_32(ETH_PHY_BASE + 0x068) & ~0x0f00));
 
     // @Switch to MII-page0
-    mmio_write_32(0x0300907c, 0x0000);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0000);
 
     // PHY_ID
-    mmio_write_32(0x03009008, 0x0043);
-    mmio_write_32(0x0300900c, 0x5649);
+    mmio_write_32(ETH_PHY_BASE + 0x008, 0x0043);
+    mmio_write_32(ETH_PHY_BASE + 0x00c, 0x5649);
 
     // Switch to MII-page19
-    mmio_write_32(0x0300907c, 0x1300);
-    mmio_write_32(0x03009058, 0x0012);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1300);
+    mmio_write_32(ETH_PHY_BASE + 0x058, 0x0012);
     // set agc max/min swing
-    mmio_write_32(0x0300905C, 0x6848);
+    mmio_write_32(ETH_PHY_BASE + 0x05C, 0x6848);
 
     // Switch to MII-page18
-    mmio_write_32(0x0300907c, 0x1200);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1200);
     // p18.0x12, lpf
-    mmio_write_32(0x03009048, 0x0808);
-    mmio_write_32(0x0300904C, 0x0808);
+    mmio_write_32(ETH_PHY_BASE + 0x048, 0x0808);
+    mmio_write_32(ETH_PHY_BASE + 0x04C, 0x0808);
 // hpf
 //sean
-    mmio_write_32(0x03009050, 0x32f8);
-    mmio_write_32(0x03009054, 0xf8dc);
+    mmio_write_32(ETH_PHY_BASE + 0x050, 0x32f8);
+    mmio_write_32(ETH_PHY_BASE + 0x054, 0xf8dc);
 
     // Switch to MII-page0
-    mmio_write_32(0x0300907c, 0x0000);
+    mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0000);
     // EPHY start auto-neg procedure
-    mmio_write_32(0x03009800, 0x090e);
+    mmio_write_32(ETH_PHY_BASE + 0x800, 0x090e);
 
     // switch to MDIO control by ETH_MAC
-    mmio_write_32(0x03009804, 0x0000);
+    mmio_write_32(ETH_PHY_BASE + 0x804, 0x0000);
 
     genphy_config(dev);
 
diff --git a/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h b/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h
index 157888c07e..702c82dbdc 100644
--- a/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h
+++ b/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h
@@ -8,6 +8,7 @@
 #include <stdio.h>
 #include <string.h>
 #include <stdbool.h>
+#include "drv_ioremap.h"
 
 #define TOP_BASE        0x03000000
 #define DW_SDIO0_BASE               0x04320000
@@ -58,9 +59,9 @@ static inline int mmc_op_multi(uint32_t opcode)
 #define SDIO0_IRQ           36
 #define SDIO1_IRQ           38
 #define SDIO2_IRQ           34
-#define SDIO0_BASE          DW_SDIO1_BASE
-#define SDIO1_BASE          DW_SDIO0_BASE
-#define SDIO2_BASE          DW_SDIO2_BASE
+#define SDIO0_BASE          DRV_IOREMAP((void *)DW_SDIO1_BASE, 0x1000)
+#define SDIO1_BASE          DRV_IOREMAP((void *)DW_SDIO0_BASE, 0x1000)
+#define SDIO2_BASE          DRV_IOREMAP((void *)DW_SDIO2_BASE, 0x1000)
 
 #define SDIF_DMA_ADDRESS               0x00
 #define SDIF_BLOCK_SIZE                0x04
@@ -271,7 +272,7 @@ static inline int mmc_op_multi(uint32_t opcode)
 #define REG_SDIO0_DAT3_PIO_VALUE    (0x0)
 
 /*SDIO 1 register and bit flag*/
-#define RTCIO_BASE (0x5027000)
+#define RTCIO_BASE                 (uintptr_t)DRV_IOREMAP((void *)0x5027000, 0x1000)
 #define REG_SDIO1_PAD_MASK      (0xFFFFFFF3)
 #define REG_SDIO1_PAD_SHIFT     (2)
 
@@ -311,13 +312,13 @@ static inline int mmc_op_multi(uint32_t opcode)
 #define REG_SDIO1_DAT3_PIO_REG      (PINMUX_BASE + 0xD0)
 #define REG_SDIO1_DAT3_PIO_VALUE    (0x0)
 
-#define RTC_CTRL_BASE       0x5025000
+#define RTC_CTRL_BASE       (uintptr_t)DRV_IOREMAP((void *)0x5025000, 0x1000)
 #define RTCSYS_CLKMUX       (RTC_CTRL_BASE + 0x1C)
 #define RTCSYS_CLKBYP       (RTC_CTRL_BASE + 0x30)
 #define RTCSYS_MCU51_ICTRL1 (RTC_CTRL_BASE + 0x7C)
 
-#define RTCSYS_CTRL_BASE    0x03000000
-#define RTCSYS_CTRL     (RTCSYS_CTRL_BASE + 0x248)
+#define RTCSYS_CTRL_BASE    (uintptr_t)DRV_IOREMAP((void *)0x03000000, 0x1000)
+#define RTCSYS_CTRL         (RTCSYS_CTRL_BASE + 0x248)
 
 /*SDIO 2 register and bit flag*/
 #define REG_SDIO2_PAD_MASK (0xFFFFFFF3)
@@ -365,10 +366,10 @@ static inline int mmc_op_multi(uint32_t opcode)
 #define REG_SDIO2_DAT3_PIO_REG (PINMUX_BASE + 0x58)
 #define REG_SDIO2_DAT3_PIO_VALUE (0x0)
 
-
-#define MMC_SDIO0_PLL_REGISTER 0x3002070
-#define MMC_SDIO1_PLL_REGISTER 0x300207C
-#define MMC_SDIO2_PLL_REGISTER 0x3002064
+#define CLK_DIV_BASE           (uintptr_t)DRV_IOREMAP((void *)0x3002000, 0x1000)
+#define MMC_SDIO0_PLL_REGISTER (CLK_DIV_BASE + 0x70)
+#define MMC_SDIO1_PLL_REGISTER (CLK_DIV_BASE + 0x7C)
+#define MMC_SDIO2_PLL_REGISTER (CLK_DIV_BASE + 0x64)
 #define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
 #define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)