add gd32407v-start

3 files changed, 36 insertions, 70 deletions

diff --git a/bsp/gd32/libraries/HAL_Drivers/Kconfig b/bsp/gd32/libraries/HAL_Drivers/Kconfig
index 41cf5cf08b..93e9ecd88f 100644
--- a/bsp/gd32/libraries/HAL_Drivers/Kconfig
+++ b/bsp/gd32/libraries/HAL_Drivers/Kconfig
@@ -24,39 +24,3 @@ if BSP_USING_USBD
         # "ULPI: UTMI+ Low Pin Interface"
 endif
 
-config BSP_USING_CRC
-    bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
-    select RT_USING_HWCRYPTO
-    select RT_HWCRYPTO_USING_CRC
-    # "Crypto device frame dose not support above 8-bits granularity"
-    # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
-    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
-    default n 
-
-config BSP_USING_RNG
-    bool "Enable RNG (Random Number Generator)"
-    select RT_USING_HWCRYPTO
-    select RT_HWCRYPTO_USING_RNG
-    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
-                SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
-    default n
-
-config BSP_USING_HASH
-    bool "Enable HASH (Hash House Harriers)"
-    select RT_USING_HWCRYPTO
-    select RT_HWCRYPTO_USING_HASH
-    depends on (SOC_SERIES_STM32MP1)
-    default n
-
-config BSP_USING_CRYP
-    bool "Enable CRYP (Encrypt And Decrypt Data)"
-    select RT_USING_HWCRYPTO
-    select RT_HWCRYPTO_USING_CRYP
-    depends on (SOC_SERIES_STM32MP1)
-    default n
-
-config BSP_USING_UDID
-    bool "Enable UDID (Unique Device Identifier)"
-    select RT_USING_HWCRYPTO
-    default n
-
diff --git a/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c b/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c
index 1fc7339643..3ff4282c82 100644
--- a/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/gd32/libraries/HAL_Drivers/drv_gpio.c
@@ -156,7 +156,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     return index;
 };
 
-void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     const struct pin_index *index = RT_NULL;
     rt_uint32_t pin_mode = 0, pin_pupd = 0, pin_odpp = 0;
@@ -211,7 +211,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 {
     const struct pin_index *index = RT_NULL;
 
@@ -224,7 +224,7 @@ void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
 }
 
-int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+static int _pin_read(rt_device_t dev, rt_base_t pin)
 {
     int value = PIN_LOW;
     const struct pin_index *index = RT_NULL;
@@ -262,7 +262,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
     return &pin_irq_map[map_index];
 };
 
-rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
                               rt_uint32_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index = RT_NULL;
@@ -272,13 +272,13 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     index = get_pin(pin);
     if (index == RT_NULL)
     {
-        return RT_EINVAL;
+        return -RT_EINVAL;
     }
 
     hdr_index = bit2bitno(index->pin);
     if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
     {
-        return RT_EINVAL;
+        return -RT_EINVAL;
     }
 
     level = rt_hw_interrupt_disable();
@@ -293,7 +293,7 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     if (pin_irq_hdr_tab[hdr_index].pin != -1)
     {
         rt_hw_interrupt_enable(level);
-        return RT_EFULL;
+        return -RT_EFULL;
     }
     pin_irq_hdr_tab[hdr_index].pin = pin;
     pin_irq_hdr_tab[hdr_index].hdr = hdr;
@@ -304,7 +304,7 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -313,13 +313,13 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     index = get_pin(pin);
     if (index == RT_NULL)
     {
-        return RT_EINVAL;
+        return -RT_EINVAL;
     }
 
     hdr_index = bit2bitno(index->pin);
     if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
     {
-        return RT_EINVAL;
+        return -RT_EINVAL;
     }
 
     level = rt_hw_interrupt_disable();
@@ -337,7 +337,7 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;
@@ -348,7 +348,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
     index = get_pin(pin);
     if (index == RT_NULL)
     {
-        return RT_EINVAL;
+        return -RT_EINVAL;
     }
 
     if (enabled == PIN_IRQ_ENABLE)
@@ -356,14 +356,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
         hdr_index = bit2bitno(index->pin);
         if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
         {
-            return RT_EINVAL;
+            return -RT_EINVAL;
         }
 
         level = rt_hw_interrupt_disable();
         if (pin_irq_hdr_tab[hdr_index].pin == -1)
         {
             rt_hw_interrupt_enable(level);
-            return RT_EINVAL;
+            return -RT_EINVAL;
         }
 
         irqmap = &pin_irq_map[hdr_index];
@@ -381,7 +381,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
                 break;
             default:
                 rt_hw_interrupt_enable(level);
-                return RT_EINVAL;
+                return -RT_EINVAL;
         }
 
         rcu_periph_clock_enable(RCU_SYSCFG);
@@ -403,13 +403,13 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
         irqmap = get_pin_irq_map(index->pin);
         if (irqmap == RT_NULL)
         {
-            return RT_EINVAL;
+            return -RT_EINVAL;
         }
         nvic_irq_disable(irqmap->irqno);
     }
     else
     {
-        return RT_EINVAL;
+        return -RT_EINVAL;
     }
 
     return RT_EOK;
@@ -417,12 +417,12 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
 
 const static struct rt_pin_ops gd32_pin_ops =
 {
-    gd32_pin_mode,
-    gd32_pin_write,
-    gd32_pin_read,
-    gd32_pin_attach_irq,
-    gd32_pin_detach_irq,
-    gd32_pin_irq_enable,
+    _pin_mode,
+    _pin_write,
+    _pin_read,
+    _pin_attach_irq,
+    _pin_detach_irq,
+    _pin_irq_enable,
     RT_NULL,
 };
 
diff --git a/bsp/gd32/libraries/HAL_Drivers/drv_usart.c b/bsp/gd32/libraries/HAL_Drivers/drv_usart.c
index 283eb47de3..54a36d6f73 100644
--- a/bsp/gd32/libraries/HAL_Drivers/drv_usart.c
+++ b/bsp/gd32/libraries/HAL_Drivers/drv_usart.c
@@ -304,7 +304,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
     NVIC_EnableIRQ(uart->irqn);
 }
 
-static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     struct gd32_uart *uart;
 
@@ -358,7 +358,7 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
     return RT_EOK;
 }
 
-static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg)
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
     struct gd32_uart *uart;
 
@@ -385,7 +385,7 @@ static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg
     return RT_EOK;
 }
 
-static int gd32_putc(struct rt_serial_device *serial, char ch)
+static int _uart_putc(struct rt_serial_device *serial, char ch)
 {
     struct gd32_uart *uart;
 
@@ -395,10 +395,10 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
     usart_data_transmit(uart->uart_periph, ch);
     while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
 
-    return 1;
+    return RT_EOK;
 }
 
-static int gd32_getc(struct rt_serial_device *serial)
+static int _uart_getc(struct rt_serial_device *serial)
 {
     int ch;
     struct gd32_uart *uart;
@@ -435,10 +435,10 @@ static void uart_isr(struct rt_serial_device *serial)
 
 static const struct rt_uart_ops gd32_uart_ops =
 {
-    gd32_configure,
-    gd32_control,
-    gd32_putc,
-    gd32_getc,
+    _uart_configure,
+    _uart_control,
+    _uart_putc,
+    _uart_getc,
 };
 
 int gd32_hw_usart_init(void)
@@ -446,6 +446,7 @@ int gd32_hw_usart_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     int i;
 
+      int result;
 
     for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
     {
@@ -453,13 +454,14 @@ int gd32_hw_usart_init(void)
         uarts[i].serial->config = config;
 
         /* register UART1 device */
-        rt_hw_serial_register(uarts[i].serial,
+        result = rt_hw_serial_register(uarts[i].serial,
                               uarts[i].device_name,
                               RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                               (void *)&uarts[i]);
+              RT_ASSERT(result == RT_EOK);
     }
 
-    return 0;
+    return result;
 }
 INIT_BOARD_EXPORT(gd32_hw_usart_init);
 #endif