[lpcxxx] auto formatted

14 files changed, 608 insertions, 581 deletions

diff --git a/bsp/lpc176x/applications/application.c b/bsp/lpc176x/applications/application.c
index 9facb30aa8..173e2df1bb 100644
--- a/bsp/lpc176x/applications/application.c
+++ b/bsp/lpc176x/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,44 +38,44 @@ extern int lwip_system_init(void);
 /* thread phase init */
 void rt_init_thread_entry(void *parameter)
 {
-	/* initialize platform */
-	platform_init();
+    /* initialize platform */
+    platform_init();
 
 #ifdef RT_USING_LWIP
     /* register Ethernet interface device */
     lpc17xx_emac_hw_init();
 
     /* initialize lwip stack */
-	/* register ethernetif device */
-	eth_system_device_init();
+    /* register ethernetif device */
+    eth_system_device_init();
 
-	/* initialize lwip system */
-	lwip_system_init();
-	rt_kprintf("TCP/IP initialized!\n");
+    /* initialize lwip system */
+    lwip_system_init();
+    rt_kprintf("TCP/IP initialized!\n");
 #endif
 
     /* Filesystem Initialization */
 #ifdef RT_USING_DFS
     rt_hw_sdcard_init();
 
-	/* initialize the device file system */
-	dfs_init();
+    /* initialize the device file system */
+    dfs_init();
 
 #ifdef RT_USING_DFS_ELMFAT
-	/* initialize the elm chan FatFS file system*/
-	elm_init();
+    /* initialize the elm chan FatFS file system*/
+    elm_init();
 #endif
 
     /* mount sd card fat partition 1 as root directory */
     if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-    	rt_kprintf("File System initialized!\n");
+        rt_kprintf("File System initialized!\n");
     else
-    	rt_kprintf("File System init failed!\n");
+        rt_kprintf("File System init failed!\n");
 #endif
 
 #ifdef RT_USING_FINSH
-	/* initialize finsh */
-	finsh_system_init();
+    /* initialize finsh */
+    finsh_system_init();
 #endif
 }
 
@@ -84,8 +84,8 @@ int rt_application_init()
     rt_thread_t tid;
 
     tid = rt_thread_create("init",
-    		rt_init_thread_entry, RT_NULL,
-    		2048, RT_THREAD_PRIORITY_MAX/3, 20);
+            rt_init_thread_entry, RT_NULL,
+            2048, RT_THREAD_PRIORITY_MAX/3, 20);
     if (tid != RT_NULL) rt_thread_startup(tid);
 
     return 0;
diff --git a/bsp/lpc176x/applications/platform.c b/bsp/lpc176x/applications/platform.c
index 4bab858aa4..05ff436e8d 100644
--- a/bsp/lpc176x/applications/platform.c
+++ b/bsp/lpc176x/applications/platform.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ static struct rt_memheap _memheap;
 void platform_init(void)
 {
 #ifdef RT_USING_MEMHEAP
-	/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
+    /* create memory heap object on 0x2007 C000 - 0x2008 4000*/
 #ifdef RT_USING_LWIP
-	rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
+    rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
 #else
-	rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
+    rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
 #endif
 #endif
 }
diff --git a/bsp/lpc176x/applications/platform.h b/bsp/lpc176x/applications/platform.h
index e52e4066c2..25a97d8666 100644
--- a/bsp/lpc176x/applications/platform.h
+++ b/bsp/lpc176x/applications/platform.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc176x/applications/startup.c b/bsp/lpc176x/applications/startup.c
index 63d5b0f9a5..b9db54c429 100644
--- a/bsp/lpc176x/applications/startup.c
+++ b/bsp/lpc176x/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,28 +33,28 @@ extern int __bss_end;
  */
 void rtthread_startup(void)
 {
-	/* initialize board */
-	rt_hw_board_init();
+    /* initialize board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
 #ifdef RT_USING_HEAP
-	/* initialize memory system */
-	#ifdef __CC_ARM
-		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
-	#elif __ICCARM__
-	    rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
-	#else
-		rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
-	#endif
+    /* initialize memory system */
+    #ifdef __CC_ARM
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
+    #elif __ICCARM__
+        rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
+    #else
+        rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
+    #endif
 #endif
 
-	/* initialize scheduler system */
-	rt_system_scheduler_init();
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
 
-	/* initialize application */
-	rt_application_init();
+    /* initialize application */
+    rt_application_init();
 
     /* initialize timer */
     rt_system_timer_init();
@@ -62,25 +62,25 @@ void rtthread_startup(void)
     /* initialize timer thread */
     rt_system_timer_thread_init();
 
-	/* initialize idle thread */
-	rt_thread_idle_init();
+    /* initialize idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/lpc176x/drivers/board.c b/bsp/lpc176x/drivers/board.c
index c636462a2e..de3e476d55 100644
--- a/bsp/lpc176x/drivers/board.c
+++ b/bsp/lpc176x/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,13 +29,13 @@
  */
 void rt_hw_timer_handler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
-	rt_tick_increase();
+    rt_tick_increase();
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 
 void SysTick_Handler(void)
@@ -48,24 +48,24 @@ void SysTick_Handler(void)
  */
 void rt_hw_board_init()
 {
-	/* NVIC Configuration */
+    /* NVIC Configuration */
 #define NVIC_VTOR_MASK              0x3FFFFF80
 #ifdef  VECT_TAB_RAM
-	/* Set the Vector Table base location at 0x10000000 */
-	SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+    /* Set the Vector Table base location at 0x10000000 */
+    SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
 #else  /* VECT_TAB_FLASH  */
-	/* Set the Vector Table base location at 0x00000000 */
-	SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
+    /* Set the Vector Table base location at 0x00000000 */
+    SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
 #endif
 
-	/* initialize systick */
-	SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
-	/* set pend exception priority */
-	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+    /* initialize systick */
+    SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
 
 #ifdef RT_USING_UART0
-	rt_hw_uart_init();
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 }
 
diff --git a/bsp/lpc176x/drivers/board.h b/bsp/lpc176x/drivers/board.h
index 951a2c4cda..1e51e87615 100644
--- a/bsp/lpc176x/drivers/board.h
+++ b/bsp/lpc176x/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc176x/drivers/emac.c b/bsp/lpc176x/drivers/emac.c
index 27fc55397a..e4f0363626 100644
--- a/bsp/lpc176x/drivers/emac.c
+++ b/bsp/lpc176x/drivers/emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,20 +11,20 @@
 #include "lwipopts.h"
 #include <netif/ethernetif.h>
 
-#define EMAC_PHY_AUTO		0
-#define EMAC_PHY_10MBIT		1
-#define EMAC_PHY_100MBIT	2
+#define EMAC_PHY_AUTO       0
+#define EMAC_PHY_10MBIT     1
+#define EMAC_PHY_100MBIT    2
 
 #define MAX_ADDR_LEN 6
 struct lpc17xx_emac
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
-	rt_uint8_t phy_mode;
+    rt_uint8_t phy_mode;
 
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 };
 static struct lpc17xx_emac lpc17xx_emac_device;
 static struct rt_semaphore sem_lock;
@@ -36,40 +36,40 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
 
 void ENET_IRQHandler(void)
 {
-	rt_uint32_t status;
+    rt_uint32_t status;
 
     /* enter interrupt */
     rt_interrupt_enter();
 
-	status = LPC_EMAC->IntStatus;
+    status = LPC_EMAC->IntStatus;
 
-	if (status & INT_RX_DONE)
-	{
-		/* Disable EMAC RxDone interrupts. */
-		LPC_EMAC->IntEnable = INT_TX_DONE;
+    if (status & INT_RX_DONE)
+    {
+        /* Disable EMAC RxDone interrupts. */
+        LPC_EMAC->IntEnable = INT_TX_DONE;
 
-		/* a frame has been received */
-		eth_device_ready(&(lpc17xx_emac_device.parent));
-	}
-	else if (status & INT_TX_DONE)
-	{
-		/* set event */
-		rt_event_send(&tx_event, 0x01);
-	}
+        /* a frame has been received */
+        eth_device_ready(&(lpc17xx_emac_device.parent));
+    }
+    else if (status & INT_TX_DONE)
+    {
+        /* set event */
+        rt_event_send(&tx_event, 0x01);
+    }
 
-	if (status & INT_RX_OVERRUN)
-	{
-		rt_kprintf("rx overrun\n");
-	}
+    if (status & INT_RX_OVERRUN)
+    {
+        rt_kprintf("rx overrun\n");
+    }
 
-	if (status & INT_TX_UNDERRUN)
-	{
-		rt_kprintf("tx underrun\n");
-	}
+    if (status & INT_TX_UNDERRUN)
+    {
+        rt_kprintf("tx underrun\n");
+    }
+
+    /* Clear the interrupt. */
+    LPC_EMAC->IntClear = status;
 
-	/* Clear the interrupt. */ 
-	LPC_EMAC->IntClear = status; 
- 
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -77,440 +77,440 @@ void ENET_IRQHandler(void)
 /* phy write */
 static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
 {
-	unsigned int tout;
+    unsigned int tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MWTD = Value;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Value;
 
-	/* Wait utill operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_WR_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
+    /* Wait utill operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_WR_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
 }
 
 /* phy read */
 static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
 {
-	rt_uint32_t tout;
+    rt_uint32_t tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MCMD = MCMD_READ;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
 
-	/* Wait until operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_RD_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
-	LPC_EMAC->MCMD = 0;
-	return (LPC_EMAC->MRDD);
+    /* Wait until operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_RD_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
+    LPC_EMAC->MCMD = 0;
+    return (LPC_EMAC->MRDD);
 }
 
 /* init rx descriptor */
 rt_inline void rx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_RX_FRAG; i++)
-	{
-		RX_DESC_PACKET(i)  = RX_BUF(i);
-		RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
-		RX_STAT_INFO(i)    = 0;
-		RX_STAT_HASHCRC(i) = 0;
-	}
+    for (i = 0; i < NUM_RX_FRAG; i++)
+    {
+        RX_DESC_PACKET(i)  = RX_BUF(i);
+        RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
+        RX_STAT_INFO(i)    = 0;
+        RX_STAT_HASHCRC(i) = 0;
+    }
 
-	/* Set EMAC Receive Descriptor Registers. */
-	LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
-	LPC_EMAC->RxStatus        = RX_STAT_BASE;
-	LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+    /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
+    LPC_EMAC->RxStatus        = RX_STAT_BASE;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
 
-	/* Rx Descriptors Point to 0 */
-	LPC_EMAC->RxConsumeIndex  = 0;
+    /* Rx Descriptors Point to 0 */
+    LPC_EMAC->RxConsumeIndex  = 0;
 }
 
 /* init tx descriptor */
 rt_inline void tx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_TX_FRAG; i++)
-	{
-		TX_DESC_PACKET(i) = TX_BUF(i);
-		TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
-		TX_STAT_INFO(i)   = 0;
-	}
+    for (i = 0; i < NUM_TX_FRAG; i++)
+    {
+        TX_DESC_PACKET(i) = TX_BUF(i);
+        TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
+        TX_STAT_INFO(i)   = 0;
+    }
 
-	/* Set EMAC Transmit Descriptor Registers. */
-	LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
-	LPC_EMAC->TxStatus        = TX_STAT_BASE;
-	LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+    /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
+    LPC_EMAC->TxStatus        = TX_STAT_BASE;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
 
-	/* Tx Descriptors Point to 0 */
-	LPC_EMAC->TxProduceIndex  = 0;
+    /* Tx Descriptors Point to 0 */
+    LPC_EMAC->TxProduceIndex  = 0;
 }
 
 static rt_err_t lpc17xx_emac_init(rt_device_t dev)
 {
-	/* Initialize the EMAC ethernet controller. */
-	rt_uint32_t regv, tout, id1, id2;
+    /* Initialize the EMAC ethernet controller. */
+    rt_uint32_t regv, tout, id1, id2;
 
-	/* Power Up the EMAC controller. */
-	LPC_SC->PCONP |= 0x40000000;
+    /* Power Up the EMAC controller. */
+    LPC_SC->PCONP |= 0x40000000;
 
-	/* Enable P1 Ethernet Pins. */
-	LPC_PINCON->PINSEL2 = 0x50150105;
-	LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
+    /* Enable P1 Ethernet Pins. */
+    LPC_PINCON->PINSEL2 = 0x50150105;
+    LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
 
-	/* Reset all EMAC internal modules. */
-	LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
-				 MAC1_SIM_RES | MAC1_SOFT_RES;
-	LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
+    /* Reset all EMAC internal modules. */
+    LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
+                 MAC1_SIM_RES | MAC1_SOFT_RES;
+    LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
 
-	/* A short delay after reset. */
-	for (tout = 100; tout; tout--);
+    /* A short delay after reset. */
+    for (tout = 100; tout; tout--);
 
-	/* Initialize MAC control registers. */
-	LPC_EMAC->MAC1 = MAC1_PASS_ALL;
-	LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-	LPC_EMAC->MAXF = ETH_MAX_FLEN;
-	LPC_EMAC->CLRT = CLRT_DEF;
-	LPC_EMAC->IPGR = IPGR_DEF;
+    /* Initialize MAC control registers. */
+    LPC_EMAC->MAC1 = MAC1_PASS_ALL;
+    LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+    LPC_EMAC->MAXF = ETH_MAX_FLEN;
+    LPC_EMAC->CLRT = CLRT_DEF;
+    LPC_EMAC->IPGR = IPGR_DEF;
 
-	/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20;
+    /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20;
 
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
 
-	/* Reset Reduced MII Logic. */
-	LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->SUPP = SUPP_SPEED;
+    /* Reset Reduced MII Logic. */
+    LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->SUPP = SUPP_SPEED;
 
-	/* Put the PHY in reset mode */
-	write_PHY (PHY_REG_BMCR, 0x8000);
-	for (tout = 1000; tout; tout--);
+    /* Put the PHY in reset mode */
+    write_PHY (PHY_REG_BMCR, 0x8000);
+    for (tout = 1000; tout; tout--);
 
-	/* Wait for hardware reset to end. */
-	for (tout = 0; tout < 10000; tout++)
-	{
-		regv = read_PHY (PHY_REG_BMCR);
-		if (!(regv & 0x8000))
-		{
-			/* Reset complete */
-			break;
-		}
-	}
-	if (tout >= 10000) 
-	{
-		//return -RT_ERROR; /* reset failed */
-		rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout);
-	}
+    /* Wait for hardware reset to end. */
+    for (tout = 0; tout < 10000; tout++)
+    {
+        regv = read_PHY (PHY_REG_BMCR);
+        if (!(regv & 0x8000))
+        {
+            /* Reset complete */
+            break;
+        }
+    }
+    if (tout >= 10000)
+    {
+        //return -RT_ERROR; /* reset failed */
+        rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout);
+    }
 
-	/* Check if this is a DP83848C PHY. */
-	id1 = read_PHY (PHY_REG_IDR1);
-	id2 = read_PHY (PHY_REG_IDR2);
+    /* Check if this is a DP83848C PHY. */
+    id1 = read_PHY (PHY_REG_IDR1);
+    id2 = read_PHY (PHY_REG_IDR2);
 
-	if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
-	{
-	//	return -RT_ERROR;
-		rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0)));
-	}
-	else
-	{
-		/* Configure the PHY device */
-		/* Configure the PHY device */
-		switch (lpc17xx_emac_device.phy_mode)
-		{
-			case EMAC_PHY_AUTO:
-				/* Use auto negotiation about the link speed. */
-				write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
-				/* Wait to complete Auto_Negotiation. */
-				for (tout = 0; tout < 200000; tout++)
-				{
-					regv = read_PHY (PHY_REG_BMSR);
-					if (regv & 0x0020)
-					{
-						/* Auto negotiation Complete. */
-						break;
-					}
-				}
-				if(tout >= 200000)
-		                {
-		                    rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout);
-		                }
-				break;
-			case EMAC_PHY_10MBIT:
-				/* Connect at 10MBit */
-				write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
-				break;
-			case EMAC_PHY_100MBIT:
-				/* Connect at 100MBit */
-				write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
-				break;
-		}
-	}
-	//if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
+    if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
+    {
+    //  return -RT_ERROR;
+        rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0)));
+    }
+    else
+    {
+        /* Configure the PHY device */
+        /* Configure the PHY device */
+        switch (lpc17xx_emac_device.phy_mode)
+        {
+            case EMAC_PHY_AUTO:
+                /* Use auto negotiation about the link speed. */
+                write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
+                /* Wait to complete Auto_Negotiation. */
+                for (tout = 0; tout < 200000; tout++)
+                {
+                    regv = read_PHY (PHY_REG_BMSR);
+                    if (regv & 0x0020)
+                    {
+                        /* Auto negotiation Complete. */
+                        break;
+                    }
+                }
+                if(tout >= 200000)
+                        {
+                            rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout);
+                        }
+                break;
+            case EMAC_PHY_10MBIT:
+                /* Connect at 10MBit */
+                write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
+                break;
+            case EMAC_PHY_100MBIT:
+                /* Connect at 100MBit */
+                write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
+                break;
+        }
+    }
+    //if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
 
-	/* Check the link status. */
-	for (tout = 0; tout < 100; tout++)
-	{
-		regv = read_PHY (PHY_REG_STS);
-		if (regv & 0x0001)
-		{
-			/* Link is on. */
-			break;
-		}
-	}
-	if (tout >= 100) 
-	{
-		//return -RT_ERROR;
-		rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout);
-	}
-	/* Configure Full/Half Duplex mode. */
-	if (regv & 0x0004)
-	{
-		/* Full duplex is enabled. */
-		LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
-		LPC_EMAC->Command |= CR_FULL_DUP;
-		LPC_EMAC->IPGT     = IPGT_FULL_DUP;
-	}
-	else
-	{
-		/* Half duplex mode. */
-		LPC_EMAC->IPGT = IPGT_HALF_DUP;
-	}
+    /* Check the link status. */
+    for (tout = 0; tout < 100; tout++)
+    {
+        regv = read_PHY (PHY_REG_STS);
+        if (regv & 0x0001)
+        {
+            /* Link is on. */
+            break;
+        }
+    }
+    if (tout >= 100)
+    {
+        //return -RT_ERROR;
+        rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout);
+    }
+    /* Configure Full/Half Duplex mode. */
+    if (regv & 0x0004)
+    {
+        /* Full duplex is enabled. */
+        LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
+        LPC_EMAC->Command |= CR_FULL_DUP;
+        LPC_EMAC->IPGT     = IPGT_FULL_DUP;
+    }
+    else
+    {
+        /* Half duplex mode. */
+        LPC_EMAC->IPGT = IPGT_HALF_DUP;
+    }
 
-	/* Configure 100MBit/10MBit mode. */
-	if (regv & 0x0002)
-	{
-		/* 10MBit mode. */
-		LPC_EMAC->SUPP = 0;
-	}
-	else
-	{
-		/* 100MBit mode. */
-		LPC_EMAC->SUPP = SUPP_SPEED;
-	}
+    /* Configure 100MBit/10MBit mode. */
+    if (regv & 0x0002)
+    {
+        /* 10MBit mode. */
+        LPC_EMAC->SUPP = 0;
+    }
+    else
+    {
+        /* 100MBit mode. */
+        LPC_EMAC->SUPP = SUPP_SPEED;
+    }
 
-	/* Set the Ethernet MAC Address registers */
-	LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
-	LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
-	LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
+    /* Set the Ethernet MAC Address registers */
+    LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
+    LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
+    LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
 
-	/* Initialize Tx and Rx DMA Descriptors */
-	rx_descr_init ();
-	tx_descr_init ();
+    /* Initialize Tx and Rx DMA Descriptors */
+    rx_descr_init ();
+    tx_descr_init ();
 
-	/* Receive Broadcast and Perfect Match Packets */
-	LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
+    /* Receive Broadcast and Perfect Match Packets */
+    LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
 
-	/* Reset all interrupts */
-	LPC_EMAC->IntClear  = 0xFFFF;
+    /* Reset all interrupts */
+    LPC_EMAC->IntClear  = 0xFFFF;
 
-	/* Enable EMAC interrupts. */
-	LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    /* Enable EMAC interrupts. */
+    LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
 
-	/* Enable receive and transmit mode of MAC Ethernet core */
-	LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
-	LPC_EMAC->MAC1     |= MAC1_REC_EN;
+    /* Enable receive and transmit mode of MAC Ethernet core */
+    LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
+    LPC_EMAC->MAC1     |= MAC1_REC_EN;
 
-	/* Enable the ENET Interrupt */
-	NVIC_EnableIRQ(ENET_IRQn);
+    /* Enable the ENET Interrupt */
+    NVIC_EnableIRQ(ENET_IRQn);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* EtherNet Device Interface */
 /* transmit packet. */
 rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
 {
-	rt_uint32_t Index, IndexNext;
-	struct pbuf *q;
-	rt_uint8_t *ptr;
+    rt_uint32_t Index, IndexNext;
+    struct pbuf *q;
+    rt_uint8_t *ptr;
+
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
+    /* check whether block is full */
+    while (IndexNext == LPC_EMAC->TxConsumeIndex)
+    {
+        rt_err_t result;
+        rt_uint32_t recved;
 
-	/* check whether block is full */
-	while (IndexNext == LPC_EMAC->TxConsumeIndex)
-	{
-		rt_err_t result;
-		rt_uint32_t recved;
-		
-		/* there is no block yet, wait a flag */
-		result = rt_event_recv(&tx_event, 0x01, 
-			RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
+        /* there is no block yet, wait a flag */
+        result = rt_event_recv(&tx_event, 0x01,
+            RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
 
-		RT_ASSERT(result == RT_EOK);
-	}
+        RT_ASSERT(result == RT_EOK);
+    }
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* get produce index */
-	Index = LPC_EMAC->TxProduceIndex;
+    /* get produce index */
+    Index = LPC_EMAC->TxProduceIndex;
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber)
-		IndexNext = 0;
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber)
+        IndexNext = 0;
 
-	/* copy data to tx buffer */
-	q = p;
-	ptr = (rt_uint8_t*)TX_BUF(Index);
-	while (q)
-	{
-		memcpy(ptr, q->payload, q->len);
-		ptr += q->len;
-		q = q->next;
-	}
+    /* copy data to tx buffer */
+    q = p;
+    ptr = (rt_uint8_t*)TX_BUF(Index);
+    while (q)
+    {
+        memcpy(ptr, q->payload, q->len);
+        ptr += q->len;
+        q = q->next;
+    }
 
-	TX_DESC_CTRL(Index) &= ~0x7ff;
-	TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
+    TX_DESC_CTRL(Index) &= ~0x7ff;
+    TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
 
-	/* change index to the next */
-	LPC_EMAC->TxProduceIndex = IndexNext;
+    /* change index to the next */
+    LPC_EMAC->TxProduceIndex = IndexNext;
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* reception packet. */
 struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
 {
-	struct pbuf* p;
-	rt_uint32_t size;
-	rt_uint32_t Index;
+    struct pbuf* p;
+    rt_uint32_t size;
+    rt_uint32_t Index;
+
+    /* init p pointer */
+    p = RT_NULL;
 
-	/* init p pointer */
-	p = RT_NULL;
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    Index = LPC_EMAC->RxConsumeIndex;
+    if(Index != LPC_EMAC->RxProduceIndex)
+    {
+        size = (RX_STAT_INFO(Index) & 0x7ff)+1;
+        if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
 
-	Index = LPC_EMAC->RxConsumeIndex;
-	if(Index != LPC_EMAC->RxProduceIndex)
-	{
-		size = (RX_STAT_INFO(Index) & 0x7ff)+1;
-		if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
+        /* allocate buffer */
+        p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
+        if (p != RT_NULL)
+        {
+            struct pbuf* q;
+            rt_uint8_t *ptr;
 
-		/* allocate buffer */
-		p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
-		if (p != RT_NULL)
-		{
-			struct pbuf* q;
-			rt_uint8_t *ptr;
+            ptr = (rt_uint8_t*)RX_BUF(Index);
+            for (q = p; q != RT_NULL; q= q->next)
+            {
+                memcpy(q->payload, ptr, q->len);
+                ptr += q->len;
+            }
+        }
 
-			ptr = (rt_uint8_t*)RX_BUF(Index);
-			for (q = p; q != RT_NULL; q= q->next)
-			{
-				memcpy(q->payload, ptr, q->len);
-				ptr += q->len;
-			}
-		}
-		
-		/* move Index to the next */
-		if(++Index > LPC_EMAC->RxDescriptorNumber)
-			Index = 0;
+        /* move Index to the next */
+        if(++Index > LPC_EMAC->RxDescriptorNumber)
+            Index = 0;
 
-		/* set consume index */
-		LPC_EMAC->RxConsumeIndex = Index;
-	}
-	else
-	{
-		/* Enable RxDone interrupt */
-		LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
-	}
+        /* set consume index */
+        LPC_EMAC->RxConsumeIndex = Index;
+    }
+    else
+    {
+        /* Enable RxDone interrupt */
+        LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    }
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
-	return p;
+    return p;
 }
 
 int lpc17xx_emac_hw_init(void)
 {
-	rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
-	/* set auto negotiation mode */
-	lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
+    /* set auto negotiation mode */
+    lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
 
-	// OUI 00-60-37 NXP Semiconductors
-	lpc17xx_emac_device.dev_addr[0] = 0x00;
-	lpc17xx_emac_device.dev_addr[1] = 0x60;
-	lpc17xx_emac_device.dev_addr[2] = 0x37;
-	/* set mac address: (only for test) */
-	lpc17xx_emac_device.dev_addr[3] = 0x12;
-	lpc17xx_emac_device.dev_addr[4] = 0x34;
-	lpc17xx_emac_device.dev_addr[5] = 0x56;
+    // OUI 00-60-37 NXP Semiconductors
+    lpc17xx_emac_device.dev_addr[0] = 0x00;
+    lpc17xx_emac_device.dev_addr[1] = 0x60;
+    lpc17xx_emac_device.dev_addr[2] = 0x37;
+    /* set mac address: (only for test) */
+    lpc17xx_emac_device.dev_addr[3] = 0x12;
+    lpc17xx_emac_device.dev_addr[4] = 0x34;
+    lpc17xx_emac_device.dev_addr[5] = 0x56;
 
-	lpc17xx_emac_device.parent.parent.init		= lpc17xx_emac_init;
-	lpc17xx_emac_device.parent.parent.open		= lpc17xx_emac_open;
-	lpc17xx_emac_device.parent.parent.close		= lpc17xx_emac_close;
-	lpc17xx_emac_device.parent.parent.read		= lpc17xx_emac_read;
-	lpc17xx_emac_device.parent.parent.write		= lpc17xx_emac_write;
-	lpc17xx_emac_device.parent.parent.control	= lpc17xx_emac_control;
-	lpc17xx_emac_device.parent.parent.user_data	= RT_NULL;
+    lpc17xx_emac_device.parent.parent.init      = lpc17xx_emac_init;
+    lpc17xx_emac_device.parent.parent.open      = lpc17xx_emac_open;
+    lpc17xx_emac_device.parent.parent.close     = lpc17xx_emac_close;
+    lpc17xx_emac_device.parent.parent.read      = lpc17xx_emac_read;
+    lpc17xx_emac_device.parent.parent.write     = lpc17xx_emac_write;
+    lpc17xx_emac_device.parent.parent.control   = lpc17xx_emac_control;
+    lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
 
-	lpc17xx_emac_device.parent.eth_rx			= lpc17xx_emac_rx;
-	lpc17xx_emac_device.parent.eth_tx			= lpc17xx_emac_tx;
+    lpc17xx_emac_device.parent.eth_rx           = lpc17xx_emac_rx;
+    lpc17xx_emac_device.parent.eth_tx           = lpc17xx_emac_tx;
 
-	eth_device_init(&(lpc17xx_emac_device.parent), "e0");
-	return 0;
+    eth_device_init(&(lpc17xx_emac_device.parent), "e0");
+    return 0;
 }
 INIT_DEVICE_EXPORT(lpc17xx_emac_hw_init);
diff --git a/bsp/lpc176x/drivers/emac.h b/bsp/lpc176x/drivers/emac.h
index d0edd25d63..1fc8973249 100644
--- a/bsp/lpc176x/drivers/emac.h
+++ b/bsp/lpc176x/drivers/emac.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __LPC17XX_EMAC_H
 #define __LPC17XX_EMAC_H
 
@@ -11,7 +20,7 @@
 #define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
 
 /* EMAC variables located in 16K Ethernet SRAM */
-#define RX_DESC_BASE		0x20080000
+#define RX_DESC_BASE        0x20080000
 #define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
 #define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
 #define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
diff --git a/bsp/lpc176x/drivers/led.h b/bsp/lpc176x/drivers/led.h
index 658ed16d1c..92f6ff4ffd 100644
--- a/bsp/lpc176x/drivers/led.h
+++ b/bsp/lpc176x/drivers/led.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc176x/drivers/sd.c b/bsp/lpc176x/drivers/sd.c
index 61e34ba43a..53b57676de 100644
--- a/bsp/lpc176x/drivers/sd.c
+++ b/bsp/lpc176x/drivers/sd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
     if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
     {
         struct rt_device_blk_geometry *geometry;
-        
+
         geometry = (struct rt_device_blk_geometry *)args;
-        
+
         if (geometry == RT_NULL) return -RT_ERROR;
         if (dev->user_data == RT_NULL) return -RT_ERROR;
-        
+
         geometry->bytes_per_sector = ((SDCFG *)dev->user_data)->sectorsize;
         geometry->block_size = ((SDCFG *)dev->user_data)->blocksize;
         geometry->sector_count = ((SDCFG *)dev->user_data)->sectorcnt;
diff --git a/bsp/lpc176x/drivers/spi.c b/bsp/lpc176x/drivers/spi.c
index a6561195c5..ef328bc793 100644
--- a/bsp/lpc176x/drivers/spi.c
+++ b/bsp/lpc176x/drivers/spi.c
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #include "LPC17xx.h"                              /* LPC17xx definitions    */
 #include "spi.h"
 
@@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s);
 /* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */
 void LPC17xx_SPI_Init (void)
 {
-	uint32_t dummy;
+    uint32_t dummy;
 
-	dummy = dummy; // avoid warning
+    dummy = dummy; // avoid warning
 
 #if 0
-	/* Initialize and enable the SSP0 Interface module. */
-	LPC_SC->PCONP |= (1 << 21);          /* Enable power to SSPI0 block  */
+    /* Initialize and enable the SSP0 Interface module. */
+    LPC_SC->PCONP |= (1 << 21);          /* Enable power to SSPI0 block  */
 
-	/* SSEL is GPIO, output set to high. */
-	LPC_GPIO0->FIODIR  |=  (1<<16);             /* P0.16 is output */
-	LPC_PINCON->PINSEL1 &= ~(3<<0);             /* P0.16 SSEL (used as GPIO) */
-	LPC17xx_SPI_DeSelect ();					/* set P0.16 high (SSEL inactiv) */
+    /* SSEL is GPIO, output set to high. */
+    LPC_GPIO0->FIODIR  |=  (1<<16);             /* P0.16 is output */
+    LPC_PINCON->PINSEL1 &= ~(3<<0);             /* P0.16 SSEL (used as GPIO) */
+    LPC17xx_SPI_DeSelect ();                    /* set P0.16 high (SSEL inactiv) */
 
-	/* SCK, MISO, MOSI are SSP pins. */
-	LPC_PINCON->PINSEL0 &= ~(3UL<<30);          /* P0.15 cleared */
-	LPC_PINCON->PINSEL0 |=  (2UL<<30);          /* P0.15 SCK0 */
-	LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));  /* P0.17, P0.18 cleared */
-	LPC_PINCON->PINSEL1 |=  ((2<<2) | (2<<4));  /* P0.17 MISO0, P0.18 MOSI0 */
+    /* SCK, MISO, MOSI are SSP pins. */
+    LPC_PINCON->PINSEL0 &= ~(3UL<<30);          /* P0.15 cleared */
+    LPC_PINCON->PINSEL0 |=  (2UL<<30);          /* P0.15 SCK0 */
+    LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));  /* P0.17, P0.18 cleared */
+    LPC_PINCON->PINSEL1 |=  ((2<<2) | (2<<4));  /* P0.17 MISO0, P0.18 MOSI0 */
 #else
-	LPC_SC->PCONP       |= (1 << 21);           /* Enable power to SSPI0 block */
+    LPC_SC->PCONP       |= (1 << 21);           /* Enable power to SSPI0 block */
 
-	/* SSEL is GPIO, output set to high. */
-	LPC_GPIO1->FIODIR   |=  (1<<21);            /* P1.21 is output             */
-	LPC_GPIO1->FIOPIN   |=  (1<<21);            /* set P1.21 high (SSEL inact.)*/
-	LPC_PINCON->PINSEL3 &= ~(0<<10);             /* P1.21 SSEL (used as GPIO)   */
+    /* SSEL is GPIO, output set to high. */
+    LPC_GPIO1->FIODIR   |=  (1<<21);            /* P1.21 is output             */
+    LPC_GPIO1->FIOPIN   |=  (1<<21);            /* set P1.21 high (SSEL inact.)*/
+    LPC_PINCON->PINSEL3 &= ~(0<<10);             /* P1.21 SSEL (used as GPIO)   */
 
-	/* P3.26 is SD Card Power Supply Enable Pin */
-	LPC_GPIO3->FIODIR   |=  (1<<26);            /* P3.26 is output             */
-	LPC_GPIO3->FIOPIN   &= ~(1<<26);            /* set P3.26 low(enable power) */
+    /* P3.26 is SD Card Power Supply Enable Pin */
+    LPC_GPIO3->FIODIR   |=  (1<<26);            /* P3.26 is output             */
+    LPC_GPIO3->FIOPIN   &= ~(1<<26);            /* set P3.26 low(enable power) */
 
-	/* SCK, MISO, MOSI are SSP pins. */
-	LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
-	LPC_PINCON->PINSEL3 |=  (3UL<<8);          /* P1.20 SCK0                  */
-	LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
-	LPC_PINCON->PINSEL3 |=  ((3<<14) | (3<<16));  /* P1.23 MISO0, P1.24 MOSI0    */
+    /* SCK, MISO, MOSI are SSP pins. */
+    LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
+    LPC_PINCON->PINSEL3 |=  (3UL<<8);          /* P1.20 SCK0                  */
+    LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
+    LPC_PINCON->PINSEL3 |=  ((3<<14) | (3<<16));  /* P1.23 MISO0, P1.24 MOSI0    */
 #endif
 
-	/* PCLK_SSP0=CCLK */
-	LPC_SC->PCLKSEL1 &= ~(3<<10);               /* PCLKSP0 = CCLK/4 (18MHz) */
-	LPC_SC->PCLKSEL1 |=  (1<<10);               /* PCLKSP0 = CCLK   (72MHz) */
+    /* PCLK_SSP0=CCLK */
+    LPC_SC->PCLKSEL1 &= ~(3<<10);               /* PCLKSP0 = CCLK/4 (18MHz) */
+    LPC_SC->PCLKSEL1 |=  (1<<10);               /* PCLKSP0 = CCLK   (72MHz) */
 
-	LPC_SSP0->CR0  = 0x0007;                    /* 8Bit, CPOL=0, CPHA=0         */
-	LPC_SSP0->CR1  = 0x0002;                    /* SSP0 enable, master          */
+    LPC_SSP0->CR0  = 0x0007;                    /* 8Bit, CPOL=0, CPHA=0         */
+    LPC_SSP0->CR1  = 0x0002;                    /* SSP0 enable, master          */
 
-	LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
+    LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
 
-	/* wait for busy gone */
-	while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
+    /* wait for busy gone */
+    while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
 
-	/* drain SPI RX FIFO */
-	while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
-	{
-		dummy = LPC_SSP0->DR;
-	}
+    /* drain SPI RX FIFO */
+    while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
+    {
+        dummy = LPC_SSP0->DR;
+    }
 }
 
 /* Close SSP0 */
 void LPC17xx_SPI_DeInit( void )
 {
-	// disable SPI
-	LPC_SSP0->CR1  = 0;
+    // disable SPI
+    LPC_SSP0->CR1  = 0;
 
 #if 0
-	// Pins to GPIO
-	LPC_PINCON->PINSEL0 &= ~(3UL<<30);
-	LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
+    // Pins to GPIO
+    LPC_PINCON->PINSEL0 &= ~(3UL<<30);
+    LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
 #else
-	LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
-	LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
+    LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
+    LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
 #endif
 
-	// disable SSP power
-	LPC_SC->PCONP &= ~(1 << 21);
+    // disable SSP power
+    LPC_SC->PCONP &= ~(1 << 21);
 }
 
 /* Set a SSP0 clock speed to desired value. */
 void LPC17xx_SPI_SetSpeed (uint8_t speed)
 {
-	speed &= 0xFE;
-	if ( speed < 2  ) {
-		speed = 2 ;
-	}
-	LPC_SSP0->CPSR = speed;
+    speed &= 0xFE;
+    if ( speed < 2  ) {
+        speed = 2 ;
+    }
+    LPC_SSP0->CPSR = speed;
 }
 
 /* SSEL: low */
 void LPC17xx_SPI_Select ()
 {
 #if 0
-	LPC_GPIO0->FIOPIN &= ~(1<<16);
+    LPC_GPIO0->FIOPIN &= ~(1<<16);
 #else
-	LPC_GPIO1->FIOPIN &= ~(1<<21);            /* SSEL is GPIO, set to high.  */
+    LPC_GPIO1->FIOPIN &= ~(1<<21);            /* SSEL is GPIO, set to high.  */
 #endif
 }
 
@@ -120,41 +129,41 @@ void LPC17xx_SPI_Select ()
 void LPC17xx_SPI_DeSelect ()
 {
 #if 0
-	LPC_GPIO0->FIOPIN |= (1<<16);
+    LPC_GPIO0->FIOPIN |= (1<<16);
 #else
-	LPC_GPIO1->FIOPIN |= (1<<21);             /* SSEL is GPIO, set to high.  */
+    LPC_GPIO1->FIOPIN |= (1<<21);             /* SSEL is GPIO, set to high.  */
 #endif
 }
 
 /* Send one byte then recv one byte of response. */
 static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s)
 {
-	uint8_t byte_r;
+    uint8_t byte_r;
 
-	LPC_SSP0->DR = byte_s;
-	while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); 	/* Wait for transfer to finish */
-	byte_r = LPC_SSP0->DR;
+    LPC_SSP0->DR = byte_s;
+    while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/);    /* Wait for transfer to finish */
+    byte_r = LPC_SSP0->DR;
 
-	return byte_r;                      /* Return received value */
+    return byte_r;                      /* Return received value */
 }
 
 /* Send one byte */
 void LPC17xx_SPI_SendByte (uint8_t data)
 {
-	LPC17xx_SPI_SendRecvByte (data);
+    LPC17xx_SPI_SendRecvByte (data);
 }
 
 /* Recv one byte */
 uint8_t LPC17xx_SPI_RecvByte ()
 {
-	return LPC17xx_SPI_SendRecvByte (0xFF);
+    return LPC17xx_SPI_SendRecvByte (0xFF);
 }
 
 /* Release SSP0 */
 void LPC17xx_SPI_Release (void)
 {
-	LPC17xx_SPI_DeSelect ();
-	LPC17xx_SPI_RecvByte ();
+    LPC17xx_SPI_DeSelect ();
+    LPC17xx_SPI_RecvByte ();
 }
 
 
@@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void)
 #define FIFO_ELEM 8
 
 /* Receive btr (must be multiple of 4) bytes of data and store in buff. */
-void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff,	uint32_t btr)
+void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
 {
-	uint32_t hwtr, startcnt, i, rec;
+    uint32_t hwtr, startcnt, i, rec;
 
-	hwtr = btr/2;  /* byte number in unit of short */
-	if ( btr < FIFO_ELEM ) {
-		startcnt = hwtr;
-	} else {
-		startcnt = FIFO_ELEM;
-	}
+    hwtr = btr/2;  /* byte number in unit of short */
+    if ( btr < FIFO_ELEM ) {
+        startcnt = hwtr;
+    } else {
+        startcnt = FIFO_ELEM;
+    }
 
-	LPC_SSP0 -> CR0 |= 0x0f;  /* DSS to 16 bit */
+    LPC_SSP0 -> CR0 |= 0x0f;  /* DSS to 16 bit */
 
-	for ( i = startcnt; i; i-- ) {
-		LPC_SSP0 -> DR = 0xffff;  /* fill TX FIFO, prepare clk for receive */
-	}
+    for ( i = startcnt; i; i-- ) {
+        LPC_SSP0 -> DR = 0xffff;  /* fill TX FIFO, prepare clk for receive */
+    }
 
-	do {
-		while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
-			// wait for data in RX FIFO (RNE set)
-		}
-		rec = LPC_SSP0->DR;
-		if ( i < ( hwtr - startcnt ) ) {
-			LPC_SSP0->DR = 0xffff;	/* fill TX FIFO, prepare clk for receive */
-		}
-		*buff++ = (uint8_t)(rec>>8);
-		*buff++ = (uint8_t)(rec);
-		i++;
-	} while ( i < hwtr );
+    do {
+        while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
+            // wait for data in RX FIFO (RNE set)
+        }
+        rec = LPC_SSP0->DR;
+        if ( i < ( hwtr - startcnt ) ) {
+            LPC_SSP0->DR = 0xffff;  /* fill TX FIFO, prepare clk for receive */
+        }
+        *buff++ = (uint8_t)(rec>>8);
+        *buff++ = (uint8_t)(rec);
+        i++;
+    } while ( i < hwtr );
 
-	LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
+    LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
 }
 
 /* Send 512 bytes of data block (stored in buff). */
 void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff)
 {
-	uint32_t cnt;
-	uint16_t data;
+    uint32_t cnt;
+    uint16_t data;
 
-	LPC_SSP0->CR0 |= 0x0f;  /* DSS to 16 bit */
+    LPC_SSP0->CR0 |= 0x0f;  /* DSS to 16 bit */
 
-	/* fill the FIFO unless it is full */
-	for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
-	{
-		/* wait for TX FIFO not full (TNF) */
-		while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
+    /* fill the FIFO unless it is full */
+    for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
+    {
+        /* wait for TX FIFO not full (TNF) */
+        while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
 
-		data  = (*buff++) << 8;
-		data |= *buff++;
-		LPC_SSP0->DR = data;
-	}
+        data  = (*buff++) << 8;
+        data |= *buff++;
+        LPC_SSP0->DR = data;
+    }
 
-	/* wait for BSY gone */
-	while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
+    /* wait for BSY gone */
+    while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
 
-	/* drain receive FIFO */
-	while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
-		data = LPC_SSP0->DR;
-	}
+    /* drain receive FIFO */
+    while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
+        data = LPC_SSP0->DR;
+    }
 
-	LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
+    LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
 }
 #endif /* USE_FIFO */
diff --git a/bsp/lpc176x/drivers/spi.h b/bsp/lpc176x/drivers/spi.h
index d1d9c14732..bad75d38b4 100644
--- a/bsp/lpc176x/drivers/spi.h
+++ b/bsp/lpc176x/drivers/spi.h
@@ -1,17 +1,26 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __LPC17XX_SPI_H__
 #define __LPC17XX_SPI_H__
 
 #include <stdint.h>
 #include <stdbool.h>
 
-// if not use FIFO, 	R: 600kB/s, W: 500kB/s
-// if     use FIFO,   	R: 1.2MB/s, W: 800kB/s
+// if not use FIFO,     R: 600kB/s, W: 500kB/s
+// if     use FIFO,     R: 1.2MB/s, W: 800kB/s
 #define USE_FIFO        1
 
-/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even	*/
-#define SPI_SPEED_20MHz		4	/* => 18MHz */
-#define SPI_SPEED_25MHz		4	/* => 18MHz */
-#define SPI_SPEED_400kHz  180	/* => 400kHz */
+/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
+#define SPI_SPEED_20MHz     4   /* => 18MHz */
+#define SPI_SPEED_25MHz     4   /* => 18MHz */
+#define SPI_SPEED_400kHz  180   /* => 400kHz */
 
 /* external functions */
 void LPC17xx_SPI_Init (void);
@@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data);
 uint8_t LPC17xx_SPI_RecvByte (void);
 
 #if USE_FIFO
-void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff,	uint32_t btr);
+void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
 void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff);
 #endif
 
-#endif	// __LPC17XX_SPI_H__
+#endif  // __LPC17XX_SPI_H__
diff --git a/bsp/lpc176x/drivers/uart.c b/bsp/lpc176x/drivers/uart.c
index 231eccb10a..a32952124b 100644
--- a/bsp/lpc176x/drivers/uart.c
+++ b/bsp/lpc176x/drivers/uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -56,8 +56,8 @@ void UART0_IRQHandler(void)
 {
     rt_ubase_t level, iir;
     struct rt_uart_lpc *uart = &uart_device;
-	/* enter interrupt */ 
- 	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
     /* read IIR and clear it */
     iir = LPC_UART->IIR;
 
@@ -91,8 +91,8 @@ void UART0_IRQHandler(void)
     {
         iir = LPC_UART->LSR;    //oe pe fe oe read for clear interrupt
     }
-	/* leave interrupt */ 
- 	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
     return;
 }
 
diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h
index 6b28d64d32..5096b2f71d 100644
--- a/bsp/lpc176x/rtconfig.h
+++ b/bsp/lpc176x/rtconfig.h
@@ -4,17 +4,17 @@
 // <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
 
 // <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
-#define RT_NAME_MAX	6
+#define RT_NAME_MAX 6
 // <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 // <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
 // <item description="8">8</item>
 // <item description="32">32</item>
 // <item description="256">256</item>
 // </integer>
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 // <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 // <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
@@ -29,11 +29,11 @@
 // <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
 // #define RT_USING_TIMER_SOFT
 // <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
-#define RT_TIMER_THREAD_PRIO	4
+#define RT_TIMER_THREAD_PRIO    4
 // <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
-#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_THREAD_STACK_SIZE  512
 // <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_TICK_PER_SECOND    10
 // </section>
 
 // <section name="IPC" description="Inter-Thread communication" default="always" >
@@ -67,15 +67,15 @@
 // <bool name="RT_USING_UART0" description="Using UART0" default="true" />
 #define RT_USING_UART0
 // <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 // </section>
 
 // <section name="RT_USING_CONSOLE" description="Using console" default="true" >
 #define RT_USING_CONSOLE
 // <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
-#define RT_CONSOLE_DEVICE_NAME	"uart0"
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
 // </section>
 
 // <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
@@ -87,7 +87,7 @@
 // <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
 #define FINSH_USING_DESCRIPTION
 // <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
-#define FINSH_THREAD_STACK_SIZE	4096
+#define FINSH_THREAD_STACK_SIZE 4096
 // </section>
 
 // <section name="LIBC" description="C Runtime library setting" default="always" >
@@ -102,16 +102,16 @@
 // <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
 #define DFS_USING_WORKDIR
 // <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
-#define DFS_FILESYSTEMS_MAX	2
+#define DFS_FILESYSTEMS_MAX 2
 // <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
-#define DFS_FD_MAX	4
+#define DFS_FD_MAX  4
 // <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
 #define RT_USING_DFS_ELMFAT
 // <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
 // <item description="LFN1">1</item>
 // <item description="LFN1">2</item>
 // </integer>
-#define RT_DFS_ELM_USE_LFN	1
+#define RT_DFS_ELM_USE_LFN  1
 // <integer name="RT_DFS_ELM_CODE_PAGE" description="specifies the OEM code page to be used on the target system" default="936">
 // <item description="Japanese Shift-JIS (DBCS, OEM, Windows)">932</item>
 // <item description="Simplified Chinese GBK (DBCS, OEM, Windows)">936</item>
@@ -142,7 +142,7 @@
 // </integer>
 #define RT_DFS_ELM_CODE_PAGE 437
 // <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
-#define RT_DFS_ELM_MAX_LFN	64
+#define RT_DFS_ELM_MAX_LFN  64
 // <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
 // #define RT_USING_DFS_YAFFS2
 // <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
@@ -152,7 +152,7 @@
 // <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
 // #define RT_USING_DFS_NFS
 // <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+#define RT_NFS_HOST_EXPORT  "192.168.1.5:/"
 // </section>
 
 // <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
@@ -168,29 +168,29 @@
 // <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
 #define RT_LWIP_DNS
 // <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
-#define RT_LWIP_PBUF_NUM	4
+#define RT_LWIP_PBUF_NUM    4
 // <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
-#define RT_LWIP_TCP_PCB_NUM	3
+#define RT_LWIP_TCP_PCB_NUM 3
 // <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
-#define RT_LWIP_TCP_SND_BUF	(2 * TCP_MSS)
+#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
 // <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
-#define RT_LWIP_TCP_WND	2048
+#define RT_LWIP_TCP_WND 2048
 // <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
 // #define RT_LWIP_SNMP
 // <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
 // #define RT_LWIP_DHCP
 // <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
 // <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
 // <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 // <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
-#define RT_LWIP_ETHTHREAD_PRIORITY	14
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
 // <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
 // <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
 // <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
 #define RT_LWIP_IPADDR "192.168.1.30"
 // <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />