add lpc1788

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1759 bbd45198-f89e-11dd-88c7-29a3b14d5316
author: wuyangyong <[email protected]> 2011-10-13 17:15:32 +0000
committer: wuyangyong <[email protected]> 2011-10-13 17:15:32 +0000
commit: eb0af4e41ee1f7857fea77dde1ecf51bf902c9f9 (patch)
tree: 36bc386d17af582fea59c442a366df230ff4fd11 /bsp/lpc178x/drivers
parent: 1e06bb2726c1bdedbf5a962c2d81996358e3d186 (diff)
12 files changed, 3898 insertions, 0 deletions
diff --git a/bsp/lpc178x/drivers/SConscript b/bsp/lpc178x/drivers/SConscript
new file mode 100644
index 0000000000..dbcec922cf
--- /dev/null
+++ b/bsp/lpc178x/drivers/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/lpc178x/drivers/board.c b/bsp/lpc178x/drivers/board.c
new file mode 100644
index 0000000000..1504a444aa
--- /dev/null
+++ b/bsp/lpc178x/drivers/board.c
@@ -0,0 +1,77 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2010-02-04     Magicoe      ported to LPC17xx
+ * 2010-05-02     Aozima       update CMSIS to 130
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "uart.h"
+#include "board.h"
+#include "LPC177x_8x.h"
+#include "system_LPC177x_8x.h"
+
+/**
+ * @addtogroup LPC17xx
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_timer_handler(void)
+{
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
+
+void SysTick_Handler(void)
+{
+    rt_hw_timer_handler();
+}
+
+/**
+ * This function will initial LPC17xx board.
+ */
+void rt_hw_board_init()
+{
+	/* NVIC Configuration */
+#define NVIC_VTOR_MASK              0x3FFFFF80
+#ifdef  VECT_TAB_RAM
+	/* Set the Vector Table base location at 0x10000000 */
+	SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+#else  /* VECT_TAB_FLASH  */
+	/* Set the Vector Table base location at 0x00000000 */
+	SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
+#endif
+
+	/* init systick */
+	SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND - 1);
+	/* set pend exception priority */
+	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+
+	rt_hw_uart_init();
+	rt_console_set_device( CONSOLE_DEVICE );
+
+    rt_kprintf("\r\n\r\nSystemInit......\r\n");
+}
+
+/*@}*/
diff --git a/bsp/lpc178x/drivers/board.h b/bsp/lpc178x/drivers/board.h
new file mode 100644
index 0000000000..23af83af8c
--- /dev/null
+++ b/bsp/lpc178x/drivers/board.h
@@ -0,0 +1,29 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2010-02-04     Magicoe      add board.h to LPC176x bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+/* RT_USING_UART */
+#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_USING_UART0
+#define RT_USING_UART1
+
+#define CONSOLE_DEVICE      "uart1"
+#define FINSH_DEVICE_NAME   "uart1"
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
new file mode 100644
index 0000000000..008245b8e8
--- /dev/null
+++ b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
@@ -0,0 +1,301 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_clkpwr.c			2011-06-02
+*//**
+* @file		lpc177x_8x_clkpwr.c
+* @brief	Contains all functions support for Clock and Power Control
+*			firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup CLKPWR
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc177x_8x_clkpwr.h"
+
+
+uint32_t USBFrequency = 0;
+uint32_t SPIFIFrequency = 0;
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup CLKPWR_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief 		Set value of each Peripheral Clock Selection
+ * @param[in]	ClkType clock type that will be divided, should be:
+ * 				- CLKPWR_CLKTYPE_CPU 		: CPU clock
+ * 				- CLKPWR_CLKTYPE_PER		: Peripheral clock
+ * 				- CLKPWR_CLKTYPE_EMC 		: EMC clock
+ * 				- CLKPWR_CLKTYPE_USB 		: USB clock
+ * @param[in]	DivVal	Value of divider. This value should be set as follows:
+ * 					- CPU clock: DivVal must be in range: 0..31
+ * 					- Peripheral clock: DivVal must be in range: 0..31
+ * 					- EMC clock: DivVal must be:
+ * 							+ 0: The EMC uses the same clock as the CPU
+ * 							+ 1: The EMC uses a clock at half the rate of the CPU
+ *   				- USB clock: DivVal must be:
+ * 							+ 0: the divider is turned off, no clock will
+ * 								 be provided to the USB subsystem
+ * 							+ 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
+ * 							+ 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
+ * @return none
+ * Note: Pls assign right DivVal, this function will not check if it is illegal.
+ **********************************************************************/
+void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
+{
+	switch(ClkType)
+	{
+	case CLKPWR_CLKTYPE_CPU:
+		LPC_SC->CCLKSEL = DivVal;
+		SystemCoreClockUpdate(); //Update clock
+		break;
+	case CLKPWR_CLKTYPE_PER:
+		LPC_SC->PCLKSEL = DivVal;
+		SystemCoreClockUpdate(); //Update clock
+		break;
+	case CLKPWR_CLKTYPE_EMC:
+		LPC_SC->EMCCLKSEL = DivVal;
+		SystemCoreClockUpdate(); //Update clock
+		break;
+	case CLKPWR_CLKTYPE_USB:
+		LPC_SC->USBCLKSEL &= ~(0x0000001F);
+		LPC_SC->USBCLKSEL |= DivVal;
+		break;
+	default:
+		while(1);//Error Loop;
+	}
+}
+
+/*********************************************************************//**
+ * @brief 		Get current clock value
+ * @param[in]	ClkType clock type that will be divided, should be:
+ * 				- CLKPWR_CLKTYPE_CPU 		: CPU clock
+ * 				- CLKPWR_CLKTYPE_PER		: Peripheral clock
+ * 				- CLKPWR_CLKTYPE_EMC 		: EMC clock
+ * 				- CLKPWR_CLKTYPE_USB 		: USB clock
+ **********************************************************************/
+uint32_t CLKPWR_GetCLK (uint8_t ClkType)
+{
+	switch(ClkType)
+	{
+		case CLKPWR_CLKTYPE_CPU:
+			return SystemCoreClock;
+
+		case CLKPWR_CLKTYPE_PER:
+			return PeripheralClock;
+
+		case CLKPWR_CLKTYPE_EMC:
+			return EMCClock;
+
+		case CLKPWR_CLKTYPE_USB:
+			return USBClock;
+
+		default:
+			while(1);//error loop
+	}
+}
+
+/*********************************************************************//**
+ * @brief 		Configure power supply for each peripheral according to NewState
+ * @param[in]	PPType	Type of peripheral used to enable power,
+ *     			should be one of the following:
+ *     			-  CLKPWR_PCONP_PCLCD		: LCD
+ *     			-  CLKPWR_PCONP_PCTIM0 		: Timer 0
+				-  CLKPWR_PCONP_PCTIM1 		: Timer 1
+				-  CLKPWR_PCONP_PCUART0  	: UART 0
+				-  CLKPWR_PCONP_PCUART1   	: UART 1
+				-  CLKPWR_PCONP_PCPWM0		: PWM 0
+				-  CLKPWR_PCONP_PCPWM1 		: PWM 1
+				-  CLKPWR_PCONP_PCI2C0 		: I2C 0
+				-  CLKPWR_PCONP_PCUART4		: UART4
+				-  CLKPWR_PCONP_PCRTC   	: RTC
+				-  CLKPWR_PCONP_PCSSP1 		: SSP 1
+				-  CLKPWR_PCONP_PCEMC		: EMC
+				-  CLKPWR_PCONP_PCADC   		: ADC
+				-  CLKPWR_PCONP_PCAN1   	: CAN 1
+				-  CLKPWR_PCONP_PCAN2   	: CAN 2
+				-  CLKPWR_PCONP_PCGPIO 		: GPIO
+				-  CLKPWR_PCONP_PCMC 		: MCPWM
+				-  CLKPWR_PCONP_PCQEI 		: QEI
+				-  CLKPWR_PCONP_PCI2C1   	: I2C 1
+				-  CLKPWR_PCONP_PCSSP2		: SSP 2
+				-  CLKPWR_PCONP_PCSSP0 		: SSP 0
+				-  CLKPWR_PCONP_PCTIM2 		: Timer 2
+				-  CLKPWR_PCONP_PCTIM3 		: Timer 3
+				-  CLKPWR_PCONP_PCUART2  	: UART 2
+				-  CLKPWR_PCONP_PCUART3   	: UART 3
+				-  CLKPWR_PCONP_PCI2C2 		: I2C 2
+				-  CLKPWR_PCONP_PCI2S   	: I2S
+				-  CLKPWR_PCONP_PCSDC		: SDC
+				-  CLKPWR_PCONP_PCGPDMA   	: GPDMA
+				-  CLKPWR_PCONP_PCENET 		: Ethernet
+				-  CLKPWR_PCONP_PCUSB   	: USB
+ *
+ * @param[in]	NewState	New state of Peripheral Power, should be:
+ * 				- ENABLE	: Enable power for this peripheral
+ * 				- DISABLE	: Disable power for this peripheral
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		LPC_SC->PCONP |= PPType;
+	}
+	else if (NewState == DISABLE)
+	{
+		LPC_SC->PCONP &= ~PPType;
+	}
+}
+
+#if 0
+// nxp21346
+/*********************************************************************//**
+ * @brief 		Configure hardware reset for each peripheral according to NewState
+ * @param[in]	PPType	Type of peripheral used to enable power,
+ *     			should be one of the following:
+ *     			-  CLKPWR_RSTCON0_LCD		: LCD
+ *     			-  CLKPWR_RSTCON0_TIM0 		: Timer 0
+				-  CLKPWR_RSTCON0_TIM1 		: Timer 1
+				-  CLKPWR_RSTCON0_UART0  	: UART 0
+				-  CLKPWR_RSTCON0_UART1   	: UART 1
+				-  CLKPWR_RSTCON0_PWM0 		: PWM 0
+				-  CLKPWR_RSTCON0_PWM1 		: PWM 1
+				-  CLKPWR_RSTCON0_I2C0		: I2C 0
+				-  CLKPWR_RSTCON0_UART4   	: UART 4
+				-  CLKPWR_RSTCON0_RTC 		: RTC
+				-  CLKPWR_RSTCON0_SSP1		: SSP 1
+				-  CLKPWR_RSTCON0_EMC   	: EMC
+				-  CLKPWR_RSTCON0_ADC   	: ADC
+				-  CLKPWR_RSTCON0_CAN1   	: CAN 1
+				-  CLKPWR_RSTCON0_CAN2 		: CAN 2
+				-  CLKPWR_RSTCON0_GPIO 		: GPIO
+				-  CLKPWR_RSTCON0_MCPWM 	: MCPWM
+				-  CLKPWR_RSTCON0_QEI   	: QEI
+				-  CLKPWR_RSTCON0_I2C1		: I2C 1
+				-  CLKPWR_RSTCON0_SSP2 		: SSP 2
+				-  CLKPWR_RSTCON0_SSP0 		: SSP 0
+				-  CLKPWR_RSTCON0_TIM2 		: Timer 2
+				-  CLKPWR_RSTCON0_TIM3  	: Timer 3
+				-  CLKPWR_RSTCON0_UART2  	: UART 2
+				-  CLKPWR_RSTCON0_UART3   	: UART 3
+				-  CLKPWR_RSTCON0_I2C2 		: I2C 2
+				-  CLKPWR_RSTCON0_I2S   	: I2S
+				-  CLKPWR_RSTCON0_SDC		: SDC
+				-  CLKPWR_RSTCON0_GPDMA   	: GPDMA
+				-  CLKPWR_RSTCON0_ENET 		: Ethernet
+				-  CLKPWR_RSTCON0_USB   	: USB
+ *
+ * @param[in]	NewState	New state of Peripheral Power, should be:
+ * 				- ENABLE	: Enable power for this peripheral
+ * 				- DISABLE	: Disable power for this peripheral
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
+{
+	if(PType < 32)
+	{
+		if(NewState == ENABLE)
+			LPC_SC->RSTCON0 |=(1<<PType);
+		else
+			LPC_SC->RSTCON0 &=~(1<<PType);
+	}
+	else
+	{
+		if(NewState == ENABLE)
+			LPC_SC->RSTCON1 |= (1<<(PType - 31));
+		else
+			LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
+	}
+}
+// nxp21346
+#endif
+
+/*********************************************************************//**
+ * @brief 		Enter Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_Sleep(void)
+{
+	LPC_SC->PCON = 0x00;
+	/* Sleep Mode*/
+	__WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief 		Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_DeepSleep(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+	SCB->SCR = 0x4;
+	LPC_SC->PCON = 0x8;
+	/* Deep Sleep Mode*/
+	__WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief 		Enter Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_PowerDown(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+	SCB->SCR = 0x4;
+	LPC_SC->PCON = 0x09;
+	/* Power Down Mode*/
+	__WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief 		Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]	None
+ * @return		None
+ **********************************************************************/
+void CLKPWR_DeepPowerDown(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+	SCB->SCR = 0x4;
+	LPC_SC->PCON = 0x03;
+	/* Deep Power Down Mode*/
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
new file mode 100644
index 0000000000..d4e282b547
--- /dev/null
+++ b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
@@ -0,0 +1,242 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_clkpwr.h			2011-06-02
+*//**
+* @file		lpc177x_8x_clkpwr.h
+* @brief	Contains all macro definitions and function prototypes
+*			support for Clock and Power Control firmware library on 
+*			LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CLKPWR	Clock Power
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC177X_8X_CLKPWR_H_
+#define __LPC177X_8X_CLKPWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC177x_8x.h"
+#include "lpc_types.h"
+#include "system_LPC177x_8x.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
+ * @{
+ */
+
+/********************************************************************
+* Clock Source Selection Definitions
+**********************************************************************/
+#define CLKPWR_CLKSRCSEL_IRCOSC		((uint32_t)(0))
+#define CLKPWR_CLKSRCSEL_MAINOSC	((uint32_t)(1))
+
+/********************************************************************
+* Clock type/domain Definitions (calculated from input and pre-configuration
+* parameter(s)
+**********************************************************************/
+#define CLKPWR_CLKTYPE_CPU			((uint32_t)(0))
+#define CLKPWR_CLKTYPE_PER			((uint32_t)(1))
+#define CLKPWR_CLKTYPE_EMC			((uint32_t)(2))
+#define CLKPWR_CLKTYPE_USB			((uint32_t)(3))
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+/** LCD controller power/clock control bit */
+#define CLKPWR_PCONP_PCLCD		((uint32_t)(1<<0))
+
+/** Timer/Counter 0 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM0		((uint32_t)(1<<1))
+
+/* Timer/Counter 1 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM1		((uint32_t)(1<<2))
+
+/** UART0 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART0  	((uint32_t)(1<<3))
+
+/** UART1 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART1  	((uint32_t)(1<<4))
+
+/** PWM0 power/clock control bit */
+#define CLKPWR_PCONP_PCPWM0		((uint32_t)(1<<5))
+
+/** PWM1 power/clock control bit */
+#define	CLKPWR_PCONP_PCPWM1		((uint32_t)(1<<6))
+
+/** The I2C0 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCI2C0		((uint32_t)(1<<7))
+
+/** UART4 power/clock control bit */
+#define CLKPWR_PCONP_PCUART4	((uint32_t)(1<<8))
+
+/** The RTC power/clock control bit */
+#define	CLKPWR_PCONP_PCRTC  	((uint32_t)(1<<9))
+
+/** The SSP1 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCSSP1	 	((uint32_t)(1<<10))
+
+/** External Memory controller power/clock control bit */
+#define CLKPWR_PCONP_PCEMC		((uint32_t)(1<<11))
+
+/** A/D converter 0 (ADC0) power/clock control bit */
+#define	CLKPWR_PCONP_PCADC  	((uint32_t)(1<<12))
+
+/** CAN Controller 1 power/clock control bit */
+#define	CLKPWR_PCONP_PCAN1  	((uint32_t)(1<<13))
+
+/** CAN Controller 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCAN2 	((uint32_t)(1<<14))
+
+/** GPIO power/clock control bit */
+#define	CLKPWR_PCONP_PCGPIO 	((uint32_t)(1<<15))
+
+/** Motor Control PWM */
+#define CLKPWR_PCONP_PCMCPWM 	((uint32_t)(1<<17))
+
+/** Quadrature Encoder Interface power/clock control bit */
+#define CLKPWR_PCONP_PCQEI 		((uint32_t)(1<<18))
+
+/** The I2C1 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCI2C1  	((uint32_t)(1<<19))
+
+/** The SSP2 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP2		((uint32_t)(1<<20))
+
+/** The SSP0 interface power/clock control bit */
+#define	CLKPWR_PCONP_PCSSP0		((uint32_t)(1<<21))
+
+/** Timer 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM2	((uint32_t)(1<<22))
+
+/** Timer 3 power/clock control bit */
+#define	CLKPWR_PCONP_PCTIM3	((uint32_t)(1<<23))
+
+/** UART 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART2  	((uint32_t)(1<<24))
+
+/** UART 3 power/clock control bit */
+#define	CLKPWR_PCONP_PCUART3  	((uint32_t)(1<<25))
+
+/** I2C interface 2 power/clock control bit */
+#define	CLKPWR_PCONP_PCI2C2	((uint32_t)(1<<26))
+
+/** I2S interface power/clock control bit*/
+#define	CLKPWR_PCONP_PCI2S  	((uint32_t)(1<<27))
+
+/** SD card interface power/clock control bit */
+#define CLKPWR_PCONP_PCSDC		((uint32_t)(1<<28))
+
+/** GP DMA function power/clock control bit*/
+#define	 CLKPWR_PCONP_PCGPDMA  	((uint32_t)(1<<29))
+
+/** Ethernet block power/clock control bit*/
+#define	 CLKPWR_PCONP_PCENET	((uint32_t)(1<<30))
+
+/** USB interface power/clock control bit*/
+#define	 CLKPWR_PCONP_PCUSB  	((uint32_t)(1<<31))
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+#define CLKPWR_RSTCON0_LCD		((uint32_t)(0))
+#define CLKPWR_RSTCON0_TIM0		((uint32_t)(1))
+#define CLKPWR_RSTCON0_TIM1		((uint32_t)(2))
+#define CLKPWR_RSTCON0_UART0	((uint32_t)(3))
+#define CLKPWR_RSTCON0_UART1	((uint32_t)(4))
+#define CLKPWR_RSTCON0_PWM0		((uint32_t)(5))
+#define CLKPWR_RSTCON0_PWM1		((uint32_t)(6))
+#define CLKPWR_RSTCON0_I2C0		((uint32_t)(7))
+#define CLKPWR_RSTCON0_UART4	((uint32_t)(8))
+#define CLKPWR_RSTCON0_RTC		((uint32_t)(9))
+#define CLKPWR_RSTCON0_SSP1		((uint32_t)(10))
+#define CLKPWR_RSTCON0_EMC		((uint32_t)(11))
+#define CLKPWR_RSTCON0_ADC		((uint32_t)(12))
+#define CLKPWR_RSTCON0_CAN1		((uint32_t)(13))
+#define CLKPWR_RSTCON0_CAN2		((uint32_t)(14))
+#define CLKPWR_RSTCON0_GPIO		((uint32_t)(15))
+#define CLKPWR_RSTCON0_MCPWM	((uint32_t)(17))
+#define CLKPWR_RSTCON0_QEI		((uint32_t)(18))
+#define CLKPWR_RSTCON0_I2C1		((uint32_t)(19))
+#define CLKPWR_RSTCON0_SSP2		((uint32_t)(20))
+#define CLKPWR_RSTCON0_SSP0		((uint32_t)(21))
+#define CLKPWR_RSTCON0_TIM2		((uint32_t)(22))
+#define CLKPWR_RSTCON0_TIM3		((uint32_t)(23))
+#define CLKPWR_RSTCON0_UART2	((uint32_t)(24))
+#define CLKPWR_RSTCON0_UART3	((uint32_t)(25))
+#define CLKPWR_RSTCON0_I2C2		((uint32_t)(26))
+#define CLKPWR_RSTCON0_I2S		((uint32_t)(27))
+#define CLKPWR_RSTCON0_SDC		((uint32_t)(28))
+#define CLKPWR_RSTCON0_GPDMA	((uint32_t)(29))
+#define CLKPWR_RSTCON0_ENET		((uint32_t)(30))
+#define CLKPWR_RSTCON0_USB		((uint32_t)(31))
+
+#define CLKPWR_RSTCON1_IOCON	((uint32_t)(32))
+#define CLKPWR_RSTCON1_DAC		((uint32_t)(33))
+#define CLKPWR_RSTCON1_CANACC	((uint32_t)(34))
+/**
+ * @}
+ */
+ 
+/* External clock variable from system_LPC177x_8x.h */
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  	*/
+extern uint32_t PeripheralClock;	 /*!< Peripheral Clock Frequency (Pclk) 	*/
+extern uint32_t EMCClock;		 /*!< EMC Clock Frequency                   	*/
+
+/* External clock variable from lpc177x_8x_clkpwr.h */
+extern uint32_t USBClock;		/*!< USB Frequency 								*/
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
+ * @{
+ */
+
+void CLKPWR_SetCLKDiv(uint8_t ClkType, uint8_t DivVal);
+uint32_t CLKPWR_GetCLK(uint8_t ClkType);
+void CLKPWR_ConfigPPWR(uint32_t PPType, FunctionalState NewState);
+void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState);
+void CLKPWR_Sleep(void);
+void CLKPWR_DeepSleep(void);
+void CLKPWR_PowerDown(void);
+void CLKPWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC177X_8X_CLKPWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
new file mode 100644
index 0000000000..54d493d50b
--- /dev/null
+++ b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
@@ -0,0 +1,348 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_pinsel.c			2011-06-02
+*//**
+* @file		lpc177x_8x_pinsel.c
+* @brief	Contains all functions support for Pin-connection block
+*			firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup PINSEL
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc177x_8x_pinsel.h"
+
+#define PINSEL_I2C_MODE_POS				(8)
+#define PINSEL_I2C_MODE_NUMBITS			(2)
+#define PINSEL_I2C_MODE_BITMASK			(0x03)
+
+#define PINSEL_BASIC_MODE_POS			(3)
+#define PINSEL_BASIC_MODE_NUMBITS		(2)
+#define PINSEL_BASIC_MODE_BITMASK		(0x03)
+
+#define PINSEL_DACEN_POS				(16)
+#define PINSEL_DACEN_BITMASK			(0x01)
+#define PINSEL_DACEN_NUMBITS			(1)
+
+#define PINSEL_GLITCH_FILTER_POS				(8)
+#define PINSEL_GLITCH_FILTER_BITMASK			(0x01)
+#define PINSEL_GLITCH_FILTER_NUMBITS			(1)
+
+#define PINSEL_ADMODE_POS				(7)
+#define PINSEL_ADMODE_BITMASK			(0x01)
+#define PINSEL_ADMODE_NUMBITS			(1)
+
+/* Private Functions ---------------------------------------------------------- */
+
+/*********************************************************************//**
+ * @brief		Get pointer to GPIO peripheral due to GPIO port
+ * @param[in]	portnum		Port Number value, should be in range from 0..3.
+ * @param[in]	pinnum		Pin number value, should be in range from 0..31
+ * @return		Pointer to GPIO peripheral
+ **********************************************************************/
+static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t)));
+	return pPIN;
+}
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup PINSEL_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief 		Setup the pin selection function
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	funcnum Function number, should be range: 0..7
+ * 				- 0: Select GPIO (Default)
+ * 				- 1: Selects the 1st alternate function
+ * 				- 2: Selects the 2nd alternate function
+ * 				...
+ *				- 7: Selects the 7th alternate function
+ * @return 		None
+ **********************************************************************/
+void PINSEL_ConfigPin ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	*pPIN &= 0x00000007;//Clear function bits
+	*pPIN |= funcnum;
+}
+
+
+/*********************************************************************//**
+ * @brief 		Setup resistor mode for each pin
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	modenum: Mode number, should be in range: 0..3
+				- IOCON_MODE_PLAIN: Plain output
+				- IOCON_MODE_PULLDOWN: Pull-down enable
+				- IOCON_MODE_PULLUP: Pull-up enable
+				- IOCON_MODE_REPEATER: Repeater mode
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetPinMode ( uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	*(uint32_t *)pPIN &= ~(3<<3);//Clear function bits
+	*(uint32_t *)pPIN |= modenum;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup hysteresis for each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Hysteresis mode, should be:
+ * 				- ENABLE: Hysteresis enable
+ * 				- DISABLE: Hysteresis disable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits
+	}
+	else
+		*(uint32_t *)pPIN |= IOCON_HYS;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup Slew rate for each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Slew rate control, should be:
+ * 				- ENABLE: Output slew rate control is enable
+ * 				- DISABLE: Output slew rate control is disable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits
+	}
+	else
+		*(uint32_t *)pPIN |= IOCON_SLEW;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup Input Buffer for each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Input buffer mode, should be:
+ * 				- ENABLE: The input buffer is enable
+ * 				- DISABLE: The input buffer is disable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetInBufMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits
+	}
+	else
+		*(uint32_t *)pPIN |= IOCON_INBUF;
+}
+
+/*********************************************************************//**
+ * @brief 		Setup I2CMode for only pins that provide special I2C functionality
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	I2CMode I2C mode, should be:
+ * 				- IOCON_I2CMODE_FAST: Fast mode and standard I2C mode
+ * 				- IOCON_I2CMODE_OPENDRAIN: Open drain I/O
+ * 				- IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O
+ * 				- IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	*(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS);
+	*(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS);
+}
+
+/*********************************************************************//**
+ * @brief 		Setup Open-drain mode in each pin
+ * @param[in]	portnum Port number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	NewState new state of Open-drain mode:
+ * 				- DISABLE: Normal pin I/O mode
+ * 				- ENABLE: Open-drain enable
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
+{
+	uint32_t *pPIN = NULL;
+	pPIN = PIN_GetPointer(portnum, pinnum);
+	if(NewState == DISABLE)
+	{
+		*(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits
+	}
+	else
+	{
+		*(uint32_t *)pPIN |= IOCON_ODMODE;
+	}
+}
+
+/*********************************************************************//**
+ * @brief 		Enable the Analog mode for each pin (default is as Digital pins)
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	enable: the state of the pin that is expected to run
+				- ENABLE: Enable the DAC mode of the pin
+				- DISABLE: Disable the DAC mode
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable)
+{
+	uint32_t *pPIN = NULL;
+
+	uint8_t condition = 0;
+
+	condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13))
+					| ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23))
+					| ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31));
+
+	if(!condition)
+	{
+		return;
+	}
+
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	//Clear this bit to set the pin to Analog mode
+	*(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS);
+
+	if(enable)
+	{
+
+	}
+	else
+	{
+		*(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one
+	}
+
+	return;
+}
+
+
+
+/*********************************************************************//**
+ * @brief 		Choose the DAC mode for each pin
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	enable: the state of the pin that is expected to run
+				- ENABLE: Enable the DAC mode of the pin
+				- DISABLE: Disable the DAC mode
+ * @return 		None
+ **********************************************************************/
+void PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable)
+{
+	uint32_t *pPIN = NULL;
+
+	// This setting is only for DAC pin (output pin)
+	if(!((portnum == 0) && (pinnum == 26)))
+	{
+		return;
+	}
+
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	//Clear DAC Enable function bits
+	*(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS);
+
+	if(enable)
+	{
+		*(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one
+	}
+	else
+	{
+
+	}
+
+	return;
+}
+
+/*********************************************************************//**
+ * @brief 		Control the glitch filter for each pin
+ * @param[in]	portnum PORT number, should be in range: 0..3
+ * @param[in]	pinnum	Pin number, should be in range: 0..31
+ * @param[in] 	enable: the state of the pin that is expected to run
+				- ENABLE: The noise pulses below approximately 10ns are filtered out
+				- DISABLE: No input filtering is done.
+ * @return 		None
+ **********************************************************************/
+void PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable)
+{
+	uint32_t *pPIN = NULL;
+
+	// This setting is only for DAC pin (output pin)
+	if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9))))
+	{
+		return;
+	}
+
+	pPIN = PIN_GetPointer(portnum, pinnum);
+
+	*(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0
+
+	//Clear Filter bits
+	*(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS);
+
+	if(!enable)
+	{
+		*(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one
+	}
+	else
+	{
+
+	}
+
+	*pPIN = *pPIN;
+
+	return;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
new file mode 100644
index 0000000000..ad8d93644e
--- /dev/null
+++ b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
@@ -0,0 +1,263 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_pinsel.h			2011-06-02
+*//**
+* @file		lpc177x_8x_pinsel.h
+* @brief	Contains all macro definitions and function prototypes
+*			support for Pin-connection block firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PINSEL	Pin Selection
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC177X_8X_PINSEL_H
+#define __LPC177X_8X_PINSEL_H
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC177x_8x.h"
+#include "lpc_types.h"
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Macros
+ * @{
+ */
+
+/* Macros define IOCON bits */
+#define IOCON_MODE_PLAIN			((0<<3))
+#define IOCON_MODE_PULLDOWN			((1<<3))
+#define IOCON_MODE_PULLUP			((2<<3))
+#define IOCON_MODE_REPEATER			((3<<3))
+#define IOCON_HYS					((1<<5))
+#define IOCON_SLEW					((1<<6))
+#define IOCON_INBUF					((1<<7))
+#define IOCON_I2CMODE_FAST			((0<<8))
+#define IOCON_I2CMODE_OPENDRAIN		((1<<8))
+#define IOCON_I2CMODE_FASTPLUS		((2<<8))
+#define IOCON_I2CMODE_HIGHOPENDRAIN	((3<<8))
+#define IOCON_ODMODE				((1<<10))
+
+
+/* Macros define for LOC registers */
+#define LOC_CAN_RD_1_P0_0			((0))	/**< Input for CAN_RD_1 comes from P0.0 */
+#define LOC_CAN_RD_1_P0_21			((1))	/**< Input for CAN_RD_1 comes from P0.21 */
+#define LOC_CAN_RD_2_P2_7			((0))	/**< Input for CAN_RD_2 comes from P2.7 */
+#define LOC_CAN_RD_2_P0_4			((1))	/**< Input for CAN_RD_2 comes from P0.4 */
+#define LOC_ENET_MDIO_P2_9			((0))	/**< Input for ENET_MDIO comes from P2.9 */
+#define LOC_ENET_MDIO_P1_17			((1))	/**< Input for ENET_MDIO comes from P1.17 */
+#define LOC_EINT_0_P0_29			((0))	/**< Input for EINT_0 comes from P0.29 */
+#define LOC_EINT_0_P2_10			((1))	/**< Input for EINT_0 comes from P2.10 */
+#define LOC_EINT_1_P0_30			((0))	/**< Input for EINT_1 comes from P0.30 */
+#define LOC_EINT_1_P2_11			((1))	/**< Input for EINT_1 comes from P2.11 */
+#define LOC_I2C0_SCL_P1_31			((0))	/**< Input for I2C0_SCL comes from P1.31 */
+#define LOC_I2C0_SCL_P0_28			((1))	/**< Input for I2C0_SCL comes from P0.28 */
+#define LOC_I2C0_SCL_P5_3			((2))	/**< Input for I2C0_SCL comes from P5.3 */
+#define LOC_I2C0_SDA_P1_30			((0))	/**< Input for I2C0_SDA comes from P1.30 */
+#define LOC_I2C0_SDA_P0_27			((1))	/**< Input for I2C0_SDA comes from P0.27 */
+#define LOC_I2C0_SDA_P5_2			((2))	/**< Input for I2C0_SDA comes from P5.2 */
+#define LOC_I2C1_SCL_P0_1			((0))	/**< Input for I2C1_SCL comes from P0.1 */
+#define LOC_I2C1_SCL_P2_15			((1))	/**< Input for I2C1_SCL comes from P2.15 */
+#define LOC_I2C1_SCL_P0_20			((2))	/**< Input for I2C1_SCL comes from P0.20 */
+#define LOC_I2C1_SDA_P2_14			((0))	/**< Input for I2C1_SDA comes from P2.14 */
+#define LOC_I2C1_SDA_P0_0			((1))	/**< Input for I2C1_SDA comes from P0.0 */
+#define LOC_I2C1_SDA_P0_19			((2))	/**< Input for I2C1_SDA comes from P0.19 */
+#define LOC_I2C2_SCL_P2_31			((0))	/**< Input for I2C2_SCL comes from P2.31 */
+#define LOC_I2C2_SCL_P0_11			((1))	/**< Input for I2C2_SCL comes from P0.11 */
+#define LOC_I2C2_SCL_P4_21			((2))	/**< Input for I2C2_SCL comes from P4.21 */
+#define LOC_I2C2_SCL_P4_29			((3))	/**< Input for I2C2_SCL comes from P4.29 */
+#define LOC_I2C2_SDA_P2_30			((0))	/**< Input for I2C2_SDA comes from P2.30 */
+#define LOC_I2C2_SDA_P0_10			((1))	/**< Input for I2C2_SDA comes from P0.10 */
+#define LOC_I2C2_SDA_P4_20			((2))	/**< Input for I2C2_SDA comes from P4.20 */
+#define LOC_I2C2_SDA_P1_15			((3))	/**< Input for I2C2_SDA comes from P1.15 */
+#define LOC_I2S_RX_SCK_P0_23		((0))	/**< Input for I2S_RX_SCK comes from P0.23 */
+#define LOC_I2S_RX_SCK_P0_4			((1))	/**< Input for I2S_RX_SCK comes from P0.4 */
+#define LOC_I2S_RX_SDA_P0_25		((0))	/**< Input for I2S_RX_SDA comes from P0.25 */
+#define LOC_I2S_RX_SDA_P0_6			((1))	/**< Input for I2S_RX_SDA comes from P0.6 */
+#define LOC_I2S_RX_WS_P0_24			((0))	/**< Input for I2S_RX_WS comes from P0.24 */
+#define LOC_I2S_RX_WS_P0_5			((1))	/**< Input for I2S_RX_WS comes from P0.5 */
+#define LOC_I2S_TX_SCK_P2_11		((0))	/**< Input for I2S_TX_SCK comes from P2.11 */
+#define LOC_I2S_TX_SCK_P0_7			((1))	/**< Input for I2S_TX_SCK comes from P0.7 */
+#define LOC_I2S_TX_WS_P2_12			((0))	/**< Input for I2S_TX_WS comes from P2.12 */
+#define LOC_I2S_TX_WS_P0_8			((1))	/**< Input for I2S_TX_WS comes from P0.8 */
+#define LOC_PWM0_CAP_0_P1_12		((0))	/**< Input for PWM0_CAP_0 comes from P1.12 */
+#define LOC_PWM0_CAP_0_P3_22		((1))	/**< Input for PWM0_CAP_0 comes from P3.22 */
+#define LOC_PWM1_CAP_0_P3_23		((0))	/**< Input for PWM1_CAP_0 comes from P3.23 */
+#define LOC_PWM1_CAP_0_P1_28		((1))	/**< Input for PWM1_CAP_0 comes from P1.28 */
+#define LOC_PWM1_CAP_0_P2_6			((2))	/**< Input for PWM1_CAP_0 comes from P2.6 */
+#define LOC_SD_CMD_P0_20			((0))	/**< Input for SD_CMD comes from P0.20 */
+#define LOC_SD_CMD_P1_3				((1))	/**< Input for SD_CMD comes from P1.3 */
+#define LOC_SD_DAT_0_P0_22			((0))	/**< Input for SD_DAT_0 comes from P0.22 */
+#define LOC_SD_DAT_0_P1_6			((1))	/**< Input for SD_DAT_0 comes from P1.6 */
+#define LOC_SD_DAT_1_P2_11			((0))	/**< Input for SD_DAT_1 comes from P2.11 */
+#define LOC_SD_DAT_1_P1_7			((1))	/**< Input for SD_DAT_1 comes from P1.7 */
+#define LOC_SD_DAT_2_P2_12			((0))	/**< Input for SD_DAT_2 comes from P2.12 */
+#define LOC_SD_DAT_2_P1_11			((1))	/**< Input for SD_DAT_2 comes from P1.11 */
+#define LOC_SD_DAT_3_P2_13			((0))	/**< Input for SD_DAT_3 comes from P2.13 */
+#define LOC_SD_DAT_3_P1_12			((1))	/**< Input for SD_DAT_3 comes from P1.12 */
+#define LOC_SSP0_MISO_P2_26			((0))	/**< Input for SSP0_MISO comes from P2.26 */
+#define LOC_SSP0_MISO_P1_23			((1))	/**< Input for SSP0_MISO comes from P1_23 */
+#define LOC_SSP0_MISO_P0_17			((2))	/**< Input for SSP0_MISO comes from P0_17 */
+#define LOC_SSP0_MOSI_P2_27			((0))	/**< Input for SSP0_MOSI comes from P2.27 */
+#define LOC_SSP0_MOSI_P1_24			((1))	/**< Input for SSP0_MOSI comes from P1.24 */
+#define LOC_SSP0_MOSI_P0_18			((2))	/**< Input for SSP0_MOSI comes from P0.18 */
+#define LOC_SSP0_SCK_P1_20			((0))	/**< Input for SSP0_SCK comes from P1.20 */
+#define LOC_SSP0_SCK_P2_22			((1))	/**< Input for SSP0_SCK comes from P2.22 */
+#define LOC_SSP0_SCK_P0_15			((2))	/**< Input for SSP0_SCK comes from P0_15 */
+#define LOC_SSP0_SSEL_P2_23			((0))	/**< Input for SSP0_SSEL comes from P2.23 */
+#define LOC_SSP0_SSEL_P1_21			((1))	/**< Input for SSP0_SSEL comes from P1.21 */
+#define LOC_SSP0_SSEL_P1_28			((2))	/**< Input for SSP0_SSEL comes from P1.28 */
+#define LOC_SSP0_SSEL_P0_16			((3))	/**< Input for SSP0_SSEL comes from P0.16 */
+#define LOC_SSP1_MISO_P0_12			((0))	/**< Input for SSP1_MISO comes from P0.12 */
+#define LOC_SSP1_MISO_P1_18			((1))	/**< Input for SSP1_MISO comes from P1.18 */
+#define LOC_SSP1_MISO_P4_22			((2))	/**< Input for SSP1_MISO comes from P4_22 */
+#define LOC_SSP1_MISO_P0_8			((3))	/**< Input for SSP1_MISO comes from P0.8 */
+#define LOC_SSP1_MOSI_P0_13			((0))	/**< Input for SSP1_MOSI comes from P0.13 */
+#define LOC_SSP1_MOSI_P1_22			((1))	/**< Input for SSP1_MOSI comes from P1.22 */
+#define LOC_SSP1_MOSI_P4_23			((2))	/**< Input for SSP1_MOSI comes from P4.23 */
+#define LOC_SSP1_MOSI_P0_9			((3))	/**< Input for SSP1_MOSI comes from P0.9 */
+#define LOC_SSP1_SCK_P1_31			((0))	/**< Input for SSP1_SCK comes from P1.31 */
+#define LOC_SSP1_SCK_P1_19			((1))	/**< Input for SSP1_SCK comes from P1.19 */
+#define LOC_SSP1_SCK_P4_20			((2))	/**< Input for SSP1_SCK comes from P4_20 */
+#define LOC_SSP1_SCK_P0_7			((3))	/**< Input for SSP1_SCK comes from P0_7 */
+#define LOC_SSP1_SSEL_P0_14			((0))	/**< Input for SSP1_SSEL comes from P0.14 */
+#define LOC_SSP1_SSEL_P1_26			((1))	/**< Input for SSP1_SSEL comes from P1.26 */
+#define LOC_SSP1_SSEL_P4_21			((2))	/**< Input for SSP1_SSEL comes from P4.21 */
+#define LOC_SSP1_SSEL_P0_6			((3))	/**< Input for SSP1_SSEL comes from P0.6 */
+#define LOC_SSP2_MISO_P1_4			((1))	/**< Input for SSP2_MISO comes from P1.4 */
+#define LOC_SSP2_MOSI_P1_1			((1))	/**< Input for SSP2_MOSI comes from P1.1 */
+#define LOC_SSP2_SCK_P1_0			((1))	/**< Input for SSP2_SCK comes from P1.0 */
+#define LOC_SSP2_SSEL_P1_8			((1))	/**< Input for SSP2_SSEL comes from P1.8 */
+#define LOC_T0_CAP_0_P3_23			((0))	/**< Input for T0_CAP_0 comes from P3.23 */
+#define LOC_T0_CAP_0_P1_26			((1))	/**< Input for T0_CAP_0 comes from P1.26 */
+#define LOC_T0_CAP_1_P3_24			((0))	/**< Input for T0_CAP_1 comes from P3.24 */
+#define LOC_T0_CAP_1_P1_27			((1))	/**< Input for T0_CAP_1 comes from P1.27 */
+#define LOC_T1_CAP_0_P1_18			((0))	/**< Input for T1_CAP_0 comes from P1.18 */
+#define LOC_T1_CAP_0_P3_27			((1))	/**< Input for T1_CAP_0 comes from P3.27 */
+#define LOC_T1_CAP_1_P3_28			((0))	/**< Input for T1_CAP_1 comes from P3.28 */
+#define LOC_T1_CAP_1_P1_19			((1))	/**< Input for T1_CAP_1 comes from P1.19 */
+#define LOC_T2_CAP_0_P2_14			((0))	/**< Input for T2_CAP_0 comes from P2.14 */
+#define LOC_T2_CAP_0_P2_6			((1))	/**< Input for T2_CAP_0 comes from P2.6 */
+#define LOC_T2_CAP_0_P0_4			((2))	/**< Input for T2_CAP_0 comes from P0.4 */
+#define LOC_T2_CAP_0_P1_14			((3))	/**< Input for T2_CAP_0 comes from P1.14 */
+#define LOC_T2_CAP_1_P2_15			((0))	/**< Input for T2_CAP_1 comes from P2.15 */
+#define LOC_T2_CAP_1_P0_5			((1))	/**< Input for T2_CAP_1 comes from P0.5 */
+#define LOC_T3_CAP_0_P0_23			((0))	/**< Input for T3_CAP_0 comes from P0.23 */
+#define LOC_T3_CAP_0_P2_22			((1))	/**< Input for T3_CAP_0 comes from P2.22 */
+#define LOC_T3_CAP_0_P1_10			((2))	/**< Input for T3_CAP_0 comes from P1.10 */
+#define LOC_T3_CAP_1_P0_24			((0))	/**< Input for T3_CAP_1 comes from P0.24 */
+#define LOC_T3_CAP_1_P2_23			((1))	/**< Input for T3_CAP_1 comes from P2.23 */
+#define LOC_T3_CAP_1_P1_0			((2))	/**< Input for T3_CAP_1 comes from P1.0 */
+#define LOC_U0_RXD_P0_1				((0))	/**< Input for U0_RXD comes from P0.1 */
+#define LOC_U0_RXD_P0_3				((1))	/**< Input for U0_RXD comes from P0.3 */
+#define LOC_U1_CTS_P0_17			((0))	/**< Input for U1_CTS comes from P0.17 */
+#define LOC_U1_CTS_P2_8				((1))	/**< Input for U1_CTS comes from P2.8 */
+#define LOC_U1_CTS_P2_2				((2))	/**< Input for U1_CTS comes from P2.2 */
+#define LOC_U1_CTS_P3_18			((3))	/**< Input for U1_CTS comes from P3.18 */
+#define LOC_U1_DCD_P0_18			((0))	/**< Input for U1_DCD comes from P0.18 */
+#define LOC_U1_DCD_P2_3				((1))	/**< Input for U1_DCD comes from P2.3 */
+#define LOC_U1_DCD_P3_19			((2))	/**< Input for U1_DCD comes from P3_19 */
+#define LOC_U1_DSR_P0_19			((0))	/**< Input for U1_DSR comes from P0.19 */
+#define LOC_U1_DSR_P2_4				((1))	/**< Input for U1_DSR comes from P2.4 */
+#define LOC_U1_DSR_P3_20			((2))	/**< Input for U1_DSR comes from P0.19 */
+#define LOC_U1_RI_P0_21				((0))	/**< Input for U1_RI comes from P0.21 */
+#define LOC_U1_RI_P2_6				((1))	/**< Input for U1_RI comes from P2.6 */
+#define LOC_U1_RI_P3_22				((2))	/**< Input for U1_RI comes from P3.22 */
+#define LOC_U1_RXD_P0_16			((0))	/**< Input for U1_RXD comes from P0.16 */
+#define LOC_U1_RXD_P3_17			((1))	/**< Input for U1_RXD comes from P3.17 */
+#define LOC_U1_RXD_P2_1				((2))	/**< Input for U1_RXD comes from P2.1 */
+#define LOC_U2_RXD_P0_11			((0))	/**< Input for U2_RXD comes from P0.11 */
+#define LOC_U2_RXD_P4_23			((1))	/**< Input for U2_RXD comes from P4.23 */
+#define LOC_U2_RXD_P2_9				((2))	/**< Input for U2_RXD comes from P2.9 */
+#define LOC_U3_RXD_P0_26			((0))	/**< Input for U3_RXD comes from P0.26 */
+#define LOC_U3_RXD_P0_1				((1))	/**< Input for U3_RXD comes from P0.1 */
+#define LOC_U3_RXD_P4_29			((2))	/**< Input for U3_RXD comes from P4.29 */
+#define LOC_U3_RXD_P0_3				((3))	/**< Input for U3_RXD comes from P0.3 */
+#define LOC_U4_RXD_P2_9				((0))	/**< Input for U4_RXD comes from P2.9 */
+#define LOC_U4_RXD_P5_3				((1))	/**< Input for U4_RXD comes from P5.3 */
+#define LOC_USB_SCL_P0_28			((0))	/**< Input for USB_SCL comes from P0.28 */
+#define LOC_USB_SCL_P1_28			((1))	/**< Input for USB_SCL comes from P1.28 */
+#define LOC_USB_SDA_P0_27			((0))	/**< Input for USB_SDA comes from P0.27 */
+#define LOC_USB_SDA_P1_29			((1))	/**< Input for USB_SDA comes from P1.29 */
+
+/**
+ * @}
+ */
+
+/** @defgroup PINSEL_Public_Types PINSEL Public Types
+ * @{
+ */
+ 
+
+typedef enum
+{
+	PINSEL_BASICMODE_PLAINOUT  = 0,	/**< Plain output */
+	PINSEL_BASICMODE_PULLDOWN,		/**< Pull-down enabled */
+  	PINSEL_BASICMODE_PULLUP,		/**< Pull-up enabled (default) */
+	PINSEL_BASICMODE_REPEATER		/**< Repeater mode */
+}PinSel_BasicMode;
+
+typedef enum
+{
+	/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
+	PINSEL_I2CMODE_FAST_STANDARD  = 0,
+	/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
+	PINSEL_I2CMODE_OPENDRAINIO,
+	/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
+	PINSEL_I2CMODE_FASTMODEPLUS,
+	/** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
+	PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
+}PinSel_I2cMode;
+
+/**
+ * @}
+ */
+ 
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Functions
+ * @{
+ */
+void PINSEL_ConfigPin(uint8_t portnum, uint8_t pinnum, uint8_t funcnum);
+void PINSEL_SetPinMode(uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum);
+void PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetInBufMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode);
+void PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
+void PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable);
+void PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable);
+void PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
+
+
+/**
+ * @}
+ */
+
+#endif /* LPC177x_8x_PINSEL_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_uart.c b/bsp/lpc178x/drivers/lpc177x_8x_uart.c
new file mode 100644
index 0000000000..bd6129b0fd
--- /dev/null
+++ b/bsp/lpc178x/drivers/lpc177x_8x_uart.c
@@ -0,0 +1,1370 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_uart.c			2011-06-02
+*//**
+* @file		lpc177x_8x_uart.c
+* @brief	Contains all functions support for UART firmware library
+*			on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup UART
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc177x_8x_uart.h"
+#include "lpc177x_8x_clkpwr.h"
+
+/* Private Functions ---------------------------------------------------------- */
+
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate);
+
+
+/*********************************************************************//**
+ * @brief		Determines best dividers to get a target clock rate
+ * @param[in]	UARTx	Pointer to selected UART peripheral, should be:
+ * 				- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	baudrate Desired UART baud rate.
+ * @return 		Error status, could be:
+ * 				- SUCCESS
+ * 				- ERROR
+ **********************************************************************/
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
+{
+	Status errorStatus = ERROR;
+
+	uint32_t uClk;
+	uint32_t d, m, bestd, bestm, tmp;
+	uint64_t best_divisor, divisor;
+	uint32_t current_error, best_error;
+	uint32_t recalcbaud;
+
+	/* get UART block clock */
+	uClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
+
+	/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
+	* The formula is :
+	* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
+	* It involves floating point calculations. That's the reason the formulae are adjusted with
+	* Multiply and divide method.*/
+	
+	/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
+	* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
+	best_error = 0xFFFFFFFF; /* Worst case */
+	bestd = 0;
+	bestm = 0;
+	best_divisor = 0;
+	
+	for (m = 1 ; m <= 15 ;m++)
+	{
+		for (d = 0 ; d < m ; d++)
+		{
+			divisor = ((uint64_t)uClk << 28)*m / (baudrate*(m+d));
+			current_error = divisor & 0xFFFFFFFF;
+
+			tmp = divisor>>32;
+
+			/* Adjust error */
+			if(current_error > ((uint32_t)1<<31))
+			{
+				current_error = -current_error;
+				tmp++;
+			}
+
+			/* Out of range */
+			if(tmp < 1 || tmp > 65536)
+				continue;
+
+			if( current_error < best_error)
+			{
+				best_error = current_error;
+				best_divisor = tmp;
+				bestd = d;
+				bestm = m;
+				
+				if(best_error == 0) 
+					break;
+			}
+		} /* end of inner for loop */
+
+		if (best_error == 0)
+			break;
+	} /* end of outer for loop  */
+
+	/* can not find best match */
+	if(best_divisor == 0) 
+		return ERROR;
+
+	recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
+
+	/* reuse best_error to evaluate baud error*/
+	if(baudrate > recalcbaud) 
+		best_error = baudrate - recalcbaud;
+	else 
+		best_error = recalcbaud -baudrate;
+
+	best_error = best_error * 100 / baudrate;
+
+	if (best_error < UART_ACCEPTED_BAUDRATE_ERROR)
+	{
+		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+			
+			((LPC_UART1_TypeDef *)UARTx)->DLM = UART_LOAD_DLM(best_divisor);
+			
+			((LPC_UART1_TypeDef *)UARTx)->DLL = UART_LOAD_DLL(best_divisor);
+			
+			/* Then reset DLAB bit */
+			((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+			
+			((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(bestm)
+													| UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+		}
+		else
+		{
+			UARTx->LCR |= UART_LCR_DLAB_EN;
+			
+			UARTx->DLM = UART_LOAD_DLM(best_divisor);
+			
+			UARTx->DLL = UART_LOAD_DLL(best_divisor);
+			
+			/* Then reset DLAB bit */
+			UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+			
+			UARTx->FDR = (UART_FDR_MULVAL(bestm) \
+							| UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+		}
+		errorStatus = SUCCESS;
+	}
+
+	return errorStatus;
+}
+
+/* End of Private Functions ---------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup UART_Public_Functions
+ * @{
+ */
+/* UART Init/DeInit functions -------------------------------------------------*/
+/********************************************************************//**
+ * @brief		Initializes the UARTx peripheral according to the specified
+ *               parameters in the UART_ConfigStruct.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ *				- LPC_UART4: UART4 peripheral
+ * @param[in]	UART_ConfigStruct Pointer to a UART_CFG_Type structure
+*                    that contains the configuration information for the
+*                    specified UART peripheral.
+ * @return 		None
+ *********************************************************************/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct)
+{
+	uint32_t tmp;
+
+	if(UARTx == LPC_UART0)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
+	}
+	if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
+	}
+	if(UARTx == LPC_UART2)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
+	}
+	if(UARTx == LPC_UART3)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
+	}
+
+	/* FIFOs are empty */
+	UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
+
+	// Disable FIFO
+	UARTx->FCR = 0;
+
+	// Dummy reading
+	while (UARTx->LSR & UART_LSR_RDR)
+	{
+		tmp = UARTx->RBR;
+	}
+
+	UARTx->TER = UART_TER_TXEN;
+
+	// Wait for current transmit complete
+	while (!(UARTx->LSR & UART_LSR_THRE));
+
+	// Disable Tx
+	UARTx->TER = 0;
+
+	// Disable interrupt
+	UARTx->IER = 0;
+
+	// Set LCR to default state
+	UARTx->LCR = 0;
+
+	// Set ACR to default state
+	UARTx->ACR = 0;
+
+	// Set RS485 control to default state
+	UARTx->RS485CTRL = 0;
+
+	// Set RS485 delay timer to default state
+	UARTx->RS485DLY = 0;
+
+	// Set RS485 addr match to default state
+	UARTx->ADRMATCH = 0;
+
+	// Dummy reading
+	tmp = UARTx->LSR;
+
+	if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		// Set Modem Control to default state
+		((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
+
+		//Dummy Reading to Clear Status
+		tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
+	}
+	else
+	{
+		// Set IrDA to default state for all UART other than UART1
+		UARTx->ICR = 0;
+	}
+
+	// Set Line Control register ----------------------------
+
+	uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
+
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \
+													& UART_LCR_BITMASK;
+	}
+	else
+	{
+		tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
+	}
+
+	switch (UART_ConfigStruct->Databits)
+	{
+		case UART_DATABIT_5:
+			tmp |= UART_LCR_WLEN5;
+			break;
+
+		case UART_DATABIT_6:
+			tmp |= UART_LCR_WLEN6;
+			break;
+
+		case UART_DATABIT_7:
+			tmp |= UART_LCR_WLEN7;
+			break;
+
+		case UART_DATABIT_8:
+
+		default:
+			tmp |= UART_LCR_WLEN8;
+			break;
+	}
+
+	if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
+	{
+		// Do nothing...
+	}
+	else
+	{
+		tmp |= UART_LCR_PARITY_EN;
+		switch (UART_ConfigStruct->Parity)
+		{
+			case UART_PARITY_ODD:
+				tmp |= UART_LCR_PARITY_ODD;
+				break;
+
+			case UART_PARITY_EVEN:
+				tmp |= UART_LCR_PARITY_EVEN;
+				break;
+
+			case UART_PARITY_SP_1:
+				tmp |= UART_LCR_PARITY_F_1;
+				break;
+
+			case UART_PARITY_SP_0:
+				tmp |= UART_LCR_PARITY_F_0;
+				break;
+
+			default:
+				break;
+		}
+	}
+
+	switch (UART_ConfigStruct->Stopbits)
+	{
+		case UART_STOPBIT_2:
+			tmp |= UART_LCR_STOPBIT_SEL;
+			break;
+
+		case UART_STOPBIT_1:
+
+		default:
+			// Do no thing
+			break;
+	}
+
+
+	// Write back to LCR, configure FIFO and Disable Tx
+	if (((LPC_UART1_TypeDef *)UARTx) ==  LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+	}
+	else
+	{
+		UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+	}
+}
+
+/*********************************************************************//**
+ * @brief		De-initializes the UARTx peripheral registers to their
+ *                  default reset values.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return 		None
+ **********************************************************************/
+void UART_DeInit(LPC_UART_TypeDef* UARTx)
+{
+	UART_TxCmd(UARTx, DISABLE);
+
+	if (UARTx == LPC_UART0)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
+	}
+
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
+	}
+
+	if (UARTx == LPC_UART2)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
+	}
+
+	if (UARTx == LPC_UART3)
+	{
+		/* Set up clock and power for UART module */
+		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
+	}
+}
+
+/*****************************************************************************//**
+* @brief		Fills each UART_InitStruct member with its default value:
+* 				- 9600 bps
+* 				- 8-bit data
+* 				- 1 Stopbit
+* 				- None Parity
+* @param[in]	UART_InitStruct Pointer to a UART_CFG_Type structure
+*                    which will be initialized.
+* @return		None
+*******************************************************************************/
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
+{
+	UART_InitStruct->Baud_rate = 9600;
+
+	UART_InitStruct->Databits = UART_DATABIT_8;
+
+	UART_InitStruct->Parity = UART_PARITY_NONE;
+
+	UART_InitStruct->Stopbits = UART_STOPBIT_1;
+}
+
+/* UART Send/Recieve functions -------------------------------------------------*/
+/*********************************************************************//**
+ * @brief		Transmit a single data through UART peripheral
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	Data	Data to transmit (must be 8-bit long)
+ * @return 		None
+ **********************************************************************/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->THR = Data & UART_THR_MASKBIT;
+	}
+	else
+	{
+		UARTx->THR = Data & UART_THR_MASKBIT;
+	}
+
+}
+
+
+/*********************************************************************//**
+ * @brief		Receive a single data from UART peripheral
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return 		Data received
+ **********************************************************************/
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		return (((LPC_UART1_TypeDef *)UARTx)->RBR & UART_RBR_MASKBIT);
+	}
+	else
+	{
+		return (UARTx->RBR & UART_RBR_MASKBIT);
+	}
+}
+
+/*********************************************************************//**
+ * @brief		Send a block of data via UART peripheral
+ * @param[in]	UARTx	Selected UART peripheral used to send data, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	txbuf 	Pointer to Transmit buffer
+ * @param[in]	buflen 	Length of Transmit buffer
+ * @param[in] 	flag 	Flag used in  UART transfer, should be
+ * 						NONE_BLOCKING or BLOCKING
+ * @return 		Number of bytes sent.
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+							uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+	uint32_t bToSend, bSent, timeOut, fifo_cnt;
+	uint8_t *pChar = txbuf;
+
+	bToSend = buflen;
+
+	// blocking mode
+	if (flag == BLOCKING)
+	{
+		bSent = 0;
+		while (bToSend)
+		{
+			timeOut = UART_BLOCKING_TIMEOUT;
+
+			// Wait for THR empty with timeout
+			while (!(UARTx->LSR & UART_LSR_THRE))
+			{
+				if (timeOut == 0)
+					break;
+
+				timeOut--;
+			}
+
+			// Time out!
+			if(timeOut == 0)
+				break;
+
+			fifo_cnt = UART_TX_FIFO_SIZE;
+
+			while (fifo_cnt && bToSend)
+			{
+				UART_SendByte(UARTx, (*pChar++));
+
+				fifo_cnt--;
+
+				bToSend--;
+
+				bSent++;
+			}
+		}
+	}
+
+	// None blocking mode
+	else
+	{
+		bSent = 0;
+		while (bToSend)
+		{
+			if (bToSend == 0)
+				break;
+
+			if (!(UARTx->LSR & UART_LSR_THRE))
+			{
+				break;
+			}
+
+			fifo_cnt = UART_TX_FIFO_SIZE;
+
+			while (fifo_cnt && bToSend)
+			{
+				UART_SendByte(UARTx, (*pChar++));
+
+				bToSend--;
+
+				fifo_cnt--;
+
+				bSent++;
+			}
+		}
+	}
+
+	return bSent;
+}
+
+/*********************************************************************//**
+ * @brief		Receive a block of data via UART peripheral
+ * @param[in]	UARTx	Selected UART peripheral used to send data,
+ * 				should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[out]	rxbuf 	Pointer to Received buffer
+ * @param[in]	buflen 	Length of Received buffer
+ * @param[in] 	flag 	Flag mode, should be NONE_BLOCKING or BLOCKING
+
+ * @return 		Number of bytes received
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf,
+								uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+	uint32_t bToRecv, bRecv, timeOut;
+	uint8_t *pChar = rxbuf;
+
+	bToRecv = buflen;
+
+	// Blocking mode
+	if (flag == BLOCKING)
+	{
+		bRecv = 0;
+		while (bToRecv)
+		{
+			timeOut = UART_BLOCKING_TIMEOUT;
+			while (!(UARTx->LSR & UART_LSR_RDR))
+			{
+				if (timeOut == 0)
+					break;
+
+				timeOut--;
+			}
+
+			// Time out!
+			if(timeOut == 0)
+				break;
+
+			// Get data from the buffer
+			(*pChar++) = UART_ReceiveByte(UARTx);
+
+			bToRecv--;
+
+			bRecv++;
+		}
+	}
+	// None blocking mode
+	else
+	{
+		bRecv = 0;
+		while (bToRecv)
+		{
+			if (!(UARTx->LSR & UART_LSR_RDR))
+			{
+				break;
+			}
+			else
+			{
+				(*pChar++) = UART_ReceiveByte(UARTx);
+
+				bRecv++;
+
+				bToRecv--;
+			}
+		}
+	}
+
+	return bRecv;
+}
+
+/*********************************************************************//**
+ * @brief		Force BREAK character on UART line, output pin UARTx TXD is
+				forced to logic 0.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return 		None
+ **********************************************************************/
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN;
+	}
+	else
+	{
+		UARTx->LCR |= UART_LCR_BREAK_EN;
+	}
+}
+
+
+/********************************************************************//**
+ * @brief 		Enable or disable specified UART interrupt.
+ * @param[in]	UARTx	UART peripheral selected, should be
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	UARTIntCfg	Specifies the interrupt flag,
+ * 				should be one of the following:
+				- UART_INTCFG_RBR 	:  RBR Interrupt enable
+				- UART_INTCFG_THRE 	:  THR Interrupt enable
+				- UART_INTCFG_RLS 	:  RX line status interrupt enable
+				- UART1_INTCFG_MS	:  Modem status interrupt enable (UART1 only)
+				- UART1_INTCFG_CTS	:  CTS1 signal transition interrupt enable (UART1 only)
+				- UART_INTCFG_ABEO 	:  Enables the end of auto-baud interrupt
+				- UART_INTCFG_ABTO 	:  Enables the auto-baud time-out interrupt
+ * @param[in]	NewState New state of specified UART interrupt type,
+ * 				should be:
+ * 				- ENALBE: Enable this UART interrupt type.
+* 				- DISALBE: Disable this UART interrupt type.
+ * @return 		None
+ *********************************************************************/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
+{
+	uint32_t tmp;
+
+	switch(UARTIntCfg)
+	{
+		case UART_INTCFG_RBR:
+			tmp = UART_IER_RBRINT_EN;
+			break;
+
+		case UART_INTCFG_THRE:
+			tmp = UART_IER_THREINT_EN;
+			break;
+
+		case UART_INTCFG_RLS:
+			tmp = UART_IER_RLSINT_EN;
+			break;
+
+		case UART1_INTCFG_MS:
+			tmp = UART1_IER_MSINT_EN;
+			break;
+
+		case UART1_INTCFG_CTS:
+			tmp = UART1_IER_CTSINT_EN;
+			break;
+
+		case UART_INTCFG_ABEO:
+			tmp = UART_IER_ABEOINT_EN;
+			break;
+
+		case UART_INTCFG_ABTO:
+			tmp = UART_IER_ABTOINT_EN;
+			break;
+	}
+
+	if (NewState == ENABLE)
+	{
+		if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->IER |= tmp;
+		}
+		else
+		{
+			UARTx->IER |= tmp;
+		}
+	}
+	else
+	{
+		if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->IER &= (~tmp) & UART1_IER_BITMASK;
+		}
+		else
+		{
+			UARTx->IER &= (~tmp) & UART_IER_BITMASK;
+		}
+	}
+}
+
+
+/********************************************************************//**
+ * @brief 		Get current value of Line Status register in UART peripheral.
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return		Current value of Line Status register in UART peripheral.
+ * Note:	The return value of this function must be ANDed with each member in
+ * 			UART_LS_Type enumeration to determine current flag status
+ * 			corresponding to each Line status type. Because some flags in
+ * 			Line Status register will be cleared after reading, the next reading
+ * 			Line Status register could not be correct. So this function used to
+ * 			read Line status register in one time only, then the return value
+ * 			used to check all flags.
+ *********************************************************************/
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
+	}
+	else
+	{
+		return ((UARTx->LSR) & UART_LSR_BITMASK);
+	}
+}
+
+/********************************************************************//**
+ * @brief 		Get Interrupt Identification value
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return		Current value of UART UIIR register in UART peripheral.
+ *********************************************************************/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx)
+{
+	return (UARTx->IIR & 0x03CF);
+}
+
+/*********************************************************************//**
+ * @brief		Check whether if UART is busy or not
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @return		RESET if UART is not busy, otherwise return SET.
+ **********************************************************************/
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
+{
+	if (UARTx->LSR & UART_LSR_TEMT)
+	{
+		return RESET;
+	}
+	else
+	{
+		return SET;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Configure FIFO function on selected UART peripheral
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *  			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	FIFOCfg	Pointer to a UART_FIFO_CFG_Type Structure that
+ * 						contains specified information about FIFO configuration
+ * @return 		none
+ **********************************************************************/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
+{
+	uint8_t tmp = 0;
+
+	tmp |= UART_FCR_FIFO_EN;
+
+	switch (FIFOCfg->FIFO_Level)
+	{
+		case UART_FIFO_TRGLEV0:
+			tmp |= UART_FCR_TRG_LEV0;
+			break;
+
+		case UART_FIFO_TRGLEV1:
+			tmp |= UART_FCR_TRG_LEV1;
+			break;
+
+		case UART_FIFO_TRGLEV2:
+			tmp |= UART_FCR_TRG_LEV2;
+			break;
+
+		case UART_FIFO_TRGLEV3:
+
+		default:
+			tmp |= UART_FCR_TRG_LEV3;
+			break;
+	}
+
+	if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
+	{
+		tmp |= UART_FCR_TX_RS;
+	}
+
+	if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
+	{
+		tmp |= UART_FCR_RX_RS;
+	}
+
+	if (FIFOCfg->FIFO_DMAMode == ENABLE)
+	{
+		tmp |= UART_FCR_DMAMODE_SEL;
+	}
+
+
+	//write to FIFO control register
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		((LPC_UART1_TypeDef *)UARTx)->FCR = tmp & UART_FCR_BITMASK;
+	}
+	else
+	{
+		UARTx->FCR = tmp & UART_FCR_BITMASK;
+	}
+}
+
+/*****************************************************************************//**
+* @brief		Fills each UART_FIFOInitStruct member with its default value:
+* 				- FIFO_DMAMode = DISABLE
+* 				- FIFO_Level = UART_FIFO_TRGLEV0
+* 				- FIFO_ResetRxBuf = ENABLE
+* 				- FIFO_ResetTxBuf = ENABLE
+* 				- FIFO_State = ENABLE
+
+* @param[in]	UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
+*                    which will be initialized.
+* @return		None
+*******************************************************************************/
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
+{
+	UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
+
+	UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
+
+	UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
+
+	UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
+}
+
+
+/*********************************************************************//**
+ * @brief		Start/Stop Auto Baudrate activity
+ * @param[in]	UARTx	UART peripheral selected, should be
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	ABConfigStruct	A pointer to UART_AB_CFG_Type structure that
+ * 								contains specified information about UART
+ * 								auto baudrate configuration
+ * @param[in]	NewState New State of Auto baudrate activity, should be:
+ * 				- ENABLE: Start this activity
+ *				- DISABLE: Stop this activity
+ * Note:		Auto-baudrate mode enable bit will be cleared once this mode
+ * 				completed.
+ * @return 		none
+ **********************************************************************/
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct,
+							FunctionalState NewState)
+{
+	uint32_t tmp;
+
+	tmp = 0;
+	if (NewState == ENABLE)
+	{
+		if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1)
+		{
+			tmp |= UART_ACR_MODE;
+		}
+		if (ABConfigStruct->AutoRestart == ENABLE)
+		{
+			tmp |= UART_ACR_AUTO_RESTART;
+		}
+	}
+
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		if (NewState == ENABLE)
+		{
+			// Clear DLL and DLM value
+			((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+
+			((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
+
+			((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
+
+			((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
+
+			// FDR value must be reset to default value
+			((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
+
+			((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp;
+		}
+		else
+		{
+			((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
+		}
+	}
+	else
+	{
+		if (NewState == ENABLE)
+		{
+			// Clear DLL and DLM value
+			UARTx->LCR |= UART_LCR_DLAB_EN;
+
+			UARTx->DLL = 0;
+
+			UARTx->DLM = 0;
+
+			UARTx->LCR &= ~UART_LCR_DLAB_EN;
+
+			// FDR value must be reset to default value
+			UARTx->FDR = 0x10;
+
+			UARTx->ACR = UART_ACR_START | tmp;
+		}
+		else
+		{
+			UARTx->ACR = 0;
+		}
+	}
+}
+
+/*********************************************************************//**
+ * @brief		Clear Autobaud Interrupt Pending
+ * @param[in]	UARTx	UART peripheral selected, should be
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	ABIntType	type of auto-baud interrupt, should be:
+ * 				- UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
+ * 				- UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
+ * @return 		none
+ **********************************************************************/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType)
+{
+	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+	{
+		UARTx->ACR |= ABIntType;
+	}
+	else
+		UARTx->ACR |= ABIntType;
+}
+
+/*********************************************************************//**
+ * @brief		Enable/Disable transmission on UART TxD pin
+ * @param[in]	UARTx	UART peripheral selected, should be:
+ *   			- LPC_UART0: UART0 peripheral
+ * 				- LPC_UART1: UART1 peripheral
+ * 				- LPC_UART2: UART2 peripheral
+ * 				- LPC_UART3: UART3 peripheral
+ * @param[in]	NewState New State of Tx transmission function, should be:
+ * 				- ENABLE: Enable this function
+				- DISABLE: Disable this function
+ * @return none
+ **********************************************************************/
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN;
+		}
+		else
+		{
+			UARTx->TER |= UART_TER_TXEN;
+		}
+	}
+	else
+	{
+		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+		{
+			((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+		}
+		else
+		{
+			UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+		}
+	}
+}
+
+/* UART IrDA functions ---------------------------------------------------*/
+/*********************************************************************//**
+ * @brief		Enable or disable inverting serial input function of IrDA
+ * 				on UART peripheral.
+ * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]	NewState New state of inverting serial input, should be:
+ * 				- ENABLE: Enable this function.
+ * 				- DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		UARTx->ICR |= UART_ICR_IRDAINV;
+	}
+	else if (NewState == DISABLE)
+	{
+		UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Enable or disable IrDA function on UART peripheral.
+ * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]	NewState New state of IrDA function, should be:
+ * 				- ENABLE: Enable this function.
+ * 				- DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		UARTx->ICR |= UART_ICR_IRDAEN;
+	}
+	else
+	{
+		UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Configure Pulse divider for IrDA function on UART peripheral.
+ * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]	PulseDiv Pulse Divider value from Peripheral clock,
+ * 				should be one of the following:
+				- UART_IrDA_PULSEDIV2 	: Pulse width = 2 * Tpclk
+				- UART_IrDA_PULSEDIV4 	: Pulse width = 4 * Tpclk
+				- UART_IrDA_PULSEDIV8 	: Pulse width = 8 * Tpclk
+				- UART_IrDA_PULSEDIV16 	: Pulse width = 16 * Tpclk
+				- UART_IrDA_PULSEDIV32 	: Pulse width = 32 * Tpclk
+				- UART_IrDA_PULSEDIV64 	: Pulse width = 64 * Tpclk
+				- UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
+				- UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
+
+ * @return none
+ **********************************************************************/
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
+{
+	uint32_t tmp, tmp1;
+
+	tmp1 = UART_ICR_PULSEDIV(PulseDiv);
+
+	tmp = UARTx->ICR & (~ UART_ICR_PULSEDIV(7));
+
+	tmp |= tmp1 | UART_ICR_FIXPULSE_EN;
+
+	UARTx->ICR = tmp & UART_ICR_BITMASK;
+}
+
+/* UART1 FullModem function ---------------------------------------------*/
+
+/*********************************************************************//**
+ * @brief		Force pin DTR/RTS corresponding to given state (Full modem mode)
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	Pin	Pin that NewState will be applied to, should be:
+ * 				- UART1_MODEM_PIN_DTR: DTR pin.
+ * 				- UART1_MODEM_PIN_RTS: RTS pin.
+ * @param[in]	NewState New State of DTR/RTS pin, should be:
+ * 				- INACTIVE: Force the pin to inactive signal.
+				- ACTIVE: Force the pin to active signal.
+ * @return none
+ **********************************************************************/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx,
+													UART_MODEM_PIN_Type Pin,
+													UART1_SignalState NewState)
+{
+	uint8_t tmp = 0;
+
+	switch (Pin)
+	{
+		case UART1_MODEM_PIN_DTR:
+			tmp = UART1_MCR_DTR_CTRL;
+			break;
+
+		case UART1_MODEM_PIN_RTS:
+			tmp = UART1_MCR_RTS_CTRL;
+			break;
+
+		default:
+			break;
+	}
+
+	if (NewState == ACTIVE)
+	{
+		UARTx->MCR |= tmp;
+	}
+	else
+	{
+		UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Configure Full Modem mode for UART peripheral
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	Mode Full Modem mode, should be:
+ * 				- UART1_MODEM_MODE_LOOPBACK: Loop back mode.
+ * 				- UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
+ * 				- UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
+ * @param[in]	NewState New State of this mode, should be:
+ * 				- ENABLE: Enable this mode.
+				- DISABLE: Disable this mode.
+ * @return none
+ **********************************************************************/
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode,
+											FunctionalState NewState)
+{
+	uint8_t tmp;
+
+	switch(Mode)
+	{
+		case UART1_MODEM_MODE_LOOPBACK:
+			tmp = UART1_MCR_LOOPB_EN;
+			break;
+
+		case UART1_MODEM_MODE_AUTO_RTS:
+			tmp = UART1_MCR_AUTO_RTS_EN;
+			break;
+
+		case UART1_MODEM_MODE_AUTO_CTS:
+			tmp = UART1_MCR_AUTO_CTS_EN;
+			break;
+
+		default:
+			break;
+	}
+
+	if (NewState == ENABLE)
+	{
+		UARTx->MCR |= tmp;
+	}
+	else
+	{
+		UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+	}
+}
+
+
+/*********************************************************************//**
+ * @brief		Get current status of modem status register
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @return 		Current value of modem status register
+ * Note:	The return value of this function must be ANDed with each member
+ * 			UART_MODEM_STAT_type enumeration to determine current flag status
+ * 			corresponding to each modem flag status. Because some flags in
+ * 			modem status register will be cleared after reading, the next reading
+ * 			modem register could not be correct. So this function used to
+ * 			read modem status register in one time only, then the return value
+ * 			used to check all flags.
+ **********************************************************************/
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
+{
+	return ((UARTx->MSR) & UART1_MSR_BITMASK);
+}
+
+
+/* UART RS485 functions --------------------------------------------------------------*/
+
+/*********************************************************************//**
+ * @brief		Configure UART peripheral in RS485 mode according to the specified
+*               parameters in the RS485ConfigStruct.
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
+*                    that contains the configuration information for specified UART
+*                    in RS485 mode.
+ * @return		None
+ **********************************************************************/
+void UART_RS485Config(LPC_UART_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct)
+{
+	uint32_t tmp;
+
+	tmp = 0;
+
+	// If Auto Direction Control is enabled -  This function is used in Master mode
+	if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
+	{
+		tmp |= UART1_RS485CTRL_DCTRL_EN;
+
+		// Set polar
+		if (RS485ConfigStruct->DirCtrlPol_Level == SET)
+		{
+			tmp |= UART1_RS485CTRL_OINV_1;
+		}
+
+		// Set pin according to. This condition is only with UART1. The others are used
+		// OE pin as default for control the direction of RS485 buffer IC
+		if ((RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
+								&& ((LPC_UART1_TypeDef *)UARTx == LPC_UART1))
+		{
+			tmp |= UART1_RS485CTRL_SEL_DTR;
+		}
+
+		// Fill delay time
+		UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
+	}
+
+	// MultiDrop mode is enable
+	if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
+	{
+		tmp |= UART1_RS485CTRL_NMM_EN;
+	}
+
+	// Auto Address Detect function
+	if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
+	{
+		tmp |= UART1_RS485CTRL_AADEN;
+
+		// Fill Match Address
+		UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
+	}
+
+	// Receiver is disable
+	if (RS485ConfigStruct->Rx_State == DISABLE)
+	{
+		tmp |= UART1_RS485CTRL_RX_DIS;
+	}
+
+	// write back to RS485 control register
+	UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
+
+	// Enable Parity function and leave parity in stick '0' parity as default
+	UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);
+}
+
+/*********************************************************************//**
+ * @brief		Enable/Disable receiver in RS485 module in UART1
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	NewState	New State of command, should be:
+ * 							- ENABLE: Enable this function.
+ * 							- DISABLE: Disable this function.
+ * @return		None
+ **********************************************************************/
+void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
+{
+	if (NewState == ENABLE)
+	{
+		UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
+	}
+	else
+	{
+		UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS;
+	}
+}
+
+/*********************************************************************//**
+ * @brief		Send data on RS485 bus with specified parity stick value (9-bit mode).
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	pDatFrm 	Pointer to data frame.
+ * @param[in]	size		Size of data.
+ * @param[in]	ParityStick	Parity Stick value, should be 0 or 1.
+ * @return		None
+ **********************************************************************/
+uint32_t UART_RS485Send(LPC_UART_TypeDef *UARTx, uint8_t *pDatFrm,
+											uint32_t size, uint8_t ParityStick)
+{
+	uint8_t tmp, save;
+	uint32_t cnt;
+
+	if (ParityStick)
+	{
+		save = tmp = UARTx->LCR & UART_LCR_BITMASK;
+
+		tmp &= ~(UART_LCR_PARITY_EVEN);
+
+		UARTx->LCR = tmp;
+
+		cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+
+		while (!(UARTx->LSR & UART_LSR_TEMT));
+
+		UARTx->LCR = save;
+	}
+	else
+	{
+		cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+
+		while (!(UARTx->LSR & UART_LSR_TEMT));
+	}
+
+	return cnt;
+}
+
+/*********************************************************************//**
+ * @brief		Send Slave address frames on RS485 bus.
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	SlvAddr Slave Address.
+ * @return		None
+ **********************************************************************/
+void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr)
+{
+	UART_RS485Send(UARTx, &SlvAddr, 1, 1);
+}
+
+/*********************************************************************//**
+ * @brief		Send Data frames on RS485 bus.
+ * @param[in]	UARTx	LPC_UART1 (only)
+ * @param[in]	pData Pointer to data to be sent.
+ * @param[in]	size Size of data frame to be sent.
+ * @return		None
+ **********************************************************************/
+uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size)
+{
+	return (UART_RS485Send(UARTx, pData, size, 0));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_uart.h b/bsp/lpc178x/drivers/lpc177x_8x_uart.h
new file mode 100644
index 0000000000..948beec908
--- /dev/null
+++ b/bsp/lpc178x/drivers/lpc177x_8x_uart.h
@@ -0,0 +1,697 @@
+/**********************************************************************
+* $Id$		lpc177x_8x_uart.h			2011-06-02
+*//**
+* @file		lpc177x_8x_uart.h
+* @brief	Contains all macro definitions and function prototypes
+*			support for UART firmware library on LPC177x_8x
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup UART	UART (Universal Asynchronous Receiver/Transmitter)
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC177X_8X_UART_H_
+#define __LPC177X_8X_UART_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC177x_8x.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup UART_Public_Macros  UART Public Macros
+ * @{
+ */
+
+/** UART time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ */
+#define UART_BLOCKING_TIMEOUT			(0xFFFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR	(3)			/*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+/** UART Received Buffer mask bit (8 bits) */
+#define UART_RBR_MASKBIT   	((uint8_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+/** UART Transmit Holding mask bit (8 bits) */
+#define UART_THR_MASKBIT   	((uint8_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+/** Macro for loading least significant halfs of divisors */
+#define UART_LOAD_DLL(div)	((div) & 0xFF)
+/** Divisor latch LSB bit mask */
+#define UART_DLL_MASKBIT	((uint8_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+/** Divisor latch MSB bit mask */
+#define UART_DLM_MASKBIT	((uint8_t)0xFF)
+/** Macro for loading most significant halfs of divisors */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+/** RBR Interrupt enable*/
+#define UART_IER_RBRINT_EN		((uint32_t)(1<<0))
+/** THR Interrupt enable*/
+#define UART_IER_THREINT_EN		((uint32_t)(1<<1))
+/** RX line status interrupt enable*/
+#define UART_IER_RLSINT_EN		((uint32_t)(1<<2))
+/** Modem status interrupt enable */
+#define UART1_IER_MSINT_EN		((uint32_t)(1<<3))
+/** CTS1 signal transition interrupt enable */
+#define UART1_IER_CTSINT_EN		((uint32_t)(1<<7))
+/** Enables the end of auto-baud interrupt */
+#define UART_IER_ABEOINT_EN		((uint32_t)(1<<8))
+/** Enables the auto-baud time-out interrupt */
+#define UART_IER_ABTOINT_EN		((uint32_t)(1<<9))
+/** UART interrupt enable register bit mask */
+#define UART_IER_BITMASK		((uint32_t)(0x307))
+/** UART1 interrupt enable register bit mask */
+#define UART1_IER_BITMASK		((uint32_t)(0x38F))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+/** Interrupt Status - Active low */
+#define UART_IIR_INTSTAT_PEND	((uint32_t)(1<<0))
+/** Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RLS		((uint32_t)(3<<1))
+/** Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_RDA		((uint32_t)(2<<1))
+/** Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_CTI		((uint32_t)(6<<1))
+/** Interrupt identification: THRE interrupt*/
+#define UART_IIR_INTID_THRE		((uint32_t)(1<<1))
+/** Interrupt identification: Modem interrupt*/
+#define UART1_IIR_INTID_MODEM	((uint32_t)(0<<1))
+/** Interrupt identification: Interrupt ID mask */
+#define UART_IIR_INTID_MASK		((uint32_t)(7<<1))
+/** These bits are equivalent to UnFCR[0] */
+#define UART_IIR_FIFO_EN		((uint32_t)(3<<6))
+/** End of auto-baud interrupt */
+#define UART_IIR_ABEO_INT		((uint32_t)(1<<8))
+/** Auto-baud time-out interrupt */
+#define UART_IIR_ABTO_INT		((uint32_t)(1<<9))
+/** UART interrupt identification register bit mask */
+#define UART_IIR_BITMASK		((uint32_t)(0x3CF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+/** UART FIFO enable */
+#define UART_FCR_FIFO_EN		((uint8_t)(1<<0))
+/** UART FIFO RX reset */
+#define UART_FCR_RX_RS			((uint8_t)(1<<1))
+/** UART FIFO TX reset */
+#define UART_FCR_TX_RS			((uint8_t)(1<<2))
+/** UART DMA mode selection */
+#define UART_FCR_DMAMODE_SEL 	((uint8_t)(1<<3))
+/** UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV0		((uint8_t)(0))
+/** UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV1		((uint8_t)(1<<6))
+/** UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV2		((uint8_t)(2<<6))
+/** UART FIFO trigger level 3: 14 character */
+#define UART_FCR_TRG_LEV3		((uint8_t)(3<<6))
+/** UART FIFO control bit mask */
+#define UART_FCR_BITMASK		((uint8_t)(0xCF))
+
+#define UART_TX_FIFO_SIZE		(16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+/** UART 5 bit data mode */
+#define UART_LCR_WLEN5     		((uint8_t)(0))
+/** UART 6 bit data mode */
+#define UART_LCR_WLEN6     		((uint8_t)(1<<0))
+/** UART 7 bit data mode */
+#define UART_LCR_WLEN7     		((uint8_t)(2<<0))
+/** UART 8 bit data mode */
+#define UART_LCR_WLEN8     		((uint8_t)(3<<0))
+/** UART Two Stop Bits Select */
+#define UART_LCR_STOPBIT_SEL	((uint8_t)(1<<2))
+/** UART Parity Enable */
+#define UART_LCR_PARITY_EN		((uint8_t)(1<<3))
+/** UART Odd Parity Select */
+#define UART_LCR_PARITY_ODD		((uint8_t)(0))
+/** UART Even Parity Select */
+#define UART_LCR_PARITY_EVEN	((uint8_t)(1<<4))
+/** UART force 1 stick parity */
+#define UART_LCR_PARITY_F_1		((uint8_t)(2<<4))
+/** UART force 0 stick parity */
+#define UART_LCR_PARITY_F_0		((uint8_t)(3<<4))
+/** UART Transmission Break enable */
+#define UART_LCR_BREAK_EN		((uint8_t)(1<<6))
+/** UART Divisor Latches Access bit enable */
+#define UART_LCR_DLAB_EN		((uint8_t)(1<<7))
+/** UART line control bit mask */
+#define UART_LCR_BITMASK		((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+/** Source for modem output pin DTR */
+#define UART1_MCR_DTR_CTRL		((uint8_t)(1<<0))
+/** Source for modem output pin RTS */
+#define UART1_MCR_RTS_CTRL		((uint8_t)(1<<1))
+/** Loop back mode select */
+#define UART1_MCR_LOOPB_EN		((uint8_t)(1<<4))
+/** Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_RTS_EN	((uint8_t)(1<<6))
+/** Enable Auto CTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN	((uint8_t)(1<<7))
+/** UART1 bit mask value */
+#define UART1_MCR_BITMASK		((uint8_t)(0x0F3))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+/** Line status register: Receive data ready*/
+#define UART_LSR_RDR		((uint8_t)(1<<0))
+/** Line status register: Overrun error*/
+#define UART_LSR_OE			((uint8_t)(1<<1))
+/** Line status register: Parity error*/
+#define UART_LSR_PE			((uint8_t)(1<<2))
+/** Line status register: Framing error*/
+#define UART_LSR_FE			((uint8_t)(1<<3))
+/** Line status register: Break interrupt*/
+#define UART_LSR_BI			((uint8_t)(1<<4))
+/** Line status register: Transmit holding register empty*/
+#define UART_LSR_THRE		((uint8_t)(1<<5))
+/** Line status register: Transmitter empty*/
+#define UART_LSR_TEMT		((uint8_t)(1<<6))
+/** Error in RX FIFO*/
+#define UART_LSR_RXFE		((uint8_t)(1<<7))
+/** UART Line status bit mask */
+#define UART_LSR_BITMASK	((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+/** Set upon state change of input CTS */
+#define UART1_MSR_DELTA_CTS		((uint8_t)(1<<0))
+/** Set upon state change of input DSR */
+#define UART1_MSR_DELTA_DSR		((uint8_t)(1<<1))
+/** Set upon low to high transition of input RI */
+#define UART1_MSR_LO2HI_RI		((uint8_t)(1<<2))
+/** Set upon state change of input DCD */
+#define UART1_MSR_DELTA_DCD		((uint8_t)(1<<3))
+/** Clear To Send State */
+#define UART1_MSR_CTS			((uint8_t)(1<<4))
+/** Data Set Ready State */
+#define UART1_MSR_DSR			((uint8_t)(1<<5))
+/** Ring Indicator State */
+#define UART1_MSR_RI			((uint8_t)(1<<6))
+/** Data Carrier Detect State */
+#define UART1_MSR_DCD			((uint8_t)(1<<7))
+/** MSR register bit-mask value */
+#define UART1_MSR_BITMASK		((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+/** UART Scratch Pad bit mask */
+#define UART_SCR_BIMASK		((uint8_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+/** UART Auto-baud start */
+#define UART_ACR_START				((uint32_t)(1<<0))
+/** UART Auto baudrate Mode 1 */
+#define UART_ACR_MODE				((uint32_t)(1<<1))
+/** UART Auto baudrate restart */
+#define UART_ACR_AUTO_RESTART		((uint32_t)(1<<2))
+/** UART End of auto-baud interrupt clear */
+#define UART_ACR_ABEOINT_CLR		((uint32_t)(1<<8))
+/** UART Auto-baud time-out interrupt clear */
+#define UART_ACR_ABTOINT_CLR		((uint32_t)(1<<9))
+/** UART Auto Baudrate register bit mask */
+#define UART_ACR_BITMASK			((uint32_t)(0x307))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+/** IrDA mode enable */
+#define UART_ICR_IRDAEN			((uint32_t)(1<<0))
+/** IrDA serial input inverted */
+#define UART_ICR_IRDAINV		((uint32_t)(1<<1))
+/** IrDA fixed pulse width mode */
+#define UART_ICR_FIXPULSE_EN	((uint32_t)(1<<2))
+/** PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_PULSEDIV(n)	((uint32_t)((n&0x07)<<3))
+/** UART IRDA bit mask */
+#define UART_ICR_BITMASK		((uint32_t)(0x3F))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+/** Baud-rate generation pre-scaler divisor */
+#define UART_FDR_DIVADDVAL(n)	((uint32_t)(n&0x0F))
+/** Baud-rate pre-scaler multiplier value */
+#define UART_FDR_MULVAL(n)		((uint32_t)((n<<4)&0xF0))
+/** UART Fractional Divider register bit mask */
+#define UART_FDR_BITMASK		((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+/** Transmit enable bit */
+#define UART_TER_TXEN			((uint8_t)(1<<7))
+/** UART Transmit Enable Register bit mask */
+#define UART_TER_BITMASK		((uint8_t)(0x80))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+/** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
+#define UART1_RS485CTRL_NMM_EN		((uint32_t)(1<<0))
+/** The receiver is disabled */
+#define UART1_RS485CTRL_RX_DIS		((uint32_t)(1<<1))
+/** Auto Address Detect (AAD) is enabled */
+#define UART1_RS485CTRL_AADEN		((uint32_t)(1<<2))
+/** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */
+#define UART1_RS485CTRL_SEL_DTR		((uint32_t)(1<<3))
+/** Enable Auto Direction Control */
+#define UART1_RS485CTRL_DCTRL_EN	((uint32_t)(1<<4))
+/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 
+The direction control pin will be driven to logic "1" when the transmitter has data to be sent */
+#define UART1_RS485CTRL_OINV_1		((uint32_t)(1<<5))
+
+/** RS485 control bit-mask value */
+#define UART1_RS485CTRL_BITMASK		((uint32_t)(0x3F))
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Address Match register
+ **********************************************************************/
+#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) 	/**< Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Delay value register
+ **********************************************************************/
+/* Macro defines for UART1 RS-485 Delay value register */
+#define UART1_RS485DLY_BITMASK		((uint8_t)(0xFF)) 	/** Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO Level register
+ **********************************************************************/
+/** Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_RXFIFOLVL(n)	((uint32_t)(n&0x0F))
+/** Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n)	((uint32_t)((n>>8)&0x0F))
+/** UART FIFO Level Register bit mask */
+#define UART_FIFOLVL_BITMASK		((uint32_t)(0x0F0F))
+
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup UART_Public_Types UART Public Types
+ * @{
+ */
+
+/**
+ * @brief UART Databit type definitions
+ */
+typedef enum {
+	UART_DATABIT_5		= 0,     		/*!< UART 5 bit data mode */
+	UART_DATABIT_6,		     			/*!< UART 6 bit data mode */
+	UART_DATABIT_7,		     			/*!< UART 7 bit data mode */
+	UART_DATABIT_8		     			/*!< UART 8 bit data mode */
+} UART_DATABIT_Type;
+
+/**
+ * @brief UART Stop bit type definitions
+ */
+typedef enum {
+	UART_STOPBIT_1		= (0),   					/*!< UART 1 Stop Bits Select */
+	UART_STOPBIT_2,		 							/*!< UART Two Stop Bits Select */
+} UART_STOPBIT_Type;
+
+/**
+ * @brief UART Parity type definitions
+ */
+typedef enum {
+	UART_PARITY_NONE 	= 0,					/*!< No parity */
+	UART_PARITY_ODD,	 						/*!< Odd parity */
+	UART_PARITY_EVEN, 							/*!< Even parity */
+	UART_PARITY_SP_1, 							/*!< Forced "1" stick parity */
+	UART_PARITY_SP_0 							/*!< Forced "0" stick parity */
+} UART_PARITY_Type;
+
+/**
+ * @brief FIFO Level type definitions
+ */
+typedef enum {
+	UART_FIFO_TRGLEV0 = 0,	/*!< UART FIFO trigger level 0: 1 character */
+	UART_FIFO_TRGLEV1, 		/*!< UART FIFO trigger level 1: 4 character */
+	UART_FIFO_TRGLEV2,		/*!< UART FIFO trigger level 2: 8 character */
+	UART_FIFO_TRGLEV3		/*!< UART FIFO trigger level 3: 14 character */
+} UART_FITO_LEVEL_Type;
+
+/********************************************************************//**
+* @brief UART Interrupt Type definitions
+**********************************************************************/
+typedef enum {
+	UART_INTCFG_RBR = 0,	/*!< RBR Interrupt enable*/
+	UART_INTCFG_THRE,		/*!< THR Interrupt enable*/
+	UART_INTCFG_RLS,		/*!< RX line status interrupt enable*/
+	UART1_INTCFG_MS,		/*!< Modem status interrupt enable (UART1 only) */
+	UART1_INTCFG_CTS,		/*!< CTS1 signal transition interrupt enable (UART1 only) */
+	UART_INTCFG_ABEO,		/*!< Enables the end of auto-baud interrupt */
+	UART_INTCFG_ABTO		/*!< Enables the auto-baud time-out interrupt */
+} UART_INT_Type;
+
+/**
+ * @brief UART Line Status Type definition
+ */
+typedef enum {
+	UART_LINESTAT_RDR	= UART_LSR_RDR,			/*!<Line status register: Receive data ready*/
+	UART_LINESTAT_OE	= UART_LSR_OE,			/*!<Line status register: Overrun error*/
+	UART_LINESTAT_PE	= UART_LSR_PE,			/*!<Line status register: Parity error*/
+	UART_LINESTAT_FE	= UART_LSR_FE,			/*!<Line status register: Framing error*/
+	UART_LINESTAT_BI	= UART_LSR_BI,			/*!<Line status register: Break interrupt*/
+	UART_LINESTAT_THRE	= UART_LSR_THRE,		/*!<Line status register: Transmit holding register empty*/
+	UART_LINESTAT_TEMT	= UART_LSR_TEMT,		/*!<Line status register: Transmitter empty*/
+	UART_LINESTAT_RXFE	= UART_LSR_RXFE			/*!<Error in RX FIFO*/
+} UART_LS_Type;
+
+/**
+ * @brief UART Auto-baudrate mode type definition
+ */
+typedef enum {
+	UART_AUTOBAUD_MODE0				= 0,			/**< UART Auto baudrate Mode 0 */
+	UART_AUTOBAUD_MODE1,							/**< UART Auto baudrate Mode 1 */
+} UART_AB_MODE_Type;
+
+/**
+ * @brief Auto Baudrate mode configuration type definition
+ */
+typedef struct {
+	UART_AB_MODE_Type	ABMode;			/**< Autobaudrate mode */
+	FunctionalState		AutoRestart;	/**< Auto Restart state */
+} UART_AB_CFG_Type;
+
+/**
+ * @brief UART End of Auto-baudrate type definition
+ */
+typedef enum {
+	UART_AUTOBAUD_INTSTAT_ABEO		= UART_IIR_ABEO_INT,		/**< UART End of auto-baud interrupt  */
+	UART_AUTOBAUD_INTSTAT_ABTO		= UART_IIR_ABTO_INT			/**< UART Auto-baud time-out interrupt  */
+}UART_ABEO_Type;
+
+/**
+ * UART IrDA Control type Definition
+ */
+typedef enum 
+{
+	/** Pulse width = 2 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV2		= 0,
+
+	/** Pulse width = 4 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV4,
+
+	/** Pulse width = 8 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV8,
+
+	/** Pulse width = 16 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV16,
+
+	/** Pulse width = 32 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV32,
+
+	/**< Pulse width = 64 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV64,
+
+	/**< Pulse width = 128 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV128,
+
+	/**< Pulse width = 256 * Tpclk
+	- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV256
+} UART_IrDA_PULSE_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  Signal states definition
+**********************************************************************/
+typedef enum {
+	INACTIVE = 0,			/* In-active state */
+	ACTIVE = !INACTIVE 		/* Active state */
+}UART1_SignalState;
+
+/**
+ * @brief UART modem status type definition
+ */
+typedef enum {
+	UART1_MODEM_STAT_DELTA_CTS	= UART1_MSR_DELTA_CTS,		/*!< Set upon state change of input CTS */
+	UART1_MODEM_STAT_DELTA_DSR	= UART1_MSR_DELTA_DSR,		/*!< Set upon state change of input DSR */
+	UART1_MODEM_STAT_LO2HI_RI	= UART1_MSR_LO2HI_RI,		/*!< Set upon low to high transition of input RI */
+	UART1_MODEM_STAT_DELTA_DCD	= UART1_MSR_DELTA_DCD,		/*!< Set upon state change of input DCD */
+	UART1_MODEM_STAT_CTS		= UART1_MSR_CTS,			/*!< Clear To Send State */
+	UART1_MODEM_STAT_DSR		= UART1_MSR_DSR,			/*!< Data Set Ready State */
+	UART1_MODEM_STAT_RI			= UART1_MSR_RI,				/*!< Ring Indicator State */
+	UART1_MODEM_STAT_DCD		= UART1_MSR_DCD				/*!< Data Carrier Detect State */
+} UART_MODEM_STAT_type;
+
+/**
+ * @brief Modem output pin type definition
+ */
+typedef enum {
+	UART1_MODEM_PIN_DTR			= 0,		/*!< Source for modem output pin DTR */
+	UART1_MODEM_PIN_RTS						/*!< Source for modem output pin RTS */
+} UART_MODEM_PIN_Type;
+
+/**
+ * @brief UART Modem mode type definition
+ */
+typedef enum {
+	UART1_MODEM_MODE_LOOPBACK	= 0,		/*!< Loop back mode select */
+	UART1_MODEM_MODE_AUTO_RTS,				/*!< Enable Auto RTS flow-control */
+	UART1_MODEM_MODE_AUTO_CTS 				/*!< Enable Auto CTS flow-control */
+} UART_MODEM_MODE_Type;
+
+/**
+ * @brief UART Direction Control Pin type definition
+ */
+typedef enum {
+	UART1_RS485_DIRCTRL_RTS = 0,	/**< Pin RTS is used for direction control */
+	UART1_RS485_DIRCTRL_DTR			/**< Pin DTR is used for direction control */
+} UART_RS485_DIRCTRL_PIN_Type;
+
+/********************************************************************//**
+* @brief UART Configuration Structure definition
+**********************************************************************/
+typedef struct {
+  uint32_t Baud_rate;   		/**< UART baud rate */
+  UART_PARITY_Type Parity;    	/**< Parity selection, should be:
+							   - UART_PARITY_NONE: No parity
+							   - UART_PARITY_ODD: Odd parity
+							   - UART_PARITY_EVEN: Even parity
+							   - UART_PARITY_SP_1: Forced "1" stick parity
+							   - UART_PARITY_SP_0: Forced "0" stick parity
+							   */
+  UART_DATABIT_Type Databits;   /**< Number of data bits, should be:
+							   - UART_DATABIT_5: UART 5 bit data mode
+							   - UART_DATABIT_6: UART 6 bit data mode
+							   - UART_DATABIT_7: UART 7 bit data mode
+							   - UART_DATABIT_8: UART 8 bit data mode
+							   */
+  UART_STOPBIT_Type Stopbits;   /**< Number of stop bits, should be:
+							   - UART_STOPBIT_1: UART 1 Stop Bits Select
+							   - UART_STOPBIT_2: UART 2 Stop Bits Select
+							   */
+} UART_CFG_Type;
+
+/********************************************************************//**
+* @brief UART FIFO Configuration Structure definition
+**********************************************************************/
+
+typedef struct {
+	FunctionalState FIFO_ResetRxBuf;	/**< Reset Rx FIFO command state , should be:
+										 - ENABLE: Reset Rx FIFO in UART
+										 - DISABLE: Do not reset Rx FIFO  in UART
+										 */
+	FunctionalState FIFO_ResetTxBuf;	/**< Reset Tx FIFO command state , should be:
+										 - ENABLE: Reset Tx FIFO in UART
+										 - DISABLE: Do not reset Tx FIFO  in UART
+										 */
+	FunctionalState FIFO_DMAMode;		/**< DMA mode, should be:
+										 - ENABLE: Enable DMA mode in UART
+										 - DISABLE: Disable DMA mode in UART
+										 */
+	UART_FITO_LEVEL_Type FIFO_Level;	/**< Rx FIFO trigger level, should be:
+										- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
+										- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
+										- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
+										- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
+										*/
+} UART_FIFO_CFG_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  RS485 Control configuration type
+**********************************************************************/
+typedef struct {
+	FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
+													- ENABLE: Enable this function.
+													- DISABLE: Disable this function. */
+	FunctionalState Rx_State;					/*!< Receiver State:
+													- ENABLE: Enable Receiver.
+													- DISABLE: Disable Receiver. */
+	FunctionalState AutoAddrDetect_State;		/*!< Auto Address Detect mode state:
+												- ENABLE: ENABLE this function.
+												- DISABLE: Disable this function. */
+	FunctionalState AutoDirCtrl_State;			/*!< Auto Direction Control State:
+												- ENABLE: Enable this function.
+												- DISABLE: Disable this function. */
+	UART_RS485_DIRCTRL_PIN_Type DirCtrlPin;		/*!< If direction control is enabled, state:
+												- UART1_RS485_DIRCTRL_RTS:
+												pin RTS is used for direction control.
+												- UART1_RS485_DIRCTRL_DTR:
+												pin DTR is used for direction control. */
+	 SetState DirCtrlPol_Level;					/*!< Polarity of the direction control signal on
+												the RTS (or DTR) pin:
+												- RESET: The direction control pin will be driven
+												to logic "0" when the transmitter has data to be sent.
+												- SET: The direction control pin will be driven
+												to logic "1" when the transmitter has data to be sent. */
+	uint8_t MatchAddrValue;					/*!< address match value for RS-485/EIA-485 mode, 8-bit long */
+	uint8_t DelayValue;						/*!< delay time is in periods of the baud clock, 8-bit long */
+} UART1_RS485_CTRLCFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup UART_Public_Functions UART Public Functions
+ * @{
+ */
+/* UART Init/DeInit functions --------------------------------------------------*/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
+void UART_DeInit(LPC_UART_TypeDef* UARTx);
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
+
+/* UART Send/Receive functions -------------------------------------------------*/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+		uint32_t buflen, TRANSFER_BLOCK_Type flag);
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
+		uint32_t buflen, TRANSFER_BLOCK_Type flag);
+
+/* UART FIFO functions ----------------------------------------------------------*/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
+
+/* UART get information functions -----------------------------------------------*/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
+
+/* UART operate functions -------------------------------------------------------*/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
+				FunctionalState NewState);
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
+
+/* UART Auto-baud functions -----------------------------------------------------*/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+				FunctionalState NewState);
+
+/* UART1 FullModem functions ----------------------------------------------------*/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
+							UART1_SignalState NewState);
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
+							FunctionalState NewState);
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
+
+/* UART RS485 functions ----------------------------------------------------------*/
+void UART_RS485Config(LPC_UART_TypeDef *UARTx,
+									UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
+void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
+void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr);
+uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size);
+
+/* UART IrDA functions-------------------------------------------------------------*/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __LPC177X_8X_UART_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/bsp/lpc178x/drivers/lpc_types.h b/bsp/lpc178x/drivers/lpc_types.h
new file mode 100644
index 0000000000..8978f111fb
--- /dev/null
+++ b/bsp/lpc178x/drivers/lpc_types.h
@@ -0,0 +1,201 @@
+/**********************************************************************
+* $Id$		lpc_types.h			2011-06-02
+*//**
+* @file		lpc_types.h
+* @brief	Contains the NXP ABL typedefs for C standard types.
+*			It is intended to be used in ISO C conforming development
+*			environments and checks for this insofar as it is possible
+*			to do so.
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+* 
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+#ifndef __LPC_TYPES_H
+#define __LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+
+/** @defgroup LPC_Type_Def Data Types Definitions
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+ 
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types Basic Public Data Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+	NONE_BLOCKING = 0,		/**< None Blocking type */
+	BLOCKING,				/**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros  Basic Public Macros
+ * @{
+ */
+
+/** _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/** Set bit macro */
+#define _BIT(n)	(1<<n)
+
+/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) (v<<f)
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array)  (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef	uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef	int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef	uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef	int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+/**
+ * @}
+ */
+
+
+#endif /* __LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/bsp/lpc178x/drivers/uart.c b/bsp/lpc178x/drivers/uart.c
new file mode 100644
index 0000000000..31fc83fc7a
--- /dev/null
+++ b/bsp/lpc178x/drivers/uart.c
@@ -0,0 +1,353 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-03-08     Bernard      The first version for LPC17xx
+ * 2010-05-02     Aozima       update CMSIS to 130
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "LPC177x_8x.h"
+#include "lpc177x_8x_uart.h"
+#include "lpc177x_8x_pinsel.h"
+
+#define IER_RBR		0x01
+#define IER_THRE	0x02
+#define IER_RLS		0x04
+
+#define IIR_PEND	0x01
+#define IIR_RLS		0x03
+#define IIR_RDA		0x02
+#define IIR_CTI		0x06
+#define IIR_THRE	0x01
+
+#define LSR_RDR		0x01
+#define LSR_OE		0x02
+#define LSR_PE		0x04
+#define LSR_FE		0x08
+#define LSR_BI		0x10
+#define LSR_THRE	0x20
+#define LSR_TEMT	0x40
+#define LSR_RXFE	0x80
+
+/**
+ * @addtogroup LPC11xx
+ */
+
+/*@{*/
+
+#define UART_BAUDRATE   115200
+#define LPC_UART		LPC_UART0
+#define UART_IRQn		UART0_IRQn
+
+struct rt_uart_lpc
+{
+	struct rt_device parent;
+
+	LPC_UART_TypeDef * UART;
+
+	/* buffer for reception */
+	rt_uint8_t read_index, save_index;
+	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+};
+
+#ifdef RT_USING_UART1
+struct rt_uart_lpc uart1_device;
+#endif
+
+void UART0_IRQHandler(void)
+{
+//	rt_ubase_t level, iir;
+//    struct rt_uart_lpc* uart = &uart_device;
+//
+//    /* read IIR and clear it */
+//	iir = LPC_UART->IIR;
+//
+//	iir >>= 1;			    /* skip pending bit in IIR */
+//	iir &= 0x07;			/* check bit 1~3, interrupt identification */
+//
+//	if (iir == IIR_RDA)	    /* Receive Data Available */
+//	{
+//		/* Receive Data Available */
+//        uart->rx_buffer[uart->save_index] = LPC_UART->RBR;
+//
+//        level = rt_hw_interrupt_disable();
+//		uart->save_index ++;
+//        if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
+//            uart->save_index = 0;
+//        rt_hw_interrupt_enable(level);
+//
+//		/* invoke callback */
+//		if(uart->parent.rx_indicate != RT_NULL)
+//		{
+//		    rt_size_t length;
+//		    if (uart->read_index > uart->save_index)
+//                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
+//            else
+//                length = uart->save_index - uart->read_index;
+//
+//            uart->parent.rx_indicate(&uart->parent, length);
+//		}
+//	}
+//
+//	return;
+}
+
+static rt_err_t rt_uart_init (rt_device_t dev)
+{
+//	rt_uint32_t Fdiv;
+//	rt_uint32_t pclkdiv, pclk;
+//
+//	/* Init UART Hardware */
+//	if (LPC_UART == LPC_UART0)
+//	{
+//		LPC_PINCON->PINSEL0 &= ~0x000000F0;
+//		LPC_PINCON->PINSEL0 |= 0x00000050;  /* RxD0 is P0.3 and TxD0 is P0.2 */
+//		/* By default, the PCLKSELx value is zero, thus, the PCLK for
+//		all the peripherals is 1/4 of the SystemFrequency. */
+//		/* Bit 6~7 is for UART0 */
+//		pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
+//		switch ( pclkdiv )
+//		{
+//		  case 0x00:
+//		  default:
+//			pclk = SystemCoreClock/4;
+//			break;
+//		  case 0x01:
+//			pclk = SystemCoreClock;
+//			break;
+//		  case 0x02:
+//			pclk = SystemCoreClock/2;
+//			break;
+//		  case 0x03:
+//			pclk = SystemCoreClock/8;
+//			break;
+//		}
+//
+//	    LPC_UART0->LCR = 0x83;		/* 8 bits, no Parity, 1 Stop bit */
+//		Fdiv = ( pclk / 16 ) / UART_BAUDRATE;	/*baud rate */
+//	    LPC_UART0->DLM = Fdiv / 256;
+//	    LPC_UART0->DLL = Fdiv % 256;
+//		LPC_UART0->LCR = 0x03;		/* DLAB = 0 */
+//	    LPC_UART0->FCR = 0x07;		/* Enable and reset TX and RX FIFO. */
+//	}
+//	else if ((LPC_UART1_TypeDef*)LPC_UART == LPC_UART1)
+//	{
+//		LPC_PINCON->PINSEL4 &= ~0x0000000F;
+//		LPC_PINCON->PINSEL4 |= 0x0000000A;	/* Enable RxD1 P2.1, TxD1 P2.0 */
+//
+//		/* By default, the PCLKSELx value is zero, thus, the PCLK for
+//		all the peripherals is 1/4 of the SystemFrequency. */
+//		/* Bit 8,9 are for UART1 */
+//		pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
+//		switch ( pclkdiv )
+//		{
+//		  case 0x00:
+//		  default:
+//			pclk = SystemCoreClock/4;
+//			break;
+//		  case 0x01:
+//			pclk = SystemCoreClock;
+//			break;
+//		  case 0x02:
+//			pclk = SystemCoreClock/2;
+//			break;
+//		  case 0x03:
+//			pclk = SystemCoreClock/8;
+//			break;
+//		}
+//
+//	    LPC_UART1->LCR = 0x83;		/* 8 bits, no Parity, 1 Stop bit */
+//		Fdiv = ( pclk / 16 ) / UART_BAUDRATE ;	/*baud rate */
+//	    LPC_UART1->DLM = Fdiv / 256;
+//	    LPC_UART1->DLL = Fdiv % 256;
+//		LPC_UART1->LCR = 0x03;		/* DLAB = 0 */
+//	    LPC_UART1->FCR = 0x07;		/* Enable and reset TX and RX FIFO. */
+//	}
+//
+//	/* Ensure a clean start, no data in either TX or RX FIFO. */
+//	while (( LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
+//	while ( LPC_UART->LSR & LSR_RDR )
+//	{
+//		Fdiv = LPC_UART->RBR;	/* Dump data from RX FIFO */
+//	}
+//	LPC_UART->IER = IER_RBR | IER_THRE | IER_RLS;	/* Enable UART interrupt */
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
+{
+//	RT_ASSERT(dev != RT_NULL);
+//	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+//	{
+//		/* Enable the UART Interrupt */
+//		NVIC_EnableIRQ(UART_IRQn);
+//	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_close(rt_device_t dev)
+{
+//	RT_ASSERT(dev != RT_NULL);
+//	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+//	{
+//		/* Disable the UART Interrupt */
+//		NVIC_DisableIRQ(UART_IRQn);
+//	}
+
+	return RT_EOK;
+}
+
+static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+//	rt_uint8_t* ptr;
+//	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+//	RT_ASSERT(uart != RT_NULL);
+//
+//	/* point to buffer */
+//	ptr = (rt_uint8_t*) buffer;
+//	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+//	{
+//		while (size)
+//		{
+//			/* interrupt receive */
+//			rt_base_t level;
+//
+//			/* disable interrupt */
+//			level = rt_hw_interrupt_disable();
+//			if (uart->read_index != uart->save_index)
+//			{
+//				*ptr = uart->rx_buffer[uart->read_index];
+//
+//				uart->read_index ++;
+//				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+//					uart->read_index = 0;
+//			}
+//			else
+//			{
+//				/* no data in rx buffer */
+//
+//				/* enable interrupt */
+//				rt_hw_interrupt_enable(level);
+//				break;
+//			}
+//
+//			/* enable interrupt */
+//			rt_hw_interrupt_enable(level);
+//
+//			ptr ++;
+//			size --;
+//		}
+//
+//		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+//	}
+
+	return 0;
+}
+
+static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+//    rt_uint32_t i = size;
+//	char *ptr;
+//	ptr = (char*)buffer;
+//
+//    while(i)
+//    {
+//        UART_SendByte((LPC_UART_TypeDef*)LPC_UART1,*ptr);
+//        i--;
+//        ptr++;
+//    }
+//    return size;
+
+	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+	char *ptr;
+	ptr = (char*)buffer;
+
+	if (dev->flag & RT_DEVICE_FLAG_STREAM)
+	{
+		/* stream mode */
+		while (size)
+		{
+			if (*ptr == '\n')
+			{
+                UART_SendByte( uart->UART,'\r');
+			}
+
+			UART_SendByte( uart->UART,*ptr);
+			ptr ++;
+			size --;
+		}
+	}
+	else
+	{
+		while ( size != 0 )
+		{
+		    UART_SendByte( uart->UART,*ptr);
+			ptr++;
+			size--;
+		}
+	}
+
+	return (rt_size_t) ptr - (rt_size_t) buffer;
+}
+
+void rt_hw_uart_init(void)
+{
+#ifdef RT_USING_UART1
+	struct rt_uart_lpc* uart;
+	UART_CFG_Type UART_ConfigStruct;
+
+	/*
+	 * Initialize UART1 pin connect
+	 * P3.16: TXD
+	 * P3.17: RXD
+	 */
+	PINSEL_ConfigPin(3, 16, 3);
+	PINSEL_ConfigPin(3, 17, 3);
+
+	UART_ConfigStruct.Baud_rate = 115200;
+	UART_ConfigStruct.Databits = UART_DATABIT_8;
+	UART_ConfigStruct.Parity = UART_PARITY_NONE;
+	UART_ConfigStruct.Stopbits = UART_STOPBIT_1;
+
+	UART_Init((LPC_UART_TypeDef *)LPC_UART1,&UART_ConfigStruct);
+
+	// Enable UART Transmit
+	UART_TxCmd((LPC_UART_TypeDef *)LPC_UART1, ENABLE);
+
+	/* get uart device */
+	uart = &uart1_device;
+	uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
+
+	/* device initialization */
+	uart->parent.type = RT_Device_Class_Char;
+	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+	uart->read_index = uart->save_index = 0;
+
+	/* device interface */
+	uart->parent.init 	    = rt_uart_init;
+	uart->parent.open 	    = rt_uart_open;
+	uart->parent.close      = rt_uart_close;
+	uart->parent.read 	    = rt_uart_read;
+	uart->parent.write      = rt_uart_write;
+	uart->parent.control    = RT_NULL;
+	uart->parent.user_data  = RT_NULL;
+
+	rt_device_register(&uart->parent,
+		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/lpc178x/drivers/uart.h b/bsp/lpc178x/drivers/uart.h
new file mode 100644
index 0000000000..7b4663aa3d
--- /dev/null
+++ b/bsp/lpc178x/drivers/uart.h
@@ -0,0 +1,6 @@
+#ifndef __UART_H__
+#define __UART_H__
+
+void rt_hw_uart_init(void);
+
+#endif
author	wuyangyong <[email protected]>	2011-10-13 17:15:32 +0000
committer	wuyangyong <[email protected]>	2011-10-13 17:15:32 +0000
commit	eb0af4e41ee1f7857fea77dde1ecf51bf902c9f9 (patch)
tree	36bc386d17af582fea59c442a366df230ff4fd11 /bsp/lpc178x/drivers
parent	1e06bb2726c1bdedbf5a962c2d81996358e3d186 (diff)