diff options
| author | Meco Man <[email protected]> | 2024-03-10 15:11:54 -0400 |
|---|---|---|
| committer | Meco Man <[email protected]> | 2024-03-10 23:19:22 -0400 |
| commit | f71d4f33ea615b94763a23eca4674e39e08eb489 (patch) | |
| tree | cbc654f43d3717273bff93d3a457121bdfe9ef0f /bsp/lpc408x/Libraries/Device | |
| parent | 46967ef56fd3a3c564ff8119524ef0f1ce500a82 (diff) | |
[bsp][nxp][lpc] move lpc BSPs into nxp/lpc folders
Diffstat (limited to 'bsp/lpc408x/Libraries/Device')
13 files changed, 0 insertions, 6213 deletions
diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC177x_8x.h b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC177x_8x.h deleted file mode 100644 index 5ebe1428d4..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC177x_8x.h +++ /dev/null @@ -1,1442 +0,0 @@ -/********************************************************************** -* $Id$ LPC177x_8x.h 2011-06-02 -*//** -* @file LPC177x_8x.h -* @brief Cortex-M3 Core Peripheral Access Layer Header File for -* NXP LPC177x_8x Series. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __LPC177x_8x_H__ -#define __LPC177x_8x_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC177x_8x Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - Reserved0_IRQn = 13, /*!< Reserved */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /*!< USB Activity interrupt */ - CANActivity_IRQn = 34, /*!< CAN Activity interrupt */ - UART4_IRQn = 35, /*!< UART4 Interrupt */ - SSP2_IRQn = 36, /*!< SSP2 Interrupt */ - LCD_IRQn = 37, /*!< LCD Interrupt */ - GPIO_IRQn = 38, /*!< GPIO Interrupt */ - PWM0_IRQn = 39, /*!< PWM0 Interrupt */ - EEPROM_IRQn = 40, /*!< EEPROM Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -//#include "system_LPC177x_8x.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ - __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ - __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ - __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ - __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ - __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ - __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ - uint32_t RESERVED2[4]; - __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ - __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ - uint32_t RESERVED3[14]; - __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */ - __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */ - __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */ - __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ - __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ - __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ - uint32_t RESERVED4[10]; - __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ - uint32_t RESERVED5[1]; - __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ - __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ - __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */ - __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */ - uint32_t RESERVED8; - __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */ - uint32_t RESERVED9; - __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */ - uint32_t RESERVED10[1]; - __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ - __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ - __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ - __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */ - __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */ - uint32_t RESERVED11[2]; - __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */ - __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t P0_0; /* 0x000 */ - __IO uint32_t P0_1; - __IO uint32_t P0_2; - __IO uint32_t P0_3; - __IO uint32_t P0_4; - __IO uint32_t P0_5; - __IO uint32_t P0_6; - __IO uint32_t P0_7; - - __IO uint32_t P0_8; /* 0x020 */ - __IO uint32_t P0_9; - __IO uint32_t P0_10; - __IO uint32_t P0_11; - __IO uint32_t P0_12; - __IO uint32_t P0_13; - __IO uint32_t P0_14; - __IO uint32_t P0_15; - - __IO uint32_t P0_16; /* 0x040 */ - __IO uint32_t P0_17; - __IO uint32_t P0_18; - __IO uint32_t P0_19; - __IO uint32_t P0_20; - __IO uint32_t P0_21; - __IO uint32_t P0_22; - __IO uint32_t P0_23; - - __IO uint32_t P0_24; /* 0x060 */ - __IO uint32_t P0_25; - __IO uint32_t P0_26; - __IO uint32_t P0_27; - __IO uint32_t P0_28; - __IO uint32_t P0_29; - __IO uint32_t P0_30; - __IO uint32_t P0_31; - - __IO uint32_t P1_0; /* 0x080 */ - __IO uint32_t P1_1; - __IO uint32_t P1_2; - __IO uint32_t P1_3; - __IO uint32_t P1_4; - __IO uint32_t P1_5; - __IO uint32_t P1_6; - __IO uint32_t P1_7; - - __IO uint32_t P1_8; /* 0x0A0 */ - __IO uint32_t P1_9; - __IO uint32_t P1_10; - __IO uint32_t P1_11; - __IO uint32_t P1_12; - __IO uint32_t P1_13; - __IO uint32_t P1_14; - __IO uint32_t P1_15; - - __IO uint32_t P1_16; /* 0x0C0 */ - __IO uint32_t P1_17; - __IO uint32_t P1_18; - __IO uint32_t P1_19; - __IO uint32_t P1_20; - __IO uint32_t P1_21; - __IO uint32_t P1_22; - __IO uint32_t P1_23; - - __IO uint32_t P1_24; /* 0x0E0 */ - __IO uint32_t P1_25; - __IO uint32_t P1_26; - __IO uint32_t P1_27; - __IO uint32_t P1_28; - __IO uint32_t P1_29; - __IO uint32_t P1_30; - __IO uint32_t P1_31; - - __IO uint32_t P2_0; /* 0x100 */ - __IO uint32_t P2_1; - __IO uint32_t P2_2; - __IO uint32_t P2_3; - __IO uint32_t P2_4; - __IO uint32_t P2_5; - __IO uint32_t P2_6; - __IO uint32_t P2_7; - - __IO uint32_t P2_8; /* 0x120 */ - __IO uint32_t P2_9; - __IO uint32_t P2_10; - __IO uint32_t P2_11; - __IO uint32_t P2_12; - __IO uint32_t P2_13; - __IO uint32_t P2_14; - __IO uint32_t P2_15; - - __IO uint32_t P2_16; /* 0x140 */ - __IO uint32_t P2_17; - __IO uint32_t P2_18; - __IO uint32_t P2_19; - __IO uint32_t P2_20; - __IO uint32_t P2_21; - __IO uint32_t P2_22; - __IO uint32_t P2_23; - - __IO uint32_t P2_24; /* 0x160 */ - __IO uint32_t P2_25; - __IO uint32_t P2_26; - __IO uint32_t P2_27; - __IO uint32_t P2_28; - __IO uint32_t P2_29; - __IO uint32_t P2_30; - __IO uint32_t P2_31; - - __IO uint32_t P3_0; /* 0x180 */ - __IO uint32_t P3_1; - __IO uint32_t P3_2; - __IO uint32_t P3_3; - __IO uint32_t P3_4; - __IO uint32_t P3_5; - __IO uint32_t P3_6; - __IO uint32_t P3_7; - - __IO uint32_t P3_8; /* 0x1A0 */ - __IO uint32_t P3_9; - __IO uint32_t P3_10; - __IO uint32_t P3_11; - __IO uint32_t P3_12; - __IO uint32_t P3_13; - __IO uint32_t P3_14; - __IO uint32_t P3_15; - - __IO uint32_t P3_16; /* 0x1C0 */ - __IO uint32_t P3_17; - __IO uint32_t P3_18; - __IO uint32_t P3_19; - __IO uint32_t P3_20; - __IO uint32_t P3_21; - __IO uint32_t P3_22; - __IO uint32_t P3_23; - - __IO uint32_t P3_24; /* 0x1E0 */ - __IO uint32_t P3_25; - __IO uint32_t P3_26; - __IO uint32_t P3_27; - __IO uint32_t P3_28; - __IO uint32_t P3_29; - __IO uint32_t P3_30; - __IO uint32_t P3_31; - - __IO uint32_t P4_0; /* 0x200 */ - __IO uint32_t P4_1; - __IO uint32_t P4_2; - __IO uint32_t P4_3; - __IO uint32_t P4_4; - __IO uint32_t P4_5; - __IO uint32_t P4_6; - __IO uint32_t P4_7; - - __IO uint32_t P4_8; /* 0x220 */ - __IO uint32_t P4_9; - __IO uint32_t P4_10; - __IO uint32_t P4_11; - __IO uint32_t P4_12; - __IO uint32_t P4_13; - __IO uint32_t P4_14; - __IO uint32_t P4_15; - - __IO uint32_t P4_16; /* 0x240 */ - __IO uint32_t P4_17; - __IO uint32_t P4_18; - __IO uint32_t P4_19; - __IO uint32_t P4_20; - __IO uint32_t P4_21; - __IO uint32_t P4_22; - __IO uint32_t P4_23; - - __IO uint32_t P4_24; /* 0x260 */ - __IO uint32_t P4_25; - __IO uint32_t P4_26; - __IO uint32_t P4_27; - __IO uint32_t P4_28; - __IO uint32_t P4_29; - __IO uint32_t P4_30; - __IO uint32_t P4_31; - - __IO uint32_t P5_0; /* 0x280 */ - __IO uint32_t P5_1; - __IO uint32_t P5_2; - __IO uint32_t P5_3; - __IO uint32_t P5_4; /* 0x290 */ -} LPC_IOCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - __IO uint32_t DIR; - uint32_t RESERVED0[3]; - __IO uint32_t MASK; - __IO uint32_t PIN; - __IO uint32_t SET; - __O uint32_t CLR; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - uint32_t RESERVED0[2]; - __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */ - __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */ - uint32_t RESERVED0; - __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */ - __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */ - __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */ - __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */ - __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */ - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */ -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ -/* There are three types of UARTs on the chip: -(1) UART0,UART2, and UART3 are the standard UART. -(2) UART1 is the standard with modem capability. -(3) USART(UART4) is the sync/async UART with smart card capability. -More details can be found on the Users Manual. */ - -#if 0 -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; -#else -typedef struct -{ - union - { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union - { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union - { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7];//Reserved - __I uint8_t LSR; - uint8_t RESERVED2[7];//Reserved - __IO uint8_t SCR; - uint8_t RESERVED3[3];//Reserved - __IO uint32_t ACR; - uint8_t RESERVED4[4];//Reserved - __IO uint8_t FDR; - uint8_t RESERVED5[7];//Reserved - __IO uint8_t TER; - uint8_t RESERVED8[27];//Reserved - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3];//Reserved - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3];//Reserved - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3];//Reserved -}LPC_UART_TypeDef; -#endif - - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; -} LPC_UART1_TypeDef; - -typedef struct -{ - union { - __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ - __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ - __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ - }; - union { - __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ - __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ - }; - union { - __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ - __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ - }; - __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ - __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ - __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ - __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ - __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */ - __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ - __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */ - uint32_t RESERVED0[6]; - __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */ - __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ - __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ - __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ - __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */ - __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */ -} LPC_UART4_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ - __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ - __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ - __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ - __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ - __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ - __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ - __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ - __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ - __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ - __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ - __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ - __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ - __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ - __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ - __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ - __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ - __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ - __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ - __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ - __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ - __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t DAO; - __IO uint32_t DAI; - __O uint32_t TXFIFO; - __I uint32_t RXFIFO; - __I uint32_t STATE; - __IO uint32_t DMA1; - __IO uint32_t DMA2; - __IO uint32_t IRQ; - __IO uint32_t TXRATE; - __IO uint32_t RXRATE; - __IO uint32_t TXBITRATE; - __IO uint32_t RXBITRATE; - __IO uint32_t TXMODE; - __IO uint32_t RXMODE; -} LPC_I2S_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; - __IO uint32_t ERSTATUS; - __IO uint32_t ERCONTROL; - __IO uint32_t ERCOUNTERS; - uint32_t RESERVED22; - __IO uint32_t ERFIRSTSTAMP0; - __IO uint32_t ERFIRSTSTAMP1; - __IO uint32_t ERFIRSTSTAMP2; - uint32_t RESERVED23; - __IO uint32_t ERLASTSTAMP0; - __IO uint32_t ERLASTSTAMP1; - __IO uint32_t ERLASTSTAMP2; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t MOD; - uint8_t RESERVED0[3]; - __IO uint32_t TC; - __O uint8_t FEED; - uint8_t RESERVED1[3]; - __I uint32_t TV; - uint32_t RESERVED2; - __IO uint32_t WARNINT; - __IO uint32_t WINDOW; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ - __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ - __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CTRL; - __IO uint32_t CNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t CON; - __O uint32_t CON_SET; - __O uint32_t CON_CLR; - __I uint32_t CAPCON; - __O uint32_t CAPCON_SET; - __O uint32_t CAPCON_CLR; - __IO uint32_t TC0; - __IO uint32_t TC1; - __IO uint32_t TC2; - __IO uint32_t LIM0; - __IO uint32_t LIM1; - __IO uint32_t LIM2; - __IO uint32_t MAT0; - __IO uint32_t MAT1; - __IO uint32_t MAT2; - __IO uint32_t DT; - __IO uint32_t CP; - __IO uint32_t CAP0; - __IO uint32_t CAP1; - __IO uint32_t CAP2; - __I uint32_t INTEN; - __O uint32_t INTEN_SET; - __O uint32_t INTEN_CLR; - __I uint32_t CNTCON; - __O uint32_t CNTCON_SET; - __O uint32_t CNTCON_CLR; - __I uint32_t INTF; - __O uint32_t INTF_SET; - __O uint32_t INTF_CLR; - __O uint32_t CAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t CON; - __I uint32_t STAT; - __IO uint32_t CONF; - __I uint32_t POS; - __IO uint32_t MAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP0; - __IO uint32_t LOAD; - __I uint32_t TIME; - __I uint32_t VEL; - __I uint32_t CAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTERPHA; - __IO uint32_t FILTERPHB; - __IO uint32_t FILTERINX; - __IO uint32_t WINDOW; - __IO uint32_t INXCMP1; - __IO uint32_t INXCMP2; - uint32_t RESERVED0[993]; - __O uint32_t IEC; - __O uint32_t IES; - __I uint32_t INTSTAT; - __I uint32_t IE; - __O uint32_t CLR; - __O uint32_t SET; -} LPC_QEI_TypeDef; - -/*------------- SD/MMC card Interface (MCI)-----------------------------------*/ -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLOCK; - __IO uint32_t ARGUMENT; - __IO uint32_t COMMAND; - __I uint32_t RESP_CMD; - __I uint32_t RESP0; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __IO uint32_t DATATMR; - __IO uint32_t DATALEN; - __IO uint32_t DATACTRL; - __I uint32_t DATACNT; - __I uint32_t STATUS; - __O uint32_t CLEAR; - __IO uint32_t MASK0; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO[16]; -} LPC_MCI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - ///Offset: 0x00000000 - Acceptance Filter Register - __IO uint32_t AFMR; - - ///Offset: 0x00000004 - Standard Frame Individual Start Address Register - __IO uint32_t SFF_sa; - - ///Offset: 0x00000008 - Standard Frame Group Start Address Register - __IO uint32_t SFF_GRP_sa; - - ///Offset: 0x0000000C - Extended Frame Start Address Register - __IO uint32_t EFF_sa; - - ///Offset: 0x00000010 - Extended Frame Group Start Address Register - __IO uint32_t EFF_GRP_sa; - - ///Offset: 0x00000014 - End of AF Tables register - __IO uint32_t ENDofTable; - - ///Offset: 0x00000018 - LUT Error Address register - __I uint32_t LUTerrAd; - - ///Offset: 0x0000001C - LUT Error Register - __I uint32_t LUTerr; - - ///Offset: 0x00000020 - CAN Central Transmit Status Register - __IO uint32_t FCANIE; - - ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0 - __IO uint32_t FCANIC0; - - ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1 - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t TxSR; - __I uint32_t RxSR; - __I uint32_t MSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller - __IO uint32_t MOD; - - ///Offset: 0x00000004 - Command bits that affect the state - __O uint32_t CMR; - - ///Offset: 0x00000008 - Global Controller Status and Error Counters - __IO uint32_t GSR; - - ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture - __I uint32_t ICR; - - ///Offset: 0x00000010 - Interrupt Enable Register - __IO uint32_t IER; - - ///Offset: 0x00000014 - Bus Timing Register - __IO uint32_t BTR; - - ///Offset: 0x00000018 - Error Warning Limit - __IO uint32_t EWL; - - ///Offset: 0x0000001C - Status Register - __I uint32_t SR; - - ///Offset: 0x00000020 - Receive frame status - __IO uint32_t RFS; - - ///Offset: 0x00000024 - Received Identifier - __IO uint32_t RID; - - ///Offset: 0x00000028 - Received data bytes 1-4 - __IO uint32_t RDA; - - ///Offset: 0x0000002C - Received data bytes 5-8 - __IO uint32_t RDB; - - ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1) - __IO uint32_t TFI1; - - ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1) - __IO uint32_t TID1; - - ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1) - __IO uint32_t TDA1; - - ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1) - __IO uint32_t TDB1; - - ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2) - __IO uint32_t TFI2; - - ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2) - __IO uint32_t TID2; - - ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2) - __IO uint32_t TDA2; - - ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2) - __IO uint32_t TDB2; - - ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3) - __IO uint32_t TFI3; - - ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3) - __IO uint32_t TID3; - - ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3) - __IO uint32_t TDA3; - - ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3) - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t IntStat; - __I uint32_t IntTCStat; - __O uint32_t IntTCClear; - __I uint32_t IntErrStat; - __O uint32_t IntErrClr; - __I uint32_t RawIntTCStat; - __I uint32_t RawIntErrStat; - __I uint32_t EnbldChns; - __IO uint32_t SoftBReq; - __IO uint32_t SoftSReq; - __IO uint32_t SoftLBReq; - __IO uint32_t SoftLSReq; - __IO uint32_t Config; - __IO uint32_t Sync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t CSrcAddr; - __IO uint32_t CDestAddr; - __IO uint32_t CLLI; - __IO uint32_t CControl; - __IO uint32_t CConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t Revision; /* USB Host Registers */ - __IO uint32_t Control; - __IO uint32_t CommandStatus; - __IO uint32_t InterruptStatus; - __IO uint32_t InterruptEnable; - __IO uint32_t InterruptDisable; - __IO uint32_t HCCA; - __I uint32_t PeriodCurrentED; - __IO uint32_t ControlHeadED; - __IO uint32_t ControlCurrentED; - __IO uint32_t BulkHeadED; - __IO uint32_t BulkCurrentED; - __I uint32_t DoneHead; - __IO uint32_t FmInterval; - __I uint32_t FmRemaining; - __I uint32_t FmNumber; - __IO uint32_t PeriodicStart; - __IO uint32_t LSTreshold; - __IO uint32_t RhDescriptorA; - __IO uint32_t RhDescriptorB; - __IO uint32_t RhStatus; - __IO uint32_t RhPortStatus1; - __IO uint32_t RhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t IntSt; /* USB On-The-Go Registers */ - __IO uint32_t IntEn; - __O uint32_t IntSet; - __O uint32_t IntClr; - __IO uint32_t StCtrl; - __IO uint32_t Tmr; - uint32_t RESERVED1[58]; - - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevIntPri; - - __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t EpIntEn; - __O uint32_t EpIntClr; - __O uint32_t EpIntSet; - __O uint32_t EpIntPri; - - __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t EpInd; - __IO uint32_t MaxPSize; - - __I uint32_t DMARSt; /* USB Device DMA Registers */ - __O uint32_t DMARClr; - __O uint32_t DMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t UDCAH; - __I uint32_t EpDMASt; - __O uint32_t EpDMAEn; - __O uint32_t EpDMADis; - __I uint32_t DMAIntSt; - __IO uint32_t DMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t EoTIntSt; - __O uint32_t EoTIntClr; - __O uint32_t EoTIntSet; - __I uint32_t NDDRIntSt; - __O uint32_t NDDRIntClr; - __O uint32_t NDDRIntSet; - __I uint32_t SysErrIntSt; - __O uint32_t SysErrIntClr; - __O uint32_t SysErrIntSet; - uint32_t RESERVED4[15]; - - union { - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_TX; - }; - __IO uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[824]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __I uint32_t RxFilterWoLStatus; - __O uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -/*------------- LCD controller (LCD) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t TIMH; /* LCD Registers */ - __IO uint32_t TIMV; - __IO uint32_t POL; - __IO uint32_t LE; - __IO uint32_t UPBASE; - __IO uint32_t LPBASE; - __IO uint32_t CTRL; - __IO uint32_t INTMSK; - __I uint32_t INTRAW; - __I uint32_t INTSTAT; - __O uint32_t INTCLR; - __I uint32_t UPCURR; - __I uint32_t LPCURR; - uint32_t RESERVED0[115]; - __IO uint32_t PAL[128]; - uint32_t RESERVED1[256]; - __IO uint32_t CRSR_IMG[256]; - __IO uint32_t CRSR_CTRL; - __IO uint32_t CRSR_CFG; - __IO uint32_t CRSR_PAL0; - __IO uint32_t CRSR_PAL1; - __IO uint32_t CRSR_XY; - __IO uint32_t CRSR_CLIP; - uint32_t RESERVED2[2]; - __IO uint32_t CRSR_INTMSK; - __O uint32_t CRSR_INTCLR; - __I uint32_t CRSR_INTRAW; - __I uint32_t CRSR_INTSTAT; -} LPC_LCD_TypeDef; - -/*------------- External Memory Controller (EMC) -----------------------------*/ -typedef struct -{ - __IO uint32_t Control; - __I uint32_t Status; - __IO uint32_t Config; - uint32_t RESERVED0[5]; - __IO uint32_t DynamicControl; - __IO uint32_t DynamicRefresh; - __IO uint32_t DynamicReadConfig; - uint32_t RESERVED1[1]; - __IO uint32_t DynamicRP; - __IO uint32_t DynamicRAS; - __IO uint32_t DynamicSREX; - __IO uint32_t DynamicAPR; - __IO uint32_t DynamicDAL; - __IO uint32_t DynamicWR; - __IO uint32_t DynamicRC; - __IO uint32_t DynamicRFC; - __IO uint32_t DynamicXSR; - __IO uint32_t DynamicRRD; - __IO uint32_t DynamicMRD; - uint32_t RESERVED2[9]; - __IO uint32_t StaticExtendedWait; - uint32_t RESERVED3[31]; - __IO uint32_t DynamicConfig0; - __IO uint32_t DynamicRasCas0; - uint32_t RESERVED4[6]; - __IO uint32_t DynamicConfig1; - __IO uint32_t DynamicRasCas1; - uint32_t RESERVED5[6]; - __IO uint32_t DynamicConfig2; - __IO uint32_t DynamicRasCas2; - uint32_t RESERVED6[6]; - __IO uint32_t DynamicConfig3; - __IO uint32_t DynamicRasCas3; - uint32_t RESERVED7[38]; - __IO uint32_t StaticConfig0; - __IO uint32_t StaticWaitWen0; - __IO uint32_t StaticWaitOen0; - __IO uint32_t StaticWaitRd0; - __IO uint32_t StaticWaitPage0; - __IO uint32_t StaticWaitWr0; - __IO uint32_t StaticWaitTurn0; - uint32_t RESERVED8[1]; - __IO uint32_t StaticConfig1; - __IO uint32_t StaticWaitWen1; - __IO uint32_t StaticWaitOen1; - __IO uint32_t StaticWaitRd1; - __IO uint32_t StaticWaitPage1; - __IO uint32_t StaticWaitWr1; - __IO uint32_t StaticWaitTurn1; - uint32_t RESERVED9[1]; - __IO uint32_t StaticConfig2; - __IO uint32_t StaticWaitWen2; - __IO uint32_t StaticWaitOen2; - __IO uint32_t StaticWaitRd2; - __IO uint32_t StaticWaitPage2; - __IO uint32_t StaticWaitWr2; - __IO uint32_t StaticWaitTurn2; - uint32_t RESERVED10[1]; - __IO uint32_t StaticConfig3; - __IO uint32_t StaticWaitWen3; - __IO uint32_t StaticWaitOen3; - __IO uint32_t StaticWaitRd3; - __IO uint32_t StaticWaitPage3; - __IO uint32_t StaticWaitWr3; - __IO uint32_t StaticWaitTurn3; -} LPC_EMC_TypeDef; - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - struct { - __O uint32_t DATA; - } WR_DATA_DWORD; - - struct { - __O uint16_t DATA; - uint16_t RESERVED; - }WR_DATA_WORD; - - struct { - __O uint8_t DATA; - uint8_t RESERVED[3]; - }WR_DATA_BYTE; - }; -} LPC_CRC_TypeDef; - -/*------------- EEPROM Controller (EEPROM) -----------------------------------*/ -typedef struct -{ - __IO uint32_t CMD; /* 0x0080 */ - __IO uint32_t ADDR; - __IO uint32_t WDATA; - __IO uint32_t RDATA; - __IO uint32_t WSTATE; /* 0x0090 */ - __IO uint32_t CLKDIV; - __IO uint32_t PWRDWN; /* 0x0098 */ - uint32_t RESERVED0[975]; - __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ - __IO uint32_t INT_SET_ENABLE; - __IO uint32_t INT_STATUS; /* 0x0FE0 */ - __IO uint32_t INT_ENABLE; - __IO uint32_t INT_CLR_STATUS; - __IO uint32_t INT_SET_STATUS; -} LPC_EEPROM_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_PERI_RAM_BASE (0x20000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHBRAM1_BASE (0x20004000UL) -#define LPC_AHB_BASE (0x20080000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) -#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) -#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) -#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) - -#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) -#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) -#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) - -#endif // __LPC177x_8x_H__ diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC407x_8x_177x_8x.h b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC407x_8x_177x_8x.h deleted file mode 100644 index 9942f382e5..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC407x_8x_177x_8x.h +++ /dev/null @@ -1,1514 +0,0 @@ -/****************************************************************************************************//** -* $Id$ LPC407x_8x_177x_8x.h 2012-04-25 -*//** - * @file LPC407x_8x_177x_8x.h - * - * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for - * NXP LPC407x_8x_177x_8x. - * @version V0.7 - * @date 20. June 2012 - * @author NXP MCU SW Application Team -* -* Copyright(C) 2012, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __LPC407x_8x_177x_8x_H__ -#define __LPC407x_8x_177x_8x_H__ - - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - Reserved0_IRQn = 13, /*!< Reserved */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /*!< USB Activity interrupt */ - CANActivity_IRQn = 34, /*!< CAN Activity interrupt */ - UART4_IRQn = 35, /*!< UART4 Interrupt */ - SSP2_IRQn = 36, /*!< SSP2 Interrupt */ - LCD_IRQn = 37, /*!< LCD Interrupt */ - GPIO_IRQn = 38, /*!< GPIO Interrupt */ - PWM0_IRQn = 39, /*!< 39 PWM0 */ - EEPROM_IRQn = 40, /*!< 40 EEPROM */ - CMP0_IRQn = 41, /*!< 41 CMP0 */ - CMP1_IRQn = 42 /*!< 42 CMP1 */ -} IRQn_Type; - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ -#ifdef CORE_M4 -/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */ -#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ - - -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ -#else -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ - -#endif - -#include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */ - - - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#elif defined ( __ICCARM__ ) -#pragma language=save -#pragma language=extended -#endif - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t IntStat; - __I uint32_t IntTCStat; - __O uint32_t IntTCClear; - __I uint32_t IntErrStat; - __O uint32_t IntErrClr; - __I uint32_t RawIntTCStat; - __I uint32_t RawIntErrStat; - __I uint32_t EnbldChns; - __IO uint32_t SoftBReq; - __IO uint32_t SoftSReq; - __IO uint32_t SoftLBReq; - __IO uint32_t SoftLSReq; - __IO uint32_t Config; - __IO uint32_t Sync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t CSrcAddr; - __IO uint32_t CDestAddr; - __IO uint32_t CLLI; - __IO uint32_t CControl; - __IO uint32_t CConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ - __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ - __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ - __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ - __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ - __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ - __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ - uint32_t RESERVED2[4]; - __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ - __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ - __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */ - uint32_t RESERVED3[13]; - __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */ - __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */ - __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */ - __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ - __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ - __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ - uint32_t RESERVED4[10]; - __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ - uint32_t RESERVED5[1]; - __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ - __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ - __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */ - __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */ - uint32_t RESERVED8; - __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */ - __IO uint32_t SPIFICLKSEL; - __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */ - uint32_t RESERVED10[1]; - __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ - __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ - __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ - __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */ - __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */ - uint32_t RESERVED11[2]; - __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */ - __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */ - } LPC_SC_TypeDef; -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __I uint32_t RxFilterWoLStatus; - __O uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -/*------------- LCD controller (LCD) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t TIMH; /* LCD Registers */ - __IO uint32_t TIMV; - __IO uint32_t POL; - __IO uint32_t LE; - __IO uint32_t UPBASE; - __IO uint32_t LPBASE; - __IO uint32_t CTRL; - __IO uint32_t INTMSK; - __I uint32_t INTRAW; - __I uint32_t INTSTAT; - __O uint32_t INTCLR; - __I uint32_t UPCURR; - __I uint32_t LPCURR; - uint32_t RESERVED0[115]; - __IO uint32_t PAL[128]; - uint32_t RESERVED1[256]; - __IO uint32_t CRSR_IMG[256]; - __IO uint32_t CRSR_CTRL; - __IO uint32_t CRSR_CFG; - __IO uint32_t CRSR_PAL0; - __IO uint32_t CRSR_PAL1; - __IO uint32_t CRSR_XY; - __IO uint32_t CRSR_CLIP; - uint32_t RESERVED2[2]; - __IO uint32_t CRSR_INTMSK; - __O uint32_t CRSR_INTCLR; - __I uint32_t CRSR_INTRAW; - __I uint32_t CRSR_INTSTAT; -} LPC_LCD_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t Revision; /* USB Host Registers */ - __IO uint32_t Control; - __IO uint32_t CommandStatus; - __IO uint32_t InterruptStatus; - __IO uint32_t InterruptEnable; - __IO uint32_t InterruptDisable; - __IO uint32_t HCCA; - __I uint32_t PeriodCurrentED; - __IO uint32_t ControlHeadED; - __IO uint32_t ControlCurrentED; - __IO uint32_t BulkHeadED; - __IO uint32_t BulkCurrentED; - __I uint32_t DoneHead; - __IO uint32_t FmInterval; - __I uint32_t FmRemaining; - __I uint32_t FmNumber; - __IO uint32_t PeriodicStart; - __IO uint32_t LSTreshold; - __IO uint32_t RhDescriptorA; - __IO uint32_t RhDescriptorB; - __IO uint32_t RhStatus; - __IO uint32_t RhPortStatus1; - __IO uint32_t RhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t IntSt; /* USB On-The-Go Registers */ - __IO uint32_t IntEn; - __O uint32_t IntSet; - __O uint32_t IntClr; - __IO uint32_t StCtrl; - __IO uint32_t Tmr; - uint32_t RESERVED1[58]; - - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevIntPri; - - __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t EpIntEn; - __O uint32_t EpIntClr; - __O uint32_t EpIntSet; - __O uint32_t EpIntPri; - - __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t EpInd; - __IO uint32_t MaxPSize; - - __I uint32_t DMARSt; /* USB Device DMA Registers */ - __O uint32_t DMARClr; - __O uint32_t DMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t UDCAH; - __I uint32_t EpDMASt; - __O uint32_t EpDMAEn; - __O uint32_t EpDMADis; - __I uint32_t DMAIntSt; - __IO uint32_t DMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t EoTIntSt; - __O uint32_t EoTIntClr; - __O uint32_t EoTIntSet; - __I uint32_t NDDRIntSt; - __O uint32_t NDDRIntClr; - __O uint32_t NDDRIntSet; - __I uint32_t SysErrIntSt; - __O uint32_t SysErrIntClr; - __O uint32_t SysErrIntSet; - uint32_t RESERVED4[15]; - - union { - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_TX; - }; - __IO uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[824]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - struct { - __O uint32_t DATA; - } WR_DATA_DWORD; - - struct { - __O uint16_t DATA; - uint16_t RESERVED; - }WR_DATA_WORD; - - struct { - __O uint8_t DATA; - uint8_t RESERVED[3]; - }WR_DATA_BYTE; - }; -} LPC_CRC_TypeDef; -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - __IO uint32_t DIR; - uint32_t RESERVED0[3]; - __IO uint32_t MASK; - __IO uint32_t PIN; - __IO uint32_t SET; - __O uint32_t CLR; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- External Memory Controller (EMC) -----------------------------*/ -typedef struct -{ - __IO uint32_t Control; - __I uint32_t Status; - __IO uint32_t Config; - uint32_t RESERVED0[5]; - __IO uint32_t DynamicControl; - __IO uint32_t DynamicRefresh; - __IO uint32_t DynamicReadConfig; - uint32_t RESERVED1[1]; - __IO uint32_t DynamicRP; - __IO uint32_t DynamicRAS; - __IO uint32_t DynamicSREX; - __IO uint32_t DynamicAPR; - __IO uint32_t DynamicDAL; - __IO uint32_t DynamicWR; - __IO uint32_t DynamicRC; - __IO uint32_t DynamicRFC; - __IO uint32_t DynamicXSR; - __IO uint32_t DynamicRRD; - __IO uint32_t DynamicMRD; - uint32_t RESERVED2[9]; - __IO uint32_t StaticExtendedWait; - uint32_t RESERVED3[31]; - __IO uint32_t DynamicConfig0; - __IO uint32_t DynamicRasCas0; - uint32_t RESERVED4[6]; - __IO uint32_t DynamicConfig1; - __IO uint32_t DynamicRasCas1; - uint32_t RESERVED5[6]; - __IO uint32_t DynamicConfig2; - __IO uint32_t DynamicRasCas2; - uint32_t RESERVED6[6]; - __IO uint32_t DynamicConfig3; - __IO uint32_t DynamicRasCas3; - uint32_t RESERVED7[38]; - __IO uint32_t StaticConfig0; - __IO uint32_t StaticWaitWen0; - __IO uint32_t StaticWaitOen0; - __IO uint32_t StaticWaitRd0; - __IO uint32_t StaticWaitPage0; - __IO uint32_t StaticWaitWr0; - __IO uint32_t StaticWaitTurn0; - uint32_t RESERVED8[1]; - __IO uint32_t StaticConfig1; - __IO uint32_t StaticWaitWen1; - __IO uint32_t StaticWaitOen1; - __IO uint32_t StaticWaitRd1; - __IO uint32_t StaticWaitPage1; - __IO uint32_t StaticWaitWr1; - __IO uint32_t StaticWaitTurn1; - uint32_t RESERVED9[1]; - __IO uint32_t StaticConfig2; - __IO uint32_t StaticWaitWen2; - __IO uint32_t StaticWaitOen2; - __IO uint32_t StaticWaitRd2; - __IO uint32_t StaticWaitPage2; - __IO uint32_t StaticWaitWr2; - __IO uint32_t StaticWaitTurn2; - uint32_t RESERVED10[1]; - __IO uint32_t StaticConfig3; - __IO uint32_t StaticWaitWen3; - __IO uint32_t StaticWaitOen3; - __IO uint32_t StaticWaitRd3; - __IO uint32_t StaticWaitPage3; - __IO uint32_t StaticWaitWr3; - __IO uint32_t StaticWaitTurn3; -} LPC_EMC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t MOD; - uint8_t RESERVED0[3]; - __IO uint32_t TC; - __O uint8_t FEED; - uint8_t RESERVED1[3]; - __I uint32_t TV; - uint32_t RESERVED2; - __IO uint32_t WARNINT; - __IO uint32_t WINDOW; -} LPC_WDT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - uint32_t RESERVED0[2]; - __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ -} LPC_TIM_TypeDef; - - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */ - __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */ - uint32_t RESERVED0; - __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */ - __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */ - __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */ - __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */ - __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */ - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */ -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ -/* There are three types of UARTs on the chip: -(1) UART0,UART2, and UART3 are the standard UART. -(2) UART1 is the standard with modem capability. -(3) USART(UART4) is the sync/async UART with smart card capability. -More details can be found on the Users Manual. */ - -#if 0 -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; -#else -typedef struct -{ - union - { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union - { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union - { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7];//Reserved - __I uint8_t LSR; - uint8_t RESERVED2[7];//Reserved - __IO uint8_t SCR; - uint8_t RESERVED3[3];//Reserved - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3];//Reserved - __IO uint8_t FDR; - uint8_t RESERVED5[7];//Reserved - __IO uint8_t TER; - uint8_t RESERVED8[27];//Reserved - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3];//Reserved - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3];//Reserved - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3];//Reserved - __I uint8_t FIFOLVL; -}LPC_UART_TypeDef; -#endif - - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; - __I uint8_t FIFOLVL; -} LPC_UART1_TypeDef; - -typedef struct -{ - union { - __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ - __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ - __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ - }; - union { - __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ - __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ - }; - union { - __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ - __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ - }; - __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ - __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ - __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ - __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ - __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */ - __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ - __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */ - __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */ - __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */ - uint32_t RESERVED0[2]; - __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */ - uint32_t RESERVED1; - __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */ - __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ - __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ - __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ - __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */ - __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */ - uint32_t RESERVED2[989]; - __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */ - __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */ - __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */ - __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */ - __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */ - __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */ - __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */ - uint32_t RESERVED3[3]; - __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */ -} LPC_UART4_TypeDef; -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ - __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ - __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ - __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ - __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ - __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ - __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ - __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ - __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ - __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ - __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ - __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ - __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ - __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ - __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ -} LPC_I2C_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; - __IO uint32_t ERSTATUS; - __IO uint32_t ERCONTROL; - __IO uint32_t ERCOUNTERS; - uint32_t RESERVED22; - __IO uint32_t ERFIRSTSTAMP0; - __IO uint32_t ERFIRSTSTAMP1; - __IO uint32_t ERFIRSTSTAMP2; - uint32_t RESERVED23; - __IO uint32_t ERLASTSTAMP0; - __IO uint32_t ERLASTSTAMP1; - __IO uint32_t ERLASTSTAMP2; -} LPC_RTC_TypeDef; - - - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t P0_0; /* 0x000 */ - __IO uint32_t P0_1; - __IO uint32_t P0_2; - __IO uint32_t P0_3; - __IO uint32_t P0_4; - __IO uint32_t P0_5; - __IO uint32_t P0_6; - __IO uint32_t P0_7; - - __IO uint32_t P0_8; /* 0x020 */ - __IO uint32_t P0_9; - __IO uint32_t P0_10; - __IO uint32_t P0_11; - __IO uint32_t P0_12; - __IO uint32_t P0_13; - __IO uint32_t P0_14; - __IO uint32_t P0_15; - - __IO uint32_t P0_16; /* 0x040 */ - __IO uint32_t P0_17; - __IO uint32_t P0_18; - __IO uint32_t P0_19; - __IO uint32_t P0_20; - __IO uint32_t P0_21; - __IO uint32_t P0_22; - __IO uint32_t P0_23; - - __IO uint32_t P0_24; /* 0x060 */ - __IO uint32_t P0_25; - __IO uint32_t P0_26; - __IO uint32_t P0_27; - __IO uint32_t P0_28; - __IO uint32_t P0_29; - __IO uint32_t P0_30; - __IO uint32_t P0_31; - - __IO uint32_t P1_0; /* 0x080 */ - __IO uint32_t P1_1; - __IO uint32_t P1_2; - __IO uint32_t P1_3; - __IO uint32_t P1_4; - __IO uint32_t P1_5; - __IO uint32_t P1_6; - __IO uint32_t P1_7; - - __IO uint32_t P1_8; /* 0x0A0 */ - __IO uint32_t P1_9; - __IO uint32_t P1_10; - __IO uint32_t P1_11; - __IO uint32_t P1_12; - __IO uint32_t P1_13; - __IO uint32_t P1_14; - __IO uint32_t P1_15; - - __IO uint32_t P1_16; /* 0x0C0 */ - __IO uint32_t P1_17; - __IO uint32_t P1_18; - __IO uint32_t P1_19; - __IO uint32_t P1_20; - __IO uint32_t P1_21; - __IO uint32_t P1_22; - __IO uint32_t P1_23; - - __IO uint32_t P1_24; /* 0x0E0 */ - __IO uint32_t P1_25; - __IO uint32_t P1_26; - __IO uint32_t P1_27; - __IO uint32_t P1_28; - __IO uint32_t P1_29; - __IO uint32_t P1_30; - __IO uint32_t P1_31; - - __IO uint32_t P2_0; /* 0x100 */ - __IO uint32_t P2_1; - __IO uint32_t P2_2; - __IO uint32_t P2_3; - __IO uint32_t P2_4; - __IO uint32_t P2_5; - __IO uint32_t P2_6; - __IO uint32_t P2_7; - - __IO uint32_t P2_8; /* 0x120 */ - __IO uint32_t P2_9; - __IO uint32_t P2_10; - __IO uint32_t P2_11; - __IO uint32_t P2_12; - __IO uint32_t P2_13; - __IO uint32_t P2_14; - __IO uint32_t P2_15; - - __IO uint32_t P2_16; /* 0x140 */ - __IO uint32_t P2_17; - __IO uint32_t P2_18; - __IO uint32_t P2_19; - __IO uint32_t P2_20; - __IO uint32_t P2_21; - __IO uint32_t P2_22; - __IO uint32_t P2_23; - - __IO uint32_t P2_24; /* 0x160 */ - __IO uint32_t P2_25; - __IO uint32_t P2_26; - __IO uint32_t P2_27; - __IO uint32_t P2_28; - __IO uint32_t P2_29; - __IO uint32_t P2_30; - __IO uint32_t P2_31; - - __IO uint32_t P3_0; /* 0x180 */ - __IO uint32_t P3_1; - __IO uint32_t P3_2; - __IO uint32_t P3_3; - __IO uint32_t P3_4; - __IO uint32_t P3_5; - __IO uint32_t P3_6; - __IO uint32_t P3_7; - - __IO uint32_t P3_8; /* 0x1A0 */ - __IO uint32_t P3_9; - __IO uint32_t P3_10; - __IO uint32_t P3_11; - __IO uint32_t P3_12; - __IO uint32_t P3_13; - __IO uint32_t P3_14; - __IO uint32_t P3_15; - - __IO uint32_t P3_16; /* 0x1C0 */ - __IO uint32_t P3_17; - __IO uint32_t P3_18; - __IO uint32_t P3_19; - __IO uint32_t P3_20; - __IO uint32_t P3_21; - __IO uint32_t P3_22; - __IO uint32_t P3_23; - - __IO uint32_t P3_24; /* 0x1E0 */ - __IO uint32_t P3_25; - __IO uint32_t P3_26; - __IO uint32_t P3_27; - __IO uint32_t P3_28; - __IO uint32_t P3_29; - __IO uint32_t P3_30; - __IO uint32_t P3_31; - - __IO uint32_t P4_0; /* 0x200 */ - __IO uint32_t P4_1; - __IO uint32_t P4_2; - __IO uint32_t P4_3; - __IO uint32_t P4_4; - __IO uint32_t P4_5; - __IO uint32_t P4_6; - __IO uint32_t P4_7; - - __IO uint32_t P4_8; /* 0x220 */ - __IO uint32_t P4_9; - __IO uint32_t P4_10; - __IO uint32_t P4_11; - __IO uint32_t P4_12; - __IO uint32_t P4_13; - __IO uint32_t P4_14; - __IO uint32_t P4_15; - - __IO uint32_t P4_16; /* 0x240 */ - __IO uint32_t P4_17; - __IO uint32_t P4_18; - __IO uint32_t P4_19; - __IO uint32_t P4_20; - __IO uint32_t P4_21; - __IO uint32_t P4_22; - __IO uint32_t P4_23; - - __IO uint32_t P4_24; /* 0x260 */ - __IO uint32_t P4_25; - __IO uint32_t P4_26; - __IO uint32_t P4_27; - __IO uint32_t P4_28; - __IO uint32_t P4_29; - __IO uint32_t P4_30; - __IO uint32_t P4_31; - - __IO uint32_t P5_0; /* 0x280 */ - __IO uint32_t P5_1; - __IO uint32_t P5_2; - __IO uint32_t P5_3; - __IO uint32_t P5_4; /* 0x290 */ -} LPC_IOCON_TypeDef; - - - - - - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ - __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ - __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ - __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ - __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ - __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ - __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ - __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ - __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ - __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - ///Offset: 0x00000000 - Acceptance Filter Register - __IO uint32_t AFMR; - - ///Offset: 0x00000004 - Standard Frame Individual Start Address Register - __IO uint32_t SFF_sa; - - ///Offset: 0x00000008 - Standard Frame Group Start Address Register - __IO uint32_t SFF_GRP_sa; - - ///Offset: 0x0000000C - Extended Frame Start Address Register - __IO uint32_t EFF_sa; - - ///Offset: 0x00000010 - Extended Frame Group Start Address Register - __IO uint32_t EFF_GRP_sa; - - ///Offset: 0x00000014 - End of AF Tables register - __IO uint32_t ENDofTable; - - ///Offset: 0x00000018 - LUT Error Address register - __I uint32_t LUTerrAd; - - ///Offset: 0x0000001C - LUT Error Register - __I uint32_t LUTerr; - - ///Offset: 0x00000020 - CAN Central Transmit Status Register - __IO uint32_t FCANIE; - - ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0 - __IO uint32_t FCANIC0; - - ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1 - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t TxSR; - __I uint32_t RxSR; - __I uint32_t MSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller - __IO uint32_t MOD; - - ///Offset: 0x00000004 - Command bits that affect the state - __O uint32_t CMR; - - ///Offset: 0x00000008 - Global Controller Status and Error Counters - __IO uint32_t GSR; - - ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture - __I uint32_t ICR; - - ///Offset: 0x00000010 - Interrupt Enable Register - __IO uint32_t IER; - - ///Offset: 0x00000014 - Bus Timing Register - __IO uint32_t BTR; - - ///Offset: 0x00000018 - Error Warning Limit - __IO uint32_t EWL; - - ///Offset: 0x0000001C - Status Register - __I uint32_t SR; - - ///Offset: 0x00000020 - Receive frame status - __IO uint32_t RFS; - - ///Offset: 0x00000024 - Received Identifier - __IO uint32_t RID; - - ///Offset: 0x00000028 - Received data bytes 1-4 - __IO uint32_t RDA; - - ///Offset: 0x0000002C - Received data bytes 5-8 - __IO uint32_t RDB; - - ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1) - __IO uint32_t TFI1; - - ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1) - __IO uint32_t TID1; - - ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1) - __IO uint32_t TDA1; - - ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1) - __IO uint32_t TDB1; - - ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2) - __IO uint32_t TFI2; - - ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2) - __IO uint32_t TID2; - - ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2) - __IO uint32_t TDA2; - - ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2) - __IO uint32_t TDB2; - - ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3) - __IO uint32_t TFI3; - - ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3) - __IO uint32_t TID3; - - ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3) - __IO uint32_t TDA3; - - ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3) - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CTRL; - __IO uint32_t CNTVAL; -} LPC_DAC_TypeDef; - - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t DAO; - __IO uint32_t DAI; - __O uint32_t TXFIFO; - __I uint32_t RXFIFO; - __I uint32_t STATE; - __IO uint32_t DMA1; - __IO uint32_t DMA2; - __IO uint32_t IRQ; - __IO uint32_t TXRATE; - __IO uint32_t RXRATE; - __IO uint32_t TXBITRATE; - __IO uint32_t RXBITRATE; - __IO uint32_t TXMODE; - __IO uint32_t RXMODE; -} LPC_I2S_TypeDef; - - - - - - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t CON; - __O uint32_t CON_SET; - __O uint32_t CON_CLR; - __I uint32_t CAPCON; - __O uint32_t CAPCON_SET; - __O uint32_t CAPCON_CLR; - __IO uint32_t TC0; - __IO uint32_t TC1; - __IO uint32_t TC2; - __IO uint32_t LIM0; - __IO uint32_t LIM1; - __IO uint32_t LIM2; - __IO uint32_t MAT0; - __IO uint32_t MAT1; - __IO uint32_t MAT2; - __IO uint32_t DT; - __IO uint32_t CP; - __IO uint32_t CAP0; - __IO uint32_t CAP1; - __IO uint32_t CAP2; - __I uint32_t INTEN; - __O uint32_t INTEN_SET; - __O uint32_t INTEN_CLR; - __I uint32_t CNTCON; - __O uint32_t CNTCON_SET; - __O uint32_t CNTCON_CLR; - __I uint32_t INTF; - __O uint32_t INTF_SET; - __O uint32_t INTF_CLR; - __O uint32_t CAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t CON; - __I uint32_t STAT; - __IO uint32_t CONF; - __I uint32_t POS; - __IO uint32_t MAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP0; - __IO uint32_t LOAD; - __I uint32_t TIME; - __I uint32_t VEL; - __I uint32_t CAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTERPHA; - __IO uint32_t FILTERPHB; - __IO uint32_t FILTERINX; - __IO uint32_t WINDOW; - __IO uint32_t INXCMP1; - __IO uint32_t INXCMP2; - uint32_t RESERVED0[993]; - __O uint32_t IEC; - __O uint32_t IES; - __I uint32_t INTSTAT; - __I uint32_t IE; - __O uint32_t CLR; - __O uint32_t SET; -} LPC_QEI_TypeDef; - -/*------------- SD/MMC card Interface (MCI)-----------------------------------*/ -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLOCK; - __IO uint32_t ARGUMENT; - __IO uint32_t COMMAND; - __I uint32_t RESP_CMD; - __I uint32_t RESP0; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __IO uint32_t DATATMR; - __IO uint32_t DATALEN; - __IO uint32_t DATACTRL; - __I uint32_t DATACNT; - __I uint32_t STATUS; - __O uint32_t CLEAR; - __IO uint32_t MASK0; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO[16]; -} LPC_MCI_TypeDef; - - - - - - - - - - -/*------------- EEPROM Controller (EEPROM) -----------------------------------*/ -typedef struct -{ - __IO uint32_t CMD; /* 0x0080 */ - __IO uint32_t ADDR; - __IO uint32_t WDATA; - __IO uint32_t RDATA; - __IO uint32_t WSTATE; /* 0x0090 */ - __IO uint32_t CLKDIV; - __IO uint32_t PWRDWN; /* 0x0098 */ - uint32_t RESERVED0[975]; - __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ - __IO uint32_t INT_SET_ENABLE; - __IO uint32_t INT_STATUS; /* 0x0FE0 */ - __IO uint32_t INT_ENABLE; - __IO uint32_t INT_CLR_STATUS; - __IO uint32_t INT_SET_STATUS; -} LPC_EEPROM_TypeDef; - - -/*------------- COMPARATOR ----------------------------------------------------*/ - -typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */ - __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */ - __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */ -} LPC_COMPARATOR_Type; - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#elif defined ( __ICCARM__ ) -#pragma language=restore -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_PERI_RAM_BASE (0x20000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHBRAM1_BASE (0x20004000UL) -#define LPC_AHB_BASE (0x20080000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) -#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) -#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) -#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) - -#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) -#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) -#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) - - - -#endif // __LPC407x_8x_177x_8x_H__ diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC177x_8x.h b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC177x_8x.h deleted file mode 100644 index 464225eca3..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC177x_8x.h +++ /dev/null @@ -1,89 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC177x_8x.h 2011-06-02 -*//** -* @file system_LPC177x_8x.h -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC177x_8x Device Series -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __SYSTEM_LPC177x_8x_H -#define __SYSTEM_LPC177x_8x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <stdint.h> - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ -extern uint32_t EMCClock; /*!< EMC Clock */ -extern uint32_t USBClock; /*!< USB Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ -#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */ -#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */ - - - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC177x_8x_H */ diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC407x_8x_177x_8x.h b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC407x_8x_177x_8x.h deleted file mode 100644 index 18a54a0d7f..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC407x_8x_177x_8x.h +++ /dev/null @@ -1,89 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02 -*//** -* @file system_LPC407x_8x_177x_8x.h -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC Device Series -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#ifndef __SYSTEM_LPC407x_8x_177x_8x_H -#define __SYSTEM_LPC407x_8x_177x_8x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <stdint.h> - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ -extern uint32_t EMCClock; /*!< EMC Clock */ -extern uint32_t USBClock; /*!< USB Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ -#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */ -#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */ - - - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */ diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC177x_8x.s b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC177x_8x.s deleted file mode 100644 index 59cc885de3..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC177x_8x.s +++ /dev/null @@ -1,301 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC177x_8x.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC177x_8x Device Series -; * @version: V1.20 -; * @date: 07. October 2010 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: reserved, not for SPIFI anymore - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: SD/MMC card I/F - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup - DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - ;EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT PLL0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT MCI_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - EXPORT PLL1_IRQHandler [WEAK] - EXPORT USBActivity_IRQHandler [WEAK] - EXPORT CANActivity_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT SSP2_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT GPIO_IRQHandler [WEAK] - EXPORT PWM0_IRQHandler [WEAK] - EXPORT EEPROM_IRQHandler [WEAK] - -WDT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PWM1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -;SPIFI_IRQHandler ;not used -SSP0_IRQHandler -SSP1_IRQHandler -PLL0_IRQHandler -RTC_IRQHandler -EINT0_IRQHandler -EINT1_IRQHandler -EINT2_IRQHandler -EINT3_IRQHandler -ADC_IRQHandler -BOD_IRQHandler -USB_IRQHandler -CAN_IRQHandler -DMA_IRQHandler -I2S_IRQHandler -ENET_IRQHandler -MCI_IRQHandler -MCPWM_IRQHandler -QEI_IRQHandler -PLL1_IRQHandler -USBActivity_IRQHandler -CANActivity_IRQHandler -UART4_IRQHandler -SSP2_IRQHandler -LCD_IRQHandler -GPIO_IRQHandler -PWM0_IRQHandler -EEPROM_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s deleted file mode 100644 index bca9de93c8..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s +++ /dev/null @@ -1,302 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC407x_8x.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the NXP LPC407x_8x Device Series -; * @version: V1.20 -; * @date: 16. January 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M4 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - ; DCD 0xEFFFF5D6 ; Reserved- vector sum - DCD 0xEFFFF39E ; Reserved- vector sum - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: reserved, not for SPIFI anymore - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: SD/MMC card I/F - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup - DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - ;EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT PLL0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT MCI_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - EXPORT PLL1_IRQHandler [WEAK] - EXPORT USBActivity_IRQHandler [WEAK] - EXPORT CANActivity_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT SSP2_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT GPIO_IRQHandler [WEAK] - EXPORT PWM0_IRQHandler [WEAK] - EXPORT EEPROM_IRQHandler [WEAK] - -WDT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PWM1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -;SPIFI_IRQHandler ;not used -SSP0_IRQHandler -SSP1_IRQHandler -PLL0_IRQHandler -RTC_IRQHandler -EINT0_IRQHandler -EINT1_IRQHandler -EINT2_IRQHandler -EINT3_IRQHandler -ADC_IRQHandler -BOD_IRQHandler -USB_IRQHandler -CAN_IRQHandler -DMA_IRQHandler -I2S_IRQHandler -ENET_IRQHandler -MCI_IRQHandler -MCPWM_IRQHandler -QEI_IRQHandler -PLL1_IRQHandler -USBActivity_IRQHandler -CANActivity_IRQHandler -UART4_IRQHandler -SSP2_IRQHandler -LCD_IRQHandler -GPIO_IRQHandler -PWM0_IRQHandler -EEPROM_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC177x_8x.s b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC177x_8x.s deleted file mode 100644 index 5d966a39b3..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC177x_8x.s +++ /dev/null @@ -1,279 +0,0 @@ -/*****************************************************************************/ -/* startup_LPC17xx.s: Startup file for LPC17xx device series */ -/*****************************************************************************/ -/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ -/*****************************************************************************/ - - -/* -//*** <<< Use Configuration Wizard in Context Menu >>> *** -*/ - - -/* -// <h> Stack Configuration -// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// </h> -*/ - - .equ Stack_Size, 0x00000100 - .section ".stack", "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - - -/* -// <h> Heap Configuration -// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// </h> -*/ - - .equ Heap_Size, 0x00001000 - - .section ".heap", "w" - .align 3 - .globl __cs3_heap_start - .globl __cs3_heap_end -__cs3_heap_start: - .if Heap_Size - .space Heap_Size - .endif -__cs3_heap_end: - - -/* Vector Table */ - - .section ".cs3.interrupt_vector" - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long __cs3_stack /* Top of Stack */ - .long __cs3_reset /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long WDT_IRQHandler /* 16: Watchdog Timer */ - .long TIMER0_IRQHandler /* 17: Timer0 */ - .long TIMER1_IRQHandler /* 18: Timer1 */ - .long TIMER2_IRQHandler /* 19: Timer2 */ - .long TIMER3_IRQHandler /* 20: Timer3 */ - .long UART0_IRQHandler /* 21: UART0 */ - .long UART1_IRQHandler /* 22: UART1 */ - .long UART2_IRQHandler /* 23: UART2 */ - .long UART3_IRQHandler /* 24: UART3 */ - .long PWM1_IRQHandler /* 25: PWM1 */ - .long I2C0_IRQHandler /* 26: I2C0 */ - .long I2C1_IRQHandler /* 27: I2C1 */ - .long I2C2_IRQHandler /* 28: I2C2 */ - .long 0 /* 29: Reserved, not for SPIFI anymore */ - .long SSP0_IRQHandler /* 30: SSP0 */ - .long SSP1_IRQHandler /* 31: SSP1 */ - .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ - .long RTC_IRQHandler /* 33: Real Time Clock */ - .long EINT0_IRQHandler /* 34: External Interrupt 0 */ - .long EINT1_IRQHandler /* 35: External Interrupt 1 */ - .long EINT2_IRQHandler /* 36: External Interrupt 2 */ - .long EINT3_IRQHandler /* 37: External Interrupt 3 */ - .long ADC_IRQHandler /* 38: A/D Converter */ - .long BOD_IRQHandler /* 39: Brown-Out Detect */ - .long USB_IRQHandler /* 40: USB */ - .long CAN_IRQHandler /* 41: CAN */ - .long DMA_IRQHandler /* 42: General Purpose DMA */ - .long I2S_IRQHandler /* 43: I2S */ - .long ENET_IRQHandler /* 44: Ethernet */ - .long MCI_IRQHandler /* 45: SD/MMC Card */ - .long MCPWM_IRQHandler /* 46: Motor Control PWM */ - .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ - .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ - .long USBActivity_IRQHandler /* 49: USB Activity */ - .long CANActivity_IRQHandler /* 50: CAN Activity */ - .long UART4_IRQHandler /* 51: UART4 */ - .long SSP2_IRQHandler /* 52: SSP2 */ - .long LCD_IRQHandler /* 53: LCD */ - .long GPIO_IRQHandler /* 54: GPIO */ - .long PWM0_IRQHandler /* 55: PWM0 */ - .long EEPROM_IRQHandler /* 56: EEPROM */ - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - - .thumb - - .section ".crp" - .globl CRP_Value -CRP_Value: - .long 0xFFFFFFFF - -/* Reset Handler */ - - .section .cs3.reset,"x",%progbits - .thumb_func - .globl __cs3_reset_cortex_m - .type __cs3_reset_cortex_m, %function -__cs3_reset_cortex_m: - .fnstart -.if (RAM_MODE) -/* Clear .bss section (Zero init) */ - MOV R0, #0 - LDR R1, =__bss_start__ - LDR R2, =__bss_end__ - CMP R1,R2 - BEQ BSSIsEmpty -LoopZI: - CMP R1, R2 - BHS BSSIsEmpty - STR R0, [R1] - ADD R1, #4 - BLO LoopZI -BSSIsEmpty: - LDR R0, =SystemInit - BLX R0 - LDR R0,=main - BX R0 -.else - LDR R0, =SystemInit - BLX R0 - LDR R0,=_start - BX R0 -.endif - .pool - .cantunwind - .fnend - .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WDT_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ UART0_IRQHandler - IRQ UART1_IRQHandler - IRQ UART2_IRQHandler - IRQ UART3_IRQHandler - IRQ PWM1_IRQHandler - IRQ I2C0_IRQHandler - IRQ I2C1_IRQHandler - IRQ I2C2_IRQHandler -/* IRQ SPIFI_IRQHandler */ - IRQ SSP0_IRQHandler - IRQ SSP1_IRQHandler - IRQ PLL0_IRQHandler - IRQ RTC_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ ADC_IRQHandler - IRQ BOD_IRQHandler - IRQ USB_IRQHandler - IRQ CAN_IRQHandler - IRQ DMA_IRQHandler - IRQ I2S_IRQHandler - IRQ ENET_IRQHandler - IRQ MCI_IRQHandler - IRQ MCPWM_IRQHandler - IRQ QEI_IRQHandler - IRQ PLL1_IRQHandler - IRQ USBActivity_IRQHandler - IRQ CANActivity_IRQHandler - IRQ UART4_IRQHandler - IRQ SSP2_IRQHandler - IRQ LCD_IRQHandler - IRQ GPIO_IRQHandler - IRQ PWM0_IRQHandler - IRQ EEPROM_IRQHandler - - .end diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s deleted file mode 100644 index 7278ca26fa..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s +++ /dev/null @@ -1,281 +0,0 @@ -/*****************************************************************************/ -/* startup_LPC17xx.s: Startup file for LPC17xx device series */ -/*****************************************************************************/ -/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ -/*****************************************************************************/ - - -/* -//*** <<< Use Configuration Wizard in Context Menu >>> *** -*/ - - -/* -// <h> Stack Configuration -// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// </h> -*/ - - .equ Stack_Size, 0x00000100 - .section ".stack", "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - - -/* -// <h> Heap Configuration -// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// </h> -*/ - - .equ Heap_Size, 0x00001000 - - .section ".heap", "w" - .align 3 - .globl __cs3_heap_start - .globl __cs3_heap_end -__cs3_heap_start: - .if Heap_Size - .space Heap_Size - .endif -__cs3_heap_end: - - -/* Vector Table */ - - .section ".cs3.interrupt_vector" - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long __cs3_stack /* Top of Stack */ - .long __cs3_reset /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long WDT_IRQHandler /* 16: Watchdog Timer */ - .long TIMER0_IRQHandler /* 17: Timer0 */ - .long TIMER1_IRQHandler /* 18: Timer1 */ - .long TIMER2_IRQHandler /* 19: Timer2 */ - .long TIMER3_IRQHandler /* 20: Timer3 */ - .long UART0_IRQHandler /* 21: UART0 */ - .long UART1_IRQHandler /* 22: UART1 */ - .long UART2_IRQHandler /* 23: UART2 */ - .long UART3_IRQHandler /* 24: UART3 */ - .long PWM1_IRQHandler /* 25: PWM1 */ - .long I2C0_IRQHandler /* 26: I2C0 */ - .long I2C1_IRQHandler /* 27: I2C1 */ - .long I2C2_IRQHandler /* 28: I2C2 */ - .long 0 /* 29: Reserved, not for SPIFI anymore */ - .long SSP0_IRQHandler /* 30: SSP0 */ - .long SSP1_IRQHandler /* 31: SSP1 */ - .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ - .long RTC_IRQHandler /* 33: Real Time Clock */ - .long EINT0_IRQHandler /* 34: External Interrupt 0 */ - .long EINT1_IRQHandler /* 35: External Interrupt 1 */ - .long EINT2_IRQHandler /* 36: External Interrupt 2 */ - .long EINT3_IRQHandler /* 37: External Interrupt 3 */ - .long ADC_IRQHandler /* 38: A/D Converter */ - .long BOD_IRQHandler /* 39: Brown-Out Detect */ - .long USB_IRQHandler /* 40: USB */ - .long CAN_IRQHandler /* 41: CAN */ - .long DMA_IRQHandler /* 42: General Purpose DMA */ - .long I2S_IRQHandler /* 43: I2S */ - .long ENET_IRQHandler /* 44: Ethernet */ - .long MCI_IRQHandler /* 45: SD/MMC Card */ - .long MCPWM_IRQHandler /* 46: Motor Control PWM */ - .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ - .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ - .long USBActivity_IRQHandler /* 49: USB Activity */ - .long CANActivity_IRQHandler /* 50: CAN Activity */ - .long UART4_IRQHandler /* 51: UART4 */ - .long SSP2_IRQHandler /* 52: SSP2 */ - .long LCD_IRQHandler /* 53: LCD */ - .long GPIO_IRQHandler /* 54: GPIO */ - .long PWM0_IRQHandler /* 55: PWM0 */ - .long EEPROM_IRQHandler /* 56: EEPROM */ - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - - .thumb - - .section ".crp" - .globl CRP_Value -CRP_Value: - .long 0xFFFFFFFF - -/* Reset Handler */ - - .section .cs3.reset,"x",%progbits - .thumb_func - .globl __cs3_reset_cortex_m - .globl Reset_Handler - .type __cs3_reset_cortex_m, %function -__cs3_reset_cortex_m: -Reset_Handler: - .fnstart -.ifdef RAM_MODE -/* Clear .bss section (Zero init) */ - MOV R0, #0 - LDR R1, =__bss_start__ - LDR R2, =__bss_end__ - CMP R1,R2 - BEQ BSSIsEmpty -LoopZI: - CMP R1, R2 - BHS BSSIsEmpty - STR R0, [R1] - ADD R1, #4 - BLO LoopZI -BSSIsEmpty: - LDR R0, =SystemInit - BLX R0 - LDR R0,=main - BX R0 -.else - LDR R0, =SystemInit - BLX R0 - LDR R0,=main - BX R0 -.endif - .pool - .cantunwind - .fnend - .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WDT_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ UART0_IRQHandler - IRQ UART1_IRQHandler - IRQ UART2_IRQHandler - IRQ UART3_IRQHandler - IRQ PWM1_IRQHandler - IRQ I2C0_IRQHandler - IRQ I2C1_IRQHandler - IRQ I2C2_IRQHandler -/* IRQ SPIFI_IRQHandler */ - IRQ SSP0_IRQHandler - IRQ SSP1_IRQHandler - IRQ PLL0_IRQHandler - IRQ RTC_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ ADC_IRQHandler - IRQ BOD_IRQHandler - IRQ USB_IRQHandler - IRQ CAN_IRQHandler - IRQ DMA_IRQHandler - IRQ I2S_IRQHandler - IRQ ENET_IRQHandler - IRQ MCI_IRQHandler - IRQ MCPWM_IRQHandler - IRQ QEI_IRQHandler - IRQ PLL1_IRQHandler - IRQ USBActivity_IRQHandler - IRQ CANActivity_IRQHandler - IRQ UART4_IRQHandler - IRQ SSP2_IRQHandler - IRQ LCD_IRQHandler - IRQ GPIO_IRQHandler - IRQ PWM0_IRQHandler - IRQ EEPROM_IRQHandler - - .end diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC177x_8x.s b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC177x_8x.s deleted file mode 100644 index 55f4be7484..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC177x_8x.s +++ /dev/null @@ -1,396 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC177x_8x.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC17xx Device Series -; * @version: V1.03 -; * @date: 09. February 2010 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: reserved; not for SPIFI anymore - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: MCI Card - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt - DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - - - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - PUBLIC CRP_Value - RSEG CRPKEY : CODE(2) -CRP_Value - DCD 0xFFFFFFFF -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER(1) -WDT_IRQHandler - B WDT_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER(1) -PWM1_IRQHandler - B PWM1_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - ;PUBWEAK SPIFI_IRQHandler - ;SECTION .text:CODE:REORDER(1) -;SPIFI_IRQHandler - ;B SPIFI_IRQHandler - - PUBWEAK SSP0_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP0_IRQHandler - B SSP0_IRQHandler - - PUBWEAK SSP1_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP1_IRQHandler - B SSP1_IRQHandler - - PUBWEAK PLL0_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL0_IRQHandler - B PLL0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK EINT0_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT0_IRQHandler - B EINT0_IRQHandler - - PUBWEAK EINT1_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT1_IRQHandler - B EINT1_IRQHandler - - PUBWEAK EINT2_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT2_IRQHandler - B EINT2_IRQHandler - - PUBWEAK EINT3_IRQHandler - SECTION .text:CODE:REORDER(1) -EINT3_IRQHandler - B EINT3_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK BOD_IRQHandler - SECTION .text:CODE:REORDER(1) -BOD_IRQHandler - B BOD_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK CAN_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN_IRQHandler - B CAN_IRQHandler - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER(1) -I2S_IRQHandler - B I2S_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK MCI_IRQHandler - SECTION .text:CODE:REORDER(1) -MCI_IRQHandler - B MCI_IRQHandler - - PUBWEAK MCPWM_IRQHandler - SECTION .text:CODE:REORDER(1) -MCPWM_IRQHandler - B MCPWM_IRQHandler - - PUBWEAK QEI_IRQHandler - SECTION .text:CODE:REORDER(1) -QEI_IRQHandler - B QEI_IRQHandler - - PUBWEAK PLL1_IRQHandler - SECTION .text:CODE:REORDER(1) -PLL1_IRQHandler - B PLL1_IRQHandler - - PUBWEAK USBActivity_IRQHandler - SECTION .text:CODE:REORDER(1) -USBActivity_IRQHandler - B USBActivity_IRQHandler - - PUBWEAK CANActivity_IRQHandler - SECTION .text:CODE:REORDER(1) -CANActivity_IRQHandler - B CANActivity_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK SSP2_IRQHandler - SECTION .text:CODE:REORDER(1) -SSP2_IRQHandler - B SSP2_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK GPIO_IRQHandler - SECTION .text:CODE:REORDER(1) -GPIO_IRQHandler - B GPIO_IRQHandler - - PUBWEAK PWM0_IRQHandler - SECTION .text:CODE:REORDER(1) -PWM0_IRQHandler - B PWM0_IRQHandler - - PUBWEAK EEPROM_IRQHandler - SECTION .text:CODE:REORDER(1) -EEPROM_IRQHandler - B EEPROM_IRQHandler - - END diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s deleted file mode 100644 index 81a4008c85..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s +++ /dev/null @@ -1,419 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC407x_8x.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the NXP LPC40xx Device Series -; * @version: V1.00 -; * @date: September 2012 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD 0 ; 29: Reserved - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD MCI_IRQHandler ; 45: MCI Card - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt - DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt - DCD UART4_IRQHandler ; 51: UART4 - DCD SSP2_IRQHandler ; 52: SSP2 - DCD LCD_IRQHandler ; 53: LCD - DCD GPIO_IRQHandler ; 54: GPIO - DCD PWM0_IRQHandler ; 55: PWM0 - DCD EEPROM_IRQHandler ; 56: EEPROM - - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT_IRQHandler - B WDT_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_IRQHandler - B PWM1_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_IRQHandler - B I2C2_IRQHandler - -; PUBWEAK SPIFI_IRQHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;SPIFI_IRQHandler -; B SPIFI_IRQHandler - - PUBWEAK SSP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_IRQHandler - B SSP0_IRQHandler - - PUBWEAK SSP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_IRQHandler - B SSP1_IRQHandler - - PUBWEAK PLL0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PLL0_IRQHandler - B PLL0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK EINT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT0_IRQHandler - B EINT0_IRQHandler - - PUBWEAK EINT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT1_IRQHandler - B EINT1_IRQHandler - - PUBWEAK EINT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT2_IRQHandler - B EINT2_IRQHandler - - PUBWEAK EINT3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EINT3_IRQHandler - B EINT3_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK BOD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BOD_IRQHandler - B BOD_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK CAN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN_IRQHandler - B CAN_IRQHandler - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2S_IRQHandler - B I2S_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK MCI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MCI_IRQHandler - B MCI_IRQHandler - - PUBWEAK MCPWM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MCPWM_IRQHandler - B MCPWM_IRQHandler - - PUBWEAK QEI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QEI_IRQHandler - B QEI_IRQHandler - - PUBWEAK PLL1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PLL1_IRQHandler - B PLL1_IRQHandler - - PUBWEAK USBActivity_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USBActivity_IRQHandler - B USBActivity_IRQHandler - - PUBWEAK CANActivity_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CANActivity_IRQHandler - B CANActivity_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK SSP2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP2_IRQHandler - B SSP2_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK GPIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_IRQHandler - B GPIO_IRQHandler - - PUBWEAK PWM0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_IRQHandler - B PWM0_IRQHandler - - PUBWEAK EEPROM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EEPROM_IRQHandler - B EEPROM_IRQHandler - -#ifndef SRAM - SECTION .crp:CODE:ROOT(2) - DATA - -/* Code Read Protection -CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200. - - Read Memory command: disabled. - - Copy RAM to Flash command: cannot write to Sector 0. - - "Go" command: disabled. - - Erase sector(s) command: can erase any individual sector except - sector 0 only, or can erase all sectors at once. - - Compare command: disabled -CRP2 0x87654321 - Write to RAM command: disabled. - - Copy RAM to Flash: disabled. - - Erase command: only allows erase of all sectors. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - -#ifndef CRP - #define CRP 0xFFFFFFFF -#endif - - DCD CRP -#endif - END diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC177x_8x.c b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC177x_8x.c deleted file mode 100644 index ee222aee7e..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC177x_8x.c +++ /dev/null @@ -1,507 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC177x_8x.c 2011-06-02 -*//** -* @file system_LPC177x_8x.c -* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File -* for the NXP LPC177x_8x Device Series -* -* ARM Limited (ARM) is supplying this software for use with -* Cortex-M processor based microcontrollers. This file can be -* freely distributed within development tools that are supporting -* such ARM based processors. -* -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -#include <stdint.h> -#include "LPC177x_8x.h" -#include "system_LPC177x_8x.h" - -#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y)) - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ -/*--------------------- Clock Configuration ---------------------------------- -// -// <e> Clock Configuration -// <h> System Controls and Status Register (SCS - address 0x400F C1A0) -// <o1.0> EMC Shift Control Bit -// <i> Controls how addresses are output on the EMC address pins for static memories -// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0) -// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1) -// -// <o1.1> EMC Reset Disable Bit -// <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition -// <i> If 1, EMC is still retained its state through a warm reset -// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0) -// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1) -// -// <o1.2> EMC Burst Control -// <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects -// <0=> Burst enabled (Bit 2 is 0) -// <1=> Bust disbled (Bit 2 is 1) -// -// <o1.3> MCIPWR Active Level -// <i> Selects the active level for the SD card interface signal SD_PWR -// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0) -// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1) -// -// <o1.4> Main Oscillator Range Select -// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0) -// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1) -// -// <o1.5> Main Oscillator enable -// <i> 0 (zero) means disabled, 1 means enable -// -// <o1.6> Main Oscillator status (Read-Only) -// </h> -// -// <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C) -// <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock -// <0=> Internal RC oscillator (Bit 0 is 0) -// <1=> Main oscillator (Bit 0 is 1) -// </h> -// -// <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084) -// <i> F_in is in the range of 1 MHz to 25 MHz -// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// <o4.0..4> MSEL: PLL Multiplier Value -// <i> M Value -// <1-32><#-1> -// -// <o4.5..6> PSEL: PLL Divider Value -// <i> P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// </e> -// -// <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4) -// <i> F_in is in the range of 1 MHz to 25 MHz -// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// <o6.0..4> MSEL: PLL Multiplier Value -// <i> M Value -// <1-32><#-1> -// -// <o6.5..6> PSEL: PLL Divider Value -// <i> P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// </e> -// -// <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104) -// <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK) -// <i> 0: The divider is turned off. No clock will be provided to the CPU -// <i> n: The input clock is divided by n to produce the CPU clock -// <0-31> -// -// <o7.8> CCLKSEL: Select the input to the divider of CPU clock -// <0=> sysclk clock is used -// <1=> Main PLL0 clock is used -// </h> -// -// <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108) -// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection -// <0=> Divider is off and no clock provides to USB subsystem -// <4=> Divider value is 4 (The source clock is divided by 4) -// <6=> Divider value is 6 (The source clock is divided by 6) -// -// <o8.8..9> USBSEL: Select the source for USB clock divider -// <i> When CPU clock is selected, the USB can be accessed -// <i> by software but cannot perform USB functions -// <0=> sysclk clock (the clock input to PLL0) -// <1=> The clock output from PLL0 -// <2=> The clock output from PLL1 -// </h> -// -// <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100) -// <o9.0> EMCDIV: Set the divider for EMC clock -// <0=> Divider value is 1 -// <1=> Divider value is 2 (EMC clock is equal a half of input clock) -// </h> -// -// <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8) -// <o10.0..4> PCLKDIV: APB Peripheral clock divider -// <i> 0: The divider is turned off. No clock will be provided to APB peripherals -// <i> n: The input clock is divided by n to produce the APB peripheral clock -// <0-31> -// </h> -// -// <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8) -// <o11.0> PCLCD: LCD controller power/clock enable (bit 0) -// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1) -// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2) -// <o11.3> PCUART0: UART 0 power/clock enable (bit 3) -// <o11.4> PCUART1: UART 1 power/clock enable (bit 4) -// <o11.5> PCPWM0: PWM0 power/clock enable (bit 5) -// <o11.6> PCPWM1: PWM1 power/clock enable (bit 6) -// <o11.7> PCI2C0: I2C 0 interface power/clock enable (bit 7) -// <o11.8> PCUART4: UART 4 power/clock enable (bit 8) -// <o11.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9) -// <o11.10> PCSSP1: SSP 1 interface power/clock enable (bit 10) -// <o11.11> PCEMC: External Memory Controller power/clock enable (bit 11) -// <o11.12> PCADC: A/D converter power/clock enable (bit 12) -// <o11.13> PCCAN1: CAN controller 1 power/clock enable (bit 13) -// <o11.14> PCCAN2: CAN controller 2 power/clock enable (bit 14) -// <o11.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15) -// <o11.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17) -// <o11.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18) -// <o11.19> PCI2C1: I2C 1 interface power/clock enable (bit 19) -// <o11.20> PCSSP2: SSP 2 interface power/clock enable (bit 20) -// <o11.21> PCSSP0: SSP 0 interface power/clock enable (bit 21) -// <o11.22> PCTIM2: Timer 2 power/clock enable (bit 22) -// <o11.23> PCTIM3: Timer 3 power/clock enable (bit 23) -// <o11.24> PCUART2: UART 2 power/clock enable (bit 24) -// <o11.25> PCUART3: UART 3 power/clock enable (bit 25) -// <o11.26> PCI2C2: I2C 2 interface power/clock enable (bit 26) -// <o11.27> PCI2S: I2S interface power/clock enable (bit 27) -// <o11.28> PCSDC: SD Card interface power/clock enable (bit 28) -// <o11.29> PCGPDMA: GPDMA function power/clock enable (bit 29) -// <o11.30> PCENET: Ethernet block power/clock enable (bit 30) -// <o11.31> PCUSB: USB interface power/clock enable (bit 31) -// </h> -// -// <h> Clock Output Configuration Register (CLKOUTCFG) -// <o12.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection -// <0=> CPU clock -// <1=> Main Oscillator -// <2=> Internal RC Oscillator -// <3=> USB clock -// <4=> RTC Oscillator -// <5=> unused -// <6=> Watchdog Oscillator -// -// <o12.4..7> CLKOUTDIV: Output Clock Divider -// <1-16><#-1> -// -// <o12.8> CLKOUT_EN: CLKOUT enable -// </h> -// -// </e> -*/ - -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000021 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00000009 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKSEL_Val 0x00000101 -#define USBCLKSEL_Val 0x00000201 -#define EMCCLKSEL_Val 0x00000001 -#define PCLKSEL_Val 0x00000002 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000100 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) -// <o1.12..15> FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// </e> -*/ - -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00005000 - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x0000003F)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F)) - #error "CCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F)) - #error "USBCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001)) - #error "EMCCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F)) - #error "PCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #warning "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ -/* pll_out_clk = F_cco / (2 � P) - F_cco = pll_in_clk � M � 2 � P */ -#define __M ((PLL0CFG_Val & 0x1F) + 1) -#define __PLL0_CLK(__F_IN) (__F_IN * __M) -#define __CCLK_DIV (CCLKSEL_Val & 0x1F) -#define __PCLK_DIV (PCLKSEL_Val & 0x1F) -#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1) - -/* Determine core clock frequency according to settings */ -#if (CLOCK_SETUP) /* Clock Setup */ - - #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0) - #error "Main Oscillator is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0) - #error "Main PLL is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #define __PER_CLK (IRC_OSC/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #define __PER_CLK (OSC_CLK/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #endif - #else /* cclk = pll_clk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #endif - #endif - -#else - #define __CORE_CLK (IRC_OSC) - #define __PER_CLK (IRC_OSC) - #define __EMC_CLK (__CORE_CLK) -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ -uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */ -uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */ -uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will - be updated after call SystemCoreClockUpdate, should be 48MHz*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */ - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - } - } - else { /* cclk = pll_clk */ - if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */ - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div); - PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div); - PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - } - } - } - /* ---update USBClock------------------*/ - if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider - { - switch (LPC_SC->USBCLKSEL & 0x1F) - { - case 0: - USBClock = 0; //no clock will be provided to the USB subsystem - break; - case 4: - case 6: - { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F); - if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc - USBClock = OSC_CLK * mul / usb_div; - else //pll_clk_in = irc_clk - USBClock = IRC_OSC * mul / usb_div; - } - break; - default: - USBClock = 0; /* this should never happen! */ - } - } - else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1) - { - if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc - USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1)); - else //pll1_clk_in = irc_clk - USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1)); - } - else - USBClock = 0; /* this should never happen! */ -} - - /* Determine clock frequency according to clock register values */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/ - -#if (PLL0_SETUP) - LPC_SC->PLL0CFG = PLL0CFG_Val; - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ -#endif - - LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */ - LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */ - LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */ - LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */ - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - - LPC_SC->PBOOST |= 0x03; /* Power Boost control */ - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; -#endif -#ifdef __RAM_MODE__ - SCB->VTOR = 0x10000000 & 0x3FFFFF80; -#else - SCB->VTOR = 0x00000000 & 0x3FFFFF80; -#endif - SystemCoreClockUpdate(); -} diff --git a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c b/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c deleted file mode 100644 index b716d06f62..0000000000 --- a/bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c +++ /dev/null @@ -1,571 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16 -*//** -* @file system_LPC407x_8x_177x_8x.c -* @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File -* for the NXP LPC407x_8x_177x_8x Device Series -* -* ARM Limited (ARM) is supplying this software for use with -* Cortex-M processor based microcontrollers. This file can be -* freely distributed within development tools that are supporting -* such ARM based processors. -* -* @version 1.2 -* @date 20. June. 2012 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2012, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#include <stdint.h> -#include "LPC407x_8x_177x_8x.h" -#include "system_LPC407x_8x_177x_8x.h" - -#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y)) - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ -/*--------------------- Clock Configuration ---------------------------------- -// -// <e> Clock Configuration -// <h> System Controls and Status Register (SCS - address 0x400F C1A0) -// <o1.0> EMC Shift Control Bit -// <i> Controls how addresses are output on the EMC address pins for static memories -// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0) -// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1) -// -// <o1.1> EMC Reset Disable Bit -// <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition -// <i> If 1, EMC is still retained its state through a warm reset -// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0) -// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1) -// -// <o1.2> EMC Burst Control -// <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects -// <0=> Burst enabled (Bit 2 is 0) -// <1=> Bust disbled (Bit 2 is 1) -// -// <o1.3> MCIPWR Active Level -// <i> Selects the active level for the SD card interface signal SD_PWR -// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0) -// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1) -// -// <o1.4> Main Oscillator Range Select -// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0) -// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1) -// -// <o1.5> Main Oscillator enable -// <i> 0 (zero) means disabled, 1 means enable -// -// <o1.6> Main Oscillator status (Read-Only) -// </h> -// -// <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C) -// <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock -// <0=> Internal RC oscillator (Bit 0 is 0) -// <1=> Main oscillator (Bit 0 is 1) -// </h> -// -// <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084) -// <i> F_in is in the range of 1 MHz to 25 MHz -// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// <o4.0..4> MSEL: PLL Multiplier Value -// <i> M Value -// <1-32><#-1> -// -// <o4.5..6> PSEL: PLL Divider Value -// <i> P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// </e> -// -// <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4) -// <i> F_in is in the range of 1 MHz to 25 MHz -// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz -// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz -// -// <o6.0..4> MSEL: PLL Multiplier Value -// <i> M Value -// <1-32><#-1> -// -// <o6.5..6> PSEL: PLL Divider Value -// <i> P Value -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// </e> -// -// <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104) -// <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK) -// <i> 0: The divider is turned off. No clock will be provided to the CPU -// <i> n: The input clock is divided by n to produce the CPU clock -// <0-31> -// -// <o7.8> CCLKSEL: Select the input to the divider of CPU clock -// <0=> sysclk clock is used -// <1=> Main PLL0 clock is used -// </h> -// -// <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108) -// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection -// <0=> Divider is off and no clock provides to USB subsystem -// <4=> Divider value is 4 (The source clock is divided by 4) -// <6=> Divider value is 6 (The source clock is divided by 6) -// -// <o8.8..9> USBSEL: Select the source for USB clock divider -// <i> When CPU clock is selected, the USB can be accessed -// <i> by software but cannot perform USB functions -// <0=> sysclk clock (the clock input to PLL0) -// <1=> The clock output from PLL0 -// <2=> The clock output from PLL1 -// </h> -// -// <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100) -// <o9.0> EMCDIV: Set the divider for EMC clock -// <0=> Divider value is 1 -// <1=> Divider value is 2 (EMC clock is equal a half of input clock) -// </h> -// -// <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8) -// <o10.0..4> PCLKDIV: APB Peripheral clock divider -// <i> 0: The divider is turned off. No clock will be provided to APB peripherals -// <i> n: The input clock is divided by n to produce the APB peripheral clock -// <0-31> -// </h> -// -// <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4) -// <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock -// <i> 0: The divider is turned off. No clock will be provided to the SPIFI -// <i> n: The input clock is divided by n to produce the SPIFI clock -// <0-31> -// -// <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider -// <0=> sysclk clock (the clock input to PLL0) -// <1=> The clock output from PLL0 -// <2=> The clock output from PLL1 -// </h> -// -// <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8) -// <o12.0> PCLCD: LCD controller power/clock enable (bit 0) -// <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1) -// <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2) -// <o12.3> PCUART0: UART 0 power/clock enable (bit 3) -// <o12.4> PCUART1: UART 1 power/clock enable (bit 4) -// <o12.5> PCPWM0: PWM0 power/clock enable (bit 5) -// <o12.6> PCPWM1: PWM1 power/clock enable (bit 6) -// <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7) -// <o12.8> PCUART4: UART 4 power/clock enable (bit 8) -// <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9) -// <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10) -// <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11) -// <o12.12> PCADC: A/D converter power/clock enable (bit 12) -// <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13) -// <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14) -// <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15) -// <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17) -// <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18) -// <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19) -// <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20) -// <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21) -// <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22) -// <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23) -// <o12.24> PCUART2: UART 2 power/clock enable (bit 24) -// <o12.25> PCUART3: UART 3 power/clock enable (bit 25) -// <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26) -// <o12.27> PCI2S: I2S interface power/clock enable (bit 27) -// <o12.28> PCSDC: SD Card interface power/clock enable (bit 28) -// <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29) -// <o12.30> PCENET: Ethernet block power/clock enable (bit 30) -// <o12.31> PCUSB: USB interface power/clock enable (bit 31) -// </h> -// -// <h> Clock Output Configuration Register (CLKOUTCFG) -// <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection -// <0=> CPU clock -// <1=> Main Oscillator -// <2=> Internal RC Oscillator -// <3=> USB clock -// <4=> RTC Oscillator -// <5=> unused -// <6=> Watchdog Oscillator -// -// <o13.4..7> CLKOUTDIV: Output Clock Divider -// <1-16><#-1> -// -// <o13.8> CLKOUT_EN: CLKOUT enable -// </h> -// -// </e> -*/ - -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000020 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00000009 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKSEL_Val 0x00000101 -#define USBCLKSEL_Val 0x00000201 -#define EMCCLKSEL_Val 0x00000000 -#define PCLKSEL_Val 0x00000002 -#define SPIFICLKSEL_Val 0x00000002 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000100 - -#ifdef CORE_M4 -#define LPC_CPACR 0xE000ED88 - -#define SCB_MVFR0 0xE000EF40 -#define SCB_MVFR0_RESET 0x10110021 - -#define SCB_MVFR1 0xE000EF44 -#define SCB_MVFR1_RESET 0x11000011 -#endif - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) -// <o1.12..15> FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// </e> -*/ - -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00005000 - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x0000003F)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F)) - #error "CCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F)) - #error "USBCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001)) - #error "EMCCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F)) - #error "PCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ -/* pll_out_clk = F_cco / (2 ?P) - F_cco = pll_in_clk ?M ?2 ?P */ -#define __M ((PLL0CFG_Val & 0x1F) + 1) -#define __PLL0_CLK(__F_IN) (__F_IN * __M) -#define __CCLK_DIV (CCLKSEL_Val & 0x1F) -#define __PCLK_DIV (PCLKSEL_Val & 0x1F) -#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1) - -/* Determine core clock frequency according to settings */ -#if (CLOCK_SETUP) /* Clock Setup */ - - #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0) - #error "Main Oscillator is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0) - #error "Main PLL is selected as clock source but is not enabled!" - #endif - - #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #define __PER_CLK (IRC_OSC/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #define __PER_CLK (OSC_CLK/ __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) - #endif - #else /* cclk = pll_clk */ - #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ - #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #else /* sysclk = osc_clk */ - #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV) - #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV) - #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) - #endif - #endif - -#else - #define __CORE_CLK (IRC_OSC) - #define __PER_CLK (IRC_OSC) - #define __EMC_CLK (__CORE_CLK) -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ -uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */ -uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */ -uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will - be updated after call SystemCoreClockUpdate, should be 48MHz*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */ - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F)); - PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F)); - EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); - } - } - } - else { /* cclk = pll_clk */ - if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */ - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div); - PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - else { /* sysclk = osc_clk */ - if ((LPC_SC->SCS & 0x40) == 0) { - SystemCoreClock = 0; /* this should never happen! */ - PeripheralClock = 0; - EMCClock = 0; - } - else { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); - uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); - uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; - SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div); - PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div); - EMCClock = SystemCoreClock / emc_div; - } - } - } - } - /* ---update USBClock------------------*/ - if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider - { - switch (LPC_SC->USBCLKSEL & 0x1F) - { - case 0: - USBClock = 0; //no clock will be provided to the USB subsystem - break; - case 4: - case 6: - { - uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); - uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F); - if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc - USBClock = OSC_CLK * mul / usb_div; - else //pll_clk_in = irc_clk - USBClock = IRC_OSC * mul / usb_div; - } - break; - default: - USBClock = 0; /* this should never happen! */ - } - } - else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1) - { - if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc - USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1)); - else //pll1_clk_in = irc_clk - USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1)); - } - else - USBClock = 0; /* this should never happen! */ -} - - /* Determine clock frequency according to clock register values */ - -#ifdef CORE_M4 - -void fpu_init(void) -{ - // from arm trm manual: -// ; CPACR is located at address 0xE000ED88 -// LDR.W R0, =0xE000ED88 -// ; Read CPACR -// LDR R1, [R0] -// ; Set bits 20-23 to enable CP10 and CP11 coprocessors -// ORR R1, R1, #(0xF << 20) -// ; Write back the modified value to the CPACR -// STR R1, [R0] - - - volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR; - volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0; - volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1; - volatile uint32_t Cpacr; - volatile uint32_t Mvfr0; - volatile uint32_t Mvfr1; - char vfpPresent = 0; - - Mvfr0 = *regMvfr0; - Mvfr1 = *regMvfr1; - - vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); - - if(vfpPresent) - { - Cpacr = *regCpacr; - Cpacr |= (0xF << 20); - *regCpacr = Cpacr; // enable CP10 and CP11 for full access - } - -} -#endif - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#ifndef __CODE_RED -#ifdef CORE_M4 -fpu_init(); -#endif -#endif - -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/ - -#if (PLL0_SETUP) - LPC_SC->PLL0CFG = PLL0CFG_Val; - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ -#endif - - LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */ - LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */ - LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */ - LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */ - LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */ - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - - LPC_SC->PBOOST |= 0x03; /* Power Boost control */ - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; -#endif -#ifndef __CODE_RED -#ifdef __RAM_MODE__ - SCB->VTOR = 0x10000000 & 0x3FFFFF80; -#else - SCB->VTOR = 0x00000000 & 0x3FFFFF80; -#endif -#endif - SystemCoreClockUpdate(); -} diff --git a/bsp/lpc408x/Libraries/Device/SConscript b/bsp/lpc408x/Libraries/Device/SConscript deleted file mode 100644 index bb09284c42..0000000000 --- a/bsp/lpc408x/Libraries/Device/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Split(''' -NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c -''') -CPPPATH = [cwd + '/NXP/LPC407x_8x_177x_8x/Include', cwd + '/../CMSIS/Include'] -CPPDEFINES = ['CORE_M4'] - -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -Return('group') |