diff options
| author | Meco Man <[email protected]> | 2022-03-28 20:06:03 -0400 |
|---|---|---|
| committer | Meco Man <[email protected]> | 2022-03-28 20:06:03 -0400 |
| commit | 8003788ad51ff044ba2673cf58a1e214891bd4ee (patch) | |
| tree | 7cec2c812ca2d40e00e15b1893a9ffe078c4877d /bsp/ls1bdev/drivers/display_controller.h | |
| parent | 82a2fb169e3493440d66783e5d2f552b810479b9 (diff) | |
将龙芯bsp并入loongson文件夹中
Diffstat (limited to 'bsp/ls1bdev/drivers/display_controller.h')
| -rw-r--r-- | bsp/ls1bdev/drivers/display_controller.h | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/bsp/ls1bdev/drivers/display_controller.h b/bsp/ls1bdev/drivers/display_controller.h deleted file mode 100644 index 1fa6243a72..0000000000 --- a/bsp/ls1bdev/drivers/display_controller.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-08-08 lgnq first version for LS1B - */ - -#ifndef __DISPLAY_CONTROLLER_H__ -#define __DISPLAY_CONTROLLER_H__ - -#include <rtthread.h> -#include "ls1b.h" - -#define DC_BASE 0xBC301240 //Display Controller - -/* Frame Buffer registers */ -#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) -#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) -#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) -#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) -#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) -#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) -#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) -#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) -#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) -#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) -#define DC_HSYNC __REG32(DC_BASE + 0x1E0) -#define DC_VDISPLAY __REG32(DC_BASE + 0x240) -#define DC_VSYNC __REG32(DC_BASE + 0x260) -#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) - -/* Display Controller driver for 1024x768 16bit */ -#define FB_XSIZE 1024 -#define FB_YSIZE 768 -#define CONFIG_VIDEO_16BPP - -#define APB_CLK 33333333 - -#define K1BASE 0xA0000000 -#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) -#define HW_FB_ADDR KSEG1(_rt_framebuffer) -#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2) - -struct vga_struct -{ - long pclk; - int hr,hss,hse,hfl; - int vr,vss,vse,vfl; -}; - -#endif |