将龙芯bsp并入loongson文件夹中

7 files changed, 0 insertions, 726 deletions

diff --git a/bsp/ls1bdev/drivers/SConscript b/bsp/ls1bdev/drivers/SConscript
deleted file mode 100644
index 5e1060d78e..0000000000
--- a/bsp/ls1bdev/drivers/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-from building import *
-
-cwd = GetCurrentDir()
-src = Glob('*.c')
-
-# remove no need file.
-if GetDepend('RT_USING_RTGUI') == False:
-    SrcRemove(src, 'display_controller.c')
-
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/ls1bdev/drivers/board.c b/bsp/ls1bdev/drivers/board.c
deleted file mode 100644
index 933c54a172..0000000000
--- a/bsp/ls1bdev/drivers/board.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- * 2011-08-08     lgnq         modified for Loongson LS1B
- * 2019-12-04     Jiaxun Yang  Adapt new MIPS generic code
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <mips_fpu.h>
-
-#include "board.h"
-#include "drv_uart.h"
-#include "ls1b.h"
-
-#ifdef RT_USING_RTGUI
-#include <rtgui/rtgui.h>
-rt_device_t dc;
-extern void rt_hw_dc_init(void);
-#endif
-
-extern unsigned char __bss_end;
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init(void)
-{
-    /* init hardware interrupt */
-    rt_hw_exception_init();
-
-    /* init hardware interrupt */
-    rt_hw_interrupt_init();
-
-#ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
-#endif
-
-#ifdef RT_USING_SERIAL
-    /* init hardware UART device */
-    rt_hw_uart_init();
-#endif
-
-#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
-    /* set console device */
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-    /* init operating system timer */
-    rt_hw_timer_init();
-
-#ifdef RT_USING_FPU
-    /* init hardware fpu */
-    rt_hw_fpu_init();
-#endif
-
-#ifdef RT_USING_RTGUI
-    rt_device_t dc;
-
-    /* init Display Controller */
-    rt_hw_dc_init();
-
-    /* find Display Controller device */
-    dc = rt_device_find("dc");
-
-    /* set Display Controller device as rtgui graphic driver */
-    rtgui_graphic_set_device(dc);
-#endif
-
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-    rt_kprintf("current sr: 0x%08x\n", read_c0_status());
-}
-/*@}*/
diff --git a/bsp/ls1bdev/drivers/board.h b/bsp/ls1bdev/drivers/board.h
deleted file mode 100644
index 7d7002892c..0000000000
--- a/bsp/ls1bdev/drivers/board.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- * 2011-08-08     lgnq         modified for Loongson LS1B
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-void rt_hw_board_init(void);
-
-/* 64M SDRAM */
-#define RT_HW_HEAP_END  (0x80000000 + RT_MEM_SIZE * 1024 * 1024)
-#define CPU_HZ          (125 * 1000000)
-
-#endif
diff --git a/bsp/ls1bdev/drivers/display_controller.c b/bsp/ls1bdev/drivers/display_controller.c
deleted file mode 100644
index 5dba114b69..0000000000
--- a/bsp/ls1bdev/drivers/display_controller.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-08-09     lgnq         first version for LS1B DC
- */
-
-#include <rtthread.h>
-#include "display_controller.h"
-
-struct vga_struct vga_mode[] =
-{
-    {/*"640x480_70.00"*/    28560,  640,    664,    728,    816,    480,    481,    484,    500,    },
-    {/*"640x640_60.00"*/    33100,  640,    672,    736,    832,    640,    641,    644,    663,    },
-    {/*"640x768_60.00"*/    39690,  640,    672,    736,    832,    768,    769,    772,    795,    },
-    {/*"640x800_60.00"*/    42130,  640,    680,    744,    848,    800,    801,    804,    828,    },
-    {/*"800x480_70.00"*/    35840,  800,    832,    912,    1024,   480,    481,    484,    500,    },
-    {/*"800x600_60.00"*/    38220,  800,    832,    912,    1024,   600,    601,    604,    622,    },
-    {/*"800x640_60.00"*/    40730,  800,    832,    912,    1024,   640,    641,    644,    663,    },
-    {/*"832x600_60.00"*/    40010,  832,    864,    952,    1072,   600,    601,    604,    622,    },
-    {/*"832x608_60.00"*/    40520,  832,    864,    952,    1072,   608,    609,    612,    630,    },
-    {/*"1024x480_60.00"*/   38170,  1024,   1048,   1152,   1280,   480,    481,    484,    497,    },
-    {/*"1024x600_60.00"*/   48960,  1024,   1064,   1168,   1312,   600,    601,    604,    622,    },
-    {/*"1024x640_60.00"*/   52830,  1024,   1072,   1176,   1328,   640,    641,    644,    663,    },
-    {/*"1024x768_60.00"*/   64110,  1024,   1080,   1184,   1344,   768,    769,    772,    795,    },
-    {/*"1152x764_60.00"*/   71380,  1152,   1208,   1328,   1504,   764,    765,    768,    791,    },
-    {/*"1280x800_60.00"*/   83460,  1280,   1344,   1480,   1680,   800,    801,    804,    828,    },
-    {/*"1280x1024_55.00"*/  98600,  1280,   1352,   1488,   1696,   1024,   1025,   1028,   1057,   },
-    {/*"1440x800_60.00"*/   93800,  1440,   1512,   1664,   1888,   800,    801,    804,    828,    },
-    {/*"1440x900_67.00"*/   120280, 1440,   1528,   1680,   1920,   900,    901,    904,    935,    },
-};
-
-ALIGN(16)
-volatile rt_uint16_t _rt_framebuffer[FB_YSIZE][FB_XSIZE];
-static struct rt_device_graphic_info _dc_info;
-
-#define abs(x) ((x<0)?(-x):x)
-#define min(a,b) ((a<b)?a:b)
-
-int caclulate_freq(long long XIN, long long PCLK)
-{
-    int i;
-    long long clk, clk1;
-    int start, end;
-    int mi;
-    int pll,ctrl,div,div1,frac;
-
-    pll = PLL_FREQ;
-    ctrl = PLL_DIV_PARAM;
-    rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
-//  rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
-    start = -1;
-    end = 1;
-
-    for (i=start; i<=end; i++)
-    {
-        clk = (12+i+(pll&0x3f))*33333333/2;
-        div = clk/(long)PCLK/1000;
-        clk1 = (12+i+1+(pll&0x3f))*33333333/2;
-        div1 = clk1/(long)PCLK/1000;
-        if (div!=div1)
-            break;
-    }
-
-    if (div!=div1)
-    {
-        frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
-        pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
-        ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
-    }
-    else
-    {
-        clk = (12+start+(pll&0x3f))*33333333/2;
-        clk1 = (12+end+(pll&0x3f))*33333333/2;
-        if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
-        {
-            pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
-            ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
-        }
-        else
-        {
-            pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
-            ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
-        }
-    }
-
-    rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
-    ctrl |= 0x2a00;
-    PLL_DIV_PARAM = ctrl;
-    PLL_FREQ = pll;
-    rt_thread_delay(10);
-//  initserial(0);
-//  _probe_frequencies();
-//  rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
-    return 0;
-}
-
-static rt_err_t rt_dc_init(rt_device_t dev)
-{
-    int i, out, mode=-1;
-    int val;
-
-    for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
-    {
-        if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
-        {
-            mode=i;
-#ifdef LS1FSOC
-//          out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
-//          rt_kprintf("out=%x\n",out);
-            /*inner gpu dc logic fifo pll ctrl,must large then outclk*/
-//          *(volatile int *)0xbfd00414 = out+1;
-            /*output pix1 clock  pll ctrl*/
-//          *(volatile int *)0xbfd00410 = out;
-            /*output pix2 clock pll ctrl */
-//          *(volatile int *)0xbfd00424 = out;
-#else
-            caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
-#endif
-            break;
-        }
-    }
-
-    if (mode<0)
-    {
-        rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
-        return;
-    }
-
-    DC_FB_CONFIG = 0x0;
-    DC_FB_CONFIG = 0x3; //  // framebuffer configuration RGB565
-    DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
-    DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
-    DC_DITHER_CONFIG = 0x0;
-    DC_DITHER_TABLE_LOW = 0x0;
-    DC_DITHER_TABLE_HIGH = 0x0;
-    DC_PANEL_CONFIG = 0x80001311;
-    DC_PANEL_TIMING = 0x0;
-
-    DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
-    DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
-    DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
-    DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
-
-#if defined(CONFIG_VIDEO_32BPP)
-    DC_FB_CONFIG = 0x00100104;
-    DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
-#elif defined(CONFIG_VIDEO_16BPP)
-    DC_FB_CONFIG = 0x00100103;
-    DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
-#elif defined(CONFIG_VIDEO_15BPP)
-    DC_FB_CONFIG = 0x00100102;
-    DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
-#elif defined(CONFIG_VIDEO_12BPP)
-    DC_FB_CONFIG = 0x00100101;
-    DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
-#else  //640x480-32Bits
-    DC_FB_CONFIG = 0x00100104;
-    DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
-#endif //32Bits
-
-#ifdef LS1GSOC
-    /*fix ls1g dc
-     *first switch to tile mode
-     *change origin register to 0
-     *goback nomal mode
-     */
-    {
-        val = DC_FB_CONFIG;
-        DC_FB_CONFIG = val | 0x10;
-        DC_FB_BUFFER_ORIGIN = 0;
-        DC_FB_BUFFER_ORIGIN;
-        rt_thread_delay(10);
-        DC_FB_CONFIG;
-        DC_FB_CONFIG = val;
-    }
-#endif
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_dc_control(rt_device_t dev, int cmd, void *args)
-{
-    switch (cmd)
-    {
-    case RTGRAPHIC_CTRL_RECT_UPDATE:
-        break;
-    case RTGRAPHIC_CTRL_POWERON:
-        break;
-    case RTGRAPHIC_CTRL_POWEROFF:
-        break;
-    case RTGRAPHIC_CTRL_GET_INFO:
-        rt_memcpy(args, &_dc_info, sizeof(_dc_info));
-        break;
-    case RTGRAPHIC_CTRL_SET_MODE:
-        break;
-    }
-
-    return RT_EOK;
-}
-
-void rt_hw_dc_init(void)
-{
-    rt_device_t dc = rt_malloc(sizeof(struct rt_device));
-    if (dc == RT_NULL)
-    {
-        rt_kprintf("dc == RT_NULL\n");
-        return; /* no memory yet */
-    }
-
-    _dc_info.bits_per_pixel = 16;
-    _dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
-    _dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
-    _dc_info.width = FB_XSIZE;
-    _dc_info.height = FB_YSIZE;
-
-    /* init device structure */
-    dc->type = RT_Device_Class_Graphic;
-    dc->init = rt_dc_init;
-    dc->open = RT_NULL;
-    dc->close = RT_NULL;
-    dc->control = rt_dc_control;
-    dc->user_data = (void*)&_dc_info;
-
-    /* register Display Controller device to RT-Thread */
-    rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
-}
diff --git a/bsp/ls1bdev/drivers/display_controller.h b/bsp/ls1bdev/drivers/display_controller.h
deleted file mode 100644
index 1fa6243a72..0000000000
--- a/bsp/ls1bdev/drivers/display_controller.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-08-08     lgnq         first version for LS1B
- */
-
-#ifndef __DISPLAY_CONTROLLER_H__
-#define __DISPLAY_CONTROLLER_H__
-
-#include <rtthread.h>
-#include "ls1b.h"
-
-#define DC_BASE                 0xBC301240  //Display Controller
-
-/* Frame Buffer registers */
-#define DC_FB_CONFIG            __REG32(DC_BASE + 0x000)
-#define DC_FB_BUFFER_ADDR0      __REG32(DC_BASE + 0x020)
-#define DC_FB_BUFFER_STRIDE     __REG32(DC_BASE + 0x040)
-#define DC_FB_BUFFER_ORIGIN     __REG32(DC_BASE + 0x060)
-#define DC_DITHER_CONFIG        __REG32(DC_BASE + 0x120)
-#define DC_DITHER_TABLE_LOW     __REG32(DC_BASE + 0x140)
-#define DC_DITHER_TABLE_HIGH    __REG32(DC_BASE + 0x160)
-#define DC_PANEL_CONFIG         __REG32(DC_BASE + 0x180)
-#define DC_PANEL_TIMING         __REG32(DC_BASE + 0x1A0)
-#define DC_HDISPLAY             __REG32(DC_BASE + 0x1C0)
-#define DC_HSYNC                __REG32(DC_BASE + 0x1E0)
-#define DC_VDISPLAY             __REG32(DC_BASE + 0x240)
-#define DC_VSYNC                __REG32(DC_BASE + 0x260)
-#define DC_FB_BUFFER_ADDR1      __REG32(DC_BASE + 0x340)
-
-/* Display Controller driver for 1024x768 16bit */
-#define FB_XSIZE        1024
-#define FB_YSIZE        768
-#define CONFIG_VIDEO_16BPP
-
-#define APB_CLK 33333333
-
-#define K1BASE              0xA0000000
-#define KSEG1(addr)         ((void *)(K1BASE | (rt_uint32_t)(addr)))
-#define HW_FB_ADDR          KSEG1(_rt_framebuffer)
-#define HW_FB_PIXEL(x, y)   *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
-
-struct vga_struct
-{
-    long pclk;
-    int hr,hss,hse,hfl;
-    int vr,vss,vse,vfl;
-};
-
-#endif
diff --git a/bsp/ls1bdev/drivers/drv_uart.c b/bsp/ls1bdev/drivers/drv_uart.c
deleted file mode 100644
index 8f469f26ed..0000000000
--- a/bsp/ls1bdev/drivers/drv_uart.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-05-08     zhuangwei    the first version
- * 2021-02-02     [email protected]    adapt to ls1b
- */
-#include <rtthread.h>
-#include <rtdevice.h>
-#include <rthw.h>
-#include "drv_uart.h"
-#include "ls1b_pin.h"
-#include "ls1b_uart.h"
-
-/* STM32 uart driver */
-struct rt_uart_ls1b
-{
-    ls1b_uart_t UARTx;
-    rt_uint32_t IRQ;
-};
-
-static rt_err_t ls1b_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    struct rt_uart_ls1b *uart_dev = RT_NULL;
-    ls1b_uart_info_t uart_info = {0};
-
-    RT_ASSERT(serial != RT_NULL);
-    RT_ASSERT(cfg != RT_NULL);
-
-    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
-
-    // 初始化串口
-    uart_info.UARTx    = uart_dev->UARTx;
-    uart_info.baudrate = cfg->baud_rate;
-    uart_info.rx_enable = TRUE;
-    uart_init(&uart_info);
-
-    return RT_EOK;
-
-}
-
-static rt_err_t ls1b_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct rt_uart_ls1b *uart_dev = RT_NULL;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */
-        rt_hw_interrupt_mask(uart_dev->IRQ);
-        break;
-
-    case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */
-        rt_hw_interrupt_umask(uart_dev->IRQ);
-        break;
-
-    default:
-        break;
-    }
-
-    return RT_EOK;
-
-}
-
-static int ls1b_uart_putc(struct rt_serial_device *serial, char c)
-{
-    struct rt_uart_ls1b *uart_dev = RT_NULL;
-
-    RT_ASSERT(serial != RT_NULL);
-
-    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
-    uart_putc(uart_dev->UARTx, c);
-
-    return 1;
-}
-
-static int ls1b_uart_getc(struct rt_serial_device *serial)
-{
-    struct rt_uart_ls1b *uart_dev = RT_NULL;
-
-    RT_ASSERT(serial != RT_NULL);
-
-    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
-    void *uart_base = uart_get_base(uart_dev->UARTx);
-
-    if (LSR_RXRDY & reg_read_8(uart_base + LS1B_UART_LSR_OFFSET))
-    {
-        return reg_read_8(uart_base + LS1B_UART_DAT_OFFSET);
-    }
-
-    return -1;
-}
-
-/* UART interrupt handler */
-static void uart_irq_handler(int vector, void *param)
-{
-    struct rt_serial_device *serial = (struct rt_serial_device *)param;
-    struct rt_uart_ls1b *uart_dev = RT_NULL;
-
-    RT_ASSERT(serial != RT_NULL);
-
-    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
-    void *uart_base = uart_get_base(uart_dev->UARTx);
-    unsigned char iir = reg_read_8(uart_base + LS1B_UART_IIR_OFFSET);
-
-    // 判断是否为接收超时或接收到有效数据
-    if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
-    {
-        rt_interrupt_enter();
-        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-        rt_interrupt_leave();
-    }
-
-}
-
-static const struct rt_uart_ops ls1b_uart_ops =
-{
-    ls1b_uart_configure,
-    ls1b_uart_control,
-    ls1b_uart_putc,
-    ls1b_uart_getc,
-};
-
-
-#if defined(RT_USING_UART1)
-struct rt_uart_ls1b uart1 =
-{
-    LS1B_UART1,
-    LS1B_UART1_IRQ,
-};
-struct rt_serial_device serial1;
-#endif /* RT_USING_UART1 */
-
-#if defined(RT_USING_UART2)
-struct rt_uart_ls1b uart2 =
-{
-    LS1B_UART2,
-    LS1B_UART2_IRQ,
-};
-struct rt_serial_device serial2;
-#endif /* RT_USING_UART2 */
-
-
-#if defined(RT_USING_UART3)
-struct rt_uart_ls1b uart3 =
-{
-    LS1B_UART3,
-    LS1B_UART3_IRQ,
-};
-struct rt_serial_device serial3;
-#endif /* RT_USING_UART3 */
-
-#if defined(RT_USING_UART4)
-struct rt_uart_ls1b uart4 =
-{
-    LS1B_UART4,
-    LS1B_UART4_IRQ,
-};
-struct rt_serial_device serial4;
-#endif /* RT_USING_UART4 */
-
-#if defined(RT_USING_UART5)
-struct rt_uart_ls1b uart5 =
-{
-    LS1B_UART5,
-    LS1B_UART5_IRQ,
-};
-struct rt_serial_device serial5;
-#endif /* RT_USING_UART5 */
-
-
-
-void rt_hw_uart_init(void)
-{
-    struct rt_uart_ls1b *uart;
-    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
-
-#ifdef RT_USING_UART5
-		uart = &uart5;
-	
-		serial5.ops    = &ls1b_uart_ops;
-		serial5.config = config;
-	
-		rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5");
-	
-		/* register UART5 device */
-		rt_hw_serial_register(&serial5,
-							  "uart5",
-							  //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
-							  RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-							  uart);
-#endif /* RT_USING_UART5 */
-
-
-#ifdef RT_USING_UART2
-    uart = &uart2;
-
-    serial2.ops    = &ls1b_uart_ops;
-    serial2.config = config;
-
-    pin_set_purpose(36, PIN_PURPOSE_OTHER);
-    pin_set_purpose(37, PIN_PURPOSE_OTHER);
-    pin_set_remap(36, PIN_REMAP_SECOND);
-    pin_set_remap(37, PIN_REMAP_SECOND);
-
-    rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial2, "UART2");
-
-    /* register UART2 device */
-    rt_hw_serial_register(&serial2,
-                          "uart2",
-                          //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-#endif /* RT_USING_UART2 */
-
-}
-
diff --git a/bsp/ls1bdev/drivers/drv_uart.h b/bsp/ls1bdev/drivers/drv_uart.h
deleted file mode 100644
index 01dfd9aae0..0000000000
--- a/bsp/ls1bdev/drivers/drv_uart.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-05-08     zhuangwei    the first version
- */
-
-#ifndef __DRV_UART_H__
-#define __DRV_UART_H__
-
-#include "ls1b.h"
-#include <rthw.h>
-
-#define DEV_CLK 252000000 // 252MHz
-#define UART_BAUDRATE 115200
-
-#define UART0_BASE          0xBFE40000
-//#define UART0_1_BASE      0xBFE41000
-#define UART1_BASE          0xBFE44000
-#define UART2_BASE          0xBFE48000
-#define UART3_BASE          0xBFE4C000
-#define UART4_BASE          0xBFE4C400
-#define UART5_BASE          0xBFE4C500
-#define UART6_BASE          0xBFE4C600
-#define UART7_BASE          0xBFE4C700
-#define UART8_BASE          0xBFE4C800
-#define UART9_BASE          0xBFE4C900
-#define UART10_BASE         0xBFE4Ca00
-#define UART11_BASE         0xBFE4Cb00
-
-/* UART registers */
-#define UART_DAT(base)      HWREG8(base + 0x00)
-#define UART_IER(base)      HWREG8(base + 0x01)
-#define UART_IIR(base)      HWREG8(base + 0x02)
-#define UART_FCR(base)      HWREG8(base + 0x02)
-#define UART_LCR(base)      HWREG8(base + 0x03)
-#define UART_MCR(base)      HWREG8(base + 0x04)
-#define UART_LSR(base)      HWREG8(base + 0x05)
-#define UART_MSR(base)      HWREG8(base + 0x06)
-
-#define UART_LSB(base)      HWREG8(base + 0x00)
-#define UART_MSB(base)      HWREG8(base + 0x01)
-
-/* UART0 registers */
-#define UART0_DAT           HWREG8(UART0_BASE + 0x00)
-#define UART0_IER           HWREG8(UART0_BASE + 0x01)
-#define UART0_IIR           HWREG8(UART0_BASE + 0x02)
-#define UART0_FCR           HWREG8(UART0_BASE + 0x02)
-#define UART0_LCR           HWREG8(UART0_BASE + 0x03)
-#define UART0_MCR           HWREG8(UART0_BASE + 0x04)
-#define UART0_LSR           HWREG8(UART0_BASE + 0x05)
-#define UART0_MSR           HWREG8(UART0_BASE + 0x06)
-
-#define UART0_LSB           HWREG8(UART0_BASE + 0x00)
-#define UART0_MSB           HWREG8(UART0_BASE + 0x01)
-
-/* UART1 registers */
-#define UART1_DAT           HWREG8(UART1_BASE + 0x00)
-#define UART1_IER           HWREG8(UART1_BASE + 0x01)
-#define UART1_IIR           HWREG8(UART1_BASE + 0x02)
-#define UART1_FCR           HWREG8(UART1_BASE + 0x02)
-#define UART1_LCR           HWREG8(UART1_BASE + 0x03)
-#define UART1_MCR           HWREG8(UART1_BASE + 0x04)
-#define UART1_LSR           HWREG8(UART1_BASE + 0x05)
-#define UART1_MSR           HWREG8(UART1_BASE + 0x06)
-
-#define UART1_LSB           HWREG8(UART1_BASE + 0x00)
-#define UART1_MSB           HWREG8(UART1_BASE + 0x01)
-
-/* UART interrupt enable register value */
-#define UARTIER_IME     (1 << 3)
-#define UARTIER_ILE     (1 << 2)
-#define UARTIER_ITXE    (1 << 1)
-#define UARTIER_IRXE    (1 << 0)
-
-/* UART line control register value */
-#define UARTLCR_DLAB    (1 << 7)
-#define UARTLCR_BCB     (1 << 6)
-#define UARTLCR_SPB     (1 << 5)
-#define UARTLCR_EPS     (1 << 4)
-#define UARTLCR_PE      (1 << 3)
-#define UARTLCR_SB      (1 << 2)
-
-/* UART line status register value */
-#define UARTLSR_ERROR   (1 << 7)
-#define UARTLSR_TE      (1 << 6)
-#define UARTLSR_TFE     (1 << 5)
-#define UARTLSR_BI      (1 << 4)
-#define UARTLSR_FE      (1 << 3)
-#define UARTLSR_PE      (1 << 2)
-#define UARTLSR_OE      (1 << 1)
-#define UARTLSR_DR      (1 << 0)
-
-void rt_hw_uart_init(void);
-
-
-#endif