diff options
| author | sundm75 <[email protected]> | 2018-01-15 14:56:48 +0800 |
|---|---|---|
| committer | sundm75 <[email protected]> | 2018-01-15 14:56:48 +0800 |
| commit | b08ff9eee2461cb6654d52df1d29d6360f05ff97 (patch) | |
| tree | 97a63a07398ec34c6aedb17570634e21bccb399d /bsp/ls1cdev/drivers/display_controller.h | |
| parent | 123af35c942cb216096a8ef3c290b9e389688db7 (diff) | |
[bsp] Add SmartloongV3 display,touch,msd, hw_i2c driver
Diffstat (limited to 'bsp/ls1cdev/drivers/display_controller.h')
| -rw-r--r-- | bsp/ls1cdev/drivers/display_controller.h | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/bsp/ls1cdev/drivers/display_controller.h b/bsp/ls1cdev/drivers/display_controller.h new file mode 100644 index 0000000000..ad252a9c2f --- /dev/null +++ b/bsp/ls1cdev/drivers/display_controller.h @@ -0,0 +1,59 @@ +/* + * File : display_controller.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-08-08 lgnq first version for LS1B + * 2015-07-06 chinesebear modified for loongson 1c + * 2018-01-06 sundm75 modified for smartloong +*/ + +#ifndef __DISPLAY_CONTROLLER_H__ +#define __DISPLAY_CONTROLLER_H__ + +#include <rtthread.h> +#include "ls1c.h" + +#define DC_BASE 0xBC301240 //Display Controller + +/* Frame Buffer registers */ +#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) +#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) +#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) +#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) +#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) +#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) +#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) +#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) +#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) +#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) +#define DC_HSYNC __REG32(DC_BASE + 0x1E0) +#define DC_VDISPLAY __REG32(DC_BASE + 0x240) +#define DC_VSYNC __REG32(DC_BASE + 0x260) +#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) + +/* Display Controller driver for 1024x768 16bit */ +#define FB_XSIZE 480 +#define FB_YSIZE 272 +#define CONFIG_VIDEO_16BPP + +#define OSC 24000000 /* Hz */ + +#define K1BASE 0xA0000000 +#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) +#define HW_FB_ADDR KSEG1(_rt_framebuffer) + +struct vga_struct +{ + long pclk; + int hr,hss,hse,hfl; + int vr,vss,vse,vfl; +}; + +#endif |