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authorzhuangwei123 <[email protected]>2018-05-10 22:20:37 +0800
committerzhuangwei123 <[email protected]>2018-05-10 22:20:37 +0800
commit6725dfa59806410dcb60b59d269a92e64503da2d (patch)
tree0aa851cbca0223f1a5de7dd3f78339cb94eb9855 /bsp/ls1cdev/drivers/drv_uart.h
parentc13624298619508a2c8d10ce66f80564213c4fba (diff)
[bsp/ls1cdev]
1、uart驱动重写,采用uart驱动框架 2、添加并修改勤为本ls1c_uart 3、开启main为用户程序入口,删除application.c和startup.c,并对初始化部分做相应调整更新。 4、开启dhcp
Diffstat (limited to 'bsp/ls1cdev/drivers/drv_uart.h')
-rw-r--r--bsp/ls1cdev/drivers/drv_uart.h103
1 files changed, 103 insertions, 0 deletions
diff --git a/bsp/ls1cdev/drivers/drv_uart.h b/bsp/ls1cdev/drivers/drv_uart.h
new file mode 100644
index 0000000000..0904df5b10
--- /dev/null
+++ b/bsp/ls1cdev/drivers/drv_uart.h
@@ -0,0 +1,103 @@
+/*
+ * File : drv_uart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-05-08 zhuangwei the first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include "ls1c.h"
+
+#define DEV_CLK 252000000 // 252MHz
+#define UART_BAUDRATE 115200
+
+#define UART0_BASE 0xBFE40000
+//#define UART0_1_BASE 0xBFE41000
+#define UART1_BASE 0xBFE44000
+#define UART2_BASE 0xBFE48000
+#define UART3_BASE 0xBFE4C000
+#define UART4_BASE 0xBFE4C400
+#define UART5_BASE 0xBFE4C500
+#define UART6_BASE 0xBFE4C600
+#define UART7_BASE 0xBFE4C700
+#define UART8_BASE 0xBFE4C800
+#define UART9_BASE 0xBFE4C900
+#define UART10_BASE 0xBFE4Ca00
+#define UART11_BASE 0xBFE4Cb00
+
+/* UART registers */
+#define UART_DAT(base) __REG8(base + 0x00)
+#define UART_IER(base) __REG8(base + 0x01)
+#define UART_IIR(base) __REG8(base + 0x02)
+#define UART_FCR(base) __REG8(base + 0x02)
+#define UART_LCR(base) __REG8(base + 0x03)
+#define UART_MCR(base) __REG8(base + 0x04)
+#define UART_LSR(base) __REG8(base + 0x05)
+#define UART_MSR(base) __REG8(base + 0x06)
+
+#define UART_LSB(base) __REG8(base + 0x00)
+#define UART_MSB(base) __REG8(base + 0x01)
+
+/* UART0 registers */
+#define UART0_DAT __REG8(UART0_BASE + 0x00)
+#define UART0_IER __REG8(UART0_BASE + 0x01)
+#define UART0_IIR __REG8(UART0_BASE + 0x02)
+#define UART0_FCR __REG8(UART0_BASE + 0x02)
+#define UART0_LCR __REG8(UART0_BASE + 0x03)
+#define UART0_MCR __REG8(UART0_BASE + 0x04)
+#define UART0_LSR __REG8(UART0_BASE + 0x05)
+#define UART0_MSR __REG8(UART0_BASE + 0x06)
+
+#define UART0_LSB __REG8(UART0_BASE + 0x00)
+#define UART0_MSB __REG8(UART0_BASE + 0x01)
+
+/* UART1 registers */
+#define UART1_DAT __REG8(UART1_BASE + 0x00)
+#define UART1_IER __REG8(UART1_BASE + 0x01)
+#define UART1_IIR __REG8(UART1_BASE + 0x02)
+#define UART1_FCR __REG8(UART1_BASE + 0x02)
+#define UART1_LCR __REG8(UART1_BASE + 0x03)
+#define UART1_MCR __REG8(UART1_BASE + 0x04)
+#define UART1_LSR __REG8(UART1_BASE + 0x05)
+#define UART1_MSR __REG8(UART1_BASE + 0x06)
+
+#define UART1_LSB __REG8(UART1_BASE + 0x00)
+#define UART1_MSB __REG8(UART1_BASE + 0x01)
+
+/* UART interrupt enable register value */
+#define UARTIER_IME (1 << 3)
+#define UARTIER_ILE (1 << 2)
+#define UARTIER_ITXE (1 << 1)
+#define UARTIER_IRXE (1 << 0)
+
+/* UART line control register value */
+#define UARTLCR_DLAB (1 << 7)
+#define UARTLCR_BCB (1 << 6)
+#define UARTLCR_SPB (1 << 5)
+#define UARTLCR_EPS (1 << 4)
+#define UARTLCR_PE (1 << 3)
+#define UARTLCR_SB (1 << 2)
+
+/* UART line status register value */
+#define UARTLSR_ERROR (1 << 7)
+#define UARTLSR_TE (1 << 6)
+#define UARTLSR_TFE (1 << 5)
+#define UARTLSR_BI (1 << 4)
+#define UARTLSR_FE (1 << 3)
+#define UARTLSR_PE (1 << 2)
+#define UARTLSR_OE (1 << 1)
+#define UARTLSR_DR (1 << 0)
+
+void rt_hw_uart_init(void);
+
+
+#endif