diff options
| author | Ming, Bai <[email protected]> | 2013-01-08 22:40:58 +0800 |
|---|---|---|
| committer | Ming, Bai <[email protected]> | 2013-01-08 22:40:58 +0800 |
| commit | b4de7cce57305033e86c3b187271683b609ddb26 (patch) | |
| tree | 5380a19a3f6bced1d04439a94bf1f76fffb3a179 /bsp/sam7x | |
| parent | f3192c229349119dfd8361a09a52fbab6f99f97e (diff) | |
Re-normalizing the repo
Diffstat (limited to 'bsp/sam7x')
| -rw-r--r-- | bsp/sam7x/applications/SConscript | 18 | ||||
| -rw-r--r-- | bsp/sam7x/applications/application.c | 4 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/AT91SAM7X.h | 168 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/SConscript | 32 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/mii.h | 312 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/sam7x_emac.c | 1318 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/sam7x_emac.h | 218 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/sd.c | 1324 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/sd.h | 12 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/serial.c | 10 | ||||
| -rw-r--r-- | bsp/sam7x/drivers/serial.h | 26 | ||||
| -rw-r--r-- | bsp/sam7x/rtconfig.h | 290 |
12 files changed, 1866 insertions, 1866 deletions
diff --git a/bsp/sam7x/applications/SConscript b/bsp/sam7x/applications/SConscript index 4fe38ed0cf..4ccb177207 100644 --- a/bsp/sam7x/applications/SConscript +++ b/bsp/sam7x/applications/SConscript @@ -1,9 +1,9 @@ -from building import *
-
-cwd = GetCurrentDir()
-src = Glob('*.c')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
+from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/sam7x/applications/application.c b/bsp/sam7x/applications/application.c index 5cd12348de..3c915cf5b9 100644 --- a/bsp/sam7x/applications/application.c +++ b/bsp/sam7x/applications/application.c @@ -30,8 +30,8 @@ #endif #ifdef RT_USING_LWIP -#include <lwip/sys.h>
-#include <netif/ethernetif.h>
+#include <lwip/sys.h> +#include <netif/ethernetif.h> #include "sam7x_emac.h" #endif diff --git a/bsp/sam7x/drivers/AT91SAM7X.h b/bsp/sam7x/drivers/AT91SAM7X.h index 54a7d11c46..96430b2a17 100644 --- a/bsp/sam7x/drivers/AT91SAM7X.h +++ b/bsp/sam7x/drivers/AT91SAM7X.h @@ -57,11 +57,11 @@ extern "C" { #define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ #define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ -/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
-#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
-#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
-#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
+/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ #define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ @@ -240,86 +240,86 @@ extern "C" { #define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ #define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ #define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ -
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_RNPR (AT91_REG(0xFFFE4110)) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_TPR (AT91_REG(0xFFFE4108)) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_RPR (AT91_REG(0xFFFE4100)) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_PTSR (AT91_REG(0xFFFE4124)) // (PDC_SPI1) PDC Transfer Status Register
-#define AT91C_SPI1_RCR (AT91_REG(0xFFFE4104)) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_TCR (AT91_REG(0xFFFE410C)) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RNCR (AT91_REG(0xFFFE4114)) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_TNCR (AT91_REG(0xFFFE411C)) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TNPR (AT91_REG(0xFFFE4118)) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_PTCR (AT91_REG(0xFFFE4120)) // (PDC_SPI1) PDC Transfer Control Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_CSR (AT91_REG(0xFFFE4030)) // (SPI1) Chip Select Register
-#define AT91C_SPI1_IDR (AT91_REG(0xFFFE4018)) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR (AT91_REG(0xFFFE4010)) // (SPI1) Status Register
-#define AT91C_SPI1_RDR (AT91_REG(0xFFFE4008)) // (SPI1) Receive Data Register
-#define AT91C_SPI1_CR (AT91_REG(0xFFFE4000)) // (SPI1) Control Register
-#define AT91C_SPI1_IMR (AT91_REG(0xFFFE401C)) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER (AT91_REG(0xFFFE4014)) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_TDR (AT91_REG(0xFFFE400C)) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_MR (AT91_REG(0xFFFE4004)) // (SPI1) Mode Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_REG(0xFFFE0120)) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TNPR (AT91_REG(0xFFFE0118)) // (PDC_SPI0) Transmit Next Pointer Register
-#define AT91C_SPI0_RNPR (AT91_REG(0xFFFE0110)) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_TPR (AT91_REG(0xFFFE0108)) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_RPR (AT91_REG(0xFFFE0100)) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_PTSR (AT91_REG(0xFFFE0124)) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_TNCR (AT91_REG(0xFFFE011C)) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_REG(0xFFFE0114)) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TCR (AT91_REG(0xFFFE010C)) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR (AT91_REG(0xFFFE0104)) // (PDC_SPI0) Receive Counter Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_CSR (AT91_REG(0xFFFE0030)) // (SPI0) Chip Select Register
-#define AT91C_SPI0_IDR (AT91_REG(0xFFFE0018)) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_SR (AT91_REG(0xFFFE0010)) // (SPI0) Status Register
-#define AT91C_SPI0_RDR (AT91_REG(0xFFFE0008)) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CR (AT91_REG(0xFFFE0000)) // (SPI0) Control Register
-#define AT91C_SPI0_IMR (AT91_REG(0xFFFE001C)) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_IER (AT91_REG(0xFFFE0014)) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_TDR (AT91_REG(0xFFFE000C)) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_MR (AT91_REG(0xFFFE0004)) // (SPI0) Mode Register
-/******************************************************************************/
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
-/******************************************************************************/
-#define AT91C_ID_FIQ ( 0) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( 1) /* System Peripheral */
-#define AT91C_ID_PIOA ( 2) /* Parallel IO Controller A */
-#define AT91C_ID_PIOB ( 3) /* Parallel IO Controller B */
-#define AT91C_ID_SPI0 ( 4) /* Serial Peripheral Interface 0 */
-#define AT91C_ID_SPI1 ( 5) /* Serial Peripheral Interface 1 */
-#define AT91C_ID_US0 ( 6) /* USART 0 */
-#define AT91C_ID_US1 ( 7) /* USART 1 */
-#define AT91C_ID_SSC ( 8) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( 9) /* Two-Wire Interface */
-#define AT91C_ID_PWMC (10) /* PWM Controller */
-#define AT91C_ID_UDP (11) /* USB Device Port */
-#define AT91C_ID_TC0 (12) /* Timer Counter 0 */
-#define AT91C_ID_TC1 (13) /* Timer Counter 1 */
-#define AT91C_ID_TC2 (14) /* Timer Counter 2 */
-#define AT91C_ID_CAN (15) /* Control Area Network Controller */
-#define AT91C_ID_EMAC (16) /* Ethernet MAC */
-#define AT91C_ID_ADC (17) /* Analog-to-Digital Converter */
-#define AT91C_ID_AES (18) /* Advanced Encryption Standard 128-bit */
-#define AT91C_ID_TDES (19) /* Triple Data Encryption Standard */
-#define AT91C_ID_20_Reserved (20) /* Reserved */
-#define AT91C_ID_21_Reserved (21) /* Reserved */
-#define AT91C_ID_22_Reserved (22) /* Reserved */
-#define AT91C_ID_23_Reserved (23) /* Reserved */
-#define AT91C_ID_24_Reserved (24) /* Reserved */
-#define AT91C_ID_25_Reserved (25) /* Reserved */
-#define AT91C_ID_26_Reserved (26) /* Reserved */
-#define AT91C_ID_27_Reserved (27) /* Reserved */
-#define AT91C_ID_28_Reserved (28) /* Reserved */
-#define AT91C_ID_29_Reserved (29) /* Reserved */
-#define AT91C_ID_IRQ0 (30) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 (31) /* Advanced Interrupt Controller (IRQ1) */
-#define AT91C_ALL_INT (0xC00FFFFF) /* ALL VALID INTERRUPTS */
+// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_RNPR (AT91_REG(0xFFFE4110)) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_TPR (AT91_REG(0xFFFE4108)) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_RPR (AT91_REG(0xFFFE4100)) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_PTSR (AT91_REG(0xFFFE4124)) // (PDC_SPI1) PDC Transfer Status Register +#define AT91C_SPI1_RCR (AT91_REG(0xFFFE4104)) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_TCR (AT91_REG(0xFFFE410C)) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RNCR (AT91_REG(0xFFFE4114)) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_TNCR (AT91_REG(0xFFFE411C)) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TNPR (AT91_REG(0xFFFE4118)) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_PTCR (AT91_REG(0xFFFE4120)) // (PDC_SPI1) PDC Transfer Control Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_CSR (AT91_REG(0xFFFE4030)) // (SPI1) Chip Select Register +#define AT91C_SPI1_IDR (AT91_REG(0xFFFE4018)) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_REG(0xFFFE4010)) // (SPI1) Status Register +#define AT91C_SPI1_RDR (AT91_REG(0xFFFE4008)) // (SPI1) Receive Data Register +#define AT91C_SPI1_CR (AT91_REG(0xFFFE4000)) // (SPI1) Control Register +#define AT91C_SPI1_IMR (AT91_REG(0xFFFE401C)) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_REG(0xFFFE4014)) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_TDR (AT91_REG(0xFFFE400C)) // (SPI1) Transmit Data Register +#define AT91C_SPI1_MR (AT91_REG(0xFFFE4004)) // (SPI1) Mode Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_REG(0xFFFE0120)) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TNPR (AT91_REG(0xFFFE0118)) // (PDC_SPI0) Transmit Next Pointer Register +#define AT91C_SPI0_RNPR (AT91_REG(0xFFFE0110)) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_TPR (AT91_REG(0xFFFE0108)) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_RPR (AT91_REG(0xFFFE0100)) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_PTSR (AT91_REG(0xFFFE0124)) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_TNCR (AT91_REG(0xFFFE011C)) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_REG(0xFFFE0114)) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TCR (AT91_REG(0xFFFE010C)) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_REG(0xFFFE0104)) // (PDC_SPI0) Receive Counter Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_CSR (AT91_REG(0xFFFE0030)) // (SPI0) Chip Select Register +#define AT91C_SPI0_IDR (AT91_REG(0xFFFE0018)) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_SR (AT91_REG(0xFFFE0010)) // (SPI0) Status Register +#define AT91C_SPI0_RDR (AT91_REG(0xFFFE0008)) // (SPI0) Receive Data Register +#define AT91C_SPI0_CR (AT91_REG(0xFFFE0000)) // (SPI0) Control Register +#define AT91C_SPI0_IMR (AT91_REG(0xFFFE001C)) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_IER (AT91_REG(0xFFFE0014)) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_TDR (AT91_REG(0xFFFE000C)) // (SPI0) Transmit Data Register +#define AT91C_SPI0_MR (AT91_REG(0xFFFE0004)) // (SPI0) Mode Register + +/******************************************************************************/ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/******************************************************************************/ +#define AT91C_ID_FIQ ( 0) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( 1) /* System Peripheral */ +#define AT91C_ID_PIOA ( 2) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( 3) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( 4) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( 5) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( 6) /* USART 0 */ +#define AT91C_ID_US1 ( 7) /* USART 1 */ +#define AT91C_ID_SSC ( 8) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( 9) /* Two-Wire Interface */ +#define AT91C_ID_PWMC (10) /* PWM Controller */ +#define AT91C_ID_UDP (11) /* USB Device Port */ +#define AT91C_ID_TC0 (12) /* Timer Counter 0 */ +#define AT91C_ID_TC1 (13) /* Timer Counter 1 */ +#define AT91C_ID_TC2 (14) /* Timer Counter 2 */ +#define AT91C_ID_CAN (15) /* Control Area Network Controller */ +#define AT91C_ID_EMAC (16) /* Ethernet MAC */ +#define AT91C_ID_ADC (17) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES (18) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES (19) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved (20) /* Reserved */ +#define AT91C_ID_21_Reserved (21) /* Reserved */ +#define AT91C_ID_22_Reserved (22) /* Reserved */ +#define AT91C_ID_23_Reserved (23) /* Reserved */ +#define AT91C_ID_24_Reserved (24) /* Reserved */ +#define AT91C_ID_25_Reserved (25) /* Reserved */ +#define AT91C_ID_26_Reserved (26) /* Reserved */ +#define AT91C_ID_27_Reserved (27) /* Reserved */ +#define AT91C_ID_28_Reserved (28) /* Reserved */ +#define AT91C_ID_29_Reserved (29) /* Reserved */ +#define AT91C_ID_IRQ0 (30) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 (31) /* Advanced Interrupt Controller (IRQ1) */ +#define AT91C_ALL_INT (0xC00FFFFF) /* ALL VALID INTERRUPTS */ #define MCK 48054857 diff --git a/bsp/sam7x/drivers/SConscript b/bsp/sam7x/drivers/SConscript index 5b10d6f2f5..466c472cd8 100644 --- a/bsp/sam7x/drivers/SConscript +++ b/bsp/sam7x/drivers/SConscript @@ -1,16 +1,16 @@ -from building import *
-
-cwd = GetCurrentDir()
-src = Glob('*.c')
-
-# remove no need file.
-if GetDepend('RT_USING_LWIP') == False:
- SrcRemove(src, 'sam7x_emac.c')
-if GetDepend('RT_USING_DFS') == False:
- SrcRemove(src, 'ssd.c')
-
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
+from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +# remove no need file. +if GetDepend('RT_USING_LWIP') == False: + SrcRemove(src, 'sam7x_emac.c') +if GetDepend('RT_USING_DFS') == False: + SrcRemove(src, 'ssd.c') + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/sam7x/drivers/mii.h b/bsp/sam7x/drivers/mii.h index 4ec25667a3..cd243f620d 100644 --- a/bsp/sam7x/drivers/mii.h +++ b/bsp/sam7x/drivers/mii.h @@ -1,156 +1,156 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/*
- * Parts of this file are borrowed by the Linux include file linux/mii.h:
- * Copyright (C) 1996, 1999, 2001 David S. Miller ([email protected])
- */
-
-#ifndef _MII_H_
-#define _MII_H_
-
-/* Generic MII registers. */
-#define MII_BMCR 0x00 /* Basic mode control register */
-#define MII_BMSR 0x01 /* Basic mode status register */
-#define MII_PHYSID1 0x02 /* PHYS ID 1 */
-#define MII_PHYSID2 0x03 /* PHYS ID 2 */
-#define MII_ADVERTISE 0x04 /* Advertisement control reg */
-#define MII_LPA 0x05 /* Link partner ability reg */
-#define MII_EXPANSION 0x06 /* Expansion register */
-#define MII_CTRL1000 0x09 /* 1000BASE-T control */
-#define MII_STAT1000 0x0a /* 1000BASE-T status */
-#define MII_ESTATUS 0x0f /* Extended Status */
-#define MII_DCOUNTER 0x12 /* Disconnect counter */
-#define MII_FCSCOUNTER 0x13 /* False carrier counter */
-#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
-#define MII_RERRCOUNTER 0x15 /* Receive error counter */
-#define MII_SREVISION 0x16 /* Silicon revision */
-#define MII_RESV1 0x17 /* Reserved... */
-#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
-#define MII_PHYADDR 0x19 /* PHY address */
-#define MII_RESV2 0x1a /* Reserved... */
-#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
-#define MII_NCONFIG 0x1c /* Network interface config */
-
-/* Basic mode control register. */
-#define BMCR_RESV 0x003f /* Unused... */
-#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
-#define BMCR_CTST 0x0080 /* Collision test */
-#define BMCR_FULLDPLX 0x0100 /* Full duplex */
-#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
-#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
-#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
-#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
-#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
-#define BMCR_RESET 0x8000 /* Reset the DP83840 */
-
-/* Basic mode status register. */
-#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
-#define BMSR_JCD 0x0002 /* Jabber detected */
-#define BMSR_LSTATUS 0x0004 /* Link status */
-#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
-#define BMSR_RFAULT 0x0010 /* Remote fault detected */
-#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
-#define BMSR_RESV 0x00c0 /* Unused... */
-#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
-#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
-#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
-#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
-#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
-#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
-
-/* Advertisement control register. */
-#define ADVERTISE_SLCT 0x001f /* Selector bits */
-#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
-#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
-#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
-#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
-#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
-#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
-#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
-#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
-#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
-#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
-#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
-#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
-#define ADVERTISE_RESV 0x1000 /* Unused... */
-#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
-#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
-#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
-
-#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
- ADVERTISE_CSMA)
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
- ADVERTISE_100HALF | ADVERTISE_100FULL)
-
-/* Link partner ability register. */
-#define LPA_SLCT 0x001f /* Same as advertise selector */
-#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
-#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
-#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
-#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
-#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
-#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
-#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
-#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
-#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
-#define LPA_PAUSE_CAP 0x0400 /* Can pause */
-#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
-#define LPA_RESV 0x1000 /* Unused... */
-#define LPA_RFAULT 0x2000 /* Link partner faulted */
-#define LPA_LPACK 0x4000 /* Link partner acked us */
-#define LPA_NPAGE 0x8000 /* Next page bit */
-
-#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
-#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
-
-/* Expansion register for auto-negotiation. */
-#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
-#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
-#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
-#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
-#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
-#define EXPANSION_RESV 0xffe0 /* Unused... */
-
-#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
-#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
-
-/* N-way test register. */
-#define NWAYTEST_RESV1 0x00ff /* Unused... */
-#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
-#define NWAYTEST_RESV2 0xfe00 /* Unused... */
-
-/* 1000BASE-T Control register */
-#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
-#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
-
-/* 1000BASE-T Status register */
-#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
-#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
-#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
-#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
-
-#define MII_DM9161_ID 0x0181b8a0
-#define MII_AM79C875_ID 0x00225540
-#define MII_MICREL_ID 0x00221610
-
-#endif /* _MII_H_ */
+/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +/* + * Parts of this file are borrowed by the Linux include file linux/mii.h: + * Copyright (C) 1996, 1999, 2001 David S. Miller ([email protected]) + */ + +#ifndef _MII_H_ +#define _MII_H_ + +/* Generic MII registers. */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define ADVERTISE_RESV 0x1000 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* Link partner ability register. */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_PAUSE_CAP 0x0400 /* Can pause */ +#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ +#define LPA_RESV 0x1000 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* Expansion register for auto-negotiation. */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ + +/* N-way test register. */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ + +/* 1000BASE-T Status register */ +#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ +#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ +#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ +#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ + +#define MII_DM9161_ID 0x0181b8a0 +#define MII_AM79C875_ID 0x00225540 +#define MII_MICREL_ID 0x00221610 + +#endif /* _MII_H_ */ diff --git a/bsp/sam7x/drivers/sam7x_emac.c b/bsp/sam7x/drivers/sam7x_emac.c index 3cad4e8f19..b2375d45c6 100644 --- a/bsp/sam7x/drivers/sam7x_emac.c +++ b/bsp/sam7x/drivers/sam7x_emac.c @@ -1,660 +1,660 @@ -#include <rthw.h>
-#include <rtthread.h>
-#include <netif/ethernetif.h>
-
-#include "sam7x_emac.h"
-#include "AT91SAM7X256.h"
-#include "lwipopts.h"
-#include "lwip/mem.h"
-
-#define MAX_ADDR_LEN 6
-
-#ifdef DM9161
-#define EMAC_PIO_CFG (AT91C_PB8_EMDC | \
- AT91C_PB9_EMDIO | \
- AT91C_PB2_ETX0 | \
- AT91C_PB3_ETX1 | \
- AT91C_PB10_ETX2 | \
- AT91C_PB11_ETX3 | \
- AT91C_PB1_ETXEN | \
- AT91C_PB0_ETXCK_EREFCK | \
- AT91C_PB15_ERXDV_ECRSDV | \
- AT91C_PB5_ERX0 | \
- AT91C_PB6_ERX1 | \
- AT91C_PB12_ETXER | \
- AT91C_PB13_ERX2 | \
- AT91C_PB14_ERX3 | \
- AT91C_PB17_ERXCK | \
- AT91C_PB16_ECOL | \
- AT91C_PB4_ECRS | \
- AT91C_PB7_ERXER)
-#else
-#define EMAC_PIO_CFG (AT91C_PB0_ETXCK_EREFCK | \
- AT91C_PB1_ETXEN | \
- AT91C_PB2_ETX0 | \
- AT91C_PB3_ETX1 | \
- AT91C_PB4_ECRS | \
- AT91C_PB5_ERX0 | \
- AT91C_PB6_ERX1 | \
- AT91C_PB7_ERXER | \
- AT91C_PB8_EMDC | \
- AT91C_PB9_EMDIO | \
- AT91C_PB10_ETX2 | \
- AT91C_PB11_ETX3 | \
- AT91C_PB10_ETX2 | \
- AT91C_PB13_ERX2 | \
- AT91C_PB14_ERX3 | \
- AT91C_PB15_ERXDV_ECRSDV| \
- AT91C_PB16_ECOL | \
- AT91C_PB17_ERXCK)
-#endif
-
-#define RB_BUFFER_SIZE 8 /* max number of receive buffers */
-#define ETH_RX_BUF_SIZE 128
-
-#define TB_BUFFER_SIZE 4
-#define ETH_TX_BUF_SIZE (PBUF_POOL_BUFSIZE)
-
-struct rbf_t
-{
- rt_uint32_t addr;
- rt_uint32_t status;
-};
-
-static rt_uint32_t current_rb_index; /* current receive buffer index */
-static volatile struct rbf_t rb_descriptors[RB_BUFFER_SIZE];
-static volatile struct rbf_t tb_descriptors[TB_BUFFER_SIZE];
-static rt_uint8_t rx_buf[RB_BUFFER_SIZE][ETH_RX_BUF_SIZE] __attribute__ ((aligned (8)));
-static rt_uint8_t tx_buf[TB_BUFFER_SIZE][ETH_TX_BUF_SIZE] __attribute__ ((aligned (8)));
-static struct rt_semaphore tx_sem;
-
-struct net_device
-{
- /* inherit from ethernet device */
- struct eth_device parent;
-
- /* interface address info. */
- rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
-};
-static struct net_device sam7x_dev_entry;
-static struct net_device *sam7x_dev =&sam7x_dev_entry;
-AT91PS_EMAC pEmac = AT91C_BASE_EMAC;
-
-rt_inline void write_phy(rt_uint8_t addr, rt_uint32_t value)
-{
- AT91C_BASE_EMAC->EMAC_MAN = ((0x01<<30) | (2 << 16) | (1 << 28) |
- (AT91C_PHY_ADDR << 23) | (addr << 18)) | value;
- /* Wait until IDLE bit in Network Status register is cleared */
- while (!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
-}
-
-rt_inline rt_uint32_t read_phy(rt_uint8_t addr)
-{
- AT91C_BASE_EMAC->EMAC_MAN = (0x01<<30) | (0x02 << 16) | (0x02 << 28) |
- (AT91C_PHY_ADDR << 23) | (addr << 18);
-
- /* Wait until IDLE bit in Network Status register is cleared */
- while (!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
-
- return (AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff);
-}
-
-rt_inline void sam7xether_reset_tx_desc(void)
-{
- static rt_uint32_t index = 0;
-
- if(tb_descriptors[index].status & TxDESC_STATUS_USED)
- {
- while(!(tb_descriptors[index].status & TxDESC_STATUS_LAST_BUF))
- {
- index ++;
- if(index >= TB_BUFFER_SIZE)index = 0;
-
- tb_descriptors[index].status |= TxDESC_STATUS_USED;
- }
-
- index ++;
- if(index >= TB_BUFFER_SIZE)index = 0;
- }
-}
-
-
-/* interrupt service routing */
-static void sam7xether_isr(int irq)
-{
- /* Variable definitions can be made now. */
- volatile rt_uint32_t isr, rsr;
-
- /* get status */
- isr = AT91C_BASE_EMAC->EMAC_ISR;
- rsr = AT91C_BASE_EMAC->EMAC_RSR;
-
- if( ( isr & AT91C_EMAC_RCOMP ) || ( rsr & AT91C_EMAC_REC ) )
- {
- rt_err_t result;
-
- /* a frame has been received */
- result = eth_device_ready((struct eth_device*)&(sam7x_dev->parent));
- RT_ASSERT(result == RT_EOK);
-
- AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
- }
-
- if( isr & AT91C_EMAC_TCOMP )
- {
- /* A frame has been transmitted. Mark all the buffers as free */
- sam7xether_reset_tx_desc();
-
- AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP;
- }
-}
-
-rt_inline void linksetup(void)
-{
- rt_uint32_t value, tout, id1, id2;
-#ifdef DM9161
- rt_uint32_t ulBMSR,ulBMCR,i;
-#endif
-
-#ifdef DM9161
- //PHY has internal pull down : disable MII isolate
- tout = read_phy(PHY_REG_BMCR);
- tout = read_phy(PHY_REG_BMCR);
- tout &= ~BMCR_ISOLATE;
- write_phy(PHY_REG_BMCR, tout);
-
- /* Check if this is a RTL8201 or DM9161 PHY. */
- id1 = read_phy(PHY_REG_PHYID1);
- id2 = read_phy(PHY_REG_PHYID2);
-
- if (((id1 << 16) | (id2 & 0xfff0)) == MII_DM9161_ID)
- {
- rt_kprintf("read MII_DM9161_ID ok!\n");
-
- tout = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
- DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
- write_phy(PHY_REG_ANAR, tout);
- // Wait for PHY auto negotiation completed
- i = 0;
- do {
- ulBMSR = read_phy(PHY_REG_BMSR);
- ulBMSR = read_phy(PHY_REG_BMSR);
- i++;
-
- if(i >= 0xffff)
- break;
- }while (!(ulBMSR & BMSR_ANEGCOMPLETE));
-
- if(i >= 0xffff)
- rt_kprintf("PHY No Link!\n");
- else
- rt_kprintf("PHY auto negotiation completed!\n");
-
- /* Update the MAC register NCFGR. */
- AT91C_BASE_EMAC->EMAC_NCFGR = 0;
- ulBMCR = read_phy(PHY_REG_BMCR);
-
- if (ulBMCR & BMCR_ANENABLE)
- {
- /* AutoNegotiation is enabled. */
- if(!(ulBMSR & BMSR_ANEGCOMPLETE))
- {
- /* Auto-negotitation in progress. */
- rt_kprintf("Auto-negotitation in progress!\n");
- return;
- }
-
- if (ulBMCR & BMCR_SPEED100)
- {
- /* Speed 100Mbit is enabled. */
- AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD;
-
- }
- if (ulBMCR & BMCR_FULLDPLX)
- {
- /* Full duplex is enabled. */
- AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD;
- }
- }
- }
-#else
- /* Check if this is a RTL8201 or DM9161 PHY. */
- id1 = read_phy(PHY_REG_PHYID1);
- id2 = read_phy(PHY_REG_PHYID2);
-
- if (((id2 << 16) | (id1 & 0xfff0)) == MII_RTL8201_ID)
- {
- rt_kprintf("read MII_RTL8201_ID ok!\n");
-
-
- /* Configure the PHY device */
- /* Use autonegotiation about the link speed. */
- write_phy (PHY_REG_BMCR, PHY_AUTO_NEG);
-
- /* Wait to complete Auto_Negotiation. */
- for (tout = 0; tout < 0x100000; tout++)
- {
- value = read_phy (PHY_REG_BMSR);
- if (value & BMSR_ANEGCOMPLETE) break; /* autonegotiation finished. */
- }
-
- /* Check the link status. */
- for (tout = 0; tout < 0x10000; tout++)
- {
- value = read_phy (PHY_REG_BMSR);
- if (value & BMSR_LINKST) break; /* Link is on. */
- }
- }
- value = read_phy (PHY_REG_ANLPAR);
-
- /* Update the MAC register NCFGR. */
- AT91C_BASE_EMAC->EMAC_NCFGR &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-
- /* set full duplex . */
- if (value & 0xA000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD;
- /* set speed */
- if (value & 0xC000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD;
- #endif
-}
-
-/*
- * Set the MAC address.
- */
-rt_inline void update_mac_address(struct net_device* device)
-{
- AT91C_BASE_EMAC->EMAC_SA1L = (device->dev_addr[3] << 24) |
- (device->dev_addr[2] << 16) |
- (device->dev_addr[1] << 8) |
- device->dev_addr[0];
- AT91C_BASE_EMAC->EMAC_SA1H = (device->dev_addr[5] << 8) |
- device->dev_addr[4];
-}
-
-rt_inline void sam7xether_desc_init()
-{
- rt_uint32_t i;
-
- /* Rx Buffer Descriptor initialization */
- current_rb_index = 0;
- for (i = 0; i < RB_BUFFER_SIZE; i++)
- {
- rb_descriptors[i].addr = (rt_uint32_t)&(rx_buf[i][0]);
- rb_descriptors[i].status = 0;
- }
- /* Set the WRAP bit at the end of the list descriptor. */
- rb_descriptors[RB_BUFFER_SIZE-1].addr |= 0x02;
- /* Set Rx Queue pointer to descriptor list. */
- AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int)&(rb_descriptors[0]);
-
- /* Tx Buffer Descriptor initialization */
- for (i = 0; i < TB_BUFFER_SIZE; i++)
- {
- tb_descriptors[i].addr = (rt_uint32_t)&(tx_buf[i][0]);
- tb_descriptors[i].status = TxDESC_STATUS_USED;
- }
- /* Set the WRAP bit at the end of the list descriptor. */
- tb_descriptors[TB_BUFFER_SIZE-1].status |= TxDESC_STATUS_WRAP;
- /* Set Tx Queue pointer to descriptor list. */
- AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int)&(tb_descriptors[0]);
-}
-
-/* RT-Thread Device Interface */
-
-/* initialize the interface */
-rt_err_t sam7xether_init(rt_device_t dev)
-{
- rt_uint32_t i;
-
- /* enable peripheral clock for EMAC and PIO B */
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB | 1 << AT91C_ID_EMAC;
-
- /* Disable pull up on RXDV => PHY normal mode (not in test mode), */
- /* and set MII mode. PHY has internal pull down. */
- AT91C_BASE_PIOB->PIO_PPUDR = (1<<16) | (1 << 15);
-
- /* Clear PB18 <=> PHY powerdown */
- AT91C_BASE_PIOB->PIO_PER = 1<<18;
- AT91C_BASE_PIOB->PIO_OER = 1<<18;
- AT91C_BASE_PIOB->PIO_CODR = 1<<18;
-
- /* EMAC IO init for EMAC-PHY communication. */
- AT91C_BASE_PIOB->PIO_ASR = EMAC_PIO_CFG;
- AT91C_BASE_PIOB->PIO_PDR = EMAC_PIO_CFG; // Set in Periph mode
-
- /* Enable communication between EMAC-PHY. */
- AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
- /* MDC = MCK/32 */
- AT91C_BASE_EMAC->EMAC_NCFGR |= 2<<10;
-
- /* Reset PHY */
- AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB7_ERXER;
-
- AT91C_BASE_RSTC->RSTC_RMR = 0xA5000000 | (0x08 << 8) ;
- AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;
-
- i = 0;
- while(!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))
- {
- i++;
- if(i >= 0xfffff)
- break;
- }
-
- for(i=0; i<0xfffff; i++);//* �ȴ�һ��ָ����ʱ�䣬ʹPHY����
-
- linksetup();
-
- rt_kprintf("linksetup ok!\n");
-
- /* Disable management port in MAC control register. */
- AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
-
- /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK */
- AT91C_BASE_EMAC->EMAC_USRIO= AT91C_EMAC_CLKEN;
-
- /* Transmit and Receive disable. */
- AT91C_BASE_EMAC->EMAC_NCR &= ~(AT91C_EMAC_RE | AT91C_EMAC_TE);
-
- /* init descriptor */
- sam7xether_desc_init();
-
- /* Clear receive and transmit status registers. */
- AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
- AT91C_BASE_EMAC->EMAC_TSR = (AT91C_EMAC_UND | AT91C_EMAC_COMP| AT91C_EMAC_BEX |
- AT91C_EMAC_RLES| AT91C_EMAC_COL | AT91C_EMAC_UBR);
-
- /* Configure EMAC operation mode. */
- //AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_BIG | AT91C_EMAC_DRFCS);
- // ����������Ч֡�����ջ����� *������FCS�ֶ� �����չ㲥֡ ������1526�ֽڳ�֡
- AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF |AT91C_EMAC_DRFCS | AT91C_EMAC_NBC | AT91C_EMAC_BIG;
- AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);
-
- /* update MAC address */
- update_mac_address(sam7x_dev);
-
- /* enable interrupt */
- AT91C_BASE_EMAC->EMAC_IDR = 0x3fff;
- AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
-
- /* setup interrupt */
- rt_hw_interrupt_install(AT91C_ID_EMAC, sam7xether_isr, RT_NULL);
- *(volatile unsigned int*)(0xFFFFF000 + AT91C_ID_EMAC * 4) = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5;
- // AT91C_AIC_SMR(AT91C_ID_EMAC) = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5;
- rt_hw_interrupt_umask(AT91C_ID_EMAC);
-
- return RT_EOK;
-}
-
-/* control the interface */
-rt_err_t sam7xether_control(rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- switch(cmd)
- {
- case NIOCTL_GADDR:
- /* get mac address */
- if(args) rt_memcpy(args, sam7x_dev_entry.dev_addr, 6);
- else return -RT_ERROR;
- break;
-
- default :
- break;
- }
-
- return RT_EOK;
-}
-
-/* Open the ethernet interface */
-rt_err_t sam7xether_open(rt_device_t dev, rt_uint16_t oflags)
-{
- return RT_EOK;
-}
-
-/* Close the interface */
-rt_err_t sam7xether_close(rt_device_t dev)
-{
- return RT_EOK;
-}
-
-/* Read */
-rt_size_t sam7xether_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_set_errno(-RT_ENOSYS);
- return 0;
-}
-
-/* Write */
-rt_size_t sam7xether_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- rt_set_errno(-RT_ENOSYS);
- return 0;
-}
-
-/* See the header file for descriptions of public functions. */
-void sam7xether_write_frame(rt_uint8_t *ptr, rt_uint32_t length, rt_bool_t eof)
-{
- rt_uint8_t *buf_ptr;
- static rt_uint32_t current_tb_index = 0;
- rt_uint32_t is_last, tx_offset = 0, remain, pdu_length;
-
- while(tx_offset < length)
- {
- /* check whether buffer is available */
- while(!(tb_descriptors[current_tb_index].status & TxDESC_STATUS_USED))
- {
- /* no buffer */
- rt_thread_delay(5);
- }
-
- /* Get the address of the buffer from the descriptor, then copy
- the data into the buffer. */
- buf_ptr = (rt_uint8_t *)tb_descriptors[current_tb_index].addr;
-
- /* How much can we write to the buffer? */
- remain = length - tx_offset;
- pdu_length = (remain <= ETH_TX_BUF_SIZE)? remain : ETH_TX_BUF_SIZE;
-
- /* Copy the data into the buffer. */
- rt_memcpy(buf_ptr, &ptr[tx_offset], pdu_length );
- tx_offset += pdu_length;
-
- /* Is this the last data for the frame? */
- if((eof == RT_TRUE) && ( tx_offset >= length )) is_last = TxDESC_STATUS_LAST_BUF;
- else is_last = 0;
-
- /* Fill out the necessary in the descriptor to get the data sent,
- then move to the next descriptor, wrapping if necessary. */
- if(current_tb_index >= (TB_BUFFER_SIZE - 1))
- {
- tb_descriptors[current_tb_index].status = ( pdu_length & TxDESC_STATUS_BUF_SIZE )
- | is_last
- | TxDESC_STATUS_WRAP;
- current_tb_index = 0;
- }
- else
- {
- tb_descriptors[current_tb_index].status = ( pdu_length & TxDESC_STATUS_BUF_SIZE )
- | is_last;
- current_tb_index++;
- }
-
- /* If this is the last buffer to be sent for this frame we can
- start the transmission. */
- if(is_last)
- {
- AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
- }
- }
-}
-
-/* ethernet device interface */
-/*
- * Transmit packet.
- */
-rt_err_t sam7xether_tx( rt_device_t dev, struct pbuf* p)
-{
- struct pbuf* q;
-
- /* lock tx operation */
- rt_sem_take(&tx_sem, RT_WAITING_FOREVER);
-
- for (q = p; q != NULL; q = q->next)
- {
- if (q->next == RT_NULL) sam7xether_write_frame(q->payload, q->len, RT_TRUE);
- else sam7xether_write_frame(q->payload, q->len, RT_FALSE);
- }
-
- rt_sem_release(&tx_sem);
-
- return 0;
-}
-
-void sam7xether_read_frame(rt_uint8_t* ptr, rt_uint32_t section_length, rt_uint32_t total)
-{
- static rt_uint8_t* src_ptr;
- register rt_uint32_t buf_remain, section_remain;
- static rt_uint32_t section_read = 0, buf_offset = 0, frame_read = 0;
-
- if(ptr == RT_NULL)
- {
- /* Reset our state variables ready for the next read from this buffer. */
- src_ptr = (rt_uint8_t *)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK);
- frame_read = (rt_uint32_t)0;
- buf_offset = (rt_uint32_t)0;
- }
- else
- {
- /* Loop until we have obtained the required amount of data. */
- section_read = 0;
- while( section_read < section_length )
- {
- buf_remain = (ETH_RX_BUF_SIZE - buf_offset);
- section_remain = section_length - section_read;
-
- if( section_remain > buf_remain )
- {
- /* more data on section than buffer size */
- rt_memcpy(&ptr[ section_read ], &src_ptr[buf_offset], buf_remain);
- section_read += buf_remain;
- frame_read += buf_remain;
-
- /* free buffer */
- rb_descriptors[current_rb_index].addr &= ~RxDESC_FLAG_OWNSHIP;
-
- /* move to the next frame. */
- current_rb_index++;
- if(current_rb_index >= RB_BUFFER_SIZE) current_rb_index = 0;
-
- /* Reset the variables for the new buffer. */
- src_ptr = (rt_uint8_t *)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK);
- buf_offset = 0;
- }
- else
- {
- /* more data on buffer than section size */
- rt_memcpy(&ptr[section_read], &src_ptr[buf_offset], section_remain);
- buf_offset += section_remain;
- section_read += section_remain;
- frame_read += section_remain;
-
- /* finish this read */
- if((buf_offset >= ETH_RX_BUF_SIZE) || (frame_read >= total))
- {
- /* free buffer */
- rb_descriptors[current_rb_index].addr &= ~(RxDESC_FLAG_OWNSHIP);
-
- /* move to the next frame. */
- current_rb_index++;
- if( current_rb_index >= RB_BUFFER_SIZE ) current_rb_index = 0;
-
- src_ptr = (rt_uint8_t*)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK);
- buf_offset = 0;
- }
- }
- }
- }
-}
-
-struct pbuf *sam7xether_rx(rt_device_t dev)
-{
- struct pbuf *p = RT_NULL;
-
- /* skip fragment frame */
- while((rb_descriptors[current_rb_index].addr & RxDESC_FLAG_OWNSHIP)
- && !(rb_descriptors[current_rb_index].status & RxDESC_STATUS_FRAME_START))
- {
- rb_descriptors[current_rb_index].addr &= (~RxDESC_FLAG_OWNSHIP);
-
- current_rb_index++;
- if(current_rb_index >= RB_BUFFER_SIZE) current_rb_index = 0;
- }
-
- if ((rb_descriptors[current_rb_index].addr & RxDESC_FLAG_OWNSHIP))
- {
- struct pbuf* q;
- rt_uint32_t index, pkt_len = 0;
-
- /* first of all, find the frame length */
- index = current_rb_index;
- while (rb_descriptors[index].addr & RxDESC_FLAG_OWNSHIP)
- {
- pkt_len = rb_descriptors[index].status & RxDESC_STATUS_BUF_SIZE;
- if (pkt_len > 0) break;
-
- index ++;
- if (index >= RB_BUFFER_SIZE) index = 0;
- }
-
- if (pkt_len)
- {
- //p = pbuf_alloc(PBUF_LINK, pkt_len, PBUF_RAM);
- p = pbuf_alloc(PBUF_RAW, pkt_len, PBUF_POOL);
- if(p != RT_NULL)
- {
- sam7xether_read_frame(RT_NULL, 0, pkt_len);
- for(q = p; q != RT_NULL; q= q->next)
- sam7xether_read_frame(q->payload, q->len, pkt_len);
- }
- else
- {
- rt_kprintf("no memory in pbuf\n");
- }
- }
- }
-
- /* enable interrupt */
- AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
-
- return p;
-}
+#include <rthw.h> +#include <rtthread.h> +#include <netif/ethernetif.h> -int sam7xether_register(char *name)
-{
- rt_err_t result;
-
- /* init rt-thread device interface */
- sam7x_dev_entry.parent.parent.init = sam7xether_init;
- sam7x_dev_entry.parent.parent.open = sam7xether_open;
- sam7x_dev_entry.parent.parent.close = sam7xether_close;
- sam7x_dev_entry.parent.parent.read = sam7xether_read;
- sam7x_dev_entry.parent.parent.write = sam7xether_write;
- sam7x_dev_entry.parent.parent.control = sam7xether_control;
- sam7x_dev_entry.parent.eth_rx = sam7xether_rx;
- sam7x_dev_entry.parent.eth_tx = sam7xether_tx;
-
- /* Update MAC address */
- sam7x_dev_entry.dev_addr[0] = 0x1e;
- sam7x_dev_entry.dev_addr[1] = 0x30;
- sam7x_dev_entry.dev_addr[2] = 0x6c;
- sam7x_dev_entry.dev_addr[3] = 0xa2;
- sam7x_dev_entry.dev_addr[4] = 0x45;
- sam7x_dev_entry.dev_addr[5] = 0x5e;
- /* update mac address */
- update_mac_address(sam7x_dev);
-
- rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO);
-
- result = eth_device_init(&(sam7x_dev->parent), (char*)name);
- RT_ASSERT(result == RT_EOK);
-
- return RT_EOK;
-}
+#include "sam7x_emac.h" +#include "AT91SAM7X256.h" +#include "lwipopts.h" +#include "lwip/mem.h" + +#define MAX_ADDR_LEN 6 + +#ifdef DM9161 +#define EMAC_PIO_CFG (AT91C_PB8_EMDC | \ + AT91C_PB9_EMDIO | \ + AT91C_PB2_ETX0 | \ + AT91C_PB3_ETX1 | \ + AT91C_PB10_ETX2 | \ + AT91C_PB11_ETX3 | \ + AT91C_PB1_ETXEN | \ + AT91C_PB0_ETXCK_EREFCK | \ + AT91C_PB15_ERXDV_ECRSDV | \ + AT91C_PB5_ERX0 | \ + AT91C_PB6_ERX1 | \ + AT91C_PB12_ETXER | \ + AT91C_PB13_ERX2 | \ + AT91C_PB14_ERX3 | \ + AT91C_PB17_ERXCK | \ + AT91C_PB16_ECOL | \ + AT91C_PB4_ECRS | \ + AT91C_PB7_ERXER) +#else +#define EMAC_PIO_CFG (AT91C_PB0_ETXCK_EREFCK | \ + AT91C_PB1_ETXEN | \ + AT91C_PB2_ETX0 | \ + AT91C_PB3_ETX1 | \ + AT91C_PB4_ECRS | \ + AT91C_PB5_ERX0 | \ + AT91C_PB6_ERX1 | \ + AT91C_PB7_ERXER | \ + AT91C_PB8_EMDC | \ + AT91C_PB9_EMDIO | \ + AT91C_PB10_ETX2 | \ + AT91C_PB11_ETX3 | \ + AT91C_PB10_ETX2 | \ + AT91C_PB13_ERX2 | \ + AT91C_PB14_ERX3 | \ + AT91C_PB15_ERXDV_ECRSDV| \ + AT91C_PB16_ECOL | \ + AT91C_PB17_ERXCK) +#endif + +#define RB_BUFFER_SIZE 8 /* max number of receive buffers */ +#define ETH_RX_BUF_SIZE 128 + +#define TB_BUFFER_SIZE 4 +#define ETH_TX_BUF_SIZE (PBUF_POOL_BUFSIZE) + +struct rbf_t +{ + rt_uint32_t addr; + rt_uint32_t status; +}; + +static rt_uint32_t current_rb_index; /* current receive buffer index */ +static volatile struct rbf_t rb_descriptors[RB_BUFFER_SIZE]; +static volatile struct rbf_t tb_descriptors[TB_BUFFER_SIZE]; +static rt_uint8_t rx_buf[RB_BUFFER_SIZE][ETH_RX_BUF_SIZE] __attribute__ ((aligned (8))); +static rt_uint8_t tx_buf[TB_BUFFER_SIZE][ETH_TX_BUF_SIZE] __attribute__ ((aligned (8))); +static struct rt_semaphore tx_sem; + +struct net_device +{ + /* inherit from ethernet device */ + struct eth_device parent; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ +}; +static struct net_device sam7x_dev_entry; +static struct net_device *sam7x_dev =&sam7x_dev_entry; +AT91PS_EMAC pEmac = AT91C_BASE_EMAC; + +rt_inline void write_phy(rt_uint8_t addr, rt_uint32_t value) +{ + AT91C_BASE_EMAC->EMAC_MAN = ((0x01<<30) | (2 << 16) | (1 << 28) | + (AT91C_PHY_ADDR << 23) | (addr << 18)) | value; + /* Wait until IDLE bit in Network Status register is cleared */ + while (!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)); +} + +rt_inline rt_uint32_t read_phy(rt_uint8_t addr) +{ + AT91C_BASE_EMAC->EMAC_MAN = (0x01<<30) | (0x02 << 16) | (0x02 << 28) | + (AT91C_PHY_ADDR << 23) | (addr << 18); + + /* Wait until IDLE bit in Network Status register is cleared */ + while (!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)); + + return (AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff); +} + +rt_inline void sam7xether_reset_tx_desc(void) +{ + static rt_uint32_t index = 0; + + if(tb_descriptors[index].status & TxDESC_STATUS_USED) + { + while(!(tb_descriptors[index].status & TxDESC_STATUS_LAST_BUF)) + { + index ++; + if(index >= TB_BUFFER_SIZE)index = 0; + + tb_descriptors[index].status |= TxDESC_STATUS_USED; + } + + index ++; + if(index >= TB_BUFFER_SIZE)index = 0; + } +} + + +/* interrupt service routing */ +static void sam7xether_isr(int irq) +{ + /* Variable definitions can be made now. */ + volatile rt_uint32_t isr, rsr; + + /* get status */ + isr = AT91C_BASE_EMAC->EMAC_ISR; + rsr = AT91C_BASE_EMAC->EMAC_RSR; + + if( ( isr & AT91C_EMAC_RCOMP ) || ( rsr & AT91C_EMAC_REC ) ) + { + rt_err_t result; + + /* a frame has been received */ + result = eth_device_ready((struct eth_device*)&(sam7x_dev->parent)); + RT_ASSERT(result == RT_EOK); + + AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC; + } + + if( isr & AT91C_EMAC_TCOMP ) + { + /* A frame has been transmitted. Mark all the buffers as free */ + sam7xether_reset_tx_desc(); + + AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP; + } +} + +rt_inline void linksetup(void) +{ + rt_uint32_t value, tout, id1, id2; +#ifdef DM9161 + rt_uint32_t ulBMSR,ulBMCR,i; +#endif + +#ifdef DM9161 + //PHY has internal pull down : disable MII isolate + tout = read_phy(PHY_REG_BMCR); + tout = read_phy(PHY_REG_BMCR); + tout &= ~BMCR_ISOLATE; + write_phy(PHY_REG_BMCR, tout); + + /* Check if this is a RTL8201 or DM9161 PHY. */ + id1 = read_phy(PHY_REG_PHYID1); + id2 = read_phy(PHY_REG_PHYID2); + + if (((id1 << 16) | (id2 & 0xfff0)) == MII_DM9161_ID) + { + rt_kprintf("read MII_DM9161_ID ok!\n"); + + tout = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | + DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; + write_phy(PHY_REG_ANAR, tout); + // Wait for PHY auto negotiation completed + i = 0; + do { + ulBMSR = read_phy(PHY_REG_BMSR); + ulBMSR = read_phy(PHY_REG_BMSR); + i++; + + if(i >= 0xffff) + break; + }while (!(ulBMSR & BMSR_ANEGCOMPLETE)); + + if(i >= 0xffff) + rt_kprintf("PHY No Link!\n"); + else + rt_kprintf("PHY auto negotiation completed!\n"); + + /* Update the MAC register NCFGR. */ + AT91C_BASE_EMAC->EMAC_NCFGR = 0; + ulBMCR = read_phy(PHY_REG_BMCR); + + if (ulBMCR & BMCR_ANENABLE) + { + /* AutoNegotiation is enabled. */ + if(!(ulBMSR & BMSR_ANEGCOMPLETE)) + { + /* Auto-negotitation in progress. */ + rt_kprintf("Auto-negotitation in progress!\n"); + return; + } + + if (ulBMCR & BMCR_SPEED100) + { + /* Speed 100Mbit is enabled. */ + AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD; + + } + if (ulBMCR & BMCR_FULLDPLX) + { + /* Full duplex is enabled. */ + AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD; + } + } + } +#else + /* Check if this is a RTL8201 or DM9161 PHY. */ + id1 = read_phy(PHY_REG_PHYID1); + id2 = read_phy(PHY_REG_PHYID2); + + if (((id2 << 16) | (id1 & 0xfff0)) == MII_RTL8201_ID) + { + rt_kprintf("read MII_RTL8201_ID ok!\n"); + + + /* Configure the PHY device */ + /* Use autonegotiation about the link speed. */ + write_phy (PHY_REG_BMCR, PHY_AUTO_NEG); + + /* Wait to complete Auto_Negotiation. */ + for (tout = 0; tout < 0x100000; tout++) + { + value = read_phy (PHY_REG_BMSR); + if (value & BMSR_ANEGCOMPLETE) break; /* autonegotiation finished. */ + } + + /* Check the link status. */ + for (tout = 0; tout < 0x10000; tout++) + { + value = read_phy (PHY_REG_BMSR); + if (value & BMSR_LINKST) break; /* Link is on. */ + } + } + value = read_phy (PHY_REG_ANLPAR); + + /* Update the MAC register NCFGR. */ + AT91C_BASE_EMAC->EMAC_NCFGR &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + + /* set full duplex . */ + if (value & 0xA000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD; + /* set speed */ + if (value & 0xC000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD; + #endif +} + +/* + * Set the MAC address. + */ +rt_inline void update_mac_address(struct net_device* device) +{ + AT91C_BASE_EMAC->EMAC_SA1L = (device->dev_addr[3] << 24) | + (device->dev_addr[2] << 16) | + (device->dev_addr[1] << 8) | + device->dev_addr[0]; + AT91C_BASE_EMAC->EMAC_SA1H = (device->dev_addr[5] << 8) | + device->dev_addr[4]; +} + +rt_inline void sam7xether_desc_init() +{ + rt_uint32_t i; + + /* Rx Buffer Descriptor initialization */ + current_rb_index = 0; + for (i = 0; i < RB_BUFFER_SIZE; i++) + { + rb_descriptors[i].addr = (rt_uint32_t)&(rx_buf[i][0]); + rb_descriptors[i].status = 0; + } + /* Set the WRAP bit at the end of the list descriptor. */ + rb_descriptors[RB_BUFFER_SIZE-1].addr |= 0x02; + /* Set Rx Queue pointer to descriptor list. */ + AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int)&(rb_descriptors[0]); + + /* Tx Buffer Descriptor initialization */ + for (i = 0; i < TB_BUFFER_SIZE; i++) + { + tb_descriptors[i].addr = (rt_uint32_t)&(tx_buf[i][0]); + tb_descriptors[i].status = TxDESC_STATUS_USED; + } + /* Set the WRAP bit at the end of the list descriptor. */ + tb_descriptors[TB_BUFFER_SIZE-1].status |= TxDESC_STATUS_WRAP; + /* Set Tx Queue pointer to descriptor list. */ + AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int)&(tb_descriptors[0]); +} + +/* RT-Thread Device Interface */ + +/* initialize the interface */ +rt_err_t sam7xether_init(rt_device_t dev) +{ + rt_uint32_t i; + + /* enable peripheral clock for EMAC and PIO B */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB | 1 << AT91C_ID_EMAC; + + /* Disable pull up on RXDV => PHY normal mode (not in test mode), */ + /* and set MII mode. PHY has internal pull down. */ + AT91C_BASE_PIOB->PIO_PPUDR = (1<<16) | (1 << 15); + + /* Clear PB18 <=> PHY powerdown */ + AT91C_BASE_PIOB->PIO_PER = 1<<18; + AT91C_BASE_PIOB->PIO_OER = 1<<18; + AT91C_BASE_PIOB->PIO_CODR = 1<<18; + + /* EMAC IO init for EMAC-PHY communication. */ + AT91C_BASE_PIOB->PIO_ASR = EMAC_PIO_CFG; + AT91C_BASE_PIOB->PIO_PDR = EMAC_PIO_CFG; // Set in Periph mode + + /* Enable communication between EMAC-PHY. */ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; + /* MDC = MCK/32 */ + AT91C_BASE_EMAC->EMAC_NCFGR |= 2<<10; + + /* Reset PHY */ + AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB7_ERXER; + + AT91C_BASE_RSTC->RSTC_RMR = 0xA5000000 | (0x08 << 8) ; + AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST; + + i = 0; + while(!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)) + { + i++; + if(i >= 0xfffff) + break; + } + + for(i=0; i<0xfffff; i++);//* �ȴ�һ��ָ����ʱ�䣬ʹPHY���� + + linksetup(); + + rt_kprintf("linksetup ok!\n"); + + /* Disable management port in MAC control register. */ + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + + /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK */ + AT91C_BASE_EMAC->EMAC_USRIO= AT91C_EMAC_CLKEN; + + /* Transmit and Receive disable. */ + AT91C_BASE_EMAC->EMAC_NCR &= ~(AT91C_EMAC_RE | AT91C_EMAC_TE); + + /* init descriptor */ + sam7xether_desc_init(); + + /* Clear receive and transmit status registers. */ + AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); + AT91C_BASE_EMAC->EMAC_TSR = (AT91C_EMAC_UND | AT91C_EMAC_COMP| AT91C_EMAC_BEX | + AT91C_EMAC_RLES| AT91C_EMAC_COL | AT91C_EMAC_UBR); + + /* Configure EMAC operation mode. */ + //AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_BIG | AT91C_EMAC_DRFCS); + // ����������Ч֡�����ջ����� *������FCS�ֶ� �����չ㲥֡ ������1526�ֽڳ�֡ + AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF |AT91C_EMAC_DRFCS | AT91C_EMAC_NBC | AT91C_EMAC_BIG; + AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT); + + /* update MAC address */ + update_mac_address(sam7x_dev); + + /* enable interrupt */ + AT91C_BASE_EMAC->EMAC_IDR = 0x3fff; + AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP; + + /* setup interrupt */ + rt_hw_interrupt_install(AT91C_ID_EMAC, sam7xether_isr, RT_NULL); + *(volatile unsigned int*)(0xFFFFF000 + AT91C_ID_EMAC * 4) = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5; + // AT91C_AIC_SMR(AT91C_ID_EMAC) = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5; + rt_hw_interrupt_umask(AT91C_ID_EMAC); + + return RT_EOK; +} + +/* control the interface */ +rt_err_t sam7xether_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, sam7x_dev_entry.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* Open the ethernet interface */ +rt_err_t sam7xether_open(rt_device_t dev, rt_uint16_t oflags) +{ + return RT_EOK; +} + +/* Close the interface */ +rt_err_t sam7xether_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* Read */ +rt_size_t sam7xether_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +/* Write */ +rt_size_t sam7xether_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +/* See the header file for descriptions of public functions. */ +void sam7xether_write_frame(rt_uint8_t *ptr, rt_uint32_t length, rt_bool_t eof) +{ + rt_uint8_t *buf_ptr; + static rt_uint32_t current_tb_index = 0; + rt_uint32_t is_last, tx_offset = 0, remain, pdu_length; + + while(tx_offset < length) + { + /* check whether buffer is available */ + while(!(tb_descriptors[current_tb_index].status & TxDESC_STATUS_USED)) + { + /* no buffer */ + rt_thread_delay(5); + } + + /* Get the address of the buffer from the descriptor, then copy + the data into the buffer. */ + buf_ptr = (rt_uint8_t *)tb_descriptors[current_tb_index].addr; + + /* How much can we write to the buffer? */ + remain = length - tx_offset; + pdu_length = (remain <= ETH_TX_BUF_SIZE)? remain : ETH_TX_BUF_SIZE; + + /* Copy the data into the buffer. */ + rt_memcpy(buf_ptr, &ptr[tx_offset], pdu_length ); + tx_offset += pdu_length; + + /* Is this the last data for the frame? */ + if((eof == RT_TRUE) && ( tx_offset >= length )) is_last = TxDESC_STATUS_LAST_BUF; + else is_last = 0; + + /* Fill out the necessary in the descriptor to get the data sent, + then move to the next descriptor, wrapping if necessary. */ + if(current_tb_index >= (TB_BUFFER_SIZE - 1)) + { + tb_descriptors[current_tb_index].status = ( pdu_length & TxDESC_STATUS_BUF_SIZE ) + | is_last + | TxDESC_STATUS_WRAP; + current_tb_index = 0; + } + else + { + tb_descriptors[current_tb_index].status = ( pdu_length & TxDESC_STATUS_BUF_SIZE ) + | is_last; + current_tb_index++; + } + + /* If this is the last buffer to be sent for this frame we can + start the transmission. */ + if(is_last) + { + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART; + } + } +} + +/* ethernet device interface */ +/* + * Transmit packet. + */ +rt_err_t sam7xether_tx( rt_device_t dev, struct pbuf* p) +{ + struct pbuf* q; + + /* lock tx operation */ + rt_sem_take(&tx_sem, RT_WAITING_FOREVER); + + for (q = p; q != NULL; q = q->next) + { + if (q->next == RT_NULL) sam7xether_write_frame(q->payload, q->len, RT_TRUE); + else sam7xether_write_frame(q->payload, q->len, RT_FALSE); + } + + rt_sem_release(&tx_sem); + + return 0; +} + +void sam7xether_read_frame(rt_uint8_t* ptr, rt_uint32_t section_length, rt_uint32_t total) +{ + static rt_uint8_t* src_ptr; + register rt_uint32_t buf_remain, section_remain; + static rt_uint32_t section_read = 0, buf_offset = 0, frame_read = 0; + + if(ptr == RT_NULL) + { + /* Reset our state variables ready for the next read from this buffer. */ + src_ptr = (rt_uint8_t *)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK); + frame_read = (rt_uint32_t)0; + buf_offset = (rt_uint32_t)0; + } + else + { + /* Loop until we have obtained the required amount of data. */ + section_read = 0; + while( section_read < section_length ) + { + buf_remain = (ETH_RX_BUF_SIZE - buf_offset); + section_remain = section_length - section_read; + + if( section_remain > buf_remain ) + { + /* more data on section than buffer size */ + rt_memcpy(&ptr[ section_read ], &src_ptr[buf_offset], buf_remain); + section_read += buf_remain; + frame_read += buf_remain; + + /* free buffer */ + rb_descriptors[current_rb_index].addr &= ~RxDESC_FLAG_OWNSHIP; + + /* move to the next frame. */ + current_rb_index++; + if(current_rb_index >= RB_BUFFER_SIZE) current_rb_index = 0; + + /* Reset the variables for the new buffer. */ + src_ptr = (rt_uint8_t *)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK); + buf_offset = 0; + } + else + { + /* more data on buffer than section size */ + rt_memcpy(&ptr[section_read], &src_ptr[buf_offset], section_remain); + buf_offset += section_remain; + section_read += section_remain; + frame_read += section_remain; + + /* finish this read */ + if((buf_offset >= ETH_RX_BUF_SIZE) || (frame_read >= total)) + { + /* free buffer */ + rb_descriptors[current_rb_index].addr &= ~(RxDESC_FLAG_OWNSHIP); + + /* move to the next frame. */ + current_rb_index++; + if( current_rb_index >= RB_BUFFER_SIZE ) current_rb_index = 0; + + src_ptr = (rt_uint8_t*)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK); + buf_offset = 0; + } + } + } + } +} + +struct pbuf *sam7xether_rx(rt_device_t dev) +{ + struct pbuf *p = RT_NULL; + + /* skip fragment frame */ + while((rb_descriptors[current_rb_index].addr & RxDESC_FLAG_OWNSHIP) + && !(rb_descriptors[current_rb_index].status & RxDESC_STATUS_FRAME_START)) + { + rb_descriptors[current_rb_index].addr &= (~RxDESC_FLAG_OWNSHIP); + + current_rb_index++; + if(current_rb_index >= RB_BUFFER_SIZE) current_rb_index = 0; + } + + if ((rb_descriptors[current_rb_index].addr & RxDESC_FLAG_OWNSHIP)) + { + struct pbuf* q; + rt_uint32_t index, pkt_len = 0; + + /* first of all, find the frame length */ + index = current_rb_index; + while (rb_descriptors[index].addr & RxDESC_FLAG_OWNSHIP) + { + pkt_len = rb_descriptors[index].status & RxDESC_STATUS_BUF_SIZE; + if (pkt_len > 0) break; + + index ++; + if (index >= RB_BUFFER_SIZE) index = 0; + } + + if (pkt_len) + { + //p = pbuf_alloc(PBUF_LINK, pkt_len, PBUF_RAM); + p = pbuf_alloc(PBUF_RAW, pkt_len, PBUF_POOL); + if(p != RT_NULL) + { + sam7xether_read_frame(RT_NULL, 0, pkt_len); + for(q = p; q != RT_NULL; q= q->next) + sam7xether_read_frame(q->payload, q->len, pkt_len); + } + else + { + rt_kprintf("no memory in pbuf\n"); + } + } + } + + /* enable interrupt */ + AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP; + + return p; +} + +int sam7xether_register(char *name) +{ + rt_err_t result; + + /* init rt-thread device interface */ + sam7x_dev_entry.parent.parent.init = sam7xether_init; + sam7x_dev_entry.parent.parent.open = sam7xether_open; + sam7x_dev_entry.parent.parent.close = sam7xether_close; + sam7x_dev_entry.parent.parent.read = sam7xether_read; + sam7x_dev_entry.parent.parent.write = sam7xether_write; + sam7x_dev_entry.parent.parent.control = sam7xether_control; + sam7x_dev_entry.parent.eth_rx = sam7xether_rx; + sam7x_dev_entry.parent.eth_tx = sam7xether_tx; + + /* Update MAC address */ + sam7x_dev_entry.dev_addr[0] = 0x1e; + sam7x_dev_entry.dev_addr[1] = 0x30; + sam7x_dev_entry.dev_addr[2] = 0x6c; + sam7x_dev_entry.dev_addr[3] = 0xa2; + sam7x_dev_entry.dev_addr[4] = 0x45; + sam7x_dev_entry.dev_addr[5] = 0x5e; + /* update mac address */ + update_mac_address(sam7x_dev); + + rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO); + + result = eth_device_init(&(sam7x_dev->parent), (char*)name); + RT_ASSERT(result == RT_EOK); + + return RT_EOK; +} diff --git a/bsp/sam7x/drivers/sam7x_emac.h b/bsp/sam7x/drivers/sam7x_emac.h index ff9102ae4e..f1d0deff16 100644 --- a/bsp/sam7x/drivers/sam7x_emac.h +++ b/bsp/sam7x/drivers/sam7x_emac.h @@ -1,109 +1,109 @@ -#ifndef __SAM7X_EMAC_H__
-#define __SAM7X_EMAC_H__
-
-//#define DM9161
-#define RTL8201
-
-#ifdef DM9161
- #define AT91C_PHY_ADDR 31
-#else
-#define AT91C_PHY_ADDR 0x01
-#endif
-
-#define MII_DM9161_ID 0x0181b8a0
-#define MII_RTL8201_ID 0x82010000
-
-/* RTL8201 PHY registers. */
-#define PHY_REG_BMCR 0x00 /* Basic mode control register */
-#define PHY_REG_BMSR 0x01 /* Basic mode status register */
-#define PHY_REG_PHYID1 0x02 /* PHY ID identifier #1 */
-#define PHY_REG_PHYID2 0x03 /* PHY ID identifier #2 */
-#define PHY_REG_ANAR 0x04 /* AutoNegotiation Advertisement reg.*/
-#define PHY_REG_ANLPAR 0x05 /* AutoNeg.Link partner ability reg */
-#define PHY_REG_ANER 0x06 /* AutoNeg. Expansion register */
-#define PHY_REG_DSCR 0x10 /* DAVICOM Specified Config. reg */
-#define PHY_REG_DSCSR 0x11 /* DAVICOM Spec. Config/Status reg */
-#define PHY_REG_10BTCSR 0x12 /* 10BASET Configuration/Status reg */
-#define PHY_REG_PWDOR 0x13 /* Power Down Control Register */
-#define PHY_REG_SCR 0x14 /* Specified Config register */
-#define PHY_REG_INTR 0x15 /* Interrupt register */
-#define PHY_REG_RECR 0x16 /* Receive Error Counter register */
-#define PHY_REG_DISCR 0x17 /* Disconnect Counter register */
-#define PHY_REG_RLSR 0x18 /* Hardware Reset Latch State reg. */
-
-/* Basic mode control register. */
-#define BMCR_RESV 0x007f /* Unused... */
-#define BMCR_CTST 0x0080 /* Collision test */
-#define BMCR_FULLDPLX 0x0100 /* Full duplex */
-#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
-#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
-#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
-#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
-#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
-#define BMCR_RESET 0x8000 /* Reset the DP83840 */
-
-#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
-#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
-#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
-#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
-#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
-
-/* Basic mode status register. */
-#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
-#define BMSR_JCD 0x0002 /* Jabber detected */
-#define BMSR_LINKST 0x0004 /* Link status */
-#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
-#define BMSR_RFAULT 0x0010 /* Remote fault detected */
-#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
-#define BMSR_MIIPRESUP 0x0040 /* MII Frame Preamble Suppression */
-#define BMSR_RESV 0x0780 /* Unused... */
-#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
-#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
-#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
-
-#define RxDESC_FLAG_ADDR_MASK 0xfffffffc
-#define RxDESC_FLAG_WARP 0x00000002
-#define RxDESC_FLAG_OWNSHIP 0x00000001
-#define RxDESC_STATUS_BUF_SIZE (0x00000FFF)
-#define RxDESC_STATUS_FRAME_START (1U << 14)
-#define RxDESC_STATUS_FRAME_END (1U << 15)
-
-#define TxDESC_STATUS_BUF_SIZE (0x000007FF)
-#define TxDESC_STATUS_LAST_BUF (1U << 15)
-#define TxDESC_STATUS_NO_CRC (1U << 16)
-#define TxDESC_STATUS_BUF_EXHAUSTED (1U << 27)
-#define TxDESC_STATUS_Tx_UNDERRUN (1U << 28)
-#define TxDESC_STATUS_Tx_ERROR (1U << 29)
-#define TxDESC_STATUS_WRAP (1U << 30)
-#define TxDESC_STATUS_USED (1U << 31)
-
-//----dm9161 define----
-#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
-#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
-#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
-#define DM9161_AUTONEG (1 << 12) // Auto-negotiation Enable
-#define DM9161_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
-#define DM9161_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
-#define DM9161_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
-#define DM9161_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
-#define DM9161_COLLISION_TEST (1 << 7) // 1 = Collision test enabled 0 = Normal operation
-
-#define DM9161_NP (1 << 15) // Next page Indication
-#define DM9161_ACK (1 << 14) // Acknowledge
-#define DM9161_RF (1 << 13) // Remote Fault
-// Reserved 12 to 11 // Write as 0, ignore on read
-#define DM9161_FCS (1 << 10) // Flow Control Support
-#define DM9161_T4 (1 << 9) // 100BASE-T4 Support
-#define DM9161_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
-#define DM9161_TX_HDX (1 << 7) // 100BASE-TX Support
-#define DM9161_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
-#define DM9161_10_HDX (1 << 5) // 10BASE-T Support
-// Selector 4 to 0 // Protocol Selection Bits
-#define DM9161_AN_IEEE_802_3 0x0001
-
-int sam7xether_register(char *name);
-
-#endif
+#ifndef __SAM7X_EMAC_H__ +#define __SAM7X_EMAC_H__ + +//#define DM9161 +#define RTL8201 + +#ifdef DM9161 + #define AT91C_PHY_ADDR 31 +#else +#define AT91C_PHY_ADDR 0x01 +#endif + +#define MII_DM9161_ID 0x0181b8a0 +#define MII_RTL8201_ID 0x82010000 + +/* RTL8201 PHY registers. */ +#define PHY_REG_BMCR 0x00 /* Basic mode control register */ +#define PHY_REG_BMSR 0x01 /* Basic mode status register */ +#define PHY_REG_PHYID1 0x02 /* PHY ID identifier #1 */ +#define PHY_REG_PHYID2 0x03 /* PHY ID identifier #2 */ +#define PHY_REG_ANAR 0x04 /* AutoNegotiation Advertisement reg.*/ +#define PHY_REG_ANLPAR 0x05 /* AutoNeg.Link partner ability reg */ +#define PHY_REG_ANER 0x06 /* AutoNeg. Expansion register */ +#define PHY_REG_DSCR 0x10 /* DAVICOM Specified Config. reg */ +#define PHY_REG_DSCSR 0x11 /* DAVICOM Spec. Config/Status reg */ +#define PHY_REG_10BTCSR 0x12 /* 10BASET Configuration/Status reg */ +#define PHY_REG_PWDOR 0x13 /* Power Down Control Register */ +#define PHY_REG_SCR 0x14 /* Specified Config register */ +#define PHY_REG_INTR 0x15 /* Interrupt register */ +#define PHY_REG_RECR 0x16 /* Receive Error Counter register */ +#define PHY_REG_DISCR 0x17 /* Disconnect Counter register */ +#define PHY_REG_RLSR 0x18 /* Hardware Reset Latch State reg. */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x007f /* Unused... */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LINKST 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_MIIPRESUP 0x0040 /* MII Frame Preamble Suppression */ +#define BMSR_RESV 0x0780 /* Unused... */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +#define RxDESC_FLAG_ADDR_MASK 0xfffffffc +#define RxDESC_FLAG_WARP 0x00000002 +#define RxDESC_FLAG_OWNSHIP 0x00000001 +#define RxDESC_STATUS_BUF_SIZE (0x00000FFF) +#define RxDESC_STATUS_FRAME_START (1U << 14) +#define RxDESC_STATUS_FRAME_END (1U << 15) + +#define TxDESC_STATUS_BUF_SIZE (0x000007FF) +#define TxDESC_STATUS_LAST_BUF (1U << 15) +#define TxDESC_STATUS_NO_CRC (1U << 16) +#define TxDESC_STATUS_BUF_EXHAUSTED (1U << 27) +#define TxDESC_STATUS_Tx_UNDERRUN (1U << 28) +#define TxDESC_STATUS_Tx_ERROR (1U << 29) +#define TxDESC_STATUS_WRAP (1U << 30) +#define TxDESC_STATUS_USED (1U << 31) + +//----dm9161 define---- +#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation +#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation +#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps +#define DM9161_AUTONEG (1 << 12) // Auto-negotiation Enable +#define DM9161_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation +#define DM9161_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation +#define DM9161_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation +#define DM9161_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation +#define DM9161_COLLISION_TEST (1 << 7) // 1 = Collision test enabled 0 = Normal operation + +#define DM9161_NP (1 << 15) // Next page Indication +#define DM9161_ACK (1 << 14) // Acknowledge +#define DM9161_RF (1 << 13) // Remote Fault +// Reserved 12 to 11 // Write as 0, ignore on read +#define DM9161_FCS (1 << 10) // Flow Control Support +#define DM9161_T4 (1 << 9) // 100BASE-T4 Support +#define DM9161_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support +#define DM9161_TX_HDX (1 << 7) // 100BASE-TX Support +#define DM9161_10_FDX (1 << 6) // 10BASE-T Full Duplex Support +#define DM9161_10_HDX (1 << 5) // 10BASE-T Support +// Selector 4 to 0 // Protocol Selection Bits +#define DM9161_AN_IEEE_802_3 0x0001 + +int sam7xether_register(char *name); + +#endif diff --git a/bsp/sam7x/drivers/sd.c b/bsp/sam7x/drivers/sd.c index ef955d44bc..22ee7f1259 100644 --- a/bsp/sam7x/drivers/sd.c +++ b/bsp/sam7x/drivers/sd.c @@ -1,662 +1,662 @@ -#include <rtthread.h>
-#include <dfs_fs.h>
-
-#include "sd.h"
-
-#include <AT91SAM7X.h>
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
-#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
-#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
-#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
-#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
-#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
-#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
-#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
-#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
-#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
-#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
-#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
-#define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
-#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
-#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
-#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
-#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
-#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
-#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
-#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
-#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
-#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
-#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
-#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
-#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
-#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
-#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
-#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
-#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
-#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
-#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
-#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
-#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
-#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-
-#define CARD_WP_PIN AT91C_PIO_PA16
-#define CARD_INS_PIN AT91C_PIO_PA15
-#define CARD_PWR_PIN AT91C_PIO_PA12
-
-typedef volatile unsigned int AT91S_REG;// Hardware register definition
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
- AT91S_REG SPI_CR; // Control Register
- AT91S_REG SPI_MR; // Mode Register
- AT91S_REG SPI_RDR; // Receive Data Register
- AT91S_REG SPI_TDR; // Transmit Data Register
- AT91S_REG SPI_SR; // Status Register
- AT91S_REG SPI_IER; // Interrupt Enable Register
- AT91S_REG SPI_IDR; // Interrupt Disable Register
- AT91S_REG SPI_IMR; // Interrupt Mask Register
- AT91S_REG Reserved0[4]; //
- AT91S_REG SPI_CSR[4]; // Chip Select Register
- AT91S_REG Reserved1[48]; //
- AT91S_REG SPI_RPR; // Receive Pointer Register
- AT91S_REG SPI_RCR; // Receive Counter Register
- AT91S_REG SPI_TPR; // Transmit Pointer Register
- AT91S_REG SPI_TCR; // Transmit Counter Register
- AT91S_REG SPI_RNPR; // Receive Next Pointer Register
- AT91S_REG SPI_RNCR; // Receive Next Counter Register
- AT91S_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91S_REG SPI_TNCR; // Transmit Next Counter Register
- AT91S_REG SPI_PTCR; // PDC Transfer Control Register
- AT91S_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-static AT91PS_SPI pSPI = ((AT91PS_SPI) 0xFFFE0000);
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-#define CARD_SELECT_PIN AT91C_PA13_SPI0_NPCS1
-#define SPI_CSR_NUM 0
-
-#define SPI_SCBR_MIN 2
-
-/* MMC/SD command (in SPI) */
-#define CMD0 (0x40+0) /* GO_IDLE_STATE */
-#define CMD1 (0x40+1) /* SEND_OP_COND */
-#define CMD9 (0x40+9) /* SEND_CSD */
-#define CMD10 (0x40+10) /* SEND_CID */
-#define CMD12 (0x40+12) /* STOP_TRANSMISSION */
-#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */
-#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */
-#define CMD24 (0x40+24) /* WRITE_BLOCK */
-#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */
-#define CMD58 (0x40+58) /* READ_OCR */
-
-/* Control signals (Platform dependent) */
-#define SELECT() (AT91C_PIOA_CODR = CARD_SELECT_PIN) /* MMC CS = L */
-#define DESELECT() (AT91C_PIOA_SODR = CARD_SELECT_PIN) /* MMC CS = H */
-
-#define SOCKWP CARD_WP_PIN /* Write protect switch (PB5) */
-#define SOCKINS CARD_INS_PIN /* Card detect switch (PB4) */
-
-#define POWER_ON() (AT91C_PIOA_CODR = CARD_PWR_PIN)
-#define POWER_OFF() (AT91C_PIOA_SODR = CARD_PWR_PIN)
-
-static struct rt_device sd;
-static struct dfs_partition part;
-
-static void AT91_spiSetSpeed(rt_uint8_t speed)
-{
- rt_uint32_t reg;
-
- if ( speed < SPI_SCBR_MIN ) speed = SPI_SCBR_MIN;
- if ( speed > 1 ) speed &= 0xFE;
-
- reg = pSPI->SPI_CSR[SPI_CSR_NUM];
- reg = ( reg & ~(AT91C_SPI_SCBR) ) | ( (rt_uint32_t)speed << 8 );
- pSPI->SPI_CSR[SPI_CSR_NUM] = reg;
-}
-
-static rt_uint8_t AT91_spi(rt_uint8_t outgoing)
-{
- rt_uint8_t incoming;
-
- while( !( pSPI->SPI_SR & AT91C_SPI_TDRE ) ); // transfer compl. wait
- pSPI->SPI_TDR = (rt_uint16_t)( outgoing );
-
- while( !( pSPI->SPI_SR & AT91C_SPI_RDRF ) ); // wait for char
- incoming = (rt_uint8_t)( pSPI->SPI_RDR );
-
- return incoming;
-}
-
-/*--------------------------------*/
-/* Transmit a rt_uint8_t to MMC via SPI */
-/* (Platform dependent) */
-rt_inline void xmit_spi(rt_uint8_t dat)
-{
- AT91_spi(dat);
-}
-
-/*---------------------------------*/
-/* Receive a rt_uint8_t from MMC via SPI */
-/* (Platform dependent) */
-rt_inline rt_uint8_t rcvr_spi(void)
-{
- return AT91_spi(0xff);
-}
-
-/* Alternative "macro" (not at AT91 so far) to receive data fast */
-static void rcvr_spi_m(rt_uint8_t *dst)
-{
- *dst = rcvr_spi();
-}
-
-/*---------------------*/
-/* Wait for card ready */
-static rt_uint8_t wait_ready ()
-{
- rt_uint8_t res;
-
- rcvr_spi();
- do
- {
- res = rcvr_spi();
- } while ((res != 0xFF));
-
- return res;
-}
-
-/*--------------------------------*/
-/* Receive a data packet from MMC */
-
-rt_bool_t rcvr_datablock (rt_uint8_t *buff, rt_uint8_t wc)
-{
- rt_uint8_t token;
-
- {
- /* Wait for data packet in timeout of 100ms */
- token = rcvr_spi();
- }while ((token == 0xFF));
-
- if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */
-
- do
- {
- /* Receive the data block into buffer */
- rcvr_spi_m(buff++);
- rcvr_spi_m(buff++);
- } while (--wc);
-
- rcvr_spi(); /* Discard CRC */
- rcvr_spi();
-
- return RT_TRUE; /* Return with success */
-}
-
-/*---------------------------*/
-/* Send a data packet to MMC */
-static rt_bool_t xmit_datablock(const rt_uint8_t *buff, rt_uint8_t token)
-{
- rt_uint8_t resp, wc = 0;
-
- if (wait_ready() != 0xFF) return RT_FALSE;
-
- xmit_spi(token); /* Xmit data token */
- if (token != 0xFD)
- { /* Is data token */
- do
- {
- /* Xmit the 512 rt_uint8_t data block to MMC */
- xmit_spi(*buff++);
- xmit_spi(*buff++);
- } while (--wc);
-
- xmit_spi(0xFF); /* CRC (Dummy) */
- xmit_spi(0xFF);
- resp = rcvr_spi(); /* Reveive data response */
-
- if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */
- return RT_FALSE;
- }
-
- return RT_TRUE;
-}
-
-/*------------------------------*/
-/* Send a command packet to MMC */
-rt_uint8_t send_cmd (rt_uint8_t cmd, rt_uint32_t arg)
-{
- rt_uint8_t n, res;
-
- if (wait_ready() != 0xFF) return 0xFF;
-
- /* Send command packet */
- xmit_spi(cmd); /* Command */
- xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */
- xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */
- xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */
- xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */
- xmit_spi(0x95); /* CRC (valid for only CMD0) */
-
- /* Receive command response */
- if (cmd == CMD12) rcvr_spi(); /* Skip a stuff rt_uint8_t when stop reading */
- n = 10; /* Wait for a valid response in timeout of 10 attempts */
- do
- {
- res = rcvr_spi();
- }
- while ((res & 0x80) && --n);
-
- return res; /* Return with the response value */
-}
-
-static rt_err_t rt_sdcard_init(rt_device_t dev)
-{
- return RT_EOK;
-}
-
-static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
-{
- return RT_EOK;
-}
-
-static rt_err_t rt_sdcard_close(rt_device_t dev)
-{
- return RT_EOK;
-}
-
-static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t count;
-
- count = size / 512;
-
- /* CS = L */
- SELECT();
-
- /* append partition offset */
- pos += part.offset * 512;
-
- if (count == 1)
- { /* Single block read */
- if ((send_cmd(CMD17, pos) == 0) /* READ_SINGLE_BLOCK */
- && rcvr_datablock(buffer, (rt_uint8_t)(512/2)))
- count = 0;
- else
- count = 1;
- }
- else
- { /* Multiple block read */
- if (send_cmd(CMD18, pos) == 0)
- {
- rt_uint8_t* ptr;
-
- ptr = buffer;
- do
- {
- if (!rcvr_datablock(ptr, (rt_uint8_t)(512/2))) break;
- ptr += 512;
- } while (--count);
-
- send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
- }
- }
-
- DESELECT(); /* CS = H */
- rcvr_spi(); /* Idle (Release DO) */
-
- if (count)
- {
- // rt_set_errno(-RT_ERROR);
- return 0;
- }
-
- return size / 512;
-}
-
-static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- rt_uint8_t count;
-
- count = size / 512;
-
- /* CS = L */
- SELECT();
-
- /* append partition offset */
- pos += part.offset * 512;
-
- if (count == 1)
- {
- /* Single block write */
- if ((send_cmd(CMD24, pos) == 0) /* WRITE_BLOCK */
- && xmit_datablock(buffer, 0xFE))
- count = 0;
- else
- count = 1;
- }
- else
- {
- /* Multiple block write */
- if (send_cmd(CMD25, pos) == 0)
- {
- rt_uint8_t *ptr;
-
- ptr = (rt_uint8_t *)buffer;
- do
- {
- if (!xmit_datablock(ptr, 0xFC)) break;
- ptr += 512;
- } while (--count);
-
- if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */
- count = 1;
- }
- }
-
- DESELECT(); /* CS = H */
- rcvr_spi(); /* Idle (Release DO) */
-
- if (count)
- {
- rt_set_errno(-RT_ERROR);
- return 0;
- }
-
- return size;
-}
-
-static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- return RT_EOK;
-}
-
-void rt_hw_sdcard_init()
-{
- rt_uint32_t n;
- rt_uint8_t* sector;
-
- sd.type = RT_Device_Class_Block;
- sd.init = rt_sdcard_init;
- sd.open = rt_sdcard_open;
- sd.close = rt_sdcard_close;
- sd.read = rt_sdcard_read;
- sd.write = rt_sdcard_write;
- sd.control = rt_sdcard_control;
- sd.user_data = RT_NULL;
-
- AT91C_PIOA_PER = CARD_PWR_PIN; // enable GPIO of CS-pin
- AT91C_PIOA_CODR = CARD_PWR_PIN; // set high
- AT91C_PIOA_OER = CARD_PWR_PIN; // output enable
-
- for (n = 0; n < 3000; n ++) ;
-
- // disable PIO from controlling MOSI, MISO, SCK (=hand over to SPI)
- // keep CS untouched - used as GPIO pin during init
- AT91C_PIOA_PDR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; // | NCPS_PDR_BIT;
- // set pin-functions in PIO Controller
- AT91C_PIOA_ASR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; /// not here: | NCPS_ASR_BIT;
-
- // set chip-select as output high (unselect card)
- AT91C_PIOA_PER = CARD_SELECT_PIN; // enable GPIO of CS-pin
- AT91C_PIOA_SODR = CARD_SELECT_PIN; // set high
- AT91C_PIOA_OER = CARD_SELECT_PIN; // output enable
-
- // enable peripheral clock for SPI ( PID Bit 5 )
- AT91C_PMC_PCER = ( (rt_uint32_t) 1 << AT91C_ID_SPI0 ); // n.b. IDs are just bit-numbers
-
- // SPI enable and reset
- pSPI->SPI_CR = AT91C_SPI_SPIEN | AT91C_SPI_SWRST;
-
- // SPI mode: master, FDIV=0, fault detection disabled
- pSPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS;
-
- // set chip-select-register
- // 8 bits per transfer, CPOL=1, ClockPhase=0, DLYBCT = 0
- pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_CPOL | AT91C_SPI_BITS_8;
-
- // slow during init
- AT91_spiSetSpeed(0xFE);
-
- // enable
- pSPI->SPI_CR = AT91C_SPI_SPIEN;
-
- n = 10; /* Dummy clock */
- do
- {
- rcvr_spi();
- } while (--n);
-
- SELECT(); /* CS = L */
- if (send_cmd(CMD0, 0) == 1)
- {
- /* Enter Idle state */
- while (send_cmd(CMD1, 0));
- }
-
- DESELECT(); /* CS = H */
- rcvr_spi(); /* Idle (Release DO) */
-
- AT91_spiSetSpeed(SPI_SCBR_MIN);
-
- /* get the first sector to read partition table */
- sector = (rt_uint8_t*) rt_malloc (512);
- if (sector == RT_NULL)
- {
- rt_kprintf("allocate partition sector buffer failed\n");
- return;
- }
-
- n = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
- if (n == 512)
- {
- rt_err_t status;
-
- /* get the first partition */
- status = dfs_filesystem_get_partition(&part, sector, 0);
- if (status != RT_EOK)
- {
- /* there is no partition table */
- part.offset = 0;
- part.size = 0;
- }
- }
- else
- {
- /* there is no partition table */
- part.offset = 0;
- part.size = 0;
- }
-
- /* release sector buffer */
- rt_free(sector);
-
- /* register sd device */
- rt_device_register(&sd, "sd", RT_DEVICE_FLAG_RDWR);
-}
+#include <rtthread.h> +#include <dfs_fs.h> + +#include "sd.h" + +#include <AT91SAM7X.h> + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +#define CARD_WP_PIN AT91C_PIO_PA16 +#define CARD_INS_PIN AT91C_PIO_PA15 +#define CARD_PWR_PIN AT91C_PIO_PA12 + +typedef volatile unsigned int AT91S_REG;// Hardware register definition +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91S_REG SPI_CR; // Control Register + AT91S_REG SPI_MR; // Mode Register + AT91S_REG SPI_RDR; // Receive Data Register + AT91S_REG SPI_TDR; // Transmit Data Register + AT91S_REG SPI_SR; // Status Register + AT91S_REG SPI_IER; // Interrupt Enable Register + AT91S_REG SPI_IDR; // Interrupt Disable Register + AT91S_REG SPI_IMR; // Interrupt Mask Register + AT91S_REG Reserved0[4]; // + AT91S_REG SPI_CSR[4]; // Chip Select Register + AT91S_REG Reserved1[48]; // + AT91S_REG SPI_RPR; // Receive Pointer Register + AT91S_REG SPI_RCR; // Receive Counter Register + AT91S_REG SPI_TPR; // Transmit Pointer Register + AT91S_REG SPI_TCR; // Transmit Counter Register + AT91S_REG SPI_RNPR; // Receive Next Pointer Register + AT91S_REG SPI_RNCR; // Receive Next Counter Register + AT91S_REG SPI_TNPR; // Transmit Next Pointer Register + AT91S_REG SPI_TNCR; // Transmit Next Counter Register + AT91S_REG SPI_PTCR; // PDC Transfer Control Register + AT91S_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +static AT91PS_SPI pSPI = ((AT91PS_SPI) 0xFFFE0000); + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +#define CARD_SELECT_PIN AT91C_PA13_SPI0_NPCS1 +#define SPI_CSR_NUM 0 + +#define SPI_SCBR_MIN 2 + +/* MMC/SD command (in SPI) */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD58 (0x40+58) /* READ_OCR */ + +/* Control signals (Platform dependent) */ +#define SELECT() (AT91C_PIOA_CODR = CARD_SELECT_PIN) /* MMC CS = L */ +#define DESELECT() (AT91C_PIOA_SODR = CARD_SELECT_PIN) /* MMC CS = H */ + +#define SOCKWP CARD_WP_PIN /* Write protect switch (PB5) */ +#define SOCKINS CARD_INS_PIN /* Card detect switch (PB4) */ + +#define POWER_ON() (AT91C_PIOA_CODR = CARD_PWR_PIN) +#define POWER_OFF() (AT91C_PIOA_SODR = CARD_PWR_PIN) + +static struct rt_device sd; +static struct dfs_partition part; + +static void AT91_spiSetSpeed(rt_uint8_t speed) +{ + rt_uint32_t reg; + + if ( speed < SPI_SCBR_MIN ) speed = SPI_SCBR_MIN; + if ( speed > 1 ) speed &= 0xFE; + + reg = pSPI->SPI_CSR[SPI_CSR_NUM]; + reg = ( reg & ~(AT91C_SPI_SCBR) ) | ( (rt_uint32_t)speed << 8 ); + pSPI->SPI_CSR[SPI_CSR_NUM] = reg; +} + +static rt_uint8_t AT91_spi(rt_uint8_t outgoing) +{ + rt_uint8_t incoming; + + while( !( pSPI->SPI_SR & AT91C_SPI_TDRE ) ); // transfer compl. wait + pSPI->SPI_TDR = (rt_uint16_t)( outgoing ); + + while( !( pSPI->SPI_SR & AT91C_SPI_RDRF ) ); // wait for char + incoming = (rt_uint8_t)( pSPI->SPI_RDR ); + + return incoming; +} + +/*--------------------------------*/ +/* Transmit a rt_uint8_t to MMC via SPI */ +/* (Platform dependent) */ +rt_inline void xmit_spi(rt_uint8_t dat) +{ + AT91_spi(dat); +} + +/*---------------------------------*/ +/* Receive a rt_uint8_t from MMC via SPI */ +/* (Platform dependent) */ +rt_inline rt_uint8_t rcvr_spi(void) +{ + return AT91_spi(0xff); +} + +/* Alternative "macro" (not at AT91 so far) to receive data fast */ +static void rcvr_spi_m(rt_uint8_t *dst) +{ + *dst = rcvr_spi(); +} + +/*---------------------*/ +/* Wait for card ready */ +static rt_uint8_t wait_ready () +{ + rt_uint8_t res; + + rcvr_spi(); + do + { + res = rcvr_spi(); + } while ((res != 0xFF)); + + return res; +} + +/*--------------------------------*/ +/* Receive a data packet from MMC */ + +rt_bool_t rcvr_datablock (rt_uint8_t *buff, rt_uint8_t wc) +{ + rt_uint8_t token; + + { + /* Wait for data packet in timeout of 100ms */ + token = rcvr_spi(); + }while ((token == 0xFF)); + + if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */ + + do + { + /* Receive the data block into buffer */ + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + } while (--wc); + + rcvr_spi(); /* Discard CRC */ + rcvr_spi(); + + return RT_TRUE; /* Return with success */ +} + +/*---------------------------*/ +/* Send a data packet to MMC */ +static rt_bool_t xmit_datablock(const rt_uint8_t *buff, rt_uint8_t token) +{ + rt_uint8_t resp, wc = 0; + + if (wait_ready() != 0xFF) return RT_FALSE; + + xmit_spi(token); /* Xmit data token */ + if (token != 0xFD) + { /* Is data token */ + do + { + /* Xmit the 512 rt_uint8_t data block to MMC */ + xmit_spi(*buff++); + xmit_spi(*buff++); + } while (--wc); + + xmit_spi(0xFF); /* CRC (Dummy) */ + xmit_spi(0xFF); + resp = rcvr_spi(); /* Reveive data response */ + + if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ + return RT_FALSE; + } + + return RT_TRUE; +} + +/*------------------------------*/ +/* Send a command packet to MMC */ +rt_uint8_t send_cmd (rt_uint8_t cmd, rt_uint32_t arg) +{ + rt_uint8_t n, res; + + if (wait_ready() != 0xFF) return 0xFF; + + /* Send command packet */ + xmit_spi(cmd); /* Command */ + xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */ + xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */ + xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */ + xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */ + xmit_spi(0x95); /* CRC (valid for only CMD0) */ + + /* Receive command response */ + if (cmd == CMD12) rcvr_spi(); /* Skip a stuff rt_uint8_t when stop reading */ + n = 10; /* Wait for a valid response in timeout of 10 attempts */ + do + { + res = rcvr_spi(); + } + while ((res & 0x80) && --n); + + return res; /* Return with the response value */ +} + +static rt_err_t rt_sdcard_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_sdcard_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t count; + + count = size / 512; + + /* CS = L */ + SELECT(); + + /* append partition offset */ + pos += part.offset * 512; + + if (count == 1) + { /* Single block read */ + if ((send_cmd(CMD17, pos) == 0) /* READ_SINGLE_BLOCK */ + && rcvr_datablock(buffer, (rt_uint8_t)(512/2))) + count = 0; + else + count = 1; + } + else + { /* Multiple block read */ + if (send_cmd(CMD18, pos) == 0) + { + rt_uint8_t* ptr; + + ptr = buffer; + do + { + if (!rcvr_datablock(ptr, (rt_uint8_t)(512/2))) break; + ptr += 512; + } while (--count); + + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + if (count) + { + // rt_set_errno(-RT_ERROR); + return 0; + } + + return size / 512; +} + +static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t count; + + count = size / 512; + + /* CS = L */ + SELECT(); + + /* append partition offset */ + pos += part.offset * 512; + + if (count == 1) + { + /* Single block write */ + if ((send_cmd(CMD24, pos) == 0) /* WRITE_BLOCK */ + && xmit_datablock(buffer, 0xFE)) + count = 0; + else + count = 1; + } + else + { + /* Multiple block write */ + if (send_cmd(CMD25, pos) == 0) + { + rt_uint8_t *ptr; + + ptr = (rt_uint8_t *)buffer; + do + { + if (!xmit_datablock(ptr, 0xFC)) break; + ptr += 512; + } while (--count); + + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + if (count) + { + rt_set_errno(-RT_ERROR); + return 0; + } + + return size; +} + +static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +void rt_hw_sdcard_init() +{ + rt_uint32_t n; + rt_uint8_t* sector; + + sd.type = RT_Device_Class_Block; + sd.init = rt_sdcard_init; + sd.open = rt_sdcard_open; + sd.close = rt_sdcard_close; + sd.read = rt_sdcard_read; + sd.write = rt_sdcard_write; + sd.control = rt_sdcard_control; + sd.user_data = RT_NULL; + + AT91C_PIOA_PER = CARD_PWR_PIN; // enable GPIO of CS-pin + AT91C_PIOA_CODR = CARD_PWR_PIN; // set high + AT91C_PIOA_OER = CARD_PWR_PIN; // output enable + + for (n = 0; n < 3000; n ++) ; + + // disable PIO from controlling MOSI, MISO, SCK (=hand over to SPI) + // keep CS untouched - used as GPIO pin during init + AT91C_PIOA_PDR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; // | NCPS_PDR_BIT; + // set pin-functions in PIO Controller + AT91C_PIOA_ASR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; /// not here: | NCPS_ASR_BIT; + + // set chip-select as output high (unselect card) + AT91C_PIOA_PER = CARD_SELECT_PIN; // enable GPIO of CS-pin + AT91C_PIOA_SODR = CARD_SELECT_PIN; // set high + AT91C_PIOA_OER = CARD_SELECT_PIN; // output enable + + // enable peripheral clock for SPI ( PID Bit 5 ) + AT91C_PMC_PCER = ( (rt_uint32_t) 1 << AT91C_ID_SPI0 ); // n.b. IDs are just bit-numbers + + // SPI enable and reset + pSPI->SPI_CR = AT91C_SPI_SPIEN | AT91C_SPI_SWRST; + + // SPI mode: master, FDIV=0, fault detection disabled + pSPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS; + + // set chip-select-register + // 8 bits per transfer, CPOL=1, ClockPhase=0, DLYBCT = 0 + pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_CPOL | AT91C_SPI_BITS_8; + + // slow during init + AT91_spiSetSpeed(0xFE); + + // enable + pSPI->SPI_CR = AT91C_SPI_SPIEN; + + n = 10; /* Dummy clock */ + do + { + rcvr_spi(); + } while (--n); + + SELECT(); /* CS = L */ + if (send_cmd(CMD0, 0) == 1) + { + /* Enter Idle state */ + while (send_cmd(CMD1, 0)); + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + AT91_spiSetSpeed(SPI_SCBR_MIN); + + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } + + n = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512); + if (n == 512) + { + rt_err_t status; + + /* get the first partition */ + status = dfs_filesystem_get_partition(&part, sector, 0); + if (status != RT_EOK) + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + + /* release sector buffer */ + rt_free(sector); + + /* register sd device */ + rt_device_register(&sd, "sd", RT_DEVICE_FLAG_RDWR); +} diff --git a/bsp/sam7x/drivers/sd.h b/bsp/sam7x/drivers/sd.h index 0f38e06dfb..20cc7d258f 100644 --- a/bsp/sam7x/drivers/sd.h +++ b/bsp/sam7x/drivers/sd.h @@ -1,6 +1,6 @@ -#ifndef __SPI_SD_H__
-#define __SPI_SD_H__
-
-void rt_hw_sdcard_init(void);
-
-#endif
+#ifndef __SPI_SD_H__ +#define __SPI_SD_H__ + +void rt_hw_sdcard_init(void); + +#endif diff --git a/bsp/sam7x/drivers/serial.c b/bsp/sam7x/drivers/serial.c index 19aa87666b..0a658e9471 100644 --- a/bsp/sam7x/drivers/serial.c +++ b/bsp/sam7x/drivers/serial.c @@ -80,22 +80,22 @@ static void rt_hw_serial_isr(int irqno) { rt_base_t level; struct rt_device* device; - struct rt_at91serial* serial = RT_NULL;
+ struct rt_at91serial* serial = RT_NULL; #ifdef RT_USING_UART1 if (irqno == AT91C_ID_US0) { /* serial 1 */ serial = &serial1; - }
-#endif
-
+ } +#endif + #ifdef RT_USING_UART2 if (irqno == AT91C_ID_US1) { /* serial 2 */ serial = &serial2; - }
+ } #endif RT_ASSERT(serial != RT_NULL); diff --git a/bsp/sam7x/drivers/serial.h b/bsp/sam7x/drivers/serial.h index 5fe0928c9a..401b0c3129 100644 --- a/bsp/sam7x/drivers/serial.h +++ b/bsp/sam7x/drivers/serial.h @@ -1,14 +1,14 @@ -#ifndef __RT_SERIAL_H__
-#define __RT_SERIAL_H__
-
-#ifndef AT91C_BASE_US0
-#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
-#endif
-
-#ifndef AT91C_BASE_US1
-#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
-#endif
-
+#ifndef __RT_SERIAL_H__ +#define __RT_SERIAL_H__ + +#ifndef AT91C_BASE_US0 +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#endif + +#ifndef AT91C_BASE_US1 +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#endif + #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ @@ -52,5 +52,5 @@ #define MCK 48054857 #define BR 115200 /* Baud Rate */ #define BRD (MCK/16/BR) /* Baud Rate Divisor */ -
-#endif
+ +#endif diff --git a/bsp/sam7x/rtconfig.h b/bsp/sam7x/rtconfig.h index 30f3eca988..464d40c4d1 100644 --- a/bsp/sam7x/rtconfig.h +++ b/bsp/sam7x/rtconfig.h @@ -1,152 +1,152 @@ -/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX 8
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE 4
-
-/* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX 32
-
-/* Tick per Second*/
-#define RT_TICK_PER_SECOND 100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug*/
-/* #define RT_THREAD_DEBUG */
-
-/* Using Hook*/
-#define RT_USING_HOOK
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex*/
-#define RT_USING_MUTEX
-
-/* Using Event*/
-#define RT_USING_EVENT
-
-/* Using Faset Event*/
-/* #define RT_USING_FASTEVENT */
-
-/* Using MailBox*/
-#define RT_USING_MAILBOX
-
-/* Using Message Queue*/
-#define RT_USING_MESSAGEQUEUE
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
-
-/* Using Dynamic Heap Management*/
-#define RT_USING_HEAP
-
-/* Using Small MM*/
-#define RT_USING_SMALL_MEM
-#define RT_MEM_STATS
-
-/* Using SLAB Allocator*/
-/* #define RT_USING_SLAB */
-
-/* SECTION: Device System */
-/* Using Device System*/
-#define RT_USING_DEVICE
-#define RT_USING_UART1
-#define RT_UART_RX_BUFFER_SIZE 128
-
-/* SECTION: Console options */
-#define RT_USING_CONSOLE
-/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE 128
-
-/* SECTION: FinSH shell options */
-/* Using FinSH as Shell*/
-#define RT_USING_FINSH
-/* use symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-
-/* SECTION: a mini libc */
-/* Using mini libc library*/
-/* #define RT_USING_MINILIBC */
-
-/* SECTION: C++ support */
-/* Using C++ support*/
-/* #define RT_USING_CPLUSPLUS */
-
-/* SECTION: lwip, a lighwight TCP/IP protocol stack */
-/* Using lighweight TCP/IP protocol stack*/
-#define RT_USING_LWIP
-#define RT_LWIP_USING_RT_MEM
-
-/* Trace LwIP protocol*/
-/* #define RT_LWIP_DEBUG */
-
-/* LwIP tcp thread option */
-#define RT_LWIP_TCPTHREAD_PRIORITY 8
-#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
-
-/* LwIP eth thread option */
-#define RT_LWIP_ETHTHREAD_PRIORITY 15
-#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
-
-/* Enable ICMP protocol*/
-#define RT_LWIP_ICMP
-
-/* Enable IGMP protocol*/
-//#define RT_LWIP_IGMP
-
-/* Enable UDP protocol*/
-#define RT_LWIP_UDP
-
-/* Enable TCP protocol*/
-#define RT_LWIP_TCP
-
-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM 5
-
-/* TCP sender buffer space*/
-#define RT_LWIP_TCP_SND_BUF 1500
-
-/* Enable SNMP protocol*/
-/* #define RT_LWIP_SNMP */
-
-/* Using DHCP*/
-/* #define RT_LWIP_DHCP */
-
-/* ip address of target*/
-#define RT_LWIP_IPADDR0 192
-#define RT_LWIP_IPADDR1 168
-#define RT_LWIP_IPADDR2 1
-#define RT_LWIP_IPADDR3 30
-
-/* gateway address of target*/
-#define RT_LWIP_GWADDR0 192
-#define RT_LWIP_GWADDR1 168
-#define RT_LWIP_GWADDR2 1
-#define RT_LWIP_GWADDR3 1
-
-/* mask address of target*/
-#define RT_LWIP_MSKADDR0 255
-#define RT_LWIP_MSKADDR1 255
-#define RT_LWIP_MSKADDR2 255
-#define RT_LWIP_MSKADDR3 0
-
-/* SECTION: DFS options */
+/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX*/ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second*/ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug*/ +/* #define RT_THREAD_DEBUG */ + +/* Using Hook*/ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore*/ +#define RT_USING_SEMAPHORE + +/* Using Mutex*/ +#define RT_USING_MUTEX + +/* Using Event*/ +#define RT_USING_EVENT + +/* Using Faset Event*/ +/* #define RT_USING_FASTEVENT */ + +/* Using MailBox*/ +#define RT_USING_MAILBOX + +/* Using Message Queue*/ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management*/ +#define RT_USING_HEAP + +/* Using Small MM*/ +#define RT_USING_SMALL_MEM +#define RT_MEM_STATS + +/* Using SLAB Allocator*/ +/* #define RT_USING_SLAB */ + +/* SECTION: Device System */ +/* Using Device System*/ +#define RT_USING_DEVICE +#define RT_USING_UART1 +#define RT_UART_RX_BUFFER_SIZE 128 + +/* SECTION: Console options */ +#define RT_USING_CONSOLE +/* the buffer size of console*/ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: FinSH shell options */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* use symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION + +/* SECTION: a mini libc */ +/* Using mini libc library*/ +/* #define RT_USING_MINILIBC */ + +/* SECTION: C++ support */ +/* Using C++ support*/ +/* #define RT_USING_CPLUSPLUS */ + +/* SECTION: lwip, a lighwight TCP/IP protocol stack */ +/* Using lighweight TCP/IP protocol stack*/ +#define RT_USING_LWIP +#define RT_LWIP_USING_RT_MEM + +/* Trace LwIP protocol*/ +/* #define RT_LWIP_DEBUG */ + +/* LwIP tcp thread option */ +#define RT_LWIP_TCPTHREAD_PRIORITY 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 + +/* LwIP eth thread option */ +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 + +/* Enable ICMP protocol*/ +#define RT_LWIP_ICMP + +/* Enable IGMP protocol*/ +//#define RT_LWIP_IGMP + +/* Enable UDP protocol*/ +#define RT_LWIP_UDP + +/* Enable TCP protocol*/ +#define RT_LWIP_TCP + +/* the number of simulatenously active TCP connections*/ +#define RT_LWIP_TCP_PCB_NUM 5 + +/* TCP sender buffer space*/ +#define RT_LWIP_TCP_SND_BUF 1500 + +/* Enable SNMP protocol*/ +/* #define RT_LWIP_SNMP */ + +/* Using DHCP*/ +/* #define RT_LWIP_DHCP */ + +/* ip address of target*/ +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 + +/* gateway address of target*/ +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 + +/* mask address of target*/ +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 + +/* SECTION: DFS options */ //#define RT_USING_DFS /* the max number of mounted filesystem */ #define DFS_FILESYSTEMS_MAX 1 /* the max number of opened files */ #define DFS_FD_MAX 2 /* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4
+#define DFS_CACHE_MAX_NUM 4 -#endif
+#endif |