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authorzhuyunfan <[email protected]>2020-08-28 12:27:06 +0800
committerzhuyunfan <[email protected]>2020-08-28 12:30:33 +0800
commit6dd5af4fa62c4e27f6ed2c1b99d7f52167d09aa4 (patch)
treeda2bf6c4e1bd4f26bad0d59ec2a9c6dc4afb3bf6 /bsp/stm32/libraries/HAL_Drivers/drv_can.c
parent672881ee15d1c6df0ada197b22abd19a656974cd (diff)
[bsp][stm32]add can support for stm32l4
Diffstat (limited to 'bsp/stm32/libraries/HAL_Drivers/drv_can.c')
-rw-r--r--bsp/stm32/libraries/HAL_Drivers/drv_can.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.c b/bsp/stm32/libraries/HAL_Drivers/drv_can.c
index b423d79c95..c7d0428d48 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_can.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.c
@@ -59,6 +59,19 @@ static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
{CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 150)},
{CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 300)}
};
+#elif defined (SOC_SERIES_STM32L4)/* APB1 80MHz(max) */
+static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
+{
+ {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_5TQ | CAN_BS2_2TQ | 10)},
+ {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_14TQ | CAN_BS2_5TQ | 5)},
+ {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_7TQ | CAN_BS2_2TQ | 16)},
+ {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 20)},
+ {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 40)},
+ {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 50)},
+ {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 100)},
+ {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 250)},
+ {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 500)}
+};
#endif
#ifdef BSP_USING_CAN1