Merge branch 'master' into rtt_sensor

16 files changed, 378 insertions, 62 deletions

diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h
new file mode 100644
index 0000000000..739598e7d0
--- /dev/null
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV1,          \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD,    \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.LowPowerAutoPowerOff  = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.DiscontinuousConvMode = ENABLE,                        \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = ENABLE,                        \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h
index 8dd8598a28..39a79dd536 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h
@@ -19,35 +19,71 @@ extern "C" {
 #endif
 
 /* DMA1 channel1  */
-
-/* DMA1 channel2-3 DMA2 channel1-2 */
-#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
-#define UART1_DMA_RX_IRQHandler          DMA1_Channel2_3_IRQHandler
-#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define UART1_RX_DMA_INSTANCE            DMA1_Channel3
-#define UART1_RX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA1_Channel1_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE             DMA1_Channel1
+#define SPI1_RX_DMA_REQUEST              DMA_REQUEST_SPI1_RX
+#define SPI1_RX_DMA_IRQ                  DMA1_Channel1_IRQn
+#ifdef BSP_UART1_RX_USING_DMA
+#undef BSP_UART1_RX_USING_DMA
+#endif
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel1_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel1
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#define UART1_RX_DMA_IRQ                DMA1_Channel1_IRQn
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel1_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel1
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_SPI2_RX
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel1_IRQn
 #endif
-/* DMA1 channel2-3 DMA2 channel1-2 */
 
-/* DMA1 channel4-7 DMA2 channel3-5 */
-#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
-#define UART2_DMA_RX_IRQHandler          DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
-#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define UART2_RX_DMA_INSTANCE            DMA1_Channel5
-#define UART2_RX_DMA_IRQ                 DMA1_Ch4_7_DMAMUX1_OVR_IRQn
+/* DMA1 channle2-3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#ifdef BSP_UART2_RX_USING_DMA
+#undef BSP_UART2_RX_USING_DMA
 #endif
-/* DMA1 channel4-7 DMA2 channel3-5 */
-#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
-#define UART3_DMA_RX_IRQHandler          DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
-#define UART3_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define UART3_RX_DMA_INSTANCE            DMA1_Channel4
-#define UART3_RX_DMA_IRQ                 DMA1_Ch4_7_DMAMUX1_OVR_IRQn
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
 #endif
-#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
-#define UART4_DMA_RX_IRQHandler          DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
-#define UART4_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define UART4_RX_DMA_INSTANCE            DMA1_Channel6
-#define UART4_RX_DMA_IRQ                 DMA1_Ch4_7_DMAMUX1_OVR_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel2_3_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel2
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_USART2_RX
+#define UART2_RX_DMA_IRQ                DMA1_Channel2_3_IRQn
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_SPI2_TX
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#endif
+
+#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHBENR_DMA1EN
+#define LPUART1_RX_DMA_INSTANCE         DMA1_Channel5
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_LPUART1_RX
+#define LPUART1_RX_DMA_IRQ              DMA1_Ch4_7_DMAMUX1_OVR_IRQn
 #endif
 
 #ifdef __cplusplus
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h
new file mode 100644
index 0000000000..834903f656
--- /dev/null
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h
new file mode 100644
index 0000000000..a09ec948a9
--- /dev/null
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .request = SPI1_TX_DMA_REQUEST,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .request = SPI1_RX_DMA_REQUEST,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .request = SPI2_TX_DMA_REQUEST,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .request = SPI2_RX_DMA_REQUEST,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h
new file mode 100644
index 0000000000..01d3af18f1
--- /dev/null
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h
index bca5ef2cc4..a3019f5dec 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h
@@ -21,14 +21,16 @@
         .Instance = LPUART1,                                        \
         .irq_type = USART3_4_LPUART1_IRQn,                          \
     }
+#define LPUART1_IRQHandler      USART3_4_LPUART1_IRQHandler
 #endif /* LPUART1_CONFIG */
 #if defined(BSP_LPUART1_RX_USING_DMA)
 #ifndef LPUART1_DMA_CONFIG
 #define LPUART1_DMA_CONFIG                                          \
     {                                                               \
-        .Instance = DMA1_Channel1,                                  \
-        .dma_rcc  = RCC_AHBENR_DMA1EN,                              \
-        .dma_irq  = DMA1_Channel1_IRQn,                             \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request =  LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
     }
 #endif /* LPUART1_DMA_CONFIG */
 #endif /* BSP_LPUART1_RX_USING_DMA */
@@ -50,6 +52,7 @@
 #define UART1_DMA_CONFIG                                            \
     {                                                               \
         .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request =  UART1_RX_DMA_REQUEST,                           \
         .dma_rcc  = UART1_RX_DMA_RCC,                               \
         .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
@@ -72,6 +75,7 @@
 #define UART2_DMA_CONFIG                                            \
     {                                                               \
         .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request =  UART2_RX_DMA_REQUEST,                           \
         .dma_rcc  = UART2_RX_DMA_RCC,                               \
         .dma_irq  = UART2_RX_DMA_IRQ,                               \
     }
@@ -103,6 +107,7 @@
 #define UART3_DMA_CONFIG                                            \
     {                                                               \
         .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request =  UART3_RX_DMA_REQUEST,                           \
         .dma_rcc  = UART3_RX_DMA_RCC,                               \
         .dma_irq  = UART3_RX_DMA_IRQ,                               \
     }
@@ -134,6 +139,7 @@
 #define UART4_DMA_CONFIG                                            \
     {                                                               \
         .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .request =  UART4_RX_DMA_REQUEST,                           \
         .dma_rcc  = UART4_RX_DMA_RCC,                               \
         .dma_irq  = UART4_RX_DMA_IRQ,                               \
     }
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c
index 124fdab6bc..c998e0ce5a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c
@@ -50,7 +50,7 @@ static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
 
     if (enabled)
     {
-#ifdef SOC_SERIES_STM32L4
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
         ADC_Enable(stm32_adc_handler);
 #else
         __HAL_ADC_ENABLE(stm32_adc_handler);
@@ -58,7 +58,7 @@ static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
     }
     else
     {
-#ifdef SOC_SERIES_STM32L4
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
         ADC_Disable(stm32_adc_handler);
 #else
         __HAL_ADC_DISABLE(stm32_adc_handler);
@@ -150,7 +150,8 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
 
 #if defined(SOC_SERIES_STM32F1)
     if (channel <= 17)
-#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
+        || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
     if (channel <= 18)
 #endif
     {
@@ -161,7 +162,8 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     {
 #if defined(SOC_SERIES_STM32F1)
         LOG_E("ADC channel must be between 0 and 17.");
-#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
+        || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
         LOG_E("ADC channel must be between 0 and 18.");
 #endif
         return -RT_ERROR;
@@ -215,18 +217,24 @@ static int stm32_adc_init(void)
         /* ADC init */
         name_buf[3] = '0';
         stm32_adc_obj[i].ADC_Handler = adc_config[i];
+#if defined(ADC1)
         if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
         {
             name_buf[3] = '1';
         }
+#endif
+#if defined(ADC2)
         if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
         {
             name_buf[3] = '2';
         }
+#endif
+#if defined(ADC3)
         if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
         {
             name_buf[3] = '3';
         }
+#endif
         if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
         {
             LOG_E("%s init failed", name_buf);
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h
index b6549e09e3..e497f496af 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h
@@ -65,6 +65,10 @@ extern "C" {
 #elif  defined(SOC_SERIES_STM32G0)
 #include "g0/dma_config.h"
 #include "g0/uart_config.h"
+#include "g0/spi_config.h"
+#include "g0/adc_config.h"
+#include "g0/tim_config.h"
+#include "g0/pwm_config.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
index 1113c87095..a6ff9e209a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
@@ -34,7 +34,7 @@ struct dma_config {
     rt_uint32_t channel;
 #endif
 
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
     rt_uint32_t request;
 #endif
 };
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
index 42f41fb620..9824d3eb2f 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
@@ -544,7 +544,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         HAL_GPIO_DeInit(index->gpio, index->pin);
 
         pin_irq_enable_mask &= ~irqmap->pinbit;
-#if defined(SOC_SERIES_STM32F0)
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         if (( irqmap->pinbit>=GPIO_PIN_0 )&&( irqmap->pinbit<=GPIO_PIN_1 ))
         {
             if(!(pin_irq_enable_mask&(GPIO_PIN_0|GPIO_PIN_1)))
@@ -618,12 +618,24 @@ rt_inline void pin_irq_hdr(int irqno)
     }
 }
 
+#if defined(SOC_SERIES_STM32G0)
+void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
+{
+    pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+
+void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
+{
+    pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+#else
 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
     pin_irq_hdr(bit2bitno(GPIO_Pin));
 }
+#endif
 
-#if defined(SOC_SERIES_STM32F0)
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
 void EXTI0_1_IRQHandler(void)
 {
     rt_interrupt_enter();
@@ -758,6 +770,10 @@ int rt_hw_pin_init(void)
     __HAL_RCC_GPIOJ_CLK_ENABLE();
 #endif
 
+#if defined(__HAL_RCC_GPIOK_CLK_ENABLE)
+    __HAL_RCC_GPIOK_CLK_ENABLE();
+#endif
+
     return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
 }
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
index 57ff812c52..d8ad946fd0 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
@@ -168,11 +168,11 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
         if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
 #elif defined(SOC_SERIES_STM32L4)
         if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
-#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         if (0)
 #endif
         {
-#ifndef SOC_SERIES_STM32F0
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
             prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * 2 / 10000) - 1;
 #endif
         }
@@ -192,7 +192,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
             tim->Init.CounterMode   = TIM_COUNTERMODE_DOWN;
         }
         tim->Init.RepetitionCounter = 0;
-#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 #endif
         if (HAL_TIM_Base_Init(tim) != HAL_OK)
@@ -282,7 +282,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
         if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
 #elif defined(SOC_SERIES_STM32L4)
         if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
-#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         if (0)
 #endif
         {
@@ -296,7 +296,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
         {
 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
             val = HAL_RCC_GetPCLK1Freq() * 2 / freq;
-#elif defined(SOC_SERIES_STM32F0)
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
             val = HAL_RCC_GetPCLK1Freq() / freq;
 #endif
         }
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
index f0157976ce..f781e51b0d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
@@ -189,17 +189,17 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
     if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
 #elif defined(SOC_SERIES_STM32L4)
     if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
-#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
     if (0)
 #endif
     {
-#ifndef SOC_SERIES_STM32F0
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
         tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
 #endif
     }
     else
     {
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         tim_clock = HAL_RCC_GetPCLK1Freq();
 #else
         tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
@@ -234,17 +234,17 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
     if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
 #elif defined(SOC_SERIES_STM32L4)
     if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
-#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
     if (0)
 #endif
     {
-#ifndef SOC_SERIES_STM32F0
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
         tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
 #endif
     }
     else
     {
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         tim_clock = HAL_RCC_GetPCLK1Freq();
 #else
         tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c
index 06c0a90217..12e9fbf3d6 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c
@@ -145,7 +145,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
 
     uint32_t SPI_APB_CLOCK;
 
-#ifdef SOC_SERIES_STM32F0
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
     SPI_APB_CLOCK = HAL_RCC_GetPCLK1Freq();
 #else
     SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();
@@ -203,7 +203,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
     spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
     spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
     spi_handle->State = HAL_SPI_STATE_RESET;
-#ifdef SOC_SERIES_STM32L4
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
     spi_handle->Init.NSSPMode          = SPI_NSS_PULSE_DISABLE;
 #endif
 
@@ -212,7 +212,8 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
         return RT_EIO;
     }
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)|| defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
+        || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0)
     SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
 #endif
 
@@ -389,7 +390,7 @@ static int rt_hw_spi_bus_init(void)
             spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
 #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
             spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
-#elif defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
             spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
 #endif
             spi_bus_obj[i].dma.handle_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
@@ -408,7 +409,7 @@ static int rt_hw_spi_bus_init(void)
 
             {
                 rt_uint32_t tmpreg = 0x00U;
-#if defined(SOC_SERIES_STM32F1)
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0)
                 /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
                 SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
                 tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
@@ -427,7 +428,7 @@ static int rt_hw_spi_bus_init(void)
             spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
 #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
             spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
-#elif defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
             spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
 #endif
             spi_bus_obj[i].dma.handle_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
@@ -446,7 +447,7 @@ static int rt_hw_spi_bus_init(void)
 
             {
                 rt_uint32_t tmpreg = 0x00U;
-#if defined(SOC_SERIES_STM32F1)
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0)
                 /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
                 SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
                 tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
index 83d479a413..446533d89f 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
@@ -483,13 +483,12 @@ static void stm32_dma_config(struct rt_serial_device *serial)
 
     __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma.handle);
 
-#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
-	|| defined(SOC_SERIES_STM32L0)
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
     uart->dma.handle.Instance                 = uart->config->dma_rx->Instance;
 #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     uart->dma.handle.Instance                 = uart->config->dma_rx->Instance;
     uart->dma.handle.Init.Channel             = uart->config->dma_rx->channel;
-#elif defined(SOC_SERIES_STM32L4) 
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
     uart->dma.handle.Instance                 = uart->config->dma_rx->Instance;
     uart->dma.handle.Init.Request             = uart->config->dma_rx->request;
 #endif
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
index f7f7e7bf06..f7654671e4 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
@@ -85,7 +85,7 @@ LoopFillZerobss:
 /* Call the clock system intitialization function.*/
   bl  SystemInit
 /* Call static constructors */
-  bl __libc_init_array
+/*  bl __libc_init_array */
 /* Call the application's entry point.*/
   bl entry
 
diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/SConscript b/bsp/stm32/libraries/STM32G0xx_HAL/SConscript
index e01201e47a..aa9dd911bc 100644
--- a/bsp/stm32/libraries/STM32G0xx_HAL/SConscript
+++ b/bsp/stm32/libraries/STM32G0xx_HAL/SConscript
@@ -47,11 +47,10 @@ if GetDepend(['RT_USING_ADC']):
     src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c']
     src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c']
     src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c']
-    
-if GetDepend(['RT_USING_RTC']):
-    src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c']
-    src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c']
-    src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rtc.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c']
+    src += ['STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c']
 
 path = [cwd + '/STM32G0xx_HAL_Driver/Inc', 
     cwd + '/CMSIS/ST/STM32G0xx/Include',