diff options
| author | yangjie <[email protected]> | 2020-12-28 12:02:31 +0800 |
|---|---|---|
| committer | yangjie <[email protected]> | 2020-12-28 12:02:31 +0800 |
| commit | eeaf1fcc50a9a6d25bebcc531db8e03baafaded3 (patch) | |
| tree | 3a7e70fbb26fad36211874a5bc4f9f9f22c8fa38 /bsp/stm32 | |
| parent | ef62febf1f2461bdd72efcffde050905865a99c5 (diff) | |
| parent | e3e86337862c6d84f2b55906a49d48aa33084d39 (diff) | |
resolve Conflicts
bsp/nrf52832/board/Sconscript
bsp/nrf52832/startups/Sconscript
bsp/raspberry-pi/raspi4-32/driver/SConscript
Diffstat (limited to 'bsp/stm32')
160 files changed, 25356 insertions, 5123 deletions
diff --git a/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md b/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md index cb6e4f8f47..05ac07a869 100644 --- a/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md +++ b/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md @@ -72,7 +72,7 @@ Use a Type-A to Mini-B cable to connect the development board to the PC and turn After the program is successfully downloaded, the system runs automatically. Observe the running results of the LED on the development board, the LD3 and LD1 will light all the time, and LD2 will flash periodically. -The USB virtual COM port connects to **USART2 by default**, and when the corresponding serial port (**115200-8-1-N**) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset: +The USB virtual COM port connects to **USART3 by default**, and when the corresponding serial port (**115200-8-1-N**) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset: ```shell \ | / @@ -102,7 +102,7 @@ Follow these tutorial videos to learn PuTTy: ## Advanced Features -This BSP only enables GPIO and USART2 by default. If you need more advanced features such as SPI, I2C, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env) , as follows: +This BSP only enables GPIO and USART3 by default. If you need more advanced features such as SPI, I2C, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env) , as follows: 1. Open the Env tool under the specific BSP folder; 2. Enter `menuconfig` command to configure the project, then save and exit; diff --git a/bsp/stm32/libraries/HAL_Drivers/Kconfig b/bsp/stm32/libraries/HAL_Drivers/Kconfig index 45160eee82..41cf5cf08b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/Kconfig +++ b/bsp/stm32/libraries/HAL_Drivers/Kconfig @@ -40,7 +40,21 @@ config BSP_USING_RNG depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \ SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1) default n - + +config BSP_USING_HASH + bool "Enable HASH (Hash House Harriers)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_HASH + depends on (SOC_SERIES_STM32MP1) + default n + +config BSP_USING_CRYP + bool "Enable CRYP (Encrypt And Decrypt Data)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRYP + depends on (SOC_SERIES_STM32MP1) + default n + config BSP_USING_UDID bool "Enable UDID (Unique Device Identifier)" select RT_USING_HWCRYPTO diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h new file mode 100644 index 0000000000..6ca3932831 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 thread-liu first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_CONFIG +#define DAC1_CONFIG \ + { \ + .Instance = DAC1, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_CONFIG +#define DAC2_CONFIG \ + { \ + .Instance = DAC2, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h new file mode 100644 index 0000000000..6ca3932831 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 thread-liu first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_CONFIG +#define DAC1_CONFIG \ + { \ + .Instance = DAC1, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_CONFIG +#define DAC2_CONFIG \ + { \ + .Instance = DAC2, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h index b56973ec98..8a2fc3a5fe 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h @@ -1,13 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-01-02 zylx first version - * 2019-01-08 SummerGift clean up the code - * 2020-06-20 thread-liu add stm32mp1 + * 2020-06-20 thread-liu first version */ #ifndef __DMA_CONFIG_H__ @@ -19,6 +17,22 @@ extern "C" { #endif +/* DMA1 stream0 */ + +/* DMA1 stream1 */ + +/* DMA1 stream2 */ + +/* DMA1 stream3 */ + +/* DMA1 stream4 */ + +/* DMA1 stream5 */ + +/* DMA1 stream6 */ + +/* DMA1 stream7 */ + /* DMA2 stream0 */ #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) #define UART3_RX_DMA_IRQHandler DMA2_Stream0_IRQHandler @@ -26,18 +40,12 @@ extern "C" { #define UART3_RX_DMA_INSTANCE DMA2_Stream0 #define UART3_RX_DMA_CHANNEL DMA_REQUEST_USART3_RX #define UART3_RX_DMA_IRQ DMA2_Stream0_IRQn -#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 -#define SPI4_RX_DMA_CHANNEL DMA_REQUEST_SPI4_RX -#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn -#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) -#define UART5_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define UART5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART5_RX_DMA_INSTANCE DMA2_Stream0 -#define UART5_RX_DMA_CHANNEL DMA_REQUEST_UART5_RX -#define UART5_RX_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI5_RX_DMA_CHANNEL DMA_REQUEST_SPI5_RX +#define SPI5_RX_DMA_IRQ DMA2_Stream0_IRQn #endif /* DMA2 stream1 */ @@ -47,12 +55,12 @@ extern "C" { #define UART3_TX_DMA_INSTANCE DMA2_Stream1 #define UART3_TX_DMA_CHANNEL DMA_REQUEST_USART3_TX #define UART3_TX_DMA_IRQ DMA2_Stream1_IRQn -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#define SPI4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 -#define SPI4_TX_DMA_CHANNEL DMA_REQUEST_SPI4_TX -#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI5_TX_DMA_CHANNEL DMA_REQUEST_SPI5_TX +#define SPI5_TX_DMA_IRQ DMA2_Stream1_IRQn #endif /* DMA2 stream2 */ @@ -65,48 +73,48 @@ extern "C" { #endif /* DMA2 stream3 */ -#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 -#define SPI5_RX_DMA_CHANNEL DMA_REQUEST_SPI5_RX -#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn +#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define UART4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define UART4_RX_DMA_INSTANCE DMA2_Stream3 +#define UART4_RX_DMA_CHANNEL DMA_REQUEST_UART4_RX +#define UART4_RX_DMA_IRQ DMA2_Stream3_IRQn #endif /* DMA2 stream4 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#define SPI5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 -#define SPI5_TX_DMA_CHANNEL DMA_REQUEST_SPI5_TX -#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn -#endif - -/* DMA2 stream5 */ #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) -#define UART4_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define UART4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler #define UART4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART4_TX_DMA_INSTANCE DMA2_Stream5 +#define UART4_TX_DMA_INSTANCE DMA2_Stream4 #define UART4_TX_DMA_CHANNEL DMA_REQUEST_UART4_TX -#define UART4_TX_DMA_IRQ DMA2_Stream5_IRQn +#define UART4_TX_DMA_IRQ DMA2_Stream4_IRQn +#endif + +/* DMA2 stream5 */ +#if defined(BSP_USING_CRYP) && !defined(CRYP2_OUT_DMA_INSTANCE) +#define CRYP2_DMA_OUT_IRQHandler DMA2_Stream5_IRQHandler +#define CRYP2_OUT_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define CRYP2_OUT_DMA_INSTANCE DMA2_Stream5 +#define CRYP2_OUT_DMA_CHANNEL DMA_REQUEST_CRYP2_OUT +#define CRYP2_OUT_DMA_IRQ DMA2_Stream5_IRQn #endif /* DMA2 stream6 */ -#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler -#define UART4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART4_RX_DMA_INSTANCE DMA2_Stream6 -#define UART4_RX_DMA_CHANNEL DMA_REQUEST_UART4_RX -#define UART4_RX_DMA_IRQ DMA2_Stream6_IRQn +#if defined(BSP_USING_CRYP) && !defined(CRYP2_IN_DMA_INSTANCE) +#define CRYP2_DMA_IN_IRQHandler DMA2_Stream6_IRQHandler +#define CRYP2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define CRYP2_IN_DMA_INSTANCE DMA2_Stream6 +#define CRYP2_IN_DMA_CHANNEL DMA_REQUEST_CRYP2_IN +#define CRYP2_IN_DMA_IRQ DMA2_Stream6_IRQn #endif /* DMA2 stream7 */ -#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) -#define UART5_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler -#define UART5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART5_TX_DMA_INSTANCE DMA2_Stream7 -#define UART5_TX_DMA_CHANNEL DMA_REQUEST_UART5_TX -#define UART5_TX_DMA_IRQ DMA2_Stream7_IRQn +#if defined(BSP_USING_HASH) && !defined(HASH2_IN_DMA_INSTANCE) +#define HASH2_DMA_IN_IRQHandler DMA2_Stream7_IRQHandler +#define HASH2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define HASH2_IN_DMA_INSTANCE DMA2_Stream7 +#define HASH2_IN_DMA_CHANNEL DMA_REQUEST_HASH2_IN +#define HASH2_IN_DMA_IRQ DMA2_Stream7_IRQn #endif #ifdef __cplusplus diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h new file mode 100644 index 0000000000..0dc48247e7 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-22 zylx first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = QUADSPI, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \ + .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \ + } +#endif /* QSPI_BUS_CONFIG */ +#endif /* BSP_USING_QSPI */ + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ + .Init.Direction = DMA_PERIPH_TO_MEMORY, \ + .Init.PeriphInc = DMA_PINC_DISABLE, \ + .Init.MemInc = DMA_MINC_ENABLE, \ + .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ + .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ + .Init.Mode = DMA_NORMAL, \ + .Init.Priority = DMA_PRIORITY_LOW \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ + +#define QSPI_IRQn QUADSPI_IRQn +#define QSPI_IRQHandler QUADSPI_IRQHandler + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h index 69de2adccd..26edfa927c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h @@ -23,7 +23,6 @@ extern "C" { { \ .Instance = SPI1, \ .bus_name = "spi1", \ - .irq_type = SPI1_IRQn, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ @@ -58,7 +57,6 @@ extern "C" { { \ .Instance = SPI2, \ .bus_name = "spi2", \ - .irq_type = SPI2_IRQn, \ } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ @@ -93,7 +91,6 @@ extern "C" { { \ .Instance = SPI3, \ .bus_name = "spi3", \ - .irq_type = SPI3_IRQn, \ } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ @@ -128,7 +125,6 @@ extern "C" { { \ .Instance = SPI4, \ .bus_name = "spi4", \ - .irq_type = SPI4_IRQn, \ } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index 95c1440560..fe0c0d932b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -51,6 +51,7 @@ extern "C" { #include "f4/qspi_config.h" #include "f4/usbd_config.h" #include "f4/adc_config.h" +#include "f4/dac_config.h" #include "f4/tim_config.h" #include "f4/sdio_config.h" #include "f4/pwm_config.h" @@ -73,6 +74,7 @@ extern "C" { #include "l4/spi_config.h" #include "l4/qspi_config.h" #include "l4/adc_config.h" +#include "l4/dac_config.h" #include "l4/tim_config.h" #include "l4/sdio_config.h" #include "l4/pwm_config.h" @@ -109,6 +111,7 @@ extern "C" { #elif defined(SOC_SERIES_STM32MP1) #include "mp1/dma_config.h" #include "mp1/uart_config.h" +#include "mp1/qspi_config.h" #include "mp1/spi_config.h" #include "mp1/adc_config.h" #include "mp1/dac_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c b/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c index e82446c4a6..b093516ca5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c @@ -7,6 +7,9 @@ * Date Author Notes * 2019-07-10 Ernest 1st version * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-11-26 thread-liu add hash + * 2020-11-26 thread-liu add cryp + * 2020-12-11 WKJay fix build problem */ #include <rtthread.h> @@ -15,7 +18,8 @@ #include <string.h> #include "drv_crypto.h" #include "board.h" - +#include "drv_config.h" + struct stm32_hwcrypto_device { struct rt_hwcrypto_device dev; @@ -24,12 +28,7 @@ struct stm32_hwcrypto_device #if defined(BSP_USING_CRC) -struct hash_ctx_des -{ - CRC_HandleTypeDef contex; -}; - -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) static struct hwcrypto_crc_cfg crc_backup_cfg; static int reverse_bit(rt_uint32_t n) @@ -49,12 +48,12 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r rt_uint32_t result = 0; struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; -#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) CRC_HandleTypeDef *HW_TypeDef = (CRC_HandleTypeDef *)(ctx->parent.contex); #endif rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0) { if (HW_TypeDef->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_DISABLE) @@ -113,7 +112,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r result = HAL_CRC_Accumulate(ctx->parent.contex, (rt_uint32_t *)in, length); -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) if (HW_TypeDef->Init.OutputDataInversionMode) { ctx ->crc_cfg.last_val = reverse_bit(result); @@ -149,7 +148,7 @@ static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx) { return gen_random ; } - + return 0; } @@ -159,10 +158,213 @@ static const struct hwcrypto_rng_ops rng_ops = }; #endif /* BSP_USING_RNG */ +#if defined(BSP_USING_HASH) +static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt_size_t length) +{ + rt_uint32_t tickstart = 0; + rt_uint32_t result = RT_EOK; + struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; + rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); + +#if defined(SOC_SERIES_STM32MP1) + HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex); + /* Start HASH computation using DMA transfer */ + switch (ctx->parent.type) + { + case HWCRYPTO_TYPE_SHA224: + result = HAL_HASHEx_SHA224_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + case HWCRYPTO_TYPE_SHA256: + result = HAL_HASHEx_SHA256_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + case HWCRYPTO_TYPE_MD5: + result = HAL_HASH_MD5_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + case HWCRYPTO_TYPE_SHA1: + result = HAL_HASH_SHA1_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + default : + rt_kprintf("not support hash type: %x", ctx->parent.type); + break; + } + if (result != HAL_OK) + { + goto _exit; + } + /* Wait for DMA transfer to complete */ + tickstart = rt_tick_get(); + while (HAL_HASH_GetState(HW_TypeDef) == HAL_HASH_STATE_BUSY) + { + if (rt_tick_get() - tickstart > 0xFFFF) + { + result = RT_ETIMEOUT; + goto _exit; + } + } + +#endif +_exit: + rt_mutex_release(&stm32_hw_dev->mutex); + + return result; +} + +static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size_t length) +{ + rt_uint32_t result = RT_EOK; + struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; + rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); +#if defined(SOC_SERIES_STM32MP1) + HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex); + /* Get the computed digest value */ + switch (ctx->parent.type) + { + case HWCRYPTO_TYPE_SHA224: + result = HAL_HASHEx_SHA224_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + case HWCRYPTO_TYPE_SHA256: + result = HAL_HASHEx_SHA256_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + case HWCRYPTO_TYPE_MD5: + result = HAL_HASH_MD5_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + case HWCRYPTO_TYPE_SHA1: + result = HAL_HASH_SHA1_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + default : + rt_kprintf("not support hash type: %x", ctx->parent.type); + break; + } + if (result != HAL_OK) + { + goto _exit; + } +#endif + +_exit: + rt_mutex_release(&stm32_hw_dev->mutex); + + return result; +} + +static const struct hwcrypto_hash_ops hash_ops = +{ + .update = _hash_update, + .finish = _hash_finish +}; + +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) +static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, + struct hwcrypto_symmetric_info *info) +{ + rt_uint32_t result = RT_EOK; + rt_uint32_t tickstart = 0; + + struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; + rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); + +#if defined(SOC_SERIES_STM32MP1) + CRYP_HandleTypeDef *HW_TypeDef = (CRYP_HandleTypeDef *)(ctx->parent.contex); + + switch (ctx->parent.type) + { + case HWCRYPTO_TYPE_AES_ECB: + HW_TypeDef->Init.Algorithm = CRYP_AES_ECB; + break; + + case HWCRYPTO_TYPE_AES_CBC: + HW_TypeDef->Init.Algorithm = CRYP_AES_CBC; + break; + + case HWCRYPTO_TYPE_AES_CTR: + HW_TypeDef->Init.Algorithm = CRYP_AES_CTR; + break; + + case HWCRYPTO_TYPE_DES_ECB: + HW_TypeDef->Init.Algorithm = CRYP_DES_ECB; + break; + + case HWCRYPTO_TYPE_DES_CBC: + HW_TypeDef->Init.Algorithm = CRYP_DES_CBC; + break; + + default : + rt_kprintf("not support cryp type: %x", ctx->parent.type); + break; + } + + HAL_CRYP_DeInit(HW_TypeDef); + + HW_TypeDef->Init.DataType = CRYP_DATATYPE_8B; + HW_TypeDef->Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_BYTE; + HW_TypeDef->Init.KeySize = CRYP_KEYSIZE_128B; + HW_TypeDef->Init.pKey = (uint32_t*)ctx->key; + + result = HAL_CRYP_Init(HW_TypeDef); + if (result != HAL_OK) + { + /* Initialization Error */ + goto _exit; + } + if (info->mode == HWCRYPTO_MODE_ENCRYPT) + { + result = HAL_CRYP_Encrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out); + } + else if (info->mode == HWCRYPTO_MODE_DECRYPT) + { + result = HAL_CRYP_Decrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out); + } + else + { + rt_kprintf("error cryp mode : %02x!\n", info->mode); + result = RT_ERROR; + goto _exit; + } + + if (result != HAL_OK) + { + goto _exit; + } + + tickstart = rt_tick_get(); + while (HAL_CRYP_GetState(HW_TypeDef) != HAL_CRYP_STATE_READY) + { + if (rt_tick_get() - tickstart > 0xFFFF) + { + result = RT_ETIMEOUT; + goto _exit; + } + } + +#endif + + if (result != HAL_OK) + { + goto _exit; + } + +_exit: + rt_mutex_release(&stm32_hw_dev->mutex); + + return result; +} + +static const struct hwcrypto_symmetric_ops cryp_ops = +{ + .crypt = _cryp_crypt +}; +#endif + static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) { rt_err_t res = RT_EOK; - + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) { #if defined(BSP_USING_RNG) @@ -174,8 +376,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) res = -RT_ERROR; break; } - +#if defined(SOC_SERIES_STM32MP1) + hrng->Instance = RNG2; +#else hrng->Instance = RNG; +#endif HAL_RNG_Init(hrng); ctx->contex = hrng; ((struct hwcrypto_rng *)ctx)->ops = &rng_ops; @@ -193,9 +398,12 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) res = -RT_ERROR; break; } - +#if defined(SOC_SERIES_STM32MP1) + hcrc->Instance = CRC2; +#else hcrc->Instance = CRC; -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#endif +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) hcrc->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; hcrc->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE; hcrc->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE; @@ -209,9 +417,77 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) #endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */ ctx->contex = hcrc; ((struct hwcrypto_crc *)ctx)->ops = &crc_ops; + break; } #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + { + HASH_HandleTypeDef *hash = rt_calloc(1, sizeof(HASH_HandleTypeDef)); + if (RT_NULL == hash) + { + res = -RT_ERROR; + break; + } +#if defined(SOC_SERIES_STM32MP1) + /* enable dma for hash */ + __HAL_RCC_DMA2_CLK_ENABLE(); + HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + + hash->Init.DataType = HASH_DATATYPE_8B; + if (HAL_HASH_Init(hash) != HAL_OK) + { + res = -RT_ERROR; + } +#endif + ctx->contex = hash; + ((struct hwcrypto_hash *)ctx)->ops = &hash_ops; + + break; + } +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + { + CRYP_HandleTypeDef *cryp = rt_calloc(1, sizeof(CRYP_HandleTypeDef)); + if (RT_NULL == cryp) + { + res = -RT_ERROR; + break; + } +#if defined(SOC_SERIES_STM32MP1) + cryp->Instance = CRYP2; + /* enable dma for cryp */ + __HAL_RCC_DMA2_CLK_ENABLE(); + + HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); + + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); + + if (HAL_CRYP_Init(cryp) != HAL_OK) + { + res = -RT_ERROR; + } +#endif + ctx->contex = cryp; + ((struct hwcrypto_symmetric *)ctx)->ops = &cryp_ops; + + break; + } +#endif /* BSP_USING_CRYP */ + default: res = -RT_ERROR; break; @@ -234,6 +510,26 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex)); break; #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + __HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex)); + HAL_HASH_DeInit((HASH_HandleTypeDef *)(ctx->contex)); + break; +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + HAL_CRYP_DeInit((CRYP_HandleTypeDef *)(ctx->contex)); + break; +#endif /* BSP_USING_CRYP */ + default: break; } @@ -251,7 +547,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry case HWCRYPTO_TYPE_RNG: if (des->contex && src->contex) { - rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des)); + rt_memcpy(des->contex, src->contex, sizeof(RNG_HandleTypeDef)); } break; #endif /* BSP_USING_RNG */ @@ -260,10 +556,35 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry case HWCRYPTO_TYPE_CRC: if (des->contex && src->contex) { - rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des)); + rt_memcpy(des->contex, src->contex, sizeof(CRC_HandleTypeDef)); } break; #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(HASH_HandleTypeDef)); + } + break; +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(CRYP_HandleTypeDef)); + } + break; +#endif /* BSP_USING_CRYP */ + default: res = -RT_ERROR; break; @@ -285,11 +606,74 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx) __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex); break; #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + __HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex)); + break; +#endif /* BSP_USING_HASH*/ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + break; +#endif /* BSP_USING_CRYP */ + default: break; } } +#if defined(HASH2_IN_DMA_INSTANCE) +void HASH2_DMA_IN_IRQHandler(void) +{ + extern DMA_HandleTypeDef hdma_hash_in; + + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_hash_in); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(CRYP2_IN_DMA_INSTANCE) +void CRYP2_DMA_IN_IRQHandler(void) +{ + extern DMA_HandleTypeDef hdma_cryp_in; + + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_cryp_in); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined (CRYP2_OUT_DMA_INSTANCE) +void CRYP2_DMA_OUT_IRQHandler(void) +{ + extern DMA_HandleTypeDef hdma_cryp_out; + + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_cryp_out); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + static const struct rt_hwcrypto_ops _ops = { .create = _crypto_create, @@ -306,10 +690,10 @@ int stm32_hw_crypto_device_init(void) _crypto_dev.dev.ops = &_ops; #if defined(BSP_USING_UDID) -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) cpuid[0] = HAL_GetUIDw0(); cpuid[1] = HAL_GetUIDw1(); -#elif defined(SOC_SERIES_STM32H7) +#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) cpuid[0] = HAL_GetREVID(); cpuid[1] = HAL_GetDEVID(); #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dac.c b/bsp/stm32/libraries/HAL_Drivers/drv_dac.c index e4462b0e78..3ed7aa6762 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_dac.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_dac.c @@ -43,7 +43,7 @@ static rt_err_t stm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t chan RT_ASSERT(device != RT_NULL); stm32_dac_handler = device->parent.user_data; -#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) +#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) HAL_DAC_Start(stm32_dac_handler, channel); #endif @@ -56,7 +56,7 @@ static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t cha RT_ASSERT(device != RT_NULL); stm32_dac_handler = device->parent.user_data; -#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) +#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) HAL_DAC_Stop(stm32_dac_handler, channel); #endif @@ -96,7 +96,7 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch rt_memset(&DAC_ChanConf, 0, sizeof(DAC_ChanConf)); -#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) +#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) if ((channel <= 2) && (channel > 0)) { /* set stm32 dac channel */ @@ -109,7 +109,7 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch } #endif -#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) +#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) DAC_ChanConf.DAC_Trigger = DAC_TRIGGER_NONE; DAC_ChanConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c index 2ebd013edd..1eee5b69a0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c @@ -338,7 +338,7 @@ int drv_lcd_hw_init(void) __exit: if (result != RT_EOK) { - rt_sem_delete(&_lcd.lcd_lock); + rt_sem_detach(&_lcd.lcd_lock); if (_lcd.lcd_info.framebuffer) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c index 52c184290e..81413d863a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c @@ -52,8 +52,12 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG; qspi_bus->QSPI_Handler = QSPI_Handler_config; +#if defined(SOC_SERIES_STM32MP1) + while (cfg->max_hz < HAL_RCC_GetACLKFreq() / (i + 1)) +#else while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1)) - { +#endif + { i++; if (i == 255) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c index 290c89e159..78928105cb 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c @@ -7,7 +7,8 @@ * Date Author Notes * 2018-06-22 tyx first * 2018-12-12 balanceTWK first version - * 2019-06-11 WillianChan Add SD card hot plug detection + * 2019-06-11 WillianChan Add SD card hot plug detection + * 2020-11-09 whj4674672 fix sdio non-aligned access problem */ #include "board.h" @@ -352,7 +353,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) /** * @brief This function send sdio request. - * @param sdio rthw_sdio + * @param host rt_mmcsd_host * @param req request * @retval None */ @@ -366,7 +367,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r if (req->cmd != RT_NULL) { - memset(&pkg, 0, sizeof(pkg)); + rt_memset(&pkg, 0, sizeof(pkg)); data = req->cmd->data; pkg.cmd = req->cmd; @@ -382,7 +383,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r pkg.buff = cache_buf; if (data->flags & DATA_DIR_WRITE) { - memcpy(cache_buf, data->buf, size); + rt_memcpy(cache_buf, data->buf, size); } } } @@ -391,13 +392,13 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) { - memcpy(data->buf, cache_buf, data->blksize * data->blks); + rt_memcpy(data->buf, cache_buf, data->blksize * data->blks); } } if (req->stop != RT_NULL) { - memset(&pkg, 0, sizeof(pkg)); + rt_memset(&pkg, 0, sizeof(pkg)); pkg.cmd = req->stop; rthw_sdio_send_command(sdio, &pkg); } @@ -524,11 +525,11 @@ void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) } /** - * @brief This function delect sdcard. + * @brief This function detect sdcard. * @param host rt_mmcsd_host * @retval 0x01 */ -static rt_int32_t rthw_sd_delect(struct rt_mmcsd_host *host) +static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host) { LOG_D("try to detect device"); return 0x01; @@ -604,7 +605,7 @@ static const struct rt_mmcsd_host_ops ops = { rthw_sdio_request, rthw_sdio_iocfg, - rthw_sd_delect, + rthw_sd_detect, rthw_sdio_irq_update, }; diff --git a/bsp/stm32/libraries/STM32F0xx_HAL/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h b/bsp/stm32/libraries/STM32F0xx_HAL/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h index f09577117a..e9747eeadb 100644 --- a/bsp/stm32/libraries/STM32F0xx_HAL/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h +++ b/bsp/stm32/libraries/STM32F0xx_HAL/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h @@ -44,7 +44,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32F0xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h index 32f2dd4a77..ba2f673e8b 100644 --- a/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +++ b/bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h @@ -28,7 +28,6 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32F1xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h index 345d1305b9..1fa049d31c 100644 --- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h +++ b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h @@ -28,7 +28,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f2xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32F2xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript index cb9fcd81c7..00db00252b 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript @@ -58,6 +58,10 @@ if GetDepend(['RT_USING_ADC']): src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c'] src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c'] +if GetDepend(['RT_USING_DAC']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c'] + if GetDepend(['RT_USING_RTC']): src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c'] src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c'] diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h index a8af863dd6..5b800df7de 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h +++ b/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -28,7 +28,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32F4xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h index 9f81701a62..4df6fe3128 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h @@ -28,7 +28,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32F7xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h index 499a9d2c53..e7e964dfa4 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h +++ b/bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h @@ -28,7 +28,6 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g0xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32G0xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h b/bsp/stm32/libraries/STM32G4xx_HAL/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h index d80b278be3..fcff7098aa 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h +++ b/bsp/stm32/libraries/STM32G4xx_HAL/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h @@ -28,7 +28,6 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32G4xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/bsp/stm32/libraries/STM32H7xx_HAL/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h index 015519510d..094f7bfe8e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +++ b/bsp/stm32/libraries/STM32H7xx_HAL/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -28,7 +28,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32H7xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h index 9e8ea13b5c..13d3923cb4 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h +++ b/bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h @@ -28,7 +28,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32L0xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript index 2055b3558f..d3e360ddac 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript @@ -59,6 +59,10 @@ if GetDepend(['RT_USING_ADC']): src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c'] src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c'] +if GetDepend(['RT_USING_DAC']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c'] + if GetDepend(['RT_USING_RTC']): src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c'] src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c'] diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h b/bsp/stm32/libraries/STM32L4xx_HAL/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h index 84d6d9c9b1..9643b494d4 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h +++ b/bsp/stm32/libraries/STM32L4xx_HAL/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h @@ -28,7 +28,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_conf.h" -#include <rtthread.h> /** @addtogroup STM32L4xx_HAL_Driver * @{ diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript index 32ac00af16..a991e588d0 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript @@ -35,10 +35,6 @@ if GetDepend(['RT_USING_SERIAL']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c'] -#if GetDepend(['RT_USING_SPI']): -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c'] -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c'] - if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pccard.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pcd.c'] @@ -49,14 +45,6 @@ if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): if GetDepend(['RT_USING_CAN']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_can.c'] -#if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']): -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c'] -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c'] -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c'] - -if GetDepend(['BSP_USING_ETH']): - src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_eth.c'] - if GetDepend(['BSP_USING_WWDG']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_wwdg.c'] @@ -73,13 +61,14 @@ if GetDepend(['RT_USING_WDT']): if GetDepend(['RT_USING_SDIO']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_delayblock.c'] if GetDepend(['RT_USING_AUDIO']): - src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s.c'] - src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s_ex.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai_ex.c'] - +if GetDepend(['BSP_USING_DCMI']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dcmi.c'] + if GetDepend(['BSP_USING_FMC']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fmc.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fsmc.c'] @@ -102,6 +91,34 @@ if GetDepend(['BSP_USING_LTDC']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_dma2d.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dsi.c'] +if GetDepend(['BSP_USING_FDCAN']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c'] + +if GetDepend(['BSP_USING_QSPI']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c'] + +if GetDepend(['BSP_USING_SPDIFRX']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spdifrx.c'] + +if GetDepend(['BSP_USING_DFSDM']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dfsdm.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dfsdm_ex.c'] + +if GetDepend(['BSP_USING_HASH']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hash.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hash_ex.c'] + +if GetDepend(['BSP_USING_CRC']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc_ex.c'] + +if GetDepend(['BSP_USING_RNG']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rng.c'] + +if GetDepend(['BSP_USING_CRYP']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp_ex.c'] + path = [cwd + '/STM32MP1xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32MP1xx/Include', cwd + '/CMSIS/Core/Include', diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c b/bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c index 59044a2669..a7a01539d8 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c +++ b/bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c @@ -3236,7 +3236,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) { SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); } - loop += 8U; + loop ++; } if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) @@ -3351,7 +3351,7 @@ uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) { SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); } - loop += 8U; + loop ++; } if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) diff --git a/bsp/stm32/stm32f401-st-nucleo/README.md b/bsp/stm32/stm32f401-st-nucleo/README.md index d65c08ac11..5029651c1a 100644 --- a/bsp/stm32/stm32f401-st-nucleo/README.md +++ b/bsp/stm32/stm32f401-st-nucleo/README.md @@ -1,4 +1,4 @@ -# STM32F401 Nucleo-64 BSP (Board Support Package) Execution Instruction +# STM32F401 Nucleo-64 BSP Introduction [中文页](README_zh.md) | @@ -33,9 +33,11 @@ The mainly-used **on-board resources** are shown as follows: - Common-used interface: USB, Arduino Uno, and ST morpho - Debug interface: ST-LINK/V2-1 -For more details about this board, please refer to the ST official documentation: [STM32 Nucleo-64 development board with STM32F401RE MCU](https://www.st.com/zh/evaluation-tools/nucleo-f401re.html) +#### For more details about this board, please refer to the [ST official documentation](https://www.st.com/zh/evaluation-tools/nucleo-f401re.html) -## Peripheral Condition + + +### Peripheral Condition Each peripheral supporting condition for this BSP is as follows: @@ -45,11 +47,11 @@ Each peripheral supporting condition for this BSP is as follows: | UART | Support | UART2 | | SPI | Support | SPI1 | -## Execution Instruction -### Quickly Get Started -This BSP provides MDK5 and IAR projects for developers. Also support GCC development environment Here's an example of the MDK5 development environment, to introduce how to run the system. +## Quickly Get Started + +This BSP provides MDK5 and IAR projects for developers. Also support GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system. #### Hardware Connection @@ -57,7 +59,7 @@ Use a Type-A to Mini-B cable to connect the development board to the PC and turn #### Compile And Download -Double-click the project.uvprojx file, to open the MDK5 project, compile and download the program to the board. +Double-click the `project.uvprojx` file, to open the MDK5 project, compile and download the program to the board. > By default, the project uses ST_LINK simulator to download the program, when the ST_LINK connects the board, clicking the download button can download the program to the board. @@ -93,8 +95,6 @@ This BSP only enables GPIO and serial port 2 by default. If need more advanced f According to the pin number specification, in the new stm32 bsp framework, the GPIO driver is managed in a sequential numbering manner. -## Notes - The pin serial number corresponds to the pin name as shown in the following table: | STM32 Pin Name | Pin Sequence Number | @@ -104,3 +104,8 @@ The pin serial number corresponds to the pin name as shown in the following tabl | PC0 - PC15 | 32 - 47 | | PD0 - ... | 48 - ... | + + +## Maintained By + +[shaoguoji](https://github.com/shaoguoji) [email protected] diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject index aac1f3438e..85c79639c9 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject @@ -1,11 +1,5 @@ -[PreviousGenFiles] -HeaderPath=D:/rt_thread_learn/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc -HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=D:/rt_thread_learn/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src -SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; - [PreviousLibFiles] -LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c; [PreviousUsedKeilFiles] SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; @@ -15,3 +9,9 @@ CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [] SourceFiles=;; +[PreviousGenFiles] +HeaderPath=G:/workspaces/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc +HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=G:/workspaces/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src +SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc index 0637ec0fe2..02fb59d94c 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc @@ -1,442 +1,441 @@ #MicroXplorer Configuration settings - do not modify -PH0-OSC_IN.Signal=RCC_OSC_IN -SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1 -SPI1.VirtualType=VM_MASTER -SPI2.VirtualType=VM_MASTER -PB10.Mode=Asynchronous -PG4.Signal=FSMC_A14 -RCC.PLLCLKFreq_Value=168000000 -PC12.Signal=SDIO_CK -SH.FSMC_NWE.0=FSMC_NWE,Sram1 -RCC.PLLQCLKFreq_Value=48000000 -PG0.Signal=FSMC_A10 -VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled -RCC.RTCFreq_Value=32768 -PC5.Mode=RMII -USART1.IPParameters=VirtualMode -PB13.Signal=SPI2_SCK -PG13.Signal=ETH_TXD0 -PinOutPanel.RotationAngle=0 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +ETH.IPParameters=MediaInterface +ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII +FSMC.IPParameters=WriteOperation1 +FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.Family=STM32F4 +Mcu.IP0=DAC +Mcu.IP1=ETH +Mcu.IP10=SYS +Mcu.IP11=TIM2 +Mcu.IP12=TIM4 +Mcu.IP13=TIM11 +Mcu.IP14=TIM13 +Mcu.IP15=TIM14 +Mcu.IP16=USART1 +Mcu.IP17=USART3 +Mcu.IP18=USB_OTG_FS +Mcu.IP2=FSMC +Mcu.IP3=IWDG +Mcu.IP4=NVIC +Mcu.IP5=RCC +Mcu.IP6=RTC +Mcu.IP7=SDIO +Mcu.IP8=SPI1 +Mcu.IP9=SPI2 +Mcu.IPNb=19 +Mcu.Name=STM32F407Z(E-G)Tx +Mcu.Package=LQFP144 +Mcu.Pin0=PC14-OSC32_IN +Mcu.Pin1=PC15-OSC32_OUT +Mcu.Pin10=PC1 +Mcu.Pin11=PC2 +Mcu.Pin12=PC3 +Mcu.Pin13=PA1 +Mcu.Pin14=PA2 +Mcu.Pin15=PA3 +Mcu.Pin16=PA4 +Mcu.Pin17=PA5 +Mcu.Pin18=PA7 +Mcu.Pin19=PC4 +Mcu.Pin2=PF0 +Mcu.Pin20=PC5 +Mcu.Pin21=PF12 +Mcu.Pin22=PF13 +Mcu.Pin23=PF14 +Mcu.Pin24=PF15 +Mcu.Pin25=PG0 +Mcu.Pin26=PG1 +Mcu.Pin27=PE7 +Mcu.Pin28=PE8 +Mcu.Pin29=PE9 +Mcu.Pin3=PF1 +Mcu.Pin30=PE10 +Mcu.Pin31=PE11 +Mcu.Pin32=PE12 +Mcu.Pin33=PE13 +Mcu.Pin34=PE14 +Mcu.Pin35=PE15 +Mcu.Pin36=PB10 +Mcu.Pin37=PB11 +Mcu.Pin38=PB13 +Mcu.Pin39=PD8 +Mcu.Pin4=PF2 +Mcu.Pin40=PD9 +Mcu.Pin41=PD10 +Mcu.Pin42=PD11 +Mcu.Pin43=PD12 +Mcu.Pin44=PD13 +Mcu.Pin45=PD14 +Mcu.Pin46=PD15 +Mcu.Pin47=PG2 +Mcu.Pin48=PG3 +Mcu.Pin49=PG4 +Mcu.Pin5=PF3 +Mcu.Pin50=PG5 +Mcu.Pin51=PC8 +Mcu.Pin52=PC9 +Mcu.Pin53=PA9 +Mcu.Pin54=PA10 +Mcu.Pin55=PA11 +Mcu.Pin56=PA12 +Mcu.Pin57=PA13 +Mcu.Pin58=PA14 +Mcu.Pin59=PC10 +Mcu.Pin6=PF4 +Mcu.Pin60=PC11 +Mcu.Pin61=PC12 +Mcu.Pin62=PD0 +Mcu.Pin63=PD1 +Mcu.Pin64=PD2 +Mcu.Pin65=PD4 +Mcu.Pin66=PD5 +Mcu.Pin67=PG10 +Mcu.Pin68=PG11 +Mcu.Pin69=PG13 +Mcu.Pin7=PF5 +Mcu.Pin70=PG14 +Mcu.Pin71=PB3 +Mcu.Pin72=PB4 +Mcu.Pin73=PB5 +Mcu.Pin74=PB6 +Mcu.Pin75=PB7 +Mcu.Pin76=PE0 +Mcu.Pin77=PE1 +Mcu.Pin78=VP_IWDG_VS_IWDG +Mcu.Pin79=VP_RTC_VS_RTC_Activate +Mcu.Pin8=PH0-OSC_IN +Mcu.Pin80=VP_SYS_VS_Systick +Mcu.Pin81=VP_TIM2_VS_ClockSourceINT +Mcu.Pin82=VP_TIM11_VS_ClockSourceINT +Mcu.Pin83=VP_TIM13_VS_ClockSourceINT +Mcu.Pin84=VP_TIM14_VS_ClockSourceINT +Mcu.Pin9=PH1-OSC_OUT +Mcu.PinsNb=85 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F407ZGTx +MxCube.Version=6.0.1 +MxDb.Version=DB.6.0.0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SPI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false -SH.FSMC_A15.ConfNb=1 -SH.FSMC_A11.ConfNb=1 -SPI1.Direction=SPI_DIRECTION_2LINES -TIM2.IPParameters=Channel-PWM Generation4 CH4 -PD4.Signal=FSMC_NOE -RCC.APB2TimFreq_Value=168000000 -PB6.Signal=S_TIM4_CH1 -SPI1.CalculateBaudRate=42.0 MBits/s -PC3.Signal=SPI2_MOSI -PD0.Signal=FSMC_D2_DA2 -PD8.Signal=FSMC_D13_DA13 -VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT -PE1.Signal=FSMC_NBL1 -SH.FSMC_D4_DA4.ConfNb=1 -ProjectManager.ProjectBuild=false -PG13.Locked=true +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA11.Mode=Device_Only +PA11.Signal=USB_OTG_FS_DM +PA12.Mode=Device_Only +PA12.Signal=USB_OTG_FS_DP +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA3.Signal=S_TIM2_CH4 +PA4.Signal=COMP_DAC1_group +PA5.Locked=true +PA5.Signal=COMP_DAC2_group +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB10.Mode=Asynchronous +PB10.Signal=USART3_TX +PB11.Mode=Asynchronous +PB11.Signal=USART3_RX +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK +PB3.Locked=true PB3.Mode=Full_Duplex_Master -PG14.Mode=RMII -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0 -MxDb.Version=DB.5.0.60 -SH.FSMC_NOE.ConfNb=1 -ProjectManager.BackupPrevious=false -SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1 -PE9.Signal=FSMC_D6_DA6 -SH.FSMC_A0.0=FSMC_A0,19b-a1 -PC9.Mode=SD_4_bits_Wide_bus -SPI2.CalculateBaudRate=21.0 MBits/s -SH.S_TIM4_CH2.0=TIM4_CH2,Encoder_Interface +PB3.Signal=SPI1_SCK +PB4.Locked=true +PB4.Mode=Full_Duplex_Master +PB4.Signal=SPI1_MISO +PB5.Locked=true +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI1_MOSI PB6.Locked=true -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PF3.Signal=FSMC_A3 -PE10.Signal=FSMC_D7_DA7 -SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1 -ProjectManager.HalAssertFull=false -ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES -SH.FSMC_A0.ConfNb=1 -RCC.MCO2PinFreq_Value=168000000 -SH.FSMC_A8.ConfNb=1 -Mcu.Package=LQFP144 -PA5.Locked=true -SPI2.Mode=SPI_MODE_MASTER -SH.FSMC_D15_DA15.ConfNb=1 -FSMC.IPParameters=WriteOperation1 -PD12.Signal=FSMC_A17_ALE -SH.FSMC_D14_DA14.ConfNb=1 -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -USART3.IPParameters=VirtualMode -PA10.Signal=USART1_RX -VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +PB6.Signal=S_TIM4_CH1 +PB7.Locked=true +PB7.Signal=S_TIM4_CH2 +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 PC11.Mode=SD_4_bits_Wide_bus -SH.FSMC_A1.0=FSMC_A1,19b-a1 -RCC.APB2CLKDivider=RCC_HCLK_DIV2 -SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1 -SH.S_TIM4_CH1.0=TIM4_CH1,Encoder_Interface -PF14.Signal=FSMC_A8 -RCC.APB1TimFreq_Value=84000000 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -USB_OTG_FS.IPParameters=VirtualMode -PB13.Mode=Full_Duplex_Master -VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer -SH.S_TIM2_CH4.ConfNb=1 -NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true -SH.FSMC_D7_DA7.ConfNb=1 -PD15.Signal=FSMC_D1_DA1 -ProjectManager.CustomerFirmwarePackage= -PC4.Mode=RMII -SH.FSMC_A5.ConfNb=1 -Mcu.Pin80=VP_TIM2_VS_ClockSourceINT -SH.S_TIM4_CH1.ConfNb=1 -Mcu.Pin81=VP_TIM11_VS_ClockSourceINT -ProjectManager.ProjectFileName=CubeMX_Config.ioc -ADC1.Rank-0\#ChannelRegularConversion=1 -Mcu.Pin79=VP_SYS_VS_Systick -SH.FSMC_A2.0=FSMC_A2,19b-a1 -Mcu.PinsNb=84 -Mcu.Pin73=PB6 -Mcu.Pin74=PB7 -Mcu.Pin71=PB4 -Mcu.Pin72=PB5 -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master -Mcu.Pin77=VP_IWDG_VS_IWDG -PG5.Signal=FSMC_A15 -Mcu.Pin78=VP_RTC_VS_RTC_Activate -Mcu.Pin75=PE0 -Mcu.Pin76=PE1 -SH.FSMC_NBL1.ConfNb=1 -Mcu.Pin70=PB3 +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC2.Mode=Full_Duplex_Master PC2.Signal=SPI2_MISO -SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1 -SH.FSMC_D8_DA8.ConfNb=1 +PC3.Mode=Full_Duplex_Master +PC3.Signal=SPI2_MOSI +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 +PD0.Signal=FSMC_D2_DA2 PD1.Signal=FSMC_D3_DA3 -SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1 -Mcu.Pin68=PG13 -Mcu.Pin69=PG14 -RCC.APB1CLKDivider=RCC_HCLK_DIV4 -PC14-OSC32_IN.Signal=RCC_OSC32_IN -Mcu.Pin62=PD1 -PG14.Locked=true -Mcu.Pin63=PD2 -Mcu.Pin60=PC12 -Mcu.Pin61=PD0 -Mcu.Pin66=PG10 -Mcu.Pin67=PG11 -Mcu.Pin64=PD4 -Mcu.Pin65=PD5 -PG10.Signal=FSMC_NE3 -SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1 -ETH.IPParameters=MediaInterface PD10.Signal=FSMC_D15_DA15 -Mcu.Pin59=PC11 -SH.FSMC_A14.ConfNb=1 -Mcu.Pin57=PA14 -Mcu.Pin58=PC10 -PB11.Mode=Asynchronous -SH.FSMC_A3.0=FSMC_A3,19b-a1 -SH.FSMC_A15.0=FSMC_A15,19b-a1 -SH.FSMC_D5_DA5.ConfNb=1 -Mcu.Pin51=PC9 -SH.FSMC_A10.ConfNb=1 -Mcu.Pin52=PA9 -Mcu.Pin50=PC8 -Mcu.Pin55=PA12 -Mcu.Pin56=PA13 -Mcu.Pin53=PA10 -Mcu.Pin54=PA11 -SH.FSMC_A3.ConfNb=1 -PA9.Signal=USART1_TX -PB5.Locked=true -Mcu.Pin48=PG4 -Mcu.Pin49=PG5 -Mcu.Pin46=PG2 -Mcu.Pin47=PG3 -PB10.Signal=USART3_TX -PA5.Signal=ADCx_IN5 -Mcu.Pin40=PD10 -Mcu.Pin41=PD11 -Mcu.Pin44=PD14 -PC12.Mode=SD_4_bits_Wide_bus -SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1 -Mcu.Pin45=PD15 -Mcu.Pin42=PD12 -Mcu.Pin43=PD13 -ProjectManager.LastFirmware=true -SH.FSMC_D3_DA3.ConfNb=1 -NVIC.SPI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true -VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer -PA1.Mode=RMII +PD11.Signal=FSMC_A16_CLE +PD12.Signal=FSMC_A17_ALE +PD13.Signal=FSMC_A18 +PD14.Signal=FSMC_D0_DA0 +PD15.Signal=FSMC_D1_DA1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD +PD4.Signal=FSMC_NOE +PD5.Signal=FSMC_NWE +PD8.Signal=FSMC_D13_DA13 +PD9.Signal=FSMC_D14_DA14 +PE0.Signal=FSMC_NBL0 +PE1.Signal=FSMC_NBL1 +PE10.Signal=FSMC_D7_DA7 +PE11.Signal=FSMC_D8_DA8 +PE12.Signal=FSMC_D9_DA9 +PE13.Signal=FSMC_D10_DA10 PE14.Signal=FSMC_D11_DA11 PE15.Signal=FSMC_D12_DA12 -Mcu.Pin37=PB13 -Mcu.Pin38=PD8 -Mcu.Pin35=PB10 +PE7.Signal=FSMC_D4_DA4 PE8.Signal=FSMC_D5_DA5 -Mcu.Pin36=PB11 -SPI1.Mode=SPI_MODE_MASTER -SH.FSMC_A18.0=FSMC_A18,19b-a1 -Mcu.Pin39=PD9 -Mcu.Pin30=PE11 -SH.FSMC_A4.0=FSMC_A4,19b-a1 -RCC.EthernetFreq_Value=168000000 -Mcu.Pin33=PE14 -Mcu.Pin34=PE15 -Mcu.Pin31=PE12 -RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE -Mcu.Pin32=PE13 -SH.FSMC_A4.ConfNb=1 -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PE9.Signal=FSMC_D6_DA6 +PF0.Signal=FSMC_A0 +PF1.Signal=FSMC_A1 +PF12.Signal=FSMC_A6 PF13.Signal=FSMC_A7 -PA13.Mode=Serial_Wire -ProjectManager.FreePins=false -Mcu.Pin26=PE7 -Mcu.Pin27=PE8 -RCC.RTCHSEDivFreq_Value=4000000 -Mcu.Pin24=PG0 -ProjectManager.UnderRoot=false -Mcu.Pin25=PG1 -SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1 -Mcu.Pin28=PE9 -PC8.Mode=SD_4_bits_Wide_bus -Mcu.Pin29=PE10 -PB4.Locked=true -Mcu.Pin22=PF14 -PB5.Signal=SPI1_MOSI -ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII -Mcu.Pin23=PF15 -Mcu.Pin20=PF12 -ADC1.master=1 -Mcu.Pin21=PF13 -NVIC.ForceEnableDMAVector=true -PD11.Signal=FSMC_A16_CLE -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false -USART1.VirtualMode=VM_ASYNC -ProjectManager.CompilerOptimize=6 +PF14.Signal=FSMC_A8 +PF15.Signal=FSMC_A9 +PF2.Signal=FSMC_A2 +PF3.Signal=FSMC_A3 +PF4.Signal=FSMC_A4 +PF5.Signal=FSMC_A5 +PG0.Signal=FSMC_A10 +PG1.Signal=FSMC_A11 +PG10.Mode=NorPsramChipSelect3_1 +PG10.Signal=FSMC_NE3 +PG11.Locked=true PG11.Mode=RMII -PA11.Signal=USB_OTG_FS_DM -SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1 -ProjectManager.HeapSize=0x200 -Mcu.Pin15=PA3 -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -Mcu.Pin16=PA5 -Mcu.Pin13=PA1 -Mcu.Pin14=PA2 -Mcu.Pin19=PC5 +PG11.Signal=ETH_TX_EN +PG13.Locked=true +PG13.Mode=RMII +PG13.Signal=ETH_TXD0 +PG14.Locked=true +PG14.Mode=RMII +PG14.Signal=ETH_TXD1 +PG2.Signal=FSMC_A12 +PG3.Signal=FSMC_A13 +PG4.Signal=FSMC_A14 +PG5.Signal=FSMC_A15 +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false -Mcu.Pin17=PA7 -Mcu.Pin18=PC4 -SH.FSMC_D1_DA1.ConfNb=1 -SH.ADCx_IN5.0=ADC1_IN5,IN5 -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -SH.FSMC_A5.0=FSMC_A5,19b-a1 -Mcu.Pin11=PC2 -Mcu.Pin12=PC3 -Mcu.Pin10=PC1 -SH.FSMC_NBL0.ConfNb=1 -SH.ADCx_IN5.ConfNb=1 -PF4.Signal=FSMC_A4 -PD2.Signal=SDIO_CMD -PC1.Signal=ETH_MDC -PC1.Mode=RMII -SH.FSMC_A9.ConfNb=1 -SH.FSMC_D10_DA10.ConfNb=1 -Mcu.Family=STM32F4 -PC3.Mode=Full_Duplex_Master -ProjectManager.MainLocation=Src -SH.S_TIM4_CH2.ConfNb=1 -RCC.CortexFreq_Value=168000000 -SH.FSMC_A12.0=FSMC_A12,19b-a1 +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F407ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.2 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true -Mcu.UserName=STM32F407ZGTx -SH.FSMC_A6.0=FSMC_A6,19b-a1 -PG2.Signal=FSMC_A12 -PC10.Signal=SDIO_D2 -VP_IWDG_VS_IWDG.Mode=IWDG_Activate -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,11-MX_TIM13_Init-TIM13-false-HAL-true,12-MX_TIM11_Init-TIM11-false-HAL-true,13-MX_SDIO_SD_Init-SDIO-false-HAL-true,14-MX_TIM2_Init-TIM2-false-HAL-true,15-MX_SPI2_Init-SPI2-false-HAL-true,16-MX_TIM4_Init-TIM4-false-HAL-true,17-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,18-MX_FSMC_Init-FSMC-false-HAL-true -SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1 -PA11.Mode=Device_Only -PB11.Signal=USART3_RX -PG11.Signal=ETH_TX_EN +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 -PD13.Signal=FSMC_A18 -Mcu.IP4=NVIC -Mcu.IP5=RCC +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,11-MX_TIM13_Init-TIM13-false-HAL-true,12-MX_TIM11_Init-TIM11-false-HAL-true,13-MX_SDIO_SD_Init-SDIO-false-HAL-true,14-MX_TIM2_Init-TIM2-false-HAL-true,15-MX_SPI2_Init-SPI2-false-HAL-true,16-MX_TIM4_Init-TIM4-false-HAL-true,17-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,18-MX_FSMC_Init-FSMC-false-HAL-true +RCC.48MHZClocksFreq_Value=48000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 RCC.FCLKCortexFreq_Value=168000000 -Mcu.IP2=FSMC -Mcu.IP3=IWDG -Mcu.IP0=ADC1 -Mcu.IP1=ETH -PA12.Signal=USB_OTG_FS_DP -SH.FSMC_A11.0=FSMC_A11,19b-a1 -Mcu.UserConstants= -RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE -SH.FSMC_A7.0=FSMC_A7,19b-a1 -Mcu.ThirdPartyNb=0 +RCC.FamilyName=M RCC.HCLKFreq_Value=168000000 -Mcu.IPNb=19 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=192000000 -ProjectManager.PreviousToolchain= +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLM=4 +RCC.PLLN=168 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE +RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 +RCC.RTCHSEDivFreq_Value=4000000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=336000000 RCC.VcooutputI2S=192000000 -PF12.Signal=FSMC_A6 -Mcu.Pin6=PF4 -Mcu.Pin7=PF5 -Mcu.Pin8=PH0-OSC_IN -Mcu.Pin9=PH1-OSC_OUT +SH.COMP_DAC1_group.0=DAC_OUT1,DAC_OUT1 +SH.COMP_DAC1_group.ConfNb=1 +SH.COMP_DAC2_group.0=DAC_OUT2,DAC_OUT2 +SH.COMP_DAC2_group.ConfNb=1 +SH.FSMC_A0.0=FSMC_A0,19b-a1 +SH.FSMC_A0.ConfNb=1 +SH.FSMC_A1.0=FSMC_A1,19b-a1 +SH.FSMC_A1.ConfNb=1 SH.FSMC_A10.0=FSMC_A10,19b-a1 -RCC.AHBFreq_Value=168000000 -PH0-OSC_IN.Mode=HSE-External-Oscillator -Mcu.Pin0=PC14-OSC32_IN -Mcu.Pin1=PC15-OSC32_OUT -GPIO.groupedBy=Group By Peripherals -Mcu.Pin2=PF0 -Mcu.Pin3=PF1 -SH.FSMC_D12_DA12.ConfNb=1 -Mcu.Pin4=PF2 -Mcu.Pin5=PF3 -ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5 -RCC.HSE_VALUE=8000000 -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false -Mcu.IP10=SYS -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -Mcu.IP12=TIM4 -SH.FSMC_D6_DA6.ConfNb=1 -Mcu.IP11=TIM2 +SH.FSMC_A10.ConfNb=1 +SH.FSMC_A11.0=FSMC_A11,19b-a1 +SH.FSMC_A11.ConfNb=1 +SH.FSMC_A12.0=FSMC_A12,19b-a1 +SH.FSMC_A12.ConfNb=1 +SH.FSMC_A13.0=FSMC_A13,19b-a1 +SH.FSMC_A13.ConfNb=1 +SH.FSMC_A14.0=FSMC_A14,19b-a1 +SH.FSMC_A14.ConfNb=1 +SH.FSMC_A15.0=FSMC_A15,19b-a1 +SH.FSMC_A15.ConfNb=1 +SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1 SH.FSMC_A16_CLE.ConfNb=1 -SH.FSMC_NBL0.0=FSMC_NBL0,2ByteEnable1 +SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1 SH.FSMC_A17_ALE.ConfNb=1 -Mcu.IP18=USB_OTG_FS -Mcu.IP17=USART3 -Mcu.IP14=TIM13 -PB4.Mode=Full_Duplex_Master -Mcu.IP13=TIM11 -PE13.Signal=FSMC_D10_DA10 -Mcu.IP16=USART1 +SH.FSMC_A18.0=FSMC_A18,19b-a1 +SH.FSMC_A18.ConfNb=1 +SH.FSMC_A2.0=FSMC_A2,19b-a1 +SH.FSMC_A2.ConfNb=1 +SH.FSMC_A3.0=FSMC_A3,19b-a1 +SH.FSMC_A3.ConfNb=1 +SH.FSMC_A4.0=FSMC_A4,19b-a1 +SH.FSMC_A4.ConfNb=1 +SH.FSMC_A5.0=FSMC_A5,19b-a1 +SH.FSMC_A5.ConfNb=1 +SH.FSMC_A6.0=FSMC_A6,19b-a1 +SH.FSMC_A6.ConfNb=1 +SH.FSMC_A7.0=FSMC_A7,19b-a1 +SH.FSMC_A7.ConfNb=1 +SH.FSMC_A8.0=FSMC_A8,19b-a1 +SH.FSMC_A8.ConfNb=1 +SH.FSMC_A9.0=FSMC_A9,19b-a1 +SH.FSMC_A9.ConfNb=1 +SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1 +SH.FSMC_D0_DA0.ConfNb=1 +SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1 +SH.FSMC_D10_DA10.ConfNb=1 +SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1 +SH.FSMC_D11_DA11.ConfNb=1 +SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1 +SH.FSMC_D12_DA12.ConfNb=1 +SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1 +SH.FSMC_D13_DA13.ConfNb=1 SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1 -Mcu.IP15=TIM14 -PC14-OSC32_IN.Mode=LSE-External-Oscillator -RCC.VCOInputFreq_Value=2000000 -SH.FSMC_A14.0=FSMC_A14,19b-a1 -PA14.Mode=Serial_Wire +SH.FSMC_D14_DA14.ConfNb=1 +SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1 +SH.FSMC_D15_DA15.ConfNb=1 +SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1 +SH.FSMC_D1_DA1.ConfNb=1 +SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1 +SH.FSMC_D2_DA2.ConfNb=1 +SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1 +SH.FSMC_D3_DA3.ConfNb=1 +SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1 +SH.FSMC_D4_DA4.ConfNb=1 +SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1 +SH.FSMC_D5_DA5.ConfNb=1 SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1 -PB5.Mode=Full_Duplex_Master -File.Version=6 +SH.FSMC_D6_DA6.ConfNb=1 +SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1 +SH.FSMC_D7_DA7.ConfNb=1 +SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1 +SH.FSMC_D8_DA8.ConfNb=1 +SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1 SH.FSMC_D9_DA9.ConfNb=1 -SH.FSMC_A8.0=FSMC_A8,19b-a1 -PB7.Signal=S_TIM4_CH2 -PG13.Mode=RMII -ProjectManager.ProjectName=CubeMX_Config -SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1 -PH1-OSC_OUT.Mode=HSE-External-Oscillator -SH.FSMC_A2.ConfNb=1 -PG11.Locked=true +SH.FSMC_NBL0.0=FSMC_NBL0,2ByteEnable1 +SH.FSMC_NBL0.ConfNb=1 SH.FSMC_NBL1.0=FSMC_NBL1,2ByteEnable1 -NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true -ProjectManager.ToolChainLocation= -RCC.LSI_VALUE=32000 -SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1 -USB_OTG_FS.VirtualMode=Device_Only -SH.FSMC_A13.0=FSMC_A13,19b-a1 -VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT -SH.FSMC_A13.ConfNb=1 -PF5.Signal=FSMC_A5 -SH.FSMC_A9.0=FSMC_A9,19b-a1 -SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1 +SH.FSMC_NBL1.ConfNb=1 +SH.FSMC_NOE.0=FSMC_NOE,Sram1 +SH.FSMC_NOE.ConfNb=1 +SH.FSMC_NWE.0=FSMC_NWE,Sram1 SH.FSMC_NWE.ConfNb=1 -SPI2.Direction=SPI_DIRECTION_2LINES -PF0.Signal=FSMC_A0 -PC5.Signal=ETH_RXD1 -PE7.Signal=FSMC_D4_DA4 -PB3.Locked=true -PB4.Signal=SPI1_MISO -Mcu.Pin82=VP_TIM13_VS_ClockSourceINT -Mcu.Pin83=VP_TIM14_VS_ClockSourceINT -PA3.Signal=S_TIM2_CH4 -VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate -PC15-OSC32_OUT.Mode=LSE-External-Oscillator -TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 -SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1 -PA7.Mode=RMII -PA10.Mode=Asynchronous -VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT -FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE -ProjectManager.NoMain=false +SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 +SH.S_TIM2_CH4.ConfNb=1 +SH.S_TIM4_CH1.0=TIM4_CH1,Encoder_Interface +SH.S_TIM4_CH1.ConfNb=1 +SH.S_TIM4_CH2.0=TIM4_CH2,Encoder_Interface +SH.S_TIM4_CH2.ConfNb=1 +SPI1.CalculateBaudRate=42.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -PG3.Signal=FSMC_A13 -PG1.Signal=FSMC_A11 -PC11.Signal=SDIO_D3 -PC8.Signal=SDIO_D0 -PC4.Signal=ETH_RXD0 -PC10.Mode=SD_4_bits_Wide_bus -PG10.Mode=NorPsramChipSelect3_1 -ProjectManager.DefaultFWLocation=true -PC2.Mode=Full_Duplex_Master -PD9.Signal=FSMC_D14_DA14 -PD5.Signal=FSMC_NWE -SH.FSMC_D11_DA11.ConfNb=1 -ProjectManager.DeletePrevious=true -RCC.FamilyName=M -VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer -PA13.Signal=SYS_JTMS-SWDIO -SH.FSMC_D13_DA13.ConfNb=1 -PA9.Mode=Asynchronous -ProjectManager.TargetToolchain=MDK-ARM V5 -SH.FSMC_A18.ConfNb=1 +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +SPI2.CalculateBaudRate=21.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -PF2.Signal=FSMC_A2 -PE11.Signal=FSMC_D8_DA8 -PC15-OSC32_OUT.Signal=RCC_OSC32_OUT -PA1.Signal=ETH_REF_CLK -RCC.VCOI2SOutputFreq_Value=384000000 -PD2.Mode=SD_4_bits_Wide_bus -SH.FSMC_A7.ConfNb=1 -PG14.Signal=ETH_TXD1 -board=custom -SH.FSMC_D0_DA0.ConfNb=1 -RCC.VCOOutputFreq_Value=336000000 -RCC.APB2Freq_Value=84000000 -MxCube.Version=5.6.0 -VP_TIM2_VS_ClockSourceINT.Mode=Internal -VP_SYS_VS_Systick.Mode=SysTick -PH1-OSC_OUT.Signal=RCC_OSC_OUT -PF15.Signal=FSMC_A9 -PF1.Signal=FSMC_A1 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S -ProjectManager.AskForMigrate=true -Mcu.Name=STM32F407Z(E-G)Tx -PE0.Signal=FSMC_NBL0 -PE12.Signal=FSMC_D9_DA9 -PA2.Signal=ETH_MDIO -Mcu.IP8=SPI1 -Mcu.IP9=SPI2 -PD14.Signal=FSMC_D0_DA0 -Mcu.IP6=RTC -Mcu.IP7=SDIO -ProjectManager.CoupleFile=false -RCC.48MHZClocksFreq_Value=48000000 -PB3.Signal=SPI1_SCK -RCC.SYSCLKFreq_VALUE=168000000 -SH.FSMC_A6.ConfNb=1 -PA12.Mode=Device_Only -KeepUserPlacement=false +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM2.IPParameters=Channel-PWM Generation4 CH4 +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +USART3.IPParameters=VirtualMode USART3.VirtualMode=VM_ASYNC +USB_OTG_FS.IPParameters=VirtualMode +USB_OTG_FS.VirtualMode=Device_Only +VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG -PA14.Signal=SYS_JTCK-SWCLK -SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 -SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1 -SH.FSMC_NOE.0=FSMC_NOE,Sram1 -SH.FSMC_A12.ConfNb=1 -SH.FSMC_D2_DA2.ConfNb=1 -RCC.HSI_VALUE=16000000 -RCC.PLLQ=7 -ADC1.NbrOfConversionFlag=1 -RCC.PLLM=4 -RCC.PLLN=168 -PB7.Locked=true -PA2.Mode=RMII -PC9.Signal=SDIO_D1 -RCC.APB1Freq_Value=42000000 -ProjectManager.DeviceId=STM32F407ZGTx -ProjectManager.LibraryCopy=0 -PA7.Signal=ETH_CRS_DV -SH.FSMC_A1.ConfNb=1 +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +VP_TIM2_VS_ClockSourceINT.Mode=Internal +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT +board=custom diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 7733b60c42..ccb457f100 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f4xx_hal_conf_template.h * @author MCD Application Team - * @brief HAL configuration template file. + * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f4xx_hal_conf.h. ****************************************************************************** @@ -17,7 +17,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -32,16 +32,17 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED - #define HAL_ADC_MODULE_ENABLED + /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED /* #define HAL_DCMI_MODULE_ENABLED */ /* #define HAL_DMA2D_MODULE_ENABLED */ #define HAL_ETH_MODULE_ENABLED @@ -90,9 +91,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -103,7 +104,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -112,7 +113,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -130,8 +131,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ @@ -144,16 +145,55 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -170,7 +210,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -178,9 +218,9 @@ /* Section 2: PHY configuration section */ -/* LAN8742A_PHY_ADDRESS Address*/ +/* LAN8742A_PHY_ADDRESS Address*/ #define LAN8742A_PHY_ADDRESS 1U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY ((uint32_t)0x000000FFU) /* PHY Configuration delay */ #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) @@ -192,7 +232,7 @@ #define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -207,7 +247,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */ @@ -215,7 +255,7 @@ #define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ #define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ +#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ /* ################## SPI peripheral configuration ########################## */ @@ -228,25 +268,25 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32f4xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32f4xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -259,18 +299,18 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ -#ifdef HAL_SMBUS_MODULE_ENABLED -#include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - #ifdef HAL_DMA2D_MODULE_ENABLED #include "stm32f4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ @@ -290,7 +330,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -305,11 +345,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -319,6 +359,10 @@ #include "stm32f4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + #ifdef HAL_I2S_MODULE_ENABLED #include "stm32f4xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ @@ -351,10 +395,6 @@ #include "stm32f4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - #ifdef HAL_SPI_MODULE_ENABLED #include "stm32f4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ @@ -390,7 +430,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -418,14 +458,18 @@ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32f4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ - + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -434,13 +478,12 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_CONF_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h index 44c3bafe0f..8c1f4cf3e1 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -39,7 +39,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c index 6d1ddd0123..b2964b0092 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c @@ -37,7 +37,6 @@ ****************************************************************************** */ /* USER CODE END Header */ - /* Includes ------------------------------------------------------------------*/ #include "main.h" @@ -62,7 +61,7 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ -ADC_HandleTypeDef hadc1; +DAC_HandleTypeDef hdac; ETH_HandleTypeDef heth; @@ -86,6 +85,8 @@ UART_HandleTypeDef huart3; PCD_HandleTypeDef hpcd_USB_OTG_FS; +SRAM_HandleTypeDef hsram1; + /* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/ @@ -98,7 +99,6 @@ static void MX_USART1_UART_Init(void); static void MX_SPI1_Init(void); static void MX_ETH_Init(void); static void MX_USART3_UART_Init(void); -static void MX_ADC1_Init(void); static void MX_RTC_Init(void); static void MX_IWDG_Init(void); static void MX_TIM14_Init(void); @@ -109,6 +109,8 @@ static void MX_TIM2_Init(void); static void MX_SPI2_Init(void); static void MX_TIM4_Init(void); static void MX_USB_OTG_FS_PCD_Init(void); +static void MX_FSMC_Init(void); +static void MX_DAC_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -128,7 +130,6 @@ int main(void) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ @@ -152,7 +153,6 @@ int main(void) MX_SPI1_Init(); MX_ETH_Init(); MX_USART3_UART_Init(); - MX_ADC1_Init(); MX_RTC_Init(); MX_IWDG_Init(); MX_TIM14_Init(); @@ -163,6 +163,8 @@ int main(void) MX_SPI2_Init(); MX_TIM4_Init(); MX_USB_OTG_FS_PCD_Init(); + MX_FSMC_Init(); + MX_DAC_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -190,11 +192,12 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -211,7 +214,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -233,52 +236,46 @@ void SystemClock_Config(void) } /** - * @brief ADC1 Initialization Function + * @brief DAC Initialization Function * @param None * @retval None */ -static void MX_ADC1_Init(void) +static void MX_DAC_Init(void) { - /* USER CODE BEGIN ADC1_Init 0 */ + /* USER CODE BEGIN DAC_Init 0 */ - /* USER CODE END ADC1_Init 0 */ + /* USER CODE END DAC_Init 0 */ - ADC_ChannelConfTypeDef sConfig = {0}; + DAC_ChannelConfTypeDef sConfig = {0}; - /* USER CODE BEGIN ADC1_Init 1 */ + /* USER CODE BEGIN DAC_Init 1 */ - /* USER CODE END ADC1_Init 1 */ - /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + /* USER CODE END DAC_Init 1 */ + /** DAC Initialization + */ + hdac.Instance = DAC; + if (HAL_DAC_Init(&hdac) != HAL_OK) + { + Error_Handler(); + } + /** DAC channel OUT1 config */ - hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - hadc1.Init.Resolution = ADC_RESOLUTION_12B; - hadc1.Init.ScanConvMode = DISABLE; - hadc1.Init.ContinuousConvMode = DISABLE; - hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.NbrOfConversion = 1; - hadc1.Init.DMAContinuousRequests = DISABLE; - hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - if (HAL_ADC_Init(&hadc1) != HAL_OK) + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK) { Error_Handler(); } - /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + /** DAC channel OUT2 config */ - sConfig.Channel = ADC_CHANNEL_5; - sConfig.Rank = 1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_2) != HAL_OK) { Error_Handler(); } - /* USER CODE BEGIN ADC1_Init 2 */ + /* USER CODE BEGIN DAC_Init 2 */ - /* USER CODE END ADC1_Init 2 */ + /* USER CODE END DAC_Init 2 */ } @@ -367,7 +364,7 @@ static void MX_RTC_Init(void) /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ - /** Initialize RTC Only + /** Initialize RTC Only */ hrtc.Instance = RTC; hrtc.Init.HourFormat = RTC_HOURFORMAT_24; @@ -520,7 +517,7 @@ static void MX_TIM2_Init(void) htim2.Instance = TIM2; htim2.Init.Prescaler = 0; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; - htim2.Init.Period = 0; + htim2.Init.Period = 4294967295; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim2) != HAL_OK) @@ -578,7 +575,7 @@ static void MX_TIM4_Init(void) htim4.Instance = TIM4; htim4.Init.Prescaler = 0; htim4.Init.CounterMode = TIM_COUNTERMODE_UP; - htim4.Init.Period = 0; + htim4.Init.Period = 65535; htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; sConfig.EncoderMode = TIM_ENCODERMODE_TI1; @@ -624,7 +621,7 @@ static void MX_TIM11_Init(void) htim11.Instance = TIM11; htim11.Init.Prescaler = 0; htim11.Init.CounterMode = TIM_COUNTERMODE_UP; - htim11.Init.Period = 0; + htim11.Init.Period = 65535; htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim11) != HAL_OK) @@ -655,7 +652,7 @@ static void MX_TIM13_Init(void) htim13.Instance = TIM13; htim13.Init.Prescaler = 0; htim13.Init.CounterMode = TIM_COUNTERMODE_UP; - htim13.Init.Period = 0; + htim13.Init.Period = 65535; htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim13) != HAL_OK) @@ -686,7 +683,7 @@ static void MX_TIM14_Init(void) htim14.Instance = TIM14; htim14.Init.Prescaler = 0; htim14.Init.CounterMode = TIM_COUNTERMODE_UP; - htim14.Init.Period = 0; + htim14.Init.Period = 65535; htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim14) != HAL_OK) @@ -810,14 +807,69 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); } +/* FSMC initialization function */ +static void MX_FSMC_Init(void) +{ + + /* USER CODE BEGIN FSMC_Init 0 */ + + /* USER CODE END FSMC_Init 0 */ + + FSMC_NORSRAM_TimingTypeDef Timing = {0}; + + /* USER CODE BEGIN FSMC_Init 1 */ + + /* USER CODE END FSMC_Init 1 */ + + /** Perform the SRAM1 memory initialization sequence + */ + hsram1.Instance = FSMC_NORSRAM_DEVICE; + hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + /* hsram1.Init */ + hsram1.Init.NSBank = FSMC_NORSRAM_BANK3; + hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; + hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; + hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE; + /* Timing */ + Timing.AddressSetupTime = 15; + Timing.AddressHoldTime = 15; + Timing.DataSetupTime = 255; + Timing.BusTurnAroundDuration = 15; + Timing.CLKDivision = 16; + Timing.DataLatency = 17; + Timing.AccessMode = FSMC_ACCESS_MODE_A; + /* ExtTiming */ + + if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) + { + Error_Handler( ); + } + + /* USER CODE BEGIN FSMC_Init 2 */ + + /* USER CODE END FSMC_Init 2 */ +} + /* USER CODE BEGIN 4 */ /* USER CODE END 4 */ @@ -845,7 +897,7 @@ void Error_Handler(void) * @retval None */ void assert_failed(uint8_t *file, uint32_t line) -{ +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index fa88cded20..08cc9f847e 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -100,62 +100,64 @@ void HAL_MspInit(void) } /** -* @brief ADC MSP Initialization +* @brief DAC MSP Initialization * This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer +* @param hdac: DAC handle pointer * @retval None */ -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hadc->Instance==ADC1) + if(hdac->Instance==DAC) { - /* USER CODE BEGIN ADC1_MspInit 0 */ + /* USER CODE BEGIN DAC_MspInit 0 */ - /* USER CODE END ADC1_MspInit 0 */ + /* USER CODE END DAC_MspInit 0 */ /* Peripheral clock enable */ - __HAL_RCC_ADC1_CLK_ENABLE(); - + __HAL_RCC_DAC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + /**DAC GPIO Configuration + PA4 ------> DAC_OUT1 + PA5 ------> DAC_OUT2 */ - GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - /* USER CODE BEGIN ADC1_MspInit 1 */ + /* USER CODE BEGIN DAC_MspInit 1 */ - /* USER CODE END ADC1_MspInit 1 */ + /* USER CODE END DAC_MspInit 1 */ } } /** -* @brief ADC MSP De-Initialization +* @brief DAC MSP De-Initialization * This function freeze the hardware resources used in this example -* @param hadc: ADC handle pointer +* @param hdac: DAC handle pointer * @retval None */ -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) { - if(hadc->Instance==ADC1) + if(hdac->Instance==DAC) { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ + /* USER CODE BEGIN DAC_MspDeInit 0 */ - /* USER CODE END ADC1_MspDeInit 0 */ + /* USER CODE END DAC_MspDeInit 0 */ /* Peripheral clock disable */ - __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 + __HAL_RCC_DAC_CLK_DISABLE(); + + /**DAC GPIO Configuration + PA4 ------> DAC_OUT1 + PA5 ------> DAC_OUT2 */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5); - /* USER CODE BEGIN ADC1_MspDeInit 1 */ + /* USER CODE BEGIN DAC_MspDeInit 1 */ - /* USER CODE END ADC1_MspDeInit 1 */ + /* USER CODE END DAC_MspDeInit 1 */ } } @@ -176,11 +178,11 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - /**ETH GPIO Configuration + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -189,7 +191,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PG11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -234,8 +236,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) /* USER CODE END ETH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration + + /**ETH GPIO Configuration PC1 ------> ETH_MDC PA1 ------> ETH_REF_CLK PA2 ------> ETH_MDIO @@ -244,7 +246,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) PC5 ------> ETH_RXD1 PG11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 - PG14 ------> ETH_TXD1 + PG14 ------> ETH_TXD1 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); @@ -319,18 +321,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -367,16 +369,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -404,12 +406,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PB3 ------> SPI1_SCK PB4 ------> SPI1_MISO - PB5 ------> SPI1_MOSI + PB5 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -432,13 +434,13 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB13 ------> SPI2_SCK + PB13 ------> SPI2_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -476,11 +478,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PB3 ------> SPI1_SCK PB4 ------> SPI1_MISO - PB5 ------> SPI1_MOSI + PB5 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); @@ -497,11 +499,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PC2 ------> SPI2_MISO PC3 ------> SPI2_MOSI - PB13 ------> SPI2_SCK + PB13 ------> SPI2_SCK */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); @@ -585,11 +587,11 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) /* USER CODE END TIM4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM4_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM4 GPIO Configuration + /**TIM4 GPIO Configuration PB6 ------> TIM4_CH1 - PB7 ------> TIM4_CH2 + PB7 ------> TIM4_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -613,10 +615,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM2 GPIO Configuration - PA3 ------> TIM2_CH4 + /**TIM2 GPIO Configuration + PA3 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -701,10 +703,10 @@ void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) /* USER CODE END TIM4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM4_CLK_DISABLE(); - - /**TIM4 GPIO Configuration + + /**TIM4 GPIO Configuration PB6 ------> TIM4_CH1 - PB7 ------> TIM4_CH2 + PB7 ------> TIM4_CH2 */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7); @@ -731,15 +733,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -758,15 +760,15 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); @@ -793,10 +795,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -813,10 +815,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB10 ------> USART3_TX - PB11 ------> USART3_RX + PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); @@ -841,11 +843,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -881,10 +883,10 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); @@ -911,8 +913,8 @@ static void HAL_FSMC_MspInit(void){ /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); - - /** FSMC GPIO Configuration + + /** FSMC GPIO Configuration PF0 ------> FSMC_A0 PF1 ------> FSMC_A1 PF2 ------> FSMC_A2 @@ -954,8 +956,8 @@ static void HAL_FSMC_MspInit(void){ PE0 ------> FSMC_NBL0 PE1 ------> FSMC_NBL1 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -963,7 +965,7 @@ static void HAL_FSMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FSMC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -971,8 +973,8 @@ static void HAL_FSMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FSMC; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -980,8 +982,8 @@ static void HAL_FSMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FSMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -1016,8 +1018,8 @@ static void HAL_FSMC_MspDeInit(void){ FSMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_DISABLE(); - - /** FSMC GPIO Configuration + + /** FSMC GPIO Configuration PF0 ------> FSMC_A0 PF1 ------> FSMC_A1 PF2 ------> FSMC_A2 @@ -1059,19 +1061,19 @@ static void HAL_FSMC_MspDeInit(void){ PE0 ------> FSMC_NBL0 PE1 ------> FSMC_NBL1 */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10); - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); /* USER CODE BEGIN FSMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c index 9832ed60e3..9e5e592d83 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -79,7 +79,7 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_FS; /* USER CODE END EV */ /******************************************************************************/ -/* Cortex-M4 Processor Interruption and Exception Handlers */ +/* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index 150fba5782..4811f373f0 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -273,6 +273,16 @@ menu "On-chip Peripheral Drivers" default 25 endif + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "Enable DAC1" + default n + endif + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC diff --git a/bsp/stm32/stm32f412-st-nucleo/README.md b/bsp/stm32/stm32f412-st-nucleo/README.md index 2502e29e29..fb463d6803 100644 --- a/bsp/stm32/stm32f412-st-nucleo/README.md +++ b/bsp/stm32/stm32f412-st-nucleo/README.md @@ -1,107 +1,88 @@ -# NUCLEO-F412ZG 开发板 BSP 说明 +# STM32F412-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 RT-Thread 开发团队为 NUCLEO-F412ZG 开发板提供的 BSP (板级支持包) 说明。 +## MCU: STM32F412ZG @100MHz, 1024KB FLASH, 256KB RAM -主要内容如下： +STM32F412xE/G devices are based on the high-performance Arm® Cortex® -M4 32-bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +STM32F412xE/G devices belong to the STM32 Dynamic Efficiency™ product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing even more power consumption saving during data batching. +STM32F412xE/G devices incorporate high-speed embedded memories (up to 1 Mbyte of Flash memory, 256 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. +All devices offer one 12-bit ADC, a low-power RTC, twelve general-purpose 16-bit timers, two PWM timers for motor control and two general-purpose 32-bit timers. +They also feature standard and advanced communication interfaces: +In addition, STM32F412xE/G devices embed advanced peripherals: +STM32F412xE/G devices are offered in 7 packages ranging from 48 to 144 pins. The set of available peripherals depends on the selected package. +The STM32F412xE/G operates in the -40 to +125 °C temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. +These features make the STM32F412xE/G microcontrollers suitable for a wide range of applications. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Dynamic Efficiency Line with BAM (Batch Acquisition Mode) +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Memories + - Up to 1 Mbyte of Flash memory + - 256 Kbyte of SRAM + - Flexible external static memory controller with up to 16-bit data bus: SRAM, PSRAM, NOR Flash memory + - Dual mode Quad-SPI interface +- LCD parallel interface, 8080/6800 modes +- Clock, reset and supply management + - 1.7 V to 3.6 V application supply and I/Os + - POR, PDR, PVD and BOR + - 4-to-26 MHz crystal oscillator + - Internal 16 MHz factory-trimmed RC + - 32 kHz oscillator for RTC with calibration + - Internal 32 kHz RC with calibration +- Power consumption + - Run: 112 μA/MHz (peripheral off) + - Stop (Flash in Stop mode, fast wakeup time): 50 μA Typ @ 25 °C; 75 μA max @25 °C + - Stop (Flash in Deep power down mode, slow wakeup time): down to 18 μA @ 25 °C; 40 μA max @25 °C + - Standby: 2.4 μA @25 °C / 1.7 V without RTC; 12 μA @85 °C @1.7 V + - VBAT supply for RTC: 1 μA @25 °C +- 1×12-bit, 2.4 MSPS ADC: up to 16 channels +- 2xdigital filters for sigma delta modulator, 4xPDM interfaces, stereo microphone support +- General-purpose DMA: 16-stream DMA -探索者 NUCLEO-F412ZG 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 100Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F411ZG 的芯片性能。 +- Up to 17 timers: up to twelve 16-bit timers, two 32-bit timers up to 100 MHz each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window), one SysTick timer +- Debug mode + - Serial wire debug (SWD) & JTAG + - Cortex®-M4 Embedded Trace Macrocell™ +- Up to 114 I/O ports with interrupt capability + - Up to 109 fast I/Os up to 100 MHz + - Up to 114 five V-tolerant I/Os +- Up to 17 communication interfaces + - Up to 4xI2C interfaces (SMBus/PMBus) + - Up to 4 USARTs (2x12.5 Mbit/s, 2x6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) + - Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or I2S audio protocol), out of which 2 muxed full-duplex I2S interfaces + - SDIO interface (SD/MMC/eMMC) + - Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with PHY + - 2xCAN (2.0B Active) +- True random number generator +- CRC calculation unit +- 96-bit unique ID +- RTC: subsecond accuracy, hardware calendar +- All packages are ECOPACK®2 -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32F412ZG，主频 100MHz，1024KB FLASH ，256KB RAM。 -- 常用外设 - - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 - - 按键，2 个，USER and RESET 。 -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 -- 调试接口，板载 ST-LINK/V2-1 调试器。 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) | +| [STM32F412ZG ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32f412zg.html#documentation) | STM32F412ZG datasheet and other resources | -开发板更多详细信息请参考意法半导体 [NUCLEO-F412ZG 开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f412zg.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **片上外设** | **支持情况** | **备注** | -| :------------ | :----------: | :-----------------------------------: | -| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | -| UART | 支持 | UART2,UART3 | -| Onchip Flash | 支持 | | -| USB Device | 支持 | | +[flybreak](https://github.com/guozhanxin) [email protected] -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用 Type-A to Micro-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、蓝色 LD2 会周期性闪烁。 - -USB 虚拟 COM 端口默认连接串口 3，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build Oct 20 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口 3 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 BSP 下打开 env 工具。 - -2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 - -3. 输入 `pkgs --update` 命令更新软件包。 - -4. 输入 `scons --target=mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32 系列 BSP 外设驱动使用教程. md)。 - -## 注意事项 - -暂无 - -## 联系人信息 - -维护人: - -- [flybreak](https://github.com/guozhanxin) ，邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf diff --git a/bsp/stm32/stm32f412-st-nucleo/README_zh.md b/bsp/stm32/stm32f412-st-nucleo/README_zh.md new file mode 100644 index 0000000000..2502e29e29 --- /dev/null +++ b/bsp/stm32/stm32f412-st-nucleo/README_zh.md @@ -0,0 +1,107 @@ +# NUCLEO-F412ZG 开发板 BSP 说明 + +## 简介 + +本文档为 RT-Thread 开发团队为 NUCLEO-F412ZG 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +探索者 NUCLEO-F412ZG 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 100Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F411ZG 的芯片性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32F412ZG，主频 100MHz，1024KB FLASH ，256KB RAM。 +- 常用外设 + - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 + - 按键，2 个，USER and RESET 。 +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 +- 调试接口，板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考意法半导体 [NUCLEO-F412ZG 开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f412zg.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | +| UART | 支持 | UART2,UART3 | +| Onchip Flash | 支持 | | +| USB Device | 支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Type-A to Micro-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、蓝色 LD2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 3，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Oct 20 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 3 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 BSP 下打开 env 工具。 + +2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32 系列 BSP 外设驱动使用教程. md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [flybreak](https://github.com/guozhanxin) ，邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32f413-st-nucleo/README.md b/bsp/stm32/stm32f413-st-nucleo/README.md index e795064dba..332dec7307 100644 --- a/bsp/stm32/stm32f413-st-nucleo/README.md +++ b/bsp/stm32/stm32f413-st-nucleo/README.md @@ -1,122 +1,88 @@ -# NUCLEO-F413ZH 开发板 BSP 说明 +# STM32F413-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 RT-Thread 开发团队为 NUCLEO-F413ZH 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32F413ZH @100MHz, 1.5 MB FLASH, 320KB RAM -主要内容如下： +The STM32F413xG/H devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32F413xG/H devices belong to the STM32F4 access product lines (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching. +The STM32F413xG/H devices incorporate high-speed embedded memories (up to 1.5 Mbytes of Flash memory, 320 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. +All devices offer a 12-bit ADC, two 12-bit DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timer for motor control, two general-purpose 32-bit timers and a low power timer. +They also feature standard and advanced communication interfaces. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Dynamic Efficiency Line with eBAM (enhanced Batch Acquisition Mode) + - 1.7 V to 3.6 V power supply + - -40 °C to 85/105/125 °C temperature range +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Memories + - Up to 1.5 Mbytes of Flash memory + - 320 Kbytes of SRAM + - Flexible external static memory controller with up to 16-bit data bus: SRAM, PSRAM, NOR Flash memory + - Dual mode Quad-SPI interface +- LCD parallel interface, 8080/6800 modes +- Clock, reset and supply management + - 1.7 to 3.6 V application supply and I/Os + - POR, PDR, PVD and BOR + - 4-to-26 MHz crystal oscillator + - Internal 16 MHz factory-trimmed RC + - 32 kHz oscillator for RTC with calibration + - Internal 32 kHz RC with calibration +- Power consumption + - Run: 112 μA/MHz (peripheral off) + - Stop (Flash in Stop mode, fast wakeup time): 42 μA Typ.; 80 μA max @25 °C + - Stop (Flash in Deep power down mode, slow wakeup time): 15 μA Typ.; 46 μA max @25 °C + - Standby without RTC: 1.1 μA Typ.; 14.7 μA max at @85 °C + - VBAT supply for RTC: 1 μA @25 °C +- 2x12-bit D/A converters +- 1×12-bit, 2.4 MSPS ADC: up to 16 channels +- 6x digital filters for sigma delta modulator, 12x PDM interfaces, with stereo microphone and sound source localization support +- General-purpose DMA: 16-stream DMA -探索者 NUCLEO-F413ZH 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 100Mhz，该开发板具有丰富的板载资源，可以充分发挥 NUCLEO-F413ZH 的芯片性能。 +- Up to 18 timers: up to twelve 16-bit timers, two 32-bit timers up to 100 MHz each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window), one SysTick timer, and a low-power timer +- Debug mode + - Serial wire debug (SWD) & JTAG + - Cortex®-M4 Embedded Trace Macrocell™ +- Up to 114 I/O ports with interrupt capability + - Up to 109 fast I/Os up to 100 MHz + - Up to 114 five V-tolerant I/Os +- Up to 24 communication interfaces + - Up to 4x I2C interfaces (SMBus/PMBus) + - Up to 10 UARTS: 4 USARTs / 6 UARTs (2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) + - Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or I2S audio protocol), out of which 2 muxed full-duplex I2S interfaces + - SDIO interface (SD/MMC/eMMC) + - Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with PHY + - 3x CAN (2.0B Active) + - 1xSAI +- True random number generator +- CRC calculation unit +- 96-bit unique ID +- RTC: subsecond accuracy, hardware calendar +- All packages are ECOPACK®2 -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32F413ZH，主频 100MHz，1536KB FLASH ，320KB RAM -- 常用外设 - - LED：8个，user LED (JP5跳帽需连接)(黄色，PB0，LD1；蓝色，PB7，LD2；红色，PB14，LD3), USB communication (LD4), over current (LD5), power LED (黄色，LD6), USB FAULT (LD7), VBUS (LD8)。 - - 按键：2个，B1（USER，PC13），B2（RESET） -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口等。 -- 调试接口，板载 ST-LINK/V2-1 调试器。 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) | +| [STM32F413ZH ST Official Website](https://www.st.com/zh/microcontrollers-microprocessors/stm32f413zh.html#documentation) | STM32F413ZH datasheet and other resources | -开发板更多详细信息请参考意法半导体 [NUCLEO-F413ZH 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f413zh.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :------------ | :----------: | :-----------------------------------: | -|STLINK TO USART| 支持 | UART3 | +[flybreak](https://github.com/guozhanxin) [email protected] -| **片上外设** | **支持情况** | **备注** | -| :------------ | :----------: | :-----------------------------------: | -| GPIO | 支持 | | -| UART | 支持 | UART2/3 | -| SPI | 支持 | SPI2 | -| I2C | 支持 | I2C1(软件模拟) | -| TIMER | 支持 | TIM11/13/14 | -| PWM | 支持 | PWM2_CH4 | -| ADC | 支持 | ADC1_IN5 | -| RTC | 支持 | 支持外部晶振和内部低速时钟 | -| WDT | 支持 | 独立看门狗 | -| Onchip Flash | 支持 | 片上Flash | -| USB OTG_FS | 支持 | OTGFS as USB device | -| Onchip Flash | 支持 | 片上Flash | -| USB Device | 支持 | OTGFS as USB device | -| RNG | 支持 | Random Number Generator | -| UDID | 支持 | Unique Device Identifier | -## 使用说明 -使用说明分为如下两个章节： +## Translated By -- 快速上手 +Meco Man @ RT-Thread Community - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用 Type-A to Micro-B 线连接开发板和 PC 供电，黄色 LED LD6 (PWR) 和 LD4 (COM) 会点亮。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 板载ST-LINK 仿真器下载程序，在通过 Micro USB线 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，在JP5跳帽连接时，观察开发板上LD1的运行效果，黄色LED会周期性闪烁。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.3 build Apr 28 2020 - 2006 - 2020 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 UART3 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -暂无 - -## 联系人信息 - -维护人: - -- [flybreak](https://github.com/XYX12306) ，邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32f413-st-nucleo/README_zh.md b/bsp/stm32/stm32f413-st-nucleo/README_zh.md new file mode 100644 index 0000000000..e795064dba --- /dev/null +++ b/bsp/stm32/stm32f413-st-nucleo/README_zh.md @@ -0,0 +1,122 @@ +# NUCLEO-F413ZH 开发板 BSP 说明 + +## 简介 + +本文档为 RT-Thread 开发团队为 NUCLEO-F413ZH 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +探索者 NUCLEO-F413ZH 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 100Mhz，该开发板具有丰富的板载资源，可以充分发挥 NUCLEO-F413ZH 的芯片性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32F413ZH，主频 100MHz，1536KB FLASH ，320KB RAM +- 常用外设 + - LED：8个，user LED (JP5跳帽需连接)(黄色，PB0，LD1；蓝色，PB7，LD2；红色，PB14，LD3), USB communication (LD4), over current (LD5), power LED (黄色，LD6), USB FAULT (LD7), VBUS (LD8)。 + - 按键：2个，B1（USER，PC13），B2（RESET） +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口等。 +- 调试接口，板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考意法半导体 [NUCLEO-F413ZH 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f413zh.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +|STLINK TO USART| 支持 | UART3 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +| GPIO | 支持 | | +| UART | 支持 | UART2/3 | +| SPI | 支持 | SPI2 | +| I2C | 支持 | I2C1(软件模拟) | +| TIMER | 支持 | TIM11/13/14 | +| PWM | 支持 | PWM2_CH4 | +| ADC | 支持 | ADC1_IN5 | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| WDT | 支持 | 独立看门狗 | +| Onchip Flash | 支持 | 片上Flash | +| USB OTG_FS | 支持 | OTGFS as USB device | +| Onchip Flash | 支持 | 片上Flash | +| USB Device | 支持 | OTGFS as USB device | +| RNG | 支持 | Random Number Generator | +| UDID | 支持 | Unique Device Identifier | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Type-A to Micro-B 线连接开发板和 PC 供电，黄色 LED LD6 (PWR) 和 LD4 (COM) 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 板载ST-LINK 仿真器下载程序，在通过 Micro USB线 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，在JP5跳帽连接时，观察开发板上LD1的运行效果，黄色LED会周期性闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Apr 28 2020 + 2006 - 2020 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 UART3 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [flybreak](https://github.com/XYX12306) ，邮箱：<[email protected]>
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- </OrigResetItems> - </ToolBar> - <ControlBarsSummary> - <Bars>0</Bars> - <ScreenCX>1536</ScreenCX> - <ScreenCY>864</ScreenCY> - </ControlBarsSummary> - </ViewEx> - </WinLayoutEx> - - <AlienFiles/> - - <MDIGroups> - <Orientation>1</Orientation> - <ActiveMDIGroup>0</ActiveMDIGroup> - <MDIGroup> - <Size>100</Size> - <ActiveTab>0</ActiveTab> - <Doc> - <Name>applications\main.c</Name> - <ColumnNumber>0</ColumnNumber> - <TopLine>1</TopLine> - <CurrentLine>1</CurrentLine> - <Folding>1</Folding> - <ContractedFolders></ContractedFolders> - </Doc> - </MDIGroup> - </MDIGroups> - -</ProjectGui> diff --git a/bsp/stm32/stm32f429-st-disco/.config b/bsp/stm32/stm32f429-st-disco/.config index d2e8ecd259..5dfe532571 100644 --- a/bsp/stm32/stm32f429-st-disco/.config +++ b/bsp/stm32/stm32f429-st-disco/.config @@ -135,6 +135,7 @@ CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -145,6 +146,11 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -164,11 +170,11 @@ CONFIG_RT_USING_SPI=y # POSIX layer and C standard library # CONFIG_RT_USING_LIBC=y -CONFIG_RT_USING_PTHREADS=y -CONFIG_PTHREAD_NUM_MAX=8 +# CONFIG_RT_USING_PTHREADS is not set CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set @@ -287,6 +293,9 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -312,6 +321,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -332,6 +342,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_BS8116A is not set # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -359,6 +370,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -409,6 +422,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_QLED is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -446,39 +463,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y diff --git a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.icf b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.icf index 9da4173925..ecb5fbac1f 100644 --- a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.icf @@ -5,7 +5,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
/*-Sizes-*/
diff --git a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds index 040fdd37b0..54de8e1a68 100644 --- a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.lds @@ -1,5 +1,5 @@ /* - * linker script for STM32F4xx with GNU ld + * linker script for STM32F429xx with GNU ld * bernard.xiong 2009-10-14 */ @@ -7,7 +7,7 @@ MEMORY { ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 2048KB flash */ - RAM (rw) : ORIGIN = 0x20000000, LENGTH = 320k /* 320K sram */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192K sram */ } ENTRY(Reset_Handler) _system_stack_size = 0x200; diff --git a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.sct b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.sct index 0d7c47992d..2407164991 100644 --- a/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32f429-st-disco/board/linker_scripts/link.sct @@ -2,13 +2,13 @@ ; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
-LR_IROM1 0x08000000 0x00100000 { ; load region size_region
- ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
+LR_IROM1 0x08000000 0x00200000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/bsp/stm32/stm32f429-st-disco/project.uvoptx b/bsp/stm32/stm32f429-st-disco/project.uvoptx index d3767bff36..ed66375428 100644 --- a/bsp/stm32/stm32f429-st-disco/project.uvoptx +++ b/bsp/stm32/stm32f429-st-disco/project.uvoptx @@ -182,11 +182,1167 @@ </Target> <Group> - <GroupName>Source Group 1</GroupName> + <GroupName>Applications</GroupName> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> <RteFlg>0</RteFlg> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>1</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>applications\main.c</PathWithFileName> + <FilenameWithoutPath>main.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>2</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>applications\lcd_init.c</PathWithFileName> + <FilenameWithoutPath>lcd_init.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>cpu</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>3</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\common\backtrace.c</PathWithFileName> + <FilenameWithoutPath>backtrace.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>4</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName> + <FilenameWithoutPath>div0.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>5</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName> + <FilenameWithoutPath>showmem.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>6</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\cortex-m4\cpuport.c</PathWithFileName> + <FilenameWithoutPath>cpuport.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>7</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</PathWithFileName> + <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>DeviceDrivers</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>8</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\i2c\i2c_core.c</PathWithFileName> + <FilenameWithoutPath>i2c_core.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>9</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\i2c\i2c_dev.c</PathWithFileName> + <FilenameWithoutPath>i2c_dev.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>10</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\i2c\i2c-bit-ops.c</PathWithFileName> + <FilenameWithoutPath>i2c-bit-ops.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>11</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\misc\pin.c</PathWithFileName> + <FilenameWithoutPath>pin.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>12</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\serial\serial.c</PathWithFileName> + <FilenameWithoutPath>serial.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>13</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\spi\spi_core.c</PathWithFileName> + <FilenameWithoutPath>spi_core.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>14</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\spi\spi_dev.c</PathWithFileName> + <FilenameWithoutPath>spi_dev.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>15</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\src\completion.c</PathWithFileName> + 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<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c</FilePath> </File> </Files> <Files> <File> - <FileName>pipe.c</FileName> + <FileName>stm32f4xx_hal_cryp.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\pipe.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c</FilePath> </File> </Files> <Files> <File> - <FileName>ringblk_buf.c</FileName> + <FileName>stm32f4xx_hal_cryp_ex.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c</FilePath> </File> </Files> <Files> <File> - <FileName>ringbuffer.c</FileName> + <FileName>stm32f4xx_hal_dma.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c</FilePath> </File> </Files> <Files> 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<FileName>stm32f4xx_hal_rcc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\cmd.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c</FilePath> </File> </Files> <Files> <File> - <FileName>msh.c</FileName> + <FileName>stm32f4xx_hal_rcc_ex.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\msh.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c</FilePath> </File> </Files> <Files> <File> - <FileName>msh_file.c</FileName> + <FileName>stm32f4xx_hal_rng.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\msh_file.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_compiler.c</FileName> + <FileName>stm32f4xx_hal_gpio.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_error.c</FileName> + <FileName>stm32f4xx_hal_uart.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_error.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_heap.c</FileName> + <FileName>stm32f4xx_hal_usart.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_heap.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_init.c</FileName> + <FileName>stm32f4xx_hal_i2c.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_init.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_node.c</FileName> + <FileName>stm32f4xx_hal_i2c_ex.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_node.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_ops.c</FileName> + <FileName>stm32f4xx_hal_spi.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_ops.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_parser.c</FileName> + <FileName>stm32f4xx_hal_qspi.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_parser.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_var.c</FileName> + <FileName>stm32f4xx_ll_fmc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_var.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_vm.c</FileName> + <FileName>stm32f4xx_ll_fsmc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_vm.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_token.c</FileName> + <FileName>stm32f4xx_hal_sdram.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_token.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c</FilePath> </File> </Files> - </Group> - <Group> - <GroupName>libc</GroupName> <Files> <File> - <FileName>libc.c</FileName> + <FileName>stm32f4xx_hal_ltdc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c</FilePath> </File> </Files> <Files> <File> - <FileName>mem_std.c</FileName> + <FileName>stm32f4xx_hal_ltdc_ex.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\mem_std.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c</FilePath> </File> </Files> <Files> <File> - <FileName>stdio.c</FileName> + <FileName>stm32f4xx_hal_dma2d.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\stdio.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c</FilePath> </File> </Files> <Files> <File> - <FileName>stubs.c</FileName> + <FileName>stm32f4xx_ll_dma2d.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\stubs.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_dma2d.c</FilePath> </File> </Files> <Files> <File> - <FileName>time.c</FileName> + <FileName>stm32f4xx_hal_dsi.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\common\time.c</FilePath> + <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c</FilePath> </File> </Files> </Group> diff --git a/bsp/stm32/stm32f429-st-disco/project.uvprojx b/bsp/stm32/stm32f429-st-disco/project.uvprojx index b6adb12dd1..2bfc2d6515 100644 --- a/bsp/stm32/stm32f429-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f429-st-disco/project.uvprojx @@ -1,13 +1,16 @@ <?xml version="1.0" encoding="UTF-8" standalone="no" ?> <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + <SchemaVersion>2.1</SchemaVersion> + <Header>### uVision Project, (C) Keil Software</Header> + <Targets> <Target> <TargetName>rt_thread_stm32f429</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> - <pCCUsed>5060300::V5.06 update 3 (build 300)::ARMCC</pCCUsed> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> @@ -16,28 +19,28 @@ <PackID>Keil.STM32F4xx_DFP.2.13.0</PackID> <PackURL>http://www.keil.com/pack</PackURL> <Cpu>IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x200000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu> - <FlashUtilSpec /> - <StartupFile /> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32F429ZITx$CMSIS\Flash\STM32F4xx_2048.FLM))</FlashDriverDll> <DeviceId>0</DeviceId> <RegisterFile>$$Device:STM32F429ZITx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h</RegisterFile> - <MemoryEnv /> - <Cmp /> - <Asm /> - <Linker /> - <OHString /> - <InfinionOptionDll /> - <SLE66CMisc /> - <SLE66AMisc /> - <SLE66LinkerMisc /> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> <SFDFile>$$Device:STM32F429ZITx$CMSIS\SVD\STM32F429x.svd</SFDFile> <bCustSvd>0</bCustSvd> <UseEnv>0</UseEnv> - <BinPath /> - <IncludePath /> - <LibPath /> - <RegisterFilePath /> - <DBRegisterFilePath /> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> <TargetStatus> <Error>0</Error> <ExitCodeStop>0</ExitCodeStop> @@ -59,8 +62,8 @@ <BeforeCompile> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopU1X>0</nStopU1X> @@ -69,8 +72,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -79,15 +82,15 @@ <AfterMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopA1X>0</nStopA1X> <nStopA2X>0</nStopA2X> </AfterMake> <SelectedForBatchBuild>0</SelectedForBatchBuild> - <SVCSIdString /> + <SVCSIdString></SVCSIdString> </TargetCommonOption> <CommonProperty> <UseCPPCompiler>0</UseCPPCompiler> @@ -101,8 +104,8 @@ <AssembleAssemblyFile>0</AssembleAssemblyFile> <PublicsOnly>0</PublicsOnly> <StopOnExitCode>3</StopOnExitCode> - <CustomArgument /> - <IncludeLibraryModules /> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> <ComprImg>1</ComprImg> </CommonProperty> <DllOption> @@ -135,11 +138,11 @@ </Flash1> <bUseTDR>1</bUseTDR> <Flash2>BIN\UL2CM3.DLL</Flash2> - <Flash3 /> - <Flash4 /> - <pFcarmOut /> - <pFcarmGrp /> - <pFcArmRoot /> + <Flash3></Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> <FcArmLst>0</FcArmLst> </Utilities> <TargetArmAds> @@ -172,7 +175,7 @@ <RvctClst>0</RvctClst> <GenPPlst>0</GenPPlst> <AdsCpuType>"Cortex-M4"</AdsCpuType> - <RvctDeviceName /> + <RvctDeviceName></RvctDeviceName> <mOS>0</mOS> <uocRom>0</uocRom> <uocRam>0</uocRam> @@ -305,7 +308,7 @@ <Size>0x10000</Size> </OCR_RVCT10> </OnChipMemories> - <RvctStartVector /> + <RvctStartVector></RvctStartVector> </ArmAdsMisc> <Cads> <interw>1</interw> @@ -332,10 +335,10 @@ <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> <VariousControls> - <MiscControls /> - <Define>USE_HAL_DRIVER, RT_USING_ARM_LIBC, STM32F429xx</Define> - <Undefine /> - <IncludePath>applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\..\..\components\libc\signal;..\..\..\components\libc\pthreads;..\..\..\components\libc\time;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include</IncludePath> + <MiscControls></MiscControls> + <Define>USE_HAL_DRIVER, RT_USING_ARM_LIBC, __RTTHREAD__, STM32F429xx</Define> + <Undefine></Undefine> + <IncludePath>applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include</IncludePath> </VariousControls> </Cads> <Aads> @@ -350,10 +353,10 @@ <useXO>0</useXO> <uClangAs>0</uClangAs> <VariousControls> - <MiscControls /> - <Define /> - <Undefine /> - <IncludePath /> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> </VariousControls> </Aads> <LDads> @@ -365,13 +368,13 @@ <useFile>0</useFile> <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> - <pXoBase /> + <pXoBase></pXoBase> <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile> - <IncludeLibs /> - <IncludeLibsPath /> - <Misc /> - <LinkerInputFile /> - <DisabledWarnings /> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> </LDads> </TargetArmAds> </TargetOption> @@ -384,8 +387,6 @@ <FileType>1</FileType> <FilePath>applications\main.c</FilePath> </File> - </Files> - <Files> <File> <FileName>lcd_init.c</FileName> <FileType>1</FileType> @@ -401,29 +402,21 @@ <FileType>1</FileType> <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath> </File> - </Files> - <Files> <File> <FileName>div0.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath> </File> - </Files> - <Files> <File> <FileName>showmem.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath> </File> - </Files> - <Files> <File> <FileName>cpuport.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath> </File> - </Files> - <Files> <File> <FileName>context_rvds.S</FileName> <FileType>2</FileType> @@ -433,116 +426,147 @@ </Group> <Group> <GroupName>DeviceDrivers</GroupName> + <GroupOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>0</ComprImg> + </CommonProperty> + <GroupArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls></MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <useXO>2</useXO> + <uClangAs>2</uClangAs> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </GroupArmAds> + </GroupOption> <Files> <File> <FileName>i2c_core.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\i2c\i2c_core.c</FilePath> </File> - </Files> - <Files> <File> <FileName>i2c_dev.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\i2c\i2c_dev.c</FilePath> </File> - </Files> - <Files> <File> <FileName>i2c-bit-ops.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\i2c\i2c-bit-ops.c</FilePath> </File> - </Files> - <Files> <File> <FileName>pin.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath> </File> - </Files> - <Files> <File> <FileName>serial.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath> </File> - </Files> - <Files> <File> <FileName>spi_core.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath> </File> - </Files> - <Files> <File> <FileName>spi_dev.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath> </File> - </Files> - <Files> <File> <FileName>completion.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\src\completion.c</FilePath> </File> - </Files> - <Files> <File> <FileName>dataqueue.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath> </File> - </Files> - <Files> <File> <FileName>pipe.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath> </File> - </Files> - <Files> <File> <FileName>ringblk_buf.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath> </File> - </Files> - <Files> <File> <FileName>ringbuffer.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath> </File> - </Files> - <Files> <File> <FileName>waitqueue.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath> </File> - </Files> - <Files> <File> <FileName>workqueue.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath> </File> </Files> - <GroupOption> - <GroupArmAds> - <Cads> - <VariousControls> - <MiscControls /> - <Define> </Define> - <Undefine> </Undefine> - <IncludePath> </IncludePath> - </VariousControls> - </Cads> - </GroupArmAds> - </GroupOption> </Group> <Group> <GroupName>Drivers</GroupName> @@ -552,64 +576,46 @@ <FileType>1</FileType> <FilePath>board\board.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_msp.c</FileName> <FileType>1</FileType> <FilePath>board\CubeMX_Config\Src\stm32f4xx_hal_msp.c</FilePath> </File> - </Files> - <Files> <File> <FileName>ili9341.c</FileName> <FileType>1</FileType> <FilePath>board\ports\ili9341.c</FilePath> </File> - </Files> - <Files> <File> <FileName>startup_stm32f429xx.s</FileName> <FileType>2</FileType> <FilePath>..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f429xx.s</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_gpio.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\HAL_Drivers\drv_gpio.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_usart.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\HAL_Drivers\drv_usart.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_spi.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\HAL_Drivers\drv_spi.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_sdram.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\HAL_Drivers\drv_sdram.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_lcd.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\HAL_Drivers\drv_lcd.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_common.c</FileName> <FileType>1</FileType> @@ -625,43 +631,31 @@ <FileType>1</FileType> <FilePath>..\..\..\components\dfs\src\dfs.c</FilePath> </File> - </Files> - <Files> <File> <FileName>dfs_file.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\dfs\src\dfs_file.c</FilePath> </File> - </Files> - <Files> <File> <FileName>dfs_fs.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\dfs\src\dfs_fs.c</FilePath> </File> - </Files> - <Files> <File> <FileName>dfs_posix.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\dfs\src\dfs_posix.c</FilePath> </File> - </Files> - <Files> <File> <FileName>poll.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\dfs\src\poll.c</FilePath> </File> - </Files> - <Files> <File> <FileName>select.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\dfs\src\select.c</FilePath> </File> - </Files> - <Files> <File> <FileName>devfs.c</FileName> <FileType>1</FileType> @@ -677,22 +671,16 @@ <FileType>1</FileType> <FilePath>..\..\..\components\finsh\shell.c</FilePath> </File> - </Files> - <Files> <File> <FileName>cmd.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\finsh\cmd.c</FilePath> </File> - </Files> - <Files> <File> <FileName>msh.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\finsh\msh.c</FilePath> </File> - </Files> - <Files> <File> <FileName>msh_file.c</FileName> <FileType>1</FileType> @@ -708,92 +696,66 @@ <FileType>1</FileType> <FilePath>..\..\..\src\clock.c</FilePath> </File> - </Files> - <Files> <File> <FileName>components.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\components.c</FilePath> </File> - </Files> - <Files> <File> <FileName>device.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\device.c</FilePath> </File> - </Files> - <Files> <File> <FileName>idle.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\idle.c</FilePath> </File> - </Files> - <Files> <File> <FileName>ipc.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\ipc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>irq.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\irq.c</FilePath> </File> - </Files> - <Files> <File> <FileName>kservice.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\kservice.c</FilePath> </File> - </Files> - <Files> <File> <FileName>memheap.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\memheap.c</FilePath> </File> - </Files> - <Files> <File> <FileName>mempool.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\mempool.c</FilePath> </File> - </Files> - <Files> <File> <FileName>object.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\object.c</FilePath> </File> - </Files> - <Files> <File> <FileName>scheduler.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\scheduler.c</FilePath> </File> - </Files> - <Files> <File> <FileName>signal.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\signal.c</FilePath> </File> - </Files> - <Files> <File> <FileName>thread.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\src\thread.c</FilePath> </File> - </Files> - <Files> <File> <FileName>timer.c</FileName> <FileType>1</FileType> @@ -809,143 +771,32 @@ <FileType>1</FileType> <FilePath>..\..\..\components\libc\compilers\armlibc\libc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>mem_std.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\libc\compilers\armlibc\mem_std.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stdio.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\libc\compilers\armlibc\stdio.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stubs.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\libc\compilers\armlibc\stubs.c</FilePath> </File> - </Files> - <Files> <File> <FileName>time.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath> </File> - </Files> - <Files> <File> <FileName>unistd.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\components\libc\compilers\common\unistd.c</FilePath> </File> </Files> - <Files> - <File> - <FileName>posix_signal.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\signal\posix_signal.c</FilePath> - </File> - </Files> - </Group> - <Group> - <GroupName>pthreads</GroupName> - <Files> - <File> - <FileName>mqueue.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\mqueue.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread_attr.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread_attr.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread_barrier.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread_barrier.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread_cond.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread_cond.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread_mutex.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread_mutex.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread_rwlock.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread_rwlock.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread_spin.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread_spin.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pthread_tls.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\pthread_tls.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>sched.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\sched.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>semaphore.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\pthreads\semaphore.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>clock_time.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\time\clock_time.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>posix_sleep.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\components\libc\time\posix_sleep.c</FilePath> - </File> - </Files> </Group> <Group> <GroupName>STM32_HAL</GroupName> @@ -955,197 +806,141 @@ <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_cec.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_cortex.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_crc.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_cryp.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_cryp_ex.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_dma.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_dma_ex.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_pwr.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_pwr_ex.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_rcc.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_rcc_ex.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_rng.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_gpio.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_uart.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_usart.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_i2c.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_i2c_ex.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_spi.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_qspi.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_ll_fmc.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_ll_fsmc.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_sdram.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_ltdc.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_ltdc_ex.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_dma2d.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_ll_dma2d.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_dma2d.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f4xx_hal_dsi.c</FileName> <FileType>1</FileType> @@ -1156,9 +951,11 @@ </Groups> </Target> </Targets> + <RTE> - <apis /> - <components /> - <files /> + <apis/> + <components/> + <files/> </RTE> + </Project> diff --git a/bsp/stm32/stm32f429-st-disco/rtconfig.h b/bsp/stm32/stm32f429-st-disco/rtconfig.h index 9f5b2c77c4..b82b91ec7a 100644 --- a/bsp/stm32/stm32f429-st-disco/rtconfig.h +++ b/bsp/stm32/stm32f429-st-disco/rtconfig.h @@ -93,14 +93,13 @@ #define RT_USING_I2C_BITOPS #define RT_USING_PIN #define RT_USING_SPI + /* Using USB */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -#define RT_USING_PTHREADS -#define PTHREAD_NUM_MAX 8 #define RT_USING_POSIX /* Network */ @@ -162,12 +161,6 @@ /* samples: kernel and components samples */ - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 diff --git a/bsp/stm32/stm32f429-st-disco/stm32_rom.ld b/bsp/stm32/stm32f429-st-disco/stm32_rom.ld index aa9c9b2af2..e895d97da2 100644 --- a/bsp/stm32/stm32f429-st-disco/stm32_rom.ld +++ b/bsp/stm32/stm32f429-st-disco/stm32_rom.ld @@ -1,13 +1,13 @@ /* - * linker script for STM32F10x with GNU ld + * linker script for STM32F429xx with GNU ld * bernard.xiong 2009-10-14 */ /* Program Entry, set to mark it as "used" and avoid gc */ MEMORY { - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 1024KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 128K sram */ } ENTRY(Reset_Handler) _system_stack_size = 0x200; diff --git a/bsp/stm32/stm32f429-st-disco/stm32_rom.sct b/bsp/stm32/stm32f429-st-disco/stm32_rom.sct index 0d7c47992d..2407164991 100644 --- a/bsp/stm32/stm32f429-st-disco/stm32_rom.sct +++ b/bsp/stm32/stm32f429-st-disco/stm32_rom.sct @@ -2,13 +2,13 @@ ; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
-LR_IROM1 0x08000000 0x00100000 { ; load region size_region
- ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
+LR_IROM1 0x08000000 0x00200000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/bsp/stm32/stm32f429-st-disco/stm32f429_flash.icf b/bsp/stm32/stm32f429-st-disco/stm32f429_flash.icf index 47c5280d08..4e43be768e 100644 --- a/bsp/stm32/stm32f429-st-disco/stm32f429_flash.icf +++ b/bsp/stm32/stm32f429-st-disco/stm32f429_flash.icf @@ -2,10 +2,10 @@ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; /*-Sizes-*/ diff --git a/bsp/stm32/stm32f446-st-nucleo/README.md b/bsp/stm32/stm32f446-st-nucleo/README.md index e91f1ef45a..bb260c2b31 100644 --- a/bsp/stm32/stm32f446-st-nucleo/README.md +++ b/bsp/stm32/stm32f446-st-nucleo/README.md @@ -1,106 +1,84 @@ -# NUCLEO-F446ZE 开发板 BSP 说明 +# STM32F446-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 NUCLEO-F446ZE 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32F446ZE @180MHz, 512KB FLASH, 128KB RAM -主要内容如下： +The STM32F446xC/E devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a floating point unit (FPU) single precision supporting all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32F446xC/E devices incorporate high-speed embedded memories (Flash memory up to 512 Kbytes, up to 128 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. +All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. +They also feature standard and advanced communication interfaces. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Memories + - 512 Kbytes of Flash memory + - 128 Kbytes of SRAM + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memories + - Dual mode QuadSPI interface +- LCD parallel interface, 8080/6800 modes +- Clock, reset and supply management + - 1.7 V to 3.6 V application supply and I/Os + - POR, PDR, PVD and BOR + - 4 to 26 MHz crystal oscillator + - Internal 16 MHz factory-trimmed RC (1% accuracy) + - 32 kHz oscillator for RTC with calibration + - Internal 32 kHz RC with calibration +- Low power + - Sleep, Stop and Standby modes + - VBAT supply for RTC, 20×32 bit backup registers plus optional 4 KB backup SRAM +- 3× 12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode +- 2× 12-bit D/A converters +- General-purpose DMA: 16-stream DMA controller with FIFOs and burst support +- Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to four IC/OC/PWM or pulse counter -NUCLEO-F446ZE 是 ST 公司推出的一款针对 STM32F4 系列设计的 Cortex-M4 Nucleo-144 开发板，支持 mbed，兼容 Arduino、还带有ST Zio和 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 +- Debug mode + - SWD and JTAG interfaces + - Cortex®-M4 Trace Macrocell™ +- Up to 114 I/O ports with interrupt capability + - Up to 111 fast I/Os up to 90 MHz + - Up to 112 5 V-tolerant I/Os +- Up to 20 communication interfaces + - SPDIF-Rx + - Up to 4× I2C interfaces (SMBus/PMBus) + - Up to four USARTs and two UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) + - Up to four SPIs (45 Mbits/s), three with muxed I2S for audio class accuracy via internal audio PLL or external clock + - 2x SAI (serial audio interface) + - 2× CAN (2.0B Active) + - SDIO interface + - Consumer electronics control (CEC) I/F +- Advanced connectivity + - USB 2.0 full-speed device/host/OTG controller with on-chip PHY + - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI + - Dedicated USB power rail enabling on-chip PHYs operation throughout the entire MCU power supply range +- 8- to 14-bit parallel camera interface up to 54 Mbytes/s +- CRC calculation unit +- RTC: subsecond accuracy, hardware calendar +- 96-bit unique ID -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32f446ZE，主频 180MHz，512KB FLASH ，128KB RAM -- 常用外设 - - LED：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14） -- 常用接口：USB 转串口 -- 调试接口，标准 ST-LINK/SWD +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) | +| [STM32F446ZE ST Official Website](https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f4-series/stm32f446/stm32f446ze.html#documentation) | STM32F446ZE datasheet and other resources | -开发板更多详细信息请参考【NUCLEO-F446ZE】 [开发板介绍](https://www.st.com/zh/evaluation-tools/nucleo-f446ze.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| USB 转串口 | 支持 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | | -| UART | 支持 | UART1 | -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，通过数据线对开发板供电,下载,调试。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，蓝色的 LED2 以 500MS 周期闪烁。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Jan 7 2019 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 默认终端输出设备是 UART1 - -## 联系人信息 - -维护人: - -- 邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32f446-st-nucleo/README_zh.md b/bsp/stm32/stm32f446-st-nucleo/README_zh.md new file mode 100644 index 0000000000..acc7091fd8 --- /dev/null +++ b/bsp/stm32/stm32f446-st-nucleo/README_zh.md @@ -0,0 +1,106 @@ +# NUCLEO-F446ZE 开发板 BSP 说明 + +## 简介 + +本文档为 NUCLEO-F446ZE 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-F446ZE 是 ST 公司推出的一款针对 STM32F4 系列设计的 Cortex-M4 Nucleo-144 开发板，支持 mbed，兼容 Arduino、还带有ST Zio和 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32f446ZE，主频 180MHz，512KB FLASH ，128KB RAM +- 常用外设 + - LED：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14） +- 常用接口：USB 转串口 +- 调试接口，标准 ST-LINK/SWD + +开发板更多详细信息请参考【NUCLEO-F446ZE】 [开发板介绍](https://www.st.com/zh/evaluation-tools/nucleo-f446ze.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART1 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，通过数据线对开发板供电,下载,调试。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，蓝色的 LED2 以 500MS 周期闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Jan 7 2019 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 默认终端输出设备是 UART1 + +## 联系人信息 + +维护人: + +- 邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32f746-st-disco/rtconfig.py b/bsp/stm32/stm32f746-st-disco/rtconfig.py index 32cb0dd9d4..de934eeac7 100644 --- a/bsp/stm32/stm32f746-st-disco/rtconfig.py +++ b/bsp/stm32/stm32f746-st-disco/rtconfig.py @@ -42,7 +42,7 @@ if PLATFORM == 'gcc': OBJCPY = PREFIX + 'objcopy' STRIP = PREFIX + 'strip' - DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -g -Wall' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' diff --git a/bsp/stm32/stm32f767-st-nucleo/README.md b/bsp/stm32/stm32f767-st-nucleo/README.md index 45ccf66f70..3cb5f47d34 100644 --- a/bsp/stm32/stm32f767-st-nucleo/README.md +++ b/bsp/stm32/stm32f767-st-nucleo/README.md @@ -1,110 +1,95 @@ -# STM32F767 NUCLEO-F767ZI开发板 BSP 说明 -## 简介 +# STM32F767-Nucleo BSP Introduction -本文档为 NUCLEO-F767ZI 开发板的 BSP (板级支持包) 说明。 +[中文](README_zh.md) -主要内容如下： +## MCU: STM32F767ZI @216MHz, 2MB FLASH, 512KB RAM -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a floating point unit (FPU) which supports Arm® double-precision and single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices incorporate high-speed embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of SRAM (including 128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. +All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces. +Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors. +The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 for a greater power supply choice. +The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications. +The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices offer devices in 11 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. +These features make the STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx microcontrollers suitable for a wide range of applications. -## 开发板介绍 +#### KEY FEATURES -NUCLEO-F767ZI 是st推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 216Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F767 的芯片性能。 +- Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator™ and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. +- Memories + - Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write + - SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM + - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories +- Dual mode Quad-SPI +- Graphics + - Chrom-ART Accelerator™ (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface + - Hardware JPEG codec + - LCD-TFT controller supporting up to XGA resolution + - MIPI® DSI host controller supporting up to 720p 30 Hz resolution +- Clock, reset and supply management + - 1.7 V to 3.6 V application supply and I/Os + - POR, PDR, PVD and BOR + - Dedicated USB power + - 4-to-26 MHz crystal oscillator + - Internal 16 MHz factory-trimmed RC (1% accuracy) + - 32 kHz oscillator for RTC with calibration + - Internal 32 kHz RC with calibration +- Low-power + - Sleep, Stop and Standby modes + - VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM +- 3×12-bit, 2.4 MSPS ADC: up to 24 channels +- Digital filters for sigma delta modulator (DFSDM), 8 channels / 4 filters +- 2×12-bit D/A converters +- General-purpose DMA: 16-stream DMA controller with FIFOs and burst support -开发板外观如下图所示： +- Up to 18 timers: up to thirteen 16-bit (1x low- power 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer +- Debug mode + - SWD & JTAG interfaces + - Cortex®-M7 Trace Macrocell™ +- Up to 168 I/O ports with interrupt capability + - Up to 164 fast I/Os up to 108 MHz + - Up to 166 5 V-tolerant I/Os +- Up to 28 communication interfaces + - Up to 4 I2C interfaces (SMBus/PMBus) + - Up to 4 USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) + - Up to 6 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2S for audio + - 2 x SAIs (serial audio interface) + - 3 x CANs (2.0B Active) and 2 x SDMMCs + - SPDIFRX interface + - HDMI-CEC + - MDIO slave interface +- Advanced connectivity + - USB 2.0 full-speed device/host/OTG controller with on-chip PHY + - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI + - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII +- 8- to 14-bit camera interface up to 54 Mbyte/s +- True random number generator +- CRC calculation unit +- RTC: subsecond accuracy, hardware calendar +- 96-bit unique ID - -该开发板常用 **板载资源** 如下： -- MCU：STM32f767，主频 216MHz，2MB FLASH ，512KB RAM ，16K CACHE +## Read more -- 常用外设 - - LED ：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14） - - 按键：2个，B1（用户按键，PC13），B2（复位引脚） -- 常用接口：USB 转串口3、以太网接口 -- 调试接口：ST-LINK +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) | +| [STM32F767ZI ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32f767zi.html#documentation) | STM32F767ZI datasheet and other resources | -开发板更多详细信息请参考ST [NUCLEO-F767ZI开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :-----------------| :----------: | :-------------------------------------| -| USB 转串口3 | 支持 | | -| 以太网 | 支持 | PHY 选项 LAN8720A（兼容 LAN8742A） | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 | -| UART | 支持 | UART3 | -| **扩展模块** | **支持情况** | **备注** | -| 暂无 | 暂不支持 | 暂不支持 | +[e31207077](https://github.com/e31207077) <[email protected]> -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，LED 闪烁。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Jan 9 2019 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用 Ethernet 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -暂无 - -## 联系人信息 - -维护人: - -- [e31207077](https://github.com/e31207077), 邮箱：<[email protected]> +> +> https://github.com/mysterywolf diff --git a/bsp/stm32/stm32f767-st-nucleo/README_zh.md b/bsp/stm32/stm32f767-st-nucleo/README_zh.md new file mode 100644 index 0000000000..45ccf66f70 --- /dev/null +++ b/bsp/stm32/stm32f767-st-nucleo/README_zh.md @@ -0,0 +1,110 @@ +# STM32F767 NUCLEO-F767ZI开发板 BSP 说明 +## 简介 + +本文档为 NUCLEO-F767ZI 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-F767ZI 是st推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 216Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F767 的芯片性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32f767，主频 216MHz，2MB FLASH ，512KB RAM ，16K CACHE + +- 常用外设 + - LED ：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14） + - 按键：2个，B1（用户按键，PC13），B2（复位引脚） +- 常用接口：USB 转串口3、以太网接口 +- 调试接口：ST-LINK + +开发板更多详细信息请参考ST [NUCLEO-F767ZI开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :-----------------| :----------: | :-------------------------------------| +| USB 转串口3 | 支持 | | +| 以太网 | 支持 | PHY 选项 LAN8720A（兼容 LAN8742A） | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 | +| UART | 支持 | UART3 | +| **扩展模块** | **支持情况** | **备注** | +| 暂无 | 暂不支持 | 暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Jan 9 2019 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用 Ethernet 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [e31207077](https://github.com/e31207077), 邮箱：<[email protected]> diff --git a/bsp/stm32/stm32g070-st-nucleo/README.md b/bsp/stm32/stm32g070-st-nucleo/README.md index b221d5e6d2..bf3b978d28 100644 --- a/bsp/stm32/stm32g070-st-nucleo/README.md +++ b/bsp/stm32/stm32g070-st-nucleo/README.md @@ -1,116 +1,72 @@ -# STM32G071 BSP +# STM32G070-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 STM32G070RB-Nucleo 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32G070RB @64MHz, 128KB FLASH, 36KB RAM -主要内容如下： +The STM32G070CB/KB/RB mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The devices incorporate a memory protection unit (MPU), high-speed embedded memories (128 Kbytes of Flash program memory with read protection, write protection, and 36 Kbytes of SRAM), DMA and an extensive range of system functions, enhanced I/Os and peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one I2S, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, a low-power RTC, an advanced control PWM timer, five general-purpose 16-bit timers, two basic timers, two watchdog timers, and a SysTick timer. +The devices operate within ambient temperatures from -40 to 85°C. They can operate with supply voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes allows the design of low-power applications. +VBAT direct battery input allows keeping RTC and backup registers powered. +The devices come in packages with 32 to 64 pins. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz +- -40°C to 85°C operating temperature +- Memories + - 128 Kbytes of Flash memory with protection + - 36 Kbytes of SRAM (32 Kbytes with HW parity check) +- CRC calculation unit +- Reset and power management + - Voltage range: 2.0 V to 3.6 V + - Power-on/Power-down reset (POR/PDR) + - Low-power modes:Sleep, Stop, Standby + - VBAT supply for RTC and backup registers +- Clock management + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator with calibration + - Internal 16 MHz RC with PLL option + - Internal 32 kHz RC oscillator (±5 %) +- Up to 59 fast I/Os + - All mappable on external interrupt vectors + - Multiple 5 V-tolerant I/Os -STM32G070RB-Nucleo 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，最高主频为 64Mhz，该开发板具有丰富的扩展接口，可以方便验证 STM32G070RB 的芯片性能。 +- 7-channel DMA controller with flexible mapping +- 12-bit, 0.4 µs ADC (up to 16 ext. channels) + - Up to 16-bit with hardware oversampling + - Conversion range: 0 to 3.6V +- 11 timers: 16-bit for advanced motor control, five 16-bit general-purpose, two basic 16-bit, two watchdogs, SysTick timer +- Calendar RTC with alarm and periodic wakeup from Stop/Standby +- Communication interfaces + - Two I2C-bus interfaces supporting Fast-mode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode + - Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature + - Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface +- Development support: serial wire debug (SWD) +- All packages ECOPACK 2 compliant -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32G070RB，主频 64MHz，128KB FLASH ，36KB RAM -- 外部 RAM：无 -- 外部 FLASH：无 -- 常用外设 - - 按键：1个，user（兼具唤醒功能，PC13） -- 常用接口：USB 转串口、arduino 接口等 -- 调试接口，标准 SWD +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32G070RB ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32g070rb.html#documentation) | STM32G070RB datasheet and other resources | -开发板更多详细信息请参考 ST 的 [NUCLEO 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-g070rb.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| ST-LINK 虚拟串口 | 支持 | 使用 USART2 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | -| UART | 支持 | USART1/2/3 | -| TIM | 支持 | TIM1/3 | -| PWM | 支持 | | -| SPI | 支持 | SPI1/2 | -| I2C | 支持 | 软件 I2C | -| ADC | 支持 | | -| WDT | 支持 | | -| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | -| RTC | 暂不支持 | 详见注意事项 | +[NU-LL](https://github.com/NU-LL) -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 将工程使用的仿真器设置为ST-Link并安装仿真器好驱动程序以后，将开发板连接到PC，点击下载按钮即可下载程序到开发板。 - -#### 运行结果 - -下载程序成功之后，系统会自动运行。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build Jul 1 2020 - 2006 - 2019 Copyright by rt-thread team -msh > -``` - -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 UART 的功能，如果需使用 SPI，I2C 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- G0系列RTC驱动有点问题，详见论坛 [该贴](https://www.rt-thread.org/qa/thread-424601-1-2.html) - -## 联系人信息 - -维护人: - -- [NU-LL](https://github.com/NU-LL) +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32g070-st-nucleo/README_zh.md b/bsp/stm32/stm32g070-st-nucleo/README_zh.md new file mode 100644 index 0000000000..b221d5e6d2 --- /dev/null +++ b/bsp/stm32/stm32g070-st-nucleo/README_zh.md @@ -0,0 +1,116 @@ +# STM32G071 BSP + +## 简介 + +本文档为 STM32G070RB-Nucleo 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +STM32G070RB-Nucleo 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，最高主频为 64Mhz，该开发板具有丰富的扩展接口，可以方便验证 STM32G070RB 的芯片性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32G070RB，主频 64MHz，128KB FLASH ，36KB RAM +- 外部 RAM：无 +- 外部 FLASH：无 +- 常用外设 + - 按键：1个，user（兼具唤醒功能，PC13） +- 常用接口：USB 转串口、arduino 接口等 +- 调试接口，标准 SWD + +开发板更多详细信息请参考 ST 的 [NUCLEO 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-g070rb.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| ST-LINK 虚拟串口 | 支持 | 使用 USART2 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | USART1/2/3 | +| TIM | 支持 | TIM1/3 | +| PWM | 支持 | | +| SPI | 支持 | SPI1/2 | +| I2C | 支持 | 软件 I2C | +| ADC | 支持 | | +| WDT | 支持 | | +| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | +| RTC | 暂不支持 | 详见注意事项 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 将工程使用的仿真器设置为ST-Link并安装仿真器好驱动程序以后，将开发板连接到PC，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jul 1 2020 + 2006 - 2019 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 UART 的功能，如果需使用 SPI，I2C 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- G0系列RTC驱动有点问题，详见论坛 [该贴](https://www.rt-thread.org/qa/thread-424601-1-2.html) + +## 联系人信息 + +维护人: + +- [NU-LL](https://github.com/NU-LL) diff --git a/bsp/stm32/stm32g071-st-nucleo/README.md b/bsp/stm32/stm32g071-st-nucleo/README.md index d38cd76edd..928aea83fd 100644 --- a/bsp/stm32/stm32g071-st-nucleo/README.md +++ b/bsp/stm32/stm32g071-st-nucleo/README.md @@ -1,108 +1,80 @@ -# STM32G071 BSP +# STM32G071-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 RT-Thread 开发团队为 STM32G071RB-Nucleo 开发板提供的 BSP (板级支持包) 说明。 +## MCU: STM32G071RB @64MHz, 128KB FLASH, 36KB RAM -主要内容如下： +The STM32G071x8/xB mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The devices incorporate a memory protection unit (MPU), high-speed embedded memories (up to 128 Kbytes of Flash program memory with read protection, write protection, proprietary code protection, and securable area, and 36 Kbytes of SRAM), DMA and an extensive range of system functions, enhanced I/Os and peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one I2S, one HDMI CEC, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, two fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU frequency, five general-purpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer, two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The STM32G071x8/xB devices provide a fully integrated USB Type-C Power Delivery controller. +The devices operate within ambient temperatures from -40 to 125°C. They can operate with supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes, low-power timers and low-power UART, allows the design of low-power applications. +VBAT direct battery input allows keeping RTC and backup registers powered. +The devices come in packages with 28 to 64 pins. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz +- -40°C to 85°C/105°C/125°C operating temperature +- Memories + - Up to 128 Kbytes of Flash memory with protection and securable area + - 36 Kbytes of SRAM (32 Kbytes with HW parity check) +- CRC calculation unit +- Reset and power management + - Voltage range: 1.7 V to 3.6 V + - Power-on/Power-down reset (POR/PDR) + - Programmable Brownout reset (BOR) + - Programmable voltage detector (PVD) + - Low-power modes:Sleep, Stop, Standby, Shutdown + - VBAT supply for RTC and backup registers +- Clock management + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator with calibration + - Internal 16 MHz RC with PLL option (±1 %) + - Internal 32 kHz RC oscillator (±5 %) +- Up to 60 fast I/Os + - All mappable on external interrupt vectors + - Multiple 5 V-tolerant I/Os +- 7-channel DMA controller with flexible mapping +- 12-bit, 0.4 µs ADC (up to 16 ext. channels) + - Up to 16-bit with hardware oversampling + - Conversion range: 0 to 3.6V -STM32G071RB-Nucleo 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，最高主频为 64Mhz，该开发板具有丰富的扩展接口，可以方便验证 STM32G071RB 的芯片性能。 +- Two 12-bit DACs, low-power sample-and-hold +- Two fast low-power analog comparators, with programmable input and output, rail-to-rail +- 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16-bit general-purpose, two basic 16-bit, two low-power 16-bit, two watchdogs, SysTick timer +- Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown +- Communication interfaces + - Two I2C-bus interfaces supporting Fast-mode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode + - Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature + - One low-power UART + - Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface + - HDMI CEC interface, wakeup on header +- USB Type-C™ Power Delivery controller +- Development support: serial wire debug (SWD) +- 96-bit unique ID +- All packages ECOPACK®2 compliant -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32G071RB，主频 64MHz，128KB FLASH ，36KB RAM -- 外部 RAM：无 -- 外部 FLASH：无 -- 常用外设 - - 按键：1个，user（兼具唤醒功能，PC13） -- 常用接口：USB 转串口、arduino 接口等 -- 调试接口，标准 SWD +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32G071RB ST Official Website](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-g071rb.html#documentation) | STM32G071RB datasheet and other resources | -开发板更多详细信息请参考 ST 的 [NUCLEO 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-g071rb.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| ST-LINK 虚拟串口 | 支持 | 使用 LPUART | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | -| UART | 支持 | LPUART1, USART1/2 | +[gztss](https://github.com/gztss) -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 将工程使用的仿真器设置为ST-Link并安装仿真器好驱动程序以后，将开发板连接到PC，点击下载按钮即可下载程序到开发板。 - -#### 运行结果 - -下载程序成功之后，系统会自动运行。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Dec 21 2018 - 2006 - 2018 Copyright by rt-thread team -msh > -``` - -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 LPUART 的功能，如果需使用 SPI，I2C 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 无 - -## 联系人信息 - -维护人: - -- [gztss](https://github.com/gztss) +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32g071-st-nucleo/README_zh.md b/bsp/stm32/stm32g071-st-nucleo/README_zh.md new file mode 100644 index 0000000000..d38cd76edd --- /dev/null +++ b/bsp/stm32/stm32g071-st-nucleo/README_zh.md @@ -0,0 +1,108 @@ +# STM32G071 BSP + +## 简介 + +本文档为 RT-Thread 开发团队为 STM32G071RB-Nucleo 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +STM32G071RB-Nucleo 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，最高主频为 64Mhz，该开发板具有丰富的扩展接口，可以方便验证 STM32G071RB 的芯片性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32G071RB，主频 64MHz，128KB FLASH ，36KB RAM +- 外部 RAM：无 +- 外部 FLASH：无 +- 常用外设 + - 按键：1个，user（兼具唤醒功能，PC13） +- 常用接口：USB 转串口、arduino 接口等 +- 调试接口，标准 SWD + +开发板更多详细信息请参考 ST 的 [NUCLEO 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-g071rb.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| ST-LINK 虚拟串口 | 支持 | 使用 LPUART | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | LPUART1, USART1/2 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 将工程使用的仿真器设置为ST-Link并安装仿真器好驱动程序以后，将开发板连接到PC，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 21 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 LPUART 的功能，如果需使用 SPI，I2C 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 无 + +## 联系人信息 + +维护人: + +- [gztss](https://github.com/gztss) diff --git a/bsp/stm32/stm32g431-st-nucleo/README.md b/bsp/stm32/stm32g431-st-nucleo/README.md index 64ed19231b..5446988f28 100644 --- a/bsp/stm32/stm32g431-st-nucleo/README.md +++ b/bsp/stm32/stm32g431-st-nucleo/README.md @@ -1,106 +1,108 @@ -# NUCLEO-G431RB 开发板 BSP 说明 +# STM32G431-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 NUCLEO-G431RB 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32G431RB @170MHz, 128KB FLASH, 32KB RAM -主要内容如下： +The STM32G431x6/x8/xB devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security. +These devices embed high-speed memories (128 Kbytes of Flash memory, and 32 Kbytes of SRAM), an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. +The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection. +The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions). +They offer two fast 12-bit ADCs (5 Msps), four comparators, three operational amplifiers, four DAC channels (2 external and 2 internal), an internal voltage reference buffer, a low-power RTC, one general-purpose 32-bit timers, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer. +They also feature standard and advanced communication interfaces such as: +\- Three I2Cs +\- Three SPIs multiplexed with two half duplex I2Ss +\- Three USARTs, one UART and one low-power UART. +\- One FDCAN +\- One SAI +\- USB device +\- UCPD +The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. +Some independent power supplies are supported including an analog independent supply input for ADC, DAC, OPAMPs and comparators. A VBAT input allows backup of the RTC and the registers. +The STM32G431x6/x8/xB family offers 9 packages from 32-pin to 100-pin. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions +- Operating conditions: + - VDD, VDDA voltage range: 1.71 V to 3.6 V +- Mathematical hardware accelerators + - CORDIC for trigonometric functions acceleration + - FMAC: filter mathematical accelerator +- Memories + - 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP + - 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes + - Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) +- Reset and supply management + - Power-on/power-down reset (POR/PDR/BOR) + - Programmable voltage detector (PVD) + - Low-power modes: sleep, stop, standby and shutdown + - VBAT supply for RTC and backup registers +- Clock management + - 4 to 48 MHz crystal oscillator + - 32 kHz oscillator with calibration + - Internal 16 MHz RC with PLL option (± 1%) + - Internal 32 kHz RC oscillator (± 5%) +- Up to 86 fast I/Os + - All mappable on external interrupt vectors + - Several I/Os with 5 V tolerant capability +- Interconnect matrix +- 12-channel DMA controller +- 2 x ADCs 0.25 µs (up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range -NUCLEO-G431RB 是 ST 公司推出的一款针对 STM32G4 系列设计的 Cortex-M4 Nucleo-64 开发板，支持 mbed，兼容 Arduino、还带有 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 +- 4 x 12-bit DAC channels + - 2 x buffered external channels 1 MSPS + - 2 x unbuffered internal channels 15 MSPS +- 4 x ultra-fast rail-to-rail analog comparators +- 3 x operational amplifiers that can be used in PGA mode, all terminals accessible +- Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.9 V) +- 14 timers: + - 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop + - 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop + - 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop + - 2 x watchdog timers (independent, window) + - 1 x SysTick timer: 24-bit downcounter + - 2 x 16-bit basic timers + - 1 x low-power timer +- Calendar RTC with alarm, periodic wakeup from stop/standby +- Communication interfaces + - 1 x FDCAN controller supporting flexible data rate + - 3 x I2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop + - 4 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control) + - 1 x LPUART + - 3 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I2S interface + - 1 x SAI (serial audio interface) + - USB 2.0 full-speed interface with LPM and BCD support + - IRTIM (infrared interface) + - USB Type-C™ /USB power delivery controller (UCPD) +- True random number generator (RNG) +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32G431RB，主频 170MHz，128KB FLASH ，22KB RAM -- 常用外设 - - LED：1个，LD2（黄色，PA5） -- 常用接口：USB 转串口 -- 调试接口，标准 ST-LINK/SWD +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32G431RB ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32g431rb.html#documentation) | STM32G431RB datasheet and other resources | -开发板更多详细信息请参考【NUCLEO-G431RB】 [开发板介绍](https://www.st.com/zh/evaluation-tools/nucleo-g431rb.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| USB 转串口 | 支持 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | | -| UART | 支持 | LPUART1 USART1/3 UART4 | +[xuzhuoyi](https://github.com/xuzhuoyi), <[email protected]> -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，通过数据线对开发板供电,下载,调试。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，黄色的 LD2 以 500MS 周期闪烁。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build Oct 5 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 LPUART1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 默认终端输出设备是 LPUART1 - -## 联系人信息 - -维护人: - -- [xuzhuoyi](https://github.com/xuzhuoyi), 邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32g431-st-nucleo/README_zh.md b/bsp/stm32/stm32g431-st-nucleo/README_zh.md new file mode 100644 index 0000000000..a3dd55ad36 --- /dev/null +++ b/bsp/stm32/stm32g431-st-nucleo/README_zh.md @@ -0,0 +1,106 @@ +# NUCLEO-G431RB 开发板 BSP 说明 + +## 简介 + +本文档为 NUCLEO-G431RB 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-G431RB 是 ST 公司推出的一款针对 STM32G4 系列设计的 Cortex-M4 Nucleo-64 开发板，支持 mbed，兼容 Arduino、还带有 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32G431RB，主频 170MHz，128KB FLASH ，32KB RAM +- 常用外设 + - LED：1个，LD2（黄色，PA5） +- 常用接口：USB 转串口 +- 调试接口，标准 ST-LINK/SWD + +开发板更多详细信息请参考【NUCLEO-G431RB】 [开发板介绍](https://www.st.com/zh/evaluation-tools/nucleo-g431rb.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | LPUART1 USART1/3 UART4 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，通过数据线对开发板供电,下载,调试。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，黄色的 LD2 以 500MS 周期闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Oct 5 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 LPUART1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 默认终端输出设备是 LPUART1 + +## 联系人信息 + +维护人: + +- [xuzhuoyi](https://github.com/xuzhuoyi), 邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig index e2d7618062..a2065dc17e 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig @@ -41,6 +41,13 @@ menu "Onboard Peripheral Drivers" select RT_USING_DFS_ELMFAT default n + config BSP_USING_OV2640 + bool "Enable camera (ov2640)" + select BSP_USING_DCMI + select BSP_USING_I2C + select BSP_USING_I2C2 + default n + endmenu menu "On-chip Peripheral Drivers" @@ -98,28 +105,55 @@ menu "On-chip Peripheral Drivers" select RT_USING_SPI default n - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C1 - comment "Notice: PH4 --> 116; PH5 --> 117" - config BSP_I2C1_SCL_PIN - int "i2c1 scl pin number" - range 1 176 - default 116 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - range 1 176 - default 117 - endif + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + default n + if BSP_USING_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + if BSP_USING_I2C1 + comment "Notice: PH4 --> 116; PH5 --> 117" + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 116 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 117 + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + if BSP_USING_I2C2 + comment "Notice: PH13 --> 125; PH15 --> 127" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 176 + default 127 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 1 176 + default 125 + endif + endif config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n + config BSP_USING_DCMI + bool "Enable DCMI" + default n + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC diff --git a/bsp/stm32/stm32h743-atk-apollo/board/SConscript b/bsp/stm32/stm32h743-atk-apollo/board/SConscript index 8ed2e269df..07cbe41b4f 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/SConscript +++ b/bsp/stm32/stm32h743-atk-apollo/board/SConscript @@ -17,6 +17,10 @@ if GetDepend(['BSP_USING_QSPI_FLASH']): src += Glob('ports/drv_qspi_flash.c') if GetDepend(['BSP_USING_SDMMC']): src += Glob('ports/drv_sdio.c') +if GetDepend(['BSP_USING_DCMI']): + src += Glob('ports/drv_dcmi.c') +if GetDepend(['BSP_USING_OV2640']): + src += Glob('ports/drv_ov2640.c') path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c new file mode 100644 index 0000000000..8a57c37e01 --- /dev/null +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu the first version + */ + +#include "board.h" + +#if defined(BSP_USING_DCMI) + +#include <drv_dcmi.h> + +#define DRV_DEBUG +#define LOG_TAG "drv.dcmi" +#include <drv_log.h> + +struct stm32_dcmi +{ + DCMI_HandleTypeDef DCMI_Handle; + struct rt_dcmi_device dev; +}; +static struct stm32_dcmi rt_dcmi = {0}; + +DMA_HandleTypeDef hdma_dcmi; + +static void rt_hw_dcmi_dma_init(void) +{ + __HAL_RCC_DMA2_CLK_ENABLE(); + + hdma_dcmi.Instance = DMA2_Stream1; + hdma_dcmi.Init.Request = DMA_REQUEST_DCMI; + hdma_dcmi.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_dcmi.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_dcmi.Init.MemInc = DMA_MINC_ENABLE; + hdma_dcmi.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_dcmi.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_dcmi.Init.Mode = DMA_CIRCULAR; + hdma_dcmi.Init.Priority = DMA_PRIORITY_HIGH; + hdma_dcmi.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_dcmi.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_dcmi.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_dcmi.Init.PeriphBurst = DMA_PBURST_SINGLE; + + HAL_DMA_DeInit(&hdma_dcmi); + HAL_DMA_Init(&hdma_dcmi); + + __HAL_LINKDMA(&rt_dcmi.DCMI_Handle, DMA_Handle, hdma_dcmi); + + HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 0x00, 0x00); + HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);; +} + +void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint32_t len) +{ + __HAL_UNLOCK(&hdma_dcmi); + + HAL_DMAEx_MultiBufferStart(&hdma_dcmi, (rt_uint32_t)&DCMI->DR, dst_addr1, dst_addr2, len); + + __HAL_DMA_ENABLE_IT(&hdma_dcmi, DMA_IT_TC); +} + +static rt_err_t rt_hw_dcmi_init(DCMI_HandleTypeDef *device) +{ + RT_ASSERT(device != RT_NULL); + + device->Instance = DCMI; + device->Init.SynchroMode = DCMI_SYNCHRO_HARDWARE; + device->Init.PCKPolarity = DCMI_PCKPOLARITY_RISING; + device->Init.VSPolarity = DCMI_VSPOLARITY_LOW; + device->Init.HSPolarity = DCMI_HSPOLARITY_LOW; + device->Init.CaptureRate = DCMI_CR_ALL_FRAME; + device->Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B; + device->Init.JPEGMode = DCMI_JPEG_ENABLE; + device->Init.ByteSelectMode = DCMI_BSM_ALL; + device->Init.ByteSelectStart = DCMI_OEBS_ODD; + device->Init.LineSelectMode = DCMI_LSM_ALL; + device->Init.LineSelectStart = DCMI_OELS_ODD; + + if (HAL_DCMI_Init(device) != HAL_OK) + { + LOG_E("dcmi init error!"); + return RT_ERROR; + } + + DCMI->IER = 0x0; + + __HAL_DCMI_ENABLE_IT(device, DCMI_IT_FRAME); + __HAL_DCMI_ENABLE(device); + + return RT_EOK; +} + +void DCMI_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DCMI_IRQHandler(&rt_dcmi.DCMI_Handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DCMI_Start(void) +{ + __HAL_DMA_ENABLE(&hdma_dcmi); + DCMI->CR |= DCMI_CR_CAPTURE; +} + +void DCMI_Stop(void) +{ + DCMI->CR &= ~(DCMI_CR_CAPTURE); + while (DCMI->CR & 0x01); + __HAL_DMA_DISABLE(&hdma_dcmi); +} + +/* Capture a frame of the image */ +void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) +{ + extern void camera_frame_data_process(void); + /* enter interrupt */ + rt_interrupt_enter(); + /* move frame data to buffer */ + camera_frame_data_process(); + + __HAL_DCMI_ENABLE_IT(&rt_dcmi.DCMI_Handle, DCMI_IT_FRAME); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA2_Stream1_IRQHandler(void) +{ + extern void camera_dma_data_process(void); + /* enter interrupt */ + rt_interrupt_enter(); + + if (__HAL_DMA_GET_FLAG(&hdma_dcmi, DMA_FLAG_TCIF1_5) != RESET) + { + __HAL_DMA_CLEAR_FLAG(&hdma_dcmi, DMA_FLAG_TCIF1_5); + /* move dma data to buffer */ + camera_dma_data_process(); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static rt_err_t rt_dcmi_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + rt_err_t result = RT_EOK; + + result = rt_hw_dcmi_init(&rt_dcmi.DCMI_Handle); + if (result != RT_EOK) + { + return result; + } + + rt_hw_dcmi_dma_init(); + + return result; +} + +static rt_err_t rt_dcmi_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_dcmi_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_dcmi_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_dcmi_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_dcmi_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +int dcmi_init(void) +{ + rt_dcmi.dev.parent.type = RT_Device_Class_Miscellaneous; + rt_dcmi.dev.parent.init = rt_dcmi_init; + rt_dcmi.dev.parent.open = rt_dcmi_open; + rt_dcmi.dev.parent.close = rt_dcmi_close; + rt_dcmi.dev.parent.read = rt_dcmi_read; + rt_dcmi.dev.parent.write = rt_dcmi_write; + rt_dcmi.dev.parent.control = rt_dcmi_control; + rt_dcmi.dev.parent.user_data = RT_NULL; + + rt_device_register(&rt_dcmi.dev.parent, "dcmi", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + LOG_I("dcmi init success!"); + + return RT_EOK; +} +INIT_BOARD_EXPORT(dcmi_init); + +#endif diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h new file mode 100644 index 0000000000..af519987dd --- /dev/null +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu the first version + */ + +#ifndef __DRV_DCMI_H__ +#define __DRV_DCMI_H__ + +#include "board.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct rt_dcmi_device +{ + struct rt_device parent; +}; + +extern DMA_HandleTypeDef hdma_dcmi; +extern void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint32_t len); +extern void DCMI_Start(void); +extern void DCMI_Stop(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c new file mode 100644 index 0000000000..0ed9345156 --- /dev/null +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c @@ -0,0 +1,751 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-03 thread-liu the first version + */ + +#include "board.h" + +#if defined(BSP_USING_OV2640) + +#include <dfs_posix.h> +#include <drv_ov2640.h> +#include <drv_dcmi.h> +#include "pcf8574.h" + +#define DRV_DEBUG +//#define CAMERA_DUMP +#define LOG_TAG "drv.ov2640" +#include <drv_log.h> + +#define DEV_ADDRESS 0x30 /* OV2640 address */ +#define I2C_NAME "i2c2" + +#define RESET_PIN GET_PIN(A, 15) /* camera reset pin */ + +/* camera PWDN pin */ +#define DCMI_PWDN_IO 2 /* pcf8574 (0-7) */ + +volatile rt_uint32_t jpeg_data_len = 0; +volatile rt_uint8_t jpeg_data_ok = 0; +struct rt_i2c_bus_device *i2c_bus = RT_NULL; + +#define JPEG_BUF_SIZE 32 * 1024 +#define JPEG_LINE_SIZE 1 * 1024 + +static pcf8574_device_t pcf_dev = RT_NULL; + +static rt_uint32_t *jpeg_data_buf = RT_NULL; +static rt_uint32_t JPEG_LINE0_BUF[JPEG_LINE_SIZE]; +static rt_uint32_t JPEG_LINE1_BUF[JPEG_LINE_SIZE]; + +#if defined(CAMERA_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08x:", i); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%02x", buf[i + j]); + } + else + { + rt_kprintf(" "); + } + } + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } + rt_kprintf("\n"); + } +} +#endif + +static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf) +{ + struct rt_i2c_msg msg[2]; + + RT_ASSERT(bus != RT_NULL); + + msg[0].addr = DEV_ADDRESS; + msg[0].flags = RT_I2C_WR; + msg[0].buf = ® + msg[0].len = 2; + + msg[1].addr = DEV_ADDRESS; + msg[1].flags = RT_I2C_RD; + msg[1].len = len; + msg[1].buf = buf; + + if (rt_i2c_transfer(bus, msg, 2) == 2) + { + return RT_EOK; + } + + return RT_ERROR; +} + +/* i2c write reg */ +static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t data) +{ + rt_uint8_t buf[2]; + struct rt_i2c_msg msgs; + + RT_ASSERT(bus != RT_NULL); + + buf[0] = reg ; + buf[1] = data; + + msgs.addr = DEV_ADDRESS; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = 2; + + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + + return RT_ERROR; +} + +static rt_err_t ov2640_read_id(struct rt_i2c_bus_device *bus) +{ + rt_uint8_t read_value[2]; + rt_uint16_t id = 0; + read_reg(bus, OV2640_SENSOR_MIDH, 1, &read_value[0]); + read_reg(bus, OV2640_SENSOR_MIDL, 1, &read_value[1]); + id = ((rt_uint16_t)(read_value[0] << 8) & 0xFF00); + id |= ((rt_uint16_t)(read_value[1]) & 0x00FF); + + if (id != OV2640_MID) + { + LOG_E("ov2640 init error, mid: 0x%04x", id); + return RT_ERROR; + } + + LOG_I("ov2640 read mid success, mid: 0x%04x", id); + + read_reg(bus, OV2640_SENSOR_PIDH, 1, &read_value[0]); + read_reg(bus, OV2640_SENSOR_PIDL, 1, &read_value[1]); + id = ((rt_uint16_t)(read_value[0] << 8) & 0xFF00); + id |= ((rt_uint16_t)(read_value[1]) & 0x00FF); + + if (id != OV2640_PID) + { + LOG_E("ov2640 init error, pid: 0x%04x", id); + return RT_ERROR; + } + + LOG_I("ov2640 read hid success, pid: 0x%04x", id); + + return RT_EOK; +} + +/* change ov2640 to jpeg mode */ +void ov2640_jpeg_mode(void) +{ + rt_uint16_t i=0; + /* set yun422 mode */ + for (i = 0; i < (sizeof(ov2640_yuv422_reg_tbl) / 2); i++) + { + write_reg(i2c_bus, ov2640_yuv422_reg_tbl[i][0],ov2640_yuv422_reg_tbl[i][1]); + } + + /* set jpeg mode */ + for(i=0;i<(sizeof(ov2640_jpeg_reg_tbl)/2);i++) + { + write_reg(i2c_bus, ov2640_jpeg_reg_tbl[i][0],ov2640_jpeg_reg_tbl[i][1]); + } +} + +/* change ov2640 to rgb565 mode */ +void ov2640_rgb565_mode(void) +{ + rt_uint16_t i=0; + for (i = 0; i < (sizeof(ov2640_rgb565_reg_tbl) / 2); i++) + { + write_reg(i2c_bus, ov2640_rgb565_reg_tbl[i][0],ov2640_rgb565_reg_tbl[i][1]); + } +} + +/* set auto exposure */ +void ov2640_set_auto_exposure(rt_uint8_t level) +{ + rt_uint8_t i = 0; + rt_uint8_t *p = (rt_uint8_t*)OV2640_AUTOEXPOSURE_LEVEL[level]; + for (i = 0; i < 4; i++) + { + write_reg(i2c_bus, p[i*2],p[i*2+1]); + } +} + +/* set light mode + * 0: auto + * 1: sunny + * 2: cloudy + * 3: office + * 4: home + * */ +void ov2640_set_light_mode(rt_uint8_t mode) +{ + rt_uint8_t regccval, regcdval, regceval; + + switch(mode) + { + case 0: + write_reg(i2c_bus, 0xFF, 0x00); + write_reg(i2c_bus, 0xC7, 0x10); + return; + + case 2: + regccval = 0x65; + regcdval = 0x41; + regceval = 0x4F; + break; + + case 3: + regccval = 0x52; + regcdval = 0x41; + regceval = 0x66; + break; + + case 4: + regccval = 0x42; + regcdval = 0x3F; + regceval = 0x71; + break; + + default: + regccval = 0x5E; + regcdval = 0x41; + regceval = 0x54; + break; + } + + write_reg(i2c_bus, 0xFF, 0x00); + write_reg(i2c_bus, 0xC7, 0x40); + write_reg(i2c_bus, 0xCC, regccval); + write_reg(i2c_bus, 0xCD, regcdval); + write_reg(i2c_bus, 0xCE, regceval); +} + +/* set color saturation + * 0: -2 + * 1: -1 + * 2: 0 + * 3: +1 + * 4: +2 + * */ +void ov2640_set_color_saturation(rt_uint8_t sat) +{ + rt_uint8_t reg7dval = ((sat+2)<<4) | 0x08; + write_reg(i2c_bus, 0xFF, 0X00); + write_reg(i2c_bus, 0x7C, 0X00); + write_reg(i2c_bus, 0x7D, 0X02); + write_reg(i2c_bus, 0x7C, 0X03); + write_reg(i2c_bus, 0x7D, reg7dval); + write_reg(i2c_bus, 0x7D, reg7dval); +} + +/* set brightness + * 0: -2 + * 1: -1 + * 2: 0 + * 3: 1 + * 4: 2 + * */ +void ov2640_set_brightness(rt_uint8_t bright) +{ + write_reg(i2c_bus, 0xff, 0x00); + write_reg(i2c_bus, 0x7c, 0x00); + write_reg(i2c_bus, 0x7d, 0x04); + write_reg(i2c_bus, 0x7c, 0x09); + write_reg(i2c_bus, 0x7d, bright << 4); + write_reg(i2c_bus, 0x7d, 0x00); +} + +/* set contrast + * 0: -2 + * 1: -1 + * 2: 0 + * 3: 1 + * 4: 2 + * */ +void ov2640_set_contrast(rt_uint8_t contrast) +{ + rt_uint8_t reg7d0val, reg7d1val; + + switch(contrast) + { + case 0: + reg7d0val = 0x18; + reg7d1val = 0x34; + break; + + case 1: + reg7d0val = 0x1C; + reg7d1val = 0x2A; + break; + + case 3: + reg7d0val = 0x24; + reg7d1val = 0x16; + break; + + case 4: + reg7d0val = 0x28; + reg7d1val = 0x0C; + break; + + default: + reg7d0val = 0x20; + reg7d1val = 0x20; + break; + } + write_reg(i2c_bus, 0xff, 0x00); + write_reg(i2c_bus, 0x7c, 0x00); + write_reg(i2c_bus, 0x7d, 0x04); + write_reg(i2c_bus, 0x7c, 0x07); + write_reg(i2c_bus, 0x7d, 0x20); + write_reg(i2c_bus, 0x7d, reg7d0val); + write_reg(i2c_bus, 0x7d, reg7d1val); + write_reg(i2c_bus, 0x7d, 0x06); +} + +/* set special effects + * 0: noraml + * 1: negative film + * 2: black-and-white + * 3: the red + * 4: the green + * 5: the blue + * 6: Retro +*/ +void ov2640_set_special_effects(rt_uint8_t eft) +{ + rt_uint8_t reg7d0val, reg7d1val, reg7d2val; + + switch(eft) + { + case 1: + reg7d0val = 0x40; + break; + case 2: + reg7d0val = 0x18; + break; + case 3: + reg7d0val = 0x18; + reg7d1val = 0x40; + reg7d2val = 0xC0; + break; + case 4: + reg7d0val = 0x18; + reg7d1val = 0x40; + reg7d2val = 0x40; + break; + case 5: + reg7d0val = 0x18; + reg7d1val = 0xA0; + reg7d2val = 0x40; + break; + case 6: + reg7d0val = 0x18; + reg7d1val = 0x40; + reg7d2val = 0xA6; + break; + default: + reg7d0val = 0x00; + reg7d1val = 0x80; + reg7d2val = 0x80; + break; + } + write_reg(i2c_bus, 0xff, 0x00); + write_reg(i2c_bus, 0x7c, 0x00); + write_reg(i2c_bus, 0x7d, reg7d0val); + write_reg(i2c_bus, 0x7c, 0x05); + write_reg(i2c_bus, 0x7d, reg7d1val); + write_reg(i2c_bus, 0x7d, reg7d2val); +} + +/* set the image output window */ +void ov2640_set_window_size(rt_uint16_t sx,rt_uint16_t sy,rt_uint16_t width,rt_uint16_t height) +{ + rt_uint16_t endx; + rt_uint16_t endy; + rt_uint8_t temp; + endx = sx + width / 2; + endy = sy + height / 2; + + write_reg(i2c_bus, 0xFF, 0x01); + read_reg(i2c_bus, 0x03, 1, &temp); + temp &= 0xF0; + temp |= ((endy & 0x03) << 2) | (sy & 0x03); + write_reg(i2c_bus, 0x03, temp); + write_reg(i2c_bus, 0x19, sy>>2); + write_reg(i2c_bus, 0x1A, endy>>2); + + read_reg(i2c_bus, 0x32, 1, &temp); + temp &= 0xC0; + temp |= ((endx & 0x07) << 3) | (sx & 0x07); + write_reg(i2c_bus, 0x32, temp); + write_reg(i2c_bus, 0x17, sx>>3); + write_reg(i2c_bus, 0x18, endx>>3); +} + +/* set the image output size */ +rt_uint8_t ov2640_set_image_out_size(rt_uint16_t width,rt_uint16_t height) +{ + rt_uint16_t outh, outw; + rt_uint8_t temp; + + if(width%4)return 1; + if(height%4)return 2; + outw = width / 4; + outh = height / 4; + write_reg(i2c_bus, 0xFF, 0x00); + write_reg(i2c_bus, 0xE0, 0x04); + write_reg(i2c_bus, 0x5A, outw & 0XFF); + write_reg(i2c_bus, 0x5B, outh & 0XFF); + temp = (outw >> 8) & 0x03; + temp |= (outh >> 6) & 0x04; + write_reg(i2c_bus, 0x5C, temp); + write_reg(i2c_bus, 0xE0, 0X00); + + return RT_EOK; +} + +/* set the image window size */ +rt_uint8_t ov2640_set_image_window_size(rt_uint16_t offx, rt_uint16_t offy, rt_uint16_t width, rt_uint16_t height) +{ + rt_uint16_t hsize, vsize; + rt_uint8_t temp; + if ((width % 4) || (height%4)) + { + return RT_ERROR; + } + hsize = width / 4; + vsize = height / 4; + write_reg(i2c_bus, 0XFF,0X00); + write_reg(i2c_bus, 0XE0,0X04); + write_reg(i2c_bus, 0X51,hsize&0XFF); + write_reg(i2c_bus, 0X52,vsize&0XFF); + write_reg(i2c_bus, 0X53,offx&0XFF); + write_reg(i2c_bus, 0X54,offy&0XFF); + temp=(vsize>>1)&0X80; + temp|=(offy>>4)&0X70; + temp|=(hsize>>5)&0X08; + temp|=(offx>>8)&0X07; + write_reg(i2c_bus, 0X55,temp); + write_reg(i2c_bus, 0X57,(hsize>>2)&0X80); + write_reg(i2c_bus, 0XE0,0X00); + return 0; +} + +/* set output resolution */ +rt_uint8_t ov2640_set_image_size(rt_uint16_t width ,rt_uint16_t height) +{ + rt_uint8_t temp; + write_reg(i2c_bus, 0xFF, 0x00); + write_reg(i2c_bus, 0xE0, 0x04); + write_reg(i2c_bus, 0xC0, (width >>3) & 0xFF); + write_reg(i2c_bus, 0xC1, (height >> 3) & 0xFF); + temp = (width & 0x07) << 3; + temp |= height & 0x07; + temp |= (width >> 4) & 0x80; + write_reg(i2c_bus, 0x8C, temp); + write_reg(i2c_bus, 0xE0, 0x00); + + return RT_EOK; +} + +void camera_dma_data_process(void) +{ + rt_uint16_t i; + rt_uint32_t *pbuf; + pbuf = jpeg_data_buf + jpeg_data_len; + + if (DMA2_Stream1->CR & (1<<19)) + { + for (i = 0; i < JPEG_LINE_SIZE; i++) + { + pbuf[i] = JPEG_LINE0_BUF[i]; + } + jpeg_data_len += JPEG_LINE_SIZE; + } + else + { + for (i = 0; i < JPEG_LINE_SIZE; i++) + { + pbuf[i] = JPEG_LINE1_BUF[i]; + } + jpeg_data_len += JPEG_LINE_SIZE; + } + SCB_CleanInvalidateDCache(); +} + +/* After a frame of picture data has been collected. */ +void camera_frame_data_process(void) +{ + rt_uint16_t i, rlen; + rt_uint32_t *pbuf = RT_NULL; + + if (jpeg_data_ok == 0) + { + DMA2_Stream1->CR &= ~(1<<0); + while(DMA2_Stream1->CR & 0x01); + + rlen = JPEG_LINE_SIZE - DMA2_Stream1->NDTR; + pbuf = jpeg_data_buf + jpeg_data_len; + + if (DMA2_Stream1->CR & (1<<19)) + { + for (i = 0; i < rlen; i++) + { + pbuf[i] = JPEG_LINE1_BUF[i]; + } + } + else + { + for (i = 0; i < rlen; i++) + { + pbuf[i] = JPEG_LINE0_BUF[i]; + } + } + jpeg_data_len += rlen; + jpeg_data_ok = 1; + } + if (jpeg_data_ok==2) + { + DMA2_Stream1->NDTR = JPEG_LINE_SIZE; + DMA2_Stream1->CR |= 1<<0; + jpeg_data_ok = 0; + jpeg_data_len = 0; + } +} + +int ov2640_pwdn_set(rt_uint8_t sta) +{ + if (pcf_dev == RT_NULL) + { + LOG_E("can't find pcf8574 device!"); + return -1; + } + pcf8574_pin_write(pcf_dev, DCMI_PWDN_IO, sta); + + return 0; +} + +void sw_ov2640_mode(void) +{ + GPIO_InitTypeDef GPIO_Initure = {0}; + + ov2640_pwdn_set(0); + + GPIO_Initure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11; + GPIO_Initure.Mode = GPIO_MODE_AF_PP; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Alternate = GPIO_AF13_DCMI; + HAL_GPIO_Init(GPIOC,&GPIO_Initure); +} + +void sw_sdcard_mode(void) +{ + GPIO_InitTypeDef GPIO_Initure = {0}; + + ov2640_pwdn_set(1); /* OV2640 Power Down */ + + GPIO_Initure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11; + GPIO_Initure.Mode = GPIO_MODE_AF_PP; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOC, &GPIO_Initure); +} + +int rt_ov2640_init(void) +{ + rt_uint16_t i = 0; + rt_err_t result = RT_EOK; + rt_device_t dcmi_dev = RT_NULL; + + sw_ov2640_mode(); + pcf_dev = pcf8574_init("i2c1", RT_NULL); + if (pcf_dev == RT_NULL) + { + LOG_E("can't find pcf8574, please check it"); + return -RT_ERROR; + } + + ov2640_pwdn_set(0); + rt_thread_delay(20); + + /* ov2640 hard reset */ + rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT); + rt_pin_write(RESET_PIN, PIN_LOW); + rt_thread_delay(20); + rt_pin_write(RESET_PIN, PIN_HIGH); + rt_thread_delay(20); + + i2c_bus = rt_i2c_bus_device_find(I2C_NAME); + if (i2c_bus == RT_NULL) + { + LOG_E("can't find %s deivce", I2C_NAME); + return RT_ERROR; + } + /* Prepare the camera to be configured */ + result = write_reg(i2c_bus, OV2640_DSP_RA_DLMT, 0x01); + if (result != RT_EOK ) + { + LOG_E("ov2640 write reg error!"); + return RT_ERROR; + } + rt_thread_delay(10); + result = write_reg(i2c_bus, OV2640_SENSOR_COM7, 0x80); + if (result != RT_EOK) + { + LOG_E("ov2640 soft reset error!"); + return RT_ERROR; + } + rt_thread_delay(20); + + result = ov2640_read_id(i2c_bus); + if (result != RT_EOK ) + { + LOG_E("ov2640 read id error!"); + return RT_ERROR; + } + + for (i = 0; i < sizeof(ov2640_svga_init_reg_tbl) / 2; i++) + { + write_reg(i2c_bus, ov2640_svga_init_reg_tbl[i][0], ov2640_svga_init_reg_tbl[i][1]); + } + + ov2640_rgb565_mode(); + ov2640_set_light_mode(0); + ov2640_set_color_saturation(3); + ov2640_set_brightness(4); + ov2640_set_contrast(3); + ov2640_jpeg_mode(); + ov2640_set_image_window_size(0, 0, 320, 240); + ov2640_set_image_out_size(320, 240); + + dcmi_dev = rt_device_find("dcmi"); + if (dcmi_dev == RT_NULL) + { + LOG_E("can't find dcmi device!"); + return RT_ERROR; + } + rt_device_open(dcmi_dev, RT_DEVICE_FLAG_RDWR); + + jpeg_data_buf = rt_malloc(JPEG_BUF_SIZE); + if (RT_NULL == jpeg_data_buf) + { + rt_kprintf("jpeg data buf malloc error!\n"); + return RT_ERROR; + } + + /* start dcmi capture */ + rt_hw_dcmi_dma_config((rt_uint32_t)JPEG_LINE0_BUF, (rt_uint32_t)JPEG_LINE1_BUF, JPEG_LINE_SIZE); + + rt_kprintf("camera init success!\n"); + + return RT_EOK; +} +INIT_APP_EXPORT(rt_ov2640_init); + +int camera_sample(int argc, char **argv) +{ + rt_err_t result = RT_EOK; + int fd = -1; + rt_uint32_t i, jpg_start, jpg_len; + rt_uint8_t jpg_head = 0; + rt_uint8_t *p = RT_NULL; + + if (argc != 2) + { + rt_kprintf("Usage:\n"); + rt_kprintf("camera_sample file.jpg\n"); + return -1; + } + + sw_ov2640_mode(); + DCMI_Start(); + + while (1) + { + while (jpeg_data_ok != 1); + jpeg_data_ok = 2; + while (jpeg_data_ok != 1); + DCMI_Stop(); + + p = (rt_uint8_t *)jpeg_data_buf; + jpg_len = 0; + jpg_head = 0; + for (i = 0; i < jpeg_data_len * 4; i++) + { + /* jpg head */ + if ((p[i] == 0xFF) && (p[i + 1] == 0xD8)) + { + jpg_start = i; + jpg_head = 1; + } + /* jpg end */ + if ((p[i] == 0xFF) && (p[i + 1] == 0xD9) && jpg_head) + { + jpg_len = i - jpg_start + 2; /* a picture len */ + break; + } + } + if (jpg_len) + { + p += jpg_start; + sw_sdcard_mode(); + fd = open(argv[1], O_WRONLY | O_CREAT); + if (fd < 0) + { + rt_kprintf("open file for recording failed!\n"); + result = -RT_ERROR; + goto _exit; + } + else + { + write(fd, p, jpg_len); + close(fd); + rt_kprintf("%s picture capture complate!\n", argv[1]); + break; + } + } + else + { + rt_kprintf("jpg_len error!\n"); + result = -RT_ERROR; + goto _exit; + } + } + +_exit: + return result;; +} +MSH_CMD_EXPORT(camera_sample, record picture to a jpg file); + +#endif diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h new file mode 100644 index 0000000000..4ff948b0c6 --- /dev/null +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h @@ -0,0 +1,778 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu first version + */ + +#ifndef __DRV_OV2640_H__ +#define __DRV_OV2640_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <board.h> + +#define OV2640_MID 0X7FA2 +#define OV2640_PID 0X2642 + + +//褰撻�夋嫨DSP鍦板潃(0XFF=0X00)鏃�,OV2640鐨凞SP瀵勫瓨鍣ㄥ湴鍧�鏄犲皠琛� +#define OV2640_DSP_R_BYPASS 0x05 +#define OV2640_DSP_Qs 0x44 +#define OV2640_DSP_CTRL 0x50 +#define OV2640_DSP_HSIZE1 0x51 +#define OV2640_DSP_VSIZE1 0x52 +#define OV2640_DSP_XOFFL 0x53 +#define OV2640_DSP_YOFFL 0x54 +#define OV2640_DSP_VHYX 0x55 +#define OV2640_DSP_DPRP 0x56 +#define OV2640_DSP_TEST 0x57 +#define OV2640_DSP_ZMOW 0x5A +#define OV2640_DSP_ZMOH 0x5B +#define OV2640_DSP_ZMHH 0x5C +#define OV2640_DSP_BPADDR 0x7C +#define OV2640_DSP_BPDATA 0x7D +#define OV2640_DSP_CTRL2 0x86 +#define OV2640_DSP_CTRL3 0x87 +#define OV2640_DSP_SIZEL 0x8C +#define OV2640_DSP_HSIZE2 0xC0 +#define OV2640_DSP_VSIZE2 0xC1 +#define OV2640_DSP_CTRL0 0xC2 +#define OV2640_DSP_CTRL1 0xC3 +#define OV2640_DSP_R_DVP_SP 0xD3 +#define OV2640_DSP_IMAGE_MODE 0xDA +#define OV2640_DSP_RESET 0xE0 +#define OV2640_DSP_MS_SP 0xF0 +#define OV2640_DSP_SS_ID 0x7F +#define OV2640_DSP_SS_CTRL 0xF8 +#define OV2640_DSP_MC_BIST 0xF9 +#define OV2640_DSP_MC_AL 0xFA +#define OV2640_DSP_MC_AH 0xFB +#define OV2640_DSP_MC_D 0xFC +#define OV2640_DSP_P_STATUS 0xFE +#define OV2640_DSP_RA_DLMT 0xFF + +//褰撻�夋嫨浼犳劅鍣ㄥ湴鍧�(0XFF=0X01)鏃�,OV2640鐨凞SP瀵勫瓨鍣ㄥ湴鍧�鏄犲皠琛� +#define OV2640_SENSOR_GAIN 0x00 +#define OV2640_SENSOR_COM1 0x03 +#define OV2640_SENSOR_REG04 0x04 +#define OV2640_SENSOR_REG08 0x08 +#define OV2640_SENSOR_COM2 0x09 +#define OV2640_SENSOR_PIDH 0x0A +#define OV2640_SENSOR_PIDL 0x0B +#define OV2640_SENSOR_COM3 0x0C +#define OV2640_SENSOR_COM4 0x0D +#define OV2640_SENSOR_AEC 0x10 +#define OV2640_SENSOR_CLKRC 0x11 +#define OV2640_SENSOR_COM7 0x12 +#define OV2640_SENSOR_COM8 0x13 +#define OV2640_SENSOR_COM9 0x14 +#define OV2640_SENSOR_COM10 0x15 +#define OV2640_SENSOR_HREFST 0x17 +#define OV2640_SENSOR_HREFEND 0x18 +#define OV2640_SENSOR_VSTART 0x19 +#define OV2640_SENSOR_VEND 0x1A +#define OV2640_SENSOR_MIDH 0x1C +#define OV2640_SENSOR_MIDL 0x1D +#define OV2640_SENSOR_AEW 0x24 +#define OV2640_SENSOR_AEB 0x25 +#define OV2640_SENSOR_W 0x26 +#define OV2640_SENSOR_REG2A 0x2A +#define OV2640_SENSOR_FRARL 0x2B +#define OV2640_SENSOR_ADDVSL 0x2D +#define OV2640_SENSOR_ADDVHS 0x2E +#define OV2640_SENSOR_YAVG 0x2F +#define OV2640_SENSOR_REG32 0x32 +#define OV2640_SENSOR_ARCOM2 0x34 +#define OV2640_SENSOR_REG45 0x45 +#define OV2640_SENSOR_FLL 0x46 +#define OV2640_SENSOR_FLH 0x47 +#define OV2640_SENSOR_COM19 0x48 +#define OV2640_SENSOR_ZOOMS 0x49 +#define OV2640_SENSOR_COM22 0x4B +#define OV2640_SENSOR_COM25 0x4E +#define OV2640_SENSOR_BD50 0x4F +#define OV2640_SENSOR_BD60 0x50 +#define OV2640_SENSOR_REG5D 0x5D +#define OV2640_SENSOR_REG5E 0x5E +#define OV2640_SENSOR_REG5F 0x5F +#define OV2640_SENSOR_REG60 0x60 +#define OV2640_SENSOR_HISTO_LOW 0x61 +#define OV2640_SENSOR_HISTO_HIGH 0x62 + +/* Automatic exposure setting parameters table, support 5 levels */ +const rt_uint8_t OV2640_AUTOEXPOSURE_LEVEL[5][8]= +{ + { + 0xFF,0x01, + 0x24,0x20, + 0x25,0x18, + 0x26,0x60, + }, + { + 0xFF,0x01, + 0x24,0x34, + 0x25,0x1c, + 0x26,0x00, + }, + { + 0xFF,0x01, + 0x24,0x3e, + 0x25,0x38, + 0x26,0x81, + }, + { + 0xFF,0x01, + 0x24,0x48, + 0x25,0x40, + 0x26,0x81, + }, + { + 0xFF,0x01, + 0x24,0x58, + 0x25,0x50, + 0x26,0x92, + }, +}; + +const rt_uint8_t ov2640_sxga_init_reg_tbl[][2]= +{ + {0xff, 0x00}, + {0x2c, 0xff}, + {0x2e, 0xdf}, + {0xff, 0x01}, + {0x3c, 0x32}, + {0x11, 0x00}, + {0x09, 0x02}, + {0x04, 0xD8}, + {0x13, 0xe5}, + {0x14, 0x48}, + {0x2c, 0x0c}, + {0x33, 0x78}, + {0x3a, 0x33}, + {0x3b, 0xfB}, + {0x3e, 0x00}, + {0x43, 0x11}, + {0x16, 0x10}, + {0x39, 0x92}, + {0x35, 0xda}, + {0x22, 0x1a}, + {0x37, 0xc3}, + {0x23, 0x00}, + {0x34, 0xc0}, + {0x36, 0x1a}, + {0x06, 0x88}, + {0x07, 0xc0}, + {0x0d, 0x87}, + {0x0e, 0x41}, + {0x4c, 0x00}, + {0x48, 0x00}, + {0x5B, 0x00}, + {0x42, 0x03}, + {0x4a, 0x81}, + {0x21, 0x99}, + {0x24, 0x40}, + {0x25, 0x38}, + {0x26, 0x82}, + {0x5c, 0x00}, + {0x63, 0x00}, + {0x46, 0x00}, + {0x0c, 0x3c}, + {0x61, 0x70}, + {0x62, 0x80}, + {0x7c, 0x05}, + {0x20, 0x80}, + {0x28, 0x30}, + {0x6c, 0x00}, + {0x6d, 0x80}, + {0x6e, 0x00}, + {0x70, 0x02}, + {0x71, 0x94}, + {0x73, 0xc1}, + {0x3d, 0x34}, + {0x5a, 0x57}, + {0x12, 0x00}, + {0x17, 0x11}, + {0x18, 0x75}, + {0x19, 0x01}, + {0x1a, 0x97}, + {0x32, 0x36}, + {0x03, 0x0f}, + {0x37, 0x40}, + {0x4f, 0xca}, + {0x50, 0xa8}, + {0x5a, 0x23}, + {0x6d, 0x00}, + {0x6d, 0x38}, + {0xff, 0x00}, + {0xe5, 0x7f}, + {0xf9, 0xc0}, + {0x41, 0x24}, + {0xe0, 0x14}, + {0x76, 0xff}, + {0x33, 0xa0}, + {0x42, 0x20}, + {0x43, 0x18}, + {0x4c, 0x00}, + {0x87, 0xd5}, + {0x88, 0x3f}, + {0xd7, 0x03}, + {0xd9, 0x10}, + {0xd3, 0x82}, + {0xc8, 0x08}, + {0xc9, 0x80}, + {0x7c, 0x00}, + {0x7d, 0x00}, + {0x7c, 0x03}, + {0x7d, 0x48}, + {0x7d, 0x48}, + {0x7c, 0x08}, + {0x7d, 0x20}, + {0x7d, 0x10}, + {0x7d, 0x0e}, + {0x90, 0x00}, + {0x91, 0x0e}, + {0x91, 0x1a}, + {0x91, 0x31}, + {0x91, 0x5a}, + {0x91, 0x69}, + {0x91, 0x75}, + {0x91, 0x7e}, + {0x91, 0x88}, + {0x91, 0x8f}, + {0x91, 0x96}, + {0x91, 0xa3}, + {0x91, 0xaf}, + {0x91, 0xc4}, + {0x91, 0xd7}, + {0x91, 0xe8}, + {0x91, 0x20}, + {0x92, 0x00}, + {0x93, 0x06}, + {0x93, 0xe3}, + {0x93, 0x05}, + {0x93, 0x05}, + {0x93, 0x00}, + {0x93, 0x04}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x96, 0x00}, + {0x97, 0x08}, + {0x97, 0x19}, + {0x97, 0x02}, + {0x97, 0x0c}, + {0x97, 0x24}, + {0x97, 0x30}, + {0x97, 0x28}, + {0x97, 0x26}, + {0x97, 0x02}, + {0x97, 0x98}, + {0x97, 0x80}, + {0x97, 0x00}, + {0x97, 0x00}, + {0xc3, 0xef}, + {0xa4, 0x00}, + {0xa8, 0x00}, + {0xc5, 0x11}, + {0xc6, 0x51}, + {0xbf, 0x80}, + {0xc7, 0x10}, + {0xb6, 0x66}, + {0xb8, 0xA5}, + {0xb7, 0x64}, + {0xb9, 0x7C}, + {0xb3, 0xaf}, + {0xb4, 0x97}, + {0xb5, 0xFF}, + {0xb0, 0xC5}, + {0xb1, 0x94}, + {0xb2, 0x0f}, + {0xc4, 0x5c}, + {0xc0, 0xc8}, + {0xc1, 0x96}, + {0x8c, 0x00}, + {0x86, 0x3d}, + {0x50, 0x00}, + {0x51, 0x90}, + {0x52, 0x2c}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x88}, + {0x5a, 0x90}, + {0x5b, 0x2C}, + {0x5c, 0x05}, + {0xd3, 0x02}, + {0xc3, 0xed}, + {0x7f, 0x00}, + {0xda, 0x09}, + {0xe5, 0x1f}, + {0xe1, 0x67}, + {0xe0, 0x00}, + {0xdd, 0x7f}, + {0x05, 0x00}, +}; + +/* SVGA 800*600 */ +const rt_uint8_t ov2640_svga_init_reg_tbl[][2]= +{ + {0xff, 0x00}, + {0x2c, 0xff}, + {0x2e, 0xdf}, + {0xff, 0x01}, + {0x3c, 0x32}, + {0x11, 0x00}, + {0x09, 0x02}, + {0x04, 0xD8}, + {0x13, 0xe5}, + {0x14, 0x48}, + {0x2c, 0x0c}, + {0x33, 0x78}, + {0x3a, 0x33}, + {0x3b, 0xfB}, + {0x3e, 0x00}, + {0x43, 0x11}, + {0x16, 0x10}, + {0x39, 0x92}, + {0x35, 0xda}, + {0x22, 0x1a}, + {0x37, 0xc3}, + {0x23, 0x00}, + {0x34, 0xc0}, + {0x36, 0x1a}, + {0x06, 0x88}, + {0x07, 0xc0}, + {0x0d, 0x87}, + {0x0e, 0x41}, + {0x4c, 0x00}, + {0x48, 0x00}, + {0x5B, 0x00}, + {0x42, 0x03}, + {0x4a, 0x81}, + {0x21, 0x99}, + {0x24, 0x40}, + {0x25, 0x38}, + {0x26, 0x82}, + {0x5c, 0x00}, + {0x63, 0x00}, + {0x46, 0x22}, + {0x0c, 0x3c}, + {0x61, 0x70}, + {0x62, 0x80}, + {0x7c, 0x05}, + {0x20, 0x80}, + {0x28, 0x30}, + {0x6c, 0x00}, + {0x6d, 0x80}, + {0x6e, 0x00}, + {0x70, 0x02}, + {0x71, 0x94}, + {0x73, 0xc1}, + {0x3d, 0x34}, + {0x5a, 0x57}, + {0x12, 0x40}, + {0x17, 0x11}, + {0x18, 0x43}, + {0x19, 0x00}, + {0x1a, 0x4b}, + {0x32, 0x09}, + {0x37, 0xc0}, + {0x4f, 0xca}, + {0x50, 0xa8}, + {0x5a, 0x23}, + {0x6d, 0x00}, + {0x3d, 0x38}, + {0xff, 0x00}, + {0xe5, 0x7f}, + {0xf9, 0xc0}, + {0x41, 0x24}, + {0xe0, 0x14}, + {0x76, 0xff}, + {0x33, 0xa0}, + {0x42, 0x20}, + {0x43, 0x18}, + {0x4c, 0x00}, + {0x87, 0xd5}, + {0x88, 0x3f}, + {0xd7, 0x03}, + {0xd9, 0x10}, + {0xd3, 0x82}, + {0xc8, 0x08}, + {0xc9, 0x80}, + {0x7c, 0x00}, + {0x7d, 0x00}, + {0x7c, 0x03}, + {0x7d, 0x48}, + {0x7d, 0x48}, + {0x7c, 0x08}, + {0x7d, 0x20}, + {0x7d, 0x10}, + {0x7d, 0x0e}, + {0x90, 0x00}, + {0x91, 0x0e}, + {0x91, 0x1a}, + {0x91, 0x31}, + {0x91, 0x5a}, + {0x91, 0x69}, + {0x91, 0x75}, + {0x91, 0x7e}, + {0x91, 0x88}, + {0x91, 0x8f}, + {0x91, 0x96}, + {0x91, 0xa3}, + {0x91, 0xaf}, + {0x91, 0xc4}, + {0x91, 0xd7}, + {0x91, 0xe8}, + {0x91, 0x20}, + {0x92, 0x00}, + {0x93, 0x06}, + {0x93, 0xe3}, + {0x93, 0x05}, + {0x93, 0x05}, + {0x93, 0x00}, + {0x93, 0x04}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x96, 0x00}, + {0x97, 0x08}, + {0x97, 0x19}, + {0x97, 0x02}, + {0x97, 0x0c}, + {0x97, 0x24}, + {0x97, 0x30}, + {0x97, 0x28}, + {0x97, 0x26}, + {0x97, 0x02}, + {0x97, 0x98}, + {0x97, 0x80}, + {0x97, 0x00}, + {0x97, 0x00}, + {0xc3, 0xed}, + {0xa4, 0x00}, + {0xa8, 0x00}, + {0xc5, 0x11}, + {0xc6, 0x51}, + {0xbf, 0x80}, + {0xc7, 0x10}, + {0xb6, 0x66}, + {0xb8, 0xA5}, + {0xb7, 0x64}, + {0xb9, 0x7C}, + {0xb3, 0xaf}, + {0xb4, 0x97}, + {0xb5, 0xFF}, + {0xb0, 0xC5}, + {0xb1, 0x94}, + {0xb2, 0x0f}, + {0xc4, 0x5c}, + {0xc0, 0x64}, + {0xc1, 0x4B}, + {0x8c, 0x00}, + {0x86, 0x3D}, + {0x50, 0x00}, + {0x51, 0xC8}, + {0x52, 0x96}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x00}, + {0x5a, 0xC8}, + {0x5b, 0x96}, + {0x5c, 0x00}, + {0xd3, 0x02}, + {0xc3, 0xed}, + {0x7f, 0x00}, + {0xda, 0x09}, + {0xe5, 0x1f}, + {0xe1, 0x67}, + {0xe0, 0x00}, + {0xdd, 0x7f}, + {0x05, 0x00}, +}; + +/* Initialization sequence for QVGA resolution (320x240) */ +const unsigned char OV2640_QVGA[][2]= +{ + {0xff, 0x00}, + {0x2c, 0xff}, + {0x2e, 0xdf}, + {0xff, 0x01}, + {0x3c, 0x32}, + {0x11, 0x00}, + {0x09, 0x02}, + {0x04, 0xA8}, + {0x13, 0xe5}, + {0x14, 0x48}, + {0x2c, 0x0c}, + {0x33, 0x78}, + {0x3a, 0x33}, + {0x3b, 0xfB}, + {0x3e, 0x00}, + {0x43, 0x11}, + {0x16, 0x10}, + {0x4a, 0x81}, + {0x21, 0x99}, + {0x24, 0x40}, + {0x25, 0x38}, + {0x26, 0x82}, + {0x5c, 0x00}, + {0x63, 0x00}, + {0x46, 0x3f}, + {0x0c, 0x3c}, + {0x61, 0x70}, + {0x62, 0x80}, + {0x7c, 0x05}, + {0x20, 0x80}, + {0x28, 0x30}, + {0x6c, 0x00}, + {0x6d, 0x80}, + {0x6e, 0x00}, + {0x70, 0x02}, + {0x71, 0x94}, + {0x73, 0xc1}, + {0x3d, 0x34}, + {0x5a, 0x57}, + {0x12, 0x00}, + {0x11, 0x00}, + {0x17, 0x11}, + {0x18, 0x75}, + {0x19, 0x01}, + {0x1a, 0x97}, + {0x32, 0x36}, + {0x03, 0x0f}, + {0x37, 0x40}, + {0x4f, 0xbb}, + {0x50, 0x9c}, + {0x5a, 0x57}, + {0x6d, 0x80}, + {0x6d, 0x38}, + {0x39, 0x02}, + {0x35, 0x88}, + {0x22, 0x0a}, + {0x37, 0x40}, + {0x23, 0x00}, + {0x34, 0xa0}, + {0x36, 0x1a}, + {0x06, 0x02}, + {0x07, 0xc0}, + {0x0d, 0xb7}, + {0x0e, 0x01}, + {0x4c, 0x00}, + {0xff, 0x00}, + {0xe5, 0x7f}, + {0xf9, 0xc0}, + {0x41, 0x24}, + {0xe0, 0x14}, + {0x76, 0xff}, + {0x33, 0xa0}, + {0x42, 0x20}, + {0x43, 0x18}, + {0x4c, 0x00}, + {0x87, 0xd0}, + {0x88, 0x3f}, + {0xd7, 0x03}, + {0xd9, 0x10}, + {0xd3, 0x82}, + {0xc8, 0x08}, + {0xc9, 0x80}, + {0x7d, 0x00}, + {0x7c, 0x03}, + {0x7d, 0x48}, + {0x7c, 0x08}, + {0x7d, 0x20}, + {0x7d, 0x10}, + {0x7d, 0x0e}, + {0x90, 0x00}, + {0x91, 0x0e}, + {0x91, 0x1a}, + {0x91, 0x31}, + {0x91, 0x5a}, + {0x91, 0x69}, + {0x91, 0x75}, + {0x91, 0x7e}, + {0x91, 0x88}, + {0x91, 0x8f}, + {0x91, 0x96}, + {0x91, 0xa3}, + {0x91, 0xaf}, + {0x91, 0xc4}, + {0x91, 0xd7}, + {0x91, 0xe8}, + {0x91, 0x20}, + {0x92, 0x00}, + {0x93, 0x06}, + {0x93, 0xe3}, + {0x93, 0x02}, + {0x93, 0x02}, + {0x93, 0x00}, + {0x93, 0x04}, + {0x93, 0x00}, + {0x93, 0x03}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x93, 0x00}, + {0x96, 0x00}, + {0x97, 0x08}, + {0x97, 0x19}, + {0x97, 0x02}, + {0x97, 0x0c}, + {0x97, 0x24}, + {0x97, 0x30}, + {0x97, 0x28}, + {0x97, 0x26}, + {0x97, 0x02}, + {0x97, 0x98}, + {0x97, 0x80}, + {0x97, 0x00}, + {0x97, 0x00}, + {0xc3, 0xef}, + {0xff, 0x00}, + {0xba, 0xdc}, + {0xbb, 0x08}, + {0xb6, 0x24}, + {0xb8, 0x33}, + {0xb7, 0x20}, + {0xb9, 0x30}, + {0xb3, 0xb4}, + {0xb4, 0xca}, + {0xb5, 0x43}, + {0xb0, 0x5c}, + {0xb1, 0x4f}, + {0xb2, 0x06}, + {0xc7, 0x00}, + {0xc6, 0x51}, + {0xc5, 0x11}, + {0xc4, 0x9c}, + {0xbf, 0x00}, + {0xbc, 0x64}, + {0xa6, 0x00}, + {0xa7, 0x1e}, + {0xa7, 0x6b}, + {0xa7, 0x47}, + {0xa7, 0x33}, + {0xa7, 0x00}, + {0xa7, 0x23}, + {0xa7, 0x2e}, + {0xa7, 0x85}, + {0xa7, 0x42}, + {0xa7, 0x33}, + {0xa7, 0x00}, + {0xa7, 0x23}, + {0xa7, 0x1b}, + {0xa7, 0x74}, + {0xa7, 0x42}, + {0xa7, 0x33}, + {0xa7, 0x00}, + {0xa7, 0x23}, + {0xc0, 0xc8}, + {0xc1, 0x96}, + {0x8c, 0x00}, + {0x86, 0x3d}, + {0x50, 0x92}, + {0x51, 0x90}, + {0x52, 0x2c}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x88}, + {0x5a, 0x50}, + {0x5b, 0x3c}, + {0x5c, 0x00}, + {0xd3, 0x04}, + {0x7f, 0x00}, + {0xda, 0x00}, + {0xe5, 0x1f}, + {0xe1, 0x67}, + {0xe0, 0x00}, + {0xdd, 0x7f}, + {0x05, 0x00}, + {0xff, 0x00}, + {0xe0, 0x04}, + {0xc0, 0xc8}, + {0xc1, 0x96}, + {0x86, 0x3d}, + {0x50, 0x92}, + {0x51, 0x90}, + {0x52, 0x2c}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x88}, + {0x57, 0x00}, + {0x5a, 0x50}, + {0x5b, 0x3C}, + {0x5c, 0x00}, + {0xd3, 0x08}, + {0xe0, 0x00}, + {0xFF, 0x00}, + {0x05, 0x00}, + {0xDA, 0x08}, + {0xda, 0x09}, + {0x98, 0x00}, + {0x99, 0x00}, + {0x00, 0x00}, +}; + +const rt_uint8_t ov2640_jpeg_reg_tbl[][2]= +{ + {0xff, 0x01}, + {0xe0, 0x14}, + {0xe1, 0x77}, + {0xe5, 0x1f}, + {0xd7, 0x03}, + {0xda, 0x10}, + {0xe0, 0x00}, +}; + +const rt_uint8_t ov2640_rgb565_reg_tbl[][2]= +{ + {0xFF, 0x00}, + {0xDA, 0x09}, + {0xD7, 0x03}, + {0xDF, 0x02}, + {0x33, 0xa0}, + {0x3C, 0x00}, + {0xe1, 0x67}, + + {0xff, 0x01}, + {0xe0, 0x00}, + {0xe1, 0x00}, + {0xe5, 0x00}, + {0xd7, 0x00}, + {0xda, 0x00}, + {0xe0, 0x00}, +}; +const rt_uint8_t ov2640_yuv422_reg_tbl[][2] = +{ + {0xFF, 0x00}, + {0xDA, 0x10}, + {0xD7, 0x03}, + {0xDF, 0x00}, + {0x33, 0x80}, + {0x3C, 0x40}, + {0xe1, 0x77}, + {0x00, 0x00}, +}; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32h743-st-nucleo/README.md b/bsp/stm32/stm32h743-st-nucleo/README.md index 68ce1a722e..ee2ffa2135 100644 --- a/bsp/stm32/stm32h743-st-nucleo/README.md +++ b/bsp/stm32/stm32h743-st-nucleo/README.md @@ -1,109 +1,115 @@ -# STM32H743-st-nucleo 开发板 BSP 说明 +# STM32H743-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 tyustli 为 STM32H743-st-nucleo 开发板提供的 BSP (板级支持包) 说明。 +## MCU: STM32H743ZI @480MHz, 2MB FLASH, 1MB RAM -主要内容如下： +STM32H742xI/G and STM32H743xI/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H742xI/G and STM32H743xI/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +STM32H742xI/G and STM32H743xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Core + - 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Memories + - Up to 2 Mbytes of Flash memory with read-while-write support + - Up to 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Up to 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain + - Dual mode Quad-SPI memory interface running up to 133 MHz + - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 100 MHz in Synchronous mode + - CRC calculation unit +- Security + - ROP, PC-ROP, active tamper +- General-purpose input/outputs + - Up to 168 I/O ports with interrupt capability +- Reset and power management + - 3 separate power domains which can be independently clock-gated or switched off: + - D1: high-performance capabilities + - D2: communication peripherals and timers + - D3: reset/clock control/power management + - 1.62 to 3.6 V application supply and I/Os + - POR, PDR, PVD and BOR + - Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs + - Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry + - Voltage scaling in Run and Stop mode (6 configurable ranges) + - Backup regulator (~0.9 V) + - Voltage reference for analog peripheral/VREF+ + - Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging +- Low-power consumption + - VBAT battery operating mode with charging capability + - CPU and domain power state monitoring pins + - 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON) +- Clock management + - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI + - External oscillators: 4-48 MHz HSE, 32.768 kHz LSE + - 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode +- Interconnect matrix -STM32H743 是 ST 推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 400Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32H743 的芯片性能。 +- 4 DMA controllers to unload the CPU + - 1× high-speed master direct memory access controller (MDMA) with linked list support + - 2× dual-port DMAs with FIFO + - 1× basic DMA with request router capabilities +- Up to 35 communication peripherals + - 4× I2Cs FM+ interfaces (SMBus/PMBus) + - 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART + - 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz) + - 4x SAIs (serial audio interface) + - SPDIFRX interface + - SWPMI single-wire protocol master I/F + - MDIO Slave interface + - 2× SD/SDIO/MMC interfaces (up to 125 MHz) + - 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) + - 2× USB OTG interfaces (1FS, 1HS/FS) crystal-less solution with LPM and BCD + - Ethernet MAC interface with DMA controller + - HDMI-CEC + - 8- to 14-bit camera interface (up to 80 MHz) +- 11 analog peripherals + - 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) + - 1× temperature sensor + - 2× 12-bit D/A converters (1 MHz) + - 2× ultra-low-power comparators + - 2× operational amplifiers (7.3 MHz bandwidth) + - 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters +- Graphics + - LCD-TFT controller up to XGA resolution + - Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load + - Hardware JPEG Codec +- Up to 22 timers and watchdogs + - 1× high-resolution timer (2.1 ns max resolution) + - 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz) + - 2× 16-bit advanced motor control timers (up to 240 MHz) + - 10× 16-bit general-purpose timers (up to 240 MHz) + - 5× 16-bit low-power timers (up to 240 MHz) + - 2× watchdogs (independent and window) + - 1× SysTick timer + - RTC with sub-second accuracy and hardware calendar +- Debug mode + - SWD & JTAG interfaces + - 4-Kbyte Embedded Trace Buffer +- True random number generators (3 oscillators each) +- 96-bit unique ID -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32H743，主频 400MHz，2MB FLASH ，1MB RAM -- 常用接口：USB 转串口、以太网接口、arduino 接口等 -- 调试接口，标准 JTAG/SWD +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) | +| [STM32H743ZI ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32h743zi.html#documentation) | STM32H743ZI datasheet and other resources | -开发板更多详细信息请参考 ST [STM32H743](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| USB 转串口 | 支持 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | | -| UART | 支持 | UART3 | +[tyustli](https://github.com/tyustli) -## 使用说明 -使用说明分为如下两个章节： +## Translated By -- 快速上手 +Meco Man @ RT-Thread Community - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，LED闪烁。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.1 build Mar 5 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 调试串口为串口3 映射说明 - - PD8 ------> USART3_TX - - PD9 ------> USART3_RX - -## 联系人信息 - -维护人: - -- [tyustli](https://github.com/tyustli)
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32h743-st-nucleo/README_zh.md b/bsp/stm32/stm32h743-st-nucleo/README_zh.md new file mode 100644 index 0000000000..68ce1a722e --- /dev/null +++ b/bsp/stm32/stm32h743-st-nucleo/README_zh.md @@ -0,0 +1,109 @@ +# STM32H743-st-nucleo 开发板 BSP 说明 + +## 简介 + +本文档为 tyustli 为 STM32H743-st-nucleo 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +STM32H743 是 ST 推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 400Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32H743 的芯片性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32H743，主频 400MHz，2MB FLASH ，1MB RAM +- 常用接口：USB 转串口、以太网接口、arduino 接口等 +- 调试接口，标准 JTAG/SWD + +开发板更多详细信息请参考 ST [STM32H743](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART3 | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.1 build Mar 5 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 调试串口为串口3 映射说明 + + PD8 ------> USART3_TX + + PD9 ------> USART3_RX + +## 联系人信息 + +维护人: + +- [tyustli](https://github.com/tyustli)
\ No newline at end of file diff --git a/bsp/stm32/stm32l010-st-nucleo/README.md b/bsp/stm32/stm32l010-st-nucleo/README.md index c69bbe14fa..aee1a5879b 100644 --- a/bsp/stm32/stm32l010-st-nucleo/README.md +++ b/bsp/stm32/stm32l010-st-nucleo/README.md @@ -1,120 +1,77 @@ +# STM32L010-Nucleo BSP Introduction -# NUCLEO-L010RB 开发板 BSP 说明 +[中文](README_zh.md) -## 简介 +## MCU: STM32L010RB @32MHz, 128KB FLASH, 20KB RAM -本文档为ST官方 NUCLEO-L010RB 开发板的 BSP (板级支持包) 说明。 +#### KEY FEATURES -主要内容如下： +- Ultra-low-power platform + - 1.8 V to 3.6 V power supply + - –40 to 85 °C temperature range + - 0.29 µA Standby mode (2 wakeup pins) + - 0.43 µA Stop mode (16 wakeup lines) + - 0.86 µA Stop mode + RTC + 20-Kbyte RAM retention + - Down to 93 µA/MHz in Run mode + - 5 µs wakeup time (from Flash memory) + - 41 µA 12-bit ADC conversion at 10 ksps +- Core: Arm® 32-bit Cortex®-M0+ + - From 32 kHz to 32 MHz + - 0.95 DMIPS/MHz +- Reset and supply management + - Ultra-low-power BOR (brownout reset) with 5 selectable thresholds + - Ultra-low-power POR/PDR +- Clock sources + - 0 to 32 MHz external clock + - 32 kHz oscillator for RTC with calibration + - High-speed internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 37 kHz RC + - Internal multispeed low-power 65 kHz to 4.2 MHz RC + - PLL for CPU clock +- Pre-programmed bootloader + - USART, I2C, SPI supported +- Development support + - Serial wire debug supported +- 51 fast I/Os (45 I/Os 5-Volt tolerant) +- Memories + - 128-Kbyte Flash memory + - 20-Kbyte RAM + - 512 bytes of data EEPROM + - 20-byte backup register + - Sector protection against R/W operation +- Analog peripherals + - 12-bit ADC 1.14 Msps up to 16 channels (down to 1.8 V) -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +- 7-channel DMA controller, supporting ADC, SPI, I2C, USART and timers +- 4x peripherals communication interface +- 1x USART (ISO7816), 1x LPUART (low power) +- 1x SPI 16 Mbit/s +- 1x I2C (SMBus/PMBus) +- 8x timers: 1x 16-bit with up to 4 channels, 2x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x SysTick, 1x RTC and 2x watchdogs (independent/window) +- CRC calculation unit, 96-bit unique ID +- LFQFP64 package is ECOPACK2 compliant -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 -## 开发板介绍 -NUCLEO-L010RB 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，该开发板具有丰富的扩展接口，且与Arduino™ nano 接口兼容，可以方便验证 STM32L010RB 芯片的性能。 +## Read more -开发板外观如下图所示： +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32L010RB ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32l010rb.html#documentation) | STM32L010RB datasheet and other resources | - -该开发板常用 **板载资源** 如下： -- MCU：STM32L010RB - - 主频 32MHz - - 128KB FLASH - - 20KB RAM - - 512 byte EEPROM -- 常用外设 - - LED：3个，USB communication(LD1 双色)，power LED(LD3 红色)，user LED(LD2 黄色) - - 按键：1个，B1（兼具唤醒功能，PC13），B2（RESET） -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口；arduino 接口等 -- 调试接口：标准 SWD +## Maintained By -开发板更多详细信息请参考[STMicroelectronics NUCLEO-L010RB](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l010rb.html#overview)。 + [xph](https://github.com/xupenghu), <[email protected]> -## 外设支持 -本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| 板载 ST-LINK 转串口 | 支持 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | -| UART | 支持 | UART2 | -| SPI | 暂不支持 | | -| I2C | 暂不支持 | | -| RTC | 暂不支持 | | -| PWM | 暂不支持 | | -| USB Device | 暂不支持 | | -| IWG | 暂不支持 | | -| **扩展模块** | **支持情况** | **备注** | +## Translated By -## 使用说明 +Meco Man @ RT-Thread Community -使用说明分为如下两个章节： - -- 快速上手 - - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LED1 和 LED3 常亮、黄色 LED2 会周期性闪烁。 - -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.3 build Apr 9 2020 - 2006 - 2020 Copyright by rt-thread team -msh > - -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口 2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 -- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 - -## 联系人信息 - -- 维护人: [xph](https://github.com/xupenghu) -- 邮箱：<[email protected]> +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32l010-st-nucleo/README_zh.md b/bsp/stm32/stm32l010-st-nucleo/README_zh.md new file mode 100644 index 0000000000..c69bbe14fa --- /dev/null +++ b/bsp/stm32/stm32l010-st-nucleo/README_zh.md @@ -0,0 +1,120 @@ + +# NUCLEO-L010RB 开发板 BSP 说明 + +## 简介 + +本文档为ST官方 NUCLEO-L010RB 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-L010RB 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，该开发板具有丰富的扩展接口，且与Arduino™ nano 接口兼容，可以方便验证 STM32L010RB 芯片的性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L010RB + - 主频 32MHz + - 128KB FLASH + - 20KB RAM + - 512 byte EEPROM +- 常用外设 + - LED：3个，USB communication(LD1 双色)，power LED(LD3 红色)，user LED(LD2 黄色) + - 按键：1个，B1（兼具唤醒功能，PC13），B2（RESET） +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口；arduino 接口等 +- 调试接口：标准 SWD + +开发板更多详细信息请参考[STMicroelectronics NUCLEO-L010RB](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l010rb.html#overview)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| 板载 ST-LINK 转串口 | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | UART2 | +| SPI | 暂不支持 | | +| I2C | 暂不支持 | | +| RTC | 暂不支持 | | +| PWM | 暂不支持 | | +| USB Device | 暂不支持 | | +| IWG | 暂不支持 | | +| **扩展模块** | **支持情况** | **备注** | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LED1 和 LED3 常亮、黄色 LED2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Apr 9 2020 + 2006 - 2020 Copyright by rt-thread team +msh > + +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 + +## 联系人信息 + +- 维护人: [xph](https://github.com/xupenghu) +- 邮箱：<[email protected]> diff --git a/bsp/stm32/stm32l053-st-nucleo/README.md b/bsp/stm32/stm32l053-st-nucleo/README.md index 35799d2715..424ec19c46 100644 --- a/bsp/stm32/stm32l053-st-nucleo/README.md +++ b/bsp/stm32/stm32l053-st-nucleo/README.md @@ -1,115 +1,96 @@ -# NUCLEO-L053R8 开发板 BSP 说明 +# STM32L053-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为ST官方 NUCLEO-L053R8 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32L053R8 @32MHz, 64KB FLASH, 8KB RAM -主要内容如下： +The ultra-low-power STM32L053x6/8 microcontrollers incorporate the connectivity power of the universal serial bus (USB 2.0 crystal-less) with the high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (up to 64 Kbytes of Flash program memory, 2 Kbytes of data EEPROM and 8 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32L053x6/8 devices provide high power efficiency for a wide range of performance. It is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes. +The STM32L053x6/8 devices offer several analog features, one 12-bit ADC with hardware oversampling, one DAC, two ultra-low-power comparators, several timers, one low-power timer (LPTIM), three general-purpose 16-bit timers and one basic timer, one RTC and one SysTick which can be used as timebases. They also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock. +Moreover, the STM32L053x6/8 devices embed standard and advanced communication interfaces: up to two I2C, two SPIs, one I2S, two USARTs, a low-power UART (LPUART), and a crystal-less USB. The devices offer up to 24 capacitive sensing channels to simply add touch sensing functionality to any application. +The STM32L053x6/8 also include a real-time clock and a set of backup registers that remain powered in Standby mode. +Finally, their integrated LCD controller has a built-in LCD voltage generator that allows to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage. +The ultra-low-power STM32L053x6/8 devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Ultra-low-power platform + - 1.65 V to 3.6 V power supply + - -40 to 125 °C temperature range + - 0.27 μA Standby mode (2 wakeup pins) + - 0.4 μA Stop mode (16 wakeup lines) + - 0.8 μA Stop mode + RTC + 8 KB RAM retention + - 88 μA/MHz in Run mode + - 3.5 μs wakeup time (from RAM) + - 5 μs wakeup time (from Flash memory) +- Core: Arm® 32-bit Cortex®-M0+ with MPU + - From 32 kHz up to 32 MHz max. + - 0.95 DMIPS/MHz +- Memories + - Up to 64 KB Flash memory with ECC + - 8KB RAM + - 2 KB of data EEPROM with ECC + - 20-byte backup register + - Sector protection against R/W operation +- Up to 51 fast I/Os (45 I/Os 5V tolerant) +- Reset and supply management + - Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds + - Ultra-low-power POR/PDR + - Programmable voltage detector (PVD) +- Clock sources + - 1 to 25 MHz crystal oscillator + - 32 kHz oscillator for RTC with calibration + - High speed internal 16 MHz factory-trimmed RC (+/- 1%) + - Internal low-power 37 kHz RC + - Internal multispeed low-power 65 kHz to 4.2 MHz RC + - PLL for CPU clock +- Pre-programmed bootloader + - USART, SPI supported +- Development support + - Serial wire debug supported +- LCD driver for up to 8×28segments + - Support contrast adjustment + - Support blinking mode + - Step-up converted on board -NUCLEO-L053R8 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，该开发板具有丰富的扩展接口，且与Arduino™ nano 接口兼容，可以方便验证 STM32L053R8 芯片的性能。 +- Rich Analog peripherals + - 12-bit ADC 1.14 Msps up to 16 channels (down to 1.65 V) + - 12-bit 1 channel DAC with output buffers (down to 1.8 V) + - 2x ultra-low-power comparators (window mode and wake up capability, down to 1.65 V) +- Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors +- 7-channel DMA controller, supporting ADC, SPI, I2C, USART, DAC, Timers +- 8x peripheral communication interfaces + - 1x USB 2.0 crystal-less, battery charging detection and LPM + - 2x USART (ISO 7816, IrDA), 1x UART (low power) + - Up to 4x SPI 16 Mbits/s + - 2x I2C (SMBus/PMBus) +- 9x timers: 1x 16-bit with up to 4 channels, 2x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x SysTick, 1x RTC, 1x 16-bit basic for DAC, and 2x watchdogs (independent/window) +- CRC calculation unit, 96-bit unique ID +- True RNG and firewall protection +- All packages are ECOPACK®2 -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32L053R8，主频 32MHz，64KB FLASH ，8KB RAM -- 常用外设 - - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 黄色) - - 按键：1个，B1（兼具唤醒功能，PC13），B2（RESET） -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口；arduino 接口等 -- 调试接口：标准 SWD +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32L053R8 ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32l053r8.html#documentation) | STM32L053R8 datasheet and other resources | -开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L053R8](https://www.st.com/en/evaluation-tools/nucleo-l053r8.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| 板载 ST-LINK 转串口 | 支持 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | -| UART | 支持 | UART2 | -| SPI | 暂不支持 | SPI1 即将支持 | -| I2C | 暂不支持 | 软件 I2C 即将支持 | -| RTC | 暂不支持 | 即将支持 | -| PWM | 暂不支持 | 即将支持 | -| USB Device | 暂不支持 | 即将支持 | -| IWG | 暂不支持 | 即将支持 | -| **扩展模块** | **支持情况** | **备注** | + [sun_shine](https://github.com/xupenghu), <[email protected]> -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 LD3 常亮、黄色 LD2 会周期性闪烁。 - -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Jan 9 2019 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口 2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 -- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 - -## 联系人信息 - -维护人: - -- [sun_shine](https://github.com/sunshine0824), 邮箱：<[email protected]> +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32l053-st-nucleo/README_zh.md b/bsp/stm32/stm32l053-st-nucleo/README_zh.md new file mode 100644 index 0000000000..35799d2715 --- /dev/null +++ b/bsp/stm32/stm32l053-st-nucleo/README_zh.md @@ -0,0 +1,115 @@ +# NUCLEO-L053R8 开发板 BSP 说明 + +## 简介 + +本文档为ST官方 NUCLEO-L053R8 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-L053R8 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，该开发板具有丰富的扩展接口，且与Arduino™ nano 接口兼容，可以方便验证 STM32L053R8 芯片的性能。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L053R8，主频 32MHz，64KB FLASH ，8KB RAM +- 常用外设 + - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 黄色) + - 按键：1个，B1（兼具唤醒功能，PC13），B2（RESET） +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口；arduino 接口等 +- 调试接口：标准 SWD + +开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L053R8](https://www.st.com/en/evaluation-tools/nucleo-l053r8.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| 板载 ST-LINK 转串口 | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | UART2 | +| SPI | 暂不支持 | SPI1 即将支持 | +| I2C | 暂不支持 | 软件 I2C 即将支持 | +| RTC | 暂不支持 | 即将支持 | +| PWM | 暂不支持 | 即将支持 | +| USB Device | 暂不支持 | 即将支持 | +| IWG | 暂不支持 | 即将支持 | +| **扩展模块** | **支持情况** | **备注** | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 LD3 常亮、黄色 LD2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Jan 9 2019 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 + +## 联系人信息 + +维护人: + +- [sun_shine](https://github.com/sunshine0824), 邮箱：<[email protected]> diff --git a/bsp/stm32/stm32l412-st-nucleo/README.md b/bsp/stm32/stm32l412-st-nucleo/README.md index ce4af7d1f8..1bff7ef7a4 100644 --- a/bsp/stm32/stm32l412-st-nucleo/README.md +++ b/bsp/stm32/stm32l412-st-nucleo/README.md @@ -1,116 +1,99 @@ -# NUCLEO32-L412 开发板 BSP 说明 +# STM32L412-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为ST官方 NUCLEO32-L412 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32L412RB @80MHz, 128KB FLASH, 40KB RAM -主要内容如下： +The STM32L412xx devices are ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32L412xx devices embed high-speed memories (Flash memory up to 128 Kbyte,40 Kbyte of SRAM), a Quad SPI Flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. +The STM32L412xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. +The devices offer two fast 12-bit ADC (5 Msps), two comparators, one operational amplifier, a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers. +In addition, up to 12 capacitive sensing channels are available. +They also feature standard and advanced communication interfaces, namely three I2Cs, two SPIs, three USARTs and one Low-Power UART, one USB full-speed device crystal less. +The STM32L412xx operates in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using internal LDO regulator and a 1.00 to 1.32V VDD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes makes possible the design of low-power applications. +Some independent power supplies are supported: analog independent supply input for ADC, OPAMP and comparator. A VBAT input makes it possible to backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. +The STM32L412xx family offers six packages from 32 to 64-pin packages. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Ultra-low-power with FlexPowerControl + - 1.71 V to 3.6 V power supply + - -40 °C to 85/125 °C temperature range + - 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers + - 16 nA Shutdown mode (4 wakeup pins) + - 32 nA Standby mode (4 wakeup pins) + - 245 nA Standby mode with RTC + - 0.7 µA Stop 2 mode, 0.95 µA with RTC + - 79 µA/MHz run mode (LDO Mode) + - 28 μA/MHz run mode (@3.3 V SMPS Mode) + - Batch acquisition mode (BAM) + - 4 µs wakeup from Stop mode + - Brown out reset (BOR) + - Interconnect matrix +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions +- Performance benchmark + - 1.25 DMIPS/MHz (Drystone 2.1) + - 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz) +- Energy benchmark + - 442 ULPMark-CP® + - 165 ULPMark-PP® +- Clock Sources + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) + - Internal 48 MHz with clock recovery + - PLL for system clock +- Up to 52 fast I/Os, most 5 V-tolerant +- RTC with HW calendar, alarms and calibration +- Up to 12 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 10x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 1x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer -对于 NUCLEO32-L412，内核是 Cortex-M4，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，mirco USB 接口，可数的外设，Arduino™ nano 兼容的接口。 +- Memories + - 128 KB single bank Flash, proprietary code readout protection + - 40 KB of SRAM including 8 KB with hardware parity check + - Quad SPI memory interface with XIP capability +- Rich analog peripherals (independent supply) + - 2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps + - 2x operational amplifiers with built-in PGA + - 1x ultra-low-power comparator + - Accurate 2.5 V or 2.048 V reference voltage buffered output +- 12x communication interfaces + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 3x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 2x SPIs (and 1x Quad SPI) + - IRTIM (Infrared interface) +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ +- All packages are ECOPACK2 compliant -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32L412RBT6P，主频 80MHz，128KB FLASH ，40KB RAM。 -- 常用外设 - - LED：4个，LD1（COM 双色），LD2（5V_USB 红色），LD3（5V_PWR 绿色），LD4（USER 绿色） - - 按键：2个，用户按键（B1），复位按键（B2） -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 -- 调试接口：板载 ST-LINK/V2-1 调试器。 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32L412RB ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32l412rb.html#documentation) | STM32L412RB datasheet and other resources | -开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L412RB-P](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l412rb-p.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| 板载 ST-LINK 转串口 | 支持 | UART2 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | -| UART | 支持 | UART2 | -| SPI | 暂不支持 | SPI1 即将支持 | -| I2C | 暂不支持 | 软件 I2C 即将支持 | -| RTC | 支持 | 支持外部晶振和内部低速时钟 | -| PWM | 暂不支持 | 即将支持 | -| USB Device | 暂不支持 | 即将支持 | -| IWG | 支持 | 独立看门狗，未开启窗口模式 | -| **扩展模块** | **支持情况** | **备注** | +[luhuadong](https://github.com/luhuadong), [email protected] -## 使用说明 -使用说明分为如下两个章节： +## Translated By -- 快速上手 +Meco Man @ RT-Thread Community - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 LD2 常亮、黄色色 LD3 会周期性闪烁。 - -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.3 build Apr 24 2020 - 2006 - 2020 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 -- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 - -## 联系人信息 - -维护人: - -- [luhuadong](https://github.com/luhuadong), 邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32l412-st-nucleo/README_zh.md b/bsp/stm32/stm32l412-st-nucleo/README_zh.md new file mode 100644 index 0000000000..a5480bdf58 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/README_zh.md @@ -0,0 +1,116 @@ +# NUCLEO32-L412 开发板 BSP 说明 + +## 简介 + +本文档为ST官方 NUCLEO32-L412 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +对于 NUCLEO32-L412，内核是 Cortex-M4，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，mirco USB 接口，可数的外设，Arduino™ nano 兼容的接口。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L412RB，主频 80MHz，128KB FLASH ，40KB RAM。 +- 常用外设 + - LED：4个，LD1（COM 双色），LD2（5V_USB 红色），LD3（5V_PWR 绿色），LD4（USER 绿色） + - 按键：2个，用户按键（B1），复位按键（B2） +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 +- 调试接口：板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L412RB-P](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l412rb-p.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| 板载 ST-LINK 转串口 | 支持 | UART2 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | UART2 | +| SPI | 暂不支持 | SPI1 即将支持 | +| I2C | 暂不支持 | 软件 I2C 即将支持 | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| PWM | 暂不支持 | 即将支持 | +| USB Device | 暂不支持 | 即将支持 | +| IWG | 支持 | 独立看门狗，未开启窗口模式 | +| **扩展模块** | **支持情况** | **备注** | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 LD2 常亮、黄色色 LD3 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Apr 24 2020 + 2006 - 2020 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 + +## 联系人信息 + +维护人: + +- [luhuadong](https://github.com/luhuadong), 邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32l433-st-nucleo/README.md b/bsp/stm32/stm32l433-st-nucleo/README.md index 2757522345..2c744c5d47 100644 --- a/bsp/stm32/stm32l433-st-nucleo/README.md +++ b/bsp/stm32/stm32l433-st-nucleo/README.md @@ -1,113 +1,102 @@ -# NUCLEO-L433RC-P 开发板 BSP 说明 +# STM32L433-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为ST官方 NUCLEO-L433RC-P 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32L433RC @80MHz, 256KB FLASH, 64KB RAM -主要内容如下： +The STM32L433xx devices are the ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32L433xx devices embed high-speed memories (Flash memory up to 256 Kbyte, 64 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. +The STM32L433xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. +The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier, two DAC channels, an internal voltage reference buffer, a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers. +In addition, up to 21 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter. +They also feature standard and advanced communication interfaces. +The STM32L433xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V VDD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes allows the design of low-power applications. +Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMP and comparators, and 3.3 V dedicated supply input for USB. A VBAT input allows to backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. +The STM32L433xx family offers eight packages from 48 to 100-pin packages. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Ultra-low-power with FlexPowerControl + - 1.71 V to 3.6 V power supply + - -40 °C to 85/105/125 °C temperature range + - 200 nA in VBAT mode: supply for RTC and 32x32-bit backup registers + - 8 nA Shutdown mode (5 wakeup pins) + - 28 nA Standby mode (5 wakeup pins) + - 280 nA Standby mode with RTC + - 1.0 μA Stop 2 mode, 1.28 μA with RTC + - 84 μA/MHz run mode (LDO Mode) + - 36 μA/MHz run mode (@3.3 V SMPS Mode) + - Batch acquisition mode (BAM) + - 4 μs wakeup from Stop mode + - Brown out reset (BOR) + - Interconnect matrix +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions +- Performance benchmark + - 1.25 DMIPS/MHz (Drystone 2.1) + - 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz) +- Energy benchmark + - 253 ULPBench® score +- Clock Sources + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) + - Internal 48 MHz with clock recovery + - 2 PLLs for system clock, USB, audio, ADC +- Up to 83 fast I/Os, most 5 V-tolerant +- RTC with HW calendar, alarms and calibration +- LCD 8× 40 or 4× 44 with step-up converter +- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors -对于 NUCLEO-L433RC-P，内核是 Cortex-M4，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，mirco USB 接口，可数的外设，Arduino™ nano 兼容的接口。 +- 11x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer +- Memories + - Up to 256 KB single bank Flash, proprietary code readout protection + - 64 KB of SRAM including 16 KB with hardware parity check + - Quad SPI memory interface +- Rich analog peripherals (independent supply) + - 1x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps + - 2x 12-bit DAC output channels, low-power sample and hold + - 1x operational amplifier with built-in PGA + - 2x ultra-low-power comparators +- 17x communication interfaces + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAI (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 3x SPIs (and 1x Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ +- All packages are ECOPACK2® compliant -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32L433RC，主频 80MHz，256KB FLASH ，64KB RAM。 -- 常用外设 - - LED：4个，USB communication(LD1 双色)，USB overcurrent(LD2 红色)，power LED(LD3 绿色)，user LED(LD4 绿色) - - 按键：2 个，USER and RESET 。 -- 常用接口：USB 转串口、Arduino Uno 和 ST morpho 两类扩展接口 -- 调试接口：板载 ST-LINK/V2-1 调试器。 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32L433RC ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32l433rc.html#documentation) | STM32L433RC datasheet and other resources | -快速入门：[STM32 Nucleo板软件开发工具入门](https://www.st.com/resource/zh/user_manual/dm00105928-getting-started-with-stm32-nucleo-board-software-development-tools-stmicroelectronics.pdf) -原理图下载：[NUCLEO-L433RC-P schematic](https://www.st.com/resource/en/schematic_pack/nucleo-l433rc-p_sch.zip) -开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L433RC-P](https://www.st.com/content/st_com/zh/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l433rc-p.html)。 +## Maintained By -## 外设支持 +[Sunwancn](https://github.com/Sunwancn), <[email protected]> -本 BSP 目前对外设的支持情况如下： -| **片上外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------ | -| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | -| UART | 支持 | UART1, UART2 | -| SPI | 支持 | SPI1 | -| RTC | 支持 | 支持外部晶振和内部低速时钟 | +## Translated By -## 使用说明 +Meco Man @ RT-Thread Community -使用说明分为如下两个章节： - -- 快速上手 - - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 绿色 LD3 常亮、绿色 LD4 会周期性闪烁。 - -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Jan 9 2019 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 -- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 - -## 联系人信息 - -维护人: - -- [Sunwancn](https://github.com/Sunwancn), 邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32l433-st-nucleo/README_zh.md b/bsp/stm32/stm32l433-st-nucleo/README_zh.md new file mode 100644 index 0000000000..ce2d27823b --- /dev/null +++ b/bsp/stm32/stm32l433-st-nucleo/README_zh.md @@ -0,0 +1,113 @@ +# NUCLEO-L433RC 开发板 BSP 说明 + +## 简介 + +本文档为ST官方 NUCLEO-L433RC 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +对于 NUCLEO-L433RC，内核是 Cortex-M4，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，mirco USB 接口，可数的外设，Arduino™ nano 兼容的接口。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L433RC，主频 80MHz，256KB FLASH ，64KB RAM。 +- 常用外设 + - LED：4个，USB communication(LD1 双色)，USB overcurrent(LD2 红色)，power LED(LD3 绿色)，user LED(LD4 绿色) + - 按键：2 个，USER and RESET 。 +- 常用接口：USB 转串口、Arduino Uno 和 ST morpho 两类扩展接口 +- 调试接口：板载 ST-LINK/V2-1 调试器。 + +快速入门：[STM32 Nucleo板软件开发工具入门](https://www.st.com/resource/zh/user_manual/dm00105928-getting-started-with-stm32-nucleo-board-software-development-tools-stmicroelectronics.pdf) + +原理图下载：[NUCLEO-L433RC-P schematic](https://www.st.com/resource/en/schematic_pack/nucleo-l433rc-p_sch.zip) + +开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L433RC-P](https://www.st.com/content/st_com/zh/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l433rc-p.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------ | +| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | +| UART | 支持 | UART1, UART2 | +| SPI | 支持 | SPI1 | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 绿色 LD3 常亮、绿色 LD4 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Jan 9 2019 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 + +## 联系人信息 + +维护人: + +- [Sunwancn](https://github.com/Sunwancn), 邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32l452-st-nucleo/README.md b/bsp/stm32/stm32l452-st-nucleo/README.md index d054b12052..af8b1c625b 100644 --- a/bsp/stm32/stm32l452-st-nucleo/README.md +++ b/bsp/stm32/stm32l452-st-nucleo/README.md @@ -1,115 +1,32 @@ -# NUCLEO-L452RE BSP 说明 +# STM32L452-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为刘恒为 NUCLEO-L452RE 开发板提供的 BSP (板级支持包) 说明。 +## MCU: STM32L452RE @80MHz, 512KB FLASH, 160KB RAM -主要内容如下： +https://www.st.com/resource/en/datasheet/stm32l452re.pdf -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 -## 开发板介绍 +## Read more -对于 NUCLEO-L452RE，内核是 Cortex-M4，这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，MINI USB 接口，兼容 Arduino、还带有ST Zio和 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32L452RE ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32l452re.html#documentation) | STM32L452RE datasheet and other resources | -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Maintained By -- MCU：STM32L452RE，主频 80MHz，512KB FLASH ，160KB RAM -- 常用外设 - - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 绿色) - - 按键：2个，复位按键 B2，用户按键 B1。 -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 -- 调试接口：板载 ST-LINK/V2-1 调试器。 +[liuheng](https://github.com/lhxzui), <[email protected]> -开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L452RE](https://www.st.com/en/evaluation-tools/nucleo-l452re.html#)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Translated By -| **板载外设** | **支持情况** | **备注** | -| :---------------: | :----------: | :-----------------------------------: | -| ST-LINK | 支持 | | -| USB 转串口 | 支持 | UART2 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | -| UART | 支持 | UART1(TX:PA9 RX:PA10)、UART2(TX:PA2 RX:PA2) | -| SPI | 支持 | SPI1 | -| I2C | 暂不支持 | | -| RTC | 暂不支持 | | -| PWM | 暂不支持 | | -| USB Device | 暂不支持 | | -| IWG | 暂不支持 | | +Meco Man @ RT-Thread Community -## 使用说明 - -使用说明分为如下两个章节： - -- 快速上手 - - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 miniUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 常亮、绿色 LD2 会周期性闪烁。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -``` - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build May 31 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` - -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -1. MCU 片内 SRAM 有 SRAM1、SRAM2，分别是 128KB、32KB，共计 160KB，本 bsp 只使用 SRAM1 128KB. - -## 联系人信息 - -维护人: - -- [刘恒](https://github.com/lhxzui), 邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32l452-st-nucleo/README_zh.md b/bsp/stm32/stm32l452-st-nucleo/README_zh.md new file mode 100644 index 0000000000..065dd2171d --- /dev/null +++ b/bsp/stm32/stm32l452-st-nucleo/README_zh.md @@ -0,0 +1,115 @@ +# NUCLEO-L452RE BSP 说明 + +## 简介 + +本文档为 NUCLEO-L452RE 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +对于 NUCLEO-L452RE，内核是 Cortex-M4，这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，MINI USB 接口，兼容 Arduino、还带有ST Zio和 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L452RE，主频 80MHz，512KB FLASH ，160KB RAM +- 常用外设 + - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 绿色) + - 按键：2个，复位按键 B2，用户按键 B1。 +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 +- 调试接口：板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L452RE](https://www.st.com/en/evaluation-tools/nucleo-l452re.html#)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :---------------: | :----------: | :-----------------------------------: | +| ST-LINK | 支持 | | +| USB 转串口 | 支持 | UART2 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | UART1(TX:PA9 RX:PA10)、UART2(TX:PA2 RX:PA2) | +| SPI | 支持 | SPI1 | +| I2C | 暂不支持 | | +| RTC | 暂不支持 | | +| PWM | 暂不支持 | | +| USB Device | 暂不支持 | | +| IWG | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 miniUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 常亮、绿色 LD2 会周期性闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build May 31 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +1. MCU 片内 SRAM 有 SRAM1、SRAM2，分别是 128KB、32KB，共计 160KB，本 bsp 只使用 SRAM1 128KB. + +## 联系人信息 + +维护人: + +- [刘恒](https://github.com/lhxzui), 邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject index f56464c131..c2677f50a6 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject @@ -1,11 +1,5 @@ -[PreviousGenFiles] -HeaderPath=E:/1-thread-source/rt-thread_f/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc -HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; -SourcePath=E:/1-thread-source/rt-thread_f/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src -SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; - [PreviousLibFiles] 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iver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c; [PreviousUsedKeilFiles] SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;..\\Src/system_stm32l4xx.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;..\\Src/system_stm32l4xx.c;..\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;; @@ -15,3 +9,9 @@ CDefines=USE_HAL_DRIVER;STM32L475xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [] SourceFiles=;; +[PreviousGenFiles] +HeaderPath=G:/workspaces/rt-thread-gitee/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc +HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; +SourcePath=G:/workspaces/rt-thread-gitee/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src +SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; + diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index 0b52b6e496..0fbd8f3767 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -1,40 +1,27 @@ /** ****************************************************************************** * @file stm32l4xx_hal_conf.h - * @brief HAL configuration file. + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l4xx_hal_conf.h. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2020 STMicroelectronics</center></h2> + * <h2><center>© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.</center></h2> * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H +#ifndef STM32L4xx_HAL_CONF_H +#define STM32L4xx_HAL_CONF_H #ifdef __cplusplus extern "C" { @@ -45,17 +32,16 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ - -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED /*#define HAL_DCMI_MODULE_ENABLED */ /*#define HAL_DMA2D_MODULE_ENABLED */ /*#define HAL_DFSDM_MODULE_ENABLED */ @@ -97,7 +83,7 @@ /*#define HAL_EXTI_MODULE_ENABLED */ /*#define HAL_PSSI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED -#define HAL_EXTI_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED @@ -109,9 +95,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -129,7 +115,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -142,7 +128,7 @@ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * which is subject to manufacturing process variations. */ -#if !defined (HSI48_VALUE) +#if !defined (HSI48_VALUE) #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -150,8 +136,8 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ @@ -161,29 +147,29 @@ * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ + #define EXTERNAL_SAI1_CLOCK_VALUE 2097000U /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ + #define EXTERNAL_SAI2_CLOCK_VALUE 2097000U /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -192,22 +178,67 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ - -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U + */ + +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ +#define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver @@ -224,20 +255,14 @@ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32l4xx_hal_rcc.h" - #include "stm32l4xx_hal_rcc_ex.h" #endif /* HAL_RCC_MODULE_ENABLED */ -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32l4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32l4xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32l4xx_hal_dma.h" - #include "stm32l4xx_hal_dma_ex.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_DFSDM_MODULE_ENABLED @@ -256,6 +281,10 @@ #include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ @@ -284,6 +313,14 @@ #include "stm32l4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ @@ -296,26 +333,18 @@ #include "stm32l4xx_hal_hash.h" #endif /* HAL_HASH_MODULE_ENABLED */ -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32l4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED #include "stm32l4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + #ifdef HAL_IWDG_MODULE_ENABLED #include "stm32l4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ @@ -332,6 +361,18 @@ #include "stm32l4xx_hal_ltdc.h" #endif /* HAL_LTDC_MODULE_ENABLED */ +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ @@ -340,9 +381,17 @@ #include "stm32l4xx_hal_ospi.h" #endif /* HAL_OSPI_MODULE_ENABLED */ +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + #ifdef HAL_PKA_MODULE_ENABLED #include "stm32l4xx_hal_pka.h" -#endif /* HAL_PWR_MODULE_ENABLED */ +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32l4xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED #include "stm32l4xx_hal_pwr.h" @@ -368,6 +417,10 @@ #include "stm32l4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + #ifdef HAL_SMBUS_MODULE_ENABLED #include "stm32l4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ @@ -376,6 +429,10 @@ #include "stm32l4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + #ifdef HAL_SWPMI_MODULE_ENABLED #include "stm32l4xx_hal_swpmi.h" #endif /* HAL_SWPMI_MODULE_ENABLED */ @@ -396,39 +453,15 @@ #include "stm32l4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - #ifdef HAL_WWDG_MODULE_ENABLED #include "stm32l4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_GFXMMU_MODULE_ENABLED - #include "stm32l4xx_hal_gfxmmu.h" -#endif /* HAL_GFXMMU_MODULE_ENABLED */ - -#ifdef HAL_PSSI_MODULE_ENABLED - #include "stm32l4xx_hal_pssi.h" -#endif /* HAL_PSSI_MODULE_ENABLED */ - /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. @@ -436,7 +469,7 @@ */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(char *file, uint32_t line); + void assert_failed(uint8_t *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ @@ -445,6 +478,6 @@ } #endif -#endif /* __STM32L4xx_HAL_CONF_H */ +#endif /* STM32L4xx_HAL_CONF_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h index 666700442b..c609646383 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h @@ -39,7 +39,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc index 5b1083a232..3a59471b8a 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc @@ -1,363 +1,369 @@ #MicroXplorer Configuration settings - do not modify +ADC1.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_14 +ADC1.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,OffsetNumber-15\#ChannelRegularConversion,NbrOfConversionFlag,master +ADC1.NbrOfConversionFlag=1 +ADC1.OffsetNumber-15\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.Rank-15\#ChannelRegularConversion=1 +ADC1.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 +ADC1.master=1 +File.Version=6 +KeepUserPlacement=false Mcu.Family=STM32L4 -ProjectManager.MainLocation=Src -PA6.Mode=Full_Duplex_Master -SH.S_TIM4_CH2.ConfNb=1 -RCC.USART1Freq_Value=80000000 -RCC.SAI1Freq_Value=13714285.714285715 -USART2.IPParameters=VirtualMode-Asynchronous -RCC.CortexFreq_Value=80000000 -SPI3.Direction=SPI_DIRECTION_2LINES -VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer -SPI3.VirtualType=VM_MASTER -ProjectManager.KeepUserCode=true -Mcu.UserName=STM32L475VETx -SPI1.VirtualType=VM_MASTER -SPI2.VirtualType=VM_MASTER -PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN -TIM1.IPParameters=Channel-PWM Generation1 CH1 -PC10.Signal=SDMMC1_D2 -PC12.Signal=SDMMC1_CK -VP_IWDG_VS_IWDG.Mode=IWDG_Activate -RCC.PLLSAI1RoutputFreq_Value=48000000 -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true,11-MX_TIM17_Init-TIM17-false-HAL-true,12-MX_TIM16_Init-TIM16-false-HAL-true,13-MX_TIM15_Init-TIM15-false-HAL-true,14-MX_TIM4_Init-TIM4-false-HAL-true,15-MX_TIM1_Init-TIM1-false-HAL-true,16-MX_SAI1_Init-SAI1-false-HAL-true,17-MX_SPI3_Init-SPI3-false-HAL-true,18-MX_TIM2_Init-TIM2-false-HAL-true,19-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true -SAI1.VirtualProtocol-SAI_A_BASIC=VM_BASIC_PROTOCOL -VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled -SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A -PA11.Mode=Device_Only -RCC.RTCFreq_Value=32768 -RCC.USART2Freq_Value=80000000 -PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator -SH.S_TIM1_CH1.ConfNb=1 -USART1.IPParameters=VirtualMode-Asynchronous -PB11.Signal=S_TIM2_CH4 -PB13.Signal=SPI2_SCK -PB15.Signal=SPI2_MOSI -PinOutPanel.RotationAngle=0 -RCC.MCO1PinFreq_Value=80000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -ProjectManager.StackSize=0x400 -PB3\ (JTDO-TRACESWO).Signal=SPI3_SCK -PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator -PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK -RCC.I2C3Freq_Value=80000000 -RCC.LPTIM1Freq_Value=80000000 -Mcu.IP4=QUADSPI -Mcu.IP5=RCC -RCC.FCLKCortexFreq_Value=80000000 -Mcu.IP2=LPTIM1 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false -Mcu.IP3=NVIC Mcu.IP0=ADC1 -Mcu.IP1=IWDG -PA12.Signal=USB_OTG_FS_DP -Mcu.UserConstants= -PE11.Mode=Single Bank -RCC.VCOSAI1OutputFreq_Value=96000000 -SAI1.VirtualMode-SAI_B_SyncSlave=VM_SLAVE -RCC.SDMMCFreq_Value=48000000 -Mcu.ThirdPartyNb=0 -SPI1.Direction=SPI_DIRECTION_2LINES -RCC.HCLKFreq_Value=80000000 -PE2.Mode=SAI_A_MasterWithClock -Mcu.IPNb=22 -TIM2.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 -ProjectManager.PreviousToolchain= -RCC.APB2TimFreq_Value=80000000 -VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIB_SAI_BASIC -SPI1.CalculateBaudRate=40.0 MBits/s -Mcu.Pin6=PC15-OSC32_OUT (PC15) -RCC.SAI2Freq_Value=13714285.714285715 -Mcu.Pin7=PH0-OSC_IN (PH0) -VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT -Mcu.Pin8=PH1-OSC_OUT (PH1) -PE5.Signal=SAI1_SCK_A -Mcu.Pin9=PA2 -RCC.AHBFreq_Value=80000000 -PB13.Locked=true +Mcu.IP1=DAC1 +Mcu.IP10=SPI1 +Mcu.IP11=SPI2 +Mcu.IP12=SPI3 +Mcu.IP13=SYS +Mcu.IP14=TIM1 +Mcu.IP15=TIM2 +Mcu.IP16=TIM4 +Mcu.IP17=TIM15 +Mcu.IP18=TIM16 +Mcu.IP19=TIM17 +Mcu.IP2=IWDG +Mcu.IP20=USART1 +Mcu.IP21=USART2 +Mcu.IP22=USB_OTG_FS +Mcu.IP3=LPTIM1 +Mcu.IP4=NVIC +Mcu.IP5=QUADSPI +Mcu.IP6=RCC +Mcu.IP7=RTC +Mcu.IP8=SAI1 +Mcu.IP9=SDMMC1 +Mcu.IPNb=23 +Mcu.Name=STM32L475V(C-E-G)Tx +Mcu.Package=LQFP100 Mcu.Pin0=PE2 -PE14.Locked=true Mcu.Pin1=PE3 +Mcu.Pin10=PA3 +Mcu.Pin11=PA4 +Mcu.Pin12=PA5 +Mcu.Pin13=PA6 +Mcu.Pin14=PA7 +Mcu.Pin15=PC5 +Mcu.Pin16=PE9 +Mcu.Pin17=PE10 +Mcu.Pin18=PE11 +Mcu.Pin19=PE12 Mcu.Pin2=PE4 +Mcu.Pin20=PE13 +Mcu.Pin21=PE14 +Mcu.Pin22=PE15 +Mcu.Pin23=PB10 +Mcu.Pin24=PB11 +Mcu.Pin25=PB13 +Mcu.Pin26=PB14 +Mcu.Pin27=PB15 +Mcu.Pin28=PC8 +Mcu.Pin29=PC9 Mcu.Pin3=PE5 -RCC.USART3Freq_Value=80000000 +Mcu.Pin30=PA9 +Mcu.Pin31=PA10 +Mcu.Pin32=PA11 +Mcu.Pin33=PA12 +Mcu.Pin34=PA13 (JTMS-SWDIO) +Mcu.Pin35=PA14 (JTCK-SWCLK) +Mcu.Pin36=PC10 +Mcu.Pin37=PC11 +Mcu.Pin38=PC12 +Mcu.Pin39=PD2 Mcu.Pin4=PE6 +Mcu.Pin40=PB3 (JTDO-TRACESWO) +Mcu.Pin41=PB5 +Mcu.Pin42=PB7 +Mcu.Pin43=PB8 +Mcu.Pin44=VP_IWDG_VS_IWDG +Mcu.Pin45=VP_LPTIM1_VS_LPTIM_counterModeInternalClock +Mcu.Pin46=VP_RTC_VS_RTC_Activate +Mcu.Pin47=VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC +Mcu.Pin48=VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC +Mcu.Pin49=VP_SYS_VS_Systick Mcu.Pin5=PC14-OSC32_IN (PC14) -ProjectManager.ProjectBuild=false -PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator -RCC.HSE_VALUE=8000000 -TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.Pin50=VP_TIM1_VS_ClockSourceINT +Mcu.Pin51=VP_TIM2_VS_ClockSourceINT +Mcu.Pin52=VP_TIM4_VS_ClockSourceINT +Mcu.Pin53=VP_TIM15_VS_ClockSourceINT +Mcu.Pin54=VP_TIM16_VS_ClockSourceINT +Mcu.Pin55=VP_TIM17_VS_ClockSourceINT +Mcu.Pin6=PC15-OSC32_OUT (PC15) +Mcu.Pin7=PH0-OSC_IN (PH0) +Mcu.Pin8=PH1-OSC_OUT (PH1) +Mcu.Pin9=PA2 +Mcu.PinsNb=56 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32L475VETx +MxCube.Version=6.0.1 +MxDb.Version=DB.6.0.0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false -SH.ADCx_IN14.ConfNb=1 -Mcu.IP10=SPI2 -USART2.VirtualMode-Asynchronous=VM_ASYNC +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE -Mcu.IP12=SYS -Mcu.IP11=SPI3 -ADC1.OffsetNumber-15\#ChannelRegularConversion=ADC_OFFSET_NONE -Mcu.IP18=TIM17 -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.15.1 -Mcu.IP17=TIM16 -MxDb.Version=DB.5.0.60 -PE15.Locked=true -Mcu.IP19=USART1 -Mcu.IP14=TIM2 -Mcu.IP13=TIM1 -PE13.Signal=QUADSPI_BK1_IO1 -Mcu.IP16=TIM15 -ProjectManager.BackupPrevious=false -Mcu.IP15=TIM4 -RCC.VCOInputFreq_Value=8000000 -TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 -PE9.Signal=S_TIM1_CH1 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA11.Mode=Device_Only +PA11.Signal=USB_OTG_FS_DM +PA12.Mode=Device_Only +PA12.Signal=USB_OTG_FS_DP +PA13\ (JTMS-SWDIO).Mode=Serial_Wire +PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO +PA14\ (JTCK-SWCLK).Mode=Serial_Wire +PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA4.Signal=COMP_DAC11_group +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB10.Signal=S_TIM2_CH3 +PB11.Signal=S_TIM2_CH4 +PB13.Locked=true +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK +PB14.Locked=true PB14.Mode=Full_Duplex_Master +PB14.Signal=SPI2_MISO +PB15.Locked=true +PB15.Mode=Full_Duplex_Master +PB15.Signal=SPI2_MOSI +PB3\ (JTDO-TRACESWO).Locked=true +PB3\ (JTDO-TRACESWO).Mode=TX_Only_Simplex_Unidirect_Master +PB3\ (JTDO-TRACESWO).Signal=SPI3_SCK +PB5.Locked=true PB5.Mode=TX_Only_Simplex_Unidirect_Master -File.Version=6 -PC9.Mode=SD_4_bits_Wide_bus -SPI2.CalculateBaudRate=40.0 MBits/s -SAI1.InitProtocol-SAI_A_MasterWithClock=Enable -SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2 -PE2.Signal=SAI1_MCLK_A +PB5.Signal=SPI3_MOSI +PB7.Locked=true PB7.Signal=S_TIM4_CH2 -Mcu.IP21=USB_OTG_FS PB8.Locked=true -Mcu.IP20=USART2 -RCC.PLLRCLKFreq_Value=80000000 +PB8.Signal=S_TIM4_CH3 +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDMMC1_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDMMC1_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDMMC1_CK +PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator +PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN +PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator +PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT +PC5.Signal=ADCx_IN14 +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDMMC1_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDMMC1_D1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDMMC1_CMD +PE10.Mode=Single Bank +PE10.Signal=QUADSPI_CLK +PE11.Mode=Single Bank +PE11.Signal=QUADSPI_NCS +PE12.Locked=true +PE12.Mode=Single Bank +PE12.Signal=QUADSPI_BK1_IO0 +PE13.Locked=true PE13.Mode=Single Bank -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PE13.Signal=QUADSPI_BK1_IO1 +PE14.Locked=true +PE14.Mode=Single Bank +PE14.Signal=QUADSPI_BK1_IO2 +PE15.Locked=true +PE15.Mode=Single Bank +PE15.Signal=QUADSPI_BK1_IO3 +PE2.Mode=SAI_A_MasterWithClock +PE2.Signal=SAI1_MCLK_A +PE3.Mode=SAI_B_SyncSlave +PE3.Signal=SAI1_SD_B PE4.Mode=SAI_A_MasterWithClock -ADC1.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_14 PE4.Signal=SAI1_FS_A -PE10.Signal=QUADSPI_CLK -VP_TIM15_VS_ClockSourceINT.Signal=TIM15_VS_ClockSourceINT +PE5.Mode=SAI_A_MasterWithClock +PE5.Signal=SAI1_SCK_A +PE6.Mode=SAI_A_MasterWithClock +PE6.Signal=SAI1_SD_A +PE9.Signal=S_TIM1_CH1 +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32L475VETx +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.16.0 +ProjectManager.FreePins=false ProjectManager.HalAssertFull=false -VP_TIM1_VS_ClockSourceINT.Mode=Internal +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STM32L475VE.ioc ProjectManager.ProjectName=STM32L475VE -ADC1.Rank-15\#ChannelRegularConversion=1 -SAI1.OutputDrive-SAI_A_MasterWithClock=SAI_OUTPUTDRIVE_ENABLE -Mcu.Package=LQFP100 -SAI1.AudioFrequency-SAI_A_MasterWithClock=SAI_AUDIO_FREQUENCY_44K -PA6.Signal=SPI1_MISO -SPI2.Mode=SPI_MODE_MASTER -SPI3.Mode=SPI_MODE_MASTER -SH.ADCx_IN14.0=ADC1_IN14,IN14-Single-Ended -NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= -RCC.LSI_VALUE=32000 -VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -RCC.LSCOPinFreq_Value=32000 -PA10.Signal=USART1_RX -USB_OTG_FS.VirtualMode=Device_Only -RCC.DFSDMFreq_Value=80000000 -PC11.Mode=SD_4_bits_Wide_bus -ADC1.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 -RCC.PLLPoutputFreq_Value=22857142.85714286 +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true,11-MX_TIM17_Init-TIM17-false-HAL-true,12-MX_TIM16_Init-TIM16-false-HAL-true,13-MX_TIM15_Init-TIM15-false-HAL-true,14-MX_TIM4_Init-TIM4-false-HAL-true,15-MX_TIM1_Init-TIM1-false-HAL-true,16-MX_SAI1_Init-SAI1-false-HAL-true,17-MX_SPI3_Init-SPI3-false-HAL-true,18-MX_TIM2_Init-TIM2-false-HAL-true,19-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,20-MX_LPTIM1_Init-LPTIM1-false-HAL-true,21-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,22-MX_DAC1_Init-DAC1-false-HAL-true +RCC.ADCFreq_Value=48000000 +RCC.AHBFreq_Value=80000000 +RCC.APB1Freq_Value=80000000 RCC.APB1TimFreq_Value=80000000 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +RCC.APB2Freq_Value=80000000 +RCC.APB2TimFreq_Value=80000000 +RCC.CortexFreq_Value=80000000 +RCC.DFSDMFreq_Value=80000000 +RCC.FCLKCortexFreq_Value=80000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=80000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=80000000 +RCC.I2C2Freq_Value=80000000 +RCC.I2C3Freq_Value=80000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value +RCC.LPTIM1Freq_Value=80000000 +RCC.LPTIM2Freq_Value=80000000 RCC.LPUART1Freq_Value=80000000 -SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -SPI2.Direction=SPI_DIRECTION_2LINES -PC5.Signal=ADCx_IN14 -USB_OTG_FS.IPParameters=VirtualMode -PB13.Mode=Full_Duplex_Master -SH.S_TIM2_CH4.ConfNb=1 -PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO -PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator -PE12.Locked=true -PE3.Mode=SAI_B_SyncSlave -ProjectManager.CustomerFirmwarePackage= -PB15.Locked=true -PB3\ (JTDO-TRACESWO).Locked=true -RCC.PLLSAI1N=12 -PA3.Signal=USART2_RX -PA5.Mode=Full_Duplex_Master -PE12.Mode=Single Bank -VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +RCC.LSCOPinFreq_Value=32000 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=80000000 RCC.MSI_VALUE=4000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -PA14\ (JTCK-SWCLK).Mode=Serial_Wire +RCC.PLLN=20 +RCC.PLLPoutputFreq_Value=22857142.85714286 RCC.PLLQoutputFreq_Value=80000000 -ProjectManager.ProjectFileName=STM32L475VE.ioc -TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 -PA7.Mode=Full_Duplex_Master -PA10.Mode=Asynchronous -Mcu.PinsNb=55 -VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Mode=SAI_A_BASIC -ProjectManager.NoMain=false -SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -ADC1.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,OffsetNumber-15\#ChannelRegularConversion,NbrOfConversionFlag,master -SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE -PC11.Signal=SDMMC1_D3 +RCC.PLLRCLKFreq_Value=80000000 +RCC.PLLSAI1N=12 +RCC.PLLSAI1PoutputFreq_Value=13714285.714285715 +RCC.PLLSAI1QoutputFreq_Value=48000000 +RCC.PLLSAI1RoutputFreq_Value=48000000 +RCC.PLLSAI2PoutputFreq_Value=9142857.142857144 +RCC.PLLSAI2RoutputFreq_Value=32000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.PWRFreq_Value=80000000 +RCC.RNGFreq_Value=48000000 +RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 +RCC.SAI1Freq_Value=13714285.714285715 +RCC.SAI2Freq_Value=13714285.714285715 +RCC.SDMMCFreq_Value=48000000 RCC.SWPMI1Freq_Value=80000000 -PC8.Signal=SDMMC1_D0 -PE10.Mode=Single Bank -PC10.Mode=SD_4_bits_Wide_bus -VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIA_SAI_BASIC -ProjectManager.DefaultFWLocation=true -SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-72.09 % -PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer -ProjectManager.DeletePrevious=true -PB14.Locked=true +RCC.SYSCLKFreq_VALUE=80000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=80000000 +RCC.UART5Freq_Value=80000000 +RCC.USART1Freq_Value=80000000 +RCC.USART2Freq_Value=80000000 +RCC.USART3Freq_Value=80000000 +RCC.USBFreq_Value=48000000 +RCC.VCOInputFreq_Value=8000000 +RCC.VCOOutputFreq_Value=160000000 +RCC.VCOSAI1OutputFreq_Value=96000000 RCC.VCOSAI2OutputFreq_Value=64000000 -VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT -RCC.FamilyName=M -PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT -USART1.VirtualMode-Asynchronous=VM_ASYNC -PA3.Mode=Asynchronous +SAI1.AudioFrequency-SAI_A_MasterWithClock=SAI_AUDIO_FREQUENCY_44K +SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-72.09 % +SAI1.IPParameters=Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock,InitProtocol-SAI_A_MasterWithClock,VirtualProtocol-SAI_A_BASIC,AudioFrequency-SAI_A_MasterWithClock,OutputDrive-SAI_A_MasterWithClock,Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,InitProtocol-SAI_B_SyncSlave,VirtualProtocol-SAI_B_BASIC +SAI1.InitProtocol-SAI_A_MasterWithClock=Enable +SAI1.InitProtocol-SAI_B_SyncSlave=Enable +SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A +SAI1.Instance-SAI_B_SyncSlave=SAI$Index_Block_B +SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE +SAI1.OutputDrive-SAI_A_MasterWithClock=SAI_OUTPUTDRIVE_ENABLE SAI1.RealAudioFreq-SAI_A_MasterWithClock=53.571 KHz -PA9.Mode=Asynchronous +SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER +SAI1.VirtualMode-SAI_B_SyncSlave=VM_SLAVE +SAI1.VirtualProtocol-SAI_A_BASIC=VM_BASIC_PROTOCOL +SAI1.VirtualProtocol-SAI_B_BASIC=VM_BASIC_PROTOCOL +SH.ADCx_IN14.0=ADC1_IN14,IN14-Single-Ended +SH.ADCx_IN14.ConfNb=1 +SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1 +SH.COMP_DAC11_group.ConfNb=1 SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1 -VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT -ProjectManager.TargetToolchain=MDK-ARM V5 -TIM4.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation2 CH2 -Mcu.Pin51=VP_TIM4_VS_ClockSourceINT -Mcu.Pin52=VP_TIM15_VS_ClockSourceINT -Mcu.Pin50=VP_TIM2_VS_ClockSourceINT +SH.S_TIM1_CH1.ConfNb=1 +SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3 +SH.S_TIM2_CH3.ConfNb=1 +SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 +SH.S_TIM2_CH4.ConfNb=1 +SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2 +SH.S_TIM4_CH2.ConfNb=1 SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 -Mcu.Pin53=VP_TIM16_VS_ClockSourceINT -Mcu.Pin54=VP_TIM17_VS_ClockSourceINT -PA9.Signal=USART1_TX -VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT -PB5.Locked=true -SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -RCC.USBFreq_Value=48000000 -PE11.Signal=QUADSPI_NCS -Mcu.Pin48=VP_SYS_VS_Systick -Mcu.Pin49=VP_TIM1_VS_ClockSourceINT -RCC.PLLSAI1PoutputFreq_Value=13714285.714285715 -Mcu.Pin46=VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC -Mcu.Pin47=VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC -PB10.Signal=S_TIM2_CH3 -SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER SH.S_TIM4_CH3.ConfNb=1 -VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Mode=SAI_B_BASIC -PB14.Signal=SPI2_MISO -PD2.Mode=SD_4_bits_Wide_bus -RCC.PLLSAI2RoutputFreq_Value=32000000 -PA5.Signal=SPI1_SCK -Mcu.Pin40=PB5 -Mcu.Pin41=PB7 -PC12.Mode=SD_4_bits_Wide_bus -Mcu.Pin44=VP_LPTIM1_VS_LPTIM_counterModeInternalClock -Mcu.Pin45=VP_RTC_VS_RTC_Activate -Mcu.Pin42=PB8 -board=custom -Mcu.Pin43=VP_IWDG_VS_IWDG -SAI1.IPParameters=Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock,InitProtocol-SAI_A_MasterWithClock,VirtualProtocol-SAI_A_BASIC,AudioFrequency-SAI_A_MasterWithClock,OutputDrive-SAI_A_MasterWithClock,Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,InitProtocol-SAI_B_SyncSlave,VirtualProtocol-SAI_B_BASIC -RCC.VCOOutputFreq_Value=160000000 -ProjectManager.LastFirmware=true -PB15.Mode=Full_Duplex_Master -TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 -RCC.APB2Freq_Value=80000000 -PE14.Signal=QUADSPI_BK1_IO2 -RCC.UART4Freq_Value=80000000 -SPI3.CalculateBaudRate=40.0 MBits/s -PE6.Mode=SAI_A_MasterWithClock -PE15.Signal=QUADSPI_BK1_IO3 -MxCube.Version=5.6.0 -Mcu.Pin37=PC12 -Mcu.Pin38=PD2 -Mcu.Pin35=PC10 -VP_TIM2_VS_ClockSourceINT.Mode=Internal -RCC.I2C1Freq_Value=80000000 -SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3 -Mcu.Pin36=PC11 +SPI1.CalculateBaudRate=40.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate SPI1.Mode=SPI_MODE_MASTER -Mcu.Pin39=PB3 (JTDO-TRACESWO) -PE14.Mode=Single Bank -PB3\ (JTDO-TRACESWO).Mode=TX_Only_Simplex_Unidirect_Master -RCC.RNGFreq_Value=48000000 -PE5.Mode=SAI_A_MasterWithClock -RCC.PLLSAI1QoutputFreq_Value=48000000 -Mcu.Pin30=PA10 -RCC.ADCFreq_Value=48000000 -VP_SYS_VS_Systick.Mode=SysTick +SPI1.VirtualType=VM_MASTER +SPI2.CalculateBaudRate=40.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +SPI3.CalculateBaudRate=40.0 MBits/s +SPI3.Direction=SPI_DIRECTION_2LINES +SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI3.Mode=SPI_MODE_MASTER +SPI3.VirtualType=VM_MASTER +TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +TIM1.IPParameters=Channel-PWM Generation1 CH1 TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 -Mcu.Pin33=PA13 (JTMS-SWDIO) -Mcu.Pin34=PA14 (JTCK-SWCLK) -Mcu.Pin31=PA11 -Mcu.Pin32=PA12 -VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false -SH.S_TIM2_CH3.ConfNb=1 -PE6.Signal=SAI1_SD_A -RCC.UART5Freq_Value=80000000 -ProjectManager.FreePins=false -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value -ProjectManager.AskForMigrate=true -Mcu.Name=STM32L475V(C-E-G)Tx -RCC.LPTIM2Freq_Value=80000000 -Mcu.Pin26=PB15 -PE12.Signal=QUADSPI_BK1_IO0 -Mcu.Pin27=PC8 -PA2.Signal=USART2_TX -Mcu.Pin24=PB13 -ProjectManager.UnderRoot=false -Mcu.Pin25=PB14 -PE13.Locked=true -Mcu.IP8=SDMMC1 -Mcu.IP9=SPI1 -Mcu.Pin28=PC9 -Mcu.IP6=RTC -PC8.Mode=SD_4_bits_Wide_bus -Mcu.Pin29=PA9 -Mcu.IP7=SAI1 -ProjectManager.CoupleFile=false -PA13\ (JTMS-SWDIO).Mode=Serial_Wire -RCC.SYSCLKFreq_VALUE=80000000 -Mcu.Pin22=PB10 -PB5.Signal=SPI3_MOSI -Mcu.Pin23=PB11 -Mcu.Pin20=PE14 -ADC1.master=1 -Mcu.Pin21=PE15 -PA12.Mode=Device_Only -NVIC.ForceEnableDMAVector=true -RCC.PLLSAI2PoutputFreq_Value=9142857.142857144 -KeepUserPlacement=false -PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false -ProjectManager.CompilerOptimize=6 -SAI1.Instance-SAI_B_SyncSlave=SAI$Index_Block_B -PA11.Signal=USB_OTG_FS_DM +TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM2.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 +TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM4.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation2 CH2 +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +USART2.IPParameters=VirtualMode-Asynchronous +USART2.VirtualMode-Asynchronous=VM_ASYNC +USB_OTG_FS.IPParameters=VirtualMode +USB_OTG_FS.VirtualMode=Device_Only +VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Mode=SAI_A_BASIC +VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIA_SAI_BASIC +VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Mode=SAI_B_BASIC +VP_SAI1_VP_$IpInstance_SAIB_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIB_SAI_BASIC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM15_VS_ClockSourceINT.Mode=Internal -ProjectManager.HeapSize=0x200 -Mcu.Pin15=PE9 -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -Mcu.Pin16=PE10 -Mcu.Pin13=PA7 -SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 -Mcu.Pin14=PC5 -Mcu.Pin19=PE13 -ProjectManager.ComputerToolchain=false -Mcu.Pin17=PE11 -RCC.HSI_VALUE=16000000 -Mcu.Pin18=PE12 +VP_TIM15_VS_ClockSourceINT.Signal=TIM15_VS_ClockSourceINT +VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT +VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT +VP_TIM1_VS_ClockSourceINT.Mode=Internal +VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT +VP_TIM2_VS_ClockSourceINT.Mode=Internal +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT VP_TIM4_VS_ClockSourceINT.Mode=Internal -SAI1.VirtualProtocol-SAI_B_BASIC=VM_BASIC_PROTOCOL -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -ADC1.NbrOfConversionFlag=1 -Mcu.Pin11=PA5 -Mcu.Pin12=PA6 -RCC.PLLN=20 -Mcu.Pin10=PA3 -PB7.Locked=true -PE3.Signal=SAI1_SD_B -PA2.Mode=Asynchronous -PB8.Signal=S_TIM4_CH3 -VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock -RCC.PWRFreq_Value=80000000 -PC9.Signal=SDMMC1_D1 -PD2.Signal=SDMMC1_CMD -RCC.I2C2Freq_Value=80000000 -RCC.APB1Freq_Value=80000000 -SAI1.InitProtocol-SAI_B_SyncSlave=Enable -ProjectManager.DeviceId=STM32L475VETx -ProjectManager.LibraryCopy=0 -PE15.Mode=Single Bank -PA7.Signal=SPI1_MOSI +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT +board=custom diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c index 5a91b40917..2a9dcd82a7 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c @@ -37,7 +37,6 @@ ****************************************************************************** */ /* USER CODE END Header */ - /* Includes ------------------------------------------------------------------*/ #include "main.h" @@ -64,6 +63,8 @@ /* Private variables ---------------------------------------------------------*/ ADC_HandleTypeDef hadc1; +DAC_HandleTypeDef hdac1; + IWDG_HandleTypeDef hiwdg; LPTIM_HandleTypeDef hlptim1; @@ -120,6 +121,7 @@ static void MX_TIM2_Init(void); static void MX_USB_OTG_FS_PCD_Init(void); static void MX_LPTIM1_Init(void); static void MX_SDMMC1_SD_Init(void); +static void MX_DAC1_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -177,6 +179,7 @@ int main(void) MX_USB_OTG_FS_PCD_Init(); MX_LPTIM1_Init(); MX_SDMMC1_SD_Init(); + MX_DAC1_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -204,11 +207,12 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -226,7 +230,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -263,7 +267,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { @@ -289,7 +293,7 @@ static void MX_ADC1_Init(void) /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ - /** Common config + /** Common config */ hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; @@ -301,7 +305,6 @@ static void MX_ADC1_Init(void) hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.NbrOfConversion = 1; hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.NbrOfDiscConversion = 1; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; hadc1.Init.DMAContinuousRequests = DISABLE; @@ -311,14 +314,14 @@ static void MX_ADC1_Init(void) { Error_Handler(); } - /** Configure the ADC multi-mode + /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) { Error_Handler(); } - /** Configure Regular Channel + /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; sConfig.Rank = ADC_REGULAR_RANK_1; @@ -337,6 +340,47 @@ static void MX_ADC1_Init(void) } /** + * @brief DAC1 Initialization Function + * @param None + * @retval None + */ +static void MX_DAC1_Init(void) +{ + + /* USER CODE BEGIN DAC1_Init 0 */ + + /* USER CODE END DAC1_Init 0 */ + + DAC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN DAC1_Init 1 */ + + /* USER CODE END DAC1_Init 1 */ + /** DAC Initialization + */ + hdac1.Instance = DAC1; + if (HAL_DAC_Init(&hdac1) != HAL_OK) + { + Error_Handler(); + } + /** DAC channel OUT1 config + */ + sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; + sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; + if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DAC1_Init 2 */ + + /* USER CODE END DAC1_Init 2 */ + +} + +/** * @brief IWDG Initialization Function * @param None * @retval None @@ -447,7 +491,7 @@ static void MX_RTC_Init(void) /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ - /** Initialize RTC Only + /** Initialize RTC Only */ hrtc.Instance = RTC; hrtc.Init.HourFormat = RTC_HOURFORMAT_24; @@ -695,7 +739,7 @@ static void MX_TIM1_Init(void) htim1.Instance = TIM1; htim1.Init.Prescaler = 0; htim1.Init.CounterMode = TIM_COUNTERMODE_UP; - htim1.Init.Period = 0; + htim1.Init.Period = 65535; htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim1.Init.RepetitionCounter = 0; htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; @@ -774,7 +818,7 @@ static void MX_TIM2_Init(void) htim2.Instance = TIM2; htim2.Init.Prescaler = 0; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; - htim2.Init.Period = 0; + htim2.Init.Period = 4294967295; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim2) != HAL_OK) @@ -837,7 +881,7 @@ static void MX_TIM4_Init(void) htim4.Instance = TIM4; htim4.Init.Prescaler = 0; htim4.Init.CounterMode = TIM_COUNTERMODE_UP; - htim4.Init.Period = 0; + htim4.Init.Period = 65535; htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim4) != HAL_OK) @@ -899,7 +943,7 @@ static void MX_TIM15_Init(void) htim15.Instance = TIM15; htim15.Init.Prescaler = 0; htim15.Init.CounterMode = TIM_COUNTERMODE_UP; - htim15.Init.Period = 0; + htim15.Init.Period = 65535; htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim15.Init.RepetitionCounter = 0; htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; @@ -942,7 +986,7 @@ static void MX_TIM16_Init(void) htim16.Instance = TIM16; htim16.Init.Prescaler = 0; htim16.Init.CounterMode = TIM_COUNTERMODE_UP; - htim16.Init.Period = 0; + htim16.Init.Period = 65535; htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim16.Init.RepetitionCounter = 0; htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; @@ -974,7 +1018,7 @@ static void MX_TIM17_Init(void) htim17.Instance = TIM17; htim17.Init.Prescaler = 0; htim17.Init.CounterMode = TIM_COUNTERMODE_UP; - htim17.Init.Period = 0; + htim17.Init.Period = 65535; htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim17.Init.RepetitionCounter = 0; htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; @@ -1138,7 +1182,7 @@ void Error_Handler(void) * @retval None */ void assert_failed(uint8_t *file, uint32_t line) -{ +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 7dc7cc3ad7..a3f28f6117 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -78,7 +78,7 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. @@ -115,10 +115,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PC5 ------> ADC1_IN14 + /**ADC1 GPIO Configuration + PC5 ------> ADC1_IN14 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; @@ -147,9 +147,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PC5 ------> ADC1_IN14 + + /**ADC1 GPIO Configuration + PC5 ------> ADC1_IN14 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_5); @@ -161,6 +161,67 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) } /** +* @brief DAC MSP Initialization +* This function configures the hardware resources used in this example +* @param hdac: DAC handle pointer +* @retval None +*/ +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hdac->Instance==DAC1) + { + /* USER CODE BEGIN DAC1_MspInit 0 */ + + /* USER CODE END DAC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DAC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN DAC1_MspInit 1 */ + + /* USER CODE END DAC1_MspInit 1 */ + } + +} + +/** +* @brief DAC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdac: DAC handle pointer +* @retval None +*/ +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + if(hdac->Instance==DAC1) + { + /* USER CODE BEGIN DAC1_MspDeInit 0 */ + + /* USER CODE END DAC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DAC1_CLK_DISABLE(); + + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); + + /* USER CODE BEGIN DAC1_MspDeInit 1 */ + + /* USER CODE END DAC1_MspDeInit 1 */ + } + +} + +/** * @brief LPTIM MSP Initialization * This function configures the hardware resources used in this example * @param hlptim: LPTIM handle pointer @@ -220,17 +281,17 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PE10 ------> QUADSPI_CLK PE11 ------> QUADSPI_NCS PE12 ------> QUADSPI_BK1_IO0 PE13 ------> QUADSPI_BK1_IO1 PE14 ------> QUADSPI_BK1_IO2 - PE15 ------> QUADSPI_BK1_IO3 + PE15 ------> QUADSPI_BK1_IO3 */ - GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -260,16 +321,16 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PE10 ------> QUADSPI_CLK PE11 ------> QUADSPI_NCS PE12 ------> QUADSPI_BK1_IO0 PE13 ------> QUADSPI_BK1_IO1 PE14 ------> QUADSPI_BK1_IO2 - PE15 ------> QUADSPI_BK1_IO3 + PE15 ------> QUADSPI_BK1_IO3 */ - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15); /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ @@ -339,18 +400,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -387,16 +448,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration + + /**SDMMC1 GPIO Configuration PC8 ------> SDMMC1_D0 PC9 ------> SDMMC1_D1 PC10 ------> SDMMC1_D2 PC11 ------> SDMMC1_D3 PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD + PD2 ------> SDMMC1_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -424,12 +485,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -449,12 +510,12 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -474,11 +535,11 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI3 GPIO Configuration + /**SPI3 GPIO Configuration PB3 (JTDO-TRACESWO) ------> SPI3_SCK - PB5 ------> SPI3_MOSI + PB5 ------> SPI3_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -509,11 +570,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration + + /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI + PA7 ------> SPI1_MOSI */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); @@ -528,11 +589,11 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration + + /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO - PB15 ------> SPI2_MOSI + PB15 ------> SPI2_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); @@ -547,10 +608,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI3_CLK_DISABLE(); - - /**SPI3 GPIO Configuration + + /**SPI3 GPIO Configuration PB3 (JTDO-TRACESWO) ------> SPI3_SCK - PB5 ------> SPI3_MOSI + PB5 ------> SPI3_MOSI */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_5); @@ -647,8 +708,8 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOE_CLK_ENABLE(); - /**TIM1 GPIO Configuration - PE9 ------> TIM1_CH1 + /**TIM1 GPIO Configuration + PE9 ------> TIM1_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -666,11 +727,11 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM2 GPIO Configuration + /**TIM2 GPIO Configuration PB10 ------> TIM2_CH3 - PB11 ------> TIM2_CH4 + PB11 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -688,11 +749,11 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE BEGIN TIM4_MspPostInit 0 */ /* USER CODE END TIM4_MspPostInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM4 GPIO Configuration + /**TIM4 GPIO Configuration PB7 ------> TIM4_CH2 - PB8 ------> TIM4_CH3 + PB8 ------> TIM4_CH3 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -800,11 +861,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -824,11 +885,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -859,10 +920,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); @@ -877,10 +938,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); @@ -905,11 +966,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -957,10 +1018,10 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); @@ -1000,12 +1061,12 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_RCC_SAI1_CLK_ENABLE(); } SAI1_client ++; - - /**SAI1_A_Block_A GPIO Configuration + + /**SAI1_A_Block_A GPIO Configuration PE2 ------> SAI1_MCLK_A PE4 ------> SAI1_FS_A PE5 ------> SAI1_SCK_A - PE6 ------> SAI1_SD_A + PE6 ------> SAI1_SD_A */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1023,9 +1084,9 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_RCC_SAI1_CLK_ENABLE(); } SAI1_client ++; - - /**SAI1_B_Block_B GPIO Configuration - PE3 ------> SAI1_SD_B + + /**SAI1_B_Block_B GPIO Configuration + PE3 ------> SAI1_SD_B */ GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -1045,15 +1106,15 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) SAI1_client --; if (SAI1_client == 0) { - /* Peripheral clock disable */ + /* Peripheral clock disable */ __HAL_RCC_SAI1_CLK_DISABLE(); } - - /**SAI1_A_Block_A GPIO Configuration + + /**SAI1_A_Block_A GPIO Configuration PE2 ------> SAI1_MCLK_A PE4 ------> SAI1_FS_A PE5 ------> SAI1_SCK_A - PE6 ------> SAI1_SD_A + PE6 ------> SAI1_SD_A */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); @@ -1066,9 +1127,9 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) /* Peripheral clock disable */ __HAL_RCC_SAI1_CLK_DISABLE(); } - - /**SAI1_B_Block_B GPIO Configuration - PE3 ------> SAI1_SD_B + + /**SAI1_B_Block_B GPIO Configuration + PE3 ------> SAI1_SD_B */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3); diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c index 2fc0793b0e..7c46b34cef 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c @@ -77,7 +77,7 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_FS; /* USER CODE END EV */ /******************************************************************************/ -/* Cortex-M4 Processor Interruption and Exception Handlers */ +/* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index e49b1ee9fb..f6d822573b 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -308,6 +308,16 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "Enable DAC1" + default n + endif + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC diff --git a/bsp/stm32/stm32l476-st-nucleo/README.md b/bsp/stm32/stm32l476-st-nucleo/README.md index e1784c3855..90ea72296a 100644 --- a/bsp/stm32/stm32l476-st-nucleo/README.md +++ b/bsp/stm32/stm32l476-st-nucleo/README.md @@ -1,113 +1,104 @@ -# NUCLEO-L476RG 开发板的 BSP 说明 +# STM32L476-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 ST 官方 (64)NUCLEO-L476RG 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32L476RG @80MHz, 1024KB FLASH, 128KB RAM -主要内容如下： +The STM32L476xx devices are the ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32L476xx devices embed high-speed memories (Flash memory up to 1 Mbyte, up to 128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. +The STM32L476xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. +The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). +In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter. +They also feature standard and advanced communication interfaces. +The STM32L476xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V VDD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes allows the design of low-power applications. +Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. +The STM32L476xx family offers six packages from 64-pin to 144-pin packages. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Ultra-low-power with FlexPowerControl + - 1.71 V to 3.6 V power supply + - -40 °C to 85/105/125 °C temperature range + - 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers + - 30 nA Shutdown mode (5 wakeup pins) + - 120 nA Standby mode (5 wakeup pins) + - 420 nA Standby mode with RTC + - 1.1 μA Stop 2 mode, 1.4 μA with RTC + - 100 μA/MHz run mode (LDO Mode) + - 39 μA/MHz run mode (@3.3 V SMPS Mode) + - Batch acquisition mode (BAM) + - 4 μs wakeup from Stop mode + - Brown out reset (BOR) + - Interconnect matrix +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions +- Performance benchmark + - 1.25 DMIPS/MHz (Drystone 2.1) + - 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz) +- Energy benchmark + - 294 ULPMark™ CP score + - 106 ULPMark™ PP score +- Clock Sources + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- RTC with HW calendar, alarms and calibration +- LCD 8× 40 or 4× 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer -对于 NUCLEO-L476RG，内核是 Cortex-M4，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，mirco USB 接口，可数的外设，Arduino™ nano 兼容的接口。 +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 3x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps + - 2x 12-bit DAC output channels, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 20x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 3x SPIs (and 1x Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ +- All packages are ECOPACK2® compliant -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32L476RG，主频 80MHz，1024KB FLASH ，128KB RAM（96+32）。 -- 常用外设 - - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 黄绿色) - - 按键：1个，复位按键(B1)。 -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 -- 调试接口：板载 ST-LINK/V2-1 调试器。 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32L476RG ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32l476rg.html#documentation) | STM32L476RG datasheet and other resources | -开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L476RG](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-l476rg.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| 板载 ST-LINK 转串口 | 支持 | UART2 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | | -| UART | 支持 | UART2 | -| IIC | 支持 | 软件模拟 | -| RTC | 支持 | 支持外部晶振和内部低速时钟 | -| SPI | 支持 | SPI1/2/3 | -| ADC | 支持 | ADC1_IN1/ADC2_IN2/ADC3_IN3 | -| TIME | 支持 | TIME15/16/17 | -| **扩展模块** | **支持情况** | **备注** | -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 LD3 常亮、黄绿色 LD2 会周期性闪烁。 - -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Jan 9 2019 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号或将 BSP 中串口的 GPIO 速率调低 - -## 联系人信息 - -维护人: - -- [GW] 邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32l476-st-nucleo/README_zh.md b/bsp/stm32/stm32l476-st-nucleo/README_zh.md new file mode 100644 index 0000000000..e1784c3855 --- /dev/null +++ b/bsp/stm32/stm32l476-st-nucleo/README_zh.md @@ -0,0 +1,113 @@ +# NUCLEO-L476RG 开发板的 BSP 说明 + +## 简介 + +本文档为 ST 官方 (64)NUCLEO-L476RG 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +对于 NUCLEO-L476RG，内核是 Cortex-M4，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，mirco USB 接口，可数的外设，Arduino™ nano 兼容的接口。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L476RG，主频 80MHz，1024KB FLASH ，128KB RAM（96+32）。 +- 常用外设 + - LED：3个，USB communication(LD1 双色),power LED(LD3 红色),user LED(LD2 黄绿色) + - 按键：1个，复位按键(B1)。 +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 +- 调试接口：板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L476RG](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-l476rg.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| 板载 ST-LINK 转串口 | 支持 | UART2 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART2 | +| IIC | 支持 | 软件模拟 | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| SPI | 支持 | SPI1/2/3 | +| ADC | 支持 | ADC1_IN1/ADC2_IN2/ADC3_IN3 | +| TIME | 支持 | TIME15/16/17 | +| **扩展模块** | **支持情况** | **备注** | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 LD3 常亮、黄绿色 LD2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Jan 9 2019 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号或将 BSP 中串口的 GPIO 速率调低 + +## 联系人信息 + +维护人: + +- [GW] 邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32l496-st-nucleo/README.md b/bsp/stm32/stm32l496-st-nucleo/README.md index 156449a74d..c31510a214 100644 --- a/bsp/stm32/stm32l496-st-nucleo/README.md +++ b/bsp/stm32/stm32l496-st-nucleo/README.md @@ -1,107 +1,103 @@ -# NUCLEO-L496ZG 开发板的 BSP 说明 +# STM32L496-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 ST 官方 (144)NUCLEO-L496ZG 开发板的 BSP (板级支持包) 说明。 +## MCU: STM32L496ZG @80MHz, 1024KB FLASH, 320KB RAM -主要内容如下： +The STM32L496xx devices are the ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32L496xx devices embed high-speed memories (up to 1 Mbyte of Flash memory, 320 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. +The STM32L496xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. +The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). +In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter. +They also feature standard and advanced communication interfaces. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Ultra-low-power with FlexPowerControl + - 1.71 V to 3.6 V power supply + - -40 °C to 85/125 °C temperature range + - 320 nA in VBAT mode: supply for RTC and 32x32-bit backup registers + - 25 nA Shutdown mode (5 wakeup pins) + - 108 nA Standby mode (5 wakeup pins) + - 426 nA Standby mode with RTC + - 2.57 µA Stop 2 mode, 2.86 µA Stop 2 with RTC + - 91 µA/MHz run mode (LDO Mode) + - 37 μA/MHz run mode (@3.3 V SMPS Mode) + - Batch acquisition mode (BAM) + - 5 µs wakeup from Stop mode + - Brown out reset (BOR) in all modes except shutdown + - Interconnect matrix +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100 DMIPS and DSP instructions +- Performance benchmark + - 1.25 DMIPS/MHz (Drystone 2.1) + - 273.55 Coremark® (3.42 Coremark/MHz @ 80 MHz) +- Energy benchmark + - 279 ULPMark™ CP score + - 80.2 ULPMark™ PP score +- 16 x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2 x 16-bit basic, 2 x low-power 16-bit timers (available in Stop mode), 2 x watchdogs, SysTick timer +- RTC with HW calendar, alarms and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Dedicated Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D) +- 8- to 14-bit camera interface up to 32 MHz (black&white) or 10 MHz (color) +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - 320 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Dual-flash Quad SPI memory interface -NUCLEO-L496ZG 是 ST 公司推出的一款针对 STM32L4 系列设计的 Cortex-M4 Nucleo-144 开发板，支持 mbed，兼容 Arduino、还带有ST Zio和 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 +- Clock Sources + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy) + - Internal 48 MHz with clock recovery + - 3 PLLs for system clock, USB, audio, ADC +- LCD 8 × 40 or 4 × 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 4 x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 3 × 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps + - 2 x 12-bit DAC output channels, low-power sample and hold + - 2 x operational amplifiers with built-in PGA + - 2 x ultra-low-power comparators +- 20 x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2 x SAIs (serial audio interface) + - 4 x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5 x U(S)ARTs (ISO 7816, LIN, IrDA, modem) + - 1 x LPUART + - 3 x SPIs (4 x SPIs with the Quad SPI) + - 2 x CAN (2.0B Active) and SDMMC + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ -开发板外观如下图所示： - -该开发板常用 **板载资源** 如下： +## Read more -- MCU：STM32L496ZG，主频 80MHz，1MB FLASH ，320KB RAM -- 常用外设 - - LED：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14） - - 按键：1个，K1（PC13） -- 常用接口：USB OTG 等 -- 调试接口，标准 ST-LINK/SWD +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32L496ZG ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32l496zg.html#documentation) | STM32L496ZG datasheet and other resources | -开发板更多详细信息请参考【NUCLEO-L496ZG】 [L496ZG开发板介绍](https://www.st.com/content/st_com/zh/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l496zg.html)。 -## 外设支持 -本 BSP 目前对外设的支持情况如下： +## Maintained By -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| USB 转串口 | 支持 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | | -| UART | 支持 | LPUART1 | -## 使用说明 -使用说明分为如下两个章节： -- 快速上手 +## Translated By - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +Meco Man @ RT-Thread Community -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，蓝色的 LED2 以 500MS 周期闪烁。 - -连接开发板ST-LINK到 PC , 会发现有串口, 在终端工具里打开相应的串口（115200-8-1-N）, 复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build Oct 2 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 LPUART1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号或将 BSP 中串口的 GPIO 速率调低 - -## 联系人信息 - -维护人: - -- [super_mcu] 邮箱：<[email protected]>
\ No newline at end of file +> +> https://github.com/mysterywolf
\ No newline at end of file diff --git a/bsp/stm32/stm32l496-st-nucleo/README_zh.md b/bsp/stm32/stm32l496-st-nucleo/README_zh.md new file mode 100644 index 0000000000..d07e0e83c8 --- /dev/null +++ b/bsp/stm32/stm32l496-st-nucleo/README_zh.md @@ -0,0 +1,107 @@ +# NUCLEO-L496ZG 开发板的 BSP 说明 + +## 简介 + +本文档为 ST 官方 (144)NUCLEO-L496ZG 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-L496ZG 是 ST 公司推出的一款针对 STM32L4 系列设计的 Cortex-M4 Nucleo-144 开发板，支持 mbed，兼容 Arduino、还带有ST Zio和 ST Morpho 扩展接口，可连接微控制器的所有周边外设。 + +开发板外观如下图所示： + + + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L496ZG，主频 80MHz，1MB FLASH ，320KB RAM +- 常用外设 + - LED：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14） + - 按键：1个，K1（PC13） +- 常用接口：USB OTG 等 +- 调试接口，标准 ST-LINK/SWD + +开发板更多详细信息请参考 [L496ZG开发板介绍](https://www.st.com/content/st_com/zh/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l496zg.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | LPUART1 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，蓝色的 LED2 以 500MS 周期闪烁。 + +连接开发板ST-LINK到 PC , 会发现有串口, 在终端工具里打开相应的串口（115200-8-1-N）, 复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Oct 2 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 LPUART1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号或将 BSP 中串口的 GPIO 速率调低 + +## 联系人信息 + +维护人: + +- [super_mcu] 邮箱：<[email protected]>
\ No newline at end of file diff --git a/bsp/stm32/stm32mp157a-st-discovery/.config b/bsp/stm32/stm32mp157a-st-discovery/.config index 01ca2120fa..5715750c67 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/.config +++ b/bsp/stm32/stm32mp157a-st-discovery/.config @@ -123,6 +123,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -199,12 +200,15 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -231,6 +235,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -243,7 +248,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -265,6 +270,11 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # # security packages @@ -273,6 +283,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -289,6 +300,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set # # tools packages @@ -307,6 +320,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -318,6 +334,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -330,6 +347,19 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -367,6 +397,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set @@ -374,6 +405,17 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set # # miscellaneous packages @@ -403,13 +445,20 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32MP1=y @@ -427,6 +476,10 @@ CONFIG_BSP_USING_STLINK_TO_USART=y # CONFIG_BSP_USING_PWR is not set # CONFIG_BSP_USING_RCC is not set # CONFIG_BSP_USING_OPENAMP is not set +# CONFIG_BSP_USING_RS485 is not set +# CONFIG_BSP_USING_GBE is not set +# CONFIG_BSP_USING_SDMMC is not set +# CONFIG_BSP_USING_AUDIO is not set # # On-chip Peripheral Drivers @@ -435,7 +488,6 @@ CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_WWDG is not set CONFIG_BSP_USING_UART=y # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_UART3_RX_USING_DMA is not set CONFIG_BSP_USING_UART4=y # CONFIG_BSP_UART4_RX_USING_DMA is not set # CONFIG_BSP_UART4_TX_USING_DMA is not set @@ -448,6 +500,8 @@ CONFIG_BSP_USING_UART4=y # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_HASH is not set +# CONFIG_BSP_USING_CRYP is not set # CONFIG_BSP_USING_UDID is not set # diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h index 424bdc02a2..3ba077b0b5 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h @@ -34,8 +34,8 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED #define HAL_DAC_MODULE_ENABLED /*#define HAL_DCMI_MODULE_ENABLED */ /*#define HAL_DSI_MODULE_ENABLED */ @@ -43,7 +43,7 @@ /*#define HAL_DTS_MODULE_ENABLED */ /*#define HAL_ETH_MODULE_ENABLED */ /*#define HAL_FDCAN_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ +#define HAL_HASH_MODULE_ENABLED /*#define HAL_HCD_MODULE_ENABLED */ #define HAL_HSEM_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED @@ -56,9 +56,9 @@ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ -/*#define HAL_SAI_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED /*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c index d31aa64197..3a6fac25d7 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -26,7 +26,9 @@ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ - +DMA_HandleTypeDef hdma_hash_in = {0}; +DMA_HandleTypeDef hdma_cryp_in = {0}; +DMA_HandleTypeDef hdma_cryp_out = {0}; /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ @@ -58,8 +60,7 @@ /* USER CODE END 0 */ -void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); - /** +/** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -73,10 +74,10 @@ void HAL_MspInit(void) /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ -#if !defined(BSP_USING_OPENAMP) - __HAL_RCC_SYSRAM_CLK_ENABLE(); - __HAL_RCC_RETRAM_CLK_ENABLE(); -#endif + if (IS_ENGINEERING_BOOT_MODE()) + { + __HAL_RCC_SYSRAM_CLK_ENABLE(); + } HAL_NVIC_SetPriority(RCC_WAKEUP_IRQn, 0, 0); HAL_NVIC_EnableIRQ(RCC_WAKEUP_IRQn); @@ -943,6 +944,107 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) } /** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspInit 0 */ + if (IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* USER CODE END SDMMC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDMMC1 GPIO Configuration + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + __HAL_RCC_SDMMC1_FORCE_RESET(); + __HAL_RCC_SDMMC1_RELEASE_RESET(); + + /* SDMMC1 interrupt Init */ + HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspInit 1 */ + + /* USER CODE END SDMMC1_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspDeInit 0 */ + + /* USER CODE END SDMMC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDMMC1_CLK_DISABLE(); + + /**SDMMC1 GPIO Configuration + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* SDMMC1 interrupt DeInit */ + HAL_NVIC_DisableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspDeInit 1 */ + + /* USER CODE END SDMMC1_MspDeInit 1 */ + } + +} + +/** * @brief DeInitializes I2C MSP. * @param hI2c : I2C handler * @retval None @@ -967,6 +1069,250 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c) } /** +* @brief CRC MSP Initialization +* This function configures the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC2) + { + /* USER CODE BEGIN CRC2_MspInit 0 */ + + /* USER CODE END CRC2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CRC2_CLK_ENABLE(); + /* USER CODE BEGIN CRC2_MspInit 1 */ + + /* USER CODE END CRC2_MspInit 1 */ + } + +} + +/** +* @brief CRC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC2) + { + /* USER CODE BEGIN CRC2_MspDeInit 0 */ + + /* USER CODE END CRC2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC2_CLK_DISABLE(); + /* USER CODE BEGIN CRC2_MspDeInit 1 */ + + /* USER CODE END CRC2_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hrng->Instance==RNG2) + { + /* USER CODE BEGIN RNG2_MspInit 0 */ + + /* USER CODE END RNG2_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG2; + PeriphClkInit.Rng2ClockSelection = RCC_RNG2CLKSOURCE_CSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG2_CLK_ENABLE(); + /* USER CODE BEGIN RNG2_MspInit 1 */ + + /* USER CODE END RNG2_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG2) + { + /* USER CODE BEGIN RNG2_MspDeInit 0 */ + + /* USER CODE END RNG2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG2_CLK_DISABLE(); + /* USER CODE BEGIN RNG2_MspDeInit 1 */ + + /* USER CODE END RNG2_MspDeInit 1 */ + } + +} + +/** +* @brief HASH MSP Initialization +* This function configures the hardware resources used in this example +* @param hhash: HASH handle pointer +* @retval None +*/ +void HAL_HASH_MspInit(HASH_HandleTypeDef* hhash) +{ + /* USER CODE BEGIN HASH2_MspInit 0 */ + /* USER CODE END HASH2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_HASH2_CLK_ENABLE(); + /* USER CODE BEGIN HASH2_MspInit 1 */ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_hash_in.Instance = DMA2_Stream7; + hdma_hash_in.Init.Request = DMA_REQUEST_HASH2_IN; + hdma_hash_in.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_hash_in.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_hash_in.Init.MemInc = DMA_MINC_ENABLE; + hdma_hash_in.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_hash_in.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_hash_in.Init.Mode = DMA_NORMAL; + hdma_hash_in.Init.Priority = DMA_PRIORITY_HIGH; + hdma_hash_in.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_hash_in.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL; + hdma_hash_in.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_hash_in.Init.PeriphBurst = DMA_PBURST_SINGLE; + + if (HAL_DMA_DeInit(&hdma_hash_in) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_hash_in) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hhash,hdmain,hdma_hash_in); + /* USER CODE END HASH2_MspInit 1 */ + +} + +/** +* @brief HASH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hhash: HASH handle pointer +* @retval None +*/ +void HAL_HASH_MspDeInit(HASH_HandleTypeDef* hhash) +{ + /* USER CODE BEGIN HASH2_MspDeInit 0 */ + + /* USER CODE END HASH2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_HASH2_CLK_DISABLE(); + /* USER CODE BEGIN HASH2_MspDeInit 1 */ + + /* USER CODE END HASH2_MspDeInit 1 */ + +} + +#if defined (CRYP1) || defined (CRYP2) +void HAL_CRYP_MspInit(CRYP_HandleTypeDef* hcryp) +{ + if(hcryp->Instance==CRYP2) + { + /* Peripheral clock enable */ + __HAL_RCC_CRYP2_CLK_ENABLE(); + __HAL_RCC_DMAMUX_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_cryp_in.Instance = DMA2_Stream6; + hdma_cryp_in.Init.Request = DMA_REQUEST_CRYP2_IN; + hdma_cryp_in.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_cryp_in.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_cryp_in.Init.MemInc = DMA_MINC_ENABLE; + hdma_cryp_in.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_cryp_in.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_cryp_in.Init.Mode = DMA_NORMAL; + hdma_cryp_in.Init.Priority = DMA_PRIORITY_HIGH; + hdma_cryp_in.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_DeInit(&hdma_cryp_in) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_cryp_in) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hcryp,hdmain,hdma_cryp_in); + + hdma_cryp_out.Instance = DMA2_Stream5; + hdma_cryp_out.Init.Request = DMA_REQUEST_CRYP2_OUT; + hdma_cryp_out.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_cryp_out.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_cryp_out.Init.MemInc = DMA_MINC_ENABLE; + hdma_cryp_out.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_cryp_out.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_cryp_out.Init.Mode = DMA_NORMAL; + hdma_cryp_out.Init.Priority = DMA_PRIORITY_VERY_HIGH; + hdma_cryp_out.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_DeInit(&hdma_cryp_out) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_cryp_out) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hcryp,hdmaout,hdma_cryp_out); + + /* USER CODE BEGIN CRYP_MspInit 1 */ + + /* USER CODE END CRYP_MspInit 1 */ + } +} + +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef* hcryp) +{ + + if(hcryp->Instance==CRYP2) + { + /* USER CODE BEGIN CRYP_MspDeInit 0 */ + + /* USER CODE END CRYP_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRYP2_CLK_DISABLE(); + + /* Peripheral DMA DeInit*/ + HAL_DMA_DeInit(hcryp->hdmain); + HAL_DMA_DeInit(hcryp->hdmaout); + } + /* USER CODE BEGIN CRYP_MspDeInit 1 */ + + /* USER CODE END CRYP_MspDeInit 1 */ + +} +#endif +/** * @brief This function is executed in case of error occurrence. * @retval None */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig index 2ea8df97ab..9191443847 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig +++ b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig @@ -50,7 +50,37 @@ menu "Onboard Peripheral Drivers" config RS485_UART_DEVICE_NAME string "the uart name for rs485" default "uart3" + endif + + config BSP_USING_GBE + bool "Enable Ethernet" + default n + select RT_USING_LWIP + + config BSP_USING_SDMMC + bool "Enable SDMMC (SD card)" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + + menuconfig BSP_USING_AUDIO + bool "Enable Audio Device" + select RT_USING_AUDIO + select BSP_USING_PMIC + select BSP_USING_SDMMC + select BSP_USING_I2C + select BSP_USING_I2C4 + default n + + if BSP_USING_AUDIO + config BSP_USING_AUDIO_PLAY + bool "Enable Audio Play" + default y + config BSP_USING_AUDIO_RECORD + bool "Enable Audio Record" + default n endif endmenu @@ -196,7 +226,7 @@ menu "On-chip Peripheral Drivers" range 1 176 default 117 endif - menuconfig BSP_USING_I2C3 + menuconfig BSP_USING_I2C3 bool "Enable I2C3 BUS (software simulation)" default n if BSP_USING_I2C3 @@ -210,6 +240,21 @@ menu "On-chip Peripheral Drivers" range 1 191 default 181 endif + menuconfig BSP_USING_I2C4 + bool "Enable I2C4 BUS (software simulation)" + default n + if BSP_USING_I2C4 + comment "Notice: PD12 --> 60; PF15 --> 95" + config BSP_I2C4_SCL_PIN + int "i2c4 scl pin number" + range 1 191 + default 60 + config BSP_I2C4_SDA_PIN + int "I2C4 sda pin number" + range 1 191 + default 95 + endif + endif menuconfig BSP_USING_SPI diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/SConscript b/bsp/stm32/stm32mp157a-st-discovery/board/SConscript index a99f95d786..f1de10714b 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/SConscript +++ b/bsp/stm32/stm32mp157a-st-discovery/board/SConscript @@ -40,6 +40,23 @@ if GetDepend(['BSP_USING_PMIC']): if GetDepend(['BSP_USING_RS485']): src += Glob('ports/drv_rs485.c') +if GetDepend(['BSP_USING_GBE']): + src += Glob('ports/drv_eth.c') + +if GetDepend(['BSP_USING_SDMMC']): + src += Glob('ports/drv_sdio.c') + +if GetDepend(['BSP_USING_AUDIO']): + src += Glob('ports/audio/drv_cs42l51.c') + src += Glob('ports/audio/drv_sound.c') + src += Glob('ports/audio/audio_play.c') + +if GetDepend(['BSP_USING_AUDIO_RECORD']): + src += Glob('ports/audio/drv_mic.c') + +if GetDepend(['(BSP_USING_RNG)']) or GetDepend(['(BSP_USING_HASH)']) or GetDepend(['(BSP_USING_CRC)']) or GetDepend(['BSP_USING_CRYP']): + src += Glob('ports/crypto/crypto_sample.c') + if GetDepend(['BSP_USING_OPENAMP']): src += Glob('CubeMX_Config/CM4/Src/ipcc.c') src += Glob('CubeMX_Config/CM4/Src/openamp.c') @@ -58,6 +75,7 @@ if GetDepend(['BSP_USING_OPENAMP']): path = [cwd] path += [cwd + '/CubeMX_Config/CM4/Inc'] path += [cwd + '/ports'] +path += [cwd + '/ports/audio'] if GetDepend(['BSP_USING_OPENAMP']): path += [cwd + '/ports/OpenAMP'] diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/board.h b/bsp/stm32/stm32mp157a-st-discovery/board/board.h index 23fac89b39..2472d96400 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/board.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/board.h @@ -23,27 +23,24 @@ extern "C" { #endif #define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000) -#if defined(BSP_USING_OPENAMP) -#define STM32_FLASH_SIZE (64 * 1024) -#else -#define STM32_FLASH_SIZE (256 * 1024) -#endif +#define STM32_FLASH_SIZE (192 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE (64) +#define STM32_SRAM_END (0x10030000 + 64 * 1024) - -#if defined(BSP_USING_OPENAMP) -#define STM32_SRAM_BEGIN (uint32_t)0x10020000 +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) #else -#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000 +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) #endif -#define STM32_SRAM_SIZE (64) -#define STM32_SRAM_END (STM32_SRAM_BEGIN + (STM32_SRAM_SIZE * 1024)) - -#define HEAP_BEGIN STM32_SRAM_BEGIN #define HEAP_END STM32_SRAM_END -#define HEAP_END STM32_SRAM_END - void SystemClock_Config(void); extern void _Error_Handler(char *s, int num); @@ -53,4 +50,3 @@ extern void _Error_Handler(char *s, int num); #endif #endif - diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.icf b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.icf index 543a8a37d2..de9f6960b4 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.icf @@ -5,7 +5,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; /*-Memory Regions-*/ define symbol __ICFEDIT_region_text_start__ = 0x10000000; -define symbol __ICFEDIT_region_text_end__ = 0x1001FFFF; +define symbol __ICFEDIT_region_text_end__ = 0x1002FFFF; define symbol __ICFEDIT_region_data_start__ = 0x10030000; define symbol __ICFEDIT_region_data_end__ = 0x1003FFFF; /*-Sizes-*/ @@ -27,11 +27,6 @@ define symbol __OPENAMP_region_size__ = 0x8000; export symbol __OPENAMP_region_start__; export symbol __OPENAMP_region_size__; -define symbol __SDMMC_region_start__ = 0x10048000; -define symbol __SDMMC_region_size__ = 0x1FFFF; -export symbol __SDMMC_region_start__; -export symbol __SDMMC_region_size__; - define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct index df7bcadf06..a64b8cc98b 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.sct @@ -8,28 +8,20 @@ LR_VECTORS 0x00000000 0x00000400 { ; load region size_region } } -LR_IROM1 0x10000000 0x00020000 { ; load region size_region - ER_IROM1 0x10000000 0x00020000 { ; load address = execution address +LR_IROM1 0x10000000 0x00030000 { ; load region size_region + ER_IROM1 0x10000000 0x00030000 { ; load address = execution address *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } - RW_IRAM1 0x10020000 0x00050000 { ; RW data + RW_IRAM1 0x10030000 0x00010000 { ; RW data .ANY (+RW +ZI) } -; RW_IRAM2 0x10020000 0x00020000 { ; RW data -; .ANY (+RW +ZI) -; } -; RW_IRAM3 0x10040000 0x00010000 { ; RW data -; .ANY (+RW +ZI) -; } -; RW_IRAM4 0x10050000 0x00010000 { ; RW data -; .ANY (+RW +ZI) -; } -; ***** To uncomment these 4 lines if OPENAMP used ***** -; *** Create region for OPENAMP *** + + +; ***** Create region for OPENAMP ***** +; *** These 4 lines can be commented if OPENAMP is not used ***** .resource_table +0 ALIGN 4 { ; resource table *(.resource_table) - } - __OpenAMP_SHMEM__ 0x10050000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP + } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c new file mode 100644 index 0000000000..315f6320d5 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-11-24 thread-liu first version + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include <dfs_posix.h> + +#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC) +#define BUFSZ 1024 +#define SOUND_DEVICE_NAME "sound0" +static rt_device_t snd_dev; + +struct RIFF_HEADER_DEF +{ + char riff_id[4]; // 'R','I','F','F' + uint32_t riff_size; + char riff_format[4]; // 'W','A','V','E' +}; + +struct WAVE_FORMAT_DEF +{ + uint16_t FormatTag; + uint16_t Channels; + uint32_t SamplesPerSec; + uint32_t AvgBytesPerSec; + uint16_t BlockAlign; + uint16_t BitsPerSample; +}; + +struct FMT_BLOCK_DEF +{ + char fmt_id[4]; // 'f','m','t',' ' + uint32_t fmt_size; + struct WAVE_FORMAT_DEF wav_format; +}; + +struct DATA_BLOCK_DEF +{ + char data_id[4]; // 'R','I','F','F' + uint32_t data_size; +}; + +struct wav_info +{ + struct RIFF_HEADER_DEF header; + struct FMT_BLOCK_DEF fmt_block; + struct DATA_BLOCK_DEF data_block; +}; + +int wavplay_sample(int argc, char **argv) +{ + int fd = -1; + uint8_t *buffer = NULL; + struct wav_info *info = NULL; + struct rt_audio_caps caps = {0}; + + if (argc != 2) + { + rt_kprintf("Usage:\n"); + rt_kprintf("wavplay_sample song.wav\n"); + return 0; + } + + fd = open(argv[1], O_WRONLY); + if (fd < 0) + { + rt_kprintf("open file failed!\n"); + goto __exit; + } + + buffer = rt_malloc(BUFSZ); + if (buffer == RT_NULL) + goto __exit; + + info = (struct wav_info *) rt_malloc(sizeof * info); + if (info == RT_NULL) + goto __exit; + + if (read(fd, &(info->header), sizeof(struct RIFF_HEADER_DEF)) <= 0) + goto __exit; + if (read(fd, &(info->fmt_block), sizeof(struct FMT_BLOCK_DEF)) <= 0) + goto __exit; + if (read(fd, &(info->data_block), sizeof(struct DATA_BLOCK_DEF)) <= 0) + goto __exit; + + rt_kprintf("wav information:\n"); + rt_kprintf("samplerate %d\n", info->fmt_block.wav_format.SamplesPerSec); + rt_kprintf("channel %d\n", info->fmt_block.wav_format.Channels); + + snd_dev = rt_device_find(SOUND_DEVICE_NAME); + + rt_device_open(snd_dev, RT_DEVICE_OFLAG_WRONLY); + + caps.main_type = AUDIO_TYPE_OUTPUT; + caps.sub_type = AUDIO_DSP_PARAM; + caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec; + caps.udata.config.channels = info->fmt_block.wav_format.Channels; + caps.udata.config.samplebits = 16; + rt_device_control(snd_dev, AUDIO_CTL_CONFIGURE, &caps); + + while (1) + { + int length; + + length = read(fd, buffer, BUFSZ); + + if (length <= 0) + break; + + rt_device_write(snd_dev, 0, buffer, length); + } + + rt_device_close(snd_dev); + +__exit: + + if (fd >= 0) + close(fd); + + if (buffer) + rt_free(buffer); + + if (info) + rt_free(info); + + return 0; +} + +MSH_CMD_EXPORT(wavplay_sample, play wav file); + +#endif + +#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC) && defined(BSP_USING_AUDIO_RECORD) + +#define RECORD_TIME_MS 5000 +#define RECORD_SAMPLERATE 16000 +#define RECORD_CHANNEL 2 +#define RECORD_CHUNK_SZ ((RECORD_SAMPLERATE * RECORD_CHANNEL * 2) * 20 / 1000) + +#define MIC_DEVICE_NAME "mic0" +static rt_device_t mic_dev; + +struct wav_header +{ + char riff_id[4]; /* "RIFF" */ + int riff_datasize; /* RIFF chunk data size,exclude riff_id[4] and riff_datasize,total - 8 */ + char riff_type[4]; /* "WAVE" */ + char fmt_id[4]; /* "fmt " */ + int fmt_datasize; /* fmt chunk data size,16 for pcm */ + short fmt_compression_code; /* 1 for PCM */ + short fmt_channels; /* 1(mono) or 2(stereo) */ + int fmt_sample_rate; /* samples per second */ + int fmt_avg_bytes_per_sec; /* sample_rate * channels * bit_per_sample / 8 */ + short fmt_block_align; /* number bytes per sample, bit_per_sample * channels / 8 */ + short fmt_bit_per_sample; /* bits of each sample(8,16,32). */ + char data_id[4]; /* "data" */ + int data_datasize; /* data chunk size,pcm_size - 44 */ +}; + +static void wavheader_init(struct wav_header *header, int sample_rate, int channels, int datasize) +{ + memcpy(header->riff_id, "RIFF", 4); + header->riff_datasize = datasize + 44 - 8; + memcpy(header->riff_type, "WAVE", 4); + memcpy(header->fmt_id, "fmt ", 4); + header->fmt_datasize = 16; + header->fmt_compression_code = 1; + header->fmt_channels = channels; + header->fmt_sample_rate = sample_rate; + header->fmt_bit_per_sample = 16; + header->fmt_avg_bytes_per_sec = header->fmt_sample_rate * header->fmt_channels * header->fmt_bit_per_sample / 8; + header->fmt_block_align = header->fmt_bit_per_sample * header->fmt_channels / 8; + memcpy(header->data_id, "data", 4); + header->data_datasize = datasize; +} + +int wavrecord_sample(int argc, char **argv) +{ + int fd = -1; + uint8_t *buffer = NULL; + struct wav_header header; + struct rt_audio_caps caps = {0}; + int length, total_length = 0; + + if (argc != 2) + { + rt_kprintf("Usage:\n"); + rt_kprintf("wavrecord_sample file.wav\n"); + return -1; + } + + fd = open(argv[1], O_WRONLY | O_CREAT); + if (fd < 0) + { + rt_kprintf("open file for recording failed!\n"); + return -1; + } + write(fd, &header, sizeof(struct wav_header)); + + buffer = rt_malloc(RECORD_CHUNK_SZ); + if (buffer == RT_NULL) + goto __exit; + + mic_dev = rt_device_find(MIC_DEVICE_NAME); + if (mic_dev == RT_NULL) + goto __exit; + + rt_device_open(mic_dev, RT_DEVICE_OFLAG_RDONLY); + + caps.main_type = AUDIO_TYPE_INPUT; + caps.sub_type = AUDIO_DSP_PARAM; + caps.udata.config.samplerate = RECORD_SAMPLERATE; + caps.udata.config.channels = RECORD_CHANNEL; + caps.udata.config.samplebits = 16; + rt_device_control(mic_dev, AUDIO_CTL_CONFIGURE, &caps); + + while (1) + { + length = rt_device_read(mic_dev, 0, buffer, RECORD_CHUNK_SZ); + + if (length) + { + write(fd, buffer, length); + total_length += length; + } + + if ((total_length / RECORD_CHUNK_SZ) > (RECORD_TIME_MS / 20)) + break; + } + + /* write wav file head */ + wavheader_init(&header, RECORD_SAMPLERATE, RECORD_CHANNEL, total_length); + lseek(fd, 0, SEEK_SET); + write(fd, &header, sizeof(struct wav_header)); + close(fd); + + /* close audio mic device */ + rt_device_close(mic_dev); + +__exit: + if (fd >= 0) + close(fd); + + if (buffer) + rt_free(buffer); + + return 0; +} +MSH_CMD_EXPORT(wavrecord_sample, record voice to a wav file); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c new file mode 100644 index 0000000000..e0ae5f1b5e --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-02 thread-liu first version + */ + +#include "board.h" + +#if defined(BSP_USING_AUDIO) +#include <drv_cs42l51.h> + +#define DRV_DEBUG +#define LOG_TAG "drv.audio" +#include <drv_log.h> + +/* CS42L51 address */ +#define CHIP_ADDRESS 0x4A +/* reset pin, active low */ +#define CS42L51_RESET_PIN GET_PIN(G, 9) + +static uint16_t CS42L51_Device = OUT_HEADPHONE; +static struct rt_i2c_bus_device *audio_dev = RT_NULL; + +/* i2c read reg */ +static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf) +{ + struct rt_i2c_msg msg[2] = {0, 0}; + + RT_ASSERT(bus != RT_NULL); + + msg[0].addr = CHIP_ADDRESS; /* Slave address */ + msg[0].flags = RT_I2C_WR; /* Write flag */ + msg[0].buf = ® /* Slave register address */ + msg[0].len = 1; /* Number of bytes sent */ + + msg[1].addr = CHIP_ADDRESS; + msg[1].flags = RT_I2C_RD; + msg[1].len = len; + msg[1].buf = buf; + + if (rt_i2c_transfer(bus, msg, 2) == 2) + { + return RT_EOK; + } + + return RT_ERROR; +} + +/* i2c write reg */ +static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t data) +{ + rt_uint8_t buf[2]; + struct rt_i2c_msg msgs; + + RT_ASSERT(bus != RT_NULL); + + buf[0] = reg; + buf[1] = data; + + msgs.addr = CHIP_ADDRESS; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = 2; + + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + + return RT_ERROR; +} + +/** + * @brief deinitializes cs42l51 low level. + * @retval none + */ +static void cs42l51_lowlevel_deinit(void) +{ + rt_uint8_t temp = 0; + + /* Mute DAC and ADC */ + read_reg(audio_dev, CS42L51_DAC_OUT_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_DAC_OUT_CTL, (temp | 0x03)); + read_reg(audio_dev, CS42L51_ADC_INPUT, 1, &temp); + write_reg(audio_dev, CS42L51_ADC_INPUT, (temp | 0x03)); + + /* Disable soft ramp and zero cross */ + read_reg(audio_dev, CS42L51_ADC_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_ADC_CTL, (temp & 0xF0)); + + /* Set PDN to 1 */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); + + /* Set all power down bits to 1 */ + write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7F); + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E)); + + /* Power off the codec */ + rt_pin_write(CS42L51_RESET_PIN, PIN_LOW); +} + +/** + * @brief initializes cs42l51 low level. + * @retval none + */ +static void cs42l51_lowlevel_init(void) +{ + rt_uint8_t temp = 0; + + /* Initialized RESET IO */ + rt_pin_mode(CS42L51_RESET_PIN, PIN_MODE_OUTPUT); + + /* Power off the cs42l51 */ + rt_pin_write(CS42L51_RESET_PIN, PIN_LOW); + + /* wait until power supplies are stable */ + rt_thread_mdelay(10); + + /* Power on the cs42l51 */ + rt_pin_write(CS42L51_RESET_PIN, PIN_HIGH); + + /* Wait at least 500ns after reset */ + rt_thread_mdelay(1); + + /* Set the device in standby mode */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); + + /* Set all power down bits to 1 */ + write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7F); + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E)); +} + +/** + * @brief Initializes CS42L51. + * @param Device: Audio type. + * @param bus_name I2C device name. + * @param volume: Initial output volume level (from 0 (-100dB) to 100 (0dB)). + * @retval 0 if correct communication, else wrong communication + */ +static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volume) +{ + static uint8_t init_flag = 0; + rt_uint8_t temp = 0; + rt_uint8_t value = 0; + + /* check if codec is already initialized */ + if (init_flag == 0) + { + audio_dev = rt_i2c_bus_device_find(bus_name); + + if (audio_dev == RT_NULL) + { + LOG_E("%s bus not found\n", bus_name); + return -RT_ERROR; + } + /* hard reset cs42l51 */ + cs42l51_drv.reset(); + /* Wait at least 500ns after reset */ + rt_thread_mdelay(1); + /* Set the device in standby mode */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); + /* Set all power down bits to 1 */ + write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7F); + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E)); + + init_flag = 1; + } + else + { + /* Set all power down bits to 1 exept PDN to mute ADCs and DACs*/ + write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7E); + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E)); + /* Disable zero cross and soft ramp */ + read_reg(audio_dev, CS42L51_DAC_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_DAC_CTL, (temp & 0xFC)); + + /* Power control : Enter standby (PDN = 1) */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); + } + /* Mic Power and Speed Control : Auto detect on, Speed mode SSM, tri state off, MCLK divide by 2 off */ + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL, ((temp & 0x0E) | 0xA0)); + /* Interface control : Loopback off, Slave, I2S (SDIN and SOUT), Digital mix off, Mic mix off */ + write_reg(audio_dev, CS42L51_INTF_CTL, 0x0C); + /* Mic control : ADC single volume off, ADCB boost off, ADCA boost off, MicBias on AIN3B/MICIN2 pin, MicBias level 0.8xVA, MICB boost 16db, MICA boost 16dB */ + write_reg(audio_dev, CS42L51_MIC_CTL, 0x00); + /* ADC control : ADCB HPF off, ADCB HPF freeze off, ADCA HPF off, ADCA HPF freeze off, Soft ramp B off, Zero cross B off, Soft ramp A off, Zero cross A off */ + write_reg(audio_dev, CS42L51_ADC_CTL, 0x00); + /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN3A to PreAmp to PGAA, ADCB invert off, ADCA invert off, ADCB mute on, ADCA mute off */ + write_reg(audio_dev, CS42L51_ADC_INPUT, 0x32); + /* DAC output control : HP Gain to 1, Single volume control off, PCM invert signals polarity off, DAC channels mute on */ + write_reg(audio_dev, CS42L51_DAC_OUT_CTL, 0xC3); + /* DAC control : Signal processing to DAC, Freeze off, De-emphasis off, Analog output auto mute off, DAC soft ramp */ + write_reg(audio_dev, CS42L51_DAC_CTL, 0x42); + /* ALCA and PGAA Control : ALCA soft ramp disable on, ALCA zero cross disable on, PGA A Gain 0dB */ + write_reg(audio_dev, CS42L51_ALC_PGA_CTL, 0xC0); + /* ALCB and PGAB Control : ALCB soft ramp disable on, ALCB zero cross disable on, PGA B Gain 0dB */ + write_reg(audio_dev, CS42L51_ALC_PGB_CTL, 0xC0); + /* ADCA Attenuator : 0dB */ + write_reg(audio_dev, CS42L51_ADCA_ATT, 0x00); + /* ADCB Attenuator : 0dB */ + write_reg(audio_dev, CS42L51_ADCB_ATT, 0x00); + /* ADCA mixer volume control : ADCA mixer channel mute on, ADCA mixer volume 0dB */ + write_reg(audio_dev, CS42L51_ADCA_VOL, 0x80); + /* ADCB mixer volume control : ADCB mixer channel mute on, ADCB mixer volume 0dB */ + write_reg(audio_dev, CS42L51_ADCB_VOL, 0x80); + /* PCMA mixer volume control : PCMA mixer channel mute off, PCMA mixer volume 0dB */ + write_reg(audio_dev, CS42L51_PCMA_VOL, 0x00); + /* PCMB mixer volume control : PCMB mixer channel mute off, PCMB mixer volume 0dB */ + write_reg(audio_dev, CS42L51_PCMB_VOL, 0x00); + /* PCM channel mixer : AOUTA Left, AOUTB Right */ + write_reg(audio_dev, CS42L51_PCM_MIXER, 0x00); + + if(device & OUT_HEADPHONE) + { + value = VOLUME_CONVERT(volume); + /* AOUTA volume control : AOUTA volume */ + write_reg(audio_dev, CS42L51_AOUTA_VOL, value); + /* AOUTB volume control : AOUTB volume */ + write_reg(audio_dev, CS42L51_AOUTB_VOL, value); + } + + CS42L51_Device = device; + + return RT_EOK; +} + +/** + * @brief Deinitialize the audio codec. + * @param None + * @retval None + */ +static void cs42l51_deinit(void) +{ + /* Deinitialize Audio Codec interface */ + rt_uint8_t temp = 0; + + /* Mute DAC and ADC */ + read_reg(audio_dev, CS42L51_DAC_OUT_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_DAC_OUT_CTL, (temp | 0x03)); + read_reg(audio_dev, CS42L51_ADC_INPUT, 1, &temp); + write_reg(audio_dev, CS42L51_ADC_INPUT, (temp | 0x03)); + + /* Disable soft ramp and zero cross */ + read_reg(audio_dev, CS42L51_ADC_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_ADC_CTL, (temp & 0xF0)); + + /* Set PDN to 1 */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); + + /* Set all power down bits to 1 */ + write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7F); + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E)); + + /* Power off CS42L51*/ + rt_pin_write(CS42L51_RESET_PIN, PIN_LOW); +} + +/** + * @brief Verify that we have a CS42L51. + * @retval 0 if correct communication, else wrong communication + */ + +static uint32_t cs42l51_read_id(void) +{ + uint8_t temp; + + /* read cs42l51 id */ + read_reg(audio_dev, CS42L51_CHIP_REV_ID, 1, &temp); + + if ((temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) && + (temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) + { + LOG_E("device id : 0x%02x", temp); + return RT_ERROR; + } + + LOG_D("device id : 0x%02x", temp); + + return RT_EOK; +} + +/** + * @brief Start the audio Codec play feature. + * @note For this codec no Play options are required. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_play(void) +{ + rt_uint8_t temp = 0; + + switch (CS42L51_Device) + { + case OUT_HEADPHONE: + { + /* Unmute the output first */ + cs42l51_drv.set_mute(AUDIO_MUTE_OFF); + /* DAC control : Signal processing to DAC, Freeze off, De-emphasis off, Analog output auto mute off, DAC soft ramp */ + write_reg(audio_dev, CS42L51_DAC_CTL, 0x42); + /* Power control 1 : PDN_DACA, PDN_DACB disable. */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F)); + break; + } + + case IN_LINE1: + { + /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN1A to PGAA, ADCB invert off, ADCA invert off, ADCB mute off, ADCA mute off */ + write_reg(audio_dev, CS42L51_ADC_INPUT, 0x00); + /* Power control 1 : PDN_PGAA, PDN_PGAA, PDN_ADCB, PDN_ADCA disable. */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F)); + break; + } + + case IN_MIC1: + { + /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN3A to PreAmp to PGAA, ADCB invert off, ADCA invert off, ADCB mute on, ADCA mute off */ + write_reg(audio_dev, CS42L51_ADC_INPUT, 0x32); + /* Power control 1 : PDN_PGAA, PDN_ADCA disable. */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0xF5)); + /* Mic Power and Speed Control : PDN_MICA, PDN_MIC_BIAS disable. */ + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF9)); + break; + } + + case IN_MIC2: + { + /* Power control 1 : PDN_PGAB, PDN_ADCB disable. */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0xEB)); + /* Mic Power and Speed Control : PDN_MICB, PDN_MIC_BIAS disable. */ + read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); + write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF5)); + break; + } + + default: + LOG_D("error audio play mode!"); + break; + } + + /* Power control : Exit standby (PDN = 0) */ + read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0xFE)); + + return RT_EOK; +} + +/** + * @brief Pause playing on the audio codec. + * @param audio_dev: Device address on communication Bus. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_pause(void) +{ + + /* Pause the audio file playing */ + /* Mute the output first */ + return cs42l51_drv.set_mute(AUDIO_MUTE_ON); + +} + +/** + * @brief Resume playing on the audio codec. + * @param audio_dev: Device address on communication Bus. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_resume(void) +{ + /* Unmute the output */ + return cs42l51_drv.set_mute(AUDIO_MUTE_OFF); +} + +/** + * @brief Stop audio Codec playing. It powers down the codec. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_stop(void) +{ + rt_uint8_t temp = 0; + + /* Set all power down bits to 1 exept PDN to mute ADCs and DACs*/ + write_reg(audio_dev, 0x02, 0x7E); + read_reg(audio_dev, 0x03, 1, &temp); + write_reg(audio_dev, 0x03, (temp | 0x0E)); + + /* Disable zero cross and soft ramp */ + read_reg(audio_dev, 0x09, 1, &temp); + write_reg(audio_dev, 0x09, (temp & 0xFC)); + + /* Power control : Enter standby (PDN = 1) */ + read_reg(audio_dev, 0x02, 1, &temp); + write_reg(audio_dev, 0x02, (temp | 0x01)); + + return RT_EOK; +} + +/** + * @brief Set new frequency. + * @param AudioFreq: Audio frequency used to play the audio stream. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_set_frequency(uint32_t AudioFreq) +{ + return RT_EOK; +} + +/** + * @brief Set higher or lower the codec volume level. + * @param Volume: output volume level (from 0 (-100dB) to 100 (0dB)). + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_set_volume(uint8_t Volume) +{ + uint8_t convertedvol = VOLUME_CONVERT(Volume); + + /* AOUTA volume control : AOUTA volume */ + write_reg(audio_dev, CS42L51_AOUTA_VOL, convertedvol); + /* AOUTB volume control : AOUTB volume */ + write_reg(audio_dev, CS42L51_AOUTB_VOL, convertedvol); + + return RT_EOK; +} + +/** + * @brief get higher or lower the codec volume level. + * @retval value if correct communication + */ +static uint32_t cs42l51_get_volume(void) +{ + rt_uint8_t temp = 0; + + /* AOUTA volume control : AOUTA volume */ + read_reg(audio_dev, CS42L51_AOUTA_VOL, 1, &temp); + + temp = VOLUME_INVERT(temp); + + return temp; +} + +/** +* @brief Enable or disable the mute feature on the audio codec. +* @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the +* mute mode. +* @retval 0 if correct communication, else wrong communication +*/ +static uint32_t cs42l51_set_mute(uint32_t cmd) +{ + rt_uint8_t temp = 0; + + /* Read DAC output control register */ + read_reg(audio_dev, 0x08, 1, &temp); + + /* Set the Mute mode */ + if(cmd == AUDIO_MUTE_ON) + { + /* Mute DAC channels */ + write_reg(audio_dev, CS42L51_DAC_OUT_CTL, (temp | 0x03)); + } + else /* AUDIO_MUTE_OFF Disable the Mute */ + { + /* Unmute DAC channels */ + write_reg(audio_dev, CS42L51_DAC_OUT_CTL, (temp & 0xFC)); + } + + return RT_EOK; +} + +/** + * @brief Switch dynamically (while audio file is played) the output target + * (speaker, headphone, etc). + * @note This function is currently not used (only headphone output device). + * @param Output: specifies the audio output device target. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_set_output_mode(uint8_t Output) +{ + return RT_EOK; +} + +/** + * @brief Reset CS42L51 registers. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t cs42l51_reset(void) +{ + cs42l51_lowlevel_deinit(); + + cs42l51_lowlevel_init(); + + return RT_EOK; +} + +/* Audio codec driver structure initialization */ +AUDIO_DrvTypeDef cs42l51_drv = +{ + cs42l51_init, + cs42l51_deinit, + cs42l51_read_id, + + cs42l51_play, + cs42l51_pause, + cs42l51_resume, + cs42l51_stop, + + cs42l51_set_frequency, + cs42l51_set_volume, + cs42l51_get_volume, + cs42l51_set_mute, + cs42l51_set_output_mode, + cs42l51_reset, +}; + +#endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h new file mode 100644 index 0000000000..b3d7f78dca --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2020-07-02 thread-liu first version + */ + +#ifndef __DRV_CS42L51_H__ +#define __DRV_CS42L51_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + rt_err_t (*init)(uint16_t , const char *, uint8_t); + void (*deinit)(void); + uint32_t (*read_id)(void); + uint32_t (*play)(void); + uint32_t (*pause)(void); + uint32_t (*resume)(void); + uint32_t (*stop)(void); + uint32_t (*set_frequency)(uint32_t); + uint32_t (*set_volume)(uint8_t); + uint32_t (*get_volume)(void); + uint32_t (*set_mute)(uint32_t); + uint32_t (*set_output_mode)(uint8_t); + uint32_t (*reset)(void); +}AUDIO_DrvTypeDef; + +extern AUDIO_DrvTypeDef cs42l51_drv; + +/* CS42L51 register space */ +#define CS42L51_CHIP_ID 0x1B +#define CS42L51_CHIP_REV_A 0x00 +#define CS42L51_CHIP_REV_B 0x01 + +#define CS42L51_CHIP_REV_ID 0x01 +#define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b)) + +#define CS42L51_POWER_CTL1 0x02 +#define CS42L51_POWER_CTL1_PDN_DACB (1<<6) +#define CS42L51_POWER_CTL1_PDN_DACA (1<<5) +#define CS42L51_POWER_CTL1_PDN_PGAB (1<<4) +#define CS42L51_POWER_CTL1_PDN_PGAA (1<<3) +#define CS42L51_POWER_CTL1_PDN_ADCB (1<<2) +#define CS42L51_POWER_CTL1_PDN_ADCA (1<<1) +#define CS42L51_POWER_CTL1_PDN (1<<0) + +#define CS42L51_MIC_POWER_CTL 0x03 +#define CS42L51_MIC_POWER_CTL_AUTO (1<<7) +#define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) +#define CS42L51_QSM_MODE 3 +#define CS42L51_HSM_MODE 2 +#define CS42L51_SSM_MODE 1 +#define CS42L51_DSM_MODE 0 +#define CS42L51_MIC_POWER_CTL_3ST_SP (1<<4) +#define CS42L51_MIC_POWER_CTL_PDN_MICB (1<<3) +#define CS42L51_MIC_POWER_CTL_PDN_MICA (1<<2) +#define CS42L51_MIC_POWER_CTL_PDN_BIAS (1<<1) +#define CS42L51_MIC_POWER_CTL_MCLK_DIV2 (1<<0) + +#define CS42L51_INTF_CTL 0x04 +#define CS42L51_INTF_CTL_LOOPBACK (1<<7) +#define CS42L51_INTF_CTL_MASTER (1<<6) +#define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) +#define CS42L51_DAC_DIF_LJ24 0x00 +#define CS42L51_DAC_DIF_I2S 0x01 +#define CS42L51_DAC_DIF_RJ24 0x02 +#define CS42L51_DAC_DIF_RJ20 0x03 +#define CS42L51_DAC_DIF_RJ18 0x04 +#define CS42L51_DAC_DIF_RJ16 0x05 +#define CS42L51_INTF_CTL_ADC_I2S (1<<2) +#define CS42L51_INTF_CTL_DIGMIX (1<<1) +#define CS42L51_INTF_CTL_MICMIX (1<<0) + +#define CS42L51_MIC_CTL 0x05 +#define CS42L51_MIC_CTL_ADC_SNGVOL (1<<7) +#define CS42L51_MIC_CTL_ADCD_DBOOST (1<<6) +#define CS42L51_MIC_CTL_ADCA_DBOOST (1<<5) +#define CS42L51_MIC_CTL_MICBIAS_SEL (1<<4) +#define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) +#define CS42L51_MIC_CTL_MICB_BOOST (1<<1) +#define CS42L51_MIC_CTL_MICA_BOOST (1<<0) + +#define CS42L51_ADC_CTL 0x06 +#define CS42L51_ADC_CTL_ADCB_HPFEN (1<<7) +#define CS42L51_ADC_CTL_ADCB_HPFRZ (1<<6) +#define CS42L51_ADC_CTL_ADCA_HPFEN (1<<5) +#define CS42L51_ADC_CTL_ADCA_HPFRZ (1<<4) +#define CS42L51_ADC_CTL_SOFTB (1<<3) +#define CS42L51_ADC_CTL_ZCROSSB (1<<2) +#define CS42L51_ADC_CTL_SOFTA (1<<1) +#define CS42L51_ADC_CTL_ZCROSSA (1<<0) + +#define CS42L51_ADC_INPUT 0x07 +#define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) +#define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) +#define CS42L51_ADC_INPUT_INV_ADCB (1<<3) +#define CS42L51_ADC_INPUT_INV_ADCA (1<<2) +#define CS42L51_ADC_INPUT_ADCB_MUTE (1<<1) +#define CS42L51_ADC_INPUT_ADCA_MUTE (1<<0) + +#define CS42L51_DAC_OUT_CTL 0x08 +#define CS42L51_DAC_OUT_CTL_HP_GAIN(x) (((x)&7)<<5) +#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL (1<<4) +#define CS42L51_DAC_OUT_CTL_INV_PCMB (1<<3) +#define CS42L51_DAC_OUT_CTL_INV_PCMA (1<<2) +#define CS42L51_DAC_OUT_CTL_DACB_MUTE (1<<1) +#define CS42L51_DAC_OUT_CTL_DACA_MUTE (1<<0) + +#define CS42L51_DAC_CTL 0x09 +#define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6) +#define CS42L51_DAC_CTL_FREEZE (1<<5) +#define CS42L51_DAC_CTL_DEEMPH (1<<3) +#define CS42L51_DAC_CTL_AMUTE (1<<2) +#define CS42L51_DAC_CTL_DACSZ(x) (((x)&3)<<0) + +#define CS42L51_ALC_PGA_CTL 0x0A +#define CS42L51_ALC_PGB_CTL 0x0B +#define CS42L51_ALC_PGX_ALCX_SRDIS (1<<7) +#define CS42L51_ALC_PGX_ALCX_ZCDIS (1<<6) +#define CS42L51_ALC_PGX_PGX_VOL(x) (((x)&0x1f)<<0) + +#define CS42L51_ADCA_ATT 0x0C +#define CS42L51_ADCB_ATT 0x0D + +#define CS42L51_ADCA_VOL 0x0E +#define CS42L51_ADCB_VOL 0x0F +#define CS42L51_PCMA_VOL 0x10 +#define CS42L51_PCMB_VOL 0x11 +#define CS42L51_MIX_MUTE_ADCMIX (1<<7) +#define CS42L51_MIX_VOLUME(x) (((x)&0x7f)<<0) + +#define CS42L51_BEEP_FREQ 0x12 +#define CS42L51_BEEP_VOL 0x13 +#define CS42L51_BEEP_CONF 0x14 + +#define CS42L51_TONE_CTL 0x15 +#define CS42L51_TONE_CTL_TREB(x) (((x)&0xf)<<4) +#define CS42L51_TONE_CTL_BASS(x) (((x)&0xf)<<0) + +#define CS42L51_AOUTA_VOL 0x16 +#define CS42L51_AOUTB_VOL 0x17 +#define CS42L51_PCM_MIXER 0x18 +#define CS42L51_LIMIT_THRES_DIS 0x19 +#define CS42L51_LIMIT_REL 0x1A +#define CS42L51_LIMIT_ATT 0x1B +#define CS42L51_ALC_EN 0x1C +#define CS42L51_ALC_REL 0x1D +#define CS42L51_ALC_THRES 0x1E +#define CS42L51_NOISE_CONF 0x1F + +#define CS42L51_STATUS 0x20 +#define CS42L51_STATUS_SP_CLKERR (1<<6) +#define CS42L51_STATUS_SPEA_OVFL (1<<5) +#define CS42L51_STATUS_SPEB_OVFL (1<<4) +#define CS42L51_STATUS_PCMA_OVFL (1<<3) +#define CS42L51_STATUS_PCMB_OVFL (1<<2) +#define CS42L51_STATUS_ADCA_OVFL (1<<1) +#define CS42L51_STATUS_ADCB_OVFL (1<<0) + +#define CS42L51_CHARGE_FREQ 0x21 +#define CS42L51_FIRSTREG 0x01 + +enum play_type { + NONE, + OUT_HEADPHONE, + IN_MIC1, + IN_MIC2, + IN_LINE1, + IN_LINE2, + IN_LINE3, +}; + +/* + * Hack: with register 0x21, it makes 33 registers. Looks like someone in the + * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using + * 32 regs + */ +#define CS42L51_LASTREG 0x20 +#define CS42L51_NUMREGS (CS42L51_LASTREG - CS42L51_FIRSTREG + 1) + +#define VOLUME_CONVERT(Volume) ((Volume >= 100) ? 0 : ((uint8_t)(((Volume * 2) + 56)))) +#define VOLUME_INVERT(Volume) (((Volume) == 0U) ? 100U : ((uint8_t)(((Volume) - 56U) / 2U))) + +/* MUTE commands */ +#define AUDIO_MUTE_ON 1 +#define AUDIO_MUTE_OFF 0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c new file mode 100644 index 0000000000..20e98d4826 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-31 Zero-Free first implementation + * 2020-07-02 thread-liu Porting for STM32MP1 + */ + +#include <board.h> + +#if defined(BSP_USING_AUDIO_RECORD) + +#include "drv_cs42l51.h" + +//#define DRV_DEBUG +#define DBG_TAG "drv.audio" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + +#define MIC_BUS_NAME "i2c4" + +/* SYSRAM */ +#define RX_FIFO_SIZE (4096) +#if defined(__CC_ARM) || defined(__CLANG_ARM) +rt_uint8_t MIC_RX_FIFO[RX_FIFO_SIZE] __attribute__((at(0x2FFC2000))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFC2000 +rt_uint8_t MIC_RX_FIFO[RX_FIFO_SIZE]; +#elif defined ( __GNUC__ ) +rt_uint8_t MIC_RX_FIFO[RX_FIFO_SIZE] __attribute__((at(0x2FFC2000))); +#endif + +struct mic_device +{ + struct rt_audio_device audio; + struct rt_audio_configure record_config; + rt_uint8_t *rx_fifo; + rt_uint8_t volume; +}; + +static struct mic_device mic_dev = {0}; +static rt_uint16_t zero_frame[2] = {0}; + +extern SAI_HandleTypeDef hsai_BlockA2; +extern DMA_HandleTypeDef hdma_sai2_a; +extern SAI_HandleTypeDef hsai_BlockB2; +extern DMA_HandleTypeDef hdma_sai2_b; +extern void SAIA_Frequency_Set(uint32_t frequency); + +void SAIB_Init(void) +{ + HAL_SAI_DeInit(&hsai_BlockB2); + + hsai_BlockB2.Instance = SAI2_Block_B; + hsai_BlockB2.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_44K; + hsai_BlockB2.Init.AudioMode = SAI_MODESLAVE_RX; + hsai_BlockB2.Init.Synchro = SAI_SYNCHRONOUS; + hsai_BlockB2.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + hsai_BlockB2.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + hsai_BlockB2.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF; + hsai_BlockB2.Init.Mckdiv = 0; + hsai_BlockB2.Init.MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE; + hsai_BlockB2.Init.MonoStereoMode = SAI_STEREOMODE; + hsai_BlockB2.Init.CompandingMode = SAI_NOCOMPANDING; + hsai_BlockB2.Init.TriState = SAI_OUTPUT_NOTRELEASED; + hsai_BlockB2.Init.PdmInit.Activation = DISABLE; + hsai_BlockB2.Init.PdmInit.MicPairsNbr = 1; + hsai_BlockB2.Init.PdmInit.ClockEnable = SAI_PDM_CLOCK1_ENABLE; + hsai_BlockB2.Init.Protocol = SAI_FREE_PROTOCOL; + hsai_BlockB2.Init.DataSize = SAI_DATASIZE_16; + hsai_BlockB2.Init.FirstBit = SAI_FIRSTBIT_MSB; + hsai_BlockB2.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + + hsai_BlockB2.FrameInit.FrameLength = 64; + hsai_BlockB2.FrameInit.ActiveFrameLength = 32; + hsai_BlockB2.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + hsai_BlockB2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai_BlockB2.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + + hsai_BlockB2.SlotInit.FirstBitOffset = 0; + hsai_BlockB2.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + hsai_BlockB2.SlotInit.SlotNumber = 2; + hsai_BlockB2.SlotInit.SlotActive = SAI_SLOTACTIVE_0|SAI_SLOTACTIVE_1; + + /* DeInit SAI PDM input */ + HAL_SAI_DeInit(&hsai_BlockB2); + + /* Init SAI PDM input */ + if(HAL_OK != HAL_SAI_Init(&hsai_BlockB2)) + { + Error_Handler(); + } + + /* Enable SAI to generate clock used by audio driver */ + __HAL_SAI_ENABLE(&hsai_BlockB2); +} + +void SAIB_Channels_Set(uint8_t channels) +{ + if (channels == 1) + { + hsai_BlockB2.Init.MonoStereoMode = SAI_MONOMODE; + } + else + { + hsai_BlockB2.Init.MonoStereoMode = SAI_STEREOMODE; + } + + __HAL_SAI_DISABLE(&hsai_BlockB2); + HAL_SAI_Init(&hsai_BlockB2); + __HAL_SAI_ENABLE(&hsai_BlockB2); +} + +void DMA2_Stream4_IRQHandler(void) +{ + HAL_DMA_IRQHandler(&hdma_sai2_b); +} + +void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + rt_audio_rx_done(&mic_dev.audio, &mic_dev.rx_fifo[0], RX_FIFO_SIZE / 2); +} + +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) +{ + rt_audio_rx_done(&mic_dev.audio, &mic_dev.rx_fifo[RX_FIFO_SIZE / 2], RX_FIFO_SIZE / 2); +} + +static rt_err_t mic_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct mic_device *mic_dev; + + RT_ASSERT(audio != RT_NULL); + mic_dev = (struct mic_device *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */ + { + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_MIXER; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_INPUT: /* Provide capabilities of INPUT unit */ + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.samplerate = mic_dev->record_config.samplerate; + caps->udata.config.channels = mic_dev->record_config.channels; + caps->udata.config.samplebits = mic_dev->record_config.samplebits; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = mic_dev->record_config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = mic_dev->record_config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = mic_dev->record_config.samplebits; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_MIXER: /* report the Mixer Units */ + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + caps->udata.mask = AUDIO_MIXER_VOLUME | AUDIO_MIXER_LINE; + break; + + case AUDIO_MIXER_VOLUME: + caps->udata.value = mic_dev->volume; + break; + + case AUDIO_MIXER_LINE: + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t mic_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct mic_device *mic_dev; + + RT_ASSERT(audio != RT_NULL); + mic_dev = (struct mic_device *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + { + switch (caps->sub_type) + { + case AUDIO_MIXER_VOLUME: + { + rt_uint32_t volume = caps->udata.value; + mic_dev->volume = volume; + LOG_D("set volume %d", volume); + break; + } + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_INPUT: + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + SAIA_Frequency_Set(caps->udata.config.samplerate); + HAL_SAI_DMAStop(&hsai_BlockB2); + SAIB_Channels_Set(caps->udata.config.channels); + HAL_SAI_Transmit(&hsai_BlockA2, (uint8_t *)&zero_frame[0], 2, 0); + HAL_SAI_Receive_DMA(&hsai_BlockB2, mic_dev->rx_fifo, RX_FIFO_SIZE / 2); + + /* save configs */ + mic_dev->record_config.samplerate = caps->udata.config.samplerate; + mic_dev->record_config.channels = caps->udata.config.channels; + mic_dev->record_config.samplebits = caps->udata.config.samplebits; + LOG_D("set samplerate %d", mic_dev->record_config.samplerate); + LOG_D("set channels %d", mic_dev->record_config.channels); + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + mic_dev->record_config.samplerate = caps->udata.config.samplerate; + LOG_D("set channels %d", mic_dev->record_config.channels); + break; + } + + case AUDIO_DSP_CHANNELS: + { + mic_dev->record_config.channels = caps->udata.config.channels; + LOG_D("set channels %d", mic_dev->record_config.channels); + break; + } + + default: + break; + } + + break; + } + + default: + break; + } + + return result; +} + +static rt_err_t mic_init(struct rt_audio_device *audio) +{ + struct mic_device *mic_dev; + RT_ASSERT(audio != RT_NULL); + + mic_dev = (struct mic_device *)audio->parent.user_data; + SAIB_Init(); + /* set default params */ + SAIB_Channels_Set(mic_dev->record_config.channels); + + return RT_EOK; +} + +static rt_err_t mic_start(struct rt_audio_device *audio, int stream) +{ + struct mic_device *mic_dev; + RT_ASSERT(audio != RT_NULL); + + mic_dev = (struct mic_device *)audio->parent.user_data; + if (stream == AUDIO_STREAM_RECORD) + { + cs42l51_drv.init(IN_MIC1, MIC_BUS_NAME, 40); + /* open receive */ + if (HAL_SAI_Receive_DMA(&hsai_BlockB2, mic_dev->rx_fifo, RX_FIFO_SIZE / 2) != HAL_OK) + { + return RT_ERROR; + } + /* supply clk */ + HAL_SAI_Transmit(&hsai_BlockA2, (uint8_t *)&zero_frame[0], 2, 0); + + cs42l51_drv.play(); + } + + return RT_EOK; +} + +static rt_err_t mic_stop(struct rt_audio_device *audio, int stream) +{ + if (stream == AUDIO_STREAM_RECORD) + { + HAL_SAI_DMAStop(&hsai_BlockB2); + HAL_SAI_Abort(&hsai_BlockB2); + cs42l51_drv.stop(); + } + + return RT_EOK; +} + +static struct rt_audio_ops mic_ops = +{ + .getcaps = mic_getcaps, + .configure = mic_configure, + .init = mic_init, + .start = mic_start, + .stop = mic_stop, + .transmit = RT_NULL, + .buffer_info = RT_NULL, +}; + +int rt_hw_mic_init(void) +{ + rt_err_t result = RT_EOK; + struct rt_device *device; + + rt_memset(MIC_RX_FIFO, 0, RX_FIFO_SIZE); + mic_dev.rx_fifo = MIC_RX_FIFO; + + /* init default configuration */ + { + mic_dev.record_config.samplerate = 44100; + mic_dev.record_config.channels = 2; + mic_dev.record_config.samplebits = 16; + mic_dev.volume = 55; + } + + /* register sound device */ + mic_dev.audio.ops = &mic_ops; + result = rt_audio_register(&mic_dev.audio, "mic0", RT_DEVICE_FLAG_RDONLY, &mic_dev); + + if (result != RT_EOK) + { + device = &(mic_dev.audio.parent); + rt_device_unregister(device); + LOG_E("mic device init error!"); + return RT_ERROR; + } + + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_mic_init); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c new file mode 100644 index 0000000000..5d94bfc399 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-31 Zero-Free first implementation + * 2020-07-02 thread-liu Porting for STM32MP1 + */ + +#include "board.h" +#include "drv_cs42l51.h" + +#ifdef BSP_USING_AUDIO + +//#define DRV_DEBUG +#define LOG_TAG "drv.audio" +#include <drv_log.h> + +#define SOUND_BUS_NAME "i2c4" + +/* SYSRAM */ +#define TX_FIFO_SIZE (4096) +#if defined(__CC_ARM) || defined(__CLANG_ARM) +rt_uint8_t AUDIO_TX_FIFO[TX_FIFO_SIZE] __attribute__((at(0x2FFC3000))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFC3000 +rt_uint8_t AUDIO_TX_FIFO[TX_FIFO_SIZE]; +#elif defined ( __GNUC__ ) +rt_uint8_t AUDIO_TX_FIFO[TX_FIFO_SIZE] __attribute__((at(0x2FFC3000))); +#endif + +struct sound_device +{ + struct rt_audio_device audio; + struct rt_audio_configure replay_config; + rt_uint8_t *tx_fifo; + rt_uint8_t volume; +}; + +static struct sound_device snd_dev = {0}; + +SAI_HandleTypeDef hsai_BlockA2 = {0}; +DMA_HandleTypeDef hdma_sai2_a = {0}; +SAI_HandleTypeDef hsai_BlockB2 = {0}; +DMA_HandleTypeDef hdma_sai2_b = {0}; + +void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + /* SAI2 */ + if(hsai->Instance==SAI2_Block_A) + { + /* Peripheral clock enable */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; + PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_SAI2_CLK_ENABLE(); + + /**SAI2_A_Block_A GPIO Configuration + PE0 ------> SAI2_MCLK_A + PI7 ------> SAI2_FS_A + PI5 ------> SAI2_SCK_A + PI6 ------> SAI2_SD_A + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* Configure DMA used for SAI2 */ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA2_CLK_ENABLE(); + + hdma_sai2_a.Instance = DMA2_Stream5; + hdma_sai2_a.Init.Request = DMA_REQUEST_SAI2_A; + hdma_sai2_a.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_sai2_a.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sai2_a.Init.MemInc = DMA_MINC_ENABLE; + hdma_sai2_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_sai2_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_sai2_a.Init.Mode = DMA_CIRCULAR; + hdma_sai2_a.Init.Priority = DMA_PRIORITY_HIGH; + hdma_sai2_a.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + + HAL_DMA_DeInit(&hdma_sai2_a); + if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK) + { + Error_Handler(); + } + __HAL_LINKDMA(hsai,hdmatx,hdma_sai2_a); + __HAL_DMA_ENABLE(&hdma_sai2_a); + HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); + } + + if(hsai->Instance==SAI2_Block_B) + { + /* Peripheral clock enable */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; + PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_SAI2_CLK_ENABLE(); + + /**SAI2_B_Block_B GPIO Configuration + PF11 ------> SAI2_SD_B + */ + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_sai2_b.Instance = DMA2_Stream4; + hdma_sai2_b.Init.Request = DMA_REQUEST_SAI2_B; + hdma_sai2_b.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_sai2_b.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sai2_b.Init.MemInc = DMA_MINC_ENABLE; + hdma_sai2_b.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_sai2_b.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_sai2_b.Init.Mode = DMA_CIRCULAR; + hdma_sai2_b.Init.Priority = DMA_PRIORITY_HIGH; + hdma_sai2_b.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + hdma_sai2_b.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sai2_b.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_sai2_b.Init.PeriphBurst = DMA_PBURST_SINGLE; + __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b); + HAL_DMA_DeInit(&hdma_sai2_b); + if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK) + { + Error_Handler(); + } + __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b); + __HAL_DMA_ENABLE(&hdma_sai2_b); + HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn); + } +} + +void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) +{ + /* SAI2 */ + if(hsai->Instance==SAI2_Block_A) + { + + /* Peripheral clock disable */ + __HAL_RCC_SAI2_CLK_DISABLE(); + + /**SAI2_A_Block_A GPIO Configuration + PE0 ------> SAI2_MCLK_A + PI7 ------> SAI2_FS_A + PI5 ------> SAI2_SCK_A + PI6 ------> SAI2_SD_A + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_7|GPIO_PIN_5|GPIO_PIN_6); + + HAL_DMA_DeInit(hsai->hdmarx); + HAL_DMA_DeInit(hsai->hdmatx); + } + + if(hsai->Instance==SAI2_Block_B) + { + /* Peripheral clock disable */ + __HAL_RCC_SAI2_CLK_DISABLE(); + + /**SAI2_B_Block_B GPIO Configuration + PF11 ------> SAI2_SD_B + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_11); + + HAL_DMA_DeInit(hsai->hdmarx); + HAL_DMA_DeInit(hsai->hdmatx); + } +} + +static void rt_hw_sai2a_init(void) +{ + HAL_SAI_DeInit(&hsai_BlockA2); + hsai_BlockA2.Instance = SAI2_Block_A; + hsai_BlockA2.Init.Protocol = SAI_FREE_PROTOCOL; + hsai_BlockA2.Init.AudioMode = SAI_MODEMASTER_TX; + hsai_BlockA2.Init.DataSize = SAI_DATASIZE_16; + hsai_BlockA2.Init.FirstBit = SAI_FIRSTBIT_MSB; + hsai_BlockA2.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + hsai_BlockA2.Init.Synchro = SAI_ASYNCHRONOUS; + hsai_BlockA2.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + hsai_BlockA2.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + hsai_BlockA2.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; + hsai_BlockA2.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_44K; + hsai_BlockA2.Init.SynchroExt = SAI_SYNCEXT_DISABLE; + hsai_BlockA2.Init.MonoStereoMode = SAI_STEREOMODE; + hsai_BlockA2.Init.CompandingMode = SAI_NOCOMPANDING; + hsai_BlockA2.Init.TriState = SAI_OUTPUT_NOTRELEASED; + hsai_BlockA2.Init.PdmInit.Activation = DISABLE; + hsai_BlockA2.Init.PdmInit.MicPairsNbr = 0; + hsai_BlockA2.Init.PdmInit.ClockEnable = SAI_PDM_CLOCK1_ENABLE; + + hsai_BlockA2.FrameInit.FrameLength = 64; + hsai_BlockA2.FrameInit.ActiveFrameLength = 32; + hsai_BlockA2.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + hsai_BlockA2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai_BlockA2.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + + hsai_BlockA2.SlotInit.FirstBitOffset = 0; + hsai_BlockA2.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + hsai_BlockA2.SlotInit.SlotNumber = 2; + hsai_BlockA2.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; + + if(HAL_OK != HAL_SAI_Init(&hsai_BlockA2)) + { + Error_Handler(); + } + /* Enable SAI to generate clock used by audio driver */ + __HAL_SAI_ENABLE(&hsai_BlockA2); +} + +void DMA2_Stream5_IRQHandler(void) +{ + HAL_DMA_IRQHandler(&hdma_sai2_a); +} + +void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &hsai_BlockA2) + { + rt_audio_tx_complete(&snd_dev.audio); + } +} + +void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &hsai_BlockA2) + { + rt_audio_tx_complete(&snd_dev.audio); + } +} + +void SAIA_Frequency_Set(uint32_t frequency) +{ + return; +} + +void SAIA_Channels_Set(uint8_t channels) +{ + if (channels == 1) + { + hsai_BlockA2.Init.MonoStereoMode = SAI_MONOMODE; + } + else + { + hsai_BlockA2.Init.MonoStereoMode = SAI_STEREOMODE; + } + + __HAL_SAI_DISABLE(&hsai_BlockA2); + HAL_SAI_Init(&hsai_BlockA2); + __HAL_SAI_ENABLE(&hsai_BlockA2); +} + +/** + * RT-Thread Audio Device Driver Interface + */ +static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */ + { + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */ + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.samplerate = snd_dev->replay_config.samplerate; + caps->udata.config.channels = snd_dev->replay_config.channels; + caps->udata.config.samplebits = snd_dev->replay_config.samplebits; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = snd_dev->replay_config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = snd_dev->replay_config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = snd_dev->replay_config.samplebits; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_MIXER: /* report the Mixer Units */ + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + caps->udata.mask = AUDIO_MIXER_VOLUME; + break; + + case AUDIO_MIXER_VOLUME: + caps->udata.value = cs42l51_drv.get_volume(); + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + { + switch (caps->sub_type) + { + case AUDIO_MIXER_VOLUME: + { + rt_uint8_t volume = caps->udata.value; + + cs42l51_drv.set_volume(volume); + + snd_dev->volume = volume; + + LOG_D("set volume %d", volume); + break; + } + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_OUTPUT: + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + /* set samplerate */ + SAIA_Frequency_Set(caps->udata.config.samplerate); + /* set channels */ + SAIA_Channels_Set(caps->udata.config.channels); + + /* save configs */ + snd_dev->replay_config.samplerate = caps->udata.config.samplerate; + snd_dev->replay_config.channels = caps->udata.config.channels; + snd_dev->replay_config.samplebits = caps->udata.config.samplebits; + LOG_D("set samplerate %d", snd_dev->replay_config.samplerate); + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + SAIA_Frequency_Set(caps->udata.config.samplerate); + snd_dev->replay_config.samplerate = caps->udata.config.samplerate; + LOG_D("set samplerate %d", snd_dev->replay_config.samplerate); + break; + } + + case AUDIO_DSP_CHANNELS: + { + SAIA_Channels_Set(caps->udata.config.channels); + snd_dev->replay_config.channels = caps->udata.config.channels; + LOG_D("set channels %d", snd_dev->replay_config.channels); + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + /* not support */ + snd_dev->replay_config.samplebits = caps->udata.config.samplebits; + break; + } + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + break; + } + + return result; +} + +static rt_err_t sound_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 40); + + if (cs42l51_drv.read_id() != RT_EOK) + { + LOG_E("can't find low level audio device!"); + return RT_ERROR; + } + + rt_hw_sai2a_init(); + + /* set default params */ + SAIA_Frequency_Set(snd_dev->replay_config.samplerate); + SAIA_Channels_Set(snd_dev->replay_config.channels); + + return result; +} + +static rt_err_t sound_start(struct rt_audio_device *audio, int stream) +{ + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + if (stream == AUDIO_STREAM_REPLAY) + { + LOG_D("open sound device"); + + cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 60); /* set work mode */ + cs42l51_drv.play(); + + if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK) + { + return RT_ERROR; + } + } + + return RT_EOK; +} + +static rt_err_t sound_stop(struct rt_audio_device *audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + + if (stream == AUDIO_STREAM_REPLAY) + { + HAL_SAI_DMAStop(&hsai_BlockA2); + HAL_SAI_Abort(&hsai_BlockA2); + cs42l51_drv.stop(); + + LOG_D("close sound device"); + } + + return RT_EOK; +} + +static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + /** + * TX_FIFO + * +----------------+----------------+ + * | block1 | block2 | + * +----------------+----------------+ + * \ block_size / + */ + info->buffer = snd_dev->tx_fifo; + info->total_size = TX_FIFO_SIZE; + info->block_size = TX_FIFO_SIZE / 2; + info->block_count = 2; +} + +static struct rt_audio_ops snd_ops = +{ + .getcaps = sound_getcaps, + .configure = sound_configure, + .init = sound_init, + .start = sound_start, + .stop = sound_stop, + .transmit = RT_NULL, + .buffer_info = sound_buffer_info, +}; + +int rt_hw_sound_init(void) +{ + rt_err_t result = RT_EOK; + struct rt_device *device = RT_NULL; + + rt_memset(AUDIO_TX_FIFO, 0, TX_FIFO_SIZE); + snd_dev.tx_fifo = AUDIO_TX_FIFO; + + /* init default configuration */ + snd_dev.replay_config.samplerate = 44100; + snd_dev.replay_config.channels = 2; + snd_dev.replay_config.samplebits = 16; + snd_dev.volume = 55; + + /* register sound device */ + snd_dev.audio.ops = &snd_ops; + result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev); + if (result != RT_EOK) + { + device = &(snd_dev.audio.parent); + rt_device_unregister(device); + LOG_E("sound device init error!"); + return RT_ERROR; + } + + return RT_EOK; +} + +INIT_APP_EXPORT(rt_hw_sound_init); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c new file mode 100644 index 0000000000..e3eb609559 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 thread-liu first version + */ + +#include <board.h> + +#include "drv_crypto.h" +#include <hwcrypto.h> +#include <string.h> +#include <stdlib.h> + +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%02X ", buf[i + j]); + } + else + { + rt_kprintf(" "); + } + } + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } + rt_kprintf("\n"); + } +} + +#if defined(BSP_USING_RNG) +static rt_err_t hw_rng_sample(int random_num) +{ + rt_err_t result = RT_EOK; + int i = 0, num0 = 0, num1 = 0; + + if (random_num == 0) + { + return RT_ERROR; + } + + for (i = 0; i< random_num; i++) + { + result = rt_hwcrypto_rng_update(); + rt_kprintf("%d ", result); + result%2 ? num1++ : num0++; + } + rt_kprintf("\neven numbers : %d, odd numbers: %d\n",num1, num0); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_CRC) +static void hw_crc_sample(uint8_t *temp, int size) +{ + struct rt_hwcrypto_ctx *ctx; + rt_uint32_t result = 0; + + struct hwcrypto_crc_cfg cfg = + { + .last_val = 0xFFFFFFFF, + .poly = 0x04C11DB7, + .width = 32, + .xorout = 0x00000000, + .flags = 0, + }; + + ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32); + rt_hwcrypto_crc_cfg(ctx, &cfg); + + result = rt_hwcrypto_crc_update(ctx, temp, size); + + rt_kprintf("crc result: %x \n", result); + + rt_hwcrypto_crc_destroy(ctx); +} +#endif + +#if defined(BSP_USING_HASH) +static void hw_hash_sample() +{ + struct rt_hwcrypto_ctx *ctx = RT_NULL; + const uint8_t hash_input[] = "RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS)."; + + static uint8_t sha1_output[20]; + static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad, + 0x02, 0x1b, 0xa8, 0xbc, 0xa2, 0x2e, 0xa5, + 0xb0, 0x62, 0x1b, 0xdf, 0x7f, 0xec}; + + static uint8_t md5_output[16]; + static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9, + 0x4c, 0xd6, 0x7d, 0x28, 0xfc, 0xf6, 0xc3, + 0xac, 0x8b}; + + static uint8_t sha224_output[28]; + static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6, + 0x9f, 0x82, 0x78, 0x7a, 0x46, 0x91, + 0xb0, 0xe9, 0x64, 0x89, 0xe6, 0xc3, + 0x6b, 0x7e, 0xcf, 0xca, 0x11, 0x42, + 0xc8, 0x77, 0x13, 0x79}; + static uint8_t sha256_output[32]; + static uint8_t sha256_except[32] = {0x74, 0x19, 0xb9, 0x0e, 0xd1, 0x46, + 0x37, 0x0a, 0x55, 0x18, 0x26, 0x6c, + 0x50, 0xd8, 0x71, 0x34, 0xfa, 0x1f, + 0x5f, 0x5f, 0xe4, 0x9a, 0xe9, 0x40, + 0x0a, 0x7d, 0xa0, 0x26, 0x1b, 0x86, + 0x67, 0x45}; + rt_kprintf("======================== Hash Test start ========================\n"); + rt_kprintf("Hash Test string: \n"); + dump_hex(hash_input, sizeof(hash_input)); + + /* sh1 test*/ + rt_kprintf("\n============ SHA1 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA1); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA1); + return ; + } + rt_kprintf("Create sha1 type success!\n"); + rt_kprintf("Except sha1 result:\n"); + dump_hex(sha1_except, sizeof(sha1_except)); + + /* start sha1 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha1 result */ + rt_hwcrypto_hash_finish(ctx, sha1_output, rt_strlen((char const *)sha1_output)); + + rt_kprintf("Actual sha1 result:\n"); + dump_hex(sha1_output, sizeof(sha1_output)); + + if(rt_memcmp(sha1_output, sha1_except, sizeof(sha1_except)/sizeof(sha1_except[0])) != 0) + { + rt_kprintf("Hash type sha1 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha1 Test success, The actual result is equal to the except result\n"); + } + /* deinit hash*/ + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ SHA1 Test Over ============\n"); + + /* md5 test*/ + rt_kprintf("\n============ MD5 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_MD5); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_MD5); + return ; + } + rt_kprintf("Create md5 type success!\n"); + rt_kprintf("Except md5 result:\n"); + dump_hex(md5_except, sizeof(md5_except)); + + /* start md5 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get md5 result */ + rt_hwcrypto_hash_finish(ctx, md5_output, rt_strlen((char const *)md5_output)); + + rt_kprintf("Actual md5 result:\n"); + dump_hex(md5_output, sizeof(md5_output)); + + if(rt_memcmp(md5_output, md5_except, sizeof(md5_except)/sizeof(md5_except[0])) != 0) + { + rt_kprintf("Hash type md5 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type md5 Test success, The actual result is equal to the except result\n"); + } + /* deinit hash*/ + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ MD5 Test Over ============\n"); + + /* sha224 test */ + rt_kprintf("\n============ SHA224 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA224); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA224); + return ; + } + rt_kprintf("Create sha224 type success!\n"); + rt_kprintf("Except sha224 result:\n"); + dump_hex(sha224_except, sizeof(sha224_except)); + + /* start sha224 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha224 result */ + rt_hwcrypto_hash_finish(ctx, sha224_output, rt_strlen((char const *)sha224_output)); + + rt_kprintf("Actual sha224 result:\n"); + dump_hex(sha224_output, sizeof(sha224_output)); + + if(rt_memcmp(sha224_output, sha224_except, sizeof(sha224_except)/sizeof(sha224_except[0])) != 0) + { + rt_kprintf("Hash type sha224 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha224 Test success, The actual result is equal to the except result\n"); + } + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ SHA224 Test Over ============\n"); + + /* sha256 test*/ + rt_kprintf("\n============ SHA256 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA256); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA256); + return ; + } + + rt_kprintf("Create sha256 type success!\n"); + rt_kprintf("Except sha256 result:\n"); + dump_hex(sha256_except, sizeof(sha256_except)); + + /* start sha256 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha256 result */ + rt_hwcrypto_hash_finish(ctx, sha256_output, rt_strlen((char const *)sha256_output)); + + rt_kprintf("Actual sha256 result\n"); + dump_hex(sha256_output, sizeof(sha256_output)); + + if(rt_memcmp(sha256_output, sha256_except, sizeof(sha256_except)/sizeof(sha256_except[0])) != 0) + { + rt_kprintf("Hash type sha256 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha256 Test success, The actual result is equal to the except result\n"); + } + /* destory */ + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ SHA256 Test Over ============\n"); + rt_kprintf("======================== Hash Test over! ========================\n"); +} +#endif + +#if defined(BSP_USING_CRYP) +/* key*/ +static const rt_uint8_t cryp_key[16] = {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF}; + +static void hw_aes_cbc(const rt_uint8_t in[32], rt_uint8_t out[32], hwcrypto_mode mode) +{ + struct rt_hwcrypto_ctx *ctx; + + ctx = rt_hwcrypto_symmetric_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_AES_CBC); + if (ctx == RT_NULL) + { + rt_kprintf("create AES-CBC context err!"); + return; + } + rt_hwcrypto_symmetric_setkey(ctx, cryp_key, 128); + rt_hwcrypto_symmetric_crypt(ctx, mode, 32, in, out); + rt_hwcrypto_symmetric_destroy(ctx); +} + +static void hw_cryp_sample() +{ + rt_uint8_t buf_in[32]; + rt_uint8_t buf_out[32]; + int i; + + /* Populating test data */ + for (i = 0; i < sizeof(buf_in); i++) + { + buf_in[i] = i; + } + + /* dump primitive data */ + rt_kprintf("key : \n"); + dump_hex(cryp_key, sizeof(cryp_key)); + rt_kprintf("primitive data : \n"); + dump_hex(buf_in, sizeof(buf_in)); + + rt_memset(buf_out, 0, sizeof(buf_out)); + + /* encrypt */ + hw_aes_cbc(buf_in, buf_out, HWCRYPTO_MODE_ENCRYPT); + /* dump encrypt data */ + rt_kprintf("AES-enc : \n"); + dump_hex(buf_out, sizeof(buf_out)); + + rt_memset(buf_in, 0, sizeof(buf_in)); + + /* decrypt */ + hw_aes_cbc(buf_out, buf_in, HWCRYPTO_MODE_DECRYPT); + + /* dump decrypt data */ + rt_kprintf("AES-dec : \n"); + dump_hex(buf_in, sizeof(buf_in)); +} +#endif + +static int crypto(int argc, char **argv) +{ + int result = RT_EOK; + static rt_device_t device = RT_NULL; + char *result_str; + + if (argc > 1) + { + if (!strcmp(argv[1], "probe")) + { + if (argc == 3) + { + char *dev_name = argv[2]; + device = rt_device_find(dev_name); + result_str = (device == RT_NULL) ? "failure" : "success"; + rt_kprintf("probe %s %s \n", argv[2], result_str); + } + else + { + rt_kprintf("crypto probe <crypto_name> - probe crypto by name\n"); + } + } + else + { + if (device == RT_NULL) + { + rt_kprintf("Please using 'crypto probe <crypto_name>' first\n"); + return -RT_ERROR; + } + if (!strcmp(argv[1], "rng")) + { +#if defined (BSP_USING_RNG) + if (argc == 3) + { + result = hw_rng_sample(atoi(argv[2])); + if(result != RT_EOK) + { + rt_kprintf("please input a legal number, not <%d>\n", atoi(argv[2])); + } + } + else + { + rt_kprintf("rng <number> - generate <number> digital\n"); + } + +#else + rt_kprintf("please enable RNG first!\n"); +#endif + } + else if (!strcmp(argv[1], "crc")) + { +#if defined (BSP_USING_CRC) + int size = 0, i = 0; + if (argc > 3) + { + size = argc - 2; + uint8_t *data = rt_malloc(size); + if (data) + { + for (i = 0; i < size; i++) + { + data[i] = strtol(argv[2 + i], NULL, 0); + } + hw_crc_sample(data, size); + rt_free(data); + } + else + { + rt_kprintf("Low memory!\n"); + } + } + else + { + rt_kprintf("crypto crc data1 ... dataN - calculate data1 ... dataN crc\n"); + } +#else + rt_kprintf("please enable CRC first!\n"); +#endif + } + else if (!strcmp(argv[1], "hash")) + { +#if defined (BSP_USING_HASH) + if (argc == 3) + { + hw_hash_sample(); + } + else + { + rt_kprintf("crypto hash sample - hash use sample\n"); + } +#else + rt_kprintf("please enable CRC first!\n"); +#endif + } + else if (!strcmp(argv[1], "cryp")) + { +#if defined (BSP_USING_CRYP) + if (argc == 3) + { + hw_cryp_sample(); + } + else + { + rt_kprintf("crypto cryp sample - encrypt and decrypt data sample\n"); + } +#else + rt_kprintf("please enable CRYP first!\n"); +#endif + } + else + { + rt_kprintf("Unknown command. Please enter 'crypto' for help\n"); + } + } + } + else + { + rt_kprintf("Usage: \n"); + rt_kprintf("crypto probe <crypto_name> - probe crypto by name\n"); + rt_kprintf("crypto rng number - generate numbers digital\n"); + rt_kprintf("crypto crc data1 ... dataN - calculate data1 ... dataN crc\n"); + rt_kprintf("crypto hash sample - hash use sample\n"); + rt_kprintf("crypto cryp sample - encrypt and decrypt data\n"); + result = -RT_ERROR; + } + + return result; +} +MSH_CMD_EXPORT(crypto, crypto function); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c new file mode 100644 index 0000000000..b2fbc3561b --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c @@ -0,0 +1,882 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-20 thread-liu the first version + */ + +#include "board.h" +#include "drv_config.h" +#include <netif/ethernetif.h> +#include "lwipopts.h" +#include "drv_eth.h" + +#if defined(BSP_USING_GBE) + +#define DRV_DEBUG +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP +#define LOG_TAG "drv.emac" +#include <drv_log.h> + +#define MAX_ADDR_LEN 6 +rt_base_t level; + +#define TX_ADD_BASE 0x2FFC3000 +#define RX_ADD_BASE 0x2FFC5000 +#define TX_DMA_ADD_BASE 0x2FFC7000 +#define RX_DMA_ADD_BASE 0x2FFC7100 + +#if defined(__ICCARM__) +/* transmit buffer */ +#pragma location = TX_ADD_BASE +static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; +/* Receive buffer */ +#pragma location = RX_ADD_BASE +static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; +/* Transmit DMA descriptors */ +#pragma location = TX_DMA_ADD_BASE +static TxDmaDesc txDmaDesc[ETH_TXBUFNB]; +/* Receive DMA descriptors */ +#pragma location = RX_DMA_ADD_BASE +static RxDmaDesc rxDmaDesc[ETH_RXBUFNB]; + +#elif defined(__CC_ARM) || defined(__CLANG_ARM) +/* transmit buffer */ +static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(TX_ADD_BASE))); +/* Receive buffer */ +static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(RX_ADD_BASE))); +/* Transmit DMA descriptors */ +static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((at(TX_DMA_ADD_BASE))); +/* Receive DMA descriptors */ +static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((at(RX_DMA_ADD_BASE))); + +#elif defined ( __GNUC__ ) +/* transmit buffer */ +static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(TX_ADD_BASE))); +/* Receive buffer */ +static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(RX_ADD_BASE))); +/* Transmit DMA descriptors */ +static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((at(TX_DMA_ADD_BASE))); +/* Receive DMA descriptors */ +static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((at(RX_DMA_ADD_BASE))); +#endif + +/* Current transmit descriptor */ +static rt_uint8_t txIndex = 0; +/* Current receive descriptor */ +static rt_uint8_t rxIndex = 0; + +/* eth rx event */ +static struct rt_event rx_event = {0}; + +#define ETH_TIME_OUT 100000 + +struct rt_stm32_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; +#ifndef PHY_USING_INTERRUPT_MODE + rt_timer_t poll_link_timer; +#endif + /* interface address info, hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + /* eth speed */ + rt_uint32_t eth_speed; + /* eth duplex mode */ + rt_uint32_t eth_mode; +}; +static struct rt_stm32_eth stm32_eth_device = {0}; + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%02X ", buf[i + j]); + } + else + { + rt_kprintf(" "); + } + } + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } + rt_kprintf("\n"); + } +} +#endif + +static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_value) +{ + uint32_t temp; + volatile uint32_t tickstart = 0; + /* Take care not to alter MDC clock configuration */ + temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR; + /* Set up a write operation */ + temp |= ETH_MACMDIOAR_GOC_Val(1) | ETH_MACMDIOAR_GB; + /* PHY address */ + temp |= (phy_addr << 21) & ETH_MACMDIOAR_PA; + /* Register address */ + temp |= (reg_addr << 16) & ETH_MACMDIOAR_RDA; + + /* Data to be written in the PHY register */ + ETH->MACMDIODR = reg_value & ETH_MACMDIODR_GD; + + /* Start a write operation */ + ETH->MACMDIOAR = temp; + /* Wait for the write to complete */ + tickstart = rt_tick_get(); + while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0) + { + /* judge timeout */ + if((rt_tick_get() - tickstart) > ETH_TIME_OUT) + { + LOG_E("PHY write reg %02x date %04x timeout!", reg_addr, reg_value); + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr) +{ + uint16_t reg_value = 0; + uint32_t status = 0; + volatile uint32_t tickstart = 0; + + /* Take care not to alter MDC clock configuration */ + status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR; + /* Set up a read operation */ + status |= ETH_MACMDIOAR_GOC_Val(3) | ETH_MACMDIOAR_GB; + /* PHY address */ + status |= (phy_addr << 21) & ETH_MACMDIOAR_PA; + /* Register address */ + status |= (reg_addr << 16) & ETH_MACMDIOAR_RDA; + + /* Start a read operation */ + ETH->MACMDIOAR = status; + /* Wait for the read to complete */ + tickstart = rt_tick_get(); + while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0) + { + /* judge timeout */ + if((rt_tick_get() - tickstart) > ETH_TIME_OUT) + { + LOG_E("PHY read reg %02x timeout!", reg_addr); + return RT_ETIMEOUT; + } + } + + /* Get register value */ + reg_value = ETH->MACMDIODR & ETH_MACMDIODR_GD; + + return reg_value; +} + +static rt_err_t update_mac_mode(rt_uint32_t eth_speed, rt_uint32_t eth_mode) +{ + uint32_t status; + + /* Read current MAC configuration */ + status = ETH->MACCR; + + if (eth_speed == PHY_1000M) + { + status &= ~ETH_MACCR_PS; + status &= ~ETH_MACCR_FES; + } + else if (eth_speed == PHY_100M) + { + status |= ETH_MACCR_PS; + status |= ETH_MACCR_FES; + } + /* 10M */ + else + { + status |= ETH_MACCR_PS; + status &= ~ETH_MACCR_FES; + } + + if (eth_mode == PHY_FULL_DUPLEX) + { + status |= ETH_MACCR_DM; + } + else + { + status &= ~ETH_MACCR_DM; + } + + /* Update MAC configuration register */ + ETH->MACCR = status; + + return RT_EOK; +} + +static void HAL_ETH_MspInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH; + PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable GPIO clocks */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /* Select RGMII interface mode */ + HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII); + + /* Enable Ethernet MAC clock */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + __HAL_RCC_ETH1TX_CLK_ENABLE(); + __HAL_RCC_ETH1RX_CLK_ENABLE(); + + /**ETH1 GPIO Configuration + PA1 ------> ETH1_RX_CLK + PA7 ------> ETH1_RX_CTL + PB0 ------> ETH1_RXD2 + PB1 ------> ETH1_RXD3 + PC4 ------> ETH1_RXD0 + PC5 ------> ETH1_RXD1 + PA2 ------> ETH1_MDIO + PB11 ------> ETH1_TX_CTL + PC1 ------> ETH1_MDC + PC2 ------> ETH1_TXD2 + PE2 ------> ETH1_TXD3 + PG4 ------> ETH1_GTX_CLK + PG5 ------> ETH1_CLK125 + PG13 ------> ETH1_TXD0 + PG14 ------> ETH1_TXD1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_11; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00); + HAL_NVIC_EnableIRQ(ETH1_IRQn); + + /* Configure PHY_RST (PG0) */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* Reset PHY transceiver */ + HAL_GPIO_WritePin(GPIOG, GPIO_PIN_0, GPIO_PIN_RESET); + rt_thread_mdelay(20); + HAL_GPIO_WritePin(GPIOG, GPIO_PIN_0, GPIO_PIN_SET); + rt_thread_mdelay(20); +} + +static rt_err_t rt_stm32_eth_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + rt_uint32_t status, i; + volatile rt_uint32_t tickstart = 0; + rt_uint8_t *macAddr = &stm32_eth_device.dev_addr[0]; + + /* Initialize TX descriptor index */ + txIndex = 0; + /* Initialize RX descriptor index */ + rxIndex = 0; + + HAL_ETH_MspInit(); + + /* Reset Ethernet MAC peripheral */ + __HAL_RCC_ETH1MAC_FORCE_RESET(); + __HAL_RCC_ETH1MAC_RELEASE_RESET(); + + /* Ethernet Software reset */ + ETH->DMAMR |= ETH_DMAMR_SWR; + /* Wait for the reset to complete */ + tickstart = rt_tick_get(); + while (READ_BIT(ETH->DMAMR, ETH_DMAMR_SWR)) + { + if(((HAL_GetTick() - tickstart ) > ETH_TIME_OUT)) + { + LOG_E("ETH software reset timeout!"); + return RT_ERROR; + } + } + + /* Adjust MDC clock range depending on HCLK frequency */ + ETH->MACMDIOAR = ETH_MACMDIOAR_CR_Val(5); + + /* Use default MAC configuration */ + ETH->MACCR = ETH_MACCR_DO; + + /* Set the MAC address of the station */ + ETH->MACA0LR = ((macAddr[3] << 24) | (macAddr[2] << 16) | (macAddr[1] << 8) | macAddr[0]); + ETH->MACA0HR = ((macAddr[5] << 8) | macAddr[4]); + + /* The MAC supports 3 additional addresses for unicast perfect filtering */ + ETH->MACA1LR = 0; + ETH->MACA1HR = 0; + ETH->MACA2LR = 0; + ETH->MACA2HR = 0; + ETH->MACA3LR = 0; + ETH->MACA3HR = 0; + + /* Initialize hash table */ + ETH->MACHT0R = 0; + ETH->MACHT1R = 0; + + /* Configure the receive filter */ + ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC; + + /* Disable flow control */ + ETH->MACQ0TXFCR = 0; + ETH->MACRXFCR = 0; + + /* Enable the first RX queue */ + ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1); + + /* Configure DMA operating mode */ + ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0); + + /* Configure system bus mode */ + ETH->DMASBMR |= ETH_DMASBMR_AAL; + + /* The DMA takes the descriptor table as contiguous */ + ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0); + + /* Configure TX features */ + ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1); + + /* Configure RX features */ + ETH->DMAC0RXCR = ETH_DMAC0RXCR_RXPBL_Val(1) | ETH_DMAC0RXCR_RBSZ_Val(ETH_RX_BUF_SIZE); + + /* Enable store and forward mode for transmission */ + ETH->MTLTXQ0OMR = ETH_MTLTXQ0OMR_TQS_Val(7) | ETH_MTLTXQ0OMR_TXQEN_Val(2) | ETH_MTLTXQ0OMR_TSF; + + /* Enable store and forward mode for reception */ + ETH->MTLRXQ0OMR = ETH_MTLRXQ0OMR_RQS_Val(7) | ETH_MTLRXQ0OMR_RSF; + + /* Initialize TX DMA descriptor list */ + for (i = 0; i < ETH_TXBUFNB; i++) + { + /* The descriptor is initially owned by the application */ + txDmaDesc[i].tdes0 = 0; + txDmaDesc[i].tdes1 = 0; + txDmaDesc[i].tdes2 = 0; + txDmaDesc[i].tdes3 = 0; + } + + /* Initialize RX DMA descriptor list */ + for (i = 0; i < ETH_RXBUFNB; i++) + { + /* The descriptor is initially owned by the DMA */ + rxDmaDesc[i].rdes0 = (uint32_t) rxBuffer[i]; + rxDmaDesc[i].rdes1 = 0; + rxDmaDesc[i].rdes2 = 0; + rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V; + } + + /* Set Transmit Descriptor List Address Register */ + ETH->DMAC0TXDLAR = (uint32_t) &txDmaDesc[0]; + /* Length of the transmit descriptor ring */ + ETH->DMAC0TXRLR = ETH_TXBUFNB - 1; + + /* Set Receive Descriptor List Address Register */ + ETH->DMAC0RXDLAR = (uint32_t) &rxDmaDesc[0]; + /* Length of the receive descriptor ring */ + ETH->DMAC0RXRLR = ETH_RXBUFNB - 1; + + /* Prevent interrupts from being generated when the transmit statistic + * counters reach half their maximum value */ + ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM; + + /* Prevent interrupts from being generated when the receive statistic + * counters reach half their maximum value */ + ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM; + + /* Disable MAC interrupts */ + ETH->MACIER = 0; + + /* Enable the desired DMA interrupts */ + ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; + + /* Enable MAC transmission and reception */ + ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE; + + /* Enable DMA transmission and reception */ + ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST; + ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR; + + /* Reset PHY transceiver */ + phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR, RTL8211F_BMCR_RESET); + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR); + /* Wait for the reset to complete */ + tickstart = rt_tick_get(); + while (status & RTL8211F_BMCR_RESET) + { + if((rt_tick_get() - tickstart) > ETH_TIME_OUT) + { + LOG_E("PHY software reset timeout!"); + return RT_ETIMEOUT; + } + else + { + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR); + } + } + + /* The PHY will generate interrupts when link status changes are detected */ + phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_INER, RTL8211F_INER_AN_COMPLETE | RTL8211F_INER_LINK_STATUS); + + return RT_EOK; +} + +static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("emac open"); + return RT_EOK; +} + +static rt_err_t rt_stm32_eth_close(rt_device_t dev) +{ + LOG_D("emac close"); + return RT_EOK; +} + +static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("emac read"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("emac write"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) + { + rt_memcpy(args, stm32_eth_device.dev_addr, 6); + } + else + { + return -RT_ERROR; + } + break; + + default : + break; + } + + return RT_EOK; +} + +rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) +{ + uint32_t framelen = 0; + struct pbuf *q = RT_NULL; + + /* Copy user data to the transmit buffer */ + for (q = p; q != NULL; q = q->next) + { + /* Make sure the current buffer is available for writing */ + if((txDmaDesc[txIndex].tdes3 & ETH_TDES3_OWN) != 0) + { + LOG_D("buffer not valid"); + return ERR_USE; + } + + level = rt_hw_interrupt_disable(); + rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len); + framelen += q->len; + rt_hw_interrupt_enable(level); + + /* Check the frame length */ + if (framelen > ETH_TX_BUF_SIZE - 1) + { + LOG_D(" tx buffer frame length over : %d", framelen); + return ERR_USE; + } + } + +#ifdef ETH_TX_DUMP + rt_kprintf("Tx dump, len= %d\r\n", framelen); + dump_hex(txBuffer[txIndex], framelen); +#endif + + /* Set the start address of the buffer */ + txDmaDesc[txIndex].tdes0 = (uint32_t)txBuffer[txIndex]; + /* Write the number of bytes to send */ + txDmaDesc[txIndex].tdes2 = ETH_TDES2_IOC | (framelen & ETH_TDES2_B1L); + /* Give the ownership of the descriptor to the DMA */ + txDmaDesc[txIndex].tdes3 = ETH_TDES3_OWN | ETH_TDES3_FD | ETH_TDES3_LD; + + /* Data synchronization barrier */ + __DSB(); + + /* Clear TBU flag to resume processing */ + ETH->DMAC0SR = ETH_DMAC0SR_TBU; + /* Instruct the DMA to poll the transmit descriptor list */ + ETH->DMAC0TXDTPR = 0; + + if (++txIndex > ETH_TXBUFNB - 1) + { + txIndex = 0; + } + + return ERR_OK; +} + +struct pbuf *rt_stm32_eth_rx(rt_device_t dev) +{ + rt_uint32_t framelength = 0; + uint32_t framelen = 0; + struct pbuf *p = RT_NULL, *q = RT_NULL; + + /* The current buffer is available for reading */ + if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) + { + /* FD and LD flags should be set */ + if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD)) + { + /* Make sure no error occurred */ + if(!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_ES)) + { + /* Retrieve the length of the frame */ + framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL; + /* check the frame length */ + framelength = (framelength > ETH_RX_BUF_SIZE) ? ETH_RX_BUF_SIZE : framelength; + + p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM); + if (p != NULL) + { + for (q = p; q != NULL; q = q->next) + { + level=rt_hw_interrupt_disable(); + rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len); + framelen += q->len; + rt_hw_interrupt_enable(level); + + if (framelen > framelength) + { + LOG_E("frame len is too long!"); + return RT_NULL; + } + } + } + } + else + { + /* The received packet contains an error */ + LOG_D("the received packet contains an error!"); + return RT_NULL; + } + + } + else + { + /* The packet is not valid */ + LOG_D("the packet is not valid"); + return RT_NULL; + } + + /* Set the start address of the buffer */ + rxDmaDesc[rxIndex].rdes0 = (uint32_t)rxBuffer[rxIndex]; + /* Give the ownership of the descriptor back to the DMA */ + rxDmaDesc[rxIndex].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V; + +#ifdef ETH_RX_DUMP + rt_kprintf("Rx dump, len= %d\r\n", framelen); + dump_hex(rxBuffer[rxIndex], framelen); +#endif + /* Increment index and wrap around if necessary */ + if (++rxIndex > ETH_RXBUFNB - 1) + { + rxIndex = 0; + } + /* Clear RBU flag to resume processing */ + ETH->DMAC0SR = ETH_DMAC0SR_RBU; + /* Instruct the DMA to poll the receive descriptor list */ + ETH->DMAC0RXDTPR = 0; + } + + return p; +} + +void ETH1_IRQHandler(void) +{ + rt_uint32_t status = 0; + + /* enter interrupt */ + rt_interrupt_enter(); + /* Read DMA status register */ + status = ETH->DMAC0SR; + /* Frame transmitted */ + if (status & ETH_DMAC0SR_TI) + { + /* Clear the Eth DMA Tx IT pending bits */ + ETH->DMAC0SR = ETH_DMAC0SR_TI; + } + /* Frame received */ + else if (status & ETH_DMAC0SR_RI) + { + /* Disable RIE interrupt */ + ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE; + + rt_event_send(&rx_event, status); + } + /* ETH DMA Error */ + if (status & ETH_DMAC0SR_AIS) + { + ETH->DMAC0IER &= ~ETH_DMAC0IER_AIE; + LOG_E("eth dam err"); + } + /* Clear the interrupt flags */ + ETH->DMAC0SR = ETH_DMAC0SR_NIS; + + /* leave interrupt */ + rt_interrupt_leave(); + +} + +static void phy_linkchange() +{ + rt_uint32_t status = 0; + + /* Read status register to acknowledge the interrupt */ + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_INSR); + + + if (status & (RTL8211F_BMSR_LINK_STATUS | RTL8211F_INSR_AN_COMPLETE)) + { + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR); + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR); + if (status & RTL8211F_BMSR_LINK_STATUS) + { + LOG_D("link up"); + + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR); + switch (status & RTL8211F_PHYSR_SPEED) + { + case RTL8211F_PHYSR_SPEED_10MBPS: + { + LOG_D("speed: 10M"); + stm32_eth_device.eth_speed |= PHY_10M; + } + break; + + case RTL8211F_PHYSR_SPEED_100MBPS: + { + LOG_D("speed: 100M"); + stm32_eth_device.eth_speed |= PHY_100M; + } + break; + + case RTL8211F_PHYSR_SPEED_1000MBPS: + { + LOG_D("speed: 1000M"); + stm32_eth_device.eth_speed |= PHY_1000M; + } + break; + + /* Unknown speed */ + default: + rt_kprintf("Invalid speed."); + break; + } + + stm32_eth_device.eth_mode = (status & RTL8211F_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX ; + + update_mac_mode(stm32_eth_device.eth_speed, stm32_eth_device.eth_mode); + /* send link up. */ + eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); + } + else + { + LOG_I("link down"); + eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE); + } + } +} + +#ifdef PHY_USING_INTERRUPT_MODE +static void eth_phy_isr(void *args) +{ + rt_uint32_t status = 0; + + phy_read_reg(RTL8211F_PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status); + LOG_D("phy interrupt status reg is 0x%X", status); + + phy_linkchange(); +} +#endif /* PHY_USING_INTERRUPT_MODE */ + +static void phy_monitor_thread_entry(void *parameter) +{ + rt_uint32_t status = 0; + phy_linkchange(); +#ifdef PHY_USING_INTERRUPT_MODE + /* configuration intterrupt pin */ + rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs"); + rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE); + + /* enable phy interrupt */ + phy_write_reg(RTL8211F_PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK); +#if defined(PHY_INTERRUPT_CTRL_REG) + phy_write_reg( RTL8211F_PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN); +#endif +#else /* PHY_USING_INTERRUPT_MODE */ + stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange, + NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); + if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK) + { + LOG_E("Start link change detection timer failed"); + } +#endif /* PHY_USING_INTERRUPT_MODE */ + while(1) + { + if (rt_event_recv(&rx_event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_FOREVER, &status) == RT_EOK) + { + /* check dma rx buffer */ + if (ETH->DMAC0SR & ETH_DMAC0SR_RI) + { + /* Clear interrupt flag */ + ETH->DMAC0SR = ETH_DMAC0SR_RI; + /* Process all pending packets */ + while (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL) + { + /* trigger lwip receive thread */ + eth_device_ready(&(stm32_eth_device.parent)); + } + } + + /* enable DMA interrupts */ + ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; + } + } +} + +/* Register the EMAC device */ +static int rt_hw_stm32_eth_init(void) +{ + rt_err_t state = RT_EOK; + + /* OUI 00-80-E1 STMICROELECTRONICS. */ + stm32_eth_device.dev_addr[0] = 0x00; + stm32_eth_device.dev_addr[1] = 0x80; + stm32_eth_device.dev_addr[2] = 0xE1; + /* generate MAC addr from 96bit unique ID (only for test). */ + stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4); + stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2); + stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0); + + stm32_eth_device.parent.parent.init = rt_stm32_eth_init; + stm32_eth_device.parent.parent.open = rt_stm32_eth_open; + stm32_eth_device.parent.parent.close = rt_stm32_eth_close; + stm32_eth_device.parent.parent.read = rt_stm32_eth_read; + stm32_eth_device.parent.parent.write = rt_stm32_eth_write; + stm32_eth_device.parent.parent.control = rt_stm32_eth_control; + stm32_eth_device.parent.parent.user_data = RT_NULL; + + stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; + stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; + + rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO); + + /* register eth device */ + state = eth_device_init(&(stm32_eth_device.parent), "e0"); + if (RT_EOK == state) + { + LOG_D("emac device init success"); + } + else + { + LOG_E("emac device init faild: %d", state); + state = -RT_ERROR; + } + + /* start phy monitor */ + rt_thread_t tid; + tid = rt_thread_create("phy", + phy_monitor_thread_entry, + RT_NULL, + 1024, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + state = -RT_ERROR; + } + + return state; +} +INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h new file mode 100644 index 0000000000..40d7db8353 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-20 thread-liu the first version + */ + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + +#include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> +#include <board.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + uint32_t Speed; /*!< Sets the Ethernet speed: 10/100/1000 Mbps. + This parameter can be a value of @ref ETH_Speed */ + uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ +} ETH_MACConfigTypeDef; + +/** + * @brief Transmit descriptor + **/ +typedef struct +{ + uint32_t tdes0; + uint32_t tdes1; + uint32_t tdes2; + uint32_t tdes3; +} TxDmaDesc; + +/** + * @brief Receive descriptor + **/ +typedef struct +{ + uint32_t rdes0; + uint32_t rdes1; + uint32_t rdes2; + uint32_t rdes3; +} RxDmaDesc; + +enum { + PHY_LINK = (1 << 0), + PHY_10M = (1 << 1), + PHY_100M = (1 << 2), + PHY_1000M = (1 << 3), + PHY_FULL_DUPLEX = (1 << 4), + PHY_HALF_DUPLEX = (1 << 5) +}; + + +#define RTL8211F_PHY_ADDR 1 /* PHY address */ + +#define ETH_TXBUFNB 4 /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +#define ETH_TX_BUF_SIZE 1536 /* buffer size for transmit */ +#define ETH_RXBUFNB 4 /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_RX_BUF_SIZE 1536 /* buffer size for receive */ + +#define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk /* ETH_MMCTXIMR register */ + +/* Register access macros */ +#define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk) +#define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk) +#define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk) +#define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk) +#define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk) +#define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk) +#define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk) +#define ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk) +#define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk) +#define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk) +#define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk) +#define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk) + +/* Transmit normal descriptor (read format) */ +#define ETH_TDES0_BUF1AP 0xFFFFFFFF +#define ETH_TDES1_BUF2AP 0xFFFFFFFF +#define ETH_TDES2_IOC 0x80000000 +#define ETH_TDES2_TTSE 0x40000000 +#define ETH_TDES2_B2L 0x3FFF0000 +#define ETH_TDES2_VTIR 0x0000C000 +#define ETH_TDES2_B1L 0x00003FFF +#define ETH_TDES3_OWN 0x80000000 +#define ETH_TDES3_CTXT 0x40000000 +#define ETH_TDES3_FD 0x20000000 +#define ETH_TDES3_LD 0x10000000 +#define ETH_TDES3_CPC 0x0C000000 +#define ETH_TDES3_SAIC 0x03800000 +#define ETH_TDES3_THL 0x00780000 +#define ETH_TDES3_TSE 0x00040000 +#define ETH_TDES3_CIC 0x00030000 +#define ETH_TDES3_FL 0x00007FFF + +/* Transmit normal descriptor (write-back format) */ +#define ETH_TDES0_TTSL 0xFFFFFFFF +#define ETH_TDES1_TTSH 0xFFFFFFFF +#define ETH_TDES3_OWN 0x80000000 +#define ETH_TDES3_CTXT 0x40000000 +#define ETH_TDES3_FD 0x20000000 +#define ETH_TDES3_LD 0x10000000 +#define ETH_TDES3_TTSS 0x00020000 +#define ETH_TDES3_ES 0x00008000 +#define ETH_TDES3_JT 0x00004000 +#define ETH_TDES3_FF 0x00002000 +#define ETH_TDES3_PCE 0x00001000 +#define ETH_TDES3_LOC 0x00000800 +#define ETH_TDES3_NC 0x00000400 +#define ETH_TDES3_LC 0x00000200 +#define ETH_TDES3_EC 0x00000100 +#define ETH_TDES3_CC 0x000000F0 +#define ETH_TDES3_ED 0x00000008 +#define ETH_TDES3_UF 0x00000004 +#define ETH_TDES3_DB 0x00000002 +#define ETH_TDES3_IHE 0x00000001 + +/* Transmit context descriptor */ +#define ETH_TDES0_TTSL 0xFFFFFFFF +#define ETH_TDES1_TTSH 0xFFFFFFFF +#define ETH_TDES2_IVT 0xFFFF0000 +#define ETH_TDES2_MSS 0x00003FFF +#define ETH_TDES3_OWN 0x80000000 +#define ETH_TDES3_CTXT 0x40000000 +#define ETH_TDES3_OSTC 0x08000000 +#define ETH_TDES3_TCMSSV 0x04000000 +#define ETH_TDES3_CDE 0x00800000 +#define ETH_TDES3_IVLTV 0x00020000 +#define ETH_TDES3_VLTV 0x00010000 +#define ETH_TDES3_VT 0x0000FFFF + +/* Receive normal descriptor (read format) */ +#define ETH_RDES0_BUF1AP 0xFFFFFFFF +#define ETH_RDES2_BUF2AP 0xFFFFFFFF +#define ETH_RDES3_OWN 0x80000000 +#define ETH_RDES3_IOC 0x40000000 +#define ETH_RDES3_BUF2V 0x02000000 +#define ETH_RDES3_BUF1V 0x01000000 + +/* Receive normal descriptor (write-back format) */ +#define ETH_RDES0_IVT 0xFFFF0000 +#define ETH_RDES0_OVT 0x0000FFFF +#define ETH_RDES1_OPC 0xFFFF0000 +#define ETH_RDES1_TD 0x00008000 +#define ETH_RDES1_TSA 0x00004000 +#define ETH_RDES1_PV 0x00002000 +#define ETH_RDES1_PFT 0x00001000 +#define ETH_RDES1_PMT 0x00000F00 +#define ETH_RDES1_IPCE 0x00000080 +#define ETH_RDES1_IPCB 0x00000040 +#define ETH_RDES1_IPV6 0x00000020 +#define ETH_RDES1_IPV4 0x00000010 +#define ETH_RDES1_IPHE 0x00000008 +#define ETH_RDES1_PT 0x00000007 +#define ETH_RDES2_L3L4FM 0xE0000000 +#define ETH_RDES2_L4FM 0x10000000 +#define ETH_RDES2_L3FM 0x08000000 +#define ETH_RDES2_MADRM 0x07F80000 +#define ETH_RDES2_HF 0x00040000 +#define ETH_RDES2_DAF 0x00020000 +#define ETH_RDES2_SAF 0x00010000 +#define ETH_RDES2_VF 0x00008000 +#define ETH_RDES2_ARPRN 0x00000400 +#define ETH_RDES3_OWN 0x80000000 +#define ETH_RDES3_CTXT 0x40000000 +#define ETH_RDES3_FD 0x20000000 +#define ETH_RDES3_LD 0x10000000 +#define ETH_RDES3_RS2V 0x08000000 +#define ETH_RDES3_RS1V 0x04000000 +#define ETH_RDES3_RS0V 0x02000000 +#define ETH_RDES3_CE 0x01000000 +#define ETH_RDES3_GP 0x00800000 +#define ETH_RDES3_RWT 0x00400000 +#define ETH_RDES3_OE 0x00200000 +#define ETH_RDES3_RE 0x00100000 +#define ETH_RDES3_DE 0x00080000 +#define ETH_RDES3_LT 0x00070000 +#define ETH_RDES3_ES 0x00008000 +#define ETH_RDES3_PL 0x00007FFF + +/* Receive context descriptor */ +#define ETH_RDES0_RTSL 0xFFFFFFFF +#define ETH_RDES1_RTSH 0xFFFFFFFF +#define ETH_RDES3_OWN 0x80000000 +#define ETH_RDES3_CTXT 0x40000000 + +#define RTL8211F_BMCR ((uint16_t)0x0000U) /* Basic Mode Control Register. */ +#define RTL8211F_BMSR ((uint16_t)0x0001U) /* Basic Mode Status Register. */ +#define RTL8211F_PHYID1 ((uint16_t)0x0002U) /* PHY Identifier Register 1. */ +#define RTL8211F_PHYID2 ((uint16_t)0x0003U) /* PHY Identifier Register 2. */ +#define RTL8211F_ANAR ((uint16_t)0x0004U) /* Auto-Negotiation Advertising Register. */ +#define RTL8211F_ANLPAR ((uint16_t)0x0005U) /* Auto-Negotiation Link Partner Ability Register. */ +#define RTL8211F_ANER ((uint16_t)0x0006U) /* Auto-Negotiation Expansion Register.*/ +#define RTL8211F_ANNPTR ((uint16_t)0x0007U) /* Auto-Negotiation Next Page Transmit Register.*/ +#define RTL8211F_ANNPRR ((uint16_t)0x0008U) /* Auto-Negotiation Next Page Receive Register. */ +#define RTL8211F_GBCR ((uint16_t)0x0009U) /* 1000Base-T Control Register. */ +#define RTL8211F_GBSR ((uint16_t)0x000AU) /* 1000Base-T Status Register. */ +#define RTL8211F_MMDACR ((uint16_t)0x000DU) /* MMD Access Control Register. */ +#define RTL8211F_MMDAADR ((uint16_t)0x000EU) /* MMD Access Address Data Register. */ +#define RTL8211F_GBESR ((uint16_t)0x000FU) /* 1000Base-T Extended Status Register. */ +#define RTL8211F_LCR ((uint16_t)0x0010U) /* LED Control Register. */ +#define RTL8211F_INER ((uint16_t)0x0012U) /* Interrupt Enable Register. */ +#define RTL8211F_PHYSCR ((uint16_t)0x0014U) /* PHY Special Cofig Register */ +#define RTL8211F_PHYCR1 ((uint16_t)0x0018U) /* PHY Specific Control Register 1. */ +#define RTL8211F_PHYCR2 ((uint16_t)0x0019U) /* PHY Specific Control Register 2. */ +#define RTL8211F_PHYSR ((uint16_t)0x001AU) /* PHY Specific Status Register. */ +#define RTL8211F_INSR ((uint16_t)0x001DU) /* Interrupt Status Register. */ +#define RTL8211F_PAGSR ((uint16_t)0x001FU) /* Page Select Register. */ + +/* Basic Mode Control register */ +#define RTL8211F_BMCR_RESET 0x8000 +#define RTL8211F_BMCR_LOOPBACK 0x4000 +#define RTL8211F_BMCR_SPEED_SEL_LSB 0x2000 +#define RTL8211F_BMCR_AN_EN 0x1000 +#define RTL8211F_BMCR_POWER_DOWN 0x0800 +#define RTL8211F_BMCR_ISOLATE 0x0400 +#define RTL8211F_BMCR_RESTART_AN 0x0200 +#define RTL8211F_BMCR_DUPLEX_MODE 0x0100 +#define RTL8211F_BMCR_COL_TEST 0x0080 +#define RTL8211F_BMCR_SPEED_SEL_MSB 0x0040 +#define RTL8211F_BMCR_UNI_DIR_EN 0x0020 + +/* Basic Mode Status register */ +#define RTL8211F_BMSR_100BT4 0x8000 +#define RTL8211F_BMSR_100BTX_FD 0x4000 +#define RTL8211F_BMSR_100BTX_HD 0x2000 +#define RTL8211F_BMSR_10BT_FD 0x1000 +#define RTL8211F_BMSR_10BT_HD 0x0800 +#define RTL8211F_BMSR_100BT2_FD 0x0400 +#define RTL8211F_BMSR_100BT2_HD 0x0200 +#define RTL8211F_BMSR_EXTENDED_STATUS 0x0100 +#define RTL8211F_BMSR_UNI_DIR_CAPABLE 0x0080 +#define RTL8211F_BMSR_PREAMBLE_SUPPR 0x0040 +#define RTL8211F_BMSR_AN_COMPLETE 0x0020 +#define RTL8211F_BMSR_REMOTE_FAULT 0x0010 +#define RTL8211F_BMSR_AN_CAPABLE 0x0008 +#define RTL8211F_BMSR_LINK_STATUS 0x0004 +#define RTL8211F_BMSR_JABBER_DETECT 0x0002 +#define RTL8211F_BMSR_EXTENDED_CAPABLE 0x0001 + +/* PHY Identifier 1 register */ +#define RTL8211F_PHYID1_OUI_MSB 0xFFFF +#define RTL8211F_PHYID1_OUI_MSB_DEFAULT 0x001C + +/* PHY Identifier 2 register */ +#define RTL8211F_PHYID2_OUI_LSB 0xFC00 +#define RTL8211F_PHYID2_OUI_LSB_DEFAULT 0xC800 +#define RTL8211F_PHYID2_MODEL_NUM 0x03F0 +#define RTL8211F_PHYID2_MODEL_NUM_DEFAULT 0x0110 +#define RTL8211F_PHYID2_REVISION_NUM 0x000F +#define RTL8211F_PHYID2_REVISION_NUM_DEFAULT 0x0006 + +/* Auto-Negotiation Advertisement register */ +#define RTL8211F_ANAR_NEXT_PAGE 0x8000 +#define RTL8211F_ANAR_REMOTE_FAULT 0x2000 +#define RTL8211F_ANAR_ASYM_PAUSE 0x0800 +#define RTL8211F_ANAR_PAUSE 0x0400 +#define RTL8211F_ANAR_100BT4 0x0200 +#define RTL8211F_ANAR_100BTX_FD 0x0100 +#define RTL8211F_ANAR_100BTX_HD 0x0080 +#define RTL8211F_ANAR_10BT_FD 0x0040 +#define RTL8211F_ANAR_10BT_HD 0x0020 +#define RTL8211F_ANAR_SELECTOR 0x001F +#define RTL8211F_ANAR_SELECTOR_DEFAULT 0x0001 + +/* Auto-Negotiation Link Partner Ability register */ +#define RTL8211F_ANLPAR_NEXT_PAGE 0x8000 +#define RTL8211F_ANLPAR_ACK 0x4000 +#define RTL8211F_ANLPAR_REMOTE_FAULT 0x2000 +#define RTL8211F_ANLPAR_ASYM_PAUSE 0x0800 +#define RTL8211F_ANLPAR_PAUSE 0x0400 +#define RTL8211F_ANLPAR_100BT4 0x0200 +#define RTL8211F_ANLPAR_100BTX_FD 0x0100 +#define RTL8211F_ANLPAR_100BTX_HD 0x0080 +#define RTL8211F_ANLPAR_10BT_FD 0x0040 +#define RTL8211F_ANLPAR_10BT_HD 0x0020 +#define RTL8211F_ANLPAR_SELECTOR 0x001F +#define RTL8211F_ANLPAR_SELECTOR_DEFAULT 0x0001 + +/* Auto-Negotiation Expansion register */ +#define RTL8211F_ANER_RX_NP_LOCATION_ABLE 0x0040 +#define RTL8211F_ANER_RX_NP_LOCATION 0x0020 +#define RTL8211F_ANER_PAR_DETECT_FAULT 0x0010 +#define RTL8211F_ANER_LP_NEXT_PAGE_ABLE 0x0008 +#define RTL8211F_ANER_NEXT_PAGE_ABLE 0x0004 +#define RTL8211F_ANER_PAGE_RECEIVED 0x0002 +#define RTL8211F_ANER_LP_AN_ABLE 0x0001 + +/* Auto-Negotiation Next Page Transmit register */ +#define RTL8211F_ANNPTR_NEXT_PAGE 0x8000 +#define RTL8211F_ANNPTR_MSG_PAGE 0x2000 +#define RTL8211F_ANNPTR_ACK2 0x1000 +#define RTL8211F_ANNPTR_TOGGLE 0x0800 +#define RTL8211F_ANNPTR_MESSAGE 0x07FF + +/* Auto-Negotiation Next Page Receive register */ +#define RTL8211F_ANNPRR_NEXT_PAGE 0x8000 +#define RTL8211F_ANNPRR_ACK 0x4000 +#define RTL8211F_ANNPRR_MSG_PAGE 0x2000 +#define RTL8211F_ANNPRR_ACK2 0x1000 +#define RTL8211F_ANNPRR_TOGGLE 0x0800 +#define RTL8211F_ANNPRR_MESSAGE 0x07FF + +/* 1000Base-T Control register */ +#define RTL8211F_GBCR_TEST_MODE 0xE000 +#define RTL8211F_GBCR_MS_MAN_CONF_EN 0x1000 +#define RTL8211F_GBCR_MS_MAN_CONF_VAL 0x0800 +#define RTL8211F_GBCR_PORT_TYPE 0x0400 +#define RTL8211F_GBCR_1000BT_FD 0x0200 + +/* 1000Base-T Status register */ +#define RTL8211F_GBSR_MS_CONF_FAULT 0x8000 +#define RTL8211F_GBSR_MS_CONF_RES 0x4000 +#define RTL8211F_GBSR_LOCAL_RECEIVER_STATUS 0x2000 +#define RTL8211F_GBSR_REMOTE_RECEIVER_STATUS 0x1000 +#define RTL8211F_GBSR_LP_1000BT_FD 0x0800 +#define RTL8211F_GBSR_LP_1000BT_HD 0x0400 +#define RTL8211F_GBSR_IDLE_ERR_COUNT 0x00FF + +/* MMD Access Control register */ +#define RTL8211F_MMDACR_FUNC 0xC000 +#define RTL8211F_MMDACR_FUNC_ADDR 0x0000 +#define RTL8211F_MMDACR_FUNC_DATA_NO_POST_INC 0x4000 +#define RTL8211F_MMDACR_FUNC_DATA_POST_INC_RW 0x8000 +#define RTL8211F_MMDACR_FUNC_DATA_POST_INC_W 0xC000 +#define RTL8211F_MMDACR_DEVAD 0x001F + +/* 1000Base-T Extended Status register */ +#define RTL8211F_GBESR_1000BX_FD 0x8000 +#define RTL8211F_GBESR_1000BX_HD 0x4000 +#define RTL8211F_GBESR_1000BT_FD 0x2000 +#define RTL8211F_GBESR_1000BT_HD 0x1000 + +/* Interrupt Enable register */ +#define RTL8211F_INER_JABBER 0x0400 +#define RTL8211F_INER_ALDPS_STATE 0x0200 +#define RTL8211F_INER_PME 0x0080 +#define RTL8211F_INER_PHY_REG_ACCESS 0x0020 +#define RTL8211F_INER_LINK_STATUS 0x0010 +#define RTL8211F_INER_AN_COMPLETE 0x0008 +#define RTL8211F_INER_PAGE_RECEIVED 0x0004 +#define RTL8211F_INER_AN_ERROR 0x0001 + +/* PHY Specific Control 1 register */ +#define RTL8211F_PHYCR1_PHYAD_0_EN 0x2000 +#define RTL8211F_PHYCR1_MDI_MODE_MANUAL_CONFIG 0x0200 +#define RTL8211F_PHYCR1_MDI_MODE 0x0100 +#define RTL8211F_PHYCR1_TX_CRS_EN 0x0080 +#define RTL8211F_PHYCR1_PHYAD_NON_ZERO_DETECT 0x0040 +#define RTL8211F_PHYCR1_PREAMBLE_CHECK_EN 0x0010 +#define RTL8211F_PHYCR1_JABBER_DETECT_EN 0x0008 +#define RTL8211F_PHYCR1_ALDPS_EN 0x0004 + +/* PHY Specific Control 2 register */ +#define RTL8211F_PHYCR2_CLKOUT_FREQ_SEL 0x0800 +#define RTL8211F_PHYCR2_CLKOUT_SSC_EN 0x0080 +#define RTL8211F_PHYCR2_RXC_SSC_EN 0x0008 +#define RTL8211F_PHYCR2_RXC_EN 0x0002 +#define RTL8211F_PHYCR2_CLKOUT_EN 0x0001 + +/* PHY Specific Status register */ +#define RTL8211F_PHYSR_ALDPS_STATE 0x4000 +#define RTL8211F_PHYSR_MDI_PLUG 0x2000 +#define RTL8211F_PHYSR_NWAY_EN 0x1000 +#define RTL8211F_PHYSR_MASTER_MODE 0x0800 +#define RTL8211F_PHYSR_EEE_CAPABLE 0x0100 +#define RTL8211F_PHYSR_RX_FLOW_EN 0x0080 +#define RTL8211F_PHYSR_TX_FLOW_EN 0x0040 +#define RTL8211F_PHYSR_SPEED 0x0030 +#define RTL8211F_PHYSR_SPEED_10MBPS 0x0000 +#define RTL8211F_PHYSR_SPEED_100MBPS 0x0010 +#define RTL8211F_PHYSR_SPEED_1000MBPS 0x0020 +#define RTL8211F_PHYSR_DUPLEX 0x0008 +#define RTL8211F_PHYSR_LINK 0x0004 +#define RTL8211F_PHYSR_MDI_CROSSOVER_STATUS 0x0002 +#define RTL8211F_PHYSR_JABBER 0x0001 + +/* Interrupt Status register */ +#define RTL8211F_INSR_JABBER 0x0400 +#define RTL8211F_INSR_ALDPS_STATE 0x0200 +#define RTL8211F_INSR_PME 0x0080 +#define RTL8211F_INSR_PHY_REG_ACCESS 0x0020 +#define RTL8211F_INSR_LINK_STATUS 0x0010 +#define RTL8211F_INSR_AN_COMPLETE 0x0008 +#define RTL8211F_INSR_PAGE_RECEIVED 0x0004 +#define RTL8211F_INSR_AN_ERROR 0x0001 + +/* Page Select register */ +#define RTL8211F_PAGSR_PAGE_SEL 0x0007 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c index 95e385f1b8..c5f26596cc 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c @@ -19,6 +19,8 @@ #define LOG_TAG "drv.pmic" #include <drv_log.h> +#define I2C_NAME "i2c3" + static struct rt_i2c_bus_device *pmic_dev = RT_NULL; /* i2c read reg */ @@ -796,47 +798,47 @@ static rt_err_t rt_hw_pmic_init_register(void) stpmu1_write_reg(BUCK_ICC_TURNOFF_REG, 0x30); stpmu1_write_reg(LDO_ICC_TURNOFF_REG, 0x3b); - /* vddcore */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200); - STPMU1_Regulator_Enable(STPMU1_BUCK1); + /* vddcore */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200); + STPMU1_Regulator_Enable(STPMU1_BUCK1); - /* vddddr */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350); - STPMU1_Regulator_Enable(STPMU1_BUCK2); + /* vddddr */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350); + STPMU1_Regulator_Enable(STPMU1_BUCK2); - /* vdd */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300); - STPMU1_Regulator_Enable(STPMU1_BUCK3); + /* vdd */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300); + STPMU1_Regulator_Enable(STPMU1_BUCK3); - /* 3v3 */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300); - STPMU1_Regulator_Enable(STPMU1_BUCK4); +// /* 3v3 */ +// STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300); +// STPMU1_Regulator_Enable(STPMU1_BUCK4); - /* vdda */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 2900); - STPMU1_Regulator_Enable(STPMU1_LDO1); + /* 1v8_audio */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 1800); + STPMU1_Regulator_Enable(STPMU1_LDO1); - /* 2v8 */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2800); - STPMU1_Regulator_Enable(STPMU1_LDO2); + /* vdd_emmc */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2900); + STPMU1_Regulator_Enable(STPMU1_LDO2); - /* vtt_ddr lod3 mode buck2/2 */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF); - STPMU1_Regulator_Enable(STPMU1_LDO3); + /* vdd1_ddr */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF); + STPMU1_Regulator_Enable(STPMU1_LDO3); - /* vdd_usb */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300); - STPMU1_Regulator_Enable(STPMU1_LDO4); + /* vdd_usb */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300); + STPMU1_Regulator_Enable(STPMU1_LDO4); - /* vdd_sd */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900); - STPMU1_Regulator_Enable(STPMU1_LDO5); + /* vdda */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900); + STPMU1_Regulator_Enable(STPMU1_LDO5); - /* 1v8 */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 1800); - STPMU1_Regulator_Enable(STPMU1_LDO6); + /* 2v8 */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 2800); + STPMU1_Regulator_Enable(STPMU1_LDO6); - STPMU1_Regulator_Enable(STPMU1_VREFDDR); + STPMU1_Regulator_Enable(STPMU1_VREFDDR); return RT_EOK; } @@ -884,7 +886,7 @@ static int pmic_init(void) { BSP_PMIC_MspInit(); - result = rt_hw_pmic_init("i2c3"); + result = rt_hw_pmic_init(I2C_NAME); if(result != RT_EOK) { LOG_D("stpmic init failed: %02x", result); @@ -893,10 +895,7 @@ static int pmic_init(void) } rt_hw_pmic_init_register(); - } - - if(IS_ENGINEERING_BOOT_MODE()) - { + __HAL_RCC_VREF_CLK_ENABLE(); HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE); HAL_SYSCFG_EnableVREFBUF(); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c new file mode 100644 index 0000000000..3e5085c3cd --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-16 thread-liu first version + */ + +#include "board.h" +#include "drv_sdio.h" +#include <dfs_fs.h> + +#ifdef BSP_USING_SDMMC + +//#define DRV_DEBUG +#define DBG_TAG "drv.sdio" +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ +#include <rtdbg.h> + +static SD_HandleTypeDef hsd; +static struct rt_mmcsd_host *host; +#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000) + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct stm32_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; +}; + +/* SYSRAM SDMMC1/2 accesses */ +#if defined(__CC_ARM) || defined(__CLANG_ARM) +rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFC0000))); +#elif defined(__ICCARM__) +#pragma location=0x2FFC0000 +rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; +#elif defined(__GNUC__) +rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFC0000))); +#endif + +/** + * @brief This function get order from sdio. + * @param data + * @retval sdio order + */ +static int get_order(rt_uint32_t data) +{ + int order = 0; + + switch (data) + { + case 1: + order = 0; + break; + case 2: + order = 1; + break; + case 4: + order = 2; + break; + case 8: + order = 3; + break; + case 16: + order = 4; + break; + case 32: + order = 5; + break; + case 64: + order = 6; + break; + case 128: + order = 7; + break; + case 256: + order = 8; + break; + case 512: + order = 9; + break; + case 1024: + order = 10; + break; + case 2048: + order = 11; + break; + case 4096: + order = 12; + break; + case 8192: + order = 13; + break; + case 16384: + order = 14; + break; + default : + order = 0; + break; + } + return order; +} + +/** + * @brief This function wait sdio cmd completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait cmd completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + + cmd->resp[0] = hw_sdio->resp1; + cmd->resp[1] = hw_sdio->resp2; + cmd->resp[2] = hw_sdio->resp3; + cmd->resp[3] = hw_sdio->resp4; + + if (status & SDIO_ERRORS) + { + if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + + if (status & SDMMC_STA_CTIMEOUT) + { + cmd->err = -RT_ETIMEOUT; + } + + if (status & SDMMC_STA_DCRCFAIL) + { + data->err = -RT_ERROR; + } + + if (status & SDMMC_STA_DTIMEOUT) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status & SDMMC_STA_CCRCFAIL ? "CCRCFAIL " : "", + status & SDMMC_STA_DCRCFAIL ? "DCRCFAIL " : "", + status & SDMMC_STA_CTIMEOUT ? "CTIMEOUT " : "", + status & SDMMC_STA_DTIMEOUT ? "DTIMEOUT " : "", + status & SDMMC_STA_TXUNDERR ? "TXUNDERR " : "", + status & SDMMC_STA_RXOVERR ? "RXOVERR " : "", + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + } + + } + else + { + cmd->err = RT_EOK; + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; + + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + + /* config cmd reg */ + reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN; + if (resp_type(cmd) == RESP_NONE) + reg_cmd |= SDMMC_RESPONSE_NO; + else if (resp_type(cmd) == RESP_R2) + reg_cmd |= SDMMC_RESPONSE_LONG; + else + reg_cmd |= SDMMC_RESPONSE_SHORT; + + hw_sdio->mask |= SDIO_MASKR_ALL; + + /* data pre configuration */ + if (data != RT_NULL) + { + hw_sdio->dctrl = 0; + hw_sdio->mask &= ~(SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE); + reg_cmd |= SDMMC_CMD_CMDTRANS; + hw_sdio->dtimer = HW_SDIO_DATATIMEOUT; + hw_sdio->dlen = data->blks * data->blksize; + hw_sdio->dctrl = (get_order(data->blksize)<<4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0); + hw_sdio->idmabase0r = (rt_uint32_t)cache_buf; + hw_sdio->idmatrlr = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + } + + hw_sdio->arg = cmd->arg; + hw_sdio->cmd = reg_cmd; + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* Waiting for data to be sent to completion */ + if (data != RT_NULL) + { + volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS; + + while (count && (hw_sdio->sta & SDMMC_STA_DPSMACT)) + { + count--; + } + if ((count == 0) || (hw_sdio->sta & SDIO_ERRORS)) + { + cmd->err = -RT_ERROR; + } + } + + /* close irq, keep sdio irq */ + hw_sdio->mask = hw_sdio->mask & SDMMC_IT_SDIOIT ? SDMMC_IT_SDIOIT : 0x00; + + /* data post configuration */ + if (data != RT_NULL) + { + if (data->flags & DATA_DIR_READ) + { + rt_memcpy(data->buf, cache_buf, data->blks * data->blksize); + } + } +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + if (data->flags & DATA_DIR_WRITE) + { + rt_memcpy(cache_buf, data->buf, size); + } + } + + rthw_sdio_send_command(sdio, &pkg); + } + + if (req->stop != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->sta; + + /* clear irq flag*/ + hw_sdio->icr = intstatus; + + rt_event_send(&sdio->event, intstatus); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t temp, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + LOG_D("clk:%dK width:%s%s%s power:%s%s%s", + clk/1000, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "" + ); + + RTHW_SDIO_LOCK(sdio); + + clk_src = SDIO_CLOCK_FREQ; + + if (clk > 0) + { + if (clk > host->freq_max) + { + clk = host->freq_max; + } + temp = DIV_ROUND_UP(clk_src, 2 * clk); + if (temp > 0x3FF) + { + temp = 0x3FF; + } + } + + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + temp |= SDMMC_BUS_WIDE_8B; + } + else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + temp |= SDMMC_BUS_WIDE_4B; + } + else + { + temp |= SDMMC_BUS_WIDE_1B; + } + + hw_sdio->clkcr = temp; + + if (io_cfg->power_mode == MMCSD_POWER_ON) + hw_sdio->power |= SDMMC_POWER_PWRCTRL; + + RTHW_SDIO_UNLOCK(sdio); +} + +static const struct rt_mmcsd_host_ops ops = +{ + rthw_sdio_request, + rthw_sdio_iocfg, + RT_NULL, + RT_NULL, +}; + +/** + * @brief This function create mmcsd host. + * @param sdio_des stm32_sdio_des + * @retval rt_mmcsd_host + */ +struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if (sdio_des == RT_NULL) + { + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("malloc rthw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("alloc host fail"); + goto err; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des)); + + sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO_BASE_ADDRESS; + + rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + /* set host default attributes */ + host->ops = &ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */ +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED; +#endif + + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + /* ready to change */ + mmcsd_change(host); + + return host; + +err: + if (sdio) + { + rt_free(sdio); + } + + return RT_NULL; +} + +void SDMMC1_IRQHandler(void) +{ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host); + + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ + struct stm32_sdio_des sdio_des; + + hsd.Instance = SDMMC1; + HAL_SD_MspInit(&hsd); + + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return RT_NULL; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +int mnt_init(void) +{ + rt_device_t sd = RT_NULL; + + rt_thread_delay(RT_TICK_PER_SECOND); + + sd = rt_device_find("sd0"); + if (sd == RT_NULL) + { + rt_kprintf("can't find sd0 device!\n"); + return RT_ERROR; + } + + if (dfs_mount("sd0", "/", "elm", 0, 0) != 0) + { + rt_kprintf("file system mount failed!\n"); + } + else + { + rt_kprintf("file system mount success!\n"); + } + + return RT_EOK; +} +INIT_ENV_EXPORT(mnt_init); + +#endif /* BSP_USING_SDMMC */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h new file mode 100644 index 0000000000..a4428e4e71 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-16 thread-liu first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include <rtthread.h> +#include "rtdevice.h" +#include <rthw.h> +#include <drv_common.h> +#include <string.h> +#include <drivers/mmcsd_core.h> +#include <drivers/sdio.h> + +#define SDIO_BUFF_SIZE 4096 +#define SDIO_ALIGN_LEN 32 + +#ifndef SDIO_BASE_ADDRESS +#define SDIO_BASE_ADDRESS (SDMMC1) +#endif + +#ifndef SDIO_CLOCK_FREQ +#define SDIO_CLOCK_FREQ (99U * 1000 * 1000) +#endif + +#ifndef SDIO_BUFF_SIZE +#define SDIO_BUFF_SIZE (4096) +#endif + +#ifndef SDIO_ALIGN_LEN +#define SDIO_ALIGN_LEN (32) +#endif + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (50 * 1000 * 1000) +#endif + +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +#define SDMMC_POWER_OFF (0x00U) +#define SDMMC_POWER_UP (0x02U) +#define SDMMC_POWER_ON (0x03U) + +#define SDIO_ERRORS \ + (SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \ + SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \ + SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \ + SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL) + +#define SDIO_MASKR_ALL \ + (SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \ + SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \ + SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE) + +#define HW_SDIO_DATATIMEOUT (0xFFFFFFFFU) + +struct stm32_sdio +{ + volatile rt_uint32_t power; /* offset 0x00 */ + volatile rt_uint32_t clkcr; /* offset 0x04 */ + volatile rt_uint32_t arg; /* offset 0x08 */ + volatile rt_uint32_t cmd; /* offset 0x0C */ + volatile rt_uint32_t respcmd; /* offset 0x10 */ + volatile rt_uint32_t resp1; /* offset 0x14 */ + volatile rt_uint32_t resp2; /* offset 0x18 */ + volatile rt_uint32_t resp3; /* offset 0x1C */ + volatile rt_uint32_t resp4; /* offset 0x20 */ + volatile rt_uint32_t dtimer; /* offset 0x24 */ + volatile rt_uint32_t dlen; /* offset 0x28 */ + volatile rt_uint32_t dctrl; /* offset 0x2C */ + volatile rt_uint32_t dcount; /* offset 0x30 */ + volatile rt_uint32_t sta; /* offset 0x34 */ + volatile rt_uint32_t icr; /* offset 0x38 */ + volatile rt_uint32_t mask; /* offset 0x3C */ + volatile rt_uint32_t acktimer; /* offset 0x40 */ + volatile rt_uint32_t reserved0[3]; /* offset 0x44 ~ 0x4C */ + volatile rt_uint32_t idmatrlr; /* offset 0x50 */ + volatile rt_uint32_t idmabsizer; /* offset 0x54 */ + volatile rt_uint32_t idmabase0r; /* offset 0x58 */ + volatile rt_uint32_t idmabase1r; /* offset 0x5C */ + volatile rt_uint32_t reserved1[1]; /* offset 0x60 */ + volatile rt_uint32_t idmalar; + volatile rt_uint32_t idmabar; + volatile rt_uint32_t reserved2[5]; + volatile rt_uint32_t fifo; + volatile rt_uint32_t reserved3[220]; + volatile rt_uint32_t verr; + volatile rt_uint32_t ipidr; + volatile rt_uint32_t sidr; +}; + +typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio); + +struct stm32_sdio_des +{ + struct stm32_sdio *hw_sdio; + sdio_clk_get clk_get; +}; + +/* stm32 sdio dirver class */ +struct stm32_sdio_class +{ + struct stm32_sdio_des *des; + const struct stm32_sdio_config *cfg; + struct rt_mmcsd_host host; +}; + +extern void stm32_mmcsd_change(void); + +#endif /* __DRV_SDIO_H__ */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/template.uvoptx b/bsp/stm32/stm32mp157a-st-discovery/template.uvoptx index cd7d5cc09b..b43797349c 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/template.uvoptx +++ b/bsp/stm32/stm32mp157a-st-discovery/template.uvoptx @@ -10,7 +10,7 @@ <aExt>*.s*; *.src; *.a*</aExt> <oExt>*.obj; *.o</oExt> <lExt>*.lib</lExt> - <tExt>*.txt; *.h; *.inc</tExt> + <tExt>*.txt; *.h; *.inc; *.md</tExt> <pExt>*.plm</pExt> <CppX>*.cpp</CppX> <nMigrate>0</nMigrate> @@ -125,7 +125,7 @@ <SetRegEntry> <Number>0</Number> <Key>ST-LINKIII-KEIL_SWO</Key> - <Name>-U066DFF343339415043182234 -O206 -SF10000 -C0 -A2 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10020000 -FC1000 -FN0</Name> + <Name>-U0666FF343339415043182420 -O206 -SF10000 -C0 -A2 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10030000 -FC1000 -FN0</Name> </SetRegEntry> </TargetDriverDllRegistry> <Breakpoint/> diff --git a/bsp/stm32/stm32mp157a-st-discovery/template.uvprojx b/bsp/stm32/stm32mp157a-st-discovery/template.uvprojx index bc7e6847ac..8c076e73ef 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/template.uvprojx +++ b/bsp/stm32/stm32mp157a-st-discovery/template.uvprojx @@ -276,7 +276,7 @@ <OCR_RVCT4> <Type>1</Type> <StartAddress>0x10000000</StartAddress> - <Size>0x20000</Size> + <Size>0x30000</Size> </OCR_RVCT4> <OCR_RVCT5> <Type>1</Type> @@ -300,8 +300,8 @@ </OCR_RVCT8> <OCR_RVCT9> <Type>0</Type> - <StartAddress>0x10020000</StartAddress> - <Size>0x20000</Size> + <StartAddress>0x10030000</StartAddress> + <Size>0x10000</Size> </OCR_RVCT9> <OCR_RVCT10> <Type>0</Type> @@ -397,11 +397,6 @@ <Layers> <Layer> <LayName><Project Info></LayName> - <LayDesc></LayDesc> - <LayUrl></LayUrl> - <LayKeys></LayKeys> - <LayCat></LayCat> - <LayLic></LayLic> <LayTarg>0</LayTarg> <LayPrjMark>1</LayPrjMark> </Layer> diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h index 424bdc02a2..39709fbedc 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h @@ -34,16 +34,16 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED #define HAL_DAC_MODULE_ENABLED -/*#define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DCMI_MODULE_ENABLED /*#define HAL_DSI_MODULE_ENABLED */ -/*#define HAL_DFSDM_MODULE_ENABLED */ +#define HAL_DFSDM_MODULE_ENABLED /*#define HAL_DTS_MODULE_ENABLED */ /*#define HAL_ETH_MODULE_ENABLED */ -/*#define HAL_FDCAN_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ +#define HAL_FDCAN_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED /*#define HAL_HCD_MODULE_ENABLED */ #define HAL_HSEM_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED @@ -55,14 +55,14 @@ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ -/*#define HAL_QSPI_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ -/*#define HAL_SAI_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED /*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPDIFRX_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_TAMP_MODULE_ENABLED */ @@ -153,6 +153,8 @@ #define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ +#define USE_SD_TRANSCEIVER 1U + /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c index 5e6a4a3d34..20f6aa2d63 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -26,7 +26,15 @@ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ - +DMA_HandleTypeDef hdma_hash_in = {0}; +DMA_HandleTypeDef hdma_cryp_in = {0}; +DMA_HandleTypeDef hdma_cryp_out = {0}; +DMA_HandleTypeDef hdma_sai2_a = {0}; +DMA_HandleTypeDef hdma_sai2_b = {0}; +DMA_HandleTypeDef hdma_sai4_a = {0}; +DMA_HandleTypeDef hdma_spdifrx_rx = {0}; +DMA_HandleTypeDef hdma_dfsdm1_flt0 = {0}; +DMA_HandleTypeDef hdma_dfsdm1_flt1 = {0}; /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ @@ -73,10 +81,10 @@ void HAL_MspInit(void) /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ -#if !defined(BSP_USING_OPENAMP) - __HAL_RCC_SYSRAM_CLK_ENABLE(); - __HAL_RCC_RETRAM_CLK_ENABLE(); -#endif + if (IS_ENGINEERING_BOOT_MODE()) + { + __HAL_RCC_SYSRAM_CLK_ENABLE(); + } HAL_NVIC_SetPriority(RCC_WAKEUP_IRQn, 0, 0); HAL_NVIC_EnableIRQ(RCC_WAKEUP_IRQn); @@ -289,7 +297,7 @@ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; - PeriphClkInit.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_PCLK1; + PeriphClkInit.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); @@ -512,17 +520,17 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hspi->Instance==SPI5) + if(hspi->Instance==SPI1) { - /* USER CODE BEGIN SPI5_MspInit 0 */ + /* USER CODE BEGIN SPI1_MspInit 0 */ - /* USER CODE END SPI5_MspInit 0 */ + /* USER CODE END SPI1_MspInit 0 */ if(IS_ENGINEERING_BOOT_MODE()) { /** Initializes the peripherals clock */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI45; - PeriphClkInit.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PCLK2; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI1; + PeriphClkInit.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL4; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); @@ -531,19 +539,20 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) } /* Peripheral clock enable */ - __HAL_RCC_SPI5_CLK_ENABLE(); + __HAL_RCC_SPI1_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - /**SPI5 GPIO Configuration - PF9 ------> SPI5_MOSI - PF7 ------> SPI5_SCK + __HAL_RCC_GPIOZ_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PZ2 ------> SPI1_MOSI + PZ1 ------> SPI1_MISO + PZ0 ------> SPI1_SCK */ - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_7; + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI5; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOZ, &GPIO_InitStruct); /* USER CODE BEGIN SPI5_MspInit 1 */ @@ -966,6 +975,1100 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c) } /** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspInit 0 */ + if (IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* USER CODE END SDMMC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**SDMMC1 GPIO Configuration + PB9 ------> SDMMC1_CDIR + PC7 ------> SDMMC1_D123DIR + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + PE4 ------> SDMMC1_CKIN + PF2 ------> SDMMC1_D0DIR + */ + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_SDIO1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Alternate = GPIO_AF8_SDIO1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + __HAL_RCC_SDMMC1_FORCE_RESET(); + __HAL_RCC_SDMMC1_RELEASE_RESET(); + + /* SDMMC1 interrupt Init */ + HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspInit 1 */ + + /* USER CODE END SDMMC1_MspInit 1 */ + } + + if(hsd->Instance==SDMMC2) + { + /* USER CODE BEGIN SDMMC2_MspInit 0 */ + if (IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* USER CODE END SDMMC2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDMMC2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**SDMMC2 GPIO Configuration + PB14 ------> SDMMC2_D0 + PB15 ------> SDMMC2_D1 + PB3 ------> SDMMC2_D2 + PB4 ------> SDMMC2_D3 + PA8 ------> SDMMC2_D4 + PA9 ------> SDMMC2_D5 + PE5 ------> SDMMC2_D6 + PD3 ------> SDMMC2_D7 + PE3 ------> SDMMC2_CK + PG6 ------> SDMMC2_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Alternate = GPIO_AF10_SDIO2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + __HAL_RCC_SDMMC2_FORCE_RESET(); + __HAL_RCC_SDMMC2_RELEASE_RESET(); + + /* SDMMC2 interrupt Init */ + HAL_NVIC_SetPriority(SDMMC2_IRQn, 0X05, 0); + HAL_NVIC_EnableIRQ(SDMMC2_IRQn); + /* USER CODE BEGIN SDMMC2_MspInit 1 */ + + /* USER CODE END SDMMC2_MspInit 1 */ + } +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspDeInit 0 */ + + /* USER CODE END SDMMC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDMMC1_CLK_DISABLE(); + + /**SDMMC1 GPIO Configuration + PB9 ------> SDMMC1_CDIR + PC7 ------> SDMMC1_D123DIR + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + PE4 ------> SDMMC1_CKIN + PF2 ------> SDMMC1_D0DIR + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2); + /* SDMMC1 interrupt DeInit */ + HAL_NVIC_DisableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspDeInit 1 */ + + /* USER CODE END SDMMC1_MspDeInit 1 */ + } + + if(hsd->Instance==SDMMC2) + { + /* USER CODE BEGIN SDMMC2_MspDeInit 0 */ + + /* USER CODE END SDMMC2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDMMC2_CLK_DISABLE(); + + /**SDMMC2 GPIO Configuration + PB14 ------> SDMMC2_D0 + PB15 ------> SDMMC2_D1 + PB3 ------> SDMMC2_D2 + PB4 ------> SDMMC2_D3 + PA8 ------> SDMMC2_D4 + PA9 ------> SDMMC2_D5 + PE5 ------> SDMMC2_D6 + PD3 ------> SDMMC2_D7 + PE3 ------> SDMMC2_CK + PG6 ------> SDMMC2_CMD + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6); + /* SDMMC2 interrupt DeInit */ + HAL_NVIC_DisableIRQ(SDMMC2_IRQn); + /* USER CODE BEGIN SDMMC2_MspDeInit 1 */ + + /* USER CODE END SDMMC2_MspDeInit 1 */ + } +} + +void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /* SAI2 */ + if (hsai->Instance==SAI2_Block_A) + { + /* Peripheral clock enable */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; + PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_SAI2_CLK_ENABLE(); + + /**SAI2_A_Block_A GPIO Configuration + PE0 ------> SAI2_MCLK_A + PI7 ------> SAI2_FS_A + PI5 ------> SAI2_SCK_A + PI6 ------> SAI2_SD_A + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_5|GPIO_PIN_6; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* Configure DMA used for SAI2 */ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + hdma_sai2_a.Instance = DMA1_Stream0; + hdma_sai2_a.Init.Request = DMA_REQUEST_SAI2_A; + hdma_sai2_a.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_sai2_a.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sai2_a.Init.MemInc = DMA_MINC_ENABLE; + hdma_sai2_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_sai2_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_sai2_a.Init.Mode = DMA_CIRCULAR; + hdma_sai2_a.Init.Priority = DMA_PRIORITY_HIGH; + hdma_sai2_a.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_sai2_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sai2_a.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_sai2_a.Init.PeriphBurst = DMA_PBURST_SINGLE; + + HAL_DMA_DeInit(&hdma_sai2_a); + if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK) + { + Error_Handler(); + } + __HAL_LINKDMA(hsai,hdmatx,hdma_sai2_a); + __HAL_DMA_ENABLE(&hdma_sai2_a); + + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); + } + + if (hsai->Instance==SAI2_Block_B) + { + /* Peripheral clock enable */ + if (IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; + PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_SAI2_CLK_ENABLE(); + + /**SAI2_B_Block_B GPIO Configuration + PE12 ------> SAI2_MCLK_B + PE13 ------> SAI2_FS_B + PE14 ------> SAI2_SCK_B + PF11 ------> SAI2_SD_B + */ + + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI2; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_sai2_b.Instance = DMA1_Stream1; + hdma_sai2_b.Init.Request = DMA_REQUEST_SAI2_B; + hdma_sai2_b.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_sai2_b.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sai2_b.Init.MemInc = DMA_MINC_ENABLE; + hdma_sai2_b.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_sai2_b.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_sai2_b.Init.Mode = DMA_CIRCULAR; + hdma_sai2_b.Init.Priority = DMA_PRIORITY_HIGH; + hdma_sai2_b.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_sai2_b.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sai2_b.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_sai2_b.Init.PeriphBurst = DMA_PBURST_SINGLE; + + HAL_DMA_DeInit(&hdma_sai2_b); + if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK) + { + Error_Handler(); + } + __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b); + __HAL_DMA_ENABLE(&hdma_sai2_b); + HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); + } + /* SAI4 */ + if(hsai->Instance==SAI4_Block_A) + { + /* Peripheral clock enable */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI4; + PeriphClkInit.Sai4ClockSelection = RCC_SAI4CLKSOURCE_PLL3_Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_SAI4_CLK_ENABLE(); + + /**SAI4_A_Block_A GPIO Configuration + PB5 ------> SAI4_SD_A + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF10_SAI4; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral DMA init*/ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + hdma_sai4_a.Instance = DMA1_Stream2; + hdma_sai4_a.Init.Request = DMA_REQUEST_SAI4_A; + hdma_sai4_a.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_sai4_a.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sai4_a.Init.MemInc = DMA_MINC_ENABLE; + hdma_sai4_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_sai4_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_sai4_a.Init.Mode = DMA_CIRCULAR; + hdma_sai4_a.Init.Priority = DMA_PRIORITY_HIGH; + hdma_sai4_a.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_sai4_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sai4_a.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_sai4_a.Init.PeriphBurst = DMA_PBURST_SINGLE; + + HAL_DMA_DeInit(&hdma_sai4_a); + if (HAL_DMA_Init(&hdma_sai4_a) != HAL_OK) + { + Error_Handler(); + } + __HAL_LINKDMA(hsai,hdmatx,hdma_sai4_a); + __HAL_DMA_ENABLE(&hdma_sai4_a); + HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); + } +} + +/** +* @brief DCMI MSP Initialization +* This function configures the hardware resources used in this example +* @param hdcmi: DCMI handle pointer +* @retval None +*/ +void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hdcmi->Instance==DCMI) + { + /* USER CODE BEGIN DCMI_MspInit 0 */ + + /* USER CODE END DCMI_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DCMI_CLK_ENABLE(); + + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /**DCMI GPIO Configuration + PH9 ------> DCMI_D0 + PH10 ------> DCMI_D1 + PH11 ------> DCMI_D2 + PH12 ------> DCMI_D3 + PH14 ------> DCMI_D4 + PI4 ------> DCMI_D5 + PB8 ------> DCMI_D6 + PE6 ------> DCMI_D7 + PH8 ------> DCMI_HSYNC + PB7 ------> DCMI_VSYNC + PA6 ------> DCMI_PIXCLK + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF13_DCMI; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF13_DCMI; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF13_DCMI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF13_DCMI; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF13_DCMI; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + HAL_NVIC_SetPriority(DCMI_IRQn, 0x03, 0x00); + HAL_NVIC_EnableIRQ(DCMI_IRQn); + + /* USER CODE BEGIN DCMI_MspInit 1 */ + /* USER CODE END DCMI_MspInit 1 */ + } + +} + +/** +* @brief DCMI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdcmi: DCMI handle pointer +* @retval None +*/ +void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) +{ + if(hdcmi->Instance==DCMI) + { + /* USER CODE BEGIN DCMI_MspDeInit 0 */ + + /* USER CODE END DCMI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DCMI_CLK_DISABLE(); + + /**DCMI GPIO Configuration + PH10 ------> DCMI_D1 + PH11 ------> DCMI_D2 + PH14 ------> DCMI_D4 + PH8 ------> DCMI_HSYNC + PH9 ------> DCMI_D0 + PE6 ------> DCMI_D7 + PH12 ------> DCMI_D3 + PB7 ------> DCMI_VSYNC + PI4 ------> DCMI_D5 + PA6 ------> DCMI_PIXCLK + PB8 ------> DCMI_D6 + */ + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_8 + |GPIO_PIN_9|GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7|GPIO_PIN_8); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_4); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6); + + /* USER CODE BEGIN DCMI_MspDeInit 1 */ + HAL_DMA_DeInit(hdcmi->DMA_Handle); + /* USER CODE END DCMI_MspDeInit 1 */ + } + +} + +/** +* @brief FDCAN MSP Initialization +* This function configures the hardware resources used in this example +* @param hfdcan: FDCAN handle pointer +* @retval None +*/ +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hfdcan->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspInit 0 */ + + /* USER CODE END FDCAN1_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; + PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_FDCAN_CLK_ENABLE(); + + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + /**FDCAN1 GPIO Configuration + PH13 ------> FDCAN1_TX + PI9 ------> FDCAN1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* FDCAN1 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); + HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn); + HAL_NVIC_SetPriority(FDCAN_CAL_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(FDCAN_CAL_IRQn); + /* USER CODE BEGIN FDCAN1_MspInit 1 */ + /* USER CODE END FDCAN1_MspInit 1 */ + } + +} + +/** +* @brief FDCAN MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hfdcan: FDCAN handle pointer +* @retval None +*/ +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan) +{ + if(hfdcan->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ + + /* USER CODE END FDCAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_FDCAN_CLK_DISABLE(); + + /**FDCAN1 GPIO Configuration + PH13 ------> FDCAN1_TX + PI9 ------> FDCAN1_RX + */ + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9); + + /* FDCAN1 interrupt DeInit */ + HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn); + HAL_NVIC_DisableIRQ(FDCAN1_IT1_IRQn); + HAL_NVIC_DisableIRQ(FDCAN_CAL_IRQn); + /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ + + /* USER CODE END FDCAN1_MspDeInit 1 */ + } + +} + +void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef* hspdifrx) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(hspdifrx->Instance==SPDIFRX) + { + if(IS_ENGINEERING_BOOT_MODE()) + { + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPDIFRX; + PeriphClkInit.SpdifrxClockSelection = RCC_SPDIFRXCLKSOURCE_PLL4; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* Peripheral clock enable */ + __HAL_RCC_SPDIFRX_CLK_ENABLE(); + + __HAL_RCC_GPIOG_CLK_ENABLE(); + + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF8_SPDIF; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + hdma_spdifrx_rx.Instance = DMA1_Stream7; + hdma_spdifrx_rx.Init.Request = DMA_REQUEST_SPDIF_RX_DT; + hdma_spdifrx_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_spdifrx_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spdifrx_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spdifrx_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_spdifrx_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_spdifrx_rx.Init.Mode = DMA_CIRCULAR; + hdma_spdifrx_rx.Init.Priority = DMA_PRIORITY_HIGH; + hdma_spdifrx_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_spdifrx_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_spdifrx_rx.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_spdifrx_rx.Init.PeriphBurst = DMA_MBURST_SINGLE; + + HAL_DMA_DeInit(&hdma_spdifrx_rx); + if (HAL_DMA_Init(&hdma_spdifrx_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hspdifrx, hdmaDrRx, hdma_spdifrx_rx); + + HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); + } +} + +void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef* hspdifrx) +{ + if(hspdifrx->Instance==SPDIFRX) + { + __HAL_RCC_SPDIFRX_CLK_DISABLE(); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_12); + HAL_DMA_DeInit(hspdifrx->hdmaDrRx); + } +} + +void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(IS_ENGINEERING_BOOT_MODE()) + { + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* Peripheral clock enable */ + __HAL_RCC_DFSDM1_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**DFSDM1 GPIO Configuration + PC3 ------> DFSDM1_DATIN1 + PB13 ------> DFSDM1_CKOUT + PF13 ------> DFSDM1_DATIN3 + */ + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_DFSDM1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Alternate = GPIO_AF3_DFSDM1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Alternate = GPIO_AF6_DFSDM1; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); +} + +void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_DFSDM1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + + __HAL_RCC_DFSDM1_CLK_ENABLE(); + /* DMA controller clock enable */ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA2_CLK_ENABLE(); + + if(hdfsdm_filter->Instance == DFSDM1_Filter0) + { + hdma_dfsdm1_flt0.Instance = DMA2_Stream2; + hdma_dfsdm1_flt0.Init.Request = DMA_REQUEST_DFSDM1_FLT0; + hdma_dfsdm1_flt0.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_dfsdm1_flt0.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_dfsdm1_flt0.Init.MemInc = DMA_MINC_ENABLE; + hdma_dfsdm1_flt0.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_dfsdm1_flt0.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_dfsdm1_flt0.Init.Mode = DMA_CIRCULAR; + hdma_dfsdm1_flt0.Init.Priority = DMA_PRIORITY_HIGH; + hdma_dfsdm1_flt0.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_dfsdm1_flt0.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_dfsdm1_flt0.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_dfsdm1_flt0.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_dfsdm1_flt0) != HAL_OK) + { + Error_Handler(); + } + + /* Several peripheral DMA handle pointers point to the same DMA handle. + Be aware that there is only one channel to perform all the requested DMAs. */ + __HAL_LINKDMA(hdfsdm_filter,hdmaReg,hdma_dfsdm1_flt0); + + HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); + } + + if(hdfsdm_filter->Instance == DFSDM1_Filter1) + { + hdma_dfsdm1_flt1.Instance = DMA2_Stream1; + hdma_dfsdm1_flt1.Init.Request = DMA_REQUEST_DFSDM1_FLT1; + hdma_dfsdm1_flt1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_dfsdm1_flt1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_dfsdm1_flt1.Init.MemInc = DMA_MINC_ENABLE; + hdma_dfsdm1_flt1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_dfsdm1_flt1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_dfsdm1_flt1.Init.Mode = DMA_CIRCULAR; + hdma_dfsdm1_flt1.Init.Priority = DMA_PRIORITY_HIGH; + hdma_dfsdm1_flt1.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_dfsdm1_flt1.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_dfsdm1_flt1.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_dfsdm1_flt1.Init.PeriphBurst = DMA_PBURST_SINGLE; + + if (HAL_DMA_Init(&hdma_dfsdm1_flt1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hdfsdm_filter,hdmaReg,hdma_dfsdm1_flt1); + + HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn); + } +} + +void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +{ + HAL_DMA_DeInit(hdfsdm_filter->hdmaReg); +} + +void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef* hdfsdm_channel) +{ + __HAL_RCC_DFSDM1_CLK_DISABLE(); + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_13); +} + +/** +* @brief HASH MSP Initialization +* This function configures the hardware resources used in this example +* @param hhash: HASH handle pointer +* @retval None +*/ +void HAL_HASH_MspInit(HASH_HandleTypeDef* hhash) +{ + /* USER CODE BEGIN HASH2_MspInit 0 */ + /* USER CODE END HASH2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_HASH2_CLK_ENABLE(); + /* USER CODE BEGIN HASH2_MspInit 1 */ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_hash_in.Instance = DMA2_Stream7; + hdma_hash_in.Init.Request = DMA_REQUEST_HASH2_IN; + hdma_hash_in.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_hash_in.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_hash_in.Init.MemInc = DMA_MINC_ENABLE; + hdma_hash_in.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_hash_in.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_hash_in.Init.Mode = DMA_NORMAL; + hdma_hash_in.Init.Priority = DMA_PRIORITY_HIGH; + hdma_hash_in.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_hash_in.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL; + hdma_hash_in.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_hash_in.Init.PeriphBurst = DMA_PBURST_SINGLE; + + if (HAL_DMA_DeInit(&hdma_hash_in) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_hash_in) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hhash,hdmain,hdma_hash_in); + /* USER CODE END HASH2_MspInit 1 */ + +} + +/** +* @brief HASH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hhash: HASH handle pointer +* @retval None +*/ +void HAL_HASH_MspDeInit(HASH_HandleTypeDef* hhash) +{ + /* USER CODE BEGIN HASH2_MspDeInit 0 */ + + /* USER CODE END HASH2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_HASH2_CLK_DISABLE(); + /* USER CODE BEGIN HASH2_MspDeInit 1 */ + + /* USER CODE END HASH2_MspDeInit 1 */ + +} + +/** +* @brief CRC MSP Initialization +* This function configures the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC2) + { + /* USER CODE BEGIN CRC2_MspInit 0 */ + + /* USER CODE END CRC2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CRC2_CLK_ENABLE(); + /* USER CODE BEGIN CRC2_MspInit 1 */ + + /* USER CODE END CRC2_MspInit 1 */ + } + +} + +/** +* @brief CRC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC2) + { + /* USER CODE BEGIN CRC2_MspDeInit 0 */ + + /* USER CODE END CRC2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC2_CLK_DISABLE(); + /* USER CODE BEGIN CRC2_MspDeInit 1 */ + + /* USER CODE END CRC2_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hrng->Instance==RNG2) + { + /* USER CODE BEGIN RNG2_MspInit 0 */ + + /* USER CODE END RNG2_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG2; + PeriphClkInit.Rng2ClockSelection = RCC_RNG2CLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG2_CLK_ENABLE(); + /* USER CODE BEGIN RNG2_MspInit 1 */ + + /* USER CODE END RNG2_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG2) + { + /* USER CODE BEGIN RNG2_MspDeInit 0 */ + + /* USER CODE END RNG2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG2_CLK_DISABLE(); + /* USER CODE BEGIN RNG2_MspDeInit 1 */ + + /* USER CODE END RNG2_MspDeInit 1 */ + } + +} + +#if defined (CRYP1) || defined (CRYP2) +void HAL_CRYP_MspInit(CRYP_HandleTypeDef* hcryp) +{ + if(hcryp->Instance==CRYP2) + { + /* Peripheral clock enable */ + __HAL_RCC_CRYP2_CLK_ENABLE(); + __HAL_RCC_DMAMUX_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_cryp_in.Instance = DMA2_Stream6; + hdma_cryp_in.Init.Request = DMA_REQUEST_CRYP2_IN; + hdma_cryp_in.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_cryp_in.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_cryp_in.Init.MemInc = DMA_MINC_ENABLE; + hdma_cryp_in.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_cryp_in.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_cryp_in.Init.Mode = DMA_NORMAL; + hdma_cryp_in.Init.Priority = DMA_PRIORITY_HIGH; + hdma_cryp_in.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_DeInit(&hdma_cryp_in) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_cryp_in) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hcryp,hdmain,hdma_cryp_in); + + hdma_cryp_out.Instance = DMA2_Stream5; + hdma_cryp_out.Init.Request = DMA_REQUEST_CRYP2_OUT; + hdma_cryp_out.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_cryp_out.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_cryp_out.Init.MemInc = DMA_MINC_ENABLE; + hdma_cryp_out.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_cryp_out.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_cryp_out.Init.Mode = DMA_NORMAL; + hdma_cryp_out.Init.Priority = DMA_PRIORITY_VERY_HIGH; + hdma_cryp_out.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_DeInit(&hdma_cryp_out) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_cryp_out) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hcryp,hdmaout,hdma_cryp_out); + + /* USER CODE BEGIN CRYP_MspInit 1 */ + + /* USER CODE END CRYP_MspInit 1 */ + } +} + +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef* hcryp) +{ + + if(hcryp->Instance==CRYP2) + { + /* USER CODE BEGIN CRYP_MspDeInit 0 */ + + /* USER CODE END CRYP_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRYP2_CLK_DISABLE(); + + /* Peripheral DMA DeInit*/ + HAL_DMA_DeInit(hcryp->hdmain); + HAL_DMA_DeInit(hcryp->hdmaout); + } + /* USER CODE BEGIN CRYP_MspDeInit 1 */ + + /* USER CODE END CRYP_MspDeInit 1 */ + +} +#endif + +/** * @brief This function is executed in case of error occurrence. * @retval None */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig index e52a1601fe..6745682708 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig +++ b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig @@ -14,6 +14,10 @@ menu "Onboard Peripheral Drivers" select BSP_USING_UART select BSP_USING_UART4 default y + + config BSP_USING_EXTI + bool "Enable exti sample" + default n config BSP_USING_PMIC bool "Enable PMIC" @@ -21,6 +25,12 @@ menu "Onboard Peripheral Drivers" select BSP_USING_I2C3 default y + config BSP_USING_PWR + bool "Enable PM (power control)" + select BSP_USING_LPTIM + select BSP_USING_LPTIM1 + default n + config BSP_USING_NAND bool "Enable FMC (MT29F8G08ABACAH4)" select RT_USING_FMC @@ -28,11 +38,90 @@ menu "Onboard Peripheral Drivers" select RT_MTD_NAND_DEBUG default n + config BSP_USING_QSPI_FLASH + bool "Enable QSPI FLASH (MX25L51245G)" + select BSP_USING_QSPI + select RT_USING_SFUD + select RT_SFUD_USING_QSPI + default n + config BSP_USING_OPENAMP bool "Enable OpenAMP" select RT_USING_OPENAMP default n + config BSP_USING_GBE + bool "Enable Ethernet" + default n + select RT_USING_LWIP + + menuconfig BSP_USING_SDMMC + bool "Enable SDMMC" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + if BSP_USING_SDMMC + menuconfig BSP_USING_SDCARD + bool "Enable sd card" + select BSP_USING_PMIC + default n + if BSP_USING_SDCARD + config BSP_USING_SDCARD_FS + bool "sd card fatfs" + default y + endif + + menuconfig BSP_USING_EMMC + bool "Enable eMMC (32 Gbits)" + default n + if BSP_USING_EMMC + config BSP_USING_EMMC_FS + bool "emmc card fatfs" + default y + endif + endif + + config BSP_USING_AUDIO + bool "Enable Audio Device (WM8994)" + select RT_USING_AUDIO + select BSP_USING_PMIC + select BSP_USING_SDMMC + select BSP_USING_SDCARD + select SD_USING_DFS + select BSP_USING_I2C + select BSP_USING_I2C2 + default n + + config BSP_USING_DCMI + bool "Enable CAMERA (ov5640)" + select BSP_USING_MFX + select BSP_USING_PMIC + select BSP_USING_SDMMC + select BSP_USING_SDCARD + select BSP_USING_I2C + select BSP_USING_I2C2 + default n + + config BSP_USING_MFX + bool "Enable Multi Function eXpander" + default n + + menuconfig BSP_USING_RS485 + bool "Enable RS485 " + default n + if BSP_USING_RS485 + comment "set rts pin number " + config BSP_RS485_RTS_PIN + int "RS485 rts pin number" + range 1 176 + default 5 + + config RS485_UART_DEVICE_NAME + string "the uart name for rs485" + default "uart3" + + endif + endmenu menu "On-chip Peripheral Drivers" @@ -41,6 +130,32 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y + config BSP_USING_WWDG + bool "Enable WWDG" + select RT_USING_WWDG + select RT_USING_WDT + default n + + config BSP_USING_DMA + bool "Enable DMA Test" + default name + + config BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + + config BSP_USING_SPDIFRX + bool "Enable spdifrx" + select BSP_USING_AUDIO + default n + + config BSP_USING_DFSDM + bool "Enable dfsdm" + select BSP_USING_AUDIO + default n + menuconfig BSP_USING_UART bool "Enable UART" select RT_USING_SERIAL @@ -48,11 +163,11 @@ menu "On-chip Peripheral Drivers" if BSP_USING_UART config BSP_USING_UART3 bool "Enable UART3" - default y + default n config BSP_UART3_RX_USING_DMA bool "Enable UART3 RX DMA" - depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA default n config BSP_UART3_TX_USING_DMA @@ -62,7 +177,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART4 bool "Enable UART4" - default y + default n config BSP_UART4_RX_USING_DMA bool "Enable UART4 RX DMA" @@ -94,6 +209,16 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_LPTIM + bool "Enable lptimer" + default n + select RT_USING_LPTIMER + if BSP_USING_LPTIM + config BSP_USING_LPTIM1 + bool "Enable LPTIM1" + default n + endif + menuconfig BSP_USING_PWM bool "Enable pwm" default n @@ -185,22 +310,21 @@ menu "On-chip Peripheral Drivers" select RT_USING_SPI default n if BSP_USING_SPI - config BSP_USING_SPI5 - bool "Enable SPI5 BUS" - default n - - config BSP_SPI5_TX_USING_DMA - bool "Enable SPI5 TX DMA" - depends on BSP_USING_SPI5 + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" default n - config BSP_SPI5_RX_USING_DMA - bool "Enable SPI5 RX DMA" - depends on BSP_USING_SPI5 - select BSP_SPI5_TX_USING_DMA - default n endif + menuconfig BSP_USING_FDCAN + bool "Enable FDCAN" + default n + if BSP_USING_FDCAN + config BSP_USING_FDCAN1 + bool "Enable FDCAN1" + default n + endif + source "../libraries/HAL_Drivers/Kconfig" endmenu diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/SConscript b/bsp/stm32/stm32mp157a-st-ev1/board/SConscript index 15e6070c81..61c1a8029c 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/SConscript +++ b/bsp/stm32/stm32mp157a-st-ev1/board/SConscript @@ -13,12 +13,72 @@ CubeMX_Config/Common/System/system_stm32mp1xx.c CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c ''') +if GetDepend(['BSP_USING_SPI1']): + src += Glob('ports/spi_sample.c') + if GetDepend(['BSP_USING_PMIC']): src += Glob('ports/drv_pmic.c') if GetDepend(['BSP_USING_NAND']): src += Glob('ports/drv_nand.c') +if GetDepend(['BSP_USING_GBE']): + src += Glob('ports/eth/drv_eth.c') + +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/drv_sdcard.c') + +if GetDepend(['BSP_USING_EMMC']): + src += Glob('ports/drv_emmc.c') + +if GetDepend(['BSP_USING_AUDIO']): + src += Glob('ports/drv_wm8994.c') + src += Glob('ports/drv_sound.c') + +if GetDepend(['BSP_USING_DCMI']): + src += Glob('ports/drv_dcmi.c') + src += Glob('ports/drv_ov5640.c') + +if GetDepend(['BSP_USING_MFX']): + src += Glob('ports/drv_mfx.c') + src += Glob('ports/mfxstm32l152.c') + +if GetDepend(['BSP_USING_FDCAN']): + src += Glob('ports/drv_fdcan.c') + +if GetDepend(['BSP_USING_QSPI']): + src += Glob('ports/drv_qspi_flash.c') + +if GetDepend(['BSP_USING_SPDIFRX']): + src += Glob('ports/drv_spdifrx.c') + +if GetDepend(['BSP_USING_DFSDM']): + src += Glob('ports/drv_dfsdm.c') + +if GetDepend(['BSP_USING_WWDG']): + src += Glob('ports/drv_wwdg.c') + +if GetDepend(['BSP_USING_EXTI']): + src += Glob('ports/drv_exti.c') + +if GetDepend(['BSP_USING_RNG']) or GetDepend(['BSP_USING_HASH']) or GetDepend(['BSP_USING_CRC']) or GetDepend(['BSP_USING_CRYP']): + src += Glob('ports/crypto_sample.c') + +if GetDepend(['BSP_USING_PWR']): + src += Glob('ports/drv_pwr.c') + +if GetDepend(['BSP_USING_LPTIM1']): + src += Glob('ports/drv_lptim.c') + +if GetDepend(['BSP_USING_RS485']): + src += Glob('ports/drv_rs485.c') + +if GetDepend(['BSP_USING_TIM14']): + src += Glob('ports/timer_sample.c') + +if GetDepend(['BSP_USING_DMA']): + src += Glob('ports/dma_sample.c') + if GetDepend(['BSP_USING_OPENAMP']): src += Glob('CubeMX_Config/CM4/Src/ipcc.c') src += Glob('CubeMX_Config/CM4/Src/openamp.c') @@ -45,6 +105,9 @@ if GetDepend(['BSP_USING_OPENAMP']): path += [cwd + '/ports/OpenAMP/virtual_driver'] path += [cwd + '/CubeMX_Config/CM4/Inc'] +if GetDepend(['BSP_USING_GBE']): + path += [cwd + '/ports/eth'] + startup_path_prefix = SDK_LIB if rtconfig.CROSS_TOOL == 'gcc': diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.c b/bsp/stm32/stm32mp157a-st-ev1/board/board.c index 0a7bda208a..362250de22 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/board.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.c @@ -12,6 +12,7 @@ #include "board.h" +void PeriphCommonClock_Config(void); /** * @brief System Clock Configuration * @retval None @@ -124,6 +125,12 @@ void SystemClock_Config(void) /**Set the HSE division factor for RTC clock */ __HAL_RCC_RTC_HSEDIV(24); + + /* Configure the peripherals common clocks */ + if(IS_ENGINEERING_BOOT_MODE()) + { + PeriphCommonClock_Config(); + } } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.h b/bsp/stm32/stm32mp157a-st-ev1/board/board.h index 84e097714a..334eea4f5c 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/board.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.h @@ -23,23 +23,23 @@ extern "C" { #endif #define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000) -#if defined(BSP_USING_OPENAMP) -#define STM32_FLASH_SIZE (64 * 1024) -#else -#define STM32_FLASH_SIZE (256 * 1024) -#endif +#define STM32_FLASH_SIZE (192 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) - -#if defined(BSP_USING_OPENAMP) -#define STM32_SRAM_BEGIN (uint32_t)0x10020000 + +#define STM32_SRAM_SIZE (64) +#define STM32_SRAM_END (0x10030000 + 64 * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) #else -#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000 +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) #endif -#define STM32_SRAM_SIZE (64) -#define STM32_SRAM_END (STM32_SRAM_BEGIN + (STM32_SRAM_SIZE * 1024)) - -#define HEAP_BEGIN STM32_SRAM_BEGIN #define HEAP_END STM32_SRAM_END void SystemClock_Config(void); @@ -51,4 +51,3 @@ extern void _Error_Handler(char *s, int num); #endif #endif - diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf index ee4ff6ade6..9f3374e051 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf @@ -5,7 +5,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_text_start__ = 0x10000000;
-define symbol __ICFEDIT_region_text_end__ = 0x1001FFFF;
+define symbol __ICFEDIT_region_text_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_data_start__ = 0x10030000;
define symbol __ICFEDIT_region_data_end__ = 0x1003FFFF;
/*-Sizes-*/
@@ -28,11 +28,6 @@ define symbol __OPENAMP_region_size__ = 0x8000; export symbol __OPENAMP_region_start__;
export symbol __OPENAMP_region_size__;
-define symbol __SDMMC_region_start__ = 0x10048000;
-define symbol __SDMMC_region_size__ = 0x1FFFF;
-export symbol __SDMMC_region_start__;
-export symbol __SDMMC_region_size__;
-
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct index 40d9679d17..a64b8cc98b 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct @@ -8,20 +8,20 @@ LR_VECTORS 0x00000000 0x00000400 { ; load region size_region } } -LR_IROM1 0x10000000 0x00040000 { ; load region size_region - ER_IROM1 0x10000000 0x00040000 { ; load address = execution address +LR_IROM1 0x10000000 0x00030000 { ; load region size_region + ER_IROM1 0x10000000 0x00030000 { ; load address = execution address *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } - RW_IRAM1 0x10050000 0x00010000 { ; RW data + RW_IRAM1 0x10030000 0x00010000 { ; RW data .ANY (+RW +ZI) } -;; ***** Create region for OPENAMP ***** -;; *** These 4 lines can be commented if OPENAMP is not used ***** -; .resource_table +0 ALIGN 4 { ; resource table -; *(.resource_table) -; } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP +; ***** Create region for OPENAMP ***** +; *** These 4 lines can be commented if OPENAMP is not used ***** + .resource_table +0 ALIGN 4 { ; resource table + *(.resource_table) + } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c index 2705f068a3..12651efa1a 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c @@ -12,6 +12,7 @@ #ifdef BSP_USING_OPENAMP +#include <finsh.h> #include <drv_openamp.h> #include <openamp.h> #include <virt_uart.h> @@ -235,7 +236,10 @@ int rt_hw_openamp_init(void) rt_hw_openamp_register(&dev_openamp, "openamp", 0, NULL); - rt_console_set_device("openamp"); + if (RT_CONSOLE_DEVICE_NAME == "openamp") + { + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + } return RT_EOK; } @@ -289,4 +293,36 @@ static int creat_openamp_thread(void) } INIT_APP_EXPORT(creat_openamp_thread); +#ifdef FINSH_USING_MSH + +static int console(int argc, char **argv) +{ + rt_err_t result = RT_EOK; + + if (argc > 1) + { + if (!strcmp(argv[1], "set")) + { + rt_kprintf("console change to %s\n", argv[2]); + rt_console_set_device(argv[2]); + finsh_set_device(argv[2]); + } + else + { + rt_kprintf("Unknown command. Please enter 'console' for help\n"); + result = -RT_ERROR; + } + } + else + { + rt_kprintf("Usage: \n"); + rt_kprintf("console set <name> - change console by name\n"); + result = -RT_ERROR; + } + return result; +} +MSH_CMD_EXPORT(console, set console name); + +#endif /* FINSH_USING_MSH */ + #endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/crypto_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/crypto_sample.c new file mode 100644 index 0000000000..fcad8fb9ff --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/crypto_sample.c @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 thread-liu first version + */ + +#include <board.h> + +#include "drv_crypto.h" +#include <hwcrypto.h> +#include <string.h> +#include <stdlib.h> + +#if defined(BSP_USING_RNG) +static rt_err_t hw_rng_sample(int random_num) +{ + rt_err_t result = RT_EOK; + int i = 0, num0 = 0, num1 = 0; + + if (random_num == 0) + { + return RT_ERROR; + } + + for (i = 0; i< random_num; i++) + { + result = rt_hwcrypto_rng_update(); + rt_kprintf("%d ", result); + result%2 ? num1++ : num0++; + } + rt_kprintf("\neven numbers : %d, odd numbers: %d\n",num1, num0); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_CRC) +static void hw_crc_sample(uint8_t *temp, int size) +{ + struct rt_hwcrypto_ctx *ctx; + rt_uint32_t result = 0; + + struct hwcrypto_crc_cfg cfg = + { + .last_val = 0xFFFFFFFF, + .poly = 0x04C11DB7, + .width = 32, + .xorout = 0x00000000, + .flags = 0, + }; + + ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32); + rt_hwcrypto_crc_cfg(ctx, &cfg); + + result = rt_hwcrypto_crc_update(ctx, temp, size); + + rt_kprintf("crc result: %x \n", result); + + rt_hwcrypto_crc_destroy(ctx); +} +#endif + +#if defined(BSP_USING_HASH) +static void hw_hash_sample() +{ + int i = 0; + struct rt_hwcrypto_ctx *ctx = RT_NULL; + const uint8_t hash_input[] = "RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS)."; + + static uint8_t sha1_output[20]; + static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad, + 0x02, 0x1b, 0xa8, 0xbc, 0xa2, 0x2e, 0xa5, + 0xb0, 0x62, 0x1b, 0xdf, 0x7f, 0xec}; + + static uint8_t md5_output[16]; + static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9, + 0x4c, 0xd6, 0x7d, 0x28, 0xfc, 0xf6, 0xc3, + 0xac, 0x8b}; + + static uint8_t sha224_output[28]; + static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6, + 0x9f, 0x82, 0x78, 0x7a, 0x46, 0x91, + 0xb0, 0xe9, 0x64, 0x89, 0xe6, 0xc3, + 0x6b, 0x7e, 0xcf, 0xca, 0x11, 0x42, + 0xc8, 0x77, 0x13, 0x79}; + static uint8_t sha256_output[32]; + static uint8_t sha256_except[32] = {0x74, 0x19, 0xb9, 0x0e, 0xd1, 0x46, + 0x37, 0x0a, 0x55, 0x18, 0x26, 0x6c, + 0x50, 0xd8, 0x71, 0x34, 0xfa, 0x1f, + 0x5f, 0x5f, 0xe4, 0x9a, 0xe9, 0x40, + 0x0a, 0x7d, 0xa0, 0x26, 0x1b, 0x86, + 0x67, 0x45}; + rt_kprintf("Hash Test start: \n"); + rt_kprintf("Hash Test string: \n"); + for (i = 0; i < sizeof(hash_input); i++) + { + rt_kprintf("%c", hash_input[i]); + } + rt_kprintf("\n"); + + /* sh1 test*/ + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA1); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA1); + return ; + } + rt_kprintf("Create sha1 type success!\n"); + rt_kprintf("Except sha1 result: \n"); + for (i = 0; i < sizeof(sha1_except); i++) + { + rt_kprintf("%x ", sha1_except[i]); + } + rt_kprintf("\n"); + /* start sha1 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha1 result */ + rt_hwcrypto_hash_finish(ctx, sha1_output, rt_strlen((char const *)sha1_output)); + + rt_kprintf("Actual sha1 result: \n"); + for (i = 0; i < sizeof(sha1_output); i++) + { + rt_kprintf("%x ", sha1_output[i]); + } + rt_kprintf("\n"); + if(rt_memcmp(sha1_output, sha1_except, sizeof(sha1_except)/sizeof(sha1_except[0])) != 0) + { + rt_kprintf("Hash type sha1 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha1 Test success, The actual result is equal to the except result\n"); + } + /* deinit hash*/ + rt_hwcrypto_hash_destroy(ctx); + + /* md5 test*/ + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_MD5); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_MD5); + return ; + } + rt_kprintf("Create md5 type success!\n"); + rt_kprintf("Except md5 result: \n"); + for (i = 0; i < sizeof(md5_except); i++) + { + rt_kprintf("%x ", md5_except[i]); + } + rt_kprintf("\n"); + /* start md5 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get md5 result */ + rt_hwcrypto_hash_finish(ctx, md5_output, rt_strlen((char const *)md5_output)); + + rt_kprintf("Actual md5 result: \n"); + for (i = 0; i < sizeof(md5_output); i++) + { + rt_kprintf("%x ", md5_output[i]); + } + rt_kprintf("\n"); + if(rt_memcmp(md5_output, md5_except, sizeof(md5_except)/sizeof(md5_except[0])) != 0) + { + rt_kprintf("Hash type md5 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type md5 Test success, The actual result is equal to the except result\n"); + } + /* deinit hash*/ + rt_hwcrypto_hash_destroy(ctx); + + /* sha224 test */ + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA224); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA224); + return ; + } + rt_kprintf("Create sha224 type success!\n"); + rt_kprintf("Except sha224 result: \n"); + for (i = 0; i < sizeof(sha224_except); i++) + { + rt_kprintf("%x ", sha224_except[i]); + } + rt_kprintf("\n"); + /* start sha224 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha224 result */ + rt_hwcrypto_hash_finish(ctx, sha224_output, rt_strlen((char const *)sha224_output)); + + rt_kprintf("Actual sha224 result: \n"); + for (i = 0; i < sizeof(sha224_output); i++) + { + rt_kprintf("%x ", sha224_output[i]); + } + rt_kprintf("\n"); + if(rt_memcmp(sha224_output, sha224_except, sizeof(sha224_except)/sizeof(sha224_except[0])) != 0) + { + rt_kprintf("Hash type sha224 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha224 Test success, The actual result is equal to the except result\n"); + } + rt_hwcrypto_hash_destroy(ctx); + + /* sha256 test*/ + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA256); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA256); + return ; + } + + rt_kprintf("Create sha256 type success!\n"); + rt_kprintf("Except sha256 result: \n"); + for (i = 0; i < sizeof(sha256_except); i++) + { + rt_kprintf("%x ", sha256_except[i]); + } + rt_kprintf("\n"); + /* start sha256 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha256 result */ + rt_hwcrypto_hash_finish(ctx, sha256_output, rt_strlen((char const *)sha256_output)); + + rt_kprintf("Actual sha256 result: \n"); + for (i = 0; i < sizeof(sha256_output); i++) + { + rt_kprintf("%x ", sha256_output[i]); + } + rt_kprintf("\n"); + + if(rt_memcmp(sha256_output, sha256_except, sizeof(sha256_except)/sizeof(sha256_except[0])) != 0) + { + rt_kprintf("Hash type sha256 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha256 Test success, The actual result is equal to the except result\n"); + } + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("Hash Test over!\n"); +} +#endif + +static int crypto(int argc, char **argv) +{ + int result = RT_EOK; + static rt_device_t device = RT_NULL; + char *result_str; + + if (argc > 1) + { + if (!strcmp(argv[1], "probe")) + { + if (argc == 3) + { + char *dev_name = argv[2]; + device = rt_device_find(dev_name); + result_str = (device == RT_NULL) ? "failure" : "success"; + rt_kprintf("probe %s %s \n", argv[2], result_str); + } + else + { + rt_kprintf("crypto probe <crypto_name> - probe crypto by name\n"); + } + } + else + { + if (device == RT_NULL) + { + rt_kprintf("Please using 'crypto probe <crypto_name>' first\n"); + return -RT_ERROR; + } + if (!strcmp(argv[1], "rng")) + { +#if defined (BSP_USING_RNG) + if (argc == 3) + { + result = hw_rng_sample(atoi(argv[2])); + if(result != RT_EOK) + { + rt_kprintf("please input a legal number, not <%d>\n", atoi(argv[2])); + } + } + else + { + rt_kprintf("rng <number> - generate <number> digital\n"); + } + +#else + rt_kprintf("please enable RNG first!\n"); +#endif + } + else if (!strcmp(argv[1], "crc")) + { +#if defined (BSP_USING_CRC) + int size = 0, i = 0; + if (argc > 3) + { + size = argc - 2; + uint8_t *data = rt_malloc(size); + if (data) + { + for (i = 0; i < size; i++) + { + data[i] = strtol(argv[2 + i], NULL, 0); + } + hw_crc_sample(data, size); + rt_free(data); + } + else + { + rt_kprintf("Low memory!\n"); + } + } + else + { + rt_kprintf("crypto crc data1 ... dataN - calculate data1 ... dataN crc\n"); + } +#else + rt_kprintf("please enable CRC first!\n"); +#endif + } + else if (!strcmp(argv[1], "hash")) + { +#if defined (BSP_USING_HASH) + if (argc == 3) + { + hw_hash_sample(); + } + else + { + rt_kprintf("crypto hash sample - hash use sample\n"); + } +#else + rt_kprintf("please enable CRC first!\n"); +#endif + + } + else + { + rt_kprintf("Unknown command. Please enter 'crypto' for help\n"); + } + } + } + else + { + rt_kprintf("Usage: \n"); + rt_kprintf("crypto probe <crypto_name> - probe crypto by name\n"); + rt_kprintf("crypto rng number - generate numbers digital\n"); + rt_kprintf("crypto crc data1 ... dataN - calculate data1 ... dataN crc\n"); + rt_kprintf("crypto hash sample - hash use sample\n"); + result = -RT_ERROR; + } + + return result; +} +MSH_CMD_EXPORT(crypto, crypto function); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c new file mode 100644 index 0000000000..df6ead119f --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-10 thread-liu first version + */ + +#include <board.h> + +#if defined(BSP_USING_DMA) + +#define BUFFER_SIZE 32 /* DMA max buffer size */ + +static DMA_HandleTypeDef hdma_memtomem_dma1_stream5 = {0}; /* Using dma1 stream5 to test */ + +static const rt_uint32_t DMA_Src_Buffer[BUFFER_SIZE] = +{ + 0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10, + 0x11121314, 0x15161718, 0x191A1B1C, 0x1D1E1F20, + 0x21222324, 0x25262728, 0x292A2B2C, 0x2D2E2F30, + 0x31323334, 0x35363738, 0x393A3B3C, 0x3D3E3F40, + 0x41424344, 0x45464748, 0x494A4B4C, 0x4D4E4F50, + 0x51525354, 0x55565758, 0x595A5B5C, 0x5D5E5F60, + 0x61626364, 0x65666768, 0x696A6B6C, 0x6D6E6F70, + 0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80 +}; +static rt_uint32_t DMA_Dst_Buffer[BUFFER_SIZE]; + +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%02X ", buf[i + j]); + } + else + { + rt_kprintf(" "); + } + } + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } + rt_kprintf("\n"); + } +} + +void DMA1_Stream5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_memtomem_dma1_stream5); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void MX_DMA_Init(void) +{ + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + __HAL_RCC_DMAMUX_CLK_ENABLE(); + + /* Configure DMA request hdma_memtomem_dma1_stream5 on DMA1_Stream5 */ + hdma_memtomem_dma1_stream5.Instance = DMA1_Stream5; + hdma_memtomem_dma1_stream5.Init.Request = DMA_REQUEST_MEM2MEM; + hdma_memtomem_dma1_stream5.Init.Direction = DMA_MEMORY_TO_MEMORY; + hdma_memtomem_dma1_stream5.Init.PeriphInc = DMA_PINC_ENABLE; + hdma_memtomem_dma1_stream5.Init.MemInc = DMA_MINC_ENABLE; + hdma_memtomem_dma1_stream5.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_memtomem_dma1_stream5.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_memtomem_dma1_stream5.Init.Mode = DMA_NORMAL; + hdma_memtomem_dma1_stream5.Init.Priority = DMA_PRIORITY_LOW; + hdma_memtomem_dma1_stream5.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_memtomem_dma1_stream5.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_memtomem_dma1_stream5.Init.MemBurst = DMA_MBURST_INC4; + hdma_memtomem_dma1_stream5.Init.PeriphBurst = DMA_PBURST_INC4; + if (HAL_DMA_Init(&hdma_memtomem_dma1_stream5) != HAL_OK) + { + Error_Handler(); + } + + /* DMA interrupt init */ + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); +} + +static void TransferComplete(DMA_HandleTypeDef *DmaHandle) +{ + rt_kprintf("dma dst buffer :\n"); + dump_hex((rt_uint8_t *)DMA_Dst_Buffer, sizeof(DMA_Dst_Buffer)); + + rt_kprintf("============ dma transfer success ============\n"); + + rt_memset(DMA_Dst_Buffer, 0x00, sizeof(DMA_Dst_Buffer)); +} + +static void TransferError(DMA_HandleTypeDef *DmaHandle) +{ + rt_kprintf("============ dma transfer error ============\n"); +} + +static int rt_hw_dma_init(void) +{ + rt_err_t result = RT_EOK; + + MX_DMA_Init(); + /* Select Callbacks functions called after Transfer complete and Transfer error */ + HAL_DMA_RegisterCallback(&hdma_memtomem_dma1_stream5, HAL_DMA_XFER_CPLT_CB_ID, TransferComplete); + HAL_DMA_RegisterCallback(&hdma_memtomem_dma1_stream5, HAL_DMA_XFER_ERROR_CB_ID, TransferError); + + return result; +} +INIT_APP_EXPORT(rt_hw_dma_init); + +static int dma_transfer_test() +{ + rt_kprintf("============ dma travsfer start ============\n"); + + rt_kprintf("dma src buffer :\n"); + dump_hex((rt_uint8_t *)DMA_Src_Buffer, sizeof(DMA_Src_Buffer)); + + if (HAL_DMA_Start_IT(&hdma_memtomem_dma1_stream5, (rt_uint32_t)&DMA_Src_Buffer, (rt_uint32_t)&DMA_Dst_Buffer, BUFFER_SIZE) != HAL_OK) + { + /* Transfer Error */ + return -RT_ERROR; + } + + return RT_EOK; +} + +int dma_sample(int argc, char **argv) +{ + if (argc > 1) + { + if (!rt_strcmp(argv[1], "start")) + { + rt_kprintf("dma test start\n"); + dma_transfer_test(); + return RT_EOK; + } + else + { + goto _exit; + } + } +_exit: + { + rt_kprintf("Usage:\n"); + rt_kprintf("dma_sample start - start dma \n"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(dma_sample, dma test); + +#endif /* USE_DMA_SAMPLE */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c new file mode 100644 index 0000000000..def5dfd461 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu the first version + */ + +#include "board.h" + +#if defined(BSP_USING_DCMI) +#include "drv_dcmi.h" + +#define DRV_DEBUG +#define LOG_TAG "drv.dcmi" +#include <drv_log.h> + +struct stm32_dcmi +{ + struct rt_device dev; +}; +static struct stm32_dcmi rt_dcmi = {0}; +DCMI_HandleTypeDef dcmi = {0}; +DMA_HandleTypeDef hdma_dcmi = {0}; + +extern void jpeg_data_process(void); + +static void rt_hw_dmci_dma_init(void) +{ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + hdma_dcmi.Instance = DMA1_Stream3; + hdma_dcmi.Init.Request = DMA_REQUEST_DCMI; + hdma_dcmi.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_dcmi.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_dcmi.Init.MemInc = DMA_MINC_ENABLE; + hdma_dcmi.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_dcmi.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_dcmi.Init.Mode = DMA_CIRCULAR; + hdma_dcmi.Init.Priority = DMA_PRIORITY_HIGH; + hdma_dcmi.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_dcmi.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_dcmi.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_dcmi.Init.PeriphBurst = DMA_PBURST_SINGLE; + + HAL_DMA_Init(&hdma_dcmi); + + __HAL_LINKDMA(&dcmi, DMA_Handle, hdma_dcmi); + + HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0x02, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); +} + +void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint16_t len) +{ + HAL_DMAEx_MultiBufferStart(&hdma_dcmi, (rt_uint32_t)&DCMI->DR, dst_addr1, dst_addr2, len); + __HAL_DMA_ENABLE_IT(&hdma_dcmi, DMA_IT_TC); +} + +static rt_err_t rt_hw_dcmi_init(DCMI_HandleTypeDef *device) +{ + RT_ASSERT(device != RT_NULL); + + device->Instance = DCMI; + device->Init.SynchroMode = DCMI_SYNCHRO_HARDWARE; + device->Init.PCKPolarity = DCMI_PCKPOLARITY_RISING; + device->Init.VSPolarity = DCMI_VSPOLARITY_LOW; + device->Init.HSPolarity = DCMI_HSPOLARITY_LOW; + device->Init.CaptureRate = DCMI_CR_ALL_FRAME; + device->Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B; + device->Init.JPEGMode = DCMI_JPEG_DISABLE; + device->Init.ByteSelectMode = DCMI_BSM_ALL; + device->Init.ByteSelectStart = DCMI_OEBS_ODD; + device->Init.LineSelectMode = DCMI_LSM_ALL; + device->Init.LineSelectStart = DCMI_OELS_ODD; + + if (HAL_DCMI_Init(device) != HAL_OK) + { + LOG_E("dcmi init error!"); + return RT_ERROR; + } + + DCMI->IER = 0x0; + + __HAL_DCMI_ENABLE_IT(device, DCMI_IT_FRAME); + __HAL_DCMI_ENABLE(device); + + rt_hw_dmci_dma_init(); + + return RT_EOK; +} + +void DCMI_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DCMI_IRQHandler(&dcmi); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/* Capture a frame of the image */ +void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + jpeg_data_process(); + __HAL_DCMI_ENABLE_IT(&dcmi,DCMI_IT_FRAME); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA1_Stream3_IRQHandler(void) +{ + extern void rt_hw_camera_rx_callback(void); + /* enter interrupt */ + rt_interrupt_enter(); + + if(__HAL_DMA_GET_FLAG(&hdma_dcmi, DMA_FLAG_TCIF3_7)!=RESET) + { + __HAL_DMA_CLEAR_FLAG(&hdma_dcmi, DMA_FLAG_TCIF3_7); + rt_hw_camera_rx_callback(); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static rt_err_t rt_dcmi_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + rt_err_t result = RT_EOK; + + result = rt_hw_dcmi_init(&dcmi); + if (result != RT_EOK) + { + return result; + } + + return result; +} + +static rt_err_t rt_dcmi_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_dcmi_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_dcmi_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_dcmi_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_dcmi_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +int dcmi_init(void) +{ + rt_dcmi.dev.type = RT_Device_Class_Miscellaneous; + rt_dcmi.dev.init = rt_dcmi_init; + rt_dcmi.dev.open = rt_dcmi_open; + rt_dcmi.dev.close = rt_dcmi_close; + rt_dcmi.dev.read = rt_dcmi_read; + rt_dcmi.dev.write = rt_dcmi_write; + rt_dcmi.dev.control = rt_dcmi_control; + rt_dcmi.dev.user_data = RT_NULL; + + rt_device_register(&rt_dcmi.dev, "dcmi", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + LOG_I("dcmi init success!"); + + return RT_EOK; +} +INIT_BOARD_EXPORT(dcmi_init); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h new file mode 100644 index 0000000000..39fe3bdd26 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu first version + */ + +#ifndef __DRV_DCMI_H__ +#define __DRV_DCMI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c new file mode 100644 index 0000000000..38678dbdce --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-07 thread-liu first version + */ + +#include "board.h" + +#if defined(BSP_USING_DFSDM) +#include "drv_wm8994.h" +#include "drv_dfsdm.h" + +#define DRV_DEBUG +#define LOG_TAG "drv.dfsdm" +#include <drv_log.h> + +#define FILTER_FIFO_SIZE (1024) +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(0x2FFC8000))) static rt_int32_t FILTER0_FIFO[FILTER_FIFO_SIZE]; +#elif defined ( __GNUC__ ) +static rt_int32_t FILTER0_FIFO[FILTER_FIFO_SIZE] __attribute__((section(".Filter0Section"))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFC8000 +__no_init static rt_int32_t FILTER0_FIFO[FILTER_FIFO_SIZE]; +#endif + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(0x2FFC9000))) static rt_int32_t FILTER0_FIFO[FILTER_FIFO_SIZE]; +#elif defined ( __GNUC__ ) +static rt_int32_t FILTER0_FIFO[FILTER_FIFO_SIZE] __attribute__((section(".Filter1Section"))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFC9000 +__no_init static rt_int32_t FILTER1_FIFO[FILTER_FIFO_SIZE]; +#endif + +#define PALY_SIZE 2048 +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(0x2FFCA000))) static rt_int16_t PLAY_BUF[PALY_SIZE]; +#elif defined ( __GNUC__ ) +__attribute__((at(0x2FFCA000))) __attribute__((section(".DfsdmSection"))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFCA000 + __no_init static rt_int16_t PLAY_BUF[PALY_SIZE]; +#endif + +static volatile rt_uint8_t DmaLeftRecBuffCplt = 0; +static volatile rt_uint8_t DmaRightRecBuffCplt = 0; +static volatile rt_uint8_t DmaLeftRecHalfBuffCplt = 0; +static volatile rt_uint8_t DmaRightRecHalfBuffCplt = 0; + +static DFSDM_Channel_HandleTypeDef hdfsdm1_channel0 = {0}; /* data_in1_right */ +static DFSDM_Channel_HandleTypeDef hdfsdm1_channel1 = {0}; /* data_in1_left */ + +static DFSDM_Filter_HandleTypeDef hdfsdm1_filter0 = {0}; /* data_in1_right */ +static DFSDM_Filter_HandleTypeDef hdfsdm1_filter1 = {0}; /* data_in1_left */ + +extern DMA_HandleTypeDef hdma_dfsdm1_flt0; +extern DMA_HandleTypeDef hdma_dfsdm1_flt1; + +static struct rt_device dfsdm_dev = {0}; + +void DMA2_Stream2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_dfsdm1_flt1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA2_Stream1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_dfsdm1_flt0); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + if(hdfsdm_filter == &hdfsdm1_filter1) + { + DmaLeftRecHalfBuffCplt = 1; + } + else + { + DmaRightRecHalfBuffCplt = 1; + } +} + +void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + if (hdfsdm_filter == &hdfsdm1_filter1) + { + DmaLeftRecBuffCplt = 1; + } + else + { + DmaRightRecBuffCplt = 1; + } +} + +static int rt_hw_dfsdm_init(void) +{ + /* DATAIN1_LEFT */ + __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(&hdfsdm1_channel1); + hdfsdm1_channel1.Instance = DFSDM1_Channel1; + hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE; + hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM; /* 209MHZ */ + hdfsdm1_channel1.Init.OutputClock.Divider = 74; /* 209/74 = 2.82MHZ*/ + hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS; + hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; + hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS; + hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING ; /* left */ + hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL; + hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; + hdfsdm1_channel1.Init.Awd.Oversampling = 10; + hdfsdm1_channel1.Init.Offset = 0; + hdfsdm1_channel1.Init.RightBitShift = 2; + if(HAL_OK != HAL_DFSDM_ChannelInit(&hdfsdm1_channel1)) + { + return RT_ERROR; + } + + /* DATAIN1_RIGHT */ + __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(&hdfsdm1_channel0); + hdfsdm1_channel0.Instance = DFSDM1_Channel0; + hdfsdm1_channel0.Init.OutputClock.Activation = ENABLE; + hdfsdm1_channel0.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM; + hdfsdm1_channel0.Init.OutputClock.Divider = 74; /* 209/74 = 2.82MHZ*/ + hdfsdm1_channel0.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS; + hdfsdm1_channel0.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; + hdfsdm1_channel0.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS; + hdfsdm1_channel0.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_FALLING; /* right */ + hdfsdm1_channel0.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL; + hdfsdm1_channel0.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; + hdfsdm1_channel0.Init.Awd.Oversampling = 10; + hdfsdm1_channel0.Init.Offset = 0; + hdfsdm1_channel0.Init.RightBitShift = 2; + if(HAL_OK != HAL_DFSDM_ChannelInit(&hdfsdm1_channel0)) + { + return RT_ERROR; + } + + /* Initialize filter 0 (data_in1 right channel) */ + __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(&hdfsdm1_filter0); + hdfsdm1_filter0.Instance = DFSDM1_Filter0; + hdfsdm1_filter0.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER; + hdfsdm1_filter0.Init.RegularParam.FastMode = ENABLE; + hdfsdm1_filter0.Init.RegularParam.DmaMode = ENABLE; + hdfsdm1_filter0.Init.InjectedParam.Trigger = DFSDM_FILTER_SW_TRIGGER; + hdfsdm1_filter0.Init.InjectedParam.ScanMode = DISABLE; + hdfsdm1_filter0.Init.InjectedParam.DmaMode = DISABLE; + hdfsdm1_filter0.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC3_ORDER; + hdfsdm1_filter0.Init.FilterParam.Oversampling = 64; /* 209 / ( 74 * 64) = 44.1KHZ*/ + hdfsdm1_filter0.Init.FilterParam.IntOversampling = 1; + if (HAL_OK != HAL_DFSDM_FilterInit(&hdfsdm1_filter0)) + { + return RT_ERROR; + } + + /* Initialize filter 1 (data_in1 left channel) */ + __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(&hdfsdm1_filter1); + hdfsdm1_filter1.Instance = DFSDM1_Filter1; + hdfsdm1_filter1.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER; + hdfsdm1_filter1.Init.RegularParam.FastMode = ENABLE; + hdfsdm1_filter1.Init.RegularParam.DmaMode = ENABLE; + hdfsdm1_filter1.Init.InjectedParam.Trigger = DFSDM_FILTER_SW_TRIGGER; + hdfsdm1_filter1.Init.InjectedParam.ScanMode = DISABLE; + hdfsdm1_filter1.Init.InjectedParam.DmaMode = DISABLE; + hdfsdm1_filter1.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC3_ORDER; + hdfsdm1_filter1.Init.FilterParam.Oversampling = 64; /* 209 / ( 74 * 64) = 44.1KHZ*/ + hdfsdm1_filter1.Init.FilterParam.IntOversampling = 1; + if (HAL_OK != HAL_DFSDM_FilterInit(&hdfsdm1_filter1)) + { + return RT_ERROR; + } + + /* Configure regular channel and continuous mode for filter 0 (data_in1 left channel) */ + if (HAL_OK != HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter1, DFSDM_CHANNEL_1, DFSDM_CONTINUOUS_CONV_ON)) + { + return RT_ERROR; + } + + /* Configure regular channel and continuous mode for filter 1 (data_in1 right channel) */ + if (HAL_OK != HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter0, DFSDM_CHANNEL_0, DFSDM_CONTINUOUS_CONV_ON)) + { + return RT_ERROR; + } + + return RT_EOK; +} + +/* dfsdm start coversions */ +static rt_err_t rt_hw_dfsdm_open(void) +{ + if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter0, FILTER0_FIFO, FILTER_FIFO_SIZE)) + { + LOG_E("DFSDM DATA_IN1 rifht channel start conversions failed!"); + return RT_ERROR; + } + + if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter1, FILTER1_FIFO, FILTER_FIFO_SIZE)) + { + LOG_E("DFSDM DATA_IN1 left channel start conversions failed!"); + return RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t _init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + rt_hw_dfsdm_init(); + + return RT_EOK; +} + +static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + rt_hw_dfsdm_open(); + + return RT_EOK; +} + +static rt_err_t _close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + HAL_DFSDM_FilterRegularStop_DMA(&hdfsdm1_filter0); + HAL_DFSDM_FilterRegularStop_DMA(&hdfsdm1_filter1); + + return RT_EOK; +} + +static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + rt_uint32_t i = 0; + rt_int16_t *p = RT_NULL; + p = (rt_int16_t *)buffer; + + if (!pos) + { + for (i = 0; i < 512; i++) + { + p[2*i] = (int16_t)SaturaLH((FILTER0_FIFO[i] >> 8), -32768, 32767); + p[(2*i)+1] = (int16_t)SaturaLH((FILTER1_FIFO[i] >> 8), -32768, 32767); + } + } + else + { + for (i = 512; i < 1024; i++) + { + p[2*i] = (int16_t)SaturaLH((FILTER0_FIFO[i] >> 8), -32768, 32767); + p[(2*i)+1] = (int16_t)SaturaLH((FILTER1_FIFO[i] >> 8), -32768, 32767); + } + } + + return size; +} + +static rt_size_t _write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t _control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +int dfsdm_init(void) +{ + dfsdm_dev.type = RT_Device_Class_Miscellaneous; + dfsdm_dev.init = _init; + dfsdm_dev.open = _open; + dfsdm_dev.close = _close; + dfsdm_dev.read = _read; + dfsdm_dev.write = _write; + dfsdm_dev.control = _control; + dfsdm_dev.user_data = RT_NULL; + + rt_device_register(&dfsdm_dev, "dfsdm1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + LOG_I("dfsdm1 init success!"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(dfsdm_init); + +static int dfsdm_sample(int argc, char **argv) +{ + if (argc != 1) + { + rt_kprintf("Usage:\n"); + rt_kprintf("dfsdm_sample\n"); + return -1; + } + + static struct rt_device *dfsdm_dev = RT_NULL; + static struct rt_device *sound_dev = RT_NULL; + rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE; + rt_uint16_t tickstart = 0; + + extern SAI_HandleTypeDef hsai_BlockA2; + + dfsdm_dev = rt_device_find("dfsdm1"); + if (dfsdm_dev == RT_NULL) + { + rt_kprintf("no dfsdm device!"); + return RT_ERROR; + } + + sound_dev = rt_device_find("decoder"); + if (sound_dev == RT_NULL) + { + rt_kprintf("no decoder device!"); + return RT_ERROR; + } + + /* open dfsdm device */ + rt_device_open(dfsdm_dev, RT_DEVICE_OFLAG_RDWR); + /* open sound device */ + rt_device_open(sound_dev, RT_DEVICE_OFLAG_WRONLY); + + rt_device_control(sound_dev, SET_PLAY_TYPE, &play_type); + rt_device_control(sound_dev, START_PLAY, RT_NULL); + + rt_memset(PLAY_BUF, 0, PALY_SIZE); + + tickstart = rt_tick_get(); + if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, (uint8_t *)PLAY_BUF, PALY_SIZE) != HAL_OK) + { + rt_kprintf("sai transmit dma failed!\n"); + return RT_ERROR; + } + rt_kprintf("dfsdm audio record test begin!\n"); + + while (1) + { + if ((rt_tick_get() - tickstart) > 0x1000) + { + HAL_SAI_DMAStop(&hsai_BlockA2); + rt_device_close(dfsdm_dev); + break; + } + if (DmaLeftRecHalfBuffCplt && DmaRightRecHalfBuffCplt) + { + rt_device_read(dfsdm_dev, 0, PLAY_BUF, 512); + DmaLeftRecHalfBuffCplt = 0; + DmaRightRecHalfBuffCplt = 0; + } + else if (DmaLeftRecBuffCplt && DmaRightRecBuffCplt) + { + rt_device_read(dfsdm_dev, 1, PLAY_BUF, 512); + DmaLeftRecBuffCplt = 0; + DmaRightRecBuffCplt = 0; + } + } + + rt_kprintf("dfsdm audio record test end!\n"); + + return RT_EOK; +} +MSH_CMD_EXPORT(dfsdm_sample, dfsdm audiorecord test); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h new file mode 100644 index 0000000000..bf40fbf2f8 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-07 thread-liu first version + */ + +#ifndef __DRV_DFSDM_H__ +#define __DRV_DFSDM_H__ + +#include "board.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SaturaLH(N, L, H) (((N)<(L))?(L):(((N)>(H))?(H):(N))) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c new file mode 100644 index 0000000000..54af52e5e0 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c @@ -0,0 +1,594 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-16 thread-liu first version + */ + +#include "board.h" +#include "drv_emmc.h" +#include <dfs_fs.h> + +#ifdef BSP_USING_EMMC + +//#define DRV_DEBUG +//#define EMMC_RX_DUMP +//#define EMMC_TX_DUMP +#define DBG_TAG "drv.emmc" +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ +#include <rtdbg.h> + +static SD_HandleTypeDef hsd; +static struct rt_mmcsd_host *host; +#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000) + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct stm32_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; +}; + +#define EMMC_BUFF_SIZE 4096 +#define EMMC_BUFF_ADDR 0x2FFCB000 +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(EMMC_BUFF_ADDR))) static rt_uint8_t cache_buf[EMMC_BUFF_SIZE]; +#elif defined ( __GNUC__ ) +static rt_uint8_t cache_buf[EMMC_BUFF_SIZE] __attribute__((section(".eMMCSection"))); +#elif defined(__ICCARM__) +#pragma location = EMMC_BUFF_ADDR +__no_init static rt_uint8_t cache_buf[EMMC_BUFF_SIZE]; +#endif + +#if defined(EMMC_RX_DUMP) || defined(EMMC_TX_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%02X ", buf[i + j]); + else + rt_kprintf(" "); + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + rt_kprintf("\n"); + } +} +#endif + +/** + * @brief This function get order from sdio. + * @param data + * @retval sdio order + */ +static int get_order(rt_uint32_t data) +{ + int order = 0; + + switch (data) + { + case 1: + order = 0; + break; + case 2: + order = 1; + break; + case 4: + order = 2; + break; + case 8: + order = 3; + break; + case 16: + order = 4; + break; + case 32: + order = 5; + break; + case 64: + order = 6; + break; + case 128: + order = 7; + break; + case 256: + order = 8; + break; + case 512: + order = 9; + break; + case 1024: + order = 10; + break; + case 2048: + order = 11; + break; + case 4096: + order = 12; + break; + case 8192: + order = 13; + break; + case 16384: + order = 14; + break; + default : + order = 0; + break; + } + return order; +} + +/** + * @brief This function wait sdio cmd completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait cmd completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + + cmd->resp[0] = hw_sdio->resp1; + cmd->resp[1] = hw_sdio->resp2; + cmd->resp[2] = hw_sdio->resp3; + cmd->resp[3] = hw_sdio->resp4; + + if (status & SDMMC_ERRORS) + { + if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + + if (status & SDMMC_STA_CTIMEOUT) + { + cmd->err = -RT_ETIMEOUT; + } + + if (status & SDMMC_STA_DCRCFAIL) + { + data->err = -RT_ERROR; + } + + if (status & SDMMC_STA_DTIMEOUT) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status & SDMMC_STA_CCRCFAIL ? "CCRCFAIL " : "", + status & SDMMC_STA_DCRCFAIL ? "DCRCFAIL " : "", + status & SDMMC_STA_CTIMEOUT ? "CTIMEOUT " : "", + status & SDMMC_STA_DTIMEOUT ? "DTIMEOUT " : "", + status & SDMMC_STA_TXUNDERR ? "TXUNDERR " : "", + status & SDMMC_STA_RXOVERR ? "RXOVERR " : "", + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + } + + } + else + { + cmd->err = RT_EOK; + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; + + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + + /* config cmd reg */ + reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN; + if (resp_type(cmd) == RESP_NONE) + { + reg_cmd |= SDMMC_RESPONSE_NO; + } + else if (resp_type(cmd) == RESP_R2) + { + reg_cmd |= SDMMC_RESPONSE_LONG; + } + else + { + reg_cmd |= SDMMC_RESPONSE_SHORT; + } + hw_sdio->mask |= SDIO_MASKR_ALL; + + /* data pre configuration */ + if (data != RT_NULL) + { + hw_sdio->dctrl = 0; + hw_sdio->mask &= ~(SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE); + reg_cmd |= SDMMC_CMD_CMDTRANS; + hw_sdio->dtimer = HW_SDIO_DATATIMEOUT; + hw_sdio->dlen = data->blks * data->blksize; + hw_sdio->dctrl = (get_order(data->blksize)<<4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0); + hw_sdio->idmabase0r = (rt_uint32_t)cache_buf; + hw_sdio->idmatrlr = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + } + + hw_sdio->arg = cmd->arg; + hw_sdio->cmd = reg_cmd; + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* Waiting for data to be sent to completion */ + if (data != RT_NULL) + { + volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS; + + while (count && (hw_sdio->sta & SDMMC_STA_DPSMACT)) + { + count--; + } + if ((count == 0) || (hw_sdio->sta & SDMMC_ERRORS)) + { + cmd->err = -RT_ERROR; + } + } + + /* data post configuration */ + if (data != RT_NULL) + { + if (data->flags & DATA_DIR_READ) + { +#if defined(EMMC_RX_DUMP) + rt_kprintf("\nEMMC Rx:\n"); + dump_hex(cache_buf, data->blks * data->blksize); +#endif + rt_memcpy(data->buf, cache_buf, data->blks * data->blksize); + } + } +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + if (data->flags & DATA_DIR_WRITE) + { +#if defined(EMMC_TX_DUMP) + rt_kprintf("\nEMMC Tx:\n"); + dump_hex(cache_buf, data->blks * data->blksize); +#endif + rt_memcpy(cache_buf, data->buf, size); + } + } + + rthw_sdio_send_command(sdio, &pkg); + } + + if (req->stop != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->sta; + + /* clear irq flag*/ + hw_sdio->icr = intstatus; + + rt_event_send(&sdio->event, intstatus); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t temp, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + LOG_D("clk:%dK width:%s%s%s power:%s%s%s", + clk/1000, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "" + ); + + RTHW_SDIO_LOCK(sdio); + + clk_src = EMMC_CLOCK_FREQ; + + if (clk > 0) + { + if (clk > host->freq_max) + { + clk = host->freq_max; + } + temp = DIV_ROUND_UP(clk_src, 2 * clk); + if (temp > 0x3FF) + { + temp = 0x3FF; + } + } + + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + temp |= SDMMC_BUS_WIDE_8B; + } + else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + temp |= SDMMC_BUS_WIDE_4B; + } + else + { + temp |= SDMMC_BUS_WIDE_1B; + } + + hw_sdio->clkcr = temp; + + if (io_cfg->power_mode == MMCSD_POWER_ON) + hw_sdio->power |= SDMMC_POWER_PWRCTRL; + + RTHW_SDIO_UNLOCK(sdio); +} + +static const struct rt_mmcsd_host_ops ops = +{ + rthw_sdio_request, + rthw_sdio_iocfg, + RT_NULL, + RT_NULL, +}; + +/** + * @brief This function create mmcsd host. + * @param sdio_des stm32_sdio_des + * @retval rt_mmcsd_host + */ +struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if (sdio_des == RT_NULL) + { + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("malloc rthw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("alloc host fail"); + goto err; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des)); + + sdio->sdio_des.hw_sdio = (struct stm32_sdio *)EMMC_BASE_ADDRESS; + + rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + /* set host default attributes */ + host->ops = &ops; + host->freq_min = 400 * 1000; + host->freq_max = EMMC_MAX_FREQ; + host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */ + host->flags = MMCSD_BUSWIDTH_8 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED; + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + /* ready to change */ + mmcsd_change(host); + + return host; + +err: + if (sdio) + { + rt_free(sdio); + } + + return RT_NULL; +} + +void SDMMC2_IRQHandler(void) +{ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host); + + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ + struct stm32_sdio_des sdio_des; + + hsd.Instance = SDMMC2; + HAL_SD_MspInit(&hsd); + + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return RT_NULL; + } + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +#if defined(BSP_USING_EMMC_FS) +int mnt_init(void) +{ + rt_device_t sd = RT_NULL; + +#if defined(EMMC_RX_DUMP) || defined(EMMC_TX_DUMP) + rt_thread_delay(3000); +#else + rt_thread_delay(RT_TICK_PER_SECOND); +#endif + + sd = rt_device_find("sd0"); + if (sd == RT_NULL) + { + rt_kprintf("can't find emmc device!\n"); + return RT_ERROR; + } + + if (dfs_mount("sd0", "/", "elm", 0, 0) != 0) + { + rt_kprintf("file system mount failed!\n"); + } + else + { + rt_kprintf("file system mount success!\n"); + } + + return 0; +} +INIT_APP_EXPORT(mnt_init); +#endif + +#endif /* BSP_USING_SDMMC */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h new file mode 100644 index 0000000000..bd385cbb14 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-16 thread-liu first version + */ + +#ifndef __DRV_EMMC_H__ +#define __DRV_EMMC_H__ + +#include <rtthread.h> +#include "rtdevice.h" +#include <rthw.h> +#include <drv_common.h> +#include <string.h> +#include <drivers/mmcsd_core.h> +#include <drivers/sdio.h> + +#define SDIO_BUFF_SIZE 4096 + +#ifndef EMMC_BASE_ADDRESS +#define EMMC_BASE_ADDRESS (SDMMC2) +#endif + +#ifndef EMMC_CLOCK_FREQ +#define EMMC_CLOCK_FREQ (99U * 1000 * 1000) +#endif + +#ifndef EMMC_MAX_FREQ +#define EMMC_MAX_FREQ (50 * 1000 * 1000) +#endif + +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +#define SDMMC_ERRORS \ + (SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \ + SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \ + SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \ + SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL) + +#define SDIO_MASKR_ALL \ + (SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \ + SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \ + SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE) + +#define HW_SDIO_DATATIMEOUT (0xFFFFFFFFU) + +struct stm32_sdio +{ + volatile rt_uint32_t power; /* offset 0x00 */ + volatile rt_uint32_t clkcr; /* offset 0x04 */ + volatile rt_uint32_t arg; /* offset 0x08 */ + volatile rt_uint32_t cmd; /* offset 0x0C */ + volatile rt_uint32_t respcmd; /* offset 0x10 */ + volatile rt_uint32_t resp1; /* offset 0x14 */ + volatile rt_uint32_t resp2; /* offset 0x18 */ + volatile rt_uint32_t resp3; /* offset 0x1C */ + volatile rt_uint32_t resp4; /* offset 0x20 */ + volatile rt_uint32_t dtimer; /* offset 0x24 */ + volatile rt_uint32_t dlen; /* offset 0x28 */ + volatile rt_uint32_t dctrl; /* offset 0x2C */ + volatile rt_uint32_t dcount; /* offset 0x30 */ + volatile rt_uint32_t sta; /* offset 0x34 */ + volatile rt_uint32_t icr; /* offset 0x38 */ + volatile rt_uint32_t mask; /* offset 0x3C */ + volatile rt_uint32_t acktimer; /* offset 0x40 */ + volatile rt_uint32_t reserved0[3]; /* offset 0x44 ~ 0x4C */ + volatile rt_uint32_t idmatrlr; /* offset 0x50 */ + volatile rt_uint32_t idmabsizer; /* offset 0x54 */ + volatile rt_uint32_t idmabase0r; /* offset 0x58 */ + volatile rt_uint32_t idmabase1r; /* offset 0x5C */ + volatile rt_uint32_t reserved1[1]; /* offset 0x60 */ + volatile rt_uint32_t idmalar; + volatile rt_uint32_t idmabar; + volatile rt_uint32_t reserved2[5]; + volatile rt_uint32_t fifo; + volatile rt_uint32_t reserved3[220]; + volatile rt_uint32_t verr; + volatile rt_uint32_t ipidr; + volatile rt_uint32_t sidr; +}; + +typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio); + +struct stm32_sdio_des +{ + struct stm32_sdio *hw_sdio; + sdio_clk_get clk_get; +}; + +/* stm32 sdio dirver class */ +struct stm32_sdio_class +{ + struct stm32_sdio_des *des; + const struct stm32_sdio_config *cfg; + struct rt_mmcsd_host host; +}; + +extern void stm32_mmcsd_change(void); + +#endif /* __DRV_SDIO_H__ */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c new file mode 100644 index 0000000000..d3d118fd9f --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu first version + */ + +#include "board.h" +#ifdef BSP_USING_EXTI + +//#define DRV_DEBUG +#define LOG_TAG "drv.exti" +#include <drv_log.h> + +/* defined the KEY2 pin: */ +#define KEY2_PIN GET_PIN(A, 13) + +void key2_on(void *args) +{ + rt_kprintf("press key2!\n"); +} + +static int exti_sample(void) +{ + rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(KEY2_PIN, PIN_IRQ_MODE_FALLING, key2_on, RT_NULL); + rt_pin_irq_enable(KEY2_PIN, PIN_IRQ_ENABLE); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(exti_sample); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c new file mode 100644 index 0000000000..78c18e8594 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-06 thread-liu first version + */ + +#include "board.h" + +#if defined(BSP_USING_FDCAN1) || defined(BSP_USING_FDCAN2) + +#include "drv_fdcan.h" + +//#define DRV_DEBUG +#define LOG_TAG "drv.fdcan" +#include <drv_log.h> + +struct stm32_fdcan +{ + struct rt_device dev; + FDCAN_HandleTypeDef fdcan; + FDCAN_FilterTypeDef filter; + FDCAN_TxHeaderTypeDef tx_config; + FDCAN_RxHeaderTypeDef rx_config; + volatile rt_uint8_t fifo0; + volatile rt_uint8_t fifo1; +}; +static struct stm32_fdcan rt_fdcan = {0}; + +static rt_err_t rt_fdcan_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_fdcan *device = (struct stm32_fdcan *)dev; + + device->fdcan.Instance = FDCAN1; + device->fdcan.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + device->fdcan.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + device->fdcan.Init.AutoRetransmission = ENABLE; + device->fdcan.Init.TransmitPause = DISABLE; + device->fdcan.Init.ProtocolException = ENABLE; + device->fdcan.Init.NominalPrescaler = 0x01; /* tq = NominalPrescaler x (1/fdcan_ker_ck) */ + device->fdcan.Init.NominalSyncJumpWidth = 0x08; + device->fdcan.Init.DataPrescaler = 0x01; + device->fdcan.Init.DataSyncJumpWidth = 0x04; + device->fdcan.Init.DataTimeSeg1 = 0x05; /* DataTimeSeg1 = Propagation_segment + Phase_segment_1 */ + device->fdcan.Init.DataTimeSeg2 = 0x04; + device->fdcan.Init.NominalTimeSeg1 = 0x1F; /* NominalTimeSeg1 = Propagation_segment + Phase_segment_1 */ + device->fdcan.Init.NominalTimeSeg2 = 0x08; + device->fdcan.Init.MessageRAMOffset = 0x00; + device->fdcan.Init.StdFiltersNbr = 0x01; + device->fdcan.Init.ExtFiltersNbr = 0x01; + device->fdcan.Init.RxFifo0ElmtsNbr = 0x01; + device->fdcan.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; + device->fdcan.Init.RxFifo1ElmtsNbr = 0x02; + device->fdcan.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; + device->fdcan.Init.RxBuffersNbr = 0x00; + device->fdcan.Init.TxEventsNbr = 0x00; + device->fdcan.Init.TxBuffersNbr = 0x00; + device->fdcan.Init.TxFifoQueueElmtsNbr = 0x01; + device->fdcan.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + device->fdcan.Init.TxElmtSize = FDCAN_DATA_BYTES_8; + + if (HAL_FDCAN_Init(&device->fdcan) != HAL_OK) + { + return RT_ERROR; + } + + device->filter.IdType = FDCAN_EXTENDED_ID; + device->filter.FilterIndex = 0; + device->filter.FilterType = FDCAN_FILTER_MASK; + device->filter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + device->filter.FilterID1 = 0x1111111; + device->filter.FilterID2 = 0x2222222; + + if (HAL_FDCAN_ConfigFilter(&device->fdcan, &device->filter)!=HAL_OK) + { + return RT_ERROR; + } + HAL_FDCAN_Start(&device->fdcan); + HAL_FDCAN_ActivateNotification(&device->fdcan, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0); /* open rx fifo0 new message it */ + + device->fifo0 = RESET; + device->fifo1 = RESET; + + return RT_EOK; +} + +static rt_err_t rt_fdcan_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_fdcan_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_fdcan_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_fdcan *device = (struct stm32_fdcan *)dev; + + switch (cmd) + { + case FDCAN_MODE_NORMAL: + device->fdcan.Init.Mode = FDCAN_MODE_NORMAL; + break; + case FDCAN_MODE_INTERNAL_LOOPBACK: + device->fdcan.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + break; + default: + break; + } + + HAL_FDCAN_Init(&device->fdcan); + + return RT_EOK; +} + +static rt_size_t rt_fdcan_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_fdcan *device = (struct stm32_fdcan *)dev; + + if (rt_fdcan.fifo0 == SET) + { + rt_fdcan.fifo0 = RESET; + if (HAL_FDCAN_GetRxMessage(&device->fdcan, FDCAN_RX_FIFO0, &device->rx_config, (uint8_t *)buffer) != HAL_OK) + { + LOG_E("get msg error from fdcan fifo0!"); + return 0; + } + + return device->rx_config.DataLength >> 16; + } + if (rt_fdcan.fifo1 == SET) + { + rt_fdcan.fifo0 = RESET; + if (HAL_FDCAN_GetRxMessage(&device->fdcan, FDCAN_RX_FIFO1, &device->rx_config, (uint8_t *)buffer) != HAL_OK) + { + LOG_E("get msg error from fdcan fifo1!"); + return 0; + } + + return device->rx_config.DataLength >> 16; + } + + return 0; +} + +static rt_size_t rt_fdcan_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_fdcan *device = (struct stm32_fdcan *)dev; + + device->tx_config.Identifier = 0x1111112; + device->tx_config.IdType = FDCAN_EXTENDED_ID; + device->tx_config.TxFrameType = FDCAN_DATA_FRAME; + device->tx_config.DataLength = FDCAN_DLC_BYTES_8; + device->tx_config.ErrorStateIndicator = FDCAN_ESI_ACTIVE; + device->tx_config.BitRateSwitch = FDCAN_BRS_OFF; + device->tx_config.FDFormat = FDCAN_CLASSIC_CAN; + device->tx_config.TxEventFifoControl = FDCAN_NO_TX_EVENTS; + device->tx_config.MessageMarker = 0xCC; + + if (HAL_FDCAN_AddMessageToTxFifoQ(&device->fdcan, &device->tx_config, (uint8_t *)buffer) != HAL_OK) + { + return RT_ERROR; + } + + return RT_EOK; +} + +void FDCAN1_IT0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_FDCAN_IRQHandler(&rt_fdcan.fdcan); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void FDCAN1_IT1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_FDCAN_IRQHandler(&rt_fdcan.fdcan); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) +{ + if (hfdcan->Instance == FDCAN1) + { + if ((RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) != RESET) + { + rt_fdcan.fifo0 = SET; + HAL_FDCAN_ActivateNotification(hfdcan, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0); + } + } +} + +void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) +{ + if ((RxFifo1ITs & FDCAN_IT_RX_FIFO1_NEW_MESSAGE) != RESET) + { + rt_fdcan.fifo1 = SET; + HAL_FDCAN_ActivateNotification(hfdcan, FDCAN_IT_RX_FIFO1_NEW_MESSAGE, 0); + } +} + +int fdcan_init(void) +{ + rt_fdcan.dev.type = RT_Device_Class_CAN; + rt_fdcan.dev.init = rt_fdcan_init; + rt_fdcan.dev.open = rt_fdcan_open; + rt_fdcan.dev.close = rt_fdcan_close; + rt_fdcan.dev.read = rt_fdcan_read; + rt_fdcan.dev.write = rt_fdcan_write; + rt_fdcan.dev.control = rt_fdcan_control; + rt_fdcan.dev.user_data = RT_NULL; + + rt_device_register(&rt_fdcan.dev, "fdcan1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + LOG_I("fdcan1 init success!"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(fdcan_init); + +#ifdef FINSH_USING_MSH +#include <finsh.h> + +int fdcan_sample(int argc, char **argv) +{ + rt_err_t result = RT_EOK; + rt_uint8_t i, rx_buf[8], tx_buf[8]; + struct rt_device *dev = RT_NULL; + + if (argc != 9) + { + rt_kprintf("Usage:\n"); + rt_kprintf("fdcan_sample 1 2 3 4 5 6 7 8\n"); + return -1; + } + + for (i = 0; i < 8; i++) + { + tx_buf[i] = atoi(argv[i+1]); + } + + dev = rt_device_find("fdcan1"); + if (dev == RT_NULL) + { + rt_kprintf("can't find fdcan1 device!\n"); + return RT_ERROR; + } + rt_device_open(dev, RT_DEVICE_OFLAG_RDWR); + + rt_device_write(dev, 0, tx_buf, 8); + rt_thread_delay(1); + rt_device_read(dev, 0, rx_buf, 8); + + rt_kprintf("fdcan1 loopback test over, rbuf = "); + for (i = 0; i < 8; i++) + { + rt_kprintf(" %x ", rx_buf[i]); + } + rt_kprintf("\n"); + + return result; +} + +MSH_CMD_EXPORT(fdcan_sample, fdcan loopback mode test); + +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h new file mode 100644 index 0000000000..ab4280d360 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-06 thread-liu first version + */ + +#ifndef __DRV_FDCAN_H__ +#define __DRV_FDCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c new file mode 100644 index 0000000000..195345c19d --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-19 thread-liu first version + */ + +#include <board.h> + +#ifdef BSP_USING_LPTIM +#include "drv_config.h" +#include <string.h> +#include <stdlib.h> + +//#define DRV_DEBUG +#define LOG_TAG "drv.lptimer" +#include <drv_log.h> + +#define LED5_PIN GET_PIN(D, 9) +LPTIM_HandleTypeDef hlptim1; + +extern int lptim_stop(void); + +void LPTIM1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_LPTIM_IRQHandler(&hlptim1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + if(hlptim->Instance == LPTIM1) + { + HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_9); + } + +#if defined(BSP_USING_PWR) + /* All level of ITs can interrupt */ + __set_BASEPRI(0U); + + lptim_stop(); + rt_kprintf("system returns to normal!\n"); +#endif +} + +static int lptim_control(uint8_t pre_value) +{ + if(pre_value > 7) + { + pre_value = 7; + } + hlptim1.Instance->CFGR &= ~(7 << 9); /* clear PRESC[2:0] */ + hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0] */ + rt_kprintf("set lptim pre value [0x%x] success!\n", pre_value); + + return RT_EOK; +} + +int lptim_start(void) +{ + /* ### Start counting in interrupt mode ############################# */ + if (HAL_LPTIM_Counter_Start_IT(&hlptim1, 32767) != HAL_OK) + { + LOG_D("lptim1 start counting failed!\n"); + return -RT_ERROR; + } + + LOG_D("lptim1 start counting success!\n"); + + return RT_EOK; +} + +int lptim_stop(void) +{ + if (HAL_LPTIM_Counter_Stop_IT(&hlptim1) != HAL_OK) + { + LOG_D("lptim1 stop failed!\n"); + return -RT_ERROR; + } + + LOG_D("lptim1 stop counting success!\n"); + + return RT_EOK; +} + +int lptim_init(void) +{ + rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT); + + hlptim1.Instance = LPTIM1; + hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8; + hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING; + hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION; + hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; + hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; + if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) + { + LOG_D("lptim init failed!\n"); + return -RT_ERROR; + } + LOG_D("lptim init success!\n"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(lptim_init); + +static int lptim_sample(int argc, char *argv[]) +{ + if (argc > 1) + { + if (!strcmp(argv[1], "start")) + { + lptim_start(); + return RT_EOK; + } + else if (!strcmp(argv[1], "stop")) + { + lptim_stop(); + return RT_EOK; + } + else if (!strcmp(argv[1], "set")) + { + if (argc > 2) + { + lptim_control(atoi(argv[2])); + return RT_EOK; + } + else + { + goto _exit; + } + } + else + { + goto _exit; + } + } +_exit: + { + rt_kprintf("Usage:\n"); + rt_kprintf("lptim_sample start - start lptim, the LED5 will start blink\n"); + rt_kprintf("lptim_sample stop - stop lptim, the LED5 will stop blink\n"); + rt_kprintf("lptim_sample set - set the lptim prescaler to change LED5 blink frquency, lptim_sample set [0 - 7]\n"); + } + + return -RT_ERROR; +} +MSH_CMD_EXPORT(lptim_sample, low power timer sample); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c new file mode 100644 index 0000000000..071f833a10 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-08 thread-liu first version + */ + +#include "board.h" + +#include "mfxstm32l152.h" +#define DRV_DEBUG +#define LOG_TAG "drv.mfx" +#include <drv_log.h> + +#define CHIP_ADDRESS 0x42 /* mfx address */ +#define I2C_NAME "i2c2" + +struct st_mfx +{ + struct rt_device dev; + struct rt_i2c_bus_device *i2c_bus; + rt_uint8_t id; + rt_uint16_t type; +}; +static struct st_mfx rt_mfx = {0}; +static IO_DrvTypeDef *IoDrv = NULL; + +static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint16_t len, rt_uint8_t *buf) +{ + struct rt_i2c_msg msg[2] = {0, 0}; + + RT_ASSERT(bus != RT_NULL); + + msg[0].addr = CHIP_ADDRESS; + msg[0].flags = RT_I2C_WR; + msg[0].buf = ® + msg[0].len = 1; + + msg[1].addr = CHIP_ADDRESS; + msg[1].flags = RT_I2C_RD; + msg[1].len = len; + msg[1].buf = buf; + + if (rt_i2c_transfer(bus, msg, 2) == 2) + { + return RT_EOK; + } + + return RT_ERROR; +} + +/* i2c write reg */ +static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t data) +{ + rt_uint8_t buf[2]; + struct rt_i2c_msg msgs; + + RT_ASSERT(bus != RT_NULL); + buf[0] = reg; + buf[1] = data; + + msgs.addr = CHIP_ADDRESS; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = sizeof(buf); + + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + + return RT_ERROR; +} + +void MFX_IO_Init(void) +{ + rt_mfx.i2c_bus = rt_i2c_bus_device_find(I2C_NAME); + if (rt_mfx.i2c_bus == RT_NULL) + { + LOG_E("can't find %c deivce", I2C_NAME); + } +} + +void MFX_IO_DeInit(void) +{ +} + +void MFX_IO_ITConfig(void) +{ + static rt_uint8_t mfx_io_it_enabled = 0; + GPIO_InitTypeDef gpio_init_structure; + + if(mfx_io_it_enabled == 0) + { + mfx_io_it_enabled = 1; + /* Enable the GPIO EXTI clock */ + __HAL_RCC_GPIOI_CLK_ENABLE(); + + gpio_init_structure.Pin = GPIO_PIN_8; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_LOW; + gpio_init_structure.Mode = GPIO_MODE_IT_RISING; + HAL_GPIO_Init(GPIOI, &gpio_init_structure); + + /* Enable and set GPIO EXTI Interrupt to the lowest priority */ + HAL_NVIC_SetPriority((IRQn_Type)(EXTI8_IRQn), 0x04, 0x00); + HAL_NVIC_EnableIRQ((IRQn_Type)(EXTI8_IRQn)); + } +} + +void MFX_IO_Write(rt_uint16_t Addr, rt_uint8_t Reg, rt_uint8_t Value) +{ + write_reg(rt_mfx.i2c_bus, Reg, Value); +} + +rt_uint8_t MFX_IO_Read(rt_uint16_t Addr, rt_uint8_t Reg) +{ + rt_uint8_t value = 0; + read_reg(rt_mfx.i2c_bus, Reg, 1, &value); + + return value; +} + +rt_uint16_t MFX_IO_ReadMultiple(rt_uint16_t Addr, rt_uint8_t Reg, rt_uint8_t *Buffer, rt_uint16_t Length) +{ + return read_reg(rt_mfx.i2c_bus, Reg, Length, Buffer); +} + +RT_WEAK void MFX_IO_Delay(rt_uint32_t Delay) +{ + rt_thread_delay(Delay); +} + +RT_WEAK void MFX_IO_Wakeup(void) +{ +} + +RT_WEAK void MFX_IO_EnableWakeupPin(void) +{ +} + +rt_uint8_t BSP_IO_DeInit(void) +{ + IoDrv = NULL; + return RT_EOK; +} + +rt_uint32_t BSP_IO_ITGetStatus(rt_uint32_t IoPin) +{ + /* Return the IO Pin IT status */ + return (IoDrv->ITStatus(0, IoPin)); +} + +/** + * @brief Clears all the IO IT pending bits. + * @retval None + */ +void BSP_IO_ITClear(void) +{ + /* Clear all IO IT pending bits */ + IoDrv->ClearIT(0, MFXSTM32L152_GPIO_PINS_ALL); +} + +void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear) +{ + /* Clear only the selected list of IO IT pending bits */ + IoDrv->ClearIT(0, IO_Pins_To_Clear); +} + +/** + * @brief Configures the IO pin(s) according to IO mode structure value. + * @param IoPin: IO pin(s) to be configured. + * This parameter can be one of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @param IoMode: IO pin mode to configure + * This parameter can be one of the following values: + * @arg IO_MODE_INPUT + * @arg IO_MODE_OUTPUT + * @arg IO_MODE_IT_RISING_EDGE + * @arg IO_MODE_IT_FALLING_EDGE + * @arg IO_MODE_IT_LOW_LEVEL + * @arg IO_MODE_IT_HIGH_LEVEL + * @arg IO_MODE_ANALOG + * @arg IO_MODE_OFF + * @arg IO_MODE_INPUT_PU, + * @arg IO_MODE_INPUT_PD, + * @arg IO_MODE_OUTPUT_OD, + * @arg IO_MODE_OUTPUT_OD_PU, + * @arg IO_MODE_OUTPUT_OD_PD, + * @arg IO_MODE_OUTPUT_PP, + * @arg IO_MODE_OUTPUT_PP_PU, + * @arg IO_MODE_OUTPUT_PP_PD, + * @arg IO_MODE_IT_RISING_EDGE_PU + * @arg IO_MODE_IT_FALLING_EDGE_PU + * @arg IO_MODE_IT_LOW_LEVEL_PU + * @arg IO_MODE_IT_HIGH_LEVEL_PU + * @arg IO_MODE_IT_RISING_EDGE_PD + * @arg IO_MODE_IT_FALLING_EDGE_PD + * @arg IO_MODE_IT_LOW_LEVEL_PD + * @arg IO_MODE_IT_HIGH_LEVEL_PD + * @retval RT_EOK if all initializations are OK. Other value if error. + */ +rt_uint8_t rt_mfx_pin_mode(rt_uint32_t IoPin, IO_ModeTypedef IoMode) +{ + /* Configure the selected IO pin(s) mode */ + IoDrv->Config(0, IoPin, IoMode); + + return RT_EOK; +} + +/** + * @brief Sets the IRQ_OUT pin polarity and type + * @param IoIrqOutPinPolarity: High/Low + * @param IoIrqOutPinType: OpenDrain/PushPull + * @retval OK + */ +rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOutPinType) +{ + if((rt_mfx.id == MFXSTM32L152_ID_1) || (rt_mfx.id == MFXSTM32L152_ID_2)) + { + /* Initialize the IO driver structure */ + mfxstm32l152_SetIrqOutPinPolarity(0, IoIrqOutPinPolarity); + mfxstm32l152_SetIrqOutPinType(0, IoIrqOutPinType); + } + + return RT_EOK; +} + +/** + * @brief Sets the selected pins state. + * @param IoPin: Selected pins to write. + * This parameter can be any combination of the IO pins. + * @param PinState: New pins state to write + * @retval None + */ +void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState) +{ + /* Set the Pin state */ + IoDrv->WritePin(0, IoPin, PinState); +} + +/** + * @brief Gets the selected pins current state. + * @param IoPin: Selected pins to read. + * This parameter can be any combination of the IO pins. + * @retval The current pins state + */ +rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin) +{ + return(IoDrv->ReadPin(0, IoPin)); +} + +/** + * @brief Toggles the selected pins state. + * @param IoPin: Selected pins to toggle. + * This parameter can be any combination of the IO pins. + * @note This function is only used to toggle one pin in the same time + * @retval None + */ +void rt_mfx_pin_toggle(rt_uint32_t IoPin) +{ + /* Toggle the current pin state */ + if(IoDrv->ReadPin(0, IoPin) != 0) + { + IoDrv->WritePin(0, IoPin, 0); /* Reset */ + } + else + { + IoDrv->WritePin(0, IoPin, 1); /* Set */ + } +} + +int rt_mfx_init(void) +{ + /* Read ID and verify the MFX is ready */ + rt_mfx.id = mfxstm32l152_io_drv.ReadID(0); + if((rt_mfx.id == MFXSTM32L152_ID_1) || (rt_mfx.id == MFXSTM32L152_ID_2)) + { + /* Initialize the IO driver structure */ + IoDrv = &mfxstm32l152_io_drv; + + /* Initialize MFX */ + IoDrv->Init(0); + IoDrv->Start(0, IO_PIN_ALL); + + LOG_I("mfx init success, id: 0x%x", rt_mfx.id); + + return RT_EOK; + } + LOG_I("mfx init error, id: 0x%x", rt_mfx.id); + + return RT_ERROR; +} +INIT_DEVICE_EXPORT(rt_mfx_init); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h new file mode 100644 index 0000000000..a0cf46777c --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-08 thread-liu first version + */ + +#ifndef __DRV_MFX_H__ +#define __DRV_MFX_H__ + +#include "board.h" +#include "mfxstm32l152.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum +{ + BSP_IO_PIN_RESET = 0, + BSP_IO_PIN_SET = 1 +}BSP_IO_PinStateTypeDef; + +#define CAMERA_RST1 MFXSTM32L152_AGPIO_PIN_3 +#define CAMERA_XSDN MFXSTM32L152_AGPIO_PIN_2 +#define CARMERA_PLUG MFXSTM32L152_GPIO_PIN_12 + +void rt_mfx_init(void); +rt_uint32_t BSP_IO_ITGetStatus(rt_uint32_t IoPin); +void BSP_IO_ITClear(void); +void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear); +rt_uint8_t rt_mfx_pin_mode(rt_uint32_t IoPin, IO_ModeTypedef IoMode); +rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOutPinType); +void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState); +rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin); +void rt_mfx_pin_toggle(rt_uint32_t IoPin); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c new file mode 100644 index 0000000000..30eb0e4ad7 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c @@ -0,0 +1,665 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-03 thread-liu the first version + */ + +#include "board.h" + +#if defined(BSP_USING_DCMI) + +#include "drv_mfx.h" +#include <dfs_posix.h> +#include "drv_ov5640.h" + +//#define DRV_DEBUG +//#define CAMERA_DUMP +#define LOG_TAG "drv.ov5640" +#include <drv_log.h> + +#define CHIP_ADDRESS 0x3C /* OV5640 address */ +#define I2C_NAME "i2c2" + +#define JPEG_BUF_SIZE 8 * 1024 +#define JPEG_LINE_SIZE 1 * 1024 + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(0x2FFCC000))) static rt_int32_t JPEG_DATA_BUF[JPEG_BUF_SIZE]; +#elif defined(__GNUC__) +static rt_int32_t JPEG_DATA_BUF[JPEG_BUF_SIZE] __attribute__((section(".Dcmi0Section"))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFCC000 +__no_init static rt_int32_t JPEG_DATA_BUF[JPEG_BUF_SIZE]; +#endif + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(0x2FFDC000))) static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]; +#elif defined(__GNUC__) +static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE] __attribute__((section(".Dcmi1Section"))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFDC000 +__no_init static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]; +#endif + +volatile rt_uint32_t jpeg_data_len = 0; +volatile rt_uint8_t jpeg_data_ok = 0; +struct rt_i2c_bus_device *i2c_bus = RT_NULL; +extern DCMI_HandleTypeDef dcmi; +extern DMA_HandleTypeDef hdma_dcmi; + +#if defined(CAMERA_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08x:", i); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%02x", buf[i + j]); + } + else + { + rt_kprintf(" "); + } + } + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } + rt_kprintf("\n"); + } +} +#endif + +static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint8_t len, rt_uint8_t *buf) +{ + struct rt_i2c_msg msg[2] = {0, 0}; + static rt_uint8_t i2c_reg[2] = {0, 0}; + + RT_ASSERT(bus != RT_NULL); + + i2c_reg[0] = ((uint16_t)(reg >> 8) & 0xFF); + i2c_reg[1] = ((uint16_t)(reg & 0xFF)); + + msg[0].addr = CHIP_ADDRESS; + msg[0].flags = RT_I2C_WR; + msg[0].buf = i2c_reg; + msg[0].len = 2; + + msg[1].addr = CHIP_ADDRESS; + msg[1].flags = RT_I2C_RD; + msg[1].len = len; + msg[1].buf = buf; + + if (rt_i2c_transfer(bus, msg, 2) == 2) + { + return RT_EOK; + } + + return RT_ERROR; +} + +/* i2c write reg */ +static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint8_t data) +{ + rt_uint8_t buf[3]; + struct rt_i2c_msg msgs; + + RT_ASSERT(bus != RT_NULL); + + buf[0] = ((uint16_t)(reg >> 8) & 0xFF); + buf[1] = ((uint16_t)(reg)&0xFF); + + buf[2] = data; + + msgs.addr = CHIP_ADDRESS; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = 3; + + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + + return RT_ERROR; +} + +static rt_err_t ov5640_read_id(struct rt_i2c_bus_device *bus, rt_uint16_t *id) +{ + rt_uint8_t read_value[2]; + + read_reg(bus, 0x300A, 1, &read_value[0]); + read_reg(bus, 0x300B, 1, &read_value[1]); + *id = ((uint16_t)(read_value[0] << 8) & 0xFF00); + *id |= ((uint16_t)(read_value[1]) & 0x00FF); + + if (*id != OV5640_ID) + { + LOG_E("ov5640 init error, id: 0x%04x", *id); + return RT_ERROR; + } + + LOG_I("ov5640 init success, id: 0x%04x", *id); + + return RT_EOK; +} + +static rt_err_t ov5640_hard_reset(struct rt_i2c_bus_device *bus) +{ + /* Camera sensor RESET sequence */ + rt_mfx_pin_mode(CAMERA_RST1, IO_MODE_OUTPUT); + rt_mfx_pin_mode(CAMERA_XSDN, IO_MODE_OUTPUT); + + /* Assert the camera STANDBY pin (active high) */ + rt_mfx_pin_write(CAMERA_XSDN, BSP_IO_PIN_SET); + + /* Assert the camera RSTI pin (active low) */ + rt_mfx_pin_write(CAMERA_RST1, BSP_IO_PIN_RESET); + + rt_thread_delay(100); /* RST and XSDN signals asserted during 100ms */ + + /* De-assert the camera STANDBY pin (active high) */ + rt_mfx_pin_write(CAMERA_XSDN, BSP_IO_PIN_RESET); + + rt_thread_delay(3); /* RST de-asserted and XSDN asserted during 3ms */ + + /* De-assert the camera RSTI pin (active low) */ + rt_mfx_pin_write(CAMERA_RST1, BSP_IO_PIN_SET); + + rt_thread_delay(6); /* RST de-asserted during 3ms */ + + return RT_EOK; +} + +void OV5640_Flash_Ctrl(struct rt_i2c_bus_device *bus, rt_uint8_t sw) +{ + write_reg(bus, 0x3016, 0X02); + write_reg(bus, 0x301C, 0X02); + if (sw) + { + write_reg(bus, 0X3019, 0X02); + } + else + { + write_reg(bus, 0X3019, 0X00); + } +} + +static rt_err_t ov5640_config(struct rt_i2c_bus_device *bus) +{ + rt_uint32_t i = 0; + rt_uint8_t value = 0; + + write_reg(bus, 0x3103, 0X11); /* system clock from pad, bit[1] */ + write_reg(bus, 0X3008, 0X82); /* soft reset */ + + rt_thread_delay(10); + + for (i = 0; i < (sizeof(RGB565_Init) / 4); i++) + { + write_reg(bus, RGB565_Init[i][0], RGB565_Init[i][1]); + rt_thread_delay(10); + read_reg(bus, RGB565_Init[i][0], 1, &value); + + if (RGB565_Init[i][1] != value) + { + LOG_D("error reg value[0x%x]:0x%02x - 0x%02x", RGB565_Init[i][0], RGB565_Init[i][1], value); + } + } + + OV5640_Flash_Ctrl(bus, 1); /* open camera flash*/ + rt_thread_delay(3); + OV5640_Flash_Ctrl(bus, 0); /* close camera flash*/ + + return RT_EOK; +} + +/* JPEG */ +void ov5640_jpeg_mode(struct rt_i2c_bus_device *bus) +{ + rt_uint16_t i = 0; + for (i = 0; i < (sizeof(OV5640_jpeg_reg_tbl) / 4); i++) + { + write_reg(bus, OV5640_jpeg_reg_tbl[i][0], OV5640_jpeg_reg_tbl[i][1]); + } +} + +/* RGB565 */ +void ov5640_rgb565_mode(struct rt_i2c_bus_device *bus) +{ + rt_uint16_t i = 0; + for (i = 0; i < (sizeof(ov5640_rgb565_reg_tbl) / 4); i++) + { + write_reg(bus, ov5640_rgb565_reg_tbl[i][0], ov5640_rgb565_reg_tbl[i][1]); + } + + write_reg(bus, 0x3821, 0x06); +} + +rt_uint8_t ov5640_focus_init(struct rt_i2c_bus_device *bus) +{ + rt_uint16_t tickstart = 0 ,i = 0; + rt_uint16_t addr = 0x8000; + rt_uint8_t state = 0x8F; + + write_reg(bus, 0x3000, 0x20); //reset MCU + for (i = 0; i < sizeof(OV5640_AF_Config); i++) + { + write_reg(bus, addr, OV5640_AF_Config[i]); + addr++; + } + write_reg(bus, 0x3022, 0x00); + write_reg(bus, 0x3023, 0x00); + write_reg(bus, 0x3024, 0x00); + write_reg(bus, 0x3025, 0x00); + write_reg(bus, 0x3026, 0x00); + write_reg(bus, 0x3027, 0x00); + write_reg(bus, 0x3028, 0x00); + write_reg(bus, 0x3029, 0x7f); + write_reg(bus, 0x3000, 0x00); + i = 0; + + tickstart = rt_tick_get(); + do + { + read_reg(bus, 0x3029, 1, &state); + if (rt_tick_get() - tickstart > 1000) + { + return RT_ERROR; + } + } while (state != 0x70); + + return RT_EOK; +} + +void ov5640_set_light(struct rt_i2c_bus_device *bus, rt_uint8_t mode) +{ + rt_uint8_t i = 0; + write_reg(bus, 0x3212, 0x03); //start group 3 + + for (i = 0; i < 7; i++) + { + write_reg(bus, 0x3400 + i, OV5640_LIGHTMODE_TBL[mode][i]); + } + + write_reg(bus, 0x3212, 0x13); //end group 3 + write_reg(bus, 0x3212, 0xa3); //launch group 3 +} + +/* sat:0~6 */ +void ov5640_color_saturation(struct rt_i2c_bus_device *bus, rt_uint8_t sat) +{ + rt_uint8_t i = 0; + write_reg(bus, 0x3212, 0x03); //start group 3 + write_reg(bus, 0x5381, 0x1c); + write_reg(bus, 0x5382, 0x5a); + write_reg(bus, 0x5383, 0x06); + for (i = 0; i < 6; i++) + { + write_reg(bus, 0x5384 + i, OV5640_SATURATION_TBL[sat][i]); + } + write_reg(bus, 0x538b, 0x98); + write_reg(bus, 0x538a, 0x01); + write_reg(bus, 0x3212, 0x13); //end group 3 + write_reg(bus, 0x3212, 0xa3); //launch group 3 +} + +/* bright:0~8 */ +void ov5640_set_brightness(struct rt_i2c_bus_device *bus, rt_uint8_t bright) +{ + rt_uint8_t brtval; + if (bright < 4) + { + brtval = 4 - bright; + } + else + { + brtval = bright - 4; + } + write_reg(bus, 0x3212, 0x03); //start group 3 + write_reg(bus, 0x5587, brtval << 4); + if (bright < 4) + { + write_reg(bus, 0x5588, 0x09); + } + else + { + write_reg(bus, 0x5588, 0x01); + } + write_reg(bus, 0x3212, 0x13); //end group 3 + write_reg(bus, 0x3212, 0xa3); //launch group 3 +} + +/* contrast:0~6 */ +void ov5640_contrast(struct rt_i2c_bus_device *bus, rt_uint8_t contrast) +{ + rt_uint8_t reg0val = 0x00; + rt_uint8_t reg1val = 0x20; + switch (contrast) + { + case 0: + reg1val = reg0val = 0X14; + break; + + case 1: + reg1val = reg0val = 0X18; + break; + + case 2: + reg1val = reg0val = 0X1C; + break; + + case 4: + reg0val = 0X10; + reg1val = 0X24; + break; + + case 5: + reg0val = 0X18; + reg1val = 0X28; + break; + + case 6: + reg0val = 0X1C; + reg1val = 0X2C; + + break; + } + write_reg(bus, 0x3212, 0x03); //start group 3 + write_reg(bus, 0x5585, reg0val); + write_reg(bus, 0x5586, reg1val); + write_reg(bus, 0x3212, 0x13); //end group 3 + write_reg(bus, 0x3212, 0xa3); //launch group 3 +} +/* sharp:0~33 */ +void ov5640_set_sharpness(struct rt_i2c_bus_device *bus, rt_uint8_t sharp) +{ + if (sharp < 33) + { + write_reg(bus, 0x5308, 0x65); + write_reg(bus, 0x5302, sharp); + } + else + { + write_reg(bus, 0x5308, 0x25); + write_reg(bus, 0x5300, 0x08); + write_reg(bus, 0x5301, 0x30); + write_reg(bus, 0x5302, 0x10); + write_reg(bus, 0x5303, 0x00); + write_reg(bus, 0x5309, 0x08); + write_reg(bus, 0x530a, 0x30); + write_reg(bus, 0x530b, 0x04); + write_reg(bus, 0x530c, 0x06); + } +} + +rt_uint8_t ov5640_focus_constant(struct rt_i2c_bus_device *bus) +{ + rt_uint8_t temp = 0; + rt_uint16_t tickstrat = 0; + + write_reg(bus, 0x3023, 0x01); + write_reg(bus, 0x3022, 0x08); + do + { + tickstrat = rt_tick_get(); + read_reg(bus, 0x3023, 1, &temp); + if (rt_tick_get() - tickstrat > 1000) + { + return RT_ERROR; + } + } while (temp != 0x00); + + write_reg(bus, 0x3023, 0x01); + write_reg(bus, 0x3022, 0x04); + + do + { + tickstrat = rt_tick_get(); + read_reg(bus, 0x3023, 1, &temp); + if (rt_tick_get() - tickstrat > 1000) + { + return RT_ERROR; + } + } while (temp != 0x00); + + return 0; +} + +rt_uint8_t ov5640_set_outsize(struct rt_i2c_bus_device *bus, rt_uint16_t offx, rt_uint16_t offy, rt_uint16_t width, rt_uint16_t height) +{ + write_reg(bus, 0X3212, 0X03); + + write_reg(bus, 0x3808, width >> 8); + write_reg(bus, 0x3809, width & 0xff); + write_reg(bus, 0x380a, height >> 8); + write_reg(bus, 0x380b, height & 0xff); + + write_reg(bus, 0x3810, offx >> 8); + write_reg(bus, 0x3811, offx & 0xff); + + write_reg(bus, 0x3812, offy >> 8); + write_reg(bus, 0x3813, offy & 0xff); + + write_reg(bus, 0X3212, 0X13); + write_reg(bus, 0X3212, 0Xa3); + + return RT_EOK; +} + +void rt_hw_camera_rx_callback(void) +{ + rt_uint16_t i; + rt_int32_t *pbuf = RT_NULL; + pbuf = JPEG_DATA_BUF + jpeg_data_len; + + if (hdma_dcmi.Instance->CR & (1 << 19)) + { + for (i = 0; i < JPEG_LINE_SIZE; i++) + { + pbuf[i] = JPEG_LINE_BUF[0][i]; + } + jpeg_data_len += JPEG_LINE_SIZE; + + } + else + { + for (i = 0; i < JPEG_LINE_SIZE; i++) + { + pbuf[i] = JPEG_LINE_BUF[1][i]; + } + jpeg_data_len += JPEG_LINE_SIZE; + } +} + +/* After a frame of JPEG data has been collected. */ +void jpeg_data_process(void) +{ + rt_uint16_t i, rlen; + int *pbuf = RT_NULL; + + if (!jpeg_data_ok) + { + __HAL_DMA_DISABLE(&hdma_dcmi); + rlen = JPEG_LINE_SIZE - __HAL_DMA_GET_COUNTER(&hdma_dcmi); + pbuf = JPEG_DATA_BUF + jpeg_data_len; + if (hdma_dcmi.Instance->CR & (1 << 19)) + { + for (i = 0; i < rlen; i++) + { + pbuf[i] = JPEG_LINE_BUF[1][i]; + } + } + else + { + for (i = 0; i < rlen; i++) + { + pbuf[i] = JPEG_LINE_BUF[0][i]; + } + } + jpeg_data_len += rlen; + jpeg_data_ok = 1; + } + + if (jpeg_data_ok == 2) + { + __HAL_DMA_SET_COUNTER(&hdma_dcmi, JPEG_LINE_SIZE); + __HAL_DMA_ENABLE(&hdma_dcmi); + + jpeg_data_ok = 0; + jpeg_data_len = 0; + } +} + +int rt_hw_ov5640_init(void) +{ + extern void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint16_t len); + + static rt_uint16_t id = 0; + rt_device_t dcmi_dev = RT_NULL; + + i2c_bus = rt_i2c_bus_device_find(I2C_NAME); + if (i2c_bus == RT_NULL) + { + LOG_E("can't find %c deivce", I2C_NAME); + return RT_ERROR; + } + + ov5640_hard_reset(i2c_bus); + ov5640_read_id(i2c_bus, &id); + ov5640_config(i2c_bus); + ov5640_rgb565_mode(i2c_bus); /* rgb565 mode */ + ov5640_focus_init(i2c_bus); + ov5640_jpeg_mode(i2c_bus); /* jpeg mode */ + ov5640_set_light(i2c_bus, 0); /* auto mode */ + ov5640_color_saturation(i2c_bus, 3); + ov5640_set_brightness(i2c_bus, 4); /* brigetness 0 */ + ov5640_contrast(i2c_bus, 3); + ov5640_set_sharpness(i2c_bus, 33); + ov5640_focus_constant(i2c_bus); + + /* dcmi init */ + dcmi_dev = rt_device_find("dcmi"); + if (dcmi_dev == RT_NULL) + { + LOG_E("can't find dcmi device!"); + return RT_ERROR; + } + rt_device_open(dcmi_dev, RT_DEVICE_FLAG_RDWR); + + rt_hw_dcmi_dma_config((rt_uint32_t)&JPEG_LINE_BUF[0], (rt_uint32_t)&JPEG_LINE_BUF[1], JPEG_LINE_SIZE); + ov5640_set_outsize(i2c_bus, 4, 0, jpeg_picture_size[1][0], jpeg_picture_size[1][1]); + + return RT_EOK; +} +INIT_APP_EXPORT(rt_hw_ov5640_init); + +int camera_sample(int argc, char **argv) +{ + + int fd = -1; + rt_uint32_t i, jpg_start, jpg_len; + rt_uint16_t tickstart = 0; + rt_uint8_t jpg_head = 0; + rt_uint8_t *p = RT_NULL; + + if (argc != 2) + { + rt_kprintf("Usage:\n"); + rt_kprintf("camera_sample file.jpg\n"); + return -1; + } + + /* start dcmi capture */ + __HAL_DMA_ENABLE(&hdma_dcmi); + dcmi.Instance->CR |= DCMI_CR_CAPTURE; + + tickstart = rt_tick_get(); + while (1) + { + if (rt_tick_get() - tickstart > 1000) + { + LOG_E("picture capture overtime!"); + break; + } + + if (jpeg_data_ok == 1) + { + dcmi.Instance->CR &= ~(DCMI_CR_CAPTURE); + tickstart = rt_tick_get(); + while(dcmi.Instance->CR & 0x01) + { + if (rt_tick_get() - tickstart > 0x1000) + { + rt_kprintf("dcmi close failed!\n"); + jpeg_data_ok = 2; + break; + } + } + __HAL_DMA_DISABLE(&hdma_dcmi); + + p = (rt_uint8_t *)JPEG_DATA_BUF; + jpg_len = 0; + jpg_head = 0; + for (i = 0; i < jpeg_data_len * 4; i++) + { + /* jpg head */ + if ((p[i] == 0xFF) && (p[i + 1] == 0xD8)) + { + jpg_start = i; + jpg_head = 1; + } + /* jpg end */ + if ((p[i] == 0xFF) && (p[i + 1] == 0xD9) && jpg_head) + { + jpg_len = i - jpg_start + 2; /* a picture len */ + break; + } + } + + if (jpg_len) + { + p += jpg_start; + + fd = open(argv[1], O_WRONLY | O_CREAT); + if (fd < 0) + { + rt_kprintf("open file for recording failed!\n"); + return -RT_ERROR; + } + else + { + write(fd, p, jpg_len); + close(fd); + rt_kprintf("picture capture complate!\n"); + + break; + } + } + + jpeg_data_ok = 2; + } + } + + return RT_EOK; +} +MSH_CMD_EXPORT(camera_sample, record picture to a jpg file); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h new file mode 100644 index 0000000000..d005150482 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h @@ -0,0 +1,653 @@ + +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu first version + */ + +#ifndef __DRV_OV5640_H__ +#define __DRV_OV5640_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief OV5640 ID + */ +#define OV5640_ID 0x5640U + +/* JPEG picture size table */ +static const unsigned short jpeg_picture_size[][2] = +{ + 160, 120, /* QQVGA */ + 320, 240, /* QVGA */ + 640, 480, /* VGA */ + 800, 600, /* SVGA */ + 1024, 768, /* XGA */ + 1280, 800, /* WXGA */ + 1440, 900, /* WXGA+ */ + 1280, 1024, /* SXGA */ + 1600, 1200, /* UXGA */ + 1920, 1080, /* 1080P */ + 2048, 1536, /* QXGA */ + 2592, 1944, /* 500W */ +}; + +/* camera light mode */ +static const unsigned char OV5640_LIGHTMODE_TBL[5][7]= +{ + 0x04,0X00,0X04,0X00,0X04,0X00,0X00, /* Auto */ + 0x06,0X1C,0X04,0X00,0X04,0XF3,0X01, /* Sunny */ + 0x05,0X48,0X04,0X00,0X07,0XCF,0X01, /* Office */ + 0x06,0X48,0X04,0X00,0X04,0XD3,0X01, /* Cloudy */ + 0x04,0X10,0X04,0X00,0X08,0X40,0X01, /* Home */ +}; + +/* Table of color saturation setting parameters */ +static const unsigned char OV5640_SATURATION_TBL[7][6]= +{ + 0X0C,0x30,0X3D,0X3E,0X3D,0X01, /* -3 */ + 0X10,0x3D,0X4D,0X4E,0X4D,0X01, /* -2 */ + 0X15,0x52,0X66,0X68,0X66,0X02, /* -1 */ + 0X1A,0x66,0X80,0X82,0X80,0X02, /* 0 */ + 0X1F,0x7A,0X9A,0X9C,0X9A,0X02, /* 1 */ + 0X24,0x8F,0XB3,0XB6,0XB3,0X03, /* 2 */ + 0X2B,0xAB,0XD6,0XDA,0XD6,0X04, /* 3 */ +}; + +static const unsigned short OV5640_jpeg_reg_tbl[][2]= +{ + 0x4300, 0x30, // YUV 422, YUYV + 0x501f, 0x00, // YUV 422 + // Input clock = 24Mhz + 0x3035, 0x21, // PLL + 0x3036, 0x69, // PLL + 0x3c07, 0x07, // lightmeter 1 threshold[7:0] + 0x3820, 0x46, // flip + 0x3821, 0x20, // mirror + 0x3814, 0x11, // timing X inc + 0x3815, 0x11, // timing Y inc + 0x3800, 0x00, // HS + 0x3801, 0x00, // HS + 0x3802, 0x00, // VS + 0x3803, 0x00, // VS + 0x3804, 0x0a, // HW (HE) + 0x3805, 0x3f, // HW (HE) + 0x3806, 0x07, // VH (VE) + 0x3807, 0x9f, // VH (VE) + + 0x3808, 0x02, // DVPHO + 0x3809, 0x80, // DVPHO + 0x380a, 0x01, // DVPVO + 0x380b, 0xe0, // DVPVO + + 0x380c, 0x0b, // HTS // + 0x380d, 0x1c, // HTS + 0x380e, 0x07, // VTS // + 0x380f, 0xb0, // VTS + 0x3813, 0x04, // timing V offset 04 + 0x3618, 0x04, + 0x3612, 0x2b, + 0x3709, 0x12, + 0x370c, 0x00, + + 0x4004, 0x06, // BLC line number + 0x3002, 0x00, // enable JFIFO, SFIFO, JPG + 0x3006, 0xff, // enable clock of JPEG2x, JPEG + 0x4713, 0x03, // JPEG mode 3 + 0x4407, 0x01, // Quantization sacle + 0x460b, 0x35, + 0x460c, 0x22, + 0x4837, 0x16, // MIPI global timing + 0x3824, 0x02, // PCLK manual divider + 0x5001, 0xA3, // SDE on, Scaling on, CMX on, AWB on + 0x3503, 0x00, // AEC/AGC on +}; + +/* RGB565 configuration, 15 frames */ +static const unsigned short ov5640_rgb565_reg_tbl[][2]= +{ + 0x4300, 0X6F, + 0X501F, 0x01, + // 1280x800, 15fps + // input clock 24Mhz, PCLK 42Mhz + 0x3035, 0x41, // PLL + 0x3036, 0x69, // PLL + 0x3c07, 0x07, // lightmeter 1 threshold[7:0] + 0x3820, 0x46, // flip + 0x3821, 0x00, // mirror + 0x3814, 0x31, // timing X inc + 0x3815, 0x31, // timing Y inc + 0x3800, 0x00, // HS + 0x3801, 0x00, // HS + 0x3802, 0x00, // VS + 0x3803, 0x00, // VS + 0x3804, 0x0a, // HW (HE) + 0x3805, 0x3f, // HW (HE) + 0x3806, 0x06, // VH (VE) + 0x3807, 0xa9, // VH (VE) + 0x3808, 0x05, // DVPHO + 0x3809, 0x00, // DVPHO + 0x380a, 0x02, // DVPVO + 0x380b, 0xd0, // DVPVO + 0x380c, 0x05, // HTS + 0x380d, 0xF8, // HTS + 0x380e, 0x03, // VTS + 0x380f, 0x84, // VTS + 0x3813, 0x04, // timing V offset + 0x3618, 0x00, + 0x3612, 0x29, + 0x3709, 0x52, + 0x370c, 0x03, + 0x3a02, 0x02, // 60Hz max exposure + 0x3a03, 0xe0, // 60Hz max exposure + + 0x3a14, 0x02, // 50Hz max exposure + 0x3a15, 0xe0, // 50Hz max exposure + 0x4004, 0x02, // BLC line number + 0x3002, 0x1c, // reset JFIFO, SFIFO, JPG + 0x3006, 0xc3, // disable clock of JPEG2x, JPEG + 0x4713, 0x03, // JPEG mode 3 + 0x4407, 0x04, // Quantization scale + 0x460b, 0x37, + 0x460c, 0x20, + 0x4837, 0x16, // MIPI global timing + 0x3824, 0x04, // PCLK manual divider + 0x5001, 0xA3, // SDE on, scale on, UV average off, color matrix on, AWB on + 0x3503, 0x00, // AEC/AGC on +}; + +static const unsigned short RGB565_Init[][2]= +{ + /* 24MHz input clock, 24MHz PCLK */ + 0x3008, 0x42, // software power down, bit[6] + 0x3103, 0x03, // system clock from PLL, bit[1] + 0x3017, 0xff, // FREX, Vsync, HREF, PCLK, D[9:6] output enable + 0x3018, 0xff, // D[5:0], GPIO[1:0] output enable + 0x3034, 0x1a, // MIPI 10-bit + 0x3037, 0x13, // PLL root divider, bit[4], PLL pre-divider, bit[3:0] + 0x3108, 0x01, // PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] + + // SCLK root divider, bit[1:0] + 0x3630, 0x36, + 0x3631, 0x0e, + 0x3632, 0xe2, + 0x3633, 0x12, + 0x3621, 0xe0, + 0x3704, 0xa0, + 0x3703, 0x5a, + 0x3715, 0x78, + 0x3717, 0x01, + 0x370b, 0x60, + 0x3705, 0x1a, + 0x3905, 0x02, + 0x3906, 0x10, + 0x3901, 0x0a, + 0x3731, 0x12, + 0x3600, 0x08, // VCM control + 0x3601, 0x33, // VCM control + 0x302d, 0x60, // system control + 0x3620, 0x52, + 0x371b, 0x20, + 0x471c, 0x50, + 0x3a13, 0x43, // pre-gain = 1.047x + 0x3a18, 0x00, // gain ceiling + 0x3a19, 0xf8, // gain ceiling = 15.5x + 0x3635, 0x13, + 0x3636, 0x03, + 0x3634, 0x40, + 0x3622, 0x01, + // 50/60Hz detection 50/60Hz + 0x3c01, 0x34, // Band auto, bit[7] + 0x3c04, 0x28, // threshold low sum + 0x3c05, 0x98, // threshold high sum + 0x3c06, 0x00, // light meter 1 threshold[15:8] + 0x3c07, 0x08, // light meter 1 threshold[7:0] + 0x3c08, 0x00, // light meter 2 threshold[15:8] + 0x3c09, 0x1c, // light meter 2 threshold[7:0] + 0x3c0a, 0x9c, // sample number[15:8] + 0x3c0b, 0x40, // sample number[7:0] + 0x3810, 0x00, // Timing Hoffset[11:8] + 0x3811, 0x10, // Timing Hoffset[7:0] + 0x3812, 0x00, // Timing Voffset[10:8] + 0x3708, 0x64, + 0x4001, 0x02, // BLC start from line 2 + 0x4005, 0x1a, // BLC always update + 0x3000, 0x00, // enable blocks + 0x3004, 0xff, // enable clocks + 0x300e, 0x58, // MIPI power down, DVP enable + 0x302e, 0x00, + 0x4300, 0x30, // YUV 422, YUYV + 0x501f, 0x00, // YUV 422 + 0x440e, 0x00, + 0x5000, 0xa7, // Lenc on, raw gamma on, BPC on, WPC on, CIP on + // AEC target + 0x3a0f, 0x30, // stable range in high + 0x3a10, 0x28, // stable range in low + 0x3a1b, 0x30, // stable range out high + 0x3a1e, 0x26, // stable range out low + 0x3a11, 0x60, // fast zone high + 0x3a1f, 0x14, // fast zone low + // Lens correction + 0x5800, 0x23, + 0x5801, 0x14, + 0x5802, 0x0f, + 0x5803, 0x0f, + 0x5804, 0x12, + 0x5805, 0x26, + 0x5806, 0x0c, + 0x5807, 0x08, + 0x5808, 0x05, + 0x5809, 0x05, + 0x580a, 0x08, + + 0x580b, 0x0d, + 0x580c, 0x08, + 0x580d, 0x03, + 0x580e, 0x00, + 0x580f, 0x00, + 0x5810, 0x03, + 0x5811, 0x09, + 0x5812, 0x07, + 0x5813, 0x03, + 0x5814, 0x00, + 0x5815, 0x01, + 0x5816, 0x03, + 0x5817, 0x08, + 0x5818, 0x0d, + 0x5819, 0x08, + 0x581a, 0x05, + 0x581b, 0x06, + 0x581c, 0x08, + 0x581d, 0x0e, + 0x581e, 0x29, + 0x581f, 0x17, + 0x5820, 0x11, + 0x5821, 0x11, + 0x5822, 0x15, + 0x5823, 0x28, + 0x5824, 0x46, + 0x5825, 0x26, + 0x5826, 0x08, + 0x5827, 0x26, + 0x5828, 0x64, + 0x5829, 0x26, + 0x582a, 0x24, + 0x582b, 0x22, + 0x582c, 0x24, + 0x582d, 0x24, + 0x582e, 0x06, + 0x582f, 0x22, + 0x5830, 0x40, + 0x5831, 0x42, + 0x5832, 0x24, + 0x5833, 0x26, + 0x5834, 0x24, + 0x5835, 0x22, + 0x5836, 0x22, + 0x5837, 0x26, + 0x5838, 0x44, + 0x5839, 0x24, + 0x583a, 0x26, + 0x583b, 0x28, + 0x583c, 0x42, + 0x583d, 0xce, // lenc BR offset + // AWB + 0x5180, 0xff, // AWB B block + 0x5181, 0xf2, // AWB control + 0x5182, 0x00, // [7:4] max local counter, [3:0] max fast counter + 0x5183, 0x14, // AWB advanced + 0x5184, 0x25, + 0x5185, 0x24, + 0x5186, 0x09, + 0x5187, 0x09, + 0x5188, 0x09, + 0x5189, 0x75, + 0x518a, 0x54, + 0x518b, 0xe0, + 0x518c, 0xb2, + 0x518d, 0x42, + 0x518e, 0x3d, + 0x518f, 0x56, + 0x5190, 0x46, + 0x5191, 0xf8, // AWB top limit + 0x5192, 0x04, // AWB bottom limit + 0x5193, 0x70, // red limit + 0x5194, 0xf0, // green limit + 0x5195, 0xf0, // blue limit + 0x5196, 0x03, // AWB control + 0x5197, 0x01, // local limit + 0x5198, 0x04, + 0x5199, 0x12, + 0x519a, 0x04, + 0x519b, 0x00, + 0x519c, 0x06, + 0x519d, 0x82, + 0x519e, 0x38, // AWB control + // Gamma + 0x5480, 0x01, // Gamma bias plus on, bit[0] + 0x5481, 0x08, + 0x5482, 0x14, + 0x5483, 0x28, + 0x5484, 0x51, + 0x5485, 0x65, + 0x5486, 0x71, + 0x5487, 0x7d, + 0x5488, 0x87, + 0x5489, 0x91, + 0x548a, 0x9a, + 0x548b, 0xaa, + 0x548c, 0xb8, + 0x548d, 0xcd, + 0x548e, 0xdd, + 0x548f, 0xea, + 0x5490, 0x1d, + // color matrix + 0x5381, 0x1e, // CMX1 for Y + 0x5382, 0x5b, // CMX2 for Y + 0x5383, 0x08, // CMX3 for Y + 0x5384, 0x0a, // CMX4 for U + 0x5385, 0x7e, // CMX5 for U + 0x5386, 0x88, // CMX6 for U + 0x5387, 0x7c, // CMX7 for V + 0x5388, 0x6c, // CMX8 for V + 0x5389, 0x10, // CMX9 for V + 0x538a, 0x01, // sign[9] + 0x538b, 0x98, // sign[8:1] + // UV adjust UV + 0x5580, 0x06, // saturation on, bit[1] + 0x5583, 0x40, + 0x5584, 0x10, + 0x5589, 0x10, + 0x558a, 0x00, + 0x558b, 0xf8, + 0x501d, 0x40, // enable manual offset of contrast + // CIP + 0x5300, 0x08, // CIP sharpen MT threshold 1 + 0x5301, 0x30, // CIP sharpen MT threshold 2 + 0x5302, 0x10, // CIP sharpen MT offset 1 + 0x5303, 0x00, // CIP sharpen MT offset 2 + 0x5304, 0x08, // CIP DNS threshold 1 + 0x5305, 0x30, // CIP DNS threshold 2 + 0x5306, 0x08, // CIP DNS offset 1 + 0x5307, 0x16, // CIP DNS offset 2 + 0x5309, 0x08, // CIP sharpen TH threshold 1 + 0x530a, 0x30, // CIP sharpen TH threshold 2 + 0x530b, 0x04, // CIP sharpen TH offset 1 + 0x530c, 0x06, // CIP sharpen TH offset 2 + 0x5025, 0x00, + 0x3008, 0x02, // wake up from standby, bit[6] + + 0x4740, 0X21, //VSYNC +}; + +/* Autofocus initialization configuration */ +const unsigned char OV5640_AF_Config[] = +{ + 0x02, 0x0f, 0xd6, 0x02, 0x0a, 0x39, 0xc2, 0x01, 0x22, 0x22, 0x00, 0x02, 0x0f, 0xb2, 0xe5, 0x1f, //0x8000, + 0x70, 0x72, 0xf5, 0x1e, 0xd2, 0x35, 0xff, 0xef, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xe4, 0xf6, 0x08, //0x8010, + 0xf6, 0x0f, 0xbf, 0x34, 0xf2, 0x90, 0x0e, 0x93, 0xe4, 0x93, 0xff, 0xe5, 0x4b, 0xc3, 0x9f, 0x50, //0x8020, + 0x04, 0x7f, 0x05, 0x80, 0x02, 0x7f, 0xfb, 0x78, 0xbd, 0xa6, 0x07, 0x12, 0x0f, 0x04, 0x40, 0x04, //0x8030, + 0x7f, 0x03, 0x80, 0x02, 0x7f, 0x30, 0x78, 0xbc, 0xa6, 0x07, 0xe6, 0x18, 0xf6, 0x08, 0xe6, 0x78, //0x8040, + 0xb9, 0xf6, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xbf, 0x76, 0x33, 0xe4, 0x08, 0xf6, 0x78, //0x8050, + 0xb8, 0x76, 0x01, 0x75, 0x4a, 0x02, 0x78, 0xb6, 0xf6, 0x08, 0xf6, 0x74, 0xff, 0x78, 0xc1, 0xf6, //0x8060, + 0x08, 0xf6, 0x75, 0x1f, 0x01, 0x78, 0xbc, 0xe6, 0x75, 0xf0, 0x05, 0xa4, 0xf5, 0x4b, 0x12, 0x0a, //0x8070, + 0xff, 0xc2, 0x37, 0x22, 0x78, 0xb8, 0xe6, 0xd3, 0x94, 0x00, 0x40, 0x02, 0x16, 0x22, 0xe5, 0x1f, //0x8080, + 0xb4, 0x05, 0x23, 0xe4, 0xf5, 0x1f, 0xc2, 0x01, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x78, //0x8090, + 0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c, 0x90, 0x30, 0x28, 0xf0, //0x80a0, + 0x75, 0x1e, 0x10, 0xd2, 0x35, 0x22, 0xe5, 0x4b, 0x75, 0xf0, 0x05, 0x84, 0x78, 0xbc, 0xf6, 0x90, //0x80b0, + 0x0e, 0x8c, 0xe4, 0x93, 0xff, 0x25, 0xe0, 0x24, 0x0a, 0xf8, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x78, //0x80c0, + 0xbc, 0xe6, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0xef, 0x12, 0x0f, 0x0b, //0x80d0, + 0xd3, 0x78, 0xb7, 0x96, 0xee, 0x18, 0x96, 0x40, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xb9, 0xf6, 0x78, //0x80e0, + 0xb6, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x8c, 0xe4, 0x93, 0x12, 0x0f, 0x0b, 0xc3, 0x78, //0x80f0, + 0xc2, 0x96, 0xee, 0x18, 0x96, 0x50, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xc1, 0xa6, //0x8100, + 0x06, 0x08, 0xa6, 0x07, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xc3, 0x78, 0xc2, 0x96, 0xff, 0xee, //0x8110, + 0x18, 0x96, 0x78, 0xc3, 0xf6, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x95, 0xe4, 0x18, 0x12, 0x0e, 0xe9, //0x8120, + 0x40, 0x02, 0xd2, 0x37, 0x78, 0xbc, 0xe6, 0x08, 0x26, 0x08, 0xf6, 0xe5, 0x1f, 0x64, 0x01, 0x70, //0x8130, + 0x4a, 0xe6, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xdf, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, 0x39, 0x12, //0x8140, + 0x0f, 0x02, 0x40, 0x04, 0x7f, 0xfe, 0x80, 0x02, 0x7f, 0x02, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, //0x8150, + 0xe6, 0x24, 0x03, 0x78, 0xbf, 0xf6, 0x78, 0xb9, 0xe6, 0x24, 0xfd, 0x78, 0xc0, 0xf6, 0x12, 0x0f, //0x8160, + 0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8170, + 0x07, 0x75, 0x1f, 0x02, 0x78, 0xb8, 0x76, 0x01, 0x02, 0x02, 0x4a, 0xe5, 0x1f, 0x64, 0x02, 0x60, //0x8180, + 0x03, 0x02, 0x02, 0x2a, 0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x08, //0x8190, + 0x12, 0x0e, 0xda, 0x50, 0x03, 0x02, 0x02, 0x28, 0x12, 0x0f, 0x02, 0x40, 0x04, 0x7f, 0xff, 0x80, //0x81a0, + 0x02, 0x7f, 0x01, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, 0xe6, 0x04, 0x78, 0xbf, 0xf6, 0x78, 0xb9, //0x81b0, + 0xe6, 0x14, 0x78, 0xc0, 0xf6, 0x18, 0x12, 0x0f, 0x04, 0x40, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, //0x81c0, + 0x00, 0x78, 0xbf, 0xa6, 0x07, 0xd3, 0x08, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x40, 0x04, 0xe6, 0xff, //0x81d0, + 0x80, 0x02, 0x7f, 0x00, 0x78, 0xc0, 0xa6, 0x07, 0xc3, 0x18, 0xe6, 0x64, 0x80, 0x94, 0xb3, 0x50, //0x81e0, + 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xbf, 0xa6, 0x07, 0xc3, 0x08, 0xe6, 0x64, 0x80, //0x81f0, + 0x94, 0xb3, 0x50, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xc0, 0xa6, 0x07, 0x12, 0x0f, //0x8200, + 0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8210, + 0x07, 0x75, 0x1f, 0x03, 0x78, 0xb8, 0x76, 0x01, 0x80, 0x20, 0xe5, 0x1f, 0x64, 0x03, 0x70, 0x26, //0x8220, + 0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, //0x8230, + 0x09, 0x78, 0xb9, 0xe6, 0x78, 0xbe, 0xf6, 0x75, 0x1f, 0x04, 0x78, 0xbe, 0xe6, 0x75, 0xf0, 0x05, //0x8240, + 0xa4, 0xf5, 0x4b, 0x02, 0x0a, 0xff, 0xe5, 0x1f, 0xb4, 0x04, 0x10, 0x90, 0x0e, 0x94, 0xe4, 0x78, //0x8250, + 0xc3, 0x12, 0x0e, 0xe9, 0x40, 0x02, 0xd2, 0x37, 0x75, 0x1f, 0x05, 0x22, 0x30, 0x01, 0x03, 0x02, //0x8260, + 0x04, 0xc0, 0x30, 0x02, 0x03, 0x02, 0x04, 0xc0, 0x90, 0x51, 0xa5, 0xe0, 0x78, 0x93, 0xf6, 0xa3, //0x8270, + 0xe0, 0x08, 0xf6, 0xa3, 0xe0, 0x08, 0xf6, 0xe5, 0x1f, 0x70, 0x3c, 0x75, 0x1e, 0x20, 0xd2, 0x35, //0x8280, + 0x12, 0x0c, 0x7a, 0x78, 0x7e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xa6, 0x09, 0x18, 0x76, //0x8290, + 0x01, 0x12, 0x0c, 0x5b, 0x78, 0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xe6, 0x78, 0x6e, //0x82a0, + 0xf6, 0x75, 0x1f, 0x01, 0x78, 0x93, 0xe6, 0x78, 0x90, 0xf6, 0x78, 0x94, 0xe6, 0x78, 0x91, 0xf6, //0x82b0, + 0x78, 0x95, 0xe6, 0x78, 0x92, 0xf6, 0x22, 0x79, 0x90, 0xe7, 0xd3, 0x78, 0x93, 0x96, 0x40, 0x05, //0x82c0, + 0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x93, 0xe7, 0x78, 0x90, 0x96, 0xff, 0x78, 0x88, 0x76, //0x82d0, + 0x00, 0x08, 0xa6, 0x07, 0x79, 0x91, 0xe7, 0xd3, 0x78, 0x94, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, //0x82e0, + 0x80, 0x08, 0xc3, 0x79, 0x94, 0xe7, 0x78, 0x91, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x79, 0x92, 0xe7, //0x82f0, + 0xd3, 0x78, 0x95, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x95, 0xe7, 0x78, //0x8300, + 0x92, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x12, 0x0c, 0x5b, 0x78, 0x8a, 0xe6, 0x25, 0xe0, 0x24, 0x4e, //0x8310, + 0xf8, 0xa6, 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//0x8ce0, + 0xd2, 0x36, 0x30, 0x0e, 0x03, 0x12, 0x06, 0xd7, 0x30, 0x35, 0xd3, 0x90, 0x30, 0x29, 0xe5, 0x1e, //0x8cf0, + 0xf0, 0xb4, 0x10, 0x05, 0x90, 0x30, 0x23, 0xe4, 0xf0, 0xc2, 0x35, 0x80, 0xc1, 0xe4, 0xf5, 0x4b, //0x8d00, + 0x90, 0x0e, 0x7a, 0x93, 0xff, 0xe4, 0x8f, 0x37, 0xf5, 0x36, 0xf5, 0x35, 0xf5, 0x34, 0xaf, 0x37, //0x8d10, + 0xae, 0x36, 0xad, 0x35, 0xac, 0x34, 0x90, 0x0e, 0x6a, 0x12, 0x0d, 0xf6, 0x8f, 0x37, 0x8e, 0x36, //0x8d20, + 0x8d, 0x35, 0x8c, 0x34, 0x90, 0x0e, 0x72, 0x12, 0x06, 0x7c, 0xef, 0x45, 0x37, 0xf5, 0x37, 0xee, //0x8d30, + 0x45, 0x36, 0xf5, 0x36, 0xed, 0x45, 0x35, 0xf5, 0x35, 0xec, 0x45, 0x34, 0xf5, 0x34, 0xe4, 0xf5, //0x8d40, + 0x22, 0xf5, 0x23, 0x85, 0x37, 0x31, 0x85, 0x36, 0x30, 0x85, 0x35, 0x2f, 0x85, 0x34, 0x2e, 0x12, //0x8d50, + 0x0f, 0x46, 0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x90, 0x0e, 0x72, 0x12, 0x0d, 0xea, 0x12, 0x0f, 0x46, //0x8d60, + 0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x90, 0x0e, 0x6e, 0x12, 0x0d, 0xea, 0x02, 0x0f, 0x46, 0xe5, 0x40, //0x8d70, + 0x24, 0xf2, 0xf5, 0x37, 0xe5, 0x3f, 0x34, 0x43, 0xf5, 0x36, 0xe5, 0x3e, 0x34, 0xa2, 0xf5, 0x35, //0x8d80, + 0xe5, 0x3d, 0x34, 0x28, 0xf5, 0x34, 0xe5, 0x37, 0xff, 0xe4, 0xfe, 0xfd, 0xfc, 0x78, 0x18, 0x12, //0x8d90, + 0x06, 0x69, 0x8f, 0x40, 0x8e, 0x3f, 0x8d, 0x3e, 0x8c, 0x3d, 0xe5, 0x37, 0x54, 0xa0, 0xff, 0xe5, //0x8da0, + 0x36, 0xfe, 0xe4, 0xfd, 0xfc, 0x78, 0x07, 0x12, 0x06, 0x56, 0x78, 0x10, 0x12, 0x0f, 0x9a, 0xe4, //0x8db0, + 0xff, 0xfe, 0xe5, 0x35, 0xfd, 0xe4, 0xfc, 0x78, 0x0e, 0x12, 0x06, 0x56, 0x12, 0x0f, 0x9d, 0xe4, //0x8dc0, + 0xff, 0xfe, 0xfd, 0xe5, 0x34, 0xfc, 0x78, 0x18, 0x12, 0x06, 0x56, 0x78, 0x08, 0x12, 0x0f, 0x9a, //0x8dd0, + 0x22, 0x8f, 0x3b, 0x8e, 0x3a, 0x8d, 0x39, 0x8c, 0x38, 0x22, 0x12, 0x06, 0x7c, 0x8f, 0x31, 0x8e, //0x8de0, + 0x30, 0x8d, 0x2f, 0x8c, 0x2e, 0x22, 0x93, 0xf9, 0xf8, 0x02, 0x06, 0x69, 0x00, 0x00, 0x00, 0x00, //0x8df0, + 0x12, 0x01, 0x17, 0x08, 0x31, 0x15, 0x53, 0x54, 0x44, 0x20, 0x20, 0x20, 0x20, 0x20, 0x13, 0x01, //0x8e00, + 0x10, 0x01, 0x56, 0x40, 0x1a, 0x30, 0x29, 0x7e, 0x00, 0x30, 0x04, 0x20, 0xdf, 0x30, 0x05, 0x40, //0x8e10, + 0xbf, 0x50, 0x03, 0x00, 0xfd, 0x50, 0x27, 0x01, 0xfe, 0x60, 0x00, 0x11, 0x00, 0x3f, 0x05, 0x30, //0x8e20, + 0x00, 0x3f, 0x06, 0x22, 0x00, 0x3f, 0x01, 0x2a, 0x00, 0x3f, 0x02, 0x00, 0x00, 0x36, 0x06, 0x07, //0x8e30, + 0x00, 0x3f, 0x0b, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x01, 0x40, 0xbf, 0x30, 0x01, 0x00, //0x8e40, + 0xbf, 0x30, 0x29, 0x70, 0x00, 0x3a, 0x00, 0x00, 0xff, 0x3a, 0x00, 0x00, 0xff, 0x36, 0x03, 0x36, //0x8e50, + 0x02, 0x41, 0x44, 0x58, 0x20, 0x18, 0x10, 0x0a, 0x04, 0x04, 0x00, 0x03, 0xff, 0x64, 0x00, 0x00, //0x8e60, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x06, 0x06, 0x00, 0x03, 0x51, 0x00, 0x7a, //0x8e70, + 0x50, 0x3c, 0x28, 0x1e, 0x10, 0x10, 0x50, 0x2d, 0x28, 0x16, 0x10, 0x10, 0x02, 0x00, 0x10, 0x0c, //0x8e80, + 0x10, 0x04, 0x0c, 0x6e, 0x06, 0x05, 0x00, 0xa5, 0x5a, 0x00, 0xae, 0x35, 0xaf, 0x36, 0xe4, 0xfd, //0x8e90, + 0xed, 0xc3, 0x95, 0x37, 0x50, 0x33, 0x12, 0x0f, 0xe2, 0xe4, 0x93, 0xf5, 0x38, 0x74, 0x01, 0x93, //0x8ea0, + 0xf5, 0x39, 0x45, 0x38, 0x60, 0x23, 0x85, 0x39, 0x82, 0x85, 0x38, 0x83, 0xe0, 0xfc, 0x12, 0x0f, //0x8eb0, + 0xe2, 0x74, 0x03, 0x93, 0x52, 0x04, 0x12, 0x0f, 0xe2, 0x74, 0x02, 0x93, 0x42, 0x04, 0x85, 0x39, //0x8ec0, + 0x82, 0x85, 0x38, 0x83, 0xec, 0xf0, 0x0d, 0x80, 0xc7, 0x22, 0x78, 0xbe, 0xe6, 0xd3, 0x08, 0xff, //0x8ed0, + 0xe6, 0x64, 0x80, 0xf8, 0xef, 0x64, 0x80, 0x98, 0x22, 0x93, 0xff, 0x7e, 0x00, 0xe6, 0xfc, 0x08, //0x8ee0, + 0xe6, 0xfd, 0x12, 0x04, 0xc1, 0x78, 0xc1, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0xd3, 0xef, 0x9d, 0xee, //0x8ef0, + 0x9c, 0x22, 0x78, 0xbd, 0xd3, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x22, 0x25, 0xe0, 0x24, 0x0a, 0xf8, //0x8f00, + 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x22, 0xe5, 0x3c, 0xd3, 0x94, 0x00, 0x40, 0x0b, 0x90, 0x0e, 0x88, //0x8f10, + 0x12, 0x0b, 0xf1, 0x90, 0x0e, 0x86, 0x80, 0x09, 0x90, 0x0e, 0x82, 0x12, 0x0b, 0xf1, 0x90, 0x0e, //0x8f20, + 0x80, 0xe4, 0x93, 0xf5, 0x44, 0xa3, 0xe4, 0x93, 0xf5, 0x43, 0xd2, 0x06, 0x30, 0x06, 0x03, 0xd3, //0x8f30, + 0x80, 0x01, 0xc3, 0x92, 0x0e, 0x22, 0xa2, 0xaf, 0x92, 0x32, 0xc2, 0xaf, 0xe5, 0x23, 0x45, 0x22, //0x8f40, + 0x90, 0x0e, 0x5d, 0x60, 0x0e, 0x12, 0x0f, 0xcb, 0xe0, 0xf5, 0x2c, 0x12, 0x0f, 0xc8, 0xe0, 0xf5, //0x8f50, + 0x2d, 0x80, 0x0c, 0x12, 0x0f, 0xcb, 0xe5, 0x30, 0xf0, 0x12, 0x0f, 0xc8, 0xe5, 0x31, 0xf0, 0xa2, //0x8f60, + 0x32, 0x92, 0xaf, 0x22, 0xd2, 0x01, 0xc2, 0x02, 0xe4, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, //0x8f70, + 0x33, 0xd2, 0x36, 0xd2, 0x01, 0xc2, 0x02, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, 0x33, 0x22, //0x8f80, + 0xfb, 0xd3, 0xed, 0x9b, 0x74, 0x80, 0xf8, 0x6c, 0x98, 0x22, 0x12, 0x06, 0x69, 0xe5, 0x40, 0x2f, //0x8f90, + 0xf5, 0x40, 0xe5, 0x3f, 0x3e, 0xf5, 0x3f, 0xe5, 0x3e, 0x3d, 0xf5, 0x3e, 0xe5, 0x3d, 0x3c, 0xf5, //0x8fa0, + 0x3d, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82, 0x90, 0x3f, 0x0d, 0xe0, 0xf5, 0x33, 0xe5, 0x33, //0x8fb0, + 0xf0, 0xd0, 0x82, 0xd0, 0x83, 0xd0, 0xe0, 0x32, 0x90, 0x0e, 0x5f, 0xe4, 0x93, 0xfe, 0x74, 0x01, //0x8fc0, + 0x93, 0xf5, 0x82, 0x8e, 0x83, 0x22, 0x78, 0x7f, 0xe4, 0xf6, 0xd8, 0xfd, 0x75, 0x81, 0xcd, 0x02, //0x8fd0, + 0x0c, 0x98, 0x8f, 0x82, 0x8e, 0x83, 0x75, 0xf0, 0x04, 0xed, 0x02, 0x06, 0xa5, //0x8fe0 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c index 4623f41923..174fd3bdac 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c @@ -19,6 +19,8 @@ #define LOG_TAG "drv.pmic" #include <drv_log.h> +#define I2C_NAME "i2c3" + static struct rt_i2c_bus_device *pmic_dev = RT_NULL; /* i2c read reg */ @@ -796,47 +798,47 @@ static rt_err_t rt_hw_pmic_init_register(void) stpmu1_write_reg(BUCK_ICC_TURNOFF_REG, 0x30); stpmu1_write_reg(LDO_ICC_TURNOFF_REG, 0x3b); - /* vddcore */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200); - STPMU1_Regulator_Enable(STPMU1_BUCK1); + /* vddcore */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200); + STPMU1_Regulator_Enable(STPMU1_BUCK1); - /* vddddr */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350); - STPMU1_Regulator_Enable(STPMU1_BUCK2); + /* vddddr */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350); + STPMU1_Regulator_Enable(STPMU1_BUCK2); - /* vdd */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300); - STPMU1_Regulator_Enable(STPMU1_BUCK3); + /* vdd */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300); + STPMU1_Regulator_Enable(STPMU1_BUCK3); - /* 3v3 */ - STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300); - STPMU1_Regulator_Enable(STPMU1_BUCK4); + /* 3v3 */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300); + STPMU1_Regulator_Enable(STPMU1_BUCK4); - /* vdda */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 2900); - STPMU1_Regulator_Enable(STPMU1_LDO1); + /* vdda */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 2900); + STPMU1_Regulator_Enable(STPMU1_LDO1); - /* 2v8 */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2800); - STPMU1_Regulator_Enable(STPMU1_LDO2); + /* 2v8 */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2800); + STPMU1_Regulator_Enable(STPMU1_LDO2); - /* vtt_ddr lod3 mode buck2/2 */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF); - STPMU1_Regulator_Enable(STPMU1_LDO3); + /* vtt_ddr lod3 mode buck2/2 */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF); + STPMU1_Regulator_Enable(STPMU1_LDO3); - /* vdd_usb */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300); - STPMU1_Regulator_Enable(STPMU1_LDO4); + /* vdd_usb */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300); + STPMU1_Regulator_Enable(STPMU1_LDO4); - /* vdd_sd */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900); - STPMU1_Regulator_Enable(STPMU1_LDO5); + /* vdd_sd */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900); + STPMU1_Regulator_Enable(STPMU1_LDO5); - /* 1v8 */ - STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 1800); - STPMU1_Regulator_Enable(STPMU1_LDO6); + /* 1v8 */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 1800); + STPMU1_Regulator_Enable(STPMU1_LDO6); - STPMU1_Regulator_Enable(STPMU1_VREFDDR); + STPMU1_Regulator_Enable(STPMU1_VREFDDR); return RT_EOK; } @@ -884,7 +886,7 @@ static int pmic_init(void) { BSP_PMIC_MspInit(); - result = rt_hw_pmic_init("i2c3"); + result = rt_hw_pmic_init(I2C_NAME); if(result != RT_EOK) { LOG_D("stpmic init failed: %02x", result); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c new file mode 100644 index 0000000000..3aac57603d --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu first version + */ + +#include "board.h" +//#define DRV_DEBUG +#define LOG_TAG "drv.pwr" +#include <drv_log.h> + +extern int lptim_start(void); +extern int lptim_stop(void); + +static RCC_ClkInitTypeDef RCC_ClkInit = {0}; + +#define __WAIT_EVENT_TIMEOUT(__CONDITION__, __TIMEOUT_VAL__) \ + do { \ + __IO uint32_t count = __TIMEOUT_VAL__ * (SystemCoreClock / 20U / 1000U); \ + do \ + { \ + if (count-- == 0U) \ + { \ + return HAL_TIMEOUT; \ + } \ + } \ + while (__CONDITION__ == 0U); \ + } while(0) + +/* Back up clock tree */ +static void backup_cm4_clocks(void) +{ + rt_uint32_t *pFLatency = NULL; + + /* Back up MCU clock configuration */ + HAL_RCC_GetClockConfig(&RCC_ClkInit, pFLatency); +} + +/* Restore the CM4 clock source muxer and the CM4 prescaler. */ +rt_err_t restore_cm4_clock(void) +{ + /* Update SystemCoreClock variable */ + SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq(); + + /* Enable PLL3 if needed */ + if (RCC_ClkInit.MCUInit.MCU_Clock == RCC_MCUSSOURCE_PLL3) + { + /* Enable PLL3 */ + __HAL_RCC_PLL3_ENABLE(); + + /* Wait till PLL3 is ready */ + __WAIT_EVENT_TIMEOUT(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY), CLOCKSWITCH_TIMEOUT_VALUE); + + /* Enable PLL3 outputs */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR); + } + + /* Configure MCU clock only */ + __HAL_RCC_MCU_SOURCE(RCC_ClkInit.MCUInit.MCU_Clock); + + /* Wait till MCU is ready */ + __WAIT_EVENT_TIMEOUT(__HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY), + CLOCKSWITCH_TIMEOUT_VALUE); + + /* Update SystemCoreClock variable */ + SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq(); + + /* Reconfigure Systick */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return RT_ERROR; + } + + /* Set MCU division factor */ + __HAL_RCC_MCU_DIV(RCC_ClkInit.MCUInit.MCU_Div); + + /* Wait till MCUDIV is ready */ + __WAIT_EVENT_TIMEOUT(__HAL_RCC_GET_FLAG(RCC_FLAG_MCUDIVRDY), + CLOCKSWITCH_TIMEOUT_VALUE); + + /* Update SystemCoreClock variable */ + SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq(); + + /* Reconfigure Systick */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return RT_ERROR; + } + + return RT_EOK; +} + +void RCC_WAKEUP_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_RCC_WAKEUP_IRQHandler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_RCC_WAKEUP_Callback() +{ + if (__HAL_PWR_GET_FLAG(PWR_FLAG_STOP) == 1U) + { + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_STOP); + } + + restore_cm4_clock(); + /* All level of ITs can interrupt */ + __set_BASEPRI(0U); + + rt_kprintf("system exit stop mode success!\n"); +} + +static void enter_sleep_mode(void) +{ + __set_BASEPRI((1) << (8 - __NVIC_PRIO_BITS)); + + lptim_start(); + + HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); +} + +static void enter_stop_mode(void) +{ + /* + * Only the IT with the highest priority (0 value) can interrupt. + * RCC_WAKEUP_IRQn IT is intended to have the highest priority and to be the + * only one IT having this value + * RCC_WAKEUP_IRQn is generated only when RCC is completely resumed from + * CSTOP (protection mechanism) + */ + __set_BASEPRI((1) << (8 - __NVIC_PRIO_BITS)); + + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_STOP); + backup_cm4_clocks(); + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); +} + +static void pm_wackup_key_init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + __HAL_RCC_GPIOA_CLK_ENABLE(); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + HAL_NVIC_SetPriority(EXTI13_IRQn, 0x01, 0); + HAL_NVIC_EnableIRQ(EXTI13_IRQn); +} + +int drv_pm_hw_init(void) +{ + pm_wackup_key_init(); + + return RT_EOK; +} +INIT_BOARD_EXPORT(drv_pm_hw_init); + +static int pwr_sample(int argc, char *argv[]) +{ + if (argc > 1) + { + if (!rt_strcmp(argv[1], "stop")) + { + rt_kprintf("system will enter stop mode! you can press USER2 button to exit this mode\n"); + enter_stop_mode(); + return RT_EOK; + + } + else if (!rt_strcmp(argv[1], "sleep")) + { + rt_kprintf("system will enter sleep mode! lptim1 will wake up the system\n"); + enter_sleep_mode(); + return RT_EOK; + } + else + { + goto _exit; + } + } +_exit: + { + rt_kprintf("Usage:\n"); + rt_kprintf("pwr_sample stop - system enter stop mode\n"); + rt_kprintf("pwr_sample sleep - system enter sleep mode\n"); + } + + return -RT_ERROR; +} +MSH_CMD_EXPORT(pwr_sample, enter low power mode sample); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c new file mode 100644 index 0000000000..70fa977359 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-07 thread-liu first version + */ + +#include <board.h> +#include <drv_qspi.h> +#include <rtdevice.h> +#include <rthw.h> +#include <finsh.h> + +#ifdef BSP_USING_QSPI_FLASH + +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +/** +* @brief QSPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ +void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspInit 0 */ + if (IS_ENGINEERING_BOOT_MODE()) + { + PeriphClkInit.Sdmmc12ClockSelection = RCC_QSPICLKSOURCE_ACLK; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_QSPI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* USER CODE END QUADSPI_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_QSPI_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**QUADSPI GPIO Configuration + PF6 ------> QUADSPI_BK1_IO3 + PF7 ------> QUADSPI_BK1_IO2 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + PF10 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /**QUADSPI GPIO Configuration + PC0 ------> QUADSPI_BK2_NCS + PH3 ------> QUADSPI_BK2_IO1 + PG7 ------> QUADSPI_BK2_IO3 + PG10 ------> QUADSPI_BK2_IO2 + PH2 ------> QUADSPI_BK2_IO0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF11_QUADSPI; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USER CODE BEGIN QUADSPI_MspInit 1 */ + + /* USER CODE END QUADSPI_MspInit 1 */ + } +} + +/** +* @brief QSPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) +{ + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + + /* USER CODE END QUADSPI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_QSPI_CLK_DISABLE(); + + /**QUADSPI GPIO Configuration + PC0 ------> QUADSPI_BK2_NCS + PF10 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + PH3 ------> QUADSPI_BK2_IO1 + PG7 ------> QUADSPI_BK2_IO3 + PG10 ------> QUADSPI_BK2_IO2 + PF7 ------> QUADSPI_BK1_IO2 + PF6 ------> QUADSPI_BK1_IO3 + PH2 ------> QUADSPI_BK2_IO0 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_3|GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7|GPIO_PIN_10); + + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + + /* USER CODE END QUADSPI_MspDeInit 1 */ + } + +} + +static int rt_hw_qspi_flash_with_sfud_init(void) +{ + stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, RT_NULL, RT_NULL); + /* init MX25L51245G */ + if (RT_NULL == rt_sfud_flash_probe("MX25L51245G", "qspi10")) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_qspi_flash_with_sfud_init); + +#endif /* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c new file mode 100644 index 0000000000..44eba3be91 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-24 thread-liu first version + */ + +#include <board.h> +#include "drv_rs485.h" + +#ifdef BSP_USING_RS485 + +#define RS485_OUT rt_pin_write(BSP_RS485_RTS_PIN, PIN_HIGH) +#define RS485_IN rt_pin_write(BSP_RS485_RTS_PIN, PIN_LOW) + +static rt_device_t serial = {0}; +static struct rt_semaphore rx_sem = {0}; + +/* uart send data callback function */ +static rt_err_t rs485_output(rt_device_t dev, void * buffer) +{ + return RT_EOK; +} + +/* uart receive data callback function */ +static rt_err_t rs485_input(rt_device_t dev, rt_size_t size) +{ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +/* send string */ +int rs485_send_data(char *tbuf, rt_uint16_t t_len) +{ + /* change rs485 mode */ + RS485_OUT; + + /* send data */ + rt_device_write(serial, 0, tbuf, t_len); + + /* change rs485 mode */ + RS485_IN; + + return RT_EOK; +} + +static void rs485_thread_entry(void *parameter) +{ + char ch; + + while (1) + { + /* A byte of data is read from a serial port, and if it is not read, it waits for the received semaphore */ + while (rt_device_read(serial, -1, &ch, 1) != 1) + { + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + + /* The data read through the serial port output dislocation */ + ch = ch + 1; + + /* send char */ + rs485_send_data(&ch, 1); + } +} + +/* rs485 rts pin init */ +static int rs485_init(void) +{ + /* find uart device */ + serial = rt_device_find(RS485_UART_DEVICE_NAME); + if (!serial) + { + rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME); + return RT_ERROR; + } + + rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); + + /* set receive data callback function */ + rt_device_set_rx_indicate(serial, rs485_input); + + /* set the send completion callback function */ + rt_device_set_tx_complete(serial, rs485_output); + + rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT); + + RS485_IN; + + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + /* create rs485 thread */ + rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10); + + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + return RT_ERROR; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rs485_init); + +#endif /* bsp_using_RS485 */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h new file mode 100644 index 0000000000..01edf84ae8 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-24 thread-liu first version + */ + +#ifndef __DRV_RS485_H__ +#define __DRV_RS485_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RS485_SEND_MODE 0 +#define RS485_RECV_MODE 1 + +#ifdef __cplusplus +} +#endif + +#endif /* drv_rs485.h */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c new file mode 100644 index 0000000000..3ef28f4e85 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-04 thread-liu the first version + */ + +#include "board.h" + +#if defined(BSP_USING_SDCARD) +#include <dfs_fs.h> + +#define DRV_DEBUG +//#define SDMMC_TX_DUMP +//#define SDMMC_RX_DUMP +#define LOG_TAG "drv.sdmmc" +#include <drv_log.h> + +static SD_HandleTypeDef SDCARD_Handler = {0}; +static HAL_SD_CardInfoTypeDef SDCardInfo = {0}; + +struct stm32_sd +{ + struct rt_device sdcard; + struct rt_semaphore sd_lock; + volatile rt_uint8_t write_flage; + volatile rt_uint8_t read_flage; + volatile rt_base_t level; +}; +static struct stm32_sd sd_device; + +#define SD_TIMEOUT ((uint32_t)30 * 1000) +#define DETECT_PIN GET_PIN(G, 1) +#define LDO_PIN GET_PIN(F, 14) + +struct rt_completion tx_comp; +struct rt_completion rx_comp; + +/* SYSRAM SDMMC1/2 accesses */ +#define SDIO_BUFF_SIZE 512 +#define SDCARD_ADDR 0x2FFC0000 +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(SDCARD_ADDR))) static rt_uint32_t cache_buf[SDIO_BUFF_SIZE]; +#elif defined ( __GNUC__ ) +static rt_uint32_t cache_buf[SDIO_BUFF_SIZE] __attribute__((section(".SdCardSection"))); +#elif defined(__ICCARM__) +#pragma location = SDCARD_ADDR +__no_init static rt_uint32_t cache_buf[SDIO_BUFF_SIZE]; +#endif + +#if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%02X ", buf[i + j]); + else + rt_kprintf(" "); + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + rt_kprintf("\n"); + } +} +#endif + +static rt_err_t rt_hw_sd_is_detected(void) +{ + return rt_pin_read(DETECT_PIN); +} + +static rt_err_t rt_hw_sd_init(void) +{ + /* sd ldo*/ + rt_pin_mode(LDO_PIN, PIN_MODE_OUTPUT); + /* sd detect */ + rt_pin_mode(DETECT_PIN, PIN_MODE_INPUT_PULLUP); + /* judge we have a sd card */ + if (rt_hw_sd_is_detected() != 0x00) + { + LOG_E("can't find sd card!"); + return RT_ERROR; + } + + SDCARD_Handler.Instance = SDMMC1; + HAL_SD_DeInit(&SDCARD_Handler); + + /* if CLKDIV = 0 then SDMMC Clock frequency = SDMMC Kernel Clock + else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV]. + SDMMC Kernel Clock = 99MHz, SDMMC Clock frequency = 50MHz */ + + SDCARD_Handler.Init.ClockDiv = 1; + SDCARD_Handler.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + SDCARD_Handler.Init.ClockEdge = SDMMC_CLOCK_EDGE_FALLING; + SDCARD_Handler.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + SDCARD_Handler.Init.BusWide = SDMMC_BUS_WIDE_4B; + + if (HAL_SD_Init(&SDCARD_Handler) != RT_EOK) + { + LOG_E("sd device init error!"); + return RT_ERROR; + } + + if (HAL_SD_ConfigWideBusOperation(&SDCARD_Handler, SDMMC_BUS_WIDE_4B) != RT_EOK) + { + LOG_E("sd bus config error!"); + return RT_ERROR; + } + + if (HAL_SD_GetCardInfo(&SDCARD_Handler, &SDCardInfo) != RT_EOK) + { + LOG_E("sd get card info error!"); + return RT_ERROR; + } + + rt_thread_mdelay(100); + + if(HAL_SD_GetCardState(&SDCARD_Handler) != HAL_SD_CARD_TRANSFER) + { + LOG_E("sd get card state error!"); + return RT_ERROR; + } + + return RT_EOK; +} + +static void rt_hw_sd_deinit(void) +{ + HAL_SD_DeInit(&SDCARD_Handler); +} + +static rt_err_t sdcard_wait_ok(void) +{ + rt_uint32_t tick_start = 0; + + tick_start = rt_tick_get(); + while ((rt_tick_get() - tick_start) < SD_TIMEOUT) + { + if (HAL_SD_GetCardState(&SDCARD_Handler) == HAL_SD_CARD_TRANSFER) + { + return HAL_OK; + } + } + return HAL_ERROR; +} + +void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) +{ + if (status == SET) + { + rt_pin_write(LDO_PIN, PIN_HIGH); + } + else + { + rt_pin_write(LDO_PIN, PIN_LOW); + } +} + +static rt_err_t rt_sdcard_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_sd *sd = (struct stm32_sd *)dev; + + if (rt_sem_init(&sd->sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK) + { + LOG_E("init sd lock semaphore failed\n"); + } + + return RT_EOK; +} + +static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + return RT_EOK; +} + +static rt_err_t rt_sdcard_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + return RT_EOK; +} + +/** + * @brief Reads Sector(s) + * @param dev : sd dev + * @param sector: Sector address (LBA) Data buffer to store read data + * @param *buffer: Data buffer to store read data + * @param count: Number of sectors to read (1..128) + * @retval DRESULT: Operation result + */ + +static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer, rt_size_t count) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_sd *sd = (struct stm32_sd *)dev; + + rt_uint8_t ret = RT_EOK; + volatile uint32_t tickstart = 0; + sd->read_flage = 0; + + rt_memset(cache_buf, 0x00, BLOCKSIZE * count); + + ret = sdcard_wait_ok(); + if (ret != RT_EOK) + { + LOG_D("sdmmc busy!"); + return 0; + } + + rt_sem_take(&sd->sd_lock, RT_WAITING_FOREVER); + ret = HAL_SD_ReadBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (uint32_t)sector, count); + rt_sem_release(&sd->sd_lock); + + /* Wait that writing process is completed or a timeout occurs */ + tickstart = rt_tick_get(); + if (ret == HAL_OK) + { + while ((sd->read_flage == 0) && (rt_tick_get() - tickstart) < SD_TIMEOUT) + { + } + /* over time */ + if (sd->read_flage == 0) + { + return 0; + } + else + { + sd->read_flage = 0; + tickstart = rt_tick_get(); + while ((rt_tick_get() - tickstart) < SD_TIMEOUT) + { + if (sdcard_wait_ok() == RT_EOK) + { + sd->level=rt_hw_interrupt_disable(); + rt_memcpy((rt_uint8_t *)(buffer), cache_buf, BLOCKSIZE * count); + rt_hw_interrupt_enable(sd->level); +#if defined(SDMMC_RX_DUMP) + rt_kprintf("\nsd rx: \n"); + dump_hex(cache_buf, BLOCKSIZE * count); +#endif + return count; + } + } + } + } + + return 0; +} + +/** + * @brief Writes block(s) to a specified address in an SD card, in DMA mode. + * @param dev SD device + * @param sector Block index from where data is to be written P + * @param *buffer Pointer to the buffer that will contain the data to transmit + * @param count Number of SD blocks to write + * @retval BSP status + */ +static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t sector, const void *buffer, rt_size_t count) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_sd *sd = (struct stm32_sd *)dev; + rt_uint32_t i = 0; + rt_uint8_t ret = RT_EOK; + + for (i = 0; i < count; i++) + { + sd->level = rt_hw_interrupt_disable(); + rt_memset(cache_buf, 0x00, BLOCKSIZE); + rt_memcpy(cache_buf, (rt_uint32_t *)((uintptr_t)buffer + BLOCKSIZE * i), BLOCKSIZE); + rt_hw_interrupt_enable(sd->level); + +#if defined(SDMMC_TX_DUMP) + rt_kprintf("\nsd tx: \n"); + dump_hex(cache_buf, BLOCKSIZE); +#endif + ret = sdcard_wait_ok(); + if (ret != RT_EOK) + { + LOG_D("sdmmc busy!"); + return 0; + } + rt_completion_init(&tx_comp); + ret = HAL_SD_WriteBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (rt_uint32_t)(sector + i), 1); + if (ret != HAL_OK) + { + rt_kprintf("sd write error!\n"); + return 0; + } + rt_completion_wait(&tx_comp,RT_WAITING_FOREVER); + + } + + return count; +} + +static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) + { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + + geometry->bytes_per_sector = 512; + geometry->block_size = SDCARD_Handler.SdCard.BlockSize; + geometry->sector_count = SDCARD_Handler.SdCard.BlockNbr; + } + + return RT_EOK; +} + +void SDMMC1_IRQHandler(void) +{ + rt_interrupt_enter(); + + HAL_SD_IRQHandler(&SDCARD_Handler); + + rt_interrupt_leave(); +} + +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) +{ + if (hsd->Instance == SDCARD_Handler.Instance) + { + sd_device.read_flage = 1; + } +} + +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +{ + if (hsd->Instance == SDCARD_Handler.Instance) + { + rt_completion_done(&tx_comp); + } +} + +int rt_hw_sdcard_init(void) +{ + if (rt_hw_sd_init() != RT_EOK) + { + rt_hw_sd_deinit(); + LOG_E("sdcard init failed"); + + return RT_ERROR; + } + /* register sdcard device */ + sd_device.sdcard.type = RT_Device_Class_Block; + sd_device.sdcard.init = rt_sdcard_init; + sd_device.sdcard.open = rt_sdcard_open; + sd_device.sdcard.close = rt_sdcard_close; + sd_device.sdcard.read = rt_sdcard_read; + sd_device.sdcard.write = rt_sdcard_write; + sd_device.sdcard.control = rt_sdcard_control; + + /* no private */ + sd_device.sdcard.user_data = &SDCardInfo; + + rt_device_register(&sd_device.sdcard, "sd_card", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + LOG_I("sd card init success!"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_sdcard_init); + +#if defined(BSP_USING_SDCARD_FS) +int mnt_init(void) +{ + rt_device_t sd_dev = RT_NULL; + + LOG_I("init sd card file system."); +#if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP) + rt_thread_delay(3000); +#else + rt_thread_delay(RT_TICK_PER_SECOND); +#endif + sd_dev = rt_device_find("sd_card"); + if (sd_dev == RT_NULL) + { + LOG_E("can't find sd deivce name!"); + return RT_ERROR; + } + + if (dfs_mount("sd_card", "/", "elm", 0, 0) != 0) + { + rt_kprintf("file system mount failed!\n"); + } + else + { + rt_kprintf("file system mount success!\n"); + } + + return 0; +} +INIT_APP_EXPORT(mnt_init); +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c new file mode 100644 index 0000000000..14efc094e5 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-31 Zero-Free first implementation + * 2020-07-02 thread-liu Porting for STM32MP1 + */ + +#include "board.h" + +#ifdef BSP_USING_AUDIO +#include "drv_wm8994.h" +#include <dfs_posix.h> + +#define DRV_DEBUG +#define LOG_TAG "drv.sound" +#include <drv_log.h> + +#define SOUND_BUS_NAME "i2c2" + +#define TX_FIFO_SIZE (4096) +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__attribute__((at(0x2FFC2000))) static rt_uint8_t AUDIO_TX_FIFO[TX_FIFO_SIZE]; +#elif defined ( __GNUC__ ) +static rt_uint8_t AUDIO_TX_FIFO[TX_FIFO_SIZE] __attribute__((section(".AudioSection"))); +#elif defined(__ICCARM__) +#pragma location = 0x2FFC2000 +__no_init static rt_uint8_t AUDIO_TX_FIFO[TX_FIFO_SIZE]; +#endif + +struct sound_device +{ + struct rt_audio_device audio; + struct rt_audio_configure replay_config; + rt_device_t decoder; + rt_uint8_t *tx_fifo; + rt_uint8_t volume; +}; +static struct sound_device snd_dev = {0}; + +SAI_HandleTypeDef hsai_BlockA2 = {0}; +extern DMA_HandleTypeDef hdma_sai2_a; + +static void rt_hw_sai2a_init(void) +{ + hsai_BlockA2.Instance = SAI2_Block_A; + hsai_BlockA2.Init.Protocol = SAI_FREE_PROTOCOL; + hsai_BlockA2.Init.AudioMode = SAI_MODEMASTER_TX; + hsai_BlockA2.Init.DataSize = SAI_DATASIZE_16; + hsai_BlockA2.Init.FirstBit = SAI_FIRSTBIT_MSB; + hsai_BlockA2.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + hsai_BlockA2.Init.Synchro = SAI_ASYNCHRONOUS; + hsai_BlockA2.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + hsai_BlockA2.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + hsai_BlockA2.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF; + hsai_BlockA2.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_44K; + hsai_BlockA2.Init.SynchroExt = SAI_SYNCEXT_DISABLE; + hsai_BlockA2.Init.MonoStereoMode = SAI_STEREOMODE; + hsai_BlockA2.Init.CompandingMode = SAI_NOCOMPANDING; + hsai_BlockA2.Init.TriState = SAI_OUTPUT_NOTRELEASED; + hsai_BlockA2.Init.PdmInit.Activation = DISABLE; + hsai_BlockA2.Init.PdmInit.MicPairsNbr = 0; + hsai_BlockA2.Init.PdmInit.ClockEnable = SAI_PDM_CLOCK1_ENABLE; + + hsai_BlockA2.FrameInit.FrameLength = 64; + hsai_BlockA2.FrameInit.ActiveFrameLength = 32; + hsai_BlockA2.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + hsai_BlockA2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai_BlockA2.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + + hsai_BlockA2.SlotInit.FirstBitOffset = 0; + hsai_BlockA2.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE; + hsai_BlockA2.SlotInit.SlotNumber = 2; + hsai_BlockA2.SlotInit.SlotActive = (SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_2 | SAI_SLOTACTIVE_3); + + if(HAL_OK != HAL_SAI_Init(&hsai_BlockA2)) + { + Error_Handler(); + } + /* Enable SAI to generate clock used by audio driver */ + __HAL_SAI_ENABLE(&hsai_BlockA2); +} + +void DMA1_Stream0_IRQHandler(void) +{ + HAL_DMA_IRQHandler(&hdma_sai2_a); +} + +void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &hsai_BlockA2) + { + rt_audio_tx_complete(&snd_dev.audio); + } +} + +void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &hsai_BlockA2) + { + rt_audio_tx_complete(&snd_dev.audio); + } +} + +void SAIA_Frequency_Set(uint32_t frequency) +{ + /* Disable SAI peripheral to allow access to SAI internal registers */ + __HAL_SAI_DISABLE(&hsai_BlockA2); + /* Update the SAI audio frequency configuration */ + hsai_BlockA2.Init.AudioFrequency = frequency; + HAL_SAI_Init(&hsai_BlockA2); + /* Enable SAI peripheral to generate MCLK */ + __HAL_SAI_ENABLE(&hsai_BlockA2); +} + +void SAIA_Channels_Set(uint8_t channels) +{ + if (channels == 1) + { + hsai_BlockA2.Init.MonoStereoMode = SAI_MONOMODE; + } + else + { + hsai_BlockA2.Init.MonoStereoMode = SAI_STEREOMODE; + } + + __HAL_SAI_DISABLE(&hsai_BlockA2); + HAL_SAI_Init(&hsai_BlockA2); + __HAL_SAI_ENABLE(&hsai_BlockA2); +} + +/** + * RT-Thread Audio Device Driver Interface + */ +static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */ + { + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */ + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.samplerate = snd_dev->replay_config.samplerate; + caps->udata.config.channels = snd_dev->replay_config.channels; + caps->udata.config.samplebits = snd_dev->replay_config.samplebits; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = snd_dev->replay_config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = snd_dev->replay_config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = snd_dev->replay_config.samplebits; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_MIXER: /* report the Mixer Units */ + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + caps->udata.mask = AUDIO_MIXER_VOLUME; + break; + + case AUDIO_MIXER_VOLUME: + rt_device_control(snd_dev->decoder, GET_VOLUME, &(caps->udata.value)); + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + { + switch (caps->sub_type) + { + case AUDIO_MIXER_VOLUME: + { + rt_uint8_t volume = caps->udata.value; + + rt_device_control(snd_dev->decoder, SET_VOLUME, &volume); + + snd_dev->volume = volume; + + LOG_D("set volume %d", volume); + break; + } + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_OUTPUT: + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + /* set samplerate */ + SAIA_Frequency_Set(caps->udata.config.samplerate); + /* set channels */ + SAIA_Channels_Set(caps->udata.config.channels); + + /* save configs */ + snd_dev->replay_config.samplerate = caps->udata.config.samplerate; + snd_dev->replay_config.channels = caps->udata.config.channels; + snd_dev->replay_config.samplebits = caps->udata.config.samplebits; + LOG_D("set samplerate %d", snd_dev->replay_config.samplerate); + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + SAIA_Frequency_Set(caps->udata.config.samplerate); + snd_dev->replay_config.samplerate = caps->udata.config.samplerate; + LOG_D("set samplerate %d", snd_dev->replay_config.samplerate); + break; + } + + case AUDIO_DSP_CHANNELS: + { + SAIA_Channels_Set(caps->udata.config.channels); + snd_dev->replay_config.channels = caps->udata.config.channels; + LOG_D("set channels %d", snd_dev->replay_config.channels); + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + /* not support */ + snd_dev->replay_config.samplebits = caps->udata.config.samplebits; + break; + } + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + break; + } + + return result; +} + +static rt_err_t sound_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev; + rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + rt_hw_sai2a_init(); + + /* set default params */ + SAIA_Frequency_Set(snd_dev->replay_config.samplerate); + SAIA_Channels_Set(snd_dev->replay_config.channels); + + /* set audio play type */ + rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type); + /* open lowlevel audio device */ + rt_device_open(snd_dev->decoder, RT_DEVICE_OFLAG_WRONLY); + rt_device_init(snd_dev->decoder); + /* check device id */ + result = rt_device_control(snd_dev->decoder, GET_ID, RT_NULL); + if (result != RT_EOK) + { + LOG_E("can't find low level audio device!"); + return RT_ERROR; + } + + return result; +} + +static rt_err_t sound_start(struct rt_audio_device *audio, int stream) +{ + struct sound_device *snd_dev; + rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + if (stream == AUDIO_STREAM_REPLAY) + { + LOG_D("open sound device"); + + rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type); + rt_device_control(snd_dev->decoder, START_PLAY, RT_NULL); + + if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK) + { + return RT_ERROR; + } + } + + return RT_EOK; +} + +static rt_err_t sound_stop(struct rt_audio_device *audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + + if (stream == AUDIO_STREAM_REPLAY) + { + HAL_SAI_DMAStop(&hsai_BlockA2); + + LOG_D("close sound device"); + } + + return RT_EOK; +} + +static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + struct sound_device *device; + + RT_ASSERT(audio != RT_NULL); + device = (struct sound_device *)audio->parent.user_data; + + info->buffer = device->tx_fifo; + info->total_size = TX_FIFO_SIZE; + info->block_size = TX_FIFO_SIZE / 2; + info->block_count = 2; +} + +static struct rt_audio_ops snd_ops = +{ + .getcaps = sound_getcaps, + .configure = sound_configure, + .init = sound_init, + .start = sound_start, + .stop = sound_stop, + .transmit = RT_NULL, + .buffer_info = sound_buffer_info, +}; + +int rt_hw_sound_init(void) +{ + rt_err_t result = RT_EOK; + struct rt_device *device = RT_NULL; + + rt_memset(AUDIO_TX_FIFO, 0, TX_FIFO_SIZE); + snd_dev.tx_fifo = AUDIO_TX_FIFO; + + /* init default configuration */ + snd_dev.replay_config.samplerate = 44100; + snd_dev.replay_config.channels = 2; + snd_dev.replay_config.samplebits = 16; + snd_dev.volume = 55; + + /* find lowlevel decoder device*/ + snd_dev.decoder = rt_device_find("decoder"); + if (snd_dev.decoder == RT_NULL) + { + LOG_E("cant't find lowlevel decoder deivce!"); + return RT_ERROR; + } + + /* register sound device */ + snd_dev.audio.ops = &snd_ops; + result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev); + /* check sound device register success or not */ + if (result != RT_EOK) + { + device = &(snd_dev.audio.parent); + rt_device_unregister(device); + LOG_E("sound device init error!"); + return RT_ERROR; + } + + return RT_EOK; +} + +INIT_APP_EXPORT(rt_hw_sound_init); + + +struct RIFF_HEADER_DEF +{ + char riff_id[4]; // 'R','I','F','F' + uint32_t riff_size; + char riff_format[4]; // 'W','A','V','E' +}; + +struct WAVE_FORMAT_DEF +{ + uint16_t FormatTag; + uint16_t Channels; + uint32_t SamplesPerSec; + uint32_t AvgBytesPerSec; + uint16_t BlockAlign; + uint16_t BitsPerSample; +}; + +struct FMT_BLOCK_DEF +{ + char fmt_id[4]; // 'f','m','t',' ' + uint32_t fmt_size; + struct WAVE_FORMAT_DEF wav_format; +}; + +struct DATA_BLOCK_DEF +{ + char data_id[4]; // 'R','I','F','F' + uint32_t data_size; +}; + +struct wav_info +{ + struct RIFF_HEADER_DEF header; + struct FMT_BLOCK_DEF fmt_block; + struct DATA_BLOCK_DEF data_block; +}; + +int wavplay_sample(int argc, char **argv) +{ +#define BUFSZ 1024 +#define SOUND_DEVICE_NAME "sound0" +static rt_device_t sound_dev; + + int fd = -1; + uint8_t *buffer = NULL; + struct wav_info *info = NULL; + struct rt_audio_caps caps = {0}; + + if (argc != 2) + { + rt_kprintf("Usage:\n"); + rt_kprintf("wavplay_sample song.wav\n"); + return 0; + } + + fd = open(argv[1], O_WRONLY); + if (fd < 0) + { + rt_kprintf("open file failed!\n"); + goto __exit; + } + + buffer = rt_malloc(BUFSZ); + if (buffer == RT_NULL) + goto __exit; + + info = (struct wav_info *) rt_malloc(sizeof * info); + if (info == RT_NULL) + goto __exit; + + if (read(fd, &(info->header), sizeof(struct RIFF_HEADER_DEF)) <= 0) + goto __exit; + if (read(fd, &(info->fmt_block), sizeof(struct FMT_BLOCK_DEF)) <= 0) + goto __exit; + if (read(fd, &(info->data_block), sizeof(struct DATA_BLOCK_DEF)) <= 0) + goto __exit; + + rt_kprintf("wav information:\n"); + rt_kprintf("samplerate %d\n", info->fmt_block.wav_format.SamplesPerSec); + rt_kprintf("channel %d\n", info->fmt_block.wav_format.Channels); + + sound_dev = rt_device_find(SOUND_DEVICE_NAME); + + rt_device_open(sound_dev, RT_DEVICE_OFLAG_WRONLY); + + caps.main_type = AUDIO_TYPE_OUTPUT; + caps.sub_type = AUDIO_DSP_PARAM; + caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec; + caps.udata.config.channels = info->fmt_block.wav_format.Channels; + caps.udata.config.samplebits = 16; + rt_device_control(sound_dev, AUDIO_CTL_CONFIGURE, &caps); + + while (1) + { + int length; + + length = read(fd, buffer, BUFSZ); + + if (length <= 0) + break; + + rt_device_write(sound_dev, 0, buffer, length); + } + + rt_device_close(sound_dev); + +__exit: + + if (fd >= 0) + close(fd); + + if (buffer) + rt_free(buffer); + + if (info) + rt_free(info); + + return 0; +} + +MSH_CMD_EXPORT(wavplay_sample, play wav file); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c new file mode 100644 index 0000000000..6230b49a4f --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-28 thread-liu the first version + */ + +#include "board.h" + +#if defined(BSP_USING_SPDIFRX) +#include "drv_spdifrx.h" + +#define DRV_DEBUG +#define LOG_TAG "drv.spdifrx" +#include <drv_log.h> + +struct stm32_spdifrx +{ + struct rt_device dev; + SPDIFRX_HandleTypeDef spdifrx; + SAI_HandleTypeDef sai4; + volatile rt_uint8_t complate; +}; +static struct stm32_spdifrx rt_spdifrx = {0}; + +extern DMA_HandleTypeDef hdma_spdifrx_rx; +extern DMA_HandleTypeDef hdma_sai4_a; + +static void sai4a_init(SAI_HandleTypeDef* sai) +{ + sai->Instance = SAI4_Block_A; + sai->Init.Protocol = SAI_SPDIF_PROTOCOL; + sai->Init.AudioMode = SAI_MODEMASTER_TX; + sai->Init.Synchro = SAI_ASYNCHRONOUS; + sai->Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE; + sai->Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; + sai->Init.AudioFrequency = SAI_AUDIO_FREQUENCY_96K; + sai->Init.MonoStereoMode = SAI_STEREOMODE; + sai->Init.CompandingMode = SAI_NOCOMPANDING; + sai->Init.PdmInit.Activation = DISABLE; + sai->Init.PdmInit.MicPairsNbr = 0; + sai->Init.PdmInit.ClockEnable = SAI_PDM_CLOCK1_ENABLE; + sai->Init.DataSize = SAI_DATASIZE_24; + sai->Init.FirstBit = SAI_FIRSTBIT_MSB; + sai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + + sai->FrameInit.FrameLength = 64; + sai->FrameInit.ActiveFrameLength = 32; + sai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; + sai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + sai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; + + sai->SlotInit.FirstBitOffset = 0; + sai->SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE; + sai->SlotInit.SlotNumber = 4; + sai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; + + if (HAL_SAI_Init(sai) != HAL_OK) + { + Error_Handler(); + } +} + +void DMA1_Stream7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_spdifrx_rx); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA1_Stream2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_sai4_a); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) +{ + rt_spdifrx.complate = SET; +} + +static rt_err_t _init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev; + + device->spdifrx.Instance = SPDIFRX; + HAL_SPDIFRX_DeInit(&device->spdifrx); + + device->spdifrx.Init.InputSelection = SPDIFRX_INPUT_IN1; + device->spdifrx.Init.Retries = SPDIFRX_MAXRETRIES_15; + device->spdifrx.Init.WaitForActivity = SPDIFRX_WAITFORACTIVITY_ON; + device->spdifrx.Init.ChannelSelection = SPDIFRX_CHANNEL_A; + device->spdifrx.Init.DataFormat = SPDIFRX_DATAFORMAT_MSB; + device->spdifrx.Init.StereoMode = SPDIFRX_STEREOMODE_ENABLE; + device->spdifrx.Init.PreambleTypeMask = SPDIFRX_PREAMBLETYPEMASK_ON; + device->spdifrx.Init.ChannelStatusMask = SPDIFRX_CHANNELSTATUS_ON; + + if (HAL_SPDIFRX_Init(&device->spdifrx) != HAL_OK) + { + return RT_ERROR; + } + + sai4a_init(&device->sai4); + + rt_spdifrx.complate = RESET; + + return RT_EOK; +} + +static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t _close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_uint32_t tickstart = 0; + + RT_ASSERT(dev != RT_NULL); + struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev; + rt_err_t result = RT_EOK; + + result = HAL_SPDIFRX_ReceiveDataFlow_DMA(&device->spdifrx, (uint32_t *)buffer, size); + if (result != HAL_OK) + { + return 0; + } + + if(device->spdifrx.ErrorCode != HAL_SPDIFRX_ERROR_NONE) + { + return 0; + } + + tickstart = rt_tick_get(); + while (rt_spdifrx.complate == RESET) + { + if (rt_tick_get() - tickstart > 0xFFFF) + { + return 0; + } + } + + rt_spdifrx.complate = RESET; + + return size; +} + +static rt_size_t _write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev; + rt_err_t result = RT_EOK; + + result = HAL_SAI_Transmit_DMA(&device->sai4, (rt_uint8_t *)buffer, size); + if (result != HAL_OK) + { + return RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t _control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +int spdifrx_init(void) +{ + rt_spdifrx.dev.type = RT_Device_Class_Miscellaneous; + rt_spdifrx.dev.init = _init; + rt_spdifrx.dev.open = _open; + rt_spdifrx.dev.close = _close; + rt_spdifrx.dev.read = _read; + rt_spdifrx.dev.write = _write; + rt_spdifrx.dev.control = _control; + rt_spdifrx.dev.user_data = RT_NULL; + + rt_device_register(&rt_spdifrx.dev, "spdifrx", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + rt_device_init(&rt_spdifrx.dev); + + LOG_I("spdifrx init success!"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(spdifrx_init); + +#ifdef FINSH_USING_MSH +#include <finsh.h> + +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%02X ", buf[i + j]); + else + rt_kprintf(" "); + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + rt_kprintf("\n"); + } +} + +static int spdifrx_sample(int argc, char **argv) +{ + extern SAI_HandleTypeDef hsai_block4_a; + + if (argc != 1) + { + rt_kprintf("Usage:\n"); + rt_kprintf("spdifrx_sample\n"); + return -1; + } + + /* 16 bit Data Buffer for Transmission */ + static rt_uint16_t tx_buffer[64] = { + 0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C, 0x5D5E, 0x5F60, + 0x6162, 0x6364, 0x6566, 0x6768, 0x696A, 0x6B6C, 0x6D6E, 0x6F70, + 0x7172, 0x7374, 0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80, + 0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C, 0x8D8E, 0x8F90, + 0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C, 0x5D5E, 0x5F60, + 0x6162, 0x6364, 0x6566, 0x6768, 0x696A, 0x6B6C, 0x6D6E, 0x6F70, + 0x7172, 0x7374, 0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80, + 0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C, 0x8D8E, 0x8F90}; + + static rt_uint32_t *rx_buffer = NULL; + rt_uint8_t size = 64; + struct rt_device *dev = RT_NULL; + + dev = rt_device_find("spdifrx"); + if (dev == RT_NULL) + { + rt_kprintf("can't find spdifrx device!\n"); + } + + rt_device_open(dev, RT_DEVICE_OFLAG_RDWR); + + rt_kprintf("spdifrx test tx data : \n"); + dump_hex((rt_uint8_t *)tx_buffer, size); + + rx_buffer = (rt_uint32_t *)rt_malloc(size); + + rt_device_write(dev, 0, tx_buffer, size); + rt_device_read(dev, 0, rx_buffer, size); + + /* Compare the received data with the expected one */ + while (size--) + { + if (((rx_buffer[size] & 0x00ffff00) >> 8) != (tx_buffer[size])) + { + rt_kprintf("spdirex loopback mode test failed!\n"); + + return RT_ERROR; + } + } + + rt_kprintf("spdifrx rx : \n"); + dump_hex((rt_uint8_t *)rx_buffer, size); + + rt_kprintf("spdirex loopback mode test success!\n"); + + return RT_EOK; +} +MSH_CMD_EXPORT(spdifrx_sample, spdifrx loopback test); +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.h diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c new file mode 100644 index 0000000000..b162d76b0f --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c @@ -0,0 +1,782 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-02 thread-liu first version + */ + +#include "board.h" + +#if defined(BSP_USING_AUDIO) +#include <drv_wm8994.h> + +#define DRV_DEBUG +#define LOG_TAG "drv.wm8994" +#include <drv_log.h> + +#define CHIP_ADDRESS 0x1B /* wm8994 address */ +#define I2C_NAME "i2c2" + +struct wm8994_dev +{ + struct rt_device dev; + struct rt_i2c_bus_device *i2c_bus; + rt_uint16_t id; + rt_uint16_t type; +}; +static struct wm8994_dev rt_wm8994 = {0}; + +/* i2c read reg */ +static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint8_t len, rt_uint8_t *buf) +{ + struct rt_i2c_msg msg[2] = {0, 0}; + static rt_uint8_t i2c_reg[2] = {0, 0}; + + RT_ASSERT(bus != RT_NULL); + + i2c_reg[0] = ((uint16_t)(reg >> 8) & 0xFF); + i2c_reg[1] = ((uint16_t)(reg) & 0xFF); + + msg[0].addr = CHIP_ADDRESS; + msg[0].flags = RT_I2C_WR; + msg[0].buf = i2c_reg; + msg[0].len = 2; + + msg[1].addr = CHIP_ADDRESS; + msg[1].flags = RT_I2C_RD; + msg[1].len = len; + msg[1].buf = buf; + + if (rt_i2c_transfer(bus, msg, 2) == 2) + { + return RT_EOK; + } + + return RT_ERROR; +} + +/* i2c write reg */ +static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint16_t data) +{ + rt_uint8_t buf[4]; + struct rt_i2c_msg msgs; + + RT_ASSERT(bus != RT_NULL); + + buf[0] = ((uint16_t)(reg >> 8) & 0xFF); + buf[1] = ((uint16_t)(reg) & 0xFF); + + buf[2] = ((uint16_t)(data >> 8) & 0xFF); + buf[3] = ((uint16_t)(data) & 0xFF); + + msgs.addr = CHIP_ADDRESS; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = 4; + + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + + return RT_ERROR; +} + +static rt_err_t wm8994_set_output_mode(struct rt_i2c_bus_device *bus, rt_uint16_t mode) +{ + switch (mode & 0x000F) + { + case OUTPUT_DEVICE_SPEAKER: + /* Enable DAC1 (Left), Enable DAC1 (Right), + * Disable DAC2 (Left), Disable DAC2 (Right) */ + write_reg(bus, 0x0005, 0x0C0C); + + /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ + write_reg(bus, 0x0601, 0x0000); + + /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ + write_reg(bus, 0x0602, 0x0000); + + /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ + write_reg(bus, 0x0604, 0x0002); + + /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ + write_reg(bus, 0x0605, 0x0002); + break; + + case OUTPUT_DEVICE_HEADPHONE: + /* Disable DAC1 (Left), Disable DAC1 (Right), + Enable DAC2 (Left), Enable DAC2 (Right)*/ + write_reg(bus, 0x05, 0x0303); + + /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ + write_reg(bus, 0x0601, 0x01); + + /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ + write_reg(bus, 0x0602, 0x01); + + /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ + write_reg(bus, 0x0604, 0x00); + + /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ + write_reg(bus, 0x0605, 0x00); + break; + + case OUTPUT_DEVICE_BOTH: + default: + break; + } + + return RT_EOK; +} + +static rt_err_t wm8994_set_input_mode(struct rt_i2c_bus_device *bus, rt_uint16_t mode) +{ + switch (mode & 0x01F0) + { + case INPUT_DEVICE_DIGITAL_MICROPHONE_2: + /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right) + * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right) + * Enable Left ADC, Enable Right ADC */ + write_reg(bus, 0x04, 0x0C30); + + /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */ + write_reg(bus, 0x0450, 0x00DB); + + /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */ + write_reg(bus, 0x02, 0x6000); + + /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */ + write_reg(bus, 0x0608, 0x0002); + + /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */ + write_reg(bus, 0x0609, 0x0002); + + /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */ + write_reg(bus, 0x0700, 0x000E); + break; + + case INPUT_DEVICE_INPUT_LINE_1: + /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */ + write_reg(bus, 0x28, 0x0011); + + /* Disable mute on IN1L_TO_MIXINL and +30dB on IN1L PGA output */ + write_reg(bus, 0x29, 0x0035); + + /* Disable mute on IN1R_TO_MIXINL, Gain = +30dB */ + write_reg(bus, 0x2A, 0x0035); + + /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right) + * Enable Left ADC, Enable Right ADC */ + write_reg(bus, 0x04, 0x0303); + + /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */ + write_reg(bus, 0x0440, 0x00DB); + + /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */ + write_reg(bus, 0x02, 0x6350); + + /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */ + write_reg(bus, 0x0606, 0x0002); + + /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */ + write_reg(bus, 0x0607, 0x0002); + + /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */ + write_reg(bus, 0x0700, 0x000D); + break; + + case INPUT_DEVICE_DIGITAL_MICROPHONE_1: + /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right) + * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right) + * Enable Left ADC, Enable Right ADC */ + write_reg(bus, 0x04, 0x030C); + + /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */ + write_reg(bus, 0x0440, 0x00DB); + + /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */ + write_reg(bus, 0x02, 0x6350); + + /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */ + write_reg(bus, 0x0606, 0x0002); + + /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */ + write_reg(bus, 0x0607, 0x0002); + + /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */ + write_reg(bus, 0x0700, 0x000D); + break; + + case INPUT_DEVICE_DIGITAL_MIC1_MIC2: + /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right) + * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right) + * Enable Left ADC, Enable Right ADC */ + write_reg(bus, 0x04, 0x0F3C); + + /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */ + write_reg(bus, 0x0450, 0x00DB); + + /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */ + write_reg(bus, 0x0440, 0x00DB); + + /* Disable IN1L, IN1R, Enable IN2L, IN2R, Thermal sensor & shutdown */ + write_reg(bus, 0x02, 0x63A0); + + /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */ + write_reg(bus, 0x0606, 0x0002); + + /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */ + write_reg(bus, 0x0607, 0x0002); + + /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */ + write_reg(bus, 0x0608, 0x0002); + + /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */ + write_reg(bus, 0x0609, 0x0002); + + /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */ + write_reg(bus, 0x0700, 0x000D); + break; + + case INPUT_DEVICE_INPUT_LINE_2: + default: + /* Actually, no other input devices supported */ + break; + } + + return RT_EOK; +} + +static rt_err_t _wm8994_init(struct wm8994_dev *dev) +{ + RT_ASSERT(dev != RT_NULL); + + /* wm8994 Errata Work-Arounds */ + write_reg(dev->i2c_bus, 0x0102, 0x0003); + write_reg(dev->i2c_bus, 0x0817, 0x0000); + write_reg(dev->i2c_bus, 0x0102, 0x0000); + + /* Enable VMID soft start (fast), Start-up Bias Current Enabled */ + write_reg(dev->i2c_bus, 0x0039, 0x006C); + + /* Enable bias generator, Enable VMID */ + if ((dev->type & 0x01F0) != 0) + { + /* audio input */ + write_reg(dev->i2c_bus, 0x0001, 0x0013); + } + else + { + /* audio output */ + write_reg(dev->i2c_bus, 0x0001, 0x0003); + } + rt_thread_mdelay(50); + + if ((dev->type & 0x000F) != 0 ) + { + /* Path Configurations for output */ + wm8994_set_output_mode(dev->i2c_bus, dev->type); + } + if ((dev->type & 0x01F0) != 0 ) + { + /* Path Configurations for input */ + wm8994_set_input_mode(dev->i2c_bus, dev->type); + } + + if (dev->type & INPUT_DEVICE_DIGITAL_MIC1_MIC2) + { + /* AIF1 Word Length = 16-bits, AIF1 Format = DSP mode */ + write_reg(dev->i2c_bus, 0x0300, 0x4018); + } + else + { + /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */ + write_reg(dev->i2c_bus, 0x0300, 0x4010); + } + + /* slave mode */ + write_reg(dev->i2c_bus, 0x0302, 0x0000); + + /* Enable the DSP processing clock for AIF1, Enable the core clock */ + write_reg(dev->i2c_bus, 0x0208, 0x000A); + + /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */ + write_reg(dev->i2c_bus, 0x0200, 0x0001); + + /* Audio output selected */ + if ((dev->type & 0x000F) != 0 ) + { + if (dev->type & OUTPUT_DEVICE_HEADPHONE) + { + /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */ + write_reg(dev->i2c_bus, 0x2D, 0x0100); + + /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */ + write_reg(dev->i2c_bus, 0x2E, 0x0100); + + /* Startup sequence for Headphone */ + write_reg(dev->i2c_bus, 0x0110, 0x8100); + + rt_thread_mdelay(300); + + /* Soft un-Mute the AIF1 Timeslot 0 DAC1 path L&R */ + write_reg(dev->i2c_bus, 0x0420, 0x0000); + } + + /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */ + write_reg(dev->i2c_bus, 0x03, 0x0300); + + /* Left Speaker Mixer Volume = 0dB */ + write_reg(dev->i2c_bus, 0x22, 0x0000); + + /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/ + write_reg(dev->i2c_bus, 0x23, 0x0000); + + /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path, + Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */ + write_reg(dev->i2c_bus, 0x36, 0x0300); + + /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */ + write_reg(dev->i2c_bus, 0x01, 0x3003); + + /* Headphone/Speaker Enable */ + + if (dev->type & INPUT_DEVICE_DIGITAL_MIC1_MIC2) + { + /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslots 0 and 1 */ + write_reg(dev->i2c_bus, 0x51, 0x0205); + } + else + { + /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */ + write_reg(dev->i2c_bus, 0x51, 0x0005); + } + + /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */ + /* idem for Speaker */ + write_reg(dev->i2c_bus, 0x01, 0x3303); + + /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */ + write_reg(dev->i2c_bus, 0x60, 0x0022); + + /* Enable Charge Pump */ + write_reg(dev->i2c_bus, 0x4C, 0x9F25); + + /* Add Delay */ + rt_thread_mdelay(15); + + /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */ + write_reg(dev->i2c_bus, 0x2D, 0x0001); + + /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */ + write_reg(dev->i2c_bus, 0x2E, 0x0001); + + /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */ + /* idem for SPKOUTL and SPKOUTR */ + write_reg(dev->i2c_bus, 0x03, 0x0330); + + /* Enable DC Servo and trigger start-up mode on left and right channels */ + write_reg(dev->i2c_bus, 0x54, 0x0033); + + /* Add Delay */ + rt_thread_mdelay(200); + + /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */ + write_reg(dev->i2c_bus, 0x60, 0x00EE); + + /* Unmute DAC 1 (Left) */ + write_reg(dev->i2c_bus, 0x0610, 0x00C0); + + /* Unmute DAC 1 (Right) */ + write_reg(dev->i2c_bus, 0x0611, 0x00C0); + + /* Unmute the AIF1 Timeslot 0 DAC path */ + write_reg(dev->i2c_bus, 0x0420, 0x0000); + + /* Unmute DAC 2 (Left) */ + write_reg(dev->i2c_bus, 0x0612, 0x00C0); + + /* Unmute DAC 2 (Right) */ + write_reg(dev->i2c_bus, 0x0613, 0x00C0); + + /* Unmute the AIF1 Timeslot 1 DAC2 path */ + write_reg(dev->i2c_bus, 0x0422, 0x0000); + + } + + /* Audio input selected */ + if ((dev->type & 0x01F0) != 0 ) + { + if ((dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_2)) + { + /* Enable Microphone bias 1 generator, Enable VMID */ + write_reg(dev->i2c_bus, 0x01, 0x0013); + + /* ADC oversample enable */ + write_reg(dev->i2c_bus, 0x0620, 0x0002); + + /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */ + write_reg(dev->i2c_bus, 0x0411, 0x3800); + } + else if (dev->type & INPUT_DEVICE_DIGITAL_MIC1_MIC2) + { + /* Enable Microphone bias 1 generator, Enable VMID */ + write_reg(dev->i2c_bus, 0x01, 0x0013); + + /* ADC oversample enable */ + write_reg(dev->i2c_bus, 0x0620, 0x0002); + + /* AIF ADC1 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */ + write_reg(dev->i2c_bus, 0x0410, 0x1800); + + /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */ + write_reg(dev->i2c_bus, 0x0411, 0x1800); + } + else if ((dev->type & INPUT_DEVICE_INPUT_LINE_1) || (dev->type & INPUT_DEVICE_INPUT_LINE_2)) + { + + /* Disable mute on IN1L, IN1L Volume = +0dB */ + write_reg(dev->i2c_bus, 0x18, 0x000B); + + /* Disable mute on IN1R, IN1R Volume = +0dB */ + write_reg(dev->i2c_bus, 0x1A, 0x000B); + + /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */ + write_reg(dev->i2c_bus, 0x0410, 0x1800); + } + } + + /* Return communication control value */ + return RT_EOK; + +} + +static rt_err_t _read_id(struct rt_i2c_bus_device *bus, rt_uint16_t *id) +{ + rt_uint8_t read_value[2]; + + read_reg(bus, 0x0000, 2, read_value); + *id = ((uint16_t)(read_value[0] << 8) & 0xFF00); + *id |= ((uint16_t)(read_value[1])& 0x00FF); + + if (*id != WM8994_ID) + { + LOG_E("error id: 0x%04x", *id); + return RT_ERROR; + } + + LOG_I("wm8994 init success, id: %04x", *id); + + return RT_EOK; +} + +static rt_err_t _set_mute(struct rt_i2c_bus_device *bus, uint32_t cmd) +{ + /* Set the Mute mode */ + if (cmd == AUDIO_MUTE_ON) + { + /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */ + write_reg(bus, 0x420, 0x0200); + + /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */ + write_reg(bus, 0x422, 0x0200); + } + else /* AUDIO_MUTE_OFF Disable the Mute */ + { + /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */ + write_reg(bus, 0x420, 0x0010); + + /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */ + write_reg(bus, 0x422, 0x0010); + } + + return RT_EOK; +} + +static rt_err_t _play(struct rt_i2c_bus_device *bus) +{ + _set_mute(bus, AUDIO_MUTE_OFF); + + return RT_EOK; +} + +static rt_err_t _set_volume(struct rt_i2c_bus_device *bus, rt_uint16_t type, rt_uint8_t volume) +{ + rt_uint8_t convertedvol = VOLUME_CONVERT(volume); + + if (type & 0x000F) + { + /* Output volume */ + if(convertedvol > 0x3E) + { + /* Unmute audio codec */ + _set_mute(bus, AUDIO_MUTE_OFF); + + /* Left Headphone Volume */ + write_reg(bus, 0x1C, 0x3F | 0x140); + + /* Right Headphone Volume */ + write_reg(bus, 0x1D, 0x3F | 0x140); + + /* Left Speaker Volume */ + write_reg(bus, 0x26, 0x3F | 0x140); + + /* Right Speaker Volume */ + write_reg(bus, 0x27, 0x3F | 0x140); + } + else if (volume == 0) + { + /* Mute audio codec */ + _set_mute(bus, AUDIO_MUTE_ON); + } + else + { + /* Unmute audio codec */ + _set_mute(bus, AUDIO_MUTE_OFF); + + /* Left Headphone Volume */ + write_reg(bus, 0x1C, convertedvol | 0x140); + + /* Right Headphone Volume */ + write_reg(bus, 0x1D, convertedvol | 0x140); + + /* Left Speaker Volume */ + write_reg(bus, 0x26, convertedvol | 0x140); + + /* Right Speaker Volume */ + write_reg(bus, 0x27, convertedvol | 0x140); + } + } + /* Input volume */ + else + { + convertedvol = VOLUME_IN_CONVERT(volume); + + /* Left AIF1 ADC1 volume */ + write_reg(bus, 0x400, convertedvol | 0x100); + + /* Right AIF1 ADC1 volume */ + write_reg(bus, 0x401, convertedvol | 0x100); + + /* Left AIF1 ADC2 volume */ + write_reg(bus, 0x404, convertedvol | 0x100); + + /* Right AIF1 ADC2 volume */ + write_reg(bus, 0x405, convertedvol | 0x100); + } + + return RT_EOK; +} + +static rt_err_t _get_volume(struct rt_i2c_bus_device *bus, rt_uint32_t *value) +{ + rt_uint8_t read_value[2]; + + read_reg(bus, 0x001C, 2, read_value); + + *value = ((uint16_t)(read_value[0] << 8) & 0xFF00); + *value |= ((uint16_t)(read_value[1])& 0x00FF); + + return RT_EOK; +} + +static rt_err_t _set_frequency(struct rt_i2c_bus_device *bus, rt_uint32_t freq) +{ + switch (freq) + { + case AUDIO_FREQUENCY_8K: + write_reg(bus, 0x210, 0x0003); + break; + + case AUDIO_FREQUENCY_16K: + write_reg(bus, 0x210, 0x0033); + break; + + case AUDIO_FREQUENCY_32K: + write_reg(bus, 0x210, 0x0063); + break; + + case AUDIO_FREQUENCY_48K: + write_reg(bus, 0x210, 0x0083); + break; + + case AUDIO_FREQUENCY_96K: + write_reg(bus, 0x210, 0x00A3); + break; + + case AUDIO_FREQUENCY_11K: + write_reg(bus, 0x210, 0x0013); + break; + + case AUDIO_FREQUENCY_22K: + write_reg(bus, 0x210, 0x0043); + break; + + case AUDIO_FREQUENCY_44K: + write_reg(bus, 0x210, 0x0073); + break; + + default: + write_reg(bus, 0x210, 0x0083); + break; + } + + return RT_EOK; +} + +static rt_err_t _reset(struct rt_i2c_bus_device *bus) +{ + /* Reset Codec by writing in 0x0000 address register */ + write_reg(bus, 0x0000, 0x0000); + + return RT_EOK; +} + +static rt_err_t rt_wm8994_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + rt_err_t result = RT_EOK; + static rt_uint16_t old_type = DEVICE_NONE; + + struct wm8994_dev *device = (struct wm8994_dev *)dev; + + if (old_type == device->type) + { + return RT_EOK; + } + + old_type = device->type; + + device->i2c_bus = rt_i2c_bus_device_find(I2C_NAME); + if (device->i2c_bus == RT_NULL) + { + LOG_E("can't find %c deivce", I2C_NAME); + return RT_ERROR; + } + + result = _wm8994_init(device); + /* set volume */ + _set_volume(device->i2c_bus, device->type, VOLUME_CONVERT(100)); + /* set frequency */ + _set_frequency(device->i2c_bus, AUDIO_FREQUENCY_44K); + + return result; +} + +static rt_err_t rt_wm8994_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_wm8994_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + struct wm8994_dev *device = (struct wm8994_dev *)dev; + + _set_mute(device->i2c_bus, AUDIO_MUTE_ON); + + /* Mute the AIF1 Timeslot 0 DAC1 path */ + write_reg(device->i2c_bus, 0x420, 0x0200); + /* Mute the AIF1 Timeslot 1 DAC2 path */ + write_reg(device->i2c_bus, 0x422, 0x0200); + /* Disable DAC1L_TO_HPOUT1L */ + write_reg(device->i2c_bus, 0x2D, 0x0000); + /* Disable DAC1R_TO_HPOUT1R */ + write_reg(device->i2c_bus, 0x2E, 0x0000); + /* Disable DAC1 and DAC2 */ + write_reg(device->i2c_bus, 0x05, 0x0000); + /* Reset Codec by writing in 0x0000 address register */ + write_reg(device->i2c_bus, 0x0000, 0x0000); + + return RT_EOK; +} + +static rt_size_t rt_wm8994_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_wm8994_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_wm8994_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + struct wm8994_dev *device = (struct wm8994_dev *)dev; + rt_err_t result = RT_EOK; + switch (cmd) + { + case GET_ID: + result = _read_id(device->i2c_bus, (rt_uint16_t*)args); + break; + + case SET_FREQUENCE: + result = _set_frequency(device->i2c_bus, (*(rt_uint32_t *)args)); + break; + + case SET_VOLUME: + result = _set_volume(device->i2c_bus, device->type, (*(rt_uint8_t*)args)); + break; + + case GET_VOLUME: + result = _get_volume(device->i2c_bus, (rt_uint32_t *)args); + break; + + case SET_MUTE: + result = _set_mute(device->i2c_bus, (*(rt_uint32_t*)args)); + break; + + case SET_RESET: + result = _reset(device->i2c_bus); + break; + + case START_PLAY: + result = _play(device->i2c_bus); + break; + + case SET_PLAY_TYPE: + device->type = 0; + device->type = *(rt_uint32_t *)args; + rt_wm8994_init(dev); + break; + + default: + LOG_D("not support cmd"); + break; + } + + return result; +} + +int wm8994_init(void) +{ + rt_wm8994.dev.type = RT_Device_Class_Sound; + rt_wm8994.dev.init = rt_wm8994_init; + rt_wm8994.dev.open = rt_wm8994_open; + rt_wm8994.dev.close = rt_wm8994_close; + rt_wm8994.dev.read = rt_wm8994_read; + rt_wm8994.dev.write = rt_wm8994_write; + rt_wm8994.dev.control = rt_wm8994_control; + rt_wm8994.dev.user_data = RT_NULL; + + rt_device_register(&rt_wm8994.dev, "decoder", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + LOG_I("lowlevel decoder device init success!"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(wm8994_init); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h new file mode 100644 index 0000000000..872e02b162 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-02 thread-liu first version + */ + +#ifndef __DRV_WM8994_H__ +#define __DRV_WM8994_H__ + +#include "board.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum{ + GET_ID, + SET_FREQUENCE, + SET_VOLUME, + GET_VOLUME, + SET_MUTE, + SET_RESET, + START_PLAY, + SET_PLAY_TYPE, +}; + +/* codec device play type */ +#define DEVICE_NONE ((uint16_t)0x0000) +#define OUTPUT_DEVICE_SPEAKER ((uint16_t)0x0001) +#define OUTPUT_DEVICE_HEADPHONE ((uint16_t)0x0002) +#define OUTPUT_DEVICE_BOTH ((uint16_t)0x0004) +#define OUTPUT_DEVICE_AUTO ((uint16_t)0x0008) +#define INPUT_DEVICE_DIGITAL_MICROPHONE_1 ((uint16_t)0x0010) +#define INPUT_DEVICE_DIGITAL_MICROPHONE_2 ((uint16_t)0x0020) +#define INPUT_DEVICE_INPUT_LINE_1 ((uint16_t)0x0040) +#define INPUT_DEVICE_INPUT_LINE_2 ((uint16_t)0x0080) +#define INPUT_DEVICE_DIGITAL_MIC1_MIC2 ((uint16_t)0x0100) + +/* volume levels values */ +#define DEFAULT_VOLMIN 0x00 +#define DEFAULT_VOLMAX 0xFF +#define DEFAULT_VOLSTEP 0x04 + +#define AUDIO_PAUSE 0 +#define AUDIO_RESUME 1 + +/* Codec POWER DOWN modes */ +#define CODEC_PDWN_HW 1 +#define CODEC_PDWN_SW 2 + +/* MUTE commands */ +#define AUDIO_MUTE_ON 1 +#define AUDIO_MUTE_OFF 0 + +/* AUDIO FREQUENCY */ +#define AUDIO_FREQUENCY_192K ((uint32_t)192000) +#define AUDIO_FREQUENCY_96K ((uint32_t)96000) +#define AUDIO_FREQUENCY_48K ((uint32_t)48000) +#define AUDIO_FREQUENCY_44K ((uint32_t)44100) +#define AUDIO_FREQUENCY_32K ((uint32_t)32000) +#define AUDIO_FREQUENCY_22K ((uint32_t)22050) +#define AUDIO_FREQUENCY_16K ((uint32_t)16000) +#define AUDIO_FREQUENCY_11K ((uint32_t)11025) +#define AUDIO_FREQUENCY_8K ((uint32_t)8000) + +#define VOLUME_CONVERT(Volume) (((Volume) > 100)? 100:((uint8_t)(((Volume) * 63) / 100))) +#define VOLUME_IN_CONVERT(Volume) (((Volume) >= 100)? 239:((uint8_t)(((Volume) * 240) / 100))) + +#define WM8994_ID 0x8994 +#define WM8994_CHIPID_ADDR 0x00 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c new file mode 100644 index 0000000000..4e9910aa95 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-18 thread-liu the first version + */ + +#include <board.h> + +#if defined(BSP_USING_WWDG) +#include "drv_config.h" +#include <string.h> +#include <stdlib.h> + +//#define DRV_DEBUG +#define LOG_TAG "drv.wwg" +#include <drv_log.h> + +#define LED5_PIN GET_PIN(A, 14) + +static rt_uint8_t feed_flag = 0; +static WWDG_HandleTypeDef hwwdg1; + +void WWDG1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_WWDG_IRQHandler(&hwwdg1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) +{ + if(hwwdg->Instance==WWDG1) + { + if (feed_flag) + { + HAL_WWDG_Refresh(&hwwdg1); + HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_14); + } + } +} + +static void wwdg_init() +{ + rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT); + + hwwdg1.Instance = WWDG1; + hwwdg1.Init.Prescaler = WWDG_PRESCALER_8; + hwwdg1.Init.Window = 0X5F; + hwwdg1.Init.Counter = 0x7F; + hwwdg1.Init.EWIMode = WWDG_EWI_ENABLE; + + if (HAL_WWDG_Init(&hwwdg1) != HAL_OK) + { + Error_Handler(); + } + + feed_flag = 1; +} + +static void wwdg_control(uint8_t pre_value) +{ + if(pre_value > 7) + { + pre_value = 7; + } + hwwdg1.Instance->CFR &= ~(7 << 11); /* clear WDGTB[2:0] */ + hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */ +} + +static void wwdg_stop(void) +{ + feed_flag = 0; +} + +static int wwdg_sample(int argc, char *argv[]) +{ + if (argc > 1) + { + if (!strcmp(argv[1], "run")) + { + wwdg_init(); + } + else if (!strcmp(argv[1], "set")) + { + if (argc > 2) + { + wwdg_control(atoi(argv[2])); + } + } + else if (!strcmp(argv[1], "stop")) + { + wwdg_stop(); + } + } + else + { + rt_kprintf("Usage:\n"); + rt_kprintf("wwdg_sample run - open wwdg, when feed wwdg in wwdg irq, the LD5 will blink\n"); + rt_kprintf("wwdg_sample stop - stop to feed wwdg, system will reset\n"); + rt_kprintf("wwdg_sample set - set the wwdg prescaler, wwdg_sample set [0 - 7]\n"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(wwdg_sample, window watch dog sample); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c new file mode 100644 index 0000000000..42aec448f8 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c @@ -0,0 +1,870 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-20 thread-liu the first version + */ + +#include "board.h" +#include "drv_config.h" +#include <netif/ethernetif.h> +#include "lwipopts.h" +#include "drv_eth.h" + +#if defined(BSP_USING_GBE) + +//#define DRV_DEBUG +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP +#define LOG_TAG "drv.emac" +#include <drv_log.h> + +#define MAX_ADDR_LEN 6 +rt_base_t level; + +#define TX_ADD_BASE 0x2FFC3000 +#define RX_ADD_BASE 0x2FFC5000 +#define TX_DMA_ADD_BASE 0x2FFC7000 +#define RX_DMA_ADD_BASE 0x2FFC7100 + +#if defined(__ICCARM__) +/* transmit buffer */ +#pragma location = TX_ADD_BASE +__no_init static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; +/* Receive buffer */ +#pragma location = RX_ADD_BASE +__no_init static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; +/* Transmit DMA descriptors */ +#pragma location = TX_DMA_ADD_BASE +__no_init static TxDmaDesc txDmaDesc[ETH_TXBUFNB]; +/* Receive DMA descriptors */ +#pragma location = RX_DMA_ADD_BASE +__no_init static RxDmaDesc rxDmaDesc[ETH_RXBUFNB]; + +#elif defined(__CC_ARM) || defined(__CLANG_ARM) +/* transmit buffer */ +static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(TX_ADD_BASE))); +/* Receive buffer */ +static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(RX_ADD_BASE))); +/* Transmit DMA descriptors */ +static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((at(TX_DMA_ADD_BASE))); +/* Receive DMA descriptors */ +static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((at(RX_DMA_ADD_BASE))); + +#elif defined ( __GNUC__ ) +/* transmit buffer */ +static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((section(".TxArraySection"))); +/* Receive buffer */ +static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((section(".RxArraySection"))); +/* Transmit DMA descriptors */ +static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((section(".TxDecripSection"))); +/* Receive DMA descriptors */ +static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((section(".RxDecripSection"))); +#endif + +//Current transmit descriptor +static rt_uint8_t txIndex = 0; +//Current receive descriptor +static rt_uint8_t rxIndex = 0; + +/* eth */ +static struct rt_event rx_event = {0}; + +#define ETH_TIME_OUT 100000 + +struct rt_stm32_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; +#ifndef PHY_USING_INTERRUPT_MODE + rt_timer_t poll_link_timer; +#endif + /* interface address info, hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + /* eth speed */ + uint32_t eth_speed; + /* eth duplex mode */ + uint32_t eth_mode; +}; +static struct rt_stm32_eth stm32_eth_device = {0}; + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%02X ", buf[i + j]); + else + rt_kprintf(" "); + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + rt_kprintf("\n"); + } +} +#endif + +static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_value) +{ + uint32_t temp; + volatile uint32_t tickstart = 0; + /* Take care not to alter MDC clock configuration */ + temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR; + /* Set up a write operation */ + temp |= ETH_MACMDIOAR_GOC_Val(1) | ETH_MACMDIOAR_GB; + /* PHY address */ + temp |= (phy_addr << 21) & ETH_MACMDIOAR_PA; + /* Register address */ + temp |= (reg_addr << 16) & ETH_MACMDIOAR_RDA; + + /* Data to be written in the PHY register */ + ETH->MACMDIODR = reg_value & ETH_MACMDIODR_GD; + + /* Start a write operation */ + ETH->MACMDIOAR = temp; + /* Wait for the write to complete */ + tickstart = rt_tick_get(); + while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0) + { + /* judge timeout */ + if((rt_tick_get() - tickstart) > ETH_TIME_OUT) + { + LOG_E("PHY write reg %02x date %04x timeout!", reg_addr, reg_value); + return RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr) +{ + uint16_t reg_value = 0; + uint32_t status = 0; + volatile uint32_t tickstart = 0; + + /* Take care not to alter MDC clock configuration */ + status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR; + /* Set up a read operation */ + status |= ETH_MACMDIOAR_GOC_Val(3) | ETH_MACMDIOAR_GB; + /* PHY address */ + status |= (phy_addr << 21) & ETH_MACMDIOAR_PA; + /* Register address */ + status |= (reg_addr << 16) & ETH_MACMDIOAR_RDA; + + /* Start a read operation */ + ETH->MACMDIOAR = status; + /* Wait for the read to complete */ + tickstart = rt_tick_get(); + while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0) + { + /* judge timeout */ + if((rt_tick_get() - tickstart) > ETH_TIME_OUT) + { + LOG_E("PHY read reg %02x timeout!", reg_addr); + return RT_ETIMEOUT; + } + } + + /* Get register value */ + reg_value = ETH->MACMDIODR & ETH_MACMDIODR_GD; + + return reg_value; +} + +static rt_err_t update_mac_mode(void) +{ + uint32_t status; + + /* Read current MAC configuration */ + status = ETH->MACCR; + + if (stm32_eth_device.eth_speed & PHY_1000M) + { + status &= ~ETH_MACCR_PS; + status &= ~ETH_MACCR_FES; + } + else if (stm32_eth_device.eth_speed & PHY_100M) + { + status |= ETH_MACCR_PS; + status |= ETH_MACCR_FES; + } + /* 10M */ + else + { + status |= ETH_MACCR_PS; + status &= ~ETH_MACCR_FES; + } + + if (stm32_eth_device.eth_mode & PHY_FULL_DUPLEX) + { + status |= ETH_MACCR_DM; + } + else + { + status &= ~ETH_MACCR_DM; + } + + /* Update MAC configuration register */ + ETH->MACCR = status; + + return RT_EOK; +} + +static void HAL_ETH_MspInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH; + PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable GPIO clocks */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /* Select RGMII interface mode */ + HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII); + + /* Enable Ethernet MAC clock */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + __HAL_RCC_ETH1TX_CLK_ENABLE(); + __HAL_RCC_ETH1RX_CLK_ENABLE(); + + /**ETH1 GPIO Configuration + PA1 ------> ETH1_RX_CLK + PA2 ------> ETH1_MDIO + PA7 ------> ETH1_RX_CTL + PB0 ------> ETH1_RXD2 + PB1 ------> ETH1_RXD3 + PB11 ------> ETH1_TX_CTL + PC1 ------> ETH1_MDC + PC2 ------> ETH1_TXD2 + PC4 ------> ETH1_RXD0 + PC5 ------> ETH1_RXD1 + PE2 ------> ETH1_TXD3 + PG4 ------> ETH1_GTX_CLK + PG5 ------> ETH1_CLK125 + PG13 ------> ETH1_TXD0 + PG14 ------> ETH1_TXD1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_11; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00); + HAL_NVIC_EnableIRQ(ETH1_IRQn); + + /* Configure PHY_RST (PD10) */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* Reset PHY transceiver */ + HAL_GPIO_WritePin(GPIOD, GPIO_PIN_10, GPIO_PIN_RESET); + rt_thread_mdelay(20); + HAL_GPIO_WritePin(GPIOD, GPIO_PIN_10, GPIO_PIN_SET); + rt_thread_mdelay(20); +} + +static rt_err_t rt_stm32_eth_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + rt_uint32_t status; + int i = 0 ; + volatile uint32_t tickstart = 0; + uint8_t *macAddr = &stm32_eth_device.dev_addr[0]; + + /* Initialize RX/TX descriptor index */ + rxIndex = txIndex = 0; + + HAL_ETH_MspInit(); + + /* Reset Ethernet MAC peripheral */ + __HAL_RCC_ETH1MAC_FORCE_RESET(); + __HAL_RCC_ETH1MAC_RELEASE_RESET(); + + /* Ethernet Software reset */ + ETH->DMAMR |= ETH_DMAMR_SWR; + /* Wait for the reset to complete */ + tickstart = rt_tick_get(); + while (READ_BIT(ETH->DMAMR, ETH_DMAMR_SWR)) + { + if(((HAL_GetTick() - tickstart ) > ETH_TIME_OUT)) + { + LOG_E("ETH software reset timeout!"); + return RT_ERROR; + } + } + + /* Adjust MDC clock range depending on HCLK frequency */ + ETH->MACMDIOAR = ETH_MACMDIOAR_CR_Val(5); + + /* Use default MAC configuration */ + ETH->MACCR = ETH_MACCR_DO; + + /* Set the MAC address of the station */ + ETH->MACA0LR = ((macAddr[3] << 24) | (macAddr[2] << 16) | (macAddr[1] << 8) | macAddr[0]); + ETH->MACA0HR = ((macAddr[5] << 8) | macAddr[4]); + + /* The MAC supports 3 additional addresses for unicast perfect filtering */ + ETH->MACA1LR = 0; + ETH->MACA1HR = 0; + ETH->MACA2LR = 0; + ETH->MACA2HR = 0; + ETH->MACA3LR = 0; + ETH->MACA3HR = 0; + + /* Initialize hash table */ + ETH->MACHT0R = 0; + ETH->MACHT1R = 0; + + /* Configure the receive filter */ + ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC; + + /* Disable flow control */ + ETH->MACQ0TXFCR = 0; + ETH->MACRXFCR = 0; + + /* Enable the first RX queue */ + ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1); + + /* Configure DMA operating mode */ + ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0); + + /* Configure system bus mode */ + ETH->DMASBMR |= ETH_DMASBMR_AAL; + + /* The DMA takes the descriptor table as contiguous */ + ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0); + + /* Configure TX features */ + ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1); + + /* Configure RX features */ + ETH->DMAC0RXCR = ETH_DMAC0RXCR_RXPBL_Val(1) | ETH_DMAC0RXCR_RBSZ_Val(ETH_RX_BUF_SIZE); + + /* Enable store and forward mode for transmission */ + ETH->MTLTXQ0OMR = ETH_MTLTXQ0OMR_TQS_Val(7) | ETH_MTLTXQ0OMR_TXQEN_Val(2) | ETH_MTLTXQ0OMR_TSF; + + /* Enable store and forward mode for reception */ + ETH->MTLRXQ0OMR = ETH_MTLRXQ0OMR_RQS_Val(7) | ETH_MTLRXQ0OMR_RSF; + + /* Initialize TX DMA descriptor list */ + for (i = 0; i < ETH_TXBUFNB; i++) + { + /* The descriptor is initially owned by the application */ + txDmaDesc[i].tdes0 = 0; + txDmaDesc[i].tdes1 = 0; + txDmaDesc[i].tdes2 = 0; + txDmaDesc[i].tdes3 = 0; + } + + /* Initialize RX DMA descriptor list */ + for (i = 0; i < ETH_RXBUFNB; i++) + { + /* The descriptor is initially owned by the DMA */ + rxDmaDesc[i].rdes0 = (uint32_t)rxBuffer[i]; + rxDmaDesc[i].rdes1 = 0; + rxDmaDesc[i].rdes2 = 0; + rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V; + } + + /* Set Transmit Descriptor List Address Register */ + ETH->DMAC0TXDLAR = (uint32_t)&txDmaDesc[0]; + /* Length of the transmit descriptor ring */ + ETH->DMAC0TXRLR = ETH_TXBUFNB - 1; + + /* Set Receive Descriptor List Address Register */ + ETH->DMAC0RXDLAR = (uint32_t)&rxDmaDesc[0]; + /* Length of the receive descriptor ring */ + ETH->DMAC0RXRLR = ETH_RXBUFNB - 1; + + /* Prevent interrupts from being generated when the transmit statistic + * counters reach half their maximum value */ + ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM; + + /* Prevent interrupts from being generated when the receive statistic + * counters reach half their maximum value */ + ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM; + + /* Disable MAC interrupts */ + ETH->MACIER = 0; + + /* Enable the desired DMA interrupts */ + ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; + + /* Enable MAC transmission and reception */ + ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE; + + /* Enable DMA transmission and reception */ + ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST; + ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR; + + /* Reset PHY transceiver */ + phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR, RTL8211E_BMCR_RESET); + status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR); + /* Wait for the reset to complete */ + tickstart = rt_tick_get(); + while (status & RTL8211E_BMCR_RESET) + { + if((rt_tick_get() - tickstart) > ETH_TIME_OUT) + { + LOG_E("PHY software reset timeout!"); + return RT_ETIMEOUT; + } + else + { + status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR); + } + } + + /* The PHY will generate interrupts when link status changes are detected */ + phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_INER, RTL8211E_INER_AN_COMPLETE | RTL8211E_INER_LINK_STATUS); + + return RT_EOK; +} + +static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("emac open"); + return RT_EOK; +} + +static rt_err_t rt_stm32_eth_close(rt_device_t dev) +{ + LOG_D("emac close"); + return RT_EOK; +} + +static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("emac read"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("emac write"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) + { + rt_memcpy(args, stm32_eth_device.dev_addr, 6); + } + else + { + return -RT_ERROR; + } + break; + + default : + break; + } + + return RT_EOK; +} + +rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) +{ + uint32_t framelen = 0; + struct pbuf *q = RT_NULL; + + /* Copy user data to the transmit buffer */ + for (q = p; q != NULL; q = q->next) + { + /* Make sure the current buffer is available for writing */ + if((txDmaDesc[txIndex].tdes3 & ETH_TDES3_OWN) != 0) + { + LOG_D("buffer not valid"); + return ERR_USE; + } + + level = rt_hw_interrupt_disable(); + rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len); + framelen += q->len; + rt_hw_interrupt_enable(level); + + /* Check the frame length */ + if (framelen > ETH_TX_BUF_SIZE - 1) + { + LOG_D(" tx buffer frame length over : %d", framelen); + return ERR_USE; + } + } + +#ifdef ETH_TX_DUMP + rt_kprintf("Tx dump, len= %d\r\n", framelen); + dump_hex(txBuffer[txIndex], framelen); +#endif + + /* Set the start address of the buffer */ + txDmaDesc[txIndex].tdes0 = (uint32_t)txBuffer[txIndex]; + /* Write the number of bytes to send */ + txDmaDesc[txIndex].tdes2 = ETH_TDES2_IOC | (framelen & ETH_TDES2_B1L); + /* Give the ownership of the descriptor to the DMA */ + txDmaDesc[txIndex].tdes3 = ETH_TDES3_OWN | ETH_TDES3_FD | ETH_TDES3_LD; + + /* Data synchronization barrier */ + __DSB(); + + /* Clear TBU flag to resume processing */ + ETH->DMAC0SR = ETH_DMAC0SR_TBU; + /* Instruct the DMA to poll the transmit descriptor list */ + ETH->DMAC0TXDTPR = 0; + + if (++txIndex > ETH_TXBUFNB - 1) + { + txIndex = 0; + } + + return ERR_OK; +} + +struct pbuf *rt_stm32_eth_rx(rt_device_t dev) +{ + rt_uint32_t framelength = 0; + uint32_t framelen = 0; + struct pbuf *p = RT_NULL, *q = RT_NULL; + + /* The current buffer is available for reading */ + if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) + { + /* FD and LD flags should be set */ + if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD)) + { + /* Make sure no error occurred */ + if(!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_ES)) + { + /* Retrieve the length of the frame */ + framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL; + /* check the frame length */ + framelength = (framelength > ETH_RX_BUF_SIZE) ? ETH_RX_BUF_SIZE : framelength; + p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM); + if (p != NULL) + { + for (q = p; q != NULL; q = q->next) + { + level=rt_hw_interrupt_disable(); + rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len); + framelen += q->len; + rt_hw_interrupt_enable(level); + + if (framelen > framelength) + { + LOG_E("frame len is too long!"); + return RT_NULL; + } + } + } + } + else + { + /* The received packet contains an error */ + LOG_D("the received packet contains an error!"); + return RT_NULL; + } + + } + else + { + /* The packet is not valid */ + LOG_D("the packet is not valid"); + return RT_NULL; + } + + /* Set the start address of the buffer */ + rxDmaDesc[rxIndex].rdes0 = (uint32_t)rxBuffer[rxIndex]; + /* Give the ownership of the descriptor back to the DMA */ + rxDmaDesc[rxIndex].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V; +#ifdef ETH_RX_DUMP + rt_kprintf("Rx dump, len= %d\r\n", framelen); + dump_hex(rxBuffer[rxIndex], framelen); +#endif + /* Increment index and wrap around if necessary */ + if (++rxIndex > ETH_RXBUFNB - 1) + { + rxIndex = 0; + } + /* Clear RBU flag to resume processing */ + ETH->DMAC0SR = ETH_DMAC0SR_RBU; + /* Instruct the DMA to poll the receive descriptor list */ + ETH->DMAC0RXDTPR = 0; + } + + return p; +} + +void ETH1_IRQHandler(void) +{ + rt_uint32_t status = 0; + + /* enter interrupt */ + rt_interrupt_enter(); + /* Read DMA status register */ + status = ETH->DMAC0SR; + /* Frame transmitted */ + if (status & ETH_DMAC0SR_TI) + { + /* Clear the Eth DMA Tx IT pending bits */ + ETH->DMAC0SR = ETH_DMAC0SR_TI; + } + /* Frame received */ + else if (status & ETH_DMAC0SR_RI) + { + /* Disable RIE interrupt */ + ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE; + + rt_event_send(&rx_event, status); + } + /* ETH DMA Error */ + if (status & ETH_DMAC0SR_AIS) + { + ETH->DMAC0IER &= ~ETH_DMAC0IER_AIE; + LOG_E("eth dam err"); + } + /* Clear the interrupt flags */ + ETH->DMAC0SR = ETH_DMAC0SR_NIS; + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void phy_linkchange() +{ + rt_uint32_t status = 0; + + /* Read status register to acknowledge the interrupt */ + status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_INSR); + + if (status & (RTL8211E_INSR_AN_COMPLETE | RTL8211E_INSR_LINK_STATUS)) + { + status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR); + status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR); + + if (status & RTL8211E_BMSR_LINK_STATUS) + { + LOG_D("link up"); + + status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_PHYSR); + + switch (status & RTL8211E_PHYSR_SPEED) + { + case RTL8211E_PHYSR_SPEED_10MBPS: + { + LOG_D("speed: 10M"); + stm32_eth_device.eth_speed |= PHY_10M; + break; + } + + case RTL8211E_PHYSR_SPEED_100MBPS: + { + LOG_D("speed: 100M"); + stm32_eth_device.eth_speed |= PHY_100M; + break; + } + + case RTL8211E_PHYSR_SPEED_1000MBPS: + { + LOG_D("speed: 1000M"); + stm32_eth_device.eth_speed |= PHY_1000M; + break; + } + + /* Unknown speed */ + default: + rt_kprintf("Invalid speed."); + break; + } + + stm32_eth_device.eth_mode = (status & RTL8211E_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX; + update_mac_mode(); + /* send link up. */ + eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); + } + else + { + LOG_D("link down"); + eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE); + } + } +} + +#ifdef PHY_USING_INTERRUPT_MODE +static void eth_phy_isr(void *args) +{ + rt_uint32_t status = 0; + + phy_read_reg(RTL8211E_PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status); + LOG_D("phy interrupt status reg is 0x%X", status); + + phy_linkchange(); +} +#endif /* PHY_USING_INTERRUPT_MODE */ + +static void phy_monitor_thread_entry(void *parameter) +{ + rt_uint32_t status = 0; + + phy_linkchange(); +#ifdef PHY_USING_INTERRUPT_MODE + /* configuration intterrupt pin */ + rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs"); + rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE); + + /* enable phy interrupt */ + phy_write_reg(RTL8211E_PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK); +#if defined(PHY_INTERRUPT_CTRL_REG) + phy_write_reg( RTL8211E_PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN); +#endif +#else /* PHY_USING_INTERRUPT_MODE */ + stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange, + NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); + if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK) + { + LOG_E("Start link change detection timer failed"); + } +#endif /* PHY_USING_INTERRUPT_MODE */ + while(1) + { + if (rt_event_recv(&rx_event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_FOREVER, &status) == RT_EOK) + { + /* check dma rx buffer */ + if (ETH->DMAC0SR & ETH_DMAC0SR_RI) + { + /* Clear interrupt flag */ + ETH->DMAC0SR = ETH_DMAC0SR_RI; + /* Process all pending packets */ + while (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL) + { + /* trigger lwip receive thread */ + eth_device_ready(&(stm32_eth_device.parent)); + } + } + + /* enable DMA interrupts */ + ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; + } + } +} + +/* Register the EMAC device */ +static int rt_hw_stm32_eth_init(void) +{ + rt_err_t state = RT_EOK; + + /* OUI 00-80-E1 STMICROELECTRONICS. */ + stm32_eth_device.dev_addr[0] = 0x00; + stm32_eth_device.dev_addr[1] = 0x80; + stm32_eth_device.dev_addr[2] = 0xE1; + /* generate MAC addr from 96bit unique ID. */ + stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4); + stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2); + stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0); + + stm32_eth_device.parent.parent.init = rt_stm32_eth_init; + stm32_eth_device.parent.parent.open = rt_stm32_eth_open; + stm32_eth_device.parent.parent.close = rt_stm32_eth_close; + stm32_eth_device.parent.parent.read = rt_stm32_eth_read; + stm32_eth_device.parent.parent.write = rt_stm32_eth_write; + stm32_eth_device.parent.parent.control = rt_stm32_eth_control; + stm32_eth_device.parent.parent.user_data = RT_NULL; + + stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; + stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; + + rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO); + + /* register eth device */ + state = eth_device_init(&(stm32_eth_device.parent), "e0"); + if (RT_EOK == state) + { + LOG_D("emac device init success"); + } + else + { + LOG_E("emac device init faild: %d", state); + state = -RT_ERROR; + } + + /* start phy monitor */ + rt_thread_t tid; + tid = rt_thread_create("phy", + phy_monitor_thread_entry, + RT_NULL, + 1024, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + state = -RT_ERROR; + } + + return state; +} +INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h new file mode 100644 index 0000000000..9529d778a0 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-20 thread-liu the first version + */ + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + +#include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> +#include <board.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Transmit descriptor + **/ +typedef struct +{ + uint32_t tdes0; + uint32_t tdes1; + uint32_t tdes2; + uint32_t tdes3; +} TxDmaDesc; + +/** + * @brief Receive descriptor + **/ +typedef struct +{ + uint32_t rdes0; + uint32_t rdes1; + uint32_t rdes2; + uint32_t rdes3; +} RxDmaDesc; + +enum { + PHY_LINK = (1 << 0), + PHY_10M = (1 << 1), + PHY_100M = (1 << 2), + PHY_1000M = (1 << 3), + PHY_FULL_DUPLEX = (1 << 4), + PHY_HALF_DUPLEX = (1 << 5) +}; + +#define RTL8211E_PHY_ADDR 7 /* PHY address */ + +#define ETH_TXBUFNB 4 /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +#define ETH_TX_BUF_SIZE 1536 /* buffer size for transmit */ +#define ETH_RXBUFNB 4 /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_RX_BUF_SIZE 1536 /* buffer size for receive */ + +#define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk /* ETH_MMCTXIMR register */ + +/* Register access macros */ +#define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk) +#define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk) +#define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk) +#define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk) +#define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk) +#define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk) +#define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk) +#define ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk) +#define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk) +#define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk) +#define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk) +#define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk) + +/* Transmit normal descriptor (read format) */ +#define ETH_TDES0_BUF1AP 0xFFFFFFFF +#define ETH_TDES1_BUF2AP 0xFFFFFFFF +#define ETH_TDES2_IOC 0x80000000 +#define ETH_TDES2_TTSE 0x40000000 +#define ETH_TDES2_B2L 0x3FFF0000 +#define ETH_TDES2_VTIR 0x0000C000 +#define ETH_TDES2_B1L 0x00003FFF +#define ETH_TDES3_OWN 0x80000000 +#define ETH_TDES3_CTXT 0x40000000 +#define ETH_TDES3_FD 0x20000000 +#define ETH_TDES3_LD 0x10000000 +#define ETH_TDES3_CPC 0x0C000000 +#define ETH_TDES3_SAIC 0x03800000 +#define ETH_TDES3_THL 0x00780000 +#define ETH_TDES3_TSE 0x00040000 +#define ETH_TDES3_CIC 0x00030000 +#define ETH_TDES3_FL 0x00007FFF + +/* Transmit normal descriptor (write-back format) */ +#define ETH_TDES0_TTSL 0xFFFFFFFF +#define ETH_TDES1_TTSH 0xFFFFFFFF +#define ETH_TDES3_OWN 0x80000000 +#define ETH_TDES3_CTXT 0x40000000 +#define ETH_TDES3_FD 0x20000000 +#define ETH_TDES3_LD 0x10000000 +#define ETH_TDES3_TTSS 0x00020000 +#define ETH_TDES3_ES 0x00008000 +#define ETH_TDES3_JT 0x00004000 +#define ETH_TDES3_FF 0x00002000 +#define ETH_TDES3_PCE 0x00001000 +#define ETH_TDES3_LOC 0x00000800 +#define ETH_TDES3_NC 0x00000400 +#define ETH_TDES3_LC 0x00000200 +#define ETH_TDES3_EC 0x00000100 +#define ETH_TDES3_CC 0x000000F0 +#define ETH_TDES3_ED 0x00000008 +#define ETH_TDES3_UF 0x00000004 +#define ETH_TDES3_DB 0x00000002 +#define ETH_TDES3_IHE 0x00000001 + +/* Transmit context descriptor */ +#define ETH_TDES0_TTSL 0xFFFFFFFF +#define ETH_TDES1_TTSH 0xFFFFFFFF +#define ETH_TDES2_IVT 0xFFFF0000 +#define ETH_TDES2_MSS 0x00003FFF +#define ETH_TDES3_OWN 0x80000000 +#define ETH_TDES3_CTXT 0x40000000 +#define ETH_TDES3_OSTC 0x08000000 +#define ETH_TDES3_TCMSSV 0x04000000 +#define ETH_TDES3_CDE 0x00800000 +#define ETH_TDES3_IVLTV 0x00020000 +#define ETH_TDES3_VLTV 0x00010000 +#define ETH_TDES3_VT 0x0000FFFF + +/* Receive normal descriptor (read format) */ +#define ETH_RDES0_BUF1AP 0xFFFFFFFF +#define ETH_RDES2_BUF2AP 0xFFFFFFFF +#define ETH_RDES3_OWN 0x80000000 +#define ETH_RDES3_IOC 0x40000000 +#define ETH_RDES3_BUF2V 0x02000000 +#define ETH_RDES3_BUF1V 0x01000000 + +/* Receive normal descriptor (write-back format) */ +#define ETH_RDES0_IVT 0xFFFF0000 +#define ETH_RDES0_OVT 0x0000FFFF +#define ETH_RDES1_OPC 0xFFFF0000 +#define ETH_RDES1_TD 0x00008000 +#define ETH_RDES1_TSA 0x00004000 +#define ETH_RDES1_PV 0x00002000 +#define ETH_RDES1_PFT 0x00001000 +#define ETH_RDES1_PMT 0x00000F00 +#define ETH_RDES1_IPCE 0x00000080 +#define ETH_RDES1_IPCB 0x00000040 +#define ETH_RDES1_IPV6 0x00000020 +#define ETH_RDES1_IPV4 0x00000010 +#define ETH_RDES1_IPHE 0x00000008 +#define ETH_RDES1_PT 0x00000007 +#define ETH_RDES2_L3L4FM 0xE0000000 +#define ETH_RDES2_L4FM 0x10000000 +#define ETH_RDES2_L3FM 0x08000000 +#define ETH_RDES2_MADRM 0x07F80000 +#define ETH_RDES2_HF 0x00040000 +#define ETH_RDES2_DAF 0x00020000 +#define ETH_RDES2_SAF 0x00010000 +#define ETH_RDES2_VF 0x00008000 +#define ETH_RDES2_ARPRN 0x00000400 +#define ETH_RDES3_OWN 0x80000000 +#define ETH_RDES3_CTXT 0x40000000 +#define ETH_RDES3_FD 0x20000000 +#define ETH_RDES3_LD 0x10000000 +#define ETH_RDES3_RS2V 0x08000000 +#define ETH_RDES3_RS1V 0x04000000 +#define ETH_RDES3_RS0V 0x02000000 +#define ETH_RDES3_CE 0x01000000 +#define ETH_RDES3_GP 0x00800000 +#define ETH_RDES3_RWT 0x00400000 +#define ETH_RDES3_OE 0x00200000 +#define ETH_RDES3_RE 0x00100000 +#define ETH_RDES3_DE 0x00080000 +#define ETH_RDES3_LT 0x00070000 +#define ETH_RDES3_ES 0x00008000 +#define ETH_RDES3_PL 0x00007FFF + +/* Receive context descriptor */ +#define ETH_RDES0_RTSL 0xFFFFFFFF +#define ETH_RDES1_RTSH 0xFFFFFFFF +#define ETH_RDES3_OWN 0x80000000 +#define ETH_RDES3_CTXT 0x40000000 + +#define RTL8211E_BMCR ((uint16_t)0x0000U) /* Basic Mode Control Register. */ +#define RTL8211E_BMSR ((uint16_t)0x0001U) /* Basic Mode Status Register. */ +#define RTL8211E_PHYID1 ((uint16_t)0x0002U) /* PHY Identifier Register 1. */ +#define RTL8211E_PHYID2 ((uint16_t)0x0003U) /* PHY Identifier Register 2. */ +#define RTL8211E_ANAR ((uint16_t)0x0004U) /* Auto-Negotiation Advertising Register. */ +#define RTL8211E_ANLPAR ((uint16_t)0x0005U) /* Auto-Negotiation Link Partner Ability Register. */ +#define RTL8211E_ANER ((uint16_t)0x0006U) /* Auto-Negotiation Expansion Register.*/ +#define RTL8211E_ANNPTR ((uint16_t)0x0007U) /* Auto-Negotiation Next Page Transmit Register.*/ +#define RTL8211E_ANNPRR ((uint16_t)0x0008U) /* Auto-Negotiation Next Page Receive Register. */ +#define RTL8211E_GBCR ((uint16_t)0x0009U) /* 1000Base-T Control Register. */ +#define RTL8211E_GBSR ((uint16_t)0x000AU) /* 1000Base-T Status Register. */ +#define RTL8211E_MMDACR ((uint16_t)0x000DU) /* MMD Access Control Register. */ +#define RTL8211E_MMDAADR ((uint16_t)0x000EU) /* MMD Access Address Data Register. */ +#define RTL8211E_GBESR ((uint16_t)0x000FU) /* 1000Base-T Extended Status Register. */ +#define RTL8211E_PHYCR ((uint16_t)0x0010U) +#define RTL8211E_PHYSR ((uint16_t)0x0011U) +#define RTL8211E_INER ((uint16_t)0x0012U) /* Interrupt Enable Register. */ +#define RTL8211E_INSR ((uint16_t)0x0013U) /* Interrupt Status Register. */ +#define RTL8211E_RXERC ((uint16_t)0x0018U) +#define RTL8211E_LDPSR ((uint16_t)0x001BU) +#define RTL8211E_EPAGSR ((uint16_t)0x001EU) +#define RTL8211E_PAGSR ((uint16_t)0x001FU) + +/* Basic Mode Control register */ +#define RTL8211E_BMCR_RESET 0x8000 +#define RTL8211E_BMCR_LOOPBACK 0x4000 +#define RTL8211E_BMCR_SPEED_SEL_LSB 0x2000 +#define RTL8211E_BMCR_AN_EN 0x1000 +#define RTL8211E_BMCR_POWER_DOWN 0x0800 +#define RTL8211E_BMCR_ISOLATE 0x0400 +#define RTL8211E_BMCR_RESTART_AN 0x0200 +#define RTL8211E_BMCR_DUPLEX_MODE 0x0100 +#define RTL8211E_BMCR_COL_TEST 0x0080 +#define RTL8211E_BMCR_SPEED_SEL_MSB 0x0040 + +/* Basic Mode Status register */ +#define RTL8211E_BMSR_100BT4 0x8000 +#define RTL8211E_BMSR_100BTX_FD 0x4000 +#define RTL8211E_BMSR_100BTX_HD 0x2000 +#define RTL8211E_BMSR_10BT_FD 0x1000 +#define RTL8211E_BMSR_10BT_HD 0x0800 +#define RTL8211E_BMSR_100BT2_FD 0x0400 +#define RTL8211E_BMSR_100BT2_HD 0x0200 +#define RTL8211E_BMSR_EXTENDED_STATUS 0x0100 +#define RTL8211E_BMSR_PREAMBLE_SUPPR 0x0040 +#define RTL8211E_BMSR_AN_COMPLETE 0x0020 +#define RTL8211E_BMSR_REMOTE_FAULT 0x0010 +#define RTL8211E_BMSR_AN_CAPABLE 0x0008 +#define RTL8211E_BMSR_LINK_STATUS 0x0004 +#define RTL8211E_BMSR_JABBER_DETECT 0x0002 +#define RTL8211E_BMSR_EXTENDED_CAPABLE 0x0001 + +/* PHY Identifier 1 register */ +#define RTL8211E_PHYID1_OUI_MSB 0xFFFF +#define RTL8211E_PHYID1_OUI_MSB_DEFAULT 0x001C + +/* PHY Identifier 2 register */ +#define RTL8211E_PHYID2_OUI_LSB 0xFC00 +#define RTL8211E_PHYID2_OUI_LSB_DEFAULT 0xC800 +#define RTL8211E_PHYID2_MODEL_NUM 0x03F0 +#define RTL8211E_PHYID2_MODEL_NUM_DEFAULT 0x0110 +#define RTL8211E_PHYID2_REVISION_NUM 0x000F +#define RTL8211E_PHYID2_REVISION_NUM_DEFAULT 0x0005 + +/* Auto-Negotiation Advertisement register */ +#define RTL8211E_ANAR_NEXT_PAGE 0x8000 +#define RTL8211E_ANAR_REMOTE_FAULT 0x2000 +#define RTL8211E_ANAR_ASYM_PAUSE 0x0800 +#define RTL8211E_ANAR_PAUSE 0x0400 +#define RTL8211E_ANAR_100BT4 0x0200 +#define RTL8211E_ANAR_100BTX_FD 0x0100 +#define RTL8211E_ANAR_100BTX_HD 0x0080 +#define RTL8211E_ANAR_10BT_FD 0x0040 +#define RTL8211E_ANAR_10BT_HD 0x0020 +#define RTL8211E_ANAR_SELECTOR 0x001F +#define RTL8211E_ANAR_SELECTOR_DEFAULT 0x0001 + +/* Auto-Negotiation Link Partner Ability register */ +#define RTL8211E_ANLPAR_NEXT_PAGE 0x8000 +#define RTL8211E_ANLPAR_ACK 0x4000 +#define RTL8211E_ANLPAR_REMOTE_FAULT 0x2000 +#define RTL8211E_ANLPAR_ASYM_PAUSE 0x0800 +#define RTL8211E_ANLPAR_PAUSE 0x0400 +#define RTL8211E_ANLPAR_100BT4 0x0200 +#define RTL8211E_ANLPAR_100BTX_FD 0x0100 +#define RTL8211E_ANLPAR_100BTX_HD 0x0080 +#define RTL8211E_ANLPAR_10BT_FD 0x0040 +#define RTL8211E_ANLPAR_10BT_HD 0x0020 +#define RTL8211E_ANLPAR_SELECTOR 0x001F +#define RTL8211E_ANLPAR_SELECTOR_DEFAULT 0x0001 + +/* Auto-Negotiation Expansion register */ +#define RTL8211E_ANER_PAR_DETECT_FAULT 0x0010 +#define RTL8211E_ANER_LP_NEXT_PAGE_ABLE 0x0008 +#define RTL8211E_ANER_NEXT_PAGE_ABLE 0x0004 +#define RTL8211E_ANER_PAGE_RECEIVED 0x0002 +#define RTL8211E_ANER_LP_AN_ABLE 0x0001 + +/* Auto-Negotiation Next Page Transmit register */ +#define RTL8211E_ANNPTR_NEXT_PAGE 0x8000 +#define RTL8211E_ANNPTR_MSG_PAGE 0x2000 +#define RTL8211E_ANNPTR_ACK2 0x1000 +#define RTL8211E_ANNPTR_TOGGLE 0x0800 +#define RTL8211E_ANNPTR_MESSAGE 0x07FF + +/* Auto-Negotiation Next Page Receive register */ +#define RTL8211E_ANNPRR_NEXT_PAGE 0x8000 +#define RTL8211E_ANNPRR_ACK 0x4000 +#define RTL8211E_ANNPRR_MSG_PAGE 0x2000 +#define RTL8211E_ANNPRR_ACK2 0x1000 +#define RTL8211E_ANNPRR_TOGGLE 0x0800 +#define RTL8211E_ANNPRR_MESSAGE 0x07FF + +/* 1000Base-T Control register */ +#define RTL8211E_GBCR_TEST_MODE 0xE000 +#define RTL8211E_GBCR_MS_MAN_CONF_EN 0x1000 +#define RTL8211E_GBCR_MS_MAN_CONF_VAL 0x0800 +#define RTL8211E_GBCR_PORT_TYPE 0x0400 +#define RTL8211E_GBCR_1000BT_FD 0x0200 + +/* 1000Base-T Status register */ +#define RTL8211E_GBSR_MS_CONF_FAULT 0x8000 +#define RTL8211E_GBSR_MS_CONF_RES 0x4000 +#define RTL8211E_GBSR_LOCAL_RECEIVER_STATUS 0x2000 +#define RTL8211E_GBSR_REMOTE_RECEIVER_STATUS 0x1000 +#define RTL8211E_GBSR_LP_1000BT_FD 0x0800 +#define RTL8211E_GBSR_LP_1000BT_HD 0x0400 +#define RTL8211E_GBSR_IDLE_ERR_COUNT 0x00FF + +/* MMD Access Control register */ +#define RTL8211E_MMDACR_FUNC 0xC000 +#define RTL8211E_MMDACR_FUNC_ADDR 0x0000 +#define RTL8211E_MMDACR_FUNC_DATA_NO_POST_INC 0x4000 +#define RTL8211E_MMDACR_FUNC_DATA_POST_INC_RW 0x8000 +#define RTL8211E_MMDACR_FUNC_DATA_POST_INC_W 0xC000 +#define RTL8211E_MMDACR_DEVAD 0x001F + +/* 1000Base-T Extended Status register */ +#define RTL8211E_GBESR_1000BX_FD 0x8000 +#define RTL8211E_GBESR_1000BX_HD 0x4000 +#define RTL8211E_GBESR_1000BT_FD 0x2000 +#define RTL8211E_GBESR_1000BT_HD 0x1000 + +/* PHY Specific Control register */ +#define RTL8211E_PHYCR_RXC_DIS 0x8000 +#define RTL8211E_PHYCR_FPR_FAIL_SEL 0x7000 +#define RTL8211E_PHYCR_ASSERT_CRS_ON_TX 0x0800 +#define RTL8211E_PHYCR_FORCE_LINK_GOOD 0x0400 +#define RTL8211E_PHYCR_CROSSOVER_EN 0x0040 +#define RTL8211E_PHYCR_MDI_MODE 0x0020 +#define RTL8211E_PHYCR_CLK125_DIS 0x0010 +#define RTL8211E_PHYCR_JABBER_DIS 0x0001 + +/* PHY Specific Status register */ +#define RTL8211E_PHYSR_SPEED 0xC000 +#define RTL8211E_PHYSR_SPEED_10MBPS 0x0000 +#define RTL8211E_PHYSR_SPEED_100MBPS 0x4000 +#define RTL8211E_PHYSR_SPEED_1000MBPS 0x8000 +#define RTL8211E_PHYSR_DUPLEX 0x2000 +#define RTL8211E_PHYSR_PAGE_RECEIVED 0x1000 +#define RTL8211E_PHYSR_SPEED_DUPLEX_RESOLVED 0x0800 +#define RTL8211E_PHYSR_LINK 0x0400 +#define RTL8211E_PHYSR_MDI_CROSSOVER_STATUS 0x0040 +#define RTL8211E_PHYSR_PRE_LINKOK 0x0002 +#define RTL8211E_PHYSR_JABBER 0x0001 + +/* Interrupt Status register */ +#define RTL8211E_INER_AN_ERROR 0x8000 +#define RTL8211E_INER_PAGE_RECEIVED 0x1000 +#define RTL8211E_INER_AN_COMPLETE 0x0800 +#define RTL8211E_INER_LINK_STATUS 0x0400 +#define RTL8211E_INER_SYMBOL_ERROR 0x0200 +#define RTL8211E_INER_FALSE_CARRIER 0x0100 +#define RTL8211E_INER_JABBER 0x0001 + +/* Interrupt Status register */ +#define RTL8211E_INSR_AN_ERROR 0x8000 +#define RTL8211E_INSR_PAGE_RECEIVED 0x1000 +#define RTL8211E_INSR_AN_COMPLETE 0x0800 +#define RTL8211E_INSR_LINK_STATUS 0x0400 +#define RTL8211E_INSR_SYMBOL_ERROR 0x0200 +#define RTL8211E_INSR_FALSE_CARRIER 0x0100 +#define RTL8211E_INSR_JABBER 0x0001 + +/* Link Down Power Saving register */ +#define RTL8211E_LDPSR_POWER_SAVE_MODE 0x0001 + +/* Extension Page Select register */ +#define RTL8211E_EPAGSR_EXT_PAGE_SEL 0x00FF + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/mfxstm32l152.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/mfxstm32l152.c new file mode 100644 index 0000000000..d02902ca3e --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/mfxstm32l152.c @@ -0,0 +1,1602 @@ +/** + ****************************************************************************** + * @file mfxstm32l152.c + * @author MCD Application Team + * @brief This file provides a set of functions needed to manage the MFXSTM32L152 + * IO Expander devices. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "mfxstm32l152.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @defgroup MFXSTM32L152 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Types_Definitions + * @{ + */ + +/* Private define ------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Defines + * @{ + */ +#define MFXSTM32L152_MAX_INSTANCE 3 + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Macros + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Variables + * @{ + */ + +/* Touch screen driver structure initialization */ +TS_DrvTypeDef mfxstm32l152_ts_drv = +{ + mfxstm32l152_Init, + mfxstm32l152_ReadID, + mfxstm32l152_Reset, + + mfxstm32l152_TS_Start, + mfxstm32l152_TS_DetectTouch, + mfxstm32l152_TS_GetXY, + + mfxstm32l152_TS_EnableIT, + mfxstm32l152_TS_ClearIT, + mfxstm32l152_TS_ITStatus, + mfxstm32l152_TS_DisableIT, +}; + +/* IO driver structure initialization */ +IO_DrvTypeDef mfxstm32l152_io_drv = +{ + mfxstm32l152_Init, + mfxstm32l152_ReadID, + mfxstm32l152_Reset, + + mfxstm32l152_IO_Start, + mfxstm32l152_IO_Config, + mfxstm32l152_IO_WritePin, + mfxstm32l152_IO_ReadPin, + + mfxstm32l152_IO_EnableIT, + mfxstm32l152_IO_DisableIT, + mfxstm32l152_IO_ITStatus, + mfxstm32l152_IO_ClearIT, +}; + +/* IDD driver structure initialization */ +IDD_DrvTypeDef mfxstm32l152_idd_drv = +{ + mfxstm32l152_Init, + mfxstm32l152_DeInit, + mfxstm32l152_ReadID, + mfxstm32l152_Reset, + mfxstm32l152_LowPower, + mfxstm32l152_WakeUp, + + mfxstm32l152_IDD_Start, + mfxstm32l152_IDD_Config, + mfxstm32l152_IDD_GetValue, + + mfxstm32l152_IDD_EnableIT, + mfxstm32l152_IDD_ClearIT, + mfxstm32l152_IDD_GetITStatus, + mfxstm32l152_IDD_DisableIT, + + mfxstm32l152_Error_EnableIT, + mfxstm32l152_Error_ClearIT, + mfxstm32l152_Error_GetITStatus, + mfxstm32l152_Error_DisableIT, + mfxstm32l152_Error_ReadSrc, + mfxstm32l152_Error_ReadMsg +}; + + +/* mfxstm32l152 instances by address */ +uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Function_Prototypes + * @{ + */ +static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr); +static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr); +static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue ); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Functions + * @{ + */ + +/** + * @brief Initialize the mfxstm32l152 and configure the needed hardware resources + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_Init(uint16_t DeviceAddr) +{ + uint8_t instance; + uint8_t empty; + + /* Check if device instance already exists */ + instance = mfxstm32l152_GetInstance(DeviceAddr); + + /* To prevent double initialization */ + if(instance == 0xFF) + { + /* Look for empty instance */ + empty = mfxstm32l152_GetInstance(0); + + if(empty < MFXSTM32L152_MAX_INSTANCE) + { + /* Register the current device instance */ + mfxstm32l152[empty] = DeviceAddr; + + /* Initialize IO BUS layer */ + MFX_IO_Init(); + } + } + + mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH); + mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL); +} + +/** + * @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_DeInit(uint16_t DeviceAddr) +{ + uint8_t instance; + + /* release existing instance */ + instance = mfxstm32l152_ReleaseInstance(DeviceAddr); + + /* De-Init only if instance was previously registered */ + if(instance != 0xFF) + { + /* De-Initialize IO BUS layer */ + MFX_IO_DeInit(); + } +} + +/** + * @brief Reset the mfxstm32l152 by Software. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_Reset(uint16_t DeviceAddr) +{ + /* Soft Reset */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST); + + /* Wait for a delay to ensure registers erasing */ + rt_thread_delay(10); +} + +/** + * @brief Put mfxstm32l152 Device in Low Power standby mode + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_LowPower(uint16_t DeviceAddr) +{ + /* Enter standby mode */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY); + + /* enable wakeup pin */ + MFX_IO_EnableWakeupPin(); +} + +/** + * @brief WakeUp mfxstm32l152 from standby mode + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_WakeUp(uint16_t DeviceAddr) +{ + uint8_t instance; + + /* Check if device instance already exists */ + instance = mfxstm32l152_GetInstance(DeviceAddr); + + /* if instance does not exist, first initialize pins*/ + if(instance == 0xFF) + { + /* enable wakeup pin */ + MFX_IO_EnableWakeupPin(); + } + + /* toggle wakeup pin */ + MFX_IO_Wakeup(); +} + +/** + * @brief Read the MFXSTM32L152 IO Expander device ID. + * @param DeviceAddr: Device address on communication Bus. + * @retval The Device ID (two bytes). + */ +uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr) +{ + uint8_t id; + + /* Wait for a delay to ensure the state of registers */ + rt_thread_mdelay(1); + + /* Initialize IO BUS layer */ + MFX_IO_Init(); + + id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID); + + /* Return the device ID value */ + return (id); +} + +/** + * @brief Read the MFXSTM32L152 device firmware version. + * @param DeviceAddr: Device address on communication Bus. + * @retval The Device FW version (two bytes). + */ +uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr) +{ + uint8_t data[2]; + + MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ; + + /* Recompose MFX firmware value */ + return ((data[0] << 8) | data[1]); +} + +/** + * @brief Enable the interrupt mode for the selected IT source + * @param DeviceAddr: Device address on communication Bus. + * @param Source: The interrupt source to be configured, could be: + * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * @retval None + */ +void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source) +{ + uint8_t tmp = 0; + + /* Get the current value of the INT_EN register */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN); + + /* Set the interrupts to be Enabled */ + tmp |= Source; + + /* Set the register */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp); +} + +/** + * @brief Disable the interrupt mode for the selected IT source + * @param DeviceAddr: Device address on communication Bus. + * @param Source: The interrupt source to be configured, could be: + * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * @retval None + */ +void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source) +{ + uint8_t tmp = 0; + + /* Get the current value of the INT_EN register */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN); + + /* Set the interrupts to be Enabled */ + tmp &= ~Source; + + /* Set the register */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp); +} + + +/** + * @brief Returns the selected Global interrupt source pending bit value + * @param DeviceAddr: Device address on communication Bus. + * @param Source: the Global interrupt source to be checked, could be: + * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * @retval The value of the checked Global interrupt source status. + */ +uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source) +{ + /* Return the global IT source status (pending or not)*/ + return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source)); +} + +/** + * @brief Clear the selected Global interrupt pending bit(s) + * @param DeviceAddr: Device address on communication Bus. + * @param Source: the Global interrupt source to be cleared, could be any combination + * of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input + * with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers. + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers + * @retval None + */ +void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source) +{ + /* Write 1 to the bits that have to be cleared */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source); +} + +/** + * @brief Set the global interrupt Polarity of IRQ_OUT_PIN. + * @param DeviceAddr: Device address on communication Bus. + * @param Polarity: the IT mode polarity, could be one of the following values: + * @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge + * @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge + * @retval None + */ +void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity) +{ + uint8_t tmp = 0; + + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT); + + /* Mask the polarity bits */ + tmp &= ~(uint8_t)0x02; + + /* Modify the Interrupt Output line configuration */ + tmp |= Polarity; + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp); + + /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */ + rt_thread_delay(1); + +} + +/** + * @brief Set the global interrupt Type of IRQ_OUT_PIN. + * @param DeviceAddr: Device address on communication Bus. + * @param Type: Interrupt line activity type, could be one of the following values: + * @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line + * @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line + * @retval None + */ +void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type) +{ + uint8_t tmp = 0; + + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT); + + /* Mask the type bits */ + tmp &= ~(uint8_t)0x01; + + /* Modify the Interrupt Output line configuration */ + tmp |= Type; + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp); + + /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */ + rt_thread_delay(1); + +} + + +/* ------------------------------------------------------------------ */ +/* ----------------------- GPIO ------------------------------------- */ +/* ------------------------------------------------------------------ */ + + +/** + * @brief Start the IO functionality used and enable the AF for selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param AF_en: 0 to disable, else enabled. + * @retval None + */ +void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Set the IO Functionalities to be Enabled */ + mode |= MFXSTM32L152_GPIO_EN; + + /* Enable ALTERNATE functions */ + /* AGPIO[0..3] can be either IDD or GPIO */ + /* AGPIO[4..7] can be either TS or GPIO */ + /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */ + /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ + /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */ + /* if however IDD or TS are not connected then set it on gives more GPIOs availability */ + /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */ + if (IO_Pin > 0xFFFF) + { + mode |= MFXSTM32L152_ALTERNATE_GPIO_EN; + } + else + { + mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN; + } + + /* Write the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + + /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */ + rt_thread_delay(1); +} + +/** + * @brief Configures the IO pin(s) according to IO mode structure value. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The output pin to be set or reset. This parameter can be one + * of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @param IO_Mode: The IO pin mode to configure, could be one of the following values: + * @arg IO_MODE_INPUT + * @arg IO_MODE_OUTPUT + * @arg IO_MODE_IT_RISING_EDGE + * @arg IO_MODE_IT_FALLING_EDGE + * @arg IO_MODE_IT_LOW_LEVEL + * @arg IO_MODE_IT_HIGH_LEVEL + * @arg IO_MODE_INPUT_PU, + * @arg IO_MODE_INPUT_PD, + * @arg IO_MODE_OUTPUT_OD_PU, + * @arg IO_MODE_OUTPUT_OD_PD, + * @arg IO_MODE_OUTPUT_PP_PU, + * @arg IO_MODE_OUTPUT_PP_PD, + * @arg IO_MODE_IT_RISING_EDGE_PU + * @arg IO_MODE_IT_FALLING_EDGE_PU + * @arg IO_MODE_IT_LOW_LEVEL_PU + * @arg IO_MODE_IT_HIGH_LEVEL_PU + * @arg IO_MODE_IT_RISING_EDGE_PD + * @arg IO_MODE_IT_FALLING_EDGE_PD + * @arg IO_MODE_IT_LOW_LEVEL_PD + * @arg IO_MODE_IT_HIGH_LEVEL_PD + * @retval None + */ +uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode) +{ + uint8_t error_code = 0; + + /* Configure IO pin according to selected IO mode */ + switch(IO_Mode) + { + case IO_MODE_OFF: /* Off or analog mode */ + case IO_MODE_ANALOG: /* Off or analog mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_INPUT: /* Input mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_INPUT_PU: /* Input mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_INPUT_PD: /* Input mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_OUTPUT: /* Output mode */ + case IO_MODE_OUTPUT_PP_PD: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_OUTPUT_PP_PU: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_OUTPUT_OD_PD: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_OUTPUT_OD_PU: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + default: + error_code = (uint8_t) IO_Mode; + break; + } + + return error_code; +} + +/** + * @brief Initialize the selected IO pin direction. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO pin to be configured. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT. + * @retval None + */ +void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction); +} + +/** + * @brief Set the global interrupt Type. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO pin to be configured. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @param Evt: Interrupt line activity type, could be one of the following values: + * @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model + * @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model + * @retval None + */ +void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt); + rt_thread_delay(1); +} + +/** + * @brief Configure the Edge for which a transition is detectable for the + * selected pin. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO pin to be configured. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @param Evt: Interrupt line activity type, could be one of the following values: + * @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge + * @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge + * @retval None + */ +void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type); + rt_thread_delay(1); +} + +/** + * @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The output pin to be set or reset. This parameter can be one + * of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @param PinState: The new IO pin state. + * @retval None + */ +void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState) +{ + /* Apply the bit value to the selected pin */ + if (PinState != 0) + { + /* Set the SET register */ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1); + } + else + { + /* Set the CLEAR register */ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1); + } +} + +/** + * @brief Return the state of the selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The output pin to be set or reset. This parameter can be one + * of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @retval IO pin(s) state. + */ +uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + + if(IO_Pin & 0x000000FF) + { + tmp1 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1); + } + if(IO_Pin & 0x0000FF00) + { + tmp2 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2); + } + if(IO_Pin & 0x00FF0000) + { + tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3); + } + + tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16); + + return(tmp3 & IO_Pin); +} + +/** + * @brief Enable the global IO interrupt source. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global IO IT source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO); +} + +/** + * @brief Disable the global IO interrupt source. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global IO IT source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO); +} + +/** + * @brief Enable interrupt mode for the selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @retval None + */ +void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1); +} + +/** + * @brief Disable interrupt mode for the selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @retval None + */ +void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0); +} + + +/** + * @brief Check the status of the selected IO interrupt pending bit + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO interrupt to be checked could be: + * @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23. + * @retval Status of the checked IO pin(s). + */ +uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + /* Get the Interrupt status */ + uint8_t tmp1 = 0; + uint16_t tmp2 = 0; + uint32_t tmp3 = 0; + + if(IO_Pin & 0xFF) + { + tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1); + } + if(IO_Pin & 0xFFFF00) + { + tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2); + } + if(IO_Pin & 0xFFFF0000) + { + tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3); + } + + tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16); + + return(tmp3 & IO_Pin); +} + +/** + * @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: the IO interrupt to be cleared, could be: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @retval None + */ +void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + /* Clear the IO IT pending bit(s) by acknowledging */ + /* it cleans automatically also the Global IRQ_GPIO */ + /* normally this function is called under interrupt */ + uint8_t pin_0_7, pin_8_15, pin_16_23; + + pin_0_7 = IO_Pin & 0x0000ff; + pin_8_15 = IO_Pin >> 8; + pin_8_15 = pin_8_15 & 0x00ff; + pin_16_23 = IO_Pin >> 16; + + if (pin_0_7) + { + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7); + } + if (pin_8_15) + { + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15); + } + if (pin_16_23) + { + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23); + } +} + + +/** + * @brief Enable the AF for aGPIO. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Enable ALTERNATE functions */ + /* AGPIO[0..3] can be either IDD or GPIO */ + /* AGPIO[4..7] can be either TS or GPIO */ + /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */ + /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ + /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */ + /* if however IDD or TS are not connected then set it on gives more GPIOs availability */ + /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */ + mode |= MFXSTM32L152_ALTERNATE_GPIO_EN; + + /* Write the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); +} + +/** + * @brief Disable the AF for aGPIO. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ + void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Enable ALTERNATE functions */ + /* AGPIO[0..3] can be either IDD or GPIO */ + /* AGPIO[4..7] can be either TS or GPIO */ + /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */ + /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ + /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */ + /* if however IDD or TS are not connected then set it on gives more GPIOs availability */ + /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */ + mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN; + + /* Write the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + +} + + +/* ------------------------------------------------------------------ */ +/* --------------------- TOUCH SCREEN ------------------------------- */ +/* ------------------------------------------------------------------ */ + +/** + * @brief Configures the touch Screen Controller (Single point detection) + * @param DeviceAddr: Device address on communication Bus. + * @retval None. + */ +void mfxstm32l152_TS_Start(uint16_t DeviceAddr) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Set the Functionalities to be Enabled */ + mode |= MFXSTM32L152_TS_EN; + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + + /* Wait for 2 ms */ + rt_thread_delay(2); + + /* Select 2 nF filter capacitor */ + /* Configuration: + - Touch average control : 4 samples + - Touch delay time : 500 uS + - Panel driver setting time: 500 uS + */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32); + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5); + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04); + + /* Configure the Touch FIFO threshold: single point reading */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01); + + /* Clear the FIFO memory content. */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO); + + /* Touch screen control configuration : + - No window tracking index + */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00); + + + /* Clear all the IT status pending bits if any */ + mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF); + + /* Wait for 1 ms delay */ + rt_thread_delay(1); +} + +/** + * @brief Return if there is touch detected or not. + * @param DeviceAddr: Device address on communication Bus. + * @retval Touch detected state. + */ +uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr) +{ + uint8_t state; + uint8_t ret = 0; + + state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA); + state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS); + + if(state > 0) + { + if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0) + { + ret = 1; + } + } + + return ret; +} + +/** + * @brief Get the touch screen X and Y positions values + * @param DeviceAddr: Device address on communication Bus. + * @param X: Pointer to X position value + * @param Y: Pointer to Y position value + * @retval None. + */ +void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y) +{ + uint8_t data_xy[3]; + + MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ; + + /* Calculate positions values */ + *X = (data_xy[1]<<4) + (data_xy[0]>>4); + *Y = (data_xy[2]<<4) + (data_xy[0]&4); + + /* Reset the FIFO memory content. */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global TS IT source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global TS IT source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval TS interrupts status + */ +uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr) +{ + /* Return TS interrupts status */ + return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS)); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr) +{ + /* Clear the global TS IT source */ + mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS); +} + +/* ------------------------------------------------------------------ */ +/* --------------------- IDD MEASUREMENT ---------------------------- */ +/* ------------------------------------------------------------------ */ + +/** + * @brief Launch IDD current measurement + * @param DeviceAddr: Device address on communication Bus + * @retval None. + */ +void mfxstm32l152_IDD_Start(uint16_t DeviceAddr) +{ + uint8_t mode = 0; + + /* Get the current register value */ + mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL); + + /* Set the Functionalities to be enabled */ + mode |= MFXSTM32L152_IDD_CTRL_REQ; + + /* Start measurement campaign */ + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode); +} + +/** + * @brief Configures the IDD current measurement + * @param DeviceAddr: Device address on communication Bus. + * @param MfxIddConfig: Parameters depending on hardware config. + * @retval None + */ +void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig) +{ + uint8_t value = 0; + uint8_t mode = 0; + + /* Get the current register value */ + mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN) + { + /* Set the Functionalities to be enabled */ + mode |= MFXSTM32L152_IDD_EN; + + /* Set the new register value */ + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + } + + /* Control register setting: number of shunts */ + value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB); + value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS); + value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value); + + /* Idd pre delay configuration: unit and value*/ + value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) | + (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value); + + /* Shunt 0 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt0Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value); + + /* Shunt 1 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt1Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value); + + /* Shunt 2 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt2Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value); + + /* Shunt 3 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt3Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value); + + /* Shunt 4 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt4Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value); + + /* Shunt 0 stabilization delay */ + value = MfxIddConfig.Shunt0StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value); + + /* Shunt 1 stabilization delay */ + value = MfxIddConfig.Shunt1StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value); + + /* Shunt 2 stabilization delay */ + value = MfxIddConfig.Shunt2StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value); + + /* Shunt 3 stabilization delay */ + value = MfxIddConfig.Shunt3StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value); + + /* Shunt 4 stabilization delay */ + value = MfxIddConfig.Shunt4StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value); + + /* Idd ampli gain value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.AmpliGain >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value); + value = (uint8_t) (MfxIddConfig.AmpliGain); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value); + + /* Idd VDD min value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.VddMin >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value); + value = (uint8_t) (MfxIddConfig.VddMin); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value); + + /* Idd number of measurements */ + value = MfxIddConfig.MeasureNb; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value); + + /* Idd delta delay configuration: unit and value */ + value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) | + (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value); + + /* Idd number of shut on board */ + value = MfxIddConfig.ShuntNbOnBoard; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value); +} + +/** + * @brief This function allows to modify number of shunt used for a measurement + * @param DeviceAddr: Device address on communication Bus + * @retval None. + */ +void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit) +{ + uint8_t mode = 0; + + /* Get the current register value */ + mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL); + + /* Clear number of shunt limit */ + mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB); + + /* Clear number of shunt limit */ + mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB); + + /* Write noewx desired limit */ + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode); +} + +/** + * @brief Get Idd current value + * @param DeviceAddr: Device address on communication Bus + * @param ReadValue: Pointer on value to be read + * @retval Idd value in 10 nA. + */ +void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue) +{ + uint8_t data[3]; + + MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ; + + /* Recompose Idd current value */ + *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2]; + +} + +/** + * @brief Get Last shunt used for measurement + * @param DeviceAddr: Device address on communication Bus + * @retval Last shunt used + */ +uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr) +{ + return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED)); +} + +/** + * @brief Configure mfx to enable Idd interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global IDD interrupt source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD); +} + +/** + * @brief Clear Idd global interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr) +{ + /* Clear the global IDD interrupt source */ + mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD); +} + +/** + * @brief get Idd interrupt status + * @param DeviceAddr: Device address on communication Bus. + * @retval IDD interrupts status + */ +uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr) +{ + /* Return IDD interrupt status */ + return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD)); +} + +/** + * @brief disable Idd interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None. + */ +void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global IDD interrupt source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD); +} + + +/* ------------------------------------------------------------------ */ +/* --------------------- ERROR MANAGEMENT --------------------------- */ +/* ------------------------------------------------------------------ */ + +/** + * @brief Read Error Source. + * @param DeviceAddr: Device address on communication Bus. + * @retval Error message code with error source + */ +uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr) +{ + /* Get the current source register value */ + return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC)); +} + +/** + * @brief Read Error Message + * @param DeviceAddr: Device address on communication Bus. + * @retval Error message code with error source + */ +uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr) +{ + /* Get the current message register value */ + return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG)); +} + +/** + * @brief Enable Error global interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ + +void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global Error interrupt source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR); +} + +/** + * @brief Clear Error global interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr) +{ + /* Clear the global Error interrupt source */ + mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR); +} + +/** + * @brief get Error interrupt status + * @param DeviceAddr: Device address on communication Bus. + * @retval Error interrupts status + */ +uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr) +{ + /* Return Error interrupt status */ + return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR)); +} + +/** + * @brief disable Error interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None. + */ +void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global Error interrupt source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR); +} + +/** + * @brief FOR DEBUG ONLY + */ +uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr) +{ + /* Get the current register value */ + return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr)); +} + +void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value) +{ + /* set the current register value */ + MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value); +} + +/* ------------------------------------------------------------------ */ +/* ----------------------- Private functions ------------------------ */ +/* ------------------------------------------------------------------ */ +/** + * @brief Check if the device instance of the selected address is already registered + * and return its index + * @param DeviceAddr: Device address on communication Bus. + * @retval Index of the device instance if registered, 0xFF if not. + */ +static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr) +{ + uint8_t idx = 0; + + /* Check all the registered instances */ + for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++) + { + if(mfxstm32l152[idx] == DeviceAddr) + { + return idx; + } + } + + return 0xFF; +} + +/** + * @brief Release registered device instance + * @param DeviceAddr: Device address on communication Bus. + * @retval Index of released device instance, 0xFF if not. + */ +static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr) +{ + uint8_t idx = 0; + + /* Check for all the registered instances */ + for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++) + { + if(mfxstm32l152[idx] == DeviceAddr) + { + mfxstm32l152[idx] = 0; + return idx; + } + } + return 0xFF; +} + +/** + * @brief Internal routine + * @param DeviceAddr: Device address on communication Bus. + * @param RegisterAddr: Register Address + * @param PinPosition: Pin [0:23] + * @param PinValue: 0/1 + * @retval None + */ +void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue ) +{ + uint8_t tmp = 0; + uint8_t pin_0_7, pin_8_15, pin_16_23; + + pin_0_7 = PinPosition & 0x0000ff; + pin_8_15 = PinPosition >> 8; + pin_8_15 = pin_8_15 & 0x00ff; + pin_16_23 = PinPosition >> 16; + + if (pin_0_7) + { + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, RegisterAddr); + + /* Set the selected pin direction */ + if (PinValue != 0) + { + tmp |= (uint8_t)pin_0_7; + } + else + { + tmp &= ~(uint8_t)pin_0_7; + } + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, RegisterAddr, tmp); + } + + if (pin_8_15) + { + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1); + + /* Set the selected pin direction */ + if (PinValue != 0) + { + tmp |= (uint8_t)pin_8_15; + } + else + { + tmp &= ~(uint8_t)pin_8_15; + } + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp); + } + + if (pin_16_23) + { + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2); + + /* Set the selected pin direction */ + if (PinValue != 0) + { + tmp |= (uint8_t)pin_16_23; + } + else + { + tmp &= ~(uint8_t)pin_16_23; + } + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp); + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/mfxstm32l152.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/mfxstm32l152.h new file mode 100644 index 0000000000..38ca8a6f6a --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/mfxstm32l152.h @@ -0,0 +1,853 @@ +/** + ****************************************************************************** + * @file mfxstm32l152.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the + * mfxstm32l152.c IO expander driver. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MFXSTM32L152_H +#define __MFXSTM32L152_H + +#include "board.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @defgroup MFXSTM32L152 + * @{ + */ + + /** + * @brief GPIO: IO Pins definition + */ +#define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) +#define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) +#define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) +#define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) +#define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) +#define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) +#define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) +#define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) + +#define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) +#define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) +#define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) +#define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) +#define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) +#define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) +#define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) +#define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) + +#define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) +#define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) +#define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) +#define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) +#define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) +#define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) +#define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) +#define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) + +#define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 +#define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 +#define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 +#define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 +#define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 +#define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 +#define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 +#define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 + +#define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) +#define IO_PIN_ALL MFXSTM32L152_GPIO_PINS_ALL +/** + * @brief IO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + IO_PIN_RESET = 0, + IO_PIN_SET +}IO_PinState; + +typedef enum +{ + IO_MODE_INPUT = 0, /* input floating */ + IO_MODE_OUTPUT, /* output Push Pull */ + IO_MODE_IT_RISING_EDGE, /* float input - irq detect on rising edge */ + IO_MODE_IT_FALLING_EDGE, /* float input - irq detect on falling edge */ + IO_MODE_IT_LOW_LEVEL, /* float input - irq detect on low level */ + IO_MODE_IT_HIGH_LEVEL, /* float input - irq detect on high level */ + /* following modes only available on MFX*/ + IO_MODE_ANALOG, /* analog mode */ + IO_MODE_OFF, /* when pin isn't used*/ + IO_MODE_INPUT_PU, /* input with internal pull up resistor */ + IO_MODE_INPUT_PD, /* input with internal pull down resistor */ + IO_MODE_OUTPUT_OD, /* Open Drain output without internal resistor */ + IO_MODE_OUTPUT_OD_PU, /* Open Drain output with internal pullup resistor */ + IO_MODE_OUTPUT_OD_PD, /* Open Drain output with internal pulldown resistor */ + IO_MODE_OUTPUT_PP, /* PushPull output without internal resistor */ + IO_MODE_OUTPUT_PP_PU, /* PushPull output with internal pullup resistor */ + IO_MODE_OUTPUT_PP_PD, /* PushPull output with internal pulldown resistor */ + IO_MODE_IT_RISING_EDGE_PU, /* push up resistor input - irq on rising edge */ + IO_MODE_IT_RISING_EDGE_PD, /* push dw resistor input - irq on rising edge */ + IO_MODE_IT_FALLING_EDGE_PU, /* push up resistor input - irq on falling edge */ + IO_MODE_IT_FALLING_EDGE_PD, /* push dw resistor input - irq on falling edge */ + IO_MODE_IT_LOW_LEVEL_PU, /* push up resistor input - irq detect on low level */ + IO_MODE_IT_LOW_LEVEL_PD, /* push dw resistor input - irq detect on low level */ + IO_MODE_IT_HIGH_LEVEL_PU, /* push up resistor input - irq detect on high level */ + IO_MODE_IT_HIGH_LEVEL_PD, /* push dw resistor input - irq detect on high level */ + +}IO_ModeTypedef; + +/** @defgroup IO_Driver_structure IO Driver structure + * @{ + */ +typedef struct +{ + void (*Init)(uint16_t); + uint16_t (*ReadID)(uint16_t); + void (*Reset)(uint16_t); + + void (*Start)(uint16_t, uint32_t); + uint8_t (*Config)(uint16_t, uint32_t, IO_ModeTypedef); + void (*WritePin)(uint16_t, uint32_t, uint8_t); + uint32_t (*ReadPin)(uint16_t, uint32_t); + + void (*EnableIT)(uint16_t); + void (*DisableIT)(uint16_t); + uint32_t (*ITStatus)(uint16_t, uint32_t); + void (*ClearIT)(uint16_t, uint32_t); + +}IO_DrvTypeDef; + +typedef struct +{ + uint16_t AmpliGain; /*!< Specifies ampli gain value + */ + uint16_t VddMin; /*!< Specifies minimum MCU VDD can reach to protect MCU from reset + */ + uint16_t Shunt0Value; /*!< Specifies value of Shunt 0 if existing + */ + uint16_t Shunt1Value; /*!< Specifies value of Shunt 1 if existing + */ + uint16_t Shunt2Value; /*!< Specifies value of Shunt 2 if existing + */ + uint16_t Shunt3Value; /*!< Specifies value of Shunt 3 if existing + */ + uint16_t Shunt4Value; /*!< Specifies value of Shunt 4 if existing + */ + uint16_t Shunt0StabDelay; /*!< Specifies delay of Shunt 0 stabilization if existing + */ + uint16_t Shunt1StabDelay; /*!< Specifies delay of Shunt 1 stabilization if existing + */ + uint16_t Shunt2StabDelay; /*!< Specifies delay of Shunt 2 stabilization if existing + */ + uint16_t Shunt3StabDelay; /*!< Specifies delay of Shunt 3 stabilization if existing + */ + uint16_t Shunt4StabDelay; /*!< Specifies delay of Shunt 4 stabilization if existing + */ + uint8_t ShuntNbOnBoard; /*!< Specifies number of shunts that are present on board + This parameter can be a value of @ref IDD_shunt_number */ + uint8_t ShuntNbUsed; /*!< Specifies number of shunts used for measurement + This parameter can be a value of @ref IDD_shunt_number */ + uint8_t VrefMeasurement; /*!< Specifies if Vref is automatically measured before each Idd measurement + This parameter can be a value of @ref IDD_Vref_Measurement */ + uint8_t Calibration; /*!< Specifies if calibration is done before each Idd measurement + */ + uint8_t PreDelayUnit; /*!< Specifies Pre delay unit + This parameter can be a value of @ref IDD_PreDelay */ + uint8_t PreDelayValue; /*!< Specifies Pre delay value in selected unit + */ + uint8_t MeasureNb; /*!< Specifies number of Measure to be performed + This parameter can be a value between 1 and 256 */ + uint8_t DeltaDelayUnit; /*!< Specifies Delta delay unit + This parameter can be a value of @ref IDD_DeltaDelay */ + uint8_t DeltaDelayValue; /*!< Specifies Delta delay between 2 measures + value can be between 1 and 128 */ +}IDD_ConfigTypeDef; +/** + * @} + */ + +/** @defgroup IDD_Driver_structure IDD Driver structure + * @{ + */ +typedef struct +{ + void (*Init)(uint16_t); + void (*DeInit)(uint16_t); + uint16_t (*ReadID)(uint16_t); + void (*Reset)(uint16_t); + void (*LowPower)(uint16_t); + void (*WakeUp)(uint16_t); + void (*Start)(uint16_t); + void (*Config)(uint16_t,IDD_ConfigTypeDef); + void (*GetValue)(uint16_t, uint32_t *); + void (*EnableIT)(uint16_t); + void (*ClearIT)(uint16_t); + uint8_t (*GetITStatus)(uint16_t); + void (*DisableIT)(uint16_t); + void (*ErrorEnableIT)(uint16_t); + void (*ErrorClearIT)(uint16_t); + uint8_t (*ErrorGetITStatus)(uint16_t); + void (*ErrorDisableIT)(uint16_t); + uint8_t (*ErrorGetSrc)(uint16_t); + uint8_t (*ErrorGetCode)(uint16_t); +}IDD_DrvTypeDef; + +typedef struct +{ + void (*Init)(uint16_t); + uint16_t (*ReadID)(uint16_t); + void (*Reset)(uint16_t); + void (*Start)(uint16_t); + uint8_t (*DetectTouch)(uint16_t); + void (*GetXY)(uint16_t, uint16_t*, uint16_t*); + void (*EnableIT)(uint16_t); + void (*ClearIT)(uint16_t); + uint8_t (*GetITStatus)(uint16_t); + void (*DisableIT)(uint16_t); +}TS_DrvTypeDef; + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Types + * @{ + */ +typedef struct +{ + uint8_t SYS_CTRL; + uint8_t ERROR_SRC; + uint8_t ERROR_MSG; + uint8_t IRQ_OUT; + uint8_t IRQ_SRC_EN; + uint8_t IRQ_PENDING; + uint8_t IDD_CTRL; + uint8_t IDD_PRE_DELAY; + uint8_t IDD_SHUNT0_MSB; + uint8_t IDD_SHUNT0_LSB; + uint8_t IDD_SHUNT1_MSB; + uint8_t IDD_SHUNT1_LSB; + uint8_t IDD_SHUNT2_MSB; + uint8_t IDD_SHUNT2_LSB; + uint8_t IDD_SHUNT3_MSB; + uint8_t IDD_SHUNT3_LSB; + uint8_t IDD_SHUNT4_MSB; + uint8_t IDD_SHUNT4_LSB; + uint8_t IDD_GAIN_MSB; + uint8_t IDD_GAIN_LSB; + uint8_t IDD_VDD_MIN_MSB; + uint8_t IDD_VDD_MIN_LSB; + uint8_t IDD_VALUE_MSB; + uint8_t IDD_VALUE_MID; + uint8_t IDD_VALUE_LSB; + uint8_t IDD_CAL_OFFSET_MSB; + uint8_t IDD_CAL_OFFSET_LSB; + uint8_t IDD_SHUNT_USED; +}IDD_dbgTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Constants + * @{ + */ + + /** + * @brief MFX COMMON defines + */ + + /** + * @brief Register address: chip IDs (R) + */ +#define MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00) + /** + * @brief Register address: chip FW_VERSION (R) + */ +#define MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01) +#define MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00) + /** + * @brief Register address: System Control Register (R/W) + */ +#define MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40) + /** + * @brief Register address: Vdd monitoring (R) + */ +#define MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06) +#define MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07) + /** + * @brief Register address: Error source + */ +#define MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03) + /** + * @brief Register address: Error Message + */ +#define MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04) + + /** + * @brief Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear + */ +#define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41) + /** + * @brief Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal + */ +#define MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42) + /** + * @brief Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason + */ +#define MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08) + /** + * @brief Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register + */ +#define MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44) + + /** + * @brief MFXSTM32L152_REG_ADR_ID choices + */ +#define MFXSTM32L152_ID_1 ((uint8_t)0x7B) +#define MFXSTM32L152_ID_2 ((uint8_t)0x79) + + /** + * @brief MFXSTM32L152_REG_ADR_SYS_CTRL choices + */ +#define MFXSTM32L152_SWRST ((uint8_t)0x80) +#define MFXSTM32L152_STANDBY ((uint8_t)0x40) +#define MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/ +#define MFXSTM32L152_IDD_EN ((uint8_t)0x04) +#define MFXSTM32L152_TS_EN ((uint8_t)0x02) +#define MFXSTM32L152_GPIO_EN ((uint8_t)0x01) + + /** + * @brief MFXSTM32L152_REG_ADR_ERROR_SRC choices + */ +#define MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */ +#define MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */ +#define MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */ + + /** + * @brief MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices + */ +#define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00) +#define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01) +#define MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00) +#define MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02) + + /** + * @brief REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices + */ +#define MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/ +#define MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/ +#define MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/ +#define MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/ +#define MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/ +#define MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */ +#define MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */ +#define MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */ +#define MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */ +#define MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF ) + + + /** + * @brief GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided + */ + + /** + * @brief Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output. + */ +#define MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain. + * If GPIO in input: (0) input without pull resistor, (1) input with pull resistor. + */ +#define MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude + */ +#define MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level. + */ +#define MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level. + */ +#define MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO STATE (R): Give state of the GPIO pin. + */ +#define MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */ + + /** + * @brief GPIO IRQ_GPIs + */ +/* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */ +/* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too */ + /** + * @brief GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1). + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge. + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */ + + + /** + * @brief GPIO: IO Pins definition + */ +#define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) +#define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) +#define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) +#define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) +#define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) +#define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) +#define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) +#define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) + +#define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) +#define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) +#define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) +#define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) +#define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) +#define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) +#define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) +#define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) + +#define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) +#define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) +#define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) +#define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) +#define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) +#define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) +#define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) +#define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) + +#define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 +#define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 +#define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 +#define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 +#define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 +#define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 +#define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 +#define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 + +#define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) + + /** + * @brief GPIO: constant + */ +#define MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0) +#define MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1) +#define MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0) +#define MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1) +#define MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */ +#define MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */ +#define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0) +#define MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1) +#define MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0) +#define MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1) +#define MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0) +#define MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1) + + + /** + * @brief TOUCH SCREEN Registers + */ + + /** + * @brief Touch Screen Registers + */ +#define MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0) +#define MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1) +#define MFXSTM32L152_TS_AVE ((uint8_t)0xA2) +#define MFXSTM32L152_TS_TRACK ((uint8_t)0xA3) +#define MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4) +#define MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20) +#define MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21) +#define MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24) + + /** + * @brief TS registers masks + */ +#define MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08) +#define MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80) + + +/** + * @brief Register address: Idd control register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80) + +/** + * @brief Register address: Idd pre delay register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81) + +/** + * @brief Register address: Idd Shunt registers (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B) + +/** + * @brief Register address: Idd ampli gain register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C) +#define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D) + +/** + * @brief Register address: Idd VDD min register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E) +#define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F) + +/** + * @brief Register address: Idd value register (R) + */ +#define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14) +#define MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15) +#define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16) + +/** + * @brief Register address: Idd calibration offset register (R) + */ +#define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18) +#define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19) + +/** + * @brief Register address: Idd shunt used offset register (R) + */ +#define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A) + +/** + * @brief Register address: shunt stabilisation delay registers (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90) +#define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91) +#define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92) +#define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93) +#define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94) + +/** + * @brief Register address: Idd number of measurements register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96) + +/** + * @brief Register address: Idd delta delay between 2 measurements register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97) + +/** + * @brief Register address: Idd number of shunt on board register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98) + + + +/** @defgroup IDD_Control_Register_Defines IDD Control Register Defines + * @{ + */ +/** + * @brief IDD control register masks + */ +#define MFXSTM32L152_IDD_CTRL_REQ ((uint8_t)0x01) +#define MFXSTM32L152_IDD_CTRL_SHUNT_NB ((uint8_t)0x0E) +#define MFXSTM32L152_IDD_CTRL_VREF_DIS ((uint8_t)0x40) +#define MFXSTM32L152_IDD_CTRL_CAL_DIS ((uint8_t)0x80) + +/** + * @brief IDD Shunt Number + */ +#define MFXSTM32L152_IDD_SHUNT_NB_1 ((uint8_t) 0x01) +#define MFXSTM32L152_IDD_SHUNT_NB_2 ((uint8_t) 0x02) +#define MFXSTM32L152_IDD_SHUNT_NB_3 ((uint8_t) 0x03) +#define MFXSTM32L152_IDD_SHUNT_NB_4 ((uint8_t) 0x04) +#define MFXSTM32L152_IDD_SHUNT_NB_5 ((uint8_t) 0x05) + +/** + * @brief Vref Measurement + */ +#define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_ENABLE ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_DISABLE ((uint8_t) 0x70) + +/** + * @brief IDD Calibration + */ +#define MFXSTM32L152_IDD_AUTO_CALIBRATION_ENABLE ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_AUTO_CALIBRATION_DISABLE ((uint8_t) 0x80) +/** + * @} + */ + +/** @defgroup IDD_PreDelay_Defines IDD PreDelay Defines + * @{ + */ +/** + * @brief IDD PreDelay masks + */ +#define MFXSTM32L152_IDD_PREDELAY_UNIT ((uint8_t) 0x80) +#define MFXSTM32L152_IDD_PREDELAY_VALUE ((uint8_t) 0x7F) + + +/** + * @brief IDD PreDelay unit + */ +#define MFXSTM32L152_IDD_PREDELAY_0_5_MS ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_PREDELAY_20_MS ((uint8_t) 0x80) +/** + * @} + */ + +/** @defgroup IDD_DeltaDelay_Defines IDD Delta DElay Defines + * @{ + */ +/** + * @brief IDD Delta Delay masks + */ +#define MFXSTM32L152_IDD_DELTADELAY_UNIT ((uint8_t) 0x80) +#define MFXSTM32L152_IDD_DELTADELAY_VALUE ((uint8_t) 0x7F) + + +/** + * @brief IDD Delta Delay unit + */ +#define MFXSTM32L152_IDD_DELTADELAY_0_5_MS ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_DELTADELAY_20_MS ((uint8_t) 0x80) + + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Functions + * @{ + */ + +/** + * @brief MFXSTM32L152 Control functions + */ +void mfxstm32l152_Init(uint16_t DeviceAddr); +void mfxstm32l152_DeInit(uint16_t DeviceAddr); +void mfxstm32l152_Reset(uint16_t DeviceAddr); +uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr); +uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr); +void mfxstm32l152_LowPower(uint16_t DeviceAddr); +void mfxstm32l152_WakeUp(uint16_t DeviceAddr); + +void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source); +void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source); +uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source); +void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source); + +void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity); +void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type); + + +/** + * @brief MFXSTM32L152 IO functionalities functions + */ +void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin); +uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode); +void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState); +uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin); +void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr); +uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin); +void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin); + +void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction); +void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr); +void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr); +void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type); +void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt); +void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); +void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); + +/** + * @brief MFXSTM32L152 Touch screen functionalities functions + */ +void mfxstm32l152_TS_Start(uint16_t DeviceAddr); +uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr); +void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y); +void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr); +uint8_t mfxstm32l152_TS_ITStatus (uint16_t DeviceAddr); +void mfxstm32l152_TS_ClearIT (uint16_t DeviceAddr); + +/** + * @brief MFXSTM32L152 IDD current measurement functionalities functions + */ +void mfxstm32l152_IDD_Start(uint16_t DeviceAddr); +void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig); +void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit); +void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue); +uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr); +void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr); +uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr); +void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr); + +/** + * @brief MFXSTM32L152 Error management functions + */ +uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr); +uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr); +void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr); +uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr); +void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr); + +uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr); +void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value); + + + +/** + * @brief iobus prototypes (they should be defined in common/stm32_iobus.h) + */ +void MFX_IO_Init(void); +void MFX_IO_DeInit(void); +void MFX_IO_ITConfig (void); +void MFX_IO_EnableWakeupPin(void); +void MFX_IO_Wakeup(void); +void MFX_IO_Delay(uint32_t delay); +void MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value); +uint8_t MFX_IO_Read(uint16_t addr, uint8_t reg); +uint16_t MFX_IO_ReadMultiple(uint16_t addr, uint8_t reg, uint8_t *buffer, uint16_t length); + +/** + * @} + */ + +/* Touch screen driver structure */ +extern TS_DrvTypeDef mfxstm32l152_ts_drv; + +/* IO driver structure */ +extern IO_DrvTypeDef mfxstm32l152_io_drv; + +/* IDD driver structure */ +extern IDD_DrvTypeDef mfxstm32l152_idd_drv; + + +#ifdef __cplusplus +} +#endif +#endif /* __MFXSTM32L152_H */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c new file mode 100644 index 0000000000..ca31b0aa47 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-15 thread-liu first version + */ + +#include "board.h" + +#if defined(BSP_USING_SPI1) +#include <drv_spi.h> + +#define SPI_NAME "spi1" +#define SPI_DEVICE_NAME "spi10" +static struct rt_spi_device *spi_dev = RT_NULL; + +/* attach spi1 device */ +static int rt_spi_device_init(void) +{ + struct rt_spi_configuration cfg; + + rt_hw_spi_device_attach(SPI_NAME, SPI_DEVICE_NAME, NULL, NULL); + + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS; + cfg.max_hz = 1 *1000 *1000; + + spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME); + + if (RT_NULL == spi_dev) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME); + return RT_ERROR; + } + + rt_spi_configure(spi_dev, &cfg); + + return RT_EOK; +} +INIT_APP_EXPORT(rt_spi_device_init); + +/* spi5 loopback mode test case */ +static int spi_sample(int argc, char **argv) +{ + rt_uint8_t t_buf[8], r_buf[8]; + int i = 0; + static struct rt_spi_message msg1; + + if (argc != 9) + { + rt_kprintf("Usage:\n"); + rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n"); + return -RT_ERROR; + } + + for (i = 0; i < 8; i++) + { + t_buf[i] = atoi(argv[i+1]); + } + + msg1.send_buf = &t_buf; + msg1.recv_buf = &r_buf; + msg1.length = sizeof(t_buf); + msg1.cs_take = 1; + msg1.cs_release = 0; + msg1.next = RT_NULL; + + rt_spi_transfer_message(spi_dev, &msg1); + + rt_kprintf("spi rbuf : "); + for (i = 0; i < sizeof(t_buf); i++) + { + rt_kprintf("%x ", r_buf[i]); + } + + rt_kprintf("\nspi loopback mode test over!\n"); + + return RT_EOK; +} +MSH_CMD_EXPORT(spi_sample, spi loopback test); + +#endif /* BSP_USING_SPI5 */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c new file mode 100644 index 0000000000..fdbc721c8d --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-27 thread-liu first version + */ + +#include <board.h> + +#if defined(BSP_USING_TIM14) && defined(BSP_USING_ADC2) + +#include <rtthread.h> +#include <rtdevice.h> + +#define HWTIMER_DEV_NAME "timer14" +#define HWADC_DEV_NAME "adc2" +#define REFER_VOLTAGE 330 /* voltage reference */ +#define CONVERT_BITS (1 << 12) /* Conversion digit */ +#define ADC_DEV_CHANNEL 6 + +static rt_adc_device_t adc_dev = RT_NULL; + +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_uint32_t value = 0 , vol = 0; + + /* read adc value */ + value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + rt_kprintf("the value is :%d \n", value); + + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + + return 0; +} + +static int hwtimer_stop(void) +{ + rt_err_t ret = RT_EOK; + rt_device_t hw_dev = RT_NULL; + + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + ret = rt_device_close(hw_dev); + if (ret != RT_EOK) + { + rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + /* close adc channel */ + ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + + return ret; +} + +static int hwtimer_start(void) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; + rt_device_t hw_dev = RT_NULL; + + rt_hwtimer_mode_t mode; + + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + /* find adc dev */ + adc_dev = (rt_adc_device_t)rt_device_find(HWADC_DEV_NAME); + if (adc_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME); + return RT_ERROR; + } + + /* Open the device in read/write mode */ + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + /* Set the timeout callback function */ + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + /* Set the mode to periodic timer */ + mode = HWTIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + timeout_s.sec = 5; + timeout_s.usec = 0; + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + rt_thread_mdelay(3500); + + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + /* enable adc channel */ + ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + + return ret; +} + +static int tim_sample(int argc, char *argv[]) +{ + if (argc > 1) + { + if (!rt_strcmp(argv[1], "start")) + { + rt_kprintf("tim14 will start\n"); + hwtimer_start(); + return RT_EOK; + } + else if (!rt_strcmp(argv[1], "stop")) + { + hwtimer_stop(); + rt_kprintf("stop tim14 success!\n"); + return RT_EOK; + } + else + { + goto _exit; + } + } +_exit: + { + rt_kprintf("Usage:\n"); + rt_kprintf("tim_sample start - start TIM14 \n"); + rt_kprintf("tim_sample stop - stop TIM14 \n"); + } + + return RT_ERROR; +} +MSH_CMD_EXPORT(tim_sample, tim sample); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py index b1cad1d512..3daaf0c1db 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py +++ b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py @@ -23,7 +23,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + EXEC_PATH = r'D:\software\Embedded Workbench 8.3' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') diff --git a/bsp/stm32/stm32mp157a-st-ev1/template.uvoptx b/bsp/stm32/stm32mp157a-st-ev1/template.uvoptx index e3a94d45ec..69cfe32b14 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/template.uvoptx +++ b/bsp/stm32/stm32mp157a-st-ev1/template.uvoptx @@ -10,7 +10,7 @@ <aExt>*.s*; *.src; *.a*</aExt> <oExt>*.obj; *.o</oExt> <lExt>*.lib</lExt> - <tExt>*.txt; *.h; *.inc</tExt> + <tExt>*.txt; *.h; *.inc; *.md</tExt> <pExt>*.plm</pExt> <CppX>*.cpp</CppX> <nMigrate>0</nMigrate> @@ -125,7 +125,7 @@ <SetRegEntry> <Number>0</Number> <Key>ST-LINKIII-KEIL_SWO</Key> - <Name>-U066BFF343339415043223048 -O206 -SF10000 -C0 -A2 -I0 -HNlocalhost -HP7184 -P1 -N00("") -D00(00000000) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10050000 -FC1000 -FN0</Name> + <Name>-U0666FF343339415043182420 -O206 -SF10000 -C0 -A2 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10030000 -FC1000 -FN0</Name> </SetRegEntry> </TargetDriverDllRegistry> <Breakpoint/> diff --git a/bsp/stm32/stm32mp157a-st-ev1/template.uvprojx b/bsp/stm32/stm32mp157a-st-ev1/template.uvprojx index fc88195dc1..db224b3468 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/template.uvprojx +++ b/bsp/stm32/stm32mp157a-st-ev1/template.uvprojx @@ -276,7 +276,7 @@ <OCR_RVCT4> <Type>1</Type> <StartAddress>0x10000000</StartAddress> - <Size>0x40000</Size> + <Size>0x30000</Size> </OCR_RVCT4> <OCR_RVCT5> <Type>1</Type> @@ -300,13 +300,13 @@ </OCR_RVCT8> <OCR_RVCT9> <Type>0</Type> - <StartAddress>0x10050000</StartAddress> + <StartAddress>0x10030000</StartAddress> <Size>0x10000</Size> </OCR_RVCT9> <OCR_RVCT10> <Type>0</Type> - <StartAddress>0x0</StartAddress> - <Size>0x0</Size> + <StartAddress>0x10040000</StartAddress> + <Size>0x20000</Size> </OCR_RVCT10> </OnChipMemories> <RvctStartVector></RvctStartVector> @@ -397,11 +397,6 @@ <Layers> <Layer> <LayName><Project Info></LayName> - <LayDesc></LayDesc> - <LayUrl></LayUrl> - <LayKeys></LayKeys> - <LayCat></LayCat> - <LayLic></LayLic> <LayTarg>0</LayTarg> <LayPrjMark>1</LayPrjMark> </Layer> |