diff options
| author | xinyi.gao <[email protected]> | 2023-04-11 17:16:22 +0800 |
|---|---|---|
| committer | Man, Jianting (Meco) <[email protected]> | 2023-04-15 10:01:10 -0400 |
| commit | 61c239b6f014b7525d0ed46042c5a26c4cd823aa (patch) | |
| tree | 36e98e29fbf199522da3b2168196ff553e5657ed /bsp | |
| parent | b2f282545604e60804daf8b353af9471f0303fe3 (diff) | |
[nxp][imxrt1060] add link script files
Diffstat (limited to 'bsp')
25 files changed, 1196 insertions, 296 deletions
diff --git a/bsp/imxrt/imxrt1021-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1021-nxp-evk/applications/main.c index 3f65f3378a..dfd64114e6 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/applications/main.c +++ b/bsp/imxrt/imxrt1021-nxp-evk/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1021-nxp-evk/board/Kconfig index 117f98683b..4e7ad9aad1 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/Kconfig @@ -143,6 +143,9 @@ menu "On-chip Peripheral Drivers" bool "Enable RTC" select RT_USING_RTC default n + config BSP_USING_CACHE + bool "Enable CACHE" + default n endmenu @@ -188,6 +191,43 @@ menu "Onboard Peripheral Drivers" bool "Enable RS485" select BSP_USING_LPUART5 default n + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_USING_KSZ8081 + bool "i.MX RT1020EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_KSZ8081_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_RESET_KSZ8081_PORT + int "indicate port of reset" + default 1 + + config PHY_RESET_KSZ8081_PIN + int "indicate pin of reset" + default 4 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + endif + endif endmenu diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/board.c b/bsp/imxrt/imxrt1021-nxp-evk/board/board.c index fcfc532ec1..365c0acb94 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> #include "board.h" #include "pin_mux.h" - +#include "fsl_iomuxc.h" #ifdef BSP_USING_DMA #include "fsl_dmamux.h" #include "fsl_edma.h" @@ -168,6 +168,221 @@ void imxrt_dma_init(void) EDMA_Init(DMA0, &config); } #endif +#ifdef BSP_USING_ETH +void imxrt_enet_pins_init(void) +{ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 is configured as GPIO1_IO04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, /* GPIO_AD_B0_08 is configured as ENET_REF_CLK1 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B0_08 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, /* GPIO_AD_B0_09 is configured as ENET_RDATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, /* GPIO_AD_B0_10 is configured as ENET_RDATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, /* GPIO_AD_B0_11 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, /* GPIO_AD_B0_12 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, /* GPIO_AD_B0_13 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, /* GPIO_AD_B0_14 is configured as ENET_TDATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, /* GPIO_AD_B0_15 is configured as ENET_TDATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, /* GPIO_AD_B1_06 is configured as GPIO1_IO22 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDIO, /* GPIO_EMC_40 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDC, /* GPIO_EMC_41 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 PAD functional properties : */ + 0xB0A9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, /* GPIO_AD_B0_08 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, /* GPIO_AD_B0_11 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, /* GPIO_AD_B0_12 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, /* GPIO_AD_B0_13 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, /* GPIO_AD_B0_14 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, /* GPIO_AD_B0_15 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, /* GPIO_AD_B1_06 PAD functional properties : */ + 0xB0A9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDIO, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDC, /* GPIO_EMC_41 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +} + +#ifndef BSP_USING_PHY +void imxrt_enet_phy_reset_by_gpio(void) +{ + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + GPIO_PinInit(GPIO1, 9, &gpio_config); + GPIO_PinInit(GPIO1, 10, &gpio_config); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 10, 1); + GPIO_WritePinOutput(GPIO1, 9, 0); + rt_thread_delay(100); + GPIO_WritePinOutput(GPIO1, 9, 1); +} +#endif /* BSP_USING_PHY */ + +#endif /* BSP_USING_ETH */ + +#ifdef BSP_USING_PHY +void imxrt_phy_pins_init( void ) +{ +// IOMUXC_SetPinMux( +// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ +// 0U); /* Software Input On Field: Input Path is determined by functionality */ +// IOMUXC_SetPinConfig( +// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_B0_00 PAD functional properties : */ +// 0x10B0u); /* Slew Rate Field: Slow Slew Rate +// Drive Strength Field: R0/6 +// Speed Field: medium(100MHz) +// Open Drain Enable Field: Open Drain Disabled +// Pull / Keep Enable Field: Pull/Keeper Enabled +// Pull / Keep Select Field: Keeper +// Pull Up / Down Config. Field: 100K Ohm Pull Down +// Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_B0_00 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +} +#endif /* BSP_USING_PHY */ + + + + /** * This function will initial rt1050 board. */ @@ -184,6 +399,13 @@ void rt_hw_board_init() imxrt_dma_init(); #endif +#ifdef BSP_USING_ETH + imxrt_enet_pins_init(); +#endif + +#ifdef BSP_USING_PHY + imxrt_phy_pins_init(); +#endif #ifdef RT_USING_HEAP rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif diff --git a/bsp/imxrt/imxrt1021-nxp-evk/board/board.h b/bsp/imxrt/imxrt1021-nxp-evk/board/board.h index 49aa4f17b8..161d9fcb0e 100644 --- a/bsp/imxrt/imxrt1021-nxp-evk/board/board.h +++ b/bsp/imxrt/imxrt1021-nxp-evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/demo/lv_demo.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/demo/lv_demo.c index 77bdc0ac47..fd30e46f96 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/demo/lv_demo.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/demo/lv_demo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_init_thread.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_init_thread.c index 613dd7d198..75e5f0c9c0 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_init_thread.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_init_thread.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_disp.h b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_disp.h index 500dcb1d24..2183bfe7a4 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_disp.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_disp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_indev.h b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_indev.h index 17c68c5661..86bdf483e1 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_indev.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/legacy/lv_port_indev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/ui/lv_ui_entry.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/ui/lv_ui_entry.c index 27c20fbc53..bec1656815 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/ui/lv_ui_entry.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/guiguider/ui/lv_ui_entry.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_conf.h b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_conf.h index 37dc49bdd5..0fde004307 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_conf.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_conf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_disp.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_disp.c index 9417b11d63..0e6f90166e 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_disp.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_disp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_indev.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_indev.c index 0f3948cbf3..9768e48470 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_indev.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/lvgl/lv_port_indev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * Copyright 2022 NXP * * SPDX-License-Identifier: Apache-2.0 diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c index c8a1cd7636..bccdbf80e1 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c index 61ff49968e..c3dc1f74d3 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c @@ -37,276 +37,276 @@ output_format: c_array * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ const uint8_t dcd_data[] = { - /* HEADER */ - /* Tag */ - 0xD2, - /* Image Length */ - 0x04, 0x10, - /* Version */ - 0x41, + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, - /* COMMANDS */ + /* COMMANDS */ - /* group: 'Imported Commands' */ - /* #1.1-113, command header bytes for merged 'Write - value' command */ - 0xCC, 0x03, 0x8C, 0x04, - /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ - 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, - /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ - 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, - /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ - 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, - /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, - /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, - /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, - /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, - /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, - /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, - /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, - /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, - /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, - /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, - /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, - /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, - /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, - /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, - /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, - /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, - /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, - /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, - /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, - /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, - /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, - /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, - /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, - /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, - /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, - /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, - /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, - /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, - /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, - /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, - /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, - /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, - /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, - /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, - /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, - /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, - /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, - /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, - /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ - 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, - /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, - /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, - /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, - /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, - /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, - /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, - /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, - /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, - /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, - /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, - /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, - /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, - /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, - /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, - /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, - /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, - /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, - /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, - /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, - /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, - /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, - /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, - /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, - /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, - /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, - /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, - /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, - /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, - /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, - /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, - /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, - /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, - /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, - /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, - /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, - /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, - /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, - /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, - /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, - /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, - /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ - 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, - /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ - 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, - /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ - 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, - /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, - /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, - /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, - /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, - /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ - 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, - /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ - 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, - /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ - 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, - /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, - /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, - /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ - 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, - /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ - 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, - /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ - 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, - /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ - 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, - /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ - 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, - /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, - /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ - 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, - /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ - 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, - /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ - 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, - /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #3.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #5.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #7.1-3, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x1C, 0x04, - /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ - 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, - /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, - /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ - 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 - }; + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 + }; /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ #else diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/pin_mux.c b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/pin_mux.c index b843c47b6e..29fc682139 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/pin_mux.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/pin_mux.c @@ -105,8 +105,8 @@ void BOARD_InitPins(void) { IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO_AD_B0_02 is configured as GPIO1_IO02 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, /* GPIO_AD_B0_02 is configured as GPIO1_IO02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, /* GPIO_AD_B0_02 is configured as GPIO1_IO02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -187,15 +187,15 @@ void BOARD_InitPins(void) { Pull Up / Down Config. Field: 100K Ohm Pull Down Hyst. Enable Field: Hysteresis Disabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, /* GPIO_AD_B0_11 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate + IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, /* GPIO_AD_B0_11 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: R0/6 Speed Field: medium(100MHz) Open Drain Enable Field: Open Drain Disabled Pull / Keep Enable Field: Pull/Keeper Enabled Pull / Keep Select Field: Keeper Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ + Hyst. Enable Field: Hysteresis Disabled */ IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ 0x10B0u); /* Slew Rate Field: Slow Slew Rate diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/board.c b/bsp/imxrt/imxrt1060-nxp-evk/board/board.c index 7789888922..d837d6965f 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/board.h b/bsp/imxrt/imxrt1060-nxp-evk/board/board.h index 35fd056322..3451e733c8 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/board.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.sct b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.sct new file mode 100644 index 0000000000..f1393bfb83 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.sct @@ -0,0 +1,82 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1062CVJ5A +** MIMXRT1062CVL5A +** MIMXRT1062DVJ6A +** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0001FC00 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_data2_start 0x20200000 +#define m_data2_size 0x000C0000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x2000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x2000 +#endif +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (CodeQuickAccess) + .ANY (+RO) + } + VECTOR_RAM m_interrupts_start EMPTY 0 { + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + * (NonCacheable.init) + * (*NonCacheable) + * (DataQuickAccess) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + RW_m_ncache m_data2_start EMPTY 0 { + } + RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration + } +} diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram.icf b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram.icf new file mode 100644 index 0000000000..4a5478e35d --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram.icf @@ -0,0 +1,101 @@ +/* +** ################################################################### +** Processors: MIMXRT1062CVJ5A +** MIMXRT1062CVL5A +** MIMXRT1062DVJ6A +** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0001FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x202BFFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; +define exported symbol __RTT_HEAP_END = m_data2_end; +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; + +initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in DATA3_region { last block HEAP }; +} +place in NCACHE_region { block NCACHE_VAR }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block QACCESS_DATA }; +place in CSTACK_region { block CSTACK }; diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram.sct b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram.sct new file mode 100644 index 0000000000..c27b355db3 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram.sct @@ -0,0 +1,107 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1062CVJ5A +** MIMXRT1062CVL5A +** MIMXRT1062DVJ6A +** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0001FC00 + +#define m_data_start 0x80000000 +#define m_data_size 0x01E00000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00020000 + +#define m_data3_start 0x20200000 +#define m_data3_size 0x000C0000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (CodeQuickAccess) + .ANY (+RO) + } + VECTOR_RAM m_interrupts_start EMPTY 0 { + } +#if (defined(__heap_noncacheable__)) + RW_m_data m_data_start m_data_size-Stack_Size { ; RW data +#else + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data +#endif + .ANY (+RW +ZI) + * (*m_usb_dma_init_data) + * (*m_usb_dma_noninit_data) + } +#if (!defined(__heap_noncacheable__)) + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } +#endif + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + RW_m_data2 m_data2_start m_data2_size { ; + * (DataQuickAccess) + } +#if (defined(__heap_noncacheable__)) + RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data +#else + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data +#endif + * (NonCacheable.init) + * (*NonCacheable) + } +#if (defined(__heap_noncacheable__)) + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration +#else + RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration +#endif + } +} diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/ports/sdram_port.h b/bsp/imxrt/imxrt1060-nxp-evk/board/ports/sdram_port.h index eacb963fe1..35f4ac2d7b 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/ports/sdram_port.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/evkmimxrt1060_ram.ini b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/evkmimxrt1060_ram.ini new file mode 100644 index 0000000000..7eccf48374 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/evkmimxrt1060_ram.ini @@ -0,0 +1,89 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _loadDcdcTrim(void) +{ + unsigned int dcdc_trim_loaded; + unsigned long ocotp_base; + unsigned long ocotp_fuse_bank0_base; + unsigned long dcdc_base; + unsigned long reg; + unsigned long trim_value; + unsigned int index; + + ocotp_base = 0x401F4000; + ocotp_fuse_bank0_base = ocotp_base + 0x400; + dcdc_base = 0x40080000; + + dcdc_trim_loaded = 0; + + reg = _RDWORD(ocotp_fuse_bank0_base + 0x90); + if (reg & (1<<10)) + { + // DCDC: REG0->VBG_TRM + trim_value = (reg & (0x1F << 11)) >> 11; + reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24); + _WDWORD(dcdc_base + 0x4, reg); + dcdc_trim_loaded = 1; + } + + reg = _RDWORD(ocotp_fuse_bank0_base + 0x80); + if (reg & (1<<30)) + { + index = (reg & (3 << 28)) >> 28; + if (index < 4) + { + // DCDC: REG3->TRG + reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index)); + _WDWORD(dcdc_base + 0xC, reg); + dcdc_trim_loaded = 1; + } + } + + if (dcdc_trim_loaded) + { + // delay about 400us till dcdc is stable. + _Sleep_(1); + } +} + +FUNC void restoreFlexRAM(void) +{ + unsigned int value; + unsigned int base; + + base = 0x400AC000; + + value = _RDWORD(base + 0x44); + value &= ~(0xFFFFFFFF); + value |= 0x55AFFA55; + _WDWORD(base + 0x44, value); + + value = _RDWORD(base + 0x40); + value |= (1 << 2); + _WDWORD(base + 0x40, value); +} + +FUNC void Setup (void) { + _loadDcdcTrim(); + SP = _RDWORD(0x00000000); // Setup Stack Pointer + PC = _RDWORD(0x00000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register +} + +FUNC void OnResetExec (void) { // executes upon software RESET + restoreFlexRAM(); + Setup(); // Setup for Running +} + +restoreFlexRAM(); + +LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +// g, main diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/evkmimxrt1060_sdram_init.ini b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/evkmimxrt1060_sdram_init.ini new file mode 100644 index 0000000000..ad36a2e157 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/evkmimxrt1060_sdram_init.ini @@ -0,0 +1,256 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _loadDcdcTrim(void) +{ + unsigned int dcdc_trim_loaded; + unsigned long ocotp_base; + unsigned long ocotp_fuse_bank0_base; + unsigned long dcdc_base; + unsigned long reg; + unsigned long trim_value; + unsigned int index; + + ocotp_base = 0x401F4000; + ocotp_fuse_bank0_base = ocotp_base + 0x400; + dcdc_base = 0x40080000; + + dcdc_trim_loaded = 0; + + reg = _RDWORD(ocotp_fuse_bank0_base + 0x90); + if (reg & (1<<10)) + { + // DCDC: REG0->VBG_TRM + trim_value = (reg & (0x1F << 11)) >> 11; + reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24); + _WDWORD(dcdc_base + 0x4, reg); + dcdc_trim_loaded = 1; + } + + reg = _RDWORD(ocotp_fuse_bank0_base + 0x80); + if (reg & (1<<30)) + { + index = (reg & (3 << 28)) >> 28; + if (index < 4) + { + // DCDC: REG3->TRG + reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index)); + _WDWORD(dcdc_base + 0xC, reg); + dcdc_trim_loaded = 1; + } + } + + if (dcdc_trim_loaded) + { + // delay about 400us till dcdc is stable. + _Sleep_(1); + } +} + +FUNC void SDRAM_WaitIpCmdDone(void) +{ + unsigned long reg; + do + { + reg = _RDWORD(0x402F003C); + }while((reg & 0x3) == 0); + + _WDWORD(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits +} + +FUNC void _clock_init(void) +{ + unsigned int reg; + // Enable all clocks + _WDWORD(0x400FC068,0xffffffff); + _WDWORD(0x400FC06C,0xffffffff); + _WDWORD(0x400FC070,0xffffffff); + _WDWORD(0x400FC074,0xffffffff); + _WDWORD(0x400FC078,0xffffffff); + _WDWORD(0x400FC07C,0xffffffff); + _WDWORD(0x400FC080,0xffffffff); + + // PERCLK_PODF: 1 divide by 2 + _WDWORD(0x400FC01C, 0x04900001); + // Enable SYS PLL but keep it bypassed. + _WDWORD(0x400D8030, 0x00012001); + do + { + reg = _RDWORD(0x400D8030); + }while((reg & 0x80000000) == 0); + // Disable bypass of SYS PLL + _WDWORD(0x400D8030, 0x00002001); + + // PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327 + // Ungate SYS PLL PFD2 + reg = _RDWORD(0x400D8100); + reg &= ~0xBF0000; + reg |= 0x1D0000; + _WDWORD(0x400D8100,reg); + + // SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01 + // SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2 + // SEMC_CLK_SEL: 1 SEMC_ALT_CLK + _WDWORD(0x400FC014, 0x00010D40); +} + +FUNC void _sdr_Init(void) +{ + // Config IOMUX + _WDWORD(0x401F8014, 0x00000000); + _WDWORD(0x401F8018, 0x00000000); + _WDWORD(0x401F801C, 0x00000000); + _WDWORD(0x401F8020, 0x00000000); + _WDWORD(0x401F8024, 0x00000000); + _WDWORD(0x401F8028, 0x00000000); + _WDWORD(0x401F802C, 0x00000000); + _WDWORD(0x401F8030, 0x00000000); + _WDWORD(0x401F8034, 0x00000000); + _WDWORD(0x401F8038, 0x00000000); + _WDWORD(0x401F803C, 0x00000000); + _WDWORD(0x401F8040, 0x00000000); + _WDWORD(0x401F8044, 0x00000000); + _WDWORD(0x401F8048, 0x00000000); + _WDWORD(0x401F804C, 0x00000000); + _WDWORD(0x401F8050, 0x00000000); + _WDWORD(0x401F8054, 0x00000000); + _WDWORD(0x401F8058, 0x00000000); + _WDWORD(0x401F805C, 0x00000000); + _WDWORD(0x401F8060, 0x00000000); + _WDWORD(0x401F8064, 0x00000000); + _WDWORD(0x401F8068, 0x00000000); + _WDWORD(0x401F806C, 0x00000000); + _WDWORD(0x401F8070, 0x00000000); + _WDWORD(0x401F8074, 0x00000000); + _WDWORD(0x401F8078, 0x00000000); + _WDWORD(0x401F807C, 0x00000000); + _WDWORD(0x401F8080, 0x00000000); + _WDWORD(0x401F8084, 0x00000000); + _WDWORD(0x401F8088, 0x00000000); + _WDWORD(0x401F808C, 0x00000000); + _WDWORD(0x401F8090, 0x00000000); + _WDWORD(0x401F8094, 0x00000000); + _WDWORD(0x401F8098, 0x00000000); + _WDWORD(0x401F809C, 0x00000000); + _WDWORD(0x401F80A0, 0x00000000); + _WDWORD(0x401F80A4, 0x00000000); + _WDWORD(0x401F80A8, 0x00000000); + _WDWORD(0x401F80AC, 0x00000000); + _WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION + + // PAD ctrl + // drive strength = 0x7 to increase drive strength + // otherwise the data7 bit may fail. + _WDWORD(0x401F8204, 0x000110F9); + _WDWORD(0x401F8208, 0x000110F9); + _WDWORD(0x401F820C, 0x000110F9); + _WDWORD(0x401F8210, 0x000110F9); + _WDWORD(0x401F8214, 0x000110F9); + _WDWORD(0x401F8218, 0x000110F9); + _WDWORD(0x401F821C, 0x000110F9); + _WDWORD(0x401F8220, 0x000110F9); + _WDWORD(0x401F8224, 0x000110F9); + _WDWORD(0x401F8228, 0x000110F9); + _WDWORD(0x401F822C, 0x000110F9); + _WDWORD(0x401F8230, 0x000110F9); + _WDWORD(0x401F8234, 0x000110F9); + _WDWORD(0x401F8238, 0x000110F9); + _WDWORD(0x401F823C, 0x000110F9); + _WDWORD(0x401F8240, 0x000110F9); + _WDWORD(0x401F8244, 0x000110F9); + _WDWORD(0x401F8248, 0x000110F9); + _WDWORD(0x401F824C, 0x000110F9); + _WDWORD(0x401F8250, 0x000110F9); + _WDWORD(0x401F8254, 0x000110F9); + _WDWORD(0x401F8258, 0x000110F9); + _WDWORD(0x401F825C, 0x000110F9); + _WDWORD(0x401F8260, 0x000110F9); + _WDWORD(0x401F8264, 0x000110F9); + _WDWORD(0x401F8268, 0x000110F9); + _WDWORD(0x401F826C, 0x000110F9); + _WDWORD(0x401F8270, 0x000110F9); + _WDWORD(0x401F8274, 0x000110F9); + _WDWORD(0x401F8278, 0x000110F9); + _WDWORD(0x401F827C, 0x000110F9); + _WDWORD(0x401F8280, 0x000110F9); + _WDWORD(0x401F8284, 0x000110F9); + _WDWORD(0x401F8288, 0x000110F9); + _WDWORD(0x401F828C, 0x000110F9); + _WDWORD(0x401F8290, 0x000110F9); + _WDWORD(0x401F8294, 0x000110F9); + _WDWORD(0x401F8298, 0x000110F9); + _WDWORD(0x401F829C, 0x000110F9); + _WDWORD(0x401F82A0, 0x000110F9); + + // Config SDR Controller Registers/ + _WDWORD(0x402F0000,0x10000004); // MCR + _WDWORD(0x402F0008,0x00000081); // BMCR0 + _WDWORD(0x402F000C,0x00000081); // BMCR1 + _WDWORD(0x402F0010,0x8000001B); // BR0, 32MB + + _WDWORD(0x402F0040,0x00000F31); // SDRAMCR0 + _WDWORD(0x402F0044,0x00652922); // SDRAMCR1 + _WDWORD(0x402F0048,0x00010920); // SDRAMCR2 + _WDWORD(0x402F004C,0x50210A08); // SDRAMCR3 + + _WDWORD(0x402F0090,0x80000000); // IPCR0 + _WDWORD(0x402F0094,0x00000002); // IPCR1 + _WDWORD(0x402F0098,0x00000000); // IPCR2 + + + _WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F00A0,0x00000033); // IPTXDAT + _WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done. +} + +FUNC void restoreFlexRAM(void) +{ + unsigned int value; + unsigned int base; + + base = 0x400AC000; + + value = _RDWORD(base + 0x44); + value &= ~(0xFFFFFFFF); + value |= 0x55AFFA55; + _WDWORD(base + 0x44, value); + + value = _RDWORD(base + 0x40); + value |= (1 << 2); + _WDWORD(base + 0x40, value); +} + +FUNC void Setup (void) { + _loadDcdcTrim(); + SP = _RDWORD(0x00000000); // Setup Stack Pointer + PC = _RDWORD(0x00000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register +} + +FUNC void OnResetExec (void) { // executes upon software RESET + restoreFlexRAM(); + _clock_init(); + _sdr_Init(); + Setup(); // Setup for Running +} + +restoreFlexRAM(); +_clock_init(); +_sdr_Init(); + +LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +// g, main diff --git a/bsp/imxrt/libraries/drivers/drv_eth.c b/bsp/imxrt/libraries/drivers/drv_eth.c index c58e7eb312..dbe95d2410 100644 --- a/bsp/imxrt/libraries/drivers/drv_eth.c +++ b/bsp/imxrt/libraries/drivers/drv_eth.c @@ -239,6 +239,9 @@ static void _enet_clk_init(void) // IOMUXC_GPR->GPR1 |= 1 << 23; /* Set 50MHz output clock required by PHY. */ const clock_enet_pll_config_t config = {.enableClkOutput = true, .loopDivider = 1}; +#if defined(SOC_IMXRT1020_SERIES) + const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput500M = true, .loopDivider = 1}; +#endif CLOCK_InitEnetPll(&config); /* Output 50M clock to PHY. */ diff --git a/bsp/imxrt/libraries/drivers/drv_gpio.c b/bsp/imxrt/libraries/drivers/drv_gpio.c index 975c5b26ba..96d1dbb118 100644 --- a/bsp/imxrt/libraries/drivers/drv_gpio.c +++ b/bsp/imxrt/libraries/drivers/drv_gpio.c @@ -519,7 +519,7 @@ void GPIO13_Combined_0_31_IRQHandler(void) rt_interrupt_leave(); } #endif -static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { gpio_pin_config_t gpio; rt_int8_t port, pin_num; @@ -622,7 +622,7 @@ static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) GPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio); } -static int imxrt_pin_read(rt_device_t dev, rt_base_t pin) +static rt_int8_t imxrt_pin_read(rt_device_t dev, rt_base_t pin) { int value; rt_int8_t port, pin_num; @@ -640,7 +640,7 @@ static int imxrt_pin_read(rt_device_t dev, rt_base_t pin) return GPIO_PinReadPadStatus(mask_tab[port].gpio, pin_num); } -static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) { rt_int8_t port, pin_num; @@ -656,8 +656,8 @@ static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) GPIO_PinWrite(mask_tab[port].gpio, pin_num, value); } -static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) +static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) { rt_base_t level; rt_int8_t port, pin_num; @@ -690,7 +690,7 @@ static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_int32_t pin, return RT_EOK; } -static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_base_t pin) { rt_base_t level; rt_int8_t port, pin_num; @@ -719,7 +719,7 @@ static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_int32_t pin) return RT_EOK; } -static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) { gpio_interrupt_mode_t int_mode; rt_int8_t port, pin_num, irq_index; |