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authorFan YANG <[email protected]>2024-08-12 17:08:11 +0800
committerRbb666 <[email protected]>2024-08-26 10:41:15 +0800
commit0b1ba0f6125ad68ff24fb064d5f8e6f6518acc4e (patch)
tree7450144b7e797dcdd4f67e1fc853cad355e9157c /bsp
parent6c085218a3efc54509e7d5e250b3eb890483834a (diff)
[bsp][hpmicro] add missing fence apis
- added missing fence apis Signed-off-by: Fan YANG <[email protected]>
Diffstat (limited to 'bsp')
-rw-r--r--bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h
index 4f95f4db9e..8cdaf95094 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h
+++ b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h
@@ -88,6 +88,18 @@ extern "C" {
#define fencei() __asm volatile("fence.i")
/**
+ * @brief execute fence rw
+ *
+ */
+#define fencerw() __asm volatile("fence rw, rw")
+
+/**
+ * @brief execute fence iorw
+ *
+ */
+#define fenceiorw() __asm volatile("fence iorw, iorw")
+
+/**
* @brief enable fpu
*/
#define enable_fpu() read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)