Merge branch 'master' of https://github.com/RT-Thread/rt-thread

7 files changed, 65 insertions, 19 deletions

diff --git a/bsp/frdm-k64f/SConstruct b/bsp/frdm-k64f/SConstruct
index d4132b593c..eb4f3d8eac 100644
--- a/bsp/frdm-k64f/SConstruct
+++ b/bsp/frdm-k64f/SConstruct
@@ -30,8 +30,5 @@ Export('rtconfig')
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-# build program 
-env.Program(TARGET, objs)
-
-# end building 
-EndBuilding(TARGET)
+# do building 
+DoBuilding(TARGET, objs)
diff --git a/bsp/stm32f40x/Libraries/SConscript b/bsp/stm32f40x/Libraries/SConscript
index d23856456a..c83c06b439 100644
--- a/bsp/stm32f40x/Libraries/SConscript
+++ b/bsp/stm32f40x/Libraries/SConscript
@@ -18,8 +18,8 @@ if rtconfig.CROSS_TOOL == 'gcc':
      src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f4xx.s']
 elif rtconfig.CROSS_TOOL == 'keil':
      src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s']
-# elif rtconfig.CROSS_TOOL == 'iar':
-    # src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/' + startup_scripts[rtconfig.STM32_TYPE]]
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s']
 
 path = [cwd + '/STM32F4xx_StdPeriph_Driver/inc', 
     cwd + '/CMSIS/ST/STM32F4xx/Include',
diff --git a/bsp/stm32f40x/readme.md b/bsp/stm32f40x/readme.md
new file mode 100644
index 0000000000..e1d0e56820
--- /dev/null
+++ b/bsp/stm32f40x/readme.md
@@ -0,0 +1,25 @@
+board info:
+STM32F4 discovery
+http://www.st.com/internet/evalboard/product/252419.jsp
+
+note:
+in drivers/stm32f4xx_conf.h
+ /* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
+ #define HSE_VALUE    ((uint32_t)8000000)
+ 
+ 
+ 
+ **================= IAR WARNING =================**
+ 
+ after use `scons --target=iar -s` cmd to product IAR project, you have to add iar link file by hand
+ 
+ IAR steps:
+ 1. Project-->Options-->Linker
+ 2. Config-->Linker Configuration file
+ 3. select `Override Default`, then select `bsp/stm32f40x/stm32f40x_flash.icf`
+ 4. rebuild project
+ 
+ 
+ **TODO**
+ auto add *.icf by scons script
+
diff --git a/bsp/stm32f40x/readme.txt b/bsp/stm32f40x/readme.txt
deleted file mode 100644
index 7bebe251c6..0000000000
--- a/bsp/stm32f40x/readme.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-board info:
-STM32F4 discovery
-http://www.st.com/internet/evalboard/product/252419.jsp
-
-note:
-in drivers/stm32f4xx_conf.h
- /* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
- #define HSE_VALUE    ((uint32_t)8000000)
-
diff --git a/bsp/stm32f40x/stm32f40x_flash.icf b/bsp/stm32f40x/stm32f40x_flash.icf
new file mode 100644
index 0000000000..8888d0e081
--- /dev/null
+++ b/bsp/stm32f40x/stm32f40x_flash.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2001FFFF; /*STM32 F446RE*/
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block CSTACK, last block HEAP};
diff --git a/bsp/stm32f7-disco/drivers/board.c b/bsp/stm32f7-disco/drivers/board.c
index 0553920a47..02f0acf2e6 100644
--- a/bsp/stm32f7-disco/drivers/board.c
+++ b/bsp/stm32f7-disco/drivers/board.c
@@ -25,7 +25,7 @@
 #include <rtthread.h>
 #include "board.h"
 #include "sram.h"
-
+#include "drv_mpu.h"
 
 /**
  * @addtogroup STM32
@@ -165,7 +165,7 @@ void HAL_ResumeTick(void)
 void rt_hw_board_init()
 {
     /* Configure the MPU attributes as Write Through */
-    //mpu_init();
+    mpu_init();
 
     /* Enable the CPU Cache */
     CPU_CACHE_Enable();
diff --git a/bsp/stm32f7-disco/drivers/drv_mpu.c b/bsp/stm32f7-disco/drivers/drv_mpu.c
index 630e48e2d2..ecf556203b 100644
--- a/bsp/stm32f7-disco/drivers/drv_mpu.c
+++ b/bsp/stm32f7-disco/drivers/drv_mpu.c
@@ -81,4 +81,4 @@ int mpu_init(void)
   HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
 	return 0;
 }
-INIT_BOARD_EXPORT(mpu_init);
+//INIT_BOARD_EXPORT(mpu_init);