diff options
| author | xjy <[email protected]> | 2023-06-21 21:59:30 +0800 |
|---|---|---|
| committer | guo <[email protected]> | 2023-06-21 22:50:22 +0800 |
| commit | a6024458ffc6c154278a1787542893d04cb69ca8 (patch) | |
| tree | 7dfd97436a41e223ec5b39d1111b5ece9635e20a /bsp | |
| parent | 878be62a0f0d595f7097c9c78b57b91c42904684 (diff) | |
add link file for iar project
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link_ram.icf | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link_ram.icf b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link_ram.icf new file mode 100644 index 0000000000..45f02d0390 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link_ram.icf @@ -0,0 +1,87 @@ +/*
+** ###################################################################
+** Processors: MIMXRT1176AVM8A_cm7
+** MIMXRT1176CVM8A_cm7
+** MIMXRT1176DVMAA_cm7
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1170RM, Rev 1, 02/2021
+** Version: rev. 1.1, 2022-04-02
+** Build: b220402
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2022 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: [email protected]
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x00002000;
+define symbol m_interrupts_end = 0x000023FF;
+
+define symbol m_text_start = 0x00002400;
+define symbol m_text_end = 0x0003FFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2003FFFF;
+
+define symbol m_data2_start = 0x202C0000;
+define symbol m_data2_end = 0x2033FFFF;
+
+define exported symbol __NCACHE_REGION_START = m_data2_start;
+define exported symbol __NCACHE_REGION_SIZE = 0x0;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __RTT_HEAP_END = m_data2_end;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE { section CodeQuickAccess };
+define block QACCESS_DATA { section DataQuickAccess };
+
+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in DATA_region { block NCACHE_VAR };
+place in TEXT_region { block QACCESS_CODE };
+place in DATA_region { block QACCESS_DATA };
+place in CSTACK_region { block CSTACK };
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