diff options
| author | bernard <[email protected]> | 2021-09-23 10:53:27 +0000 |
|---|---|---|
| committer | Gitee <[email protected]> | 2021-09-23 10:53:27 +0000 |
| commit | beff80638592d886f133f2a6d5d6aec4d78a6dce (patch) | |
| tree | 03c0a717f69f808ed882a678b827f4a849987a6f /bsp | |
| parent | d71e2ac5829925e8a9fc7203fda8830eeda44ecc (diff) | |
| parent | 29c79753dbc4ef1e1724f486d046c5c9ceb8248c (diff) | |
!324 添加 APM32F103ZE MINI 板 bsp
Merge pull request !324 from abbbcc/gitee_master
Diffstat (limited to 'bsp')
90 files changed, 39427 insertions, 0 deletions
diff --git a/bsp/apm32/apm32f103xe-minibroard/.config b/bsp/apm32/apm32f103xe-minibroard/.config new file mode 100644 index 0000000000..495e6cd0d4 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/.config @@ -0,0 +1,375 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40001 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M3=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F1=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F103ZE=y + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_EEPROM is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SDIO is not set + +# +# Board extended module Drivers +# diff --git a/bsp/apm32/apm32f103xe-minibroard/.gitignore b/bsp/apm32/apm32f103xe-minibroard/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/apm32/apm32f103xe-minibroard/Kconfig b/bsp/apm32/apm32f103xe-minibroard/Kconfig new file mode 100644 index 0000000000..7a400db91f --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/apm32/apm32f103xe-minibroard/README.md b/bsp/apm32/apm32f103xe-minibroard/README.md new file mode 100644 index 0000000000..63f3df1030 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/README.md @@ -0,0 +1,84 @@ +# APM32F103ZE MINI BOARD BSP 说明 + +## 简介 + +本文档为 APM32F103ZE MINI 开发板（MINI BOARD）的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 开发板介绍 + +APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示： + + + + + +该开发板常用 **板载资源** 如下： + +- MCU：APM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM +- 外部 RAM：无 +- 外部 FLASH：无 +- 常用外设 + - LED：2个，（黄色，PE5/PE6） + - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13） +- 常用接口：RS232转串口、、USB SLAVE +- 调试接口：标准 JTAG/SWD + + + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------------------------------------ | +| RS232转串口 | 支持 | 使用 UART1/ UART2(通过跳线选择) | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PG15 ---> PIN: 0, 1...143 | +| UART | 支持 | UART1/2 | + +## 使用说明 + +本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + + +### 快速上手 + +本 BSP 为开发者提供MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Aug 20 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +## 注意事项 + +- 可在极海官方网站进行所需资料下载，如pack安装包和MINI开发板原理图等（www.geehy.com）; + +## 联系人信息 + +-[abbbcc ](https://gitee.com/abbbcc)
\ No newline at end of file diff --git a/bsp/apm32/apm32f103xe-minibroard/SConscript b/bsp/apm32/apm32f103xe-minibroard/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/apm32/apm32f103xe-minibroard/SConstruct b/bsp/apm32/apm32f103xe-minibroard/SConstruct new file mode 100644 index 0000000000..c253622173 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +apm32_library = 'APM32F10x_Library' +rtconfig.BSP_LIBRARY_TYPE = apm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/apm32/apm32f103xe-minibroard/applications/SConscript b/bsp/apm32/apm32f103xe-minibroard/applications/SConscript new file mode 100644 index 0000000000..ca2395451a --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/apm32/apm32f103xe-minibroard/applications/main.c b/bsp/apm32/apm32f103xe-minibroard/applications/main.c new file mode 100644 index 0000000000..a592ea4f88 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include <board.h> + +/* defined the LED2 pin: PE6 */ +#define LED2_PIN GET_PIN(E, 6) + +int main(void) +{ + /* set LED2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/apm32/apm32f103xe-minibroard/board/Kconfig b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig new file mode 100644 index 0000000000..3a7d4e1312 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig @@ -0,0 +1,32 @@ +menu "Hardware Drivers Config" + +config SOC_APM32F103ZE + bool + select SOC_SERIES_APM32F1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + endif + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +endmenu diff --git a/bsp/apm32/apm32f103xe-minibroard/board/SConscript b/bsp/apm32/apm32f103xe-minibroard/board/SConscript new file mode 100644 index 0000000000..f453b68f6a --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/SConscript @@ -0,0 +1,24 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s'] + +# You can select chips from the list above +CPPDEFINES = ['APM32F103xE'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.c b/bsp/apm32/apm32f103xe-minibroard/board/board.c new file mode 100644 index 0000000000..bec2c01cde --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include "board.h" + +void apm32_usart_init(void) +{ + GPIO_Config_T GPIO_ConfigStruct; + +#ifdef BSP_USING_UART1 + RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_USART1)); + + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; + GPIO_ConfigStruct.pin = GPIO_PIN_9; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; + GPIO_ConfigStruct.pin = GPIO_PIN_10; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif + +#ifdef BSP_USING_UART2 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2); + + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; + GPIO_ConfigStruct.pin = GPIO_PIN_2; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; + GPIO_ConfigStruct.pin = GPIO_PIN_3; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif +} diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.h b/bsp/apm32/apm32f103xe-minibroard/board/board.h new file mode 100644 index 0000000000..da63a21995 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include <rtthread.h> +#include <apm32f10x.h> + +#include "apm32f10x_gpio.h" +#include "apm32f10x_rcm.h" +#include "apm32f10x_misc.h" +#include "apm32f10x_rcm.h" +#include "apm32f10x_eint.h" +#include "apm32f10x_usart.h" + +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define APM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define APM32_FLASH_SIZE (512 * 1024) +#define APM32_FLASH_END_ADDRESS ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <6-128>, Default: 128 */ +#define APM32_SRAM_SIZE 128 +#define APM32_SRAM_END (0x20000000 + APM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END APM32_SRAM_END + +void SystemClock_Config(void); + +void apm32_usart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct new file mode 100644 index 0000000000..5f21bc4aa3 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct @@ -0,0 +1,17 @@ +; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
+
diff --git a/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png b/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png Binary files differnew file mode 100644 index 0000000000..de26f5f422 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx new file mode 100644 index 0000000000..c10a97669c --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx @@ -0,0 +1,638 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + + <SchemaVersion>2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>rt-thread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>APM32F103ZE</Device> + <Vendor>Geehy</Vendor> + <PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID> + <PackURL>https://www.geehy.com/uploads/tool/</PackURL> + <Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:APM32F103ZE$Device\Include\apm32f10x.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:APM32F103ZE$SVD\APM32F103xx.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\keil\Obj\</OutputDirectory> + <OutputName>rtthread</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>0</BrowseInformation> + <ListingPath>.\build\keil\List\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>1</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments> -REMAP</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM3</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments></TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3></Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M3"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> + <RvdsCdeCp>0</RvdsCdeCp> + <hadIRAM2>0</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <nSecure>0</nSecure> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x80000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>2</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls></MiscControls> + <Define>USE_STDPERIPH_DRIVER, APM32F103xE, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define> + <Undefine></Undefine> + <IncludePath>applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\examples\utest\testcases\kernel</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <ClangAsOpt>4</ClangAsOpt> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x08000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase></pXoBase> + <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>Applications</GroupName> + <Files> + <File> + <FileName>main.c</FileName> + <FileType>1</FileType> + <FilePath>applications\main.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>CPU</GroupName> + <Files> + <File> + <FileName>showmem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath> + </File> + <File> + <FileName>backtrace.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath> + </File> + <File> + <FileName>div0.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath> + </File> + <File> + <FileName>cpuport.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath> + </File> + <File> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>DeviceDrivers</GroupName> + <Files> + <File> + <FileName>pin.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath> + </File> + <File> + <FileName>serial.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath> + </File> + <File> + <FileName>completion.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\src\completion.c</FilePath> + </File> + <File> + <FileName>pipe.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath> + </File> + <File> + <FileName>ringbuffer.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath> + </File> + <File> + <FileName>workqueue.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath> + </File> + <File> + <FileName>dataqueue.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath> + </File> + <File> + <FileName>waitqueue.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath> + </File> + <File> + <FileName>ringblk_buf.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Drivers</GroupName> + <Files> + <File> + <FileName>startup_apm32f10x_hd.s</FileName> + <FileType>2</FileType> + <FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\ARM\startup_apm32f10x_hd.s</FilePath> + </File> + <File> + <FileName>board.c</FileName> + <FileType>1</FileType> + <FilePath>board\board.c</FilePath> + </File> + <File> + <FileName>drv_gpio.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\Drivers\drv_gpio.c</FilePath> + </File> + <File> + <FileName>drv_usart.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\Drivers\drv_usart.c</FilePath> + </File> + <File> + <FileName>drv_common.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\Drivers\drv_common.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>finsh</GroupName> + <Files> + <File> + <FileName>shell.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\shell.c</FilePath> + </File> + <File> + <FileName>msh.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\msh.c</FilePath> + </File> + <File> + <FileName>cmd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\cmd.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Kernel</GroupName> + <Files> + <File> + <FileName>idle.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\idle.c</FilePath> + </File> + <File> + <FileName>object.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\object.c</FilePath> + </File> + <File> + <FileName>components.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\components.c</FilePath> + </File> + <File> + <FileName>scheduler.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\scheduler.c</FilePath> + </File> + <File> + <FileName>thread.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\thread.c</FilePath> + </File> + <File> + <FileName>timer.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\timer.c</FilePath> + </File> + <File> + <FileName>mem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\mem.c</FilePath> + </File> + <File> + <FileName>mempool.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\mempool.c</FilePath> + </File> + <File> + <FileName>clock.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\clock.c</FilePath> + </File> + <File> + <FileName>irq.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\irq.c</FilePath> + </File> + <File> + <FileName>ipc.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\ipc.c</FilePath> + </File> + <File> + <FileName>device.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\device.c</FilePath> + </File> + <File> + <FileName>kservice.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\kservice.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Libraries</GroupName> + <Files> + <File> + <FileName>system_apm32f10x.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c</FilePath> + </File> + <File> + <FileName>apm32f10x_rcm.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c</FilePath> + </File> + <File> + <FileName>apm32f10x_misc.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c</FilePath> + </File> + <File> + <FileName>apm32f10x_usart.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c</FilePath> + </File> + <File> + <FileName>apm32f10x_eint.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c</FilePath> + </File> + <File> + <FileName>apm32f10x_gpio.c</FileName> + <FileType>1</FileType> + <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> + + <RTE> + <apis/> + <components/> + <files/> + </RTE> + +</Project> diff --git a/bsp/apm32/apm32f103xe-minibroard/rtconfig.h b/bsp/apm32/apm32f103xe-minibroard/rtconfig.h new file mode 100644 index 0000000000..8919e38851 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/rtconfig.h @@ -0,0 +1,177 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40001 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M3 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_APM32 +#define SOC_SERIES_APM32F1 + +/* Hardware Drivers Config */ + +#define SOC_APM32F103ZE + +/* Onboard Peripheral Drivers */ + + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/apm32/apm32f103xe-minibroard/rtconfig.py b/bsp/apm32/apm32f103xe-minibroard/rtconfig.py new file mode 100644 index 0000000000..888e1566ba --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M3 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/apm32/apm32f103xe-minibroard/template.uvprojx b/bsp/apm32/apm32f103xe-minibroard/template.uvprojx new file mode 100644 index 0000000000..dee46dc63c --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/template.uvprojx @@ -0,0 +1,396 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + + <SchemaVersion>2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>rt-thread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>APM32F103ZE</Device> + <Vendor>Geehy</Vendor> + <PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID> + <PackURL>https://www.geehy.com/uploads/tool/</PackURL> + <Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:APM32F103ZE$Device\Include\apm32f10x.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:APM32F103ZE$SVD\APM32F103xx.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\keil\Obj\</OutputDirectory> + <OutputName>rtthread</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>0</BrowseInformation> + <ListingPath>.\build\keil\List\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>1</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + 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<TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3></Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + 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</IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x80000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>2</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <ClangAsOpt>4</ClangAsOpt> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x08000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase></pXoBase> + <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>Source Group 1</GroupName> + </Group> + </Groups> + </Target> + </Targets> + + <RTE> + <apis/> + <components/> + <files/> + </RTE> + +</Project> diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h new file mode 100644 index 0000000000..8117944933 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h @@ -0,0 +1,332 @@ +/*! + * @file apm32f10x_adc.h + * + * @brief This file contains all the functions prototypes for the ADC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_ADC_H +#define __APM32F10X_ADC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup ADC_Enumerations Enumerations + @{ +*/ + +/** + * @brief ADC configuration Mode + */ +typedef enum +{ + ADC_MODE_INDEPENDENT = ((uint32_t)0x00000000), //!< Independent mode + ADC_MODE_REG_INJEC_SIMULT = ((uint32_t)0x00010000), //!< Combined regular simultaneous and injected simultaneous mode + ADC_MODE_REG_SIMULT_ALTER_TRIG = ((uint32_t)0x00020000), //!< Combined regular simultaneous and alternate trigger mode + ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), //!< Combined injected simultaneous and fast interleaved mode + ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), //!< Combined injected simultaneous and slow interleaved mode + ADC_MODE_INJEC_SIMULT = ((uint32_t)0x00050000), //!< Injected simultaneous mode + ADC_MODE_REG_SIMULT = ((uint32_t)0x00060000), //!< Regular simultaneous mode + ADC_MODE_FAST_INTERL = ((uint32_t)0x00070000), //!< Fast interleaved mode + ADC_MODE_SLOW_INTERL = ((uint32_t)0x00080000), //!< Slow interleaved mode + ADC_MODE_ALTER_TRIG = ((uint32_t)0x00090000) //!< Alternate trigger mode +} ADC_MODE_T; + +/** + * @brief ADC external trigger sources for regular channels conversion enumeration + */ +typedef enum +{ + ADC_EXT_TRIG_CONV_TMR1_CC1 = ((uint32_t)0x00000000), + ADC_EXT_TRIG_CONV_TMR1_CC2 = ((uint32_t)0x00020000), + ADC_EXT_TRIG_CONV_TMR2_CC2 = ((uint32_t)0x00060000), + ADC_EXT_TRIG_CONV_TMR3_TRGO = ((uint32_t)0x00080000), + ADC_EXT_TRIG_CONV_TMR4_CC4 = ((uint32_t)0x000A0000), + ADC_EXT_TRIG_CONV_EINT9_T8_TRGO = ((uint32_t)0x000C0000), + ADC_EXT_TRIG_CONV_TMR1_CC3 = ((uint32_t)0x00040000), + ADC_EXT_TRIG_CONV_None = ((uint32_t)0x000E0000), + + ADC_EXT_TRIG_CONV_TMR3_CC1 = ((uint32_t)0x00000000), + ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00030000), + ADC_EXT_TRIG_CONV_TMR8_CC1 = ((uint32_t)0x00060000), + ADC_EXT_TRIG_CONV_TMR8_TRGO = ((uint32_t)0x00080000), + ADC_EXT_TRIG_CONV_TMR5_CC1 = ((uint32_t)0x000A0000), + ADC_EXT_TRIG_CONV_TMR5_CC3 = ((uint32_t)0x000C0000) +} ADC_EXT_TRIG_CONV_T; + +/** + * @brief ADC Data Align + */ +typedef enum +{ + ADC_DATA_ALIGN_RIGHT = 0x00000000, + ADC_DATA_ALIGN_LEFT = 0x00000800 +} ADC_DATA_ALIGN_T; + +/** + * @brief ADC Channels + */ +typedef enum +{ + ADC_CHANNEL_0 = ((uint8_t)0x00), + ADC_CHANNEL_1 = ((uint8_t)0x01), + ADC_CHANNEL_2 = ((uint8_t)0x02), + ADC_CHANNEL_3 = ((uint8_t)0x03), + ADC_CHANNEL_4 = ((uint8_t)0x04), + ADC_CHANNEL_5 = ((uint8_t)0x05), + ADC_CHANNEL_6 = ((uint8_t)0x06), + ADC_CHANNEL_7 = ((uint8_t)0x07), + ADC_CHANNEL_8 = ((uint8_t)0x08), + ADC_CHANNEL_9 = ((uint8_t)0x09), + ADC_CHANNEL_10 = ((uint8_t)0x0A), + ADC_CHANNEL_11 = ((uint8_t)0x0B), + ADC_CHANNEL_12 = ((uint8_t)0x0C), + ADC_CHANNEL_13 = ((uint8_t)0x0D), + ADC_CHANNEL_14 = ((uint8_t)0x0E), + ADC_CHANNEL_15 = ((uint8_t)0x0F), + ADC_CHANNEL_16 = ((uint8_t)0x10), + ADC_CHANNEL_TEMP_SENSOR = ((uint8_t)0x10), + ADC_CHANNEL_17 = ((uint8_t)0x11), + ADC_CHANNEL_V_REFINT = ((uint8_t)0x11) +} ADC_CHANNEL_T; + +/** + * @brief ADC Sampling Time + */ +typedef enum +{ + ADC_SAMPLE_TIME_1_5 = ((uint8_t)0x00), + ADC_SAMPLE_TIME_7_5 = ((uint8_t)0x01), + ADC_SAMPLE_TIME_13_5 = ((uint8_t)0x02), + ADC_SAMPLE_TIME_28_5 = ((uint8_t)0x03), + ADC_SAMPLE_TIME_41_5 = ((uint8_t)0x04), + ADC_SAMPLE_TIME_55_5 = ((uint8_t)0x05), + ADC_SAMPLE_TIME_71_5 = ((uint8_t)0x06), + ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07) +} ADC_SAMPLE_TIME_T; + +/** + * @brief ADC external trigger sources for injected channels conversion + */ +typedef enum +{ + /** for ADC1 and ADC2 */ + ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO = ((uint8_t)0x02), + ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1 = ((uint8_t)0x03), + ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4 = ((uint8_t)0x04), + ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO = ((uint8_t)0x05), + ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4 = ((uint8_t)0x06), + + /** for ADC1, ADC2 and ADC3 */ + ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO = ((uint8_t)0x00), + ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4 = ((uint8_t)0x01), + ADC_EXT_TRIG_INJEC_CONV_NONE = ((uint8_t)0x07), + + /** for ADC3 only */ + ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3 = ((uint8_t)0x02), + ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2 = ((uint8_t)0x03), + ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4 = ((uint8_t)0x04), + ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO = ((uint8_t)0x05), + ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4 = ((uint8_t)0x06) +} ADC_EXT_TRIG_INJEC_CONV_T; + +/** + * @brief ADC Injected channels + */ +typedef enum +{ + ADC_INJEC_CHANNEL_1 = ((uint8_t)0x14), + ADC_INJEC_CHANNEL_2 = ((uint8_t)0x18), + ADC_INJEC_CHANNEL_3 = ((uint8_t)0x1C), + ADC_INJEC_CHANNEL_4 = ((uint8_t)0x20) +} ADC_INJEC_CHANNEL_T; + +/** + * @brief ADC Analog Watchdog Selection + */ +typedef enum +{ + ADC_ANALOG_WATCHDOG_SINGLE_REG = ((uint32_t)0x00800200), + ADC_ANALOG_WATCHDOG_SINGLE_INJEC = ((uint32_t)0x00400200), + ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC = ((uint32_t)0x00C00200), + ADC_ANALOG_WATCHDOG_ALL_REG = ((uint32_t)0x00800000), + ADC_ANALOG_WATCHDOG_ALL_INJEC = ((uint32_t)0x00400000), + ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC = ((uint32_t)0x00C00000), + ADC_ANALOG_WATCHDOG_NONE = ((uint32_t)0x00000000) +} ADC_ANALOG_WATCHDOG_T; + +/** + * @brief ADC Interrupt definition + */ +typedef enum +{ + ADC_INT_AWD = ((uint16_t)0x0140), //!< Analog Watchdog interrupt + ADC_INT_EOC = ((uint16_t)0x0220), //!< End Of Conversion interrupt + ADC_INT_INJEOC = ((uint16_t)0x0480) //!< Injected Channel End Of Conversion interrupt +} ADC_INT_T; + +/** + * @brief ADC Flag + */ +typedef enum +{ + ADC_FLAG_AWD = ((uint8_t)0x01), //!< Analog Watchdog event occur flag + ADC_FLAG_EOC = ((uint8_t)0x02), //!< End Of Conversion flag + ADC_FLAG_INJEOC = ((uint8_t)0x04), //!< Injected Channel End Of Conversion flag + ADC_FLAG_INJCS = ((uint8_t)0x08), //!< Injected Channel Conversion Start flag + ADC_FLAG_REGCS = ((uint8_t)0x10) //!< Regular Channel Conversion Start flag +} ADC_FLAG_T; + +/**@} end of group ADC_Enumerations*/ + + +/** @addtogroup ADC_Macros Macros + @{ +*/ + +/** ADC_IJD Offset */ +#define INJDATA_OFFSET ((uint8_t)0x28) + +/** ADC_RDG register address */ +#define RDG_ADDRESS ((uint32_t)0x4001244C) + +/** INJSEQ register config */ +#define INJSEQ_SET_INJSEQC ((uint32_t)0x0000001F) +#define INJSEQ_SET_INJSEQLEN ((uint32_t)0x00300000) + +/** SMPTIM register SET */ +#define SMPCYCCFG_SET_SMPTIM1 ((uint32_t)0x00000007) +#define SMPCYCCFG_SET_SMPTIM2 ((uint32_t)0x00000007) + +/** REGSEQ register SET */ +#define REGSEQC_SET_REGSEQ3 ((uint32_t)0x0000001F) +#define REGSEQC_SET_REGSEQ2 ((uint32_t)0x0000001F) +#define REGSEQC_SET_REGSEQ1 ((uint32_t)0x0000001F) + +/**@} end of group ADC_Macros*/ + + +/** @addtogroup ADC_Structure Data Structure + @{ +*/ + +/** + * @brief ADC Config structure definition + */ +typedef struct +{ + ADC_MODE_T mode; + uint8_t scanConvMode; //!< This parameter can be ENABLE or DISABLE. + uint8_t continuosConvMode; //!< This parameter can be ENABLE or DISABLE. + ADC_EXT_TRIG_CONV_T externalTrigConv; + ADC_DATA_ALIGN_T dataAlign; + uint8_t nbrOfChannel; //!< This parameter must range from 1 to 16. +} ADC_Config_T; + +/**@} end of group ADC_Structure*/ + + +/** @addtogroup ADC_Fuctions Fuctions + @{ +*/ + +/** ADC reset and common configuration */ +void ADC_Reset(ADC_T* adc); +void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig); +void ADC_ConfigStructInit(ADC_Config_T* adcConfig); +void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime); +void ADC_Enable(ADC_T* adc); +void ADC_Disable(ADC_T* adc); + +/** ADC for DMA */ +void ADC_EnableDMA(ADC_T* adc); +void ADC_DisableDMA(ADC_T* adc); + +/** ADC Calibration */ +void ADC_ResetCalibration(ADC_T* adc); +uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc); +void ADC_StartCalibration(ADC_T* adc); +uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc); + +/** ADC software start conversion */ +void ADC_EnableSoftwareStartConv(ADC_T* adc); +void ADC_DisableSoftwareStartConv(ADC_T* adc); +uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc); + +/** ADC Discontinuous mode */ +void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number); +void ADC_EnableDiscMode(ADC_T* adc); +void ADC_DisableDiscMode(ADC_T* adc); + +/** ADC External trigger conversion */ +void ADC_EnableExternalTrigConv(ADC_T* adc); +void ADC_DisableExternalTrigConv(ADC_T* adc); + +/** ADC Conversion result */ +uint16_t ADC_ReadConversionValue(ADC_T* adc); +uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc); + +/** ADC Automatic injected group */ +void ADC_EnableInjectedConv(ADC_T* adc); +void ADC_DisableInjectedConv(ADC_T* adc); +void ADC_EnableInjectedDiscMode(ADC_T* adc); +void ADC_DisableInjectedDiscMode(ADC_T* adc); + +/** ADC External trigger for injected channels conversion */ +void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv); +void ADC_EnableExternalTrigInjectedConv(ADC_T* adc); +void ADC_DisableExternalTrigInjectedConv(ADC_T* adc); + +/** ADC Start of the injected channels conversion */ +void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc); +void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc); +uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc); + +/** ADC injected channel */ +void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length); +void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet); +uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel); + +/** ADC analog watchdog */ +void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog); +void ADC_DisableAnalogWatchdog(ADC_T* adc); +void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold); +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel); + +/** ADC temperature sensor */ +void ADC_EnableTempSensorVrefint(ADC_T* adc); +void ADC_DisableTempSensorVrefint(ADC_T* adc); + +/** Interrupt and flag */ +void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt); +void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt); +uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag); +void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag); +uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt); +void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt); + +/**@} end of group ADC_Fuctions*/ +/**@} end of group ADC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /** __APM32F10X_ADC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h new file mode 100644 index 0000000000..84b12b4fea --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h @@ -0,0 +1,135 @@ +/*! + * @file apm32f10x_bakr.h + * + * @brief This file contains all the functions prototypes for the BAKPR firmware library. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_BAKPR_H +#define __APM32F10X_BAKPR_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup BAKPR_Driver BAKPR Driver + @{ +*/ + +/** @addtogroup BAKPR_Enumerations Enumerations + @{ +*/ + +/** + * @brief BAKPR TAMPER Pin Active Level + */ +typedef enum +{ + BAKPR_TAMPER_PIN_LEVEL_HIGH, + BAKPR_TAMPER_PIN_LEVEL_LOW +} BAKPR_TAMPER_PIN_LEVEL_T; + +/** + * @brief BAKPR RTC output source + */ +typedef enum +{ + BAKPR_RTC_OUTPUT_SOURCE_NONE, + BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK, + BAKPR_RTC_OUTPUT_SOURCE_ALARM, + BAKPR_RTC_OUTPUT_SOURCE_SECOND +} BAKPR_RTC_OUTPUT_SOURCE_T; + +/** + * @brief BAKPR DATA register Addr + */ +typedef enum +{ + BAKPR_DATA1 = ((uint16_t)0x0004), + BAKPR_DATA2 = ((uint16_t)0x0008), + BAKPR_DATA3 = ((uint16_t)0x000C), + BAKPR_DATA4 = ((uint16_t)0x0010), + BAKPR_DATA5 = ((uint16_t)0x0014), + BAKPR_DATA6 = ((uint16_t)0x0018), + BAKPR_DATA7 = ((uint16_t)0x001C), + BAKPR_DATA8 = ((uint16_t)0x0020), + BAKPR_DATA9 = ((uint16_t)0x0024), + BAKPR_DATA10 = ((uint16_t)0x0028), + BAKPR_DATA11 = ((uint16_t)0x0040), + BAKPR_DATA12 = ((uint16_t)0x0044), + BAKPR_DATA13 = ((uint16_t)0x0048), + BAKPR_DATA14 = ((uint16_t)0x004C), + BAKPR_DATA15 = ((uint16_t)0x0050), + BAKPR_DATA16 = ((uint16_t)0x0054), + BAKPR_DATA17 = ((uint16_t)0x0058), + BAKPR_DATA18 = ((uint16_t)0x005C), + BAKPR_DATA19 = ((uint16_t)0x0060), + BAKPR_DATA20 = ((uint16_t)0x0064), + BAKPR_DATA21 = ((uint16_t)0x0068), + BAKPR_DATA22 = ((uint16_t)0x006C), + BAKPR_DATA23 = ((uint16_t)0x0070), + BAKPR_DATA24 = ((uint16_t)0x0074), + BAKPR_DATA25 = ((uint16_t)0x0078), + BAKPR_DATA26 = ((uint16_t)0x007C), + BAKPR_DATA27 = ((uint16_t)0x0080), + BAKPR_DATA28 = ((uint16_t)0x0084), + BAKPR_DATA29 = ((uint16_t)0x0088), + BAKPR_DATA30 = ((uint16_t)0x008C), + BAKPR_DATA31 = ((uint16_t)0x0090), + BAKPR_DATA32 = ((uint16_t)0x0094), + BAKPR_DATA33 = ((uint16_t)0x0098), + BAKPR_DATA34 = ((uint16_t)0x009C), + BAKPR_DATA35 = ((uint16_t)0x00A0), + BAKPR_DATA36 = ((uint16_t)0x00A4), + BAKPR_DATA37 = ((uint16_t)0x00A8), + BAKPR_DATA38 = ((uint16_t)0x00AC), + BAKPR_DATA39 = ((uint16_t)0x00B0), + BAKPR_DATA40 = ((uint16_t)0x00B4), + BAKPR_DATA41 = ((uint16_t)0x00B8), + BAKPR_DATA42 = ((uint16_t)0x00BC) +} BAKPR_DATA_T; + +/**@} end of group BAKPR_Enumerations*/ + + +/** @addtogroup BAKPR_Fuctions Fuctions + @{ +*/ + +/** BAKPR reset and configuration */ +void BAKPR_Reset(void); +void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value); +void BAKPR_EnableTamperPin(void); +void BAKPR_DisableTamperPin(void); +void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure); +void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue); +void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data); +uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData); + +/** Interrupts and flags */ +void BAKPR_EnableInterrupt(void); +void BAKPR_DisableInterrupt(void); +uint8_t BAKPR_ReadStatusFlag(void); +void BAKPR_ClearStatusFlag(void); +uint8_t BAKPR_ReadIntFlag(void); +void BAKPR_ClearIntFlag(void); + +/**@} end of group BAKPR_Fuctions*/ +/**@} end of group BAKPR_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_BAKPR_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h new file mode 100644 index 0000000000..766d1918e4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h @@ -0,0 +1,337 @@ +/*! + * @file apm32f10x_can.h + * + * @brief This file contains all the functions prototypes for the CAN firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_CAN_H +#define __APM32F10X_CAN_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_Enumerations Enumerations + @{ +*/ + +/** + * @brief CAN mode + */ +typedef enum +{ + CAN_MODE_NORMAL = ((uint8_t)00), //!< normal mode + CAN_MODE_LOOPBACK = ((uint8_t)01), //!< loopback mode + CAN_MODE_SILENT = ((uint8_t)02), //!< silent mode + CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03), //!< loopback combined with silent mode +} CAN_MODE_T; + +/** + * @brief CAN synchronisation jump width + */ +typedef enum +{ + CAN_SJW_1 = ((uint8_t)00), //!< 1 time quantum + CAN_SJW_2 = ((uint8_t)01), //!< 2 time quantum + CAN_SJW_3 = ((uint8_t)02), //!< 3 time quantum + CAN_SJW_4 = ((uint8_t)03) //!< 4 time quantum +} CAN_SJW_T; + +/** + * @brief CAN time quantum in bit segment 1 + */ +typedef enum +{ + CAN_TIME_SEGMENT1_1 = ((uint8_t)0x00), //!< 1 time quanta + CAN_TIME_SEGMENT1_2 = ((uint8_t)0x01), //!< 2 time quanta + CAN_TIME_SEGMENT1_3 = ((uint8_t)0x02), //!< 3 time quanta + CAN_TIME_SEGMENT1_4 = ((uint8_t)0x03), //!< 4 time quanta + CAN_TIME_SEGMENT1_5 = ((uint8_t)0x04), //!< 5 time quanta + CAN_TIME_SEGMENT1_6 = ((uint8_t)0x05), //!< 6 time quanta + CAN_TIME_SEGMENT1_7 = ((uint8_t)0x06), //!< 7 time quanta + CAN_TIME_SEGMENT1_8 = ((uint8_t)0x07), //!< 8 time quanta + CAN_TIME_SEGMENT1_9 = ((uint8_t)0x08), //!< 9 time quanta + CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09), //!< 10 time quanta + CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A), //!< 11 time quanta + CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B), //!< 12 time quanta + CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C), //!< 13 time quanta + CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D), //!< 14 time quanta + CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E), //!< 15 time quanta + CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F) //!< 16 time quanta +} CAN_TIME_SEGMENT1_T; + +/** + * @brief CAN time quantum in bit segment 2 + */ +typedef enum +{ + CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, //!< 1 time quanta + CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, //!< 2 time quanta + CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, //!< 3 time quanta + CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, //!< 4 time quanta + CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, //!< 5 time quanta + CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, //!< 6 time quanta + CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, //!< 7 time quanta + CAN_TIME_SEGMENT2_8 = (uint8_t)0x07, //!< 8 time quanta +} CAN_TIME_SEGMENT2_T; + +/** + * @brief CAN filter FIFO + */ +typedef enum +{ + CAN_FILTER_FIFO_0 = ((uint8_t)0x00), //!< filter FIFO 0 + CAN_FILTER_FIFO_1 = ((uint8_t)0x01), //!< filter FIFO 1 +} CAN_FILTER_FIFO_T; + +/** + * @brief CAN filter mode + */ +typedef enum +{ + CAN_FILTER_MODE_IDMASK = ((uint8_t)00), //!< identifier/mask mode + CAN_FILTER_MODE_IDLIST = ((uint8_t)01) //!< identifier list mode +} CAN_FILTER_MODE_T; + +/** + * @brief CAN filter scale + */ +typedef enum +{ + CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters + CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), //!< One 32-bit filter +} CAN_FILTER_SCALE_T; + +/** + * @brief CAN identifier type + */ +typedef enum +{ + CAN_TYPEID_STD = ((uint32_t)0x00000000), //!< Standard Id + CAN_TYPEID_EXT = ((uint32_t)0x00000004) //!< Extended Id +} CAN_TYPEID_T; + +/** + * @brief CAN_remote_transmission_request + */ +typedef enum +{ + CAN_RTXR_DATA = ((uint32_t)0x00000000), //!< Data frame + CAN_RTXR_REMOTE = ((uint32_t)0x00000002) //!< Remote frame +} CAN_RTXR_T; + +/** + * @brief Mailboxes definition + */ +typedef enum +{ + CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0 + CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1 + CAN_TX_MAILBIX_2 = ((uint8_t)0x02), //!< Tx mailbox2 +} CAN_TX_MAILBIX_T; + +/** + * @brief CAN receive FIFO number constants + */ +typedef enum +{ + CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0 + CAN_RX_FIFO_1 = ((uint8_t)0x01), //!< receive FIFO 1 +} CAN_RX_FIFO_T; + +/** + * @brief CAN Operating Mode + */ +typedef enum +{ + CAN_OPERATING_MODE_INIT = ((uint8_t)00), //!< Initialization mode + CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), //!< Normal mode + CAN_OPERATING_MODE_SLEEP = ((uint8_t)02), //!< sleep mode +} CAN_OPERATING_MODE_T; + +/** + * @brief CAN Interrupts + */ +typedef enum +{ + CAN_INT_TXME = ((uint32_t)0x00000001), //!< Transmit mailbox empty Interrupt + CAN_INT_F0MP = ((uint32_t)0x00000002), //!< FIFO 0 message pending Interrupt + CAN_INT_F0FULL = ((uint32_t)0x00000004), //!< FIFO 0 full Interrupt + CAN_INT_F0OVR = ((uint32_t)0x00000008), //!< FIFO 0 overrun Interrupt + CAN_INT_F1MP = ((uint32_t)0x00000010), //!< FIFO 1 message pending Interrupt + CAN_INT_F1FULL = ((uint32_t)0x00000020), //!< FIFO 1 full Interrupt + CAN_INT_F1OVR = ((uint32_t)0x00000040), //!< FIFO 1 overrun Interrupt + CAN_INT_ERRW = ((uint32_t)0x00000100), //!< Error warning Interrupt + CAN_INT_ERRP = ((uint32_t)0x00000200), //!< Error passive Interrupt + CAN_INT_BOF = ((uint32_t)0x00000400), //!< Bus-off Interrupt + CAN_INT_LEC = ((uint32_t)0x00000800), //!< Last error record code Interrupt + CAN_INT_ERR = ((uint32_t)0x00008000), //!< Error Interrupt + CAN_INT_WUP = ((uint32_t)0x00010000), //!< Wake-up Interrupt + CAN_INT_SLEEP = ((uint32_t)0x00020000) //!< Sleep acknowledge Interrupt +} CAN_INT_T; + +/** + * @brief CAN Flags + */ +typedef enum +{ + /** Error flag*/ + CAN_FLAG_ERRW = ((uint32_t)0x10F00001), //!< Error Warning Flag + CAN_FLAG_ERRP = ((uint32_t)0x10F00002), //!< Error Passive Flag + CAN_FLAG_BOF = ((uint32_t)0x10F00004), //!< Bus-Off Flag + CAN_FLAG_LERRC = ((uint32_t)0x30F00070), //!< Last error record code Flag + /** Operating Mode Flags */ + CAN_FLAG_WUPI = ((uint32_t)0x31000008), //!< Wake up Flag + CAN_FLAG_SLEEP = ((uint32_t)0x31000012), //!< Sleep acknowledge Flag + /** Receive Flags */ + CAN_FLAG_F0MP = ((uint32_t)0x12000003), //!< FIFO 0 Message Pending Flag + CAN_FLAG_F0FULL = ((uint32_t)0x32000008), //!< FIFO 0 Full Flag + CAN_FLAG_F0OVR = ((uint32_t)0x32000010), //!< FIFO 0 Overrun Flag + CAN_FLAG_F1MP = ((uint32_t)0x14000003), //!< FIFO 1 Message Pending Flag + CAN_FLAG_F1FULL = ((uint32_t)0x34000008), //!< FIFO 1 Full Flag + CAN_FLAG_F1OVR = ((uint32_t)0x34000010), //!< FIFO 1 Overrun Flag + /** Transmit Flags */ + CAN_FLAG_REQC0 = ((uint32_t)0x38000001), //!< Request MailBox0 Flag + CAN_FLAG_REQC1 = ((uint32_t)0x38000100), //!< Request MailBox1 Flag + CAN_FLAG_REQC2 = ((uint32_t)0x38010000) //!< Request MailBox2 Flag +} CAN_FLAG_T; + +/**@} end of group CAN_Enumerations*/ + + +/** + * @brief CAN Config structure definition + */ + +/** + * @brief CAN config structure definition + */ +typedef struct +{ + uint8_t timeTrigComMode; //!< Enable or disable the time triggered communication mode. + uint8_t autoBusOffManage; //!< Enable or disable the automatic bus-off management. + uint8_t autoWakeUpMode; //!< Enable or disable the automatic wake-up mode. + uint8_t nonAutoRetran; //!< Enable or disable the non-automatic retransmission mode. + uint8_t rxFIFOLockMode; //!< Enable or disable the Receive FIFO Locked mode. + uint8_t txFIFOPriority; //!< Enable or disable the transmit FIFO priority. + CAN_MODE_T mode; //!< Specifies the CAN operating mode. + CAN_SJW_T syncJumpWidth; /** Specifies the maximum number of time quanta the CAN hardware + * is allowed to lengthen or shorten a bit to perform resynchronization. + */ + CAN_TIME_SEGMENT1_T timeSegment1; //!< Specifies the number of time quanta in Bit Segment 1. + CAN_TIME_SEGMENT2_T timeSegment2; //!< Specifies the number of time quanta in Bit Segment 2. + uint16_t prescaler; //!< Specifies the length of a time quantum. It can be 1 to 1024. +} CAN_Config_T; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF. + uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. + CAN_TYPEID_T typeID; + CAN_RTXR_T remoteTxReq; + uint8_t dataLengthCode;//!< Specifies the data length code. It can be 0 to 8. + uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. +} CAN_TX_MESSAGE_T; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF. + uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. + uint32_t typeID; + uint32_t remoteTxReq; + uint8_t dataLengthCode; //!< Specifies the data length code. It can be 0 to 8. + uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. + uint8_t filterMatchIndex;//!< Specifies the filter match index. It can be 0 to 0xFF. +} CAN_RX_MESSAGE_T; + +/** + * @brief CAN filter config structure definition + */ +typedef struct +{ + uint8_t filterNumber; //!< Specifies the filter number. It can be 0 to 13. + uint16_t filterIdHigh; //!< Specifies the filter identification number.It can be 0 to 0xFFFF. + uint16_t filterIdLow; //!< Specifies the filter identification number.It can be 0 to 0xFFFF. + uint16_t filterMaskIdHigh; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF. + uint16_t filterMaskIdLow; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF. + uint16_t filterActivation; //!< Specifies the filter Activation. It can be ENABLE or DISABLE. + CAN_FILTER_FIFO_T filterFIFO; + CAN_FILTER_MODE_T filterMode; + CAN_FILTER_SCALE_T filterScale; +} CAN_FILTER_CONFIG_T; + +/**@} end of group CAN_Structure*/ + + +/** @addtogroup CAN_Fuctions Fuctions + @{ +*/ + +/** CAN reset and configuration */ +void CAN_Reset(CAN_T* can); +uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig); +void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig); +void CAN_ConfigStructInit(CAN_Config_T* canConfig); +void CAN_EnableDBGFreeze(CAN_T* can); +void CAN_DisableDBGFreeze(CAN_T* can); +void CAN_EnableTTCComMode(CAN_T* can); +void CAN_DisableTTCComMode(CAN_T* can); + +/** CAN frames transmit */ +uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage); +uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); +void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); + +/** CAN frames receive */ +void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage); +void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber); +uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber); + +/** CAN operation modes */ +uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode); +uint8_t CAN_SleepMode(CAN_T* can); +uint8_t CAN_WakeUpMode(CAN_T* can); + +/** CAN bus error management */ +uint8_t CAN_ReadLastErrorCode(CAN_T* can); +uint8_t CAN_ReadRxErrorCounter(CAN_T* can); +uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can); + +/** CAN interrupt and flag */ +void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt); +void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt); +uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag); +void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag); +uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag); +void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag); + +/**@} end of group CAN_Fuctions*/ +/**@} end of group CAN_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_CAN_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h new file mode 100644 index 0000000000..c3a0098aee --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h @@ -0,0 +1,52 @@ +/*! + * @file apm32f10x_crc.h + * + * @brief This file contains all the functions prototypes for the CRC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_CRC_H +#define __APM32F10X_CRC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_Fuctions Fuctions + @{ +*/ + +/** Reset DATA */ +void CRC_ResetDATA(void); + +/** Operation functions */ +uint32_t CRC_CalculateCRC(uint32_t data); +uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen); +uint32_t CRC_ReadCRC(void); +void CRC_WriteIDRegister(uint8_t inData); +uint8_t CRC_ReadIDRegister(void); + +/**@} end of group CRC_Fuctions*/ +/**@} end of group CRC_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_CRC_H */ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h new file mode 100644 index 0000000000..1fce07ebc1 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h @@ -0,0 +1,181 @@ +/*! + * @file apm32f10x_dac.h + * + * @brief This file contains all the functions prototypes for the DAC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_DAC_H +#define __APM32F10X_DAC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_Enumerations Enumerations + @{ +*/ + +/** + * @brief DAC Channel selection + */ +typedef enum +{ + DAC_CHANNEL_1 = 0x00000000, + DAC_CHANNEL_2 = 0x00000010 +}DAC_CHANNEL_T; + +/** + * @brief DAC trigger selection + */ +typedef enum +{ + DAC_TRIGGER_NONE = 0x00000000, + DAC_TRIGGER_TMR6_TRGO = 0x00000004, + DAC_TRIGGER_TMR8_TRGO = 0x0000000C, + DAC_TRIGGER_TMR7_TRGO = 0x00000014, + DAC_TRIGGER_TMR5_TRGO = 0x0000001C, + DAC_TRIGGER_TMR2_TRGO = 0x00000024, + DAC_TRIGGER_TMR4_TRGO = 0x0000002C, + DAC_TRIGGER_EINT9 = 0x00000034, + DAC_TRIGGER_SOFT = 0x0000003C +}DAC_TRIGGER_T; + +/** + * @brief DAC wave generation + */ +typedef enum +{ + DAC_WAVE_GENERATION_NONE = 0x00000000, + DAC_WAVE_GENERATION_NOISE = 0x00000040, + DAC_WAVE_GENERATION_TRIANGLE = 0x00000080 +}DAC_WAVE_GENERATION_T; + +/** + * @brief DAC channelx mask/amplitude selector + */ +typedef enum +{ + DAC_LFSR_MASK_BIT11_1 = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_2 = 0x00001000, //!< Mask bit[11:2] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_3 = 0x00002000, //!< Mask bit[11:3] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_4 = 0x00003000, //!< Mask bit[11:4] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_5 = 0x00004000, //!< Mask bit[11:5] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_6 = 0x00005000, //!< Mask bit[11:6] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_7 = 0x00006000, //!< Mask bit[11:7] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_8 = 0x00007000, //!< Mask bit[11:8] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_9 = 0x00008000, //!< Mask bit[11:9] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_10 = 0x00009000, //!< Mask bit[11:10] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11 = 0x0000A000, //!< Mask bit11 of LFSR for noise wave generation + DAC_LFSR_MASK_NONE = 0x0000B000, //!< Mask none bit of LFSR for noise wave generation + + DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, //!< Triangle amplitude equal to 1 + DAC_TRIANGLE_AMPLITUDE_3 = 0x00001000, //!< Triangle amplitude equal to 3 + DAC_TRIANGLE_AMPLITUDE_7 = 0x00002000, //!< Triangle amplitude equal to 7 + DAC_TRIANGLE_AMPLITUDE_15 = 0x00003000, //!< Triangle amplitude equal to 15 + DAC_TRIANGLE_AMPLITUDE_31 = 0x00004000, //!< Triangle amplitude equal to 31 + DAC_TRIANGLE_AMPLITUDE_63 = 0x00005000, //!< Triangle amplitude equal to 63 + DAC_TRIANGLE_AMPLITUDE_127 = 0x00006000, //!< Triangle amplitude equal to 127 + DAC_TRIANGLE_AMPLITUDE_255 = 0x00007000, //!< Triangle amplitude equal to 255 + DAC_TRIANGLE_AMPLITUDE_511 = 0x00008000, //!< Triangle amplitude equal to 511 + DAC_TRIANGLE_AMPLITUDE_1023 = 0x00009000, //!< Triangle amplitude equal to 1023 + DAC_TRIANGLE_AMPLITUDE_2047 = 0x0000A000, //!< Triangle amplitude equal to 2047 + DAC_TRIANGLE_AMPLITUDE_4095 = 0x0000B000 //!< Triangle amplitude equal to 4095 +}DAC_MASK_AMPLITUDE_SEL_T; + +/** + * @brief DAC output buffer + */ +typedef enum +{ + DAC_OUTPUT_BUFFER_ENBALE = 0x00000000, + DAC_OUTPUT_BUFFER_DISABLE = 0x00000002 +}DAC_OUTPUT_BUFFER_T; + +/** + * @brief DAC data align + */ +typedef enum +{ + DAC_ALIGN_12BIT_R = 0x00000000, + DAC_ALIGN_12BIT_L = 0x00000004, + DAC_ALIGN_8BIT_R = 0x00000008 +}DAC_ALIGN_T; + +/**@} end of group DAC_Enumerations*/ + + +/** @addtogroup DAC_Structure Data Structure + @{ +*/ + +/** + * @brief DAC Config structure definition + */ +typedef struct +{ + DAC_TRIGGER_T trigger; + DAC_OUTPUT_BUFFER_T outputBuffer; + DAC_WAVE_GENERATION_T waveGeneration; + DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect; +}DAC_ConfigStruct_T; + +/**@} end of group DAC_Structure*/ + + +/** @addtogroup DAC_Fuctions Fuctions + @{ +*/ + +/** DAC Reset and Configuration */ +void DAC_Reset(void); +void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct); +void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct); +void DAC_Enable(DAC_CHANNEL_T channel); +void DAC_Disable(DAC_CHANNEL_T channel); + +/** DAC channel for DAM */ +void DAC_DMA_Enable(DAC_CHANNEL_T channel); +void DAC_DMA_Disable(DAC_CHANNEL_T channel); + +/** DAC channel software trigger */ +void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel); +void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel); +void DAC_EnableDualSoftwareTrigger(void); +void DAC_DisableDualSoftwareTrigger(void); + +/** DAC channel wave generation */ +void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); +void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); + +/** DAC set channel data */ +void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data); +void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data); +void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1); + +/** DAC read data output value */ +uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel); + +/**@} end of group DAC_Fuctions*/ +/**@} end of group DAC_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DAC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h new file mode 100644 index 0000000000..193f86ffba --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h @@ -0,0 +1,83 @@ +/*! + * @file apm32f10x_dbgmcu.h + * + * @brief This file contains all the functions prototypes for the DBUGMCU firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_DBGMCU_H +#define __APM32F10X_DBGMCU_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DBGMCU_Driver DBGMCU Driver + @{ +*/ + +/** @addtogroup DBGMCU_Enumerations Enumerations + @{ +*/ + +enum +{ + DBGMCU_SLEEP = ((uint32_t)0x00000001), + DBGMCU_STOP = ((uint32_t)0x00000002), + DBGMCU_STANDBY = ((uint32_t)0x00000004), + DBGMCU_IWDT_STOP = ((uint32_t)0x00000100), + DBGMCU_WWDT_STOP = ((uint32_t)0x00000200), + DBGMCU_TMR1_STOP = ((uint32_t)0x00000400), + DBGMCU_TMR2_STOP = ((uint32_t)0x00000800), + DBGMCU_TMR3_STOP = ((uint32_t)0x00001000), + DBGMCU_TMR4_STOP = ((uint32_t)0x00002000), + DBGMCU_CAN1_STOP = ((uint32_t)0x00004000), + DBGMCU_I2C1_SMBUS_TIMEOUT = ((uint32_t)0x00008000), + DBGMCU_I2C2_SMBUS_TIMEOUT = ((uint32_t)0x00010000), + DBGMCU_TMR8_STOP = ((uint32_t)0x00020000), + DBGMCU_TMR5_STOP = ((uint32_t)0x00040000), + DBGMCU_TMR6_STOP = ((uint32_t)0x00080000), + DBGMCU_TMR7_STOP = ((uint32_t)0x00100000), + DBGMCU_CAN2_STOP = ((uint32_t)0x00200000), + DBGMCU_TMR15_STOP = ((uint32_t)0x00400000), + DBGMCU_TMR16_STOP = ((uint32_t)0x00800000), + DBGMCU_TMR17_STOP = ((uint32_t)0x01000000), + DBGMCU_TMR12_STOP = ((uint32_t)0x02000000), + DBGMCU_TMR13_STOP = ((uint32_t)0x04000000), + DBGMCU_TMR14_STOP = ((uint32_t)0x08000000), + DBGMCU_TMR9_STOP = ((uint32_t)0x10000000), + DBGMCU_TMR10_STOP = ((uint32_t)0x20000000), + DBGMCU_TMR11_STOP = ((uint32_t)0x40000000), +}; + +/**@} end of group DBGMCU_Enumerations*/ + + +/** @addtogroup DBGMCU_Fuctions Fuctions + @{ +*/ + +uint32_t DBGMCU_ReadDEVID(void); +uint32_t DBGMCU_ReadREVID(void); +void DBGMCU_Enable(uint32_t periph); +void DBGMCU_Disable(uint32_t periph); + +/**@} end of group DBGMCU_Fuctions*/ +/**@} end of group DBGMCU_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DBGMCU_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h new file mode 100644 index 0000000000..eb574afb73 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h @@ -0,0 +1,290 @@ +/*! + * @file apm32f10x_dma.h + * + * @brief This file contains all the functions prototypes for the DMA firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_DMA_H +#define __APM32F10X_DMA_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMA_Driver DMA Driver + @{ +*/ + +/** @addtogroup DMA_Enumerations Enumerations + @{ +*/ + +/** + * @brief DMA Transmission direction + */ +typedef enum +{ + DMA_DIR_PERIPHERAL_SRC, + DMA_DIR_PERIPHERAL_DST +} DMA_DIR_T; + +/** + * @brief DMA Peripheral address increment + */ +typedef enum +{ + DMA_PERIPHERAL_INC_DISABLE, + DMA_PERIPHERAL_INC_ENABLE +} DMA_PERIPHERAL_INC_T; + +/** + * @brief DMA Memory address increment + */ +typedef enum +{ + DMA_MEMORY_INC_DISABLE, + DMA_MEMORY_INC_ENABLE +} DMA_MEMORY_INC_T; + +/** + * @brief DMA Peripheral Data Size + */ +typedef enum +{ + DMA_PERIPHERAL_DATA_SIZE_BYTE, + DMA_PERIPHERAL_DATA_SIZE_HALFWORD, + DMA_PERIPHERAL_DATA_SIZE_WOED +} DMA_PERIPHERAL_DATA_SIZE_T; + +/** + * @brief DMA Memory Data Size + */ +typedef enum +{ + DMA_MEMORY_DATA_SIZE_BYTE, + DMA_MEMORY_DATA_SIZE_HALFWORD, + DMA_MEMORY_DATA_SIZE_WOED +} DMA_MEMORY_DATA_SIZE_T; + +/** + * @brief DMA Mode + */ +typedef enum +{ + DMA_MODE_NORMAL, + DMA_MODE_CIRCULAR +} DMA_LOOP_MODE_T; + +/** + * @brief DMA priority level + */ +typedef enum +{ + DMA_PRIORITY_LOW, + DMA_PRIORITY_MEDIUM, + DMA_PRIORITY_HIGH, + DMA_PRIORITY_VERYHIGH +} DMA_PRIORITY_T; + +/** + * @brief DMA Memory to Memory + */ +typedef enum +{ + DMA_M2MEN_DISABLE, + DMA_M2MEN_ENABLE +} DMA_M2MEN_T; + +/** + * @brief DMA interrupt + */ +typedef enum +{ + DMA_INT_TC = 0x00000002, + DMA_INT_HT = 0x00000004, + DMA_INT_TERR = 0x00000008 +} DMA_INT_T; + +/** + * @brief DMA Flag + */ +typedef enum +{ + DMA1_FLAG_GINT1 = 0x00000001, + DMA1_FLAG_TC1 = 0x00000002, + DMA1_FLAG_HT1 = 0x00000004, + DMA1_FLAG_TERR1 = 0x00000008, + DMA1_FLAG_GINT2 = 0x00000010, + DMA1_FLAG_TC2 = 0x00000020, + DMA1_FLAG_HT2 = 0x00000040, + DMA1_FLAG_TERR2 = 0x00000080, + DMA1_FLAG_GINT3 = 0x00000100, + DMA1_FLAG_TC3 = 0x00000200, + DMA1_FLAG_HT3 = 0x00000400, + DMA1_FLAG_TERR3 = 0x00000800, + DMA1_FLAG_GINT4 = 0x00001000, + DMA1_FLAG_TC4 = 0x00002000, + DMA1_FLAG_HT4 = 0x00004000, + DMA1_FLAG_TERR4 = 0x00008000, + DMA1_FLAG_GINT5 = 0x00010000, + DMA1_FLAG_TC5 = 0x00020000, + DMA1_FLAG_HT5 = 0x00040000, + DMA1_FLAG_TERR5 = 0x00080000, + DMA1_FLAG_GINT6 = 0x00100000, + DMA1_FLAG_TC6 = 0x00200000, + DMA1_FLAG_HT6 = 0x00400000, + DMA1_FLAG_TERR6 = 0x00800000, + DMA1_FLAG_GINT7 = 0x01000000, + DMA1_FLAG_TC7 = 0x02000000, + DMA1_FLAG_HT7 = 0x04000000, + DMA1_FLAG_TERR7 = 0x08000000, + + DMA2_FLAG_GINT1 = 0x10000001, + DMA2_FLAG_TC1 = 0x10000002, + DMA2_FLAG_HT1 = 0x10000004, + DMA2_FLAG_TERR1 = 0x10000008, + DMA2_FLAG_GINT2 = 0x10000010, + DMA2_FLAG_TC2 = 0x10000020, + DMA2_FLAG_HT2 = 0x10000040, + DMA2_FLAG_TERR2 = 0x10000080, + DMA2_FLAG_GINT3 = 0x10000100, + DMA2_FLAG_TC3 = 0x10000200, + DMA2_FLAG_HT3 = 0x10000400, + DMA2_FLAG_TERR3 = 0x10000800, + DMA2_FLAG_GINT4 = 0x10001000, + DMA2_FLAG_TC4 = 0x10002000, + DMA2_FLAG_HT4 = 0x10004000, + DMA2_FLAG_TERR4 = 0x10008000, + DMA2_FLAG_GINT5 = 0x10010000, + DMA2_FLAG_TC5 = 0x10020000, + DMA2_FLAG_HT5 = 0x10040000, + DMA2_FLAG_TERR5 = 0x10080000 +} DMA_FLAG_T; + +/** + * @brief DMA Flag + */ +typedef enum +{ + DMA1_INT_FLAG_GINT1 = 0x00000001, + DMA1_INT_FLAG_TC1 = 0x00000002, + DMA1_INT_FLAG_HT1 = 0x00000004, + DMA1_INT_FLAG_TERR1 = 0x00000008, + DMA1_INT_FLAG_GINT2 = 0x00000010, + DMA1_INT_FLAG_TC2 = 0x00000020, + DMA1_INT_FLAG_HT2 = 0x00000040, + DMA1_INT_FLAG_TERR2 = 0x00000080, + DMA1_INT_FLAG_GINT3 = 0x00000100, + DMA1_INT_FLAG_TC3 = 0x00000200, + DMA1_INT_FLAG_HT3 = 0x00000400, + DMA1_INT_FLAG_TERR3 = 0x00000800, + DMA1_INT_FLAG_GINT4 = 0x00001000, + DMA1_INT_FLAG_TC4 = 0x00002000, + DMA1_INT_FLAG_HT4 = 0x00004000, + DMA1_INT_FLAG_TERR4 = 0x00008000, + DMA1_INT_FLAG_GINT5 = 0x00010000, + DMA1_INT_FLAG_TC5 = 0x00020000, + DMA1_INT_FLAG_HT5 = 0x00040000, + DMA1_INT_FLAG_TERR5 = 0x00080000, + DMA1_INT_FLAG_GINT6 = 0x00100000, + DMA1_INT_FLAG_TC6 = 0x00200000, + DMA1_INT_FLAG_HT6 = 0x00400000, + DMA1_INT_FLAG_TERR6 = 0x00800000, + DMA1_INT_FLAG_GINT7 = 0x01000000, + DMA1_INT_FLAG_TC7 = 0x02000000, + DMA1_INT_FLAG_HT7 = 0x04000000, + DMA1_INT_FLAG_TERR7 = 0x08000000, + + DMA2_INT_FLAG_GINT1 = 0x10000001, + DMA2_INT_FLAG_TC1 = 0x10000002, + DMA2_INT_FLAG_HT1 = 0x10000004, + DMA2_INT_FLAG_TERR1 = 0x10000008, + DMA2_INT_FLAG_GINT2 = 0x10000010, + DMA2_INT_FLAG_TC2 = 0x10000020, + DMA2_INT_FLAG_HT2 = 0x10000040, + DMA2_INT_FLAG_TERR2 = 0x10000080, + DMA2_INT_FLAG_GINT3 = 0x10000100, + DMA2_INT_FLAG_TC3 = 0x10000200, + DMA2_INT_FLAG_HT3 = 0x10000400, + DMA2_INT_FLAG_TERR3 = 0x10000800, + DMA2_INT_FLAG_GINT4 = 0x10001000, + DMA2_INT_FLAG_TC4 = 0x10002000, + DMA2_INT_FLAG_HT4 = 0x10004000, + DMA2_INT_FLAG_TERR4 = 0x10008000, + DMA2_INT_FLAG_GINT5 = 0x10010000, + DMA2_INT_FLAG_TC5 = 0x10020000, + DMA2_INT_FLAG_HT5 = 0x10040000, + DMA2_INT_FLAG_TERR5 = 0x10080000 +} DMA_INT_FLAG_T; + +/**@} end of group DMA_Enumerations*/ + + +/** @addtogroup DMA_Structure Data Structure + @{ +*/ + +/** + * @brief DMA Config struct definition + */ +typedef struct +{ + uint32_t peripheralBaseAddr; + uint32_t memoryBaseAddr; + DMA_DIR_T dir; + uint32_t bufferSize; + DMA_PERIPHERAL_INC_T peripheralInc; + DMA_MEMORY_INC_T memoryInc; + DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize; + DMA_MEMORY_DATA_SIZE_T memoryDataSize; + DMA_LOOP_MODE_T loopMode; + DMA_PRIORITY_T priority; + DMA_M2MEN_T M2M; +} DMA_Config_T; + +/**@} end of group DMA_Structure*/ + + +/** @addtogroup DMA_Fuctions Fuctions + @{ +*/ + +/** Reset and configuration */ +void DMA_Reset(DMA_Channel_T *channel); +void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig); +void DMA_ConfigStructInit( DMA_Config_T* dmaConfig); +void DMA_Enable(DMA_Channel_T *channel); +void DMA_Disable(DMA_Channel_T *channel); + +/** Data number */ +void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber); +uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel); + +/** Interrupt and flag */ +void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt); +void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt); +uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag); +void DMA_ClearStatusFlag(uint32_t flag); +uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag); +void DMA_ClearIntFlag(uint32_t flag); + +/**@} end of group DMA_Fuctions*/ +/**@} end of group DMA_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DMA_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h new file mode 100644 index 0000000000..809e2663d7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h @@ -0,0 +1,351 @@ +/*! + * @file apm32f10x_dmc.h + * + * @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#ifndef __APM32F10X_DMC_H +#define __APM32F10X_DMC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMC_Driver DMC Driver + @{ +*/ + +/** @addtogroup DMC_Enumerations Enumerations + @{ +*/ + + +/** + * @brief Bank Address Width + */ +typedef enum +{ + DMC_BANK_WIDTH_1, + DMC_BANK_WIDTH_2 +}DMC_BANK_WIDTH_T; + +/** + * @brief Row Address Width + */ +typedef enum +{ + DMC_ROW_WIDTH_11 = 0x0A, + DMC_ROW_WIDTH_12, + DMC_ROW_WIDTH_13, + DMC_ROW_WIDTH_14, + DMC_ROW_WIDTH_15, + DMC_ROW_WIDTH_16 +}DMC_ROW_WIDTH_T; + +/** + * @brief Column Address Width + */ +typedef enum +{ + DMC_COL_WIDTH_8 = 0x07, + DMC_COL_WIDTH_9, + DMC_COL_WIDTH_10, + DMC_COL_WIDTH_11, + DMC_COL_WIDTH_12, + DMC_COL_WIDTH_13, + DMC_COL_WIDTH_14, + DMC_COL_WIDTH_15 +}DMC_COL_WIDTH_T; + +/** + * @brief CAS Latency Select + */ +typedef enum +{ + DMC_CAS_LATENCY_1, + DMC_CAS_LATENCY_2, + DMC_CAS_LATENCY_3, + DMC_CAS_LATENCY_4 +}DMC_CAS_LATENCY_T; + +/** + * @brief RAS Minimun Time Select + */ +typedef enum +{ + DMC_RAS_MINIMUM_1, + DMC_RAS_MINIMUM_2, + DMC_RAS_MINIMUM_3, + DMC_RAS_MINIMUM_4, + DMC_RAS_MINIMUM_5, + DMC_RAS_MINIMUM_6, + DMC_RAS_MINIMUM_7, + DMC_RAS_MINIMUM_8, + DMC_RAS_MINIMUM_9, + DMC_RAS_MINIMUM_10, + DMC_RAS_MINIMUM_11, + DMC_RAS_MINIMUM_12, + DMC_RAS_MINIMUM_13, + DMC_RAS_MINIMUM_14, + DMC_RAS_MINIMUM_15, + DMC_RAS_MINIMUM_16 +}DMC_RAS_MINIMUM_T; + +/** + * @brief RAS To CAS Delay Time Select + */ +typedef enum +{ + DMC_DELAY_TIME_1, + DMC_DELAY_TIME_2, + DMC_DELAY_TIME_3, + DMC_DELAY_TIME_4, + DMC_DELAY_TIME_5, + DMC_DELAY_TIME_6, + DMC_DELAY_TIME_7, + DMC_DELAY_TIME_8 +}DMC_DELAY_TIME_T; + +/** + * @brief Precharge Period Select + */ +typedef enum +{ + DMC_PRECHARGE_1, + DMC_PRECHARGE_2, + DMC_PRECHARGE_3, + DMC_PRECHARGE_4, + DMC_PRECHARGE_5, + DMC_PRECHARGE_6, + DMC_PRECHARGE_7, + DMC_PRECHARGE_8 +}DMC_PRECHARGE_T; + +/** + * @brief Last Data Next Precharge For Write Time Select + */ +typedef enum +{ + DMC_NEXT_PRECHARGE_1, + DMC_NEXT_PRECHARGE_2, + DMC_NEXT_PRECHARGE_3, + DMC_NEXT_PRECHARGE_4 +}DMC_NEXT_PRECHARGE_T; + +/** + * @brief Auto-Refresh Period Select + */ +typedef enum +{ + DMC_AUTO_REFRESH_1, + DMC_AUTO_REFRESH_2, + DMC_AUTO_REFRESH_3, + DMC_AUTO_REFRESH_4, + DMC_AUTO_REFRESH_5, + DMC_AUTO_REFRESH_6, + DMC_AUTO_REFRESH_7, + DMC_AUTO_REFRESH_8, + DMC_AUTO_REFRESH_9, + DMC_AUTO_REFRESH_10, + DMC_AUTO_REFRESH_11, + DMC_AUTO_REFRESH_12, + DMC_AUTO_REFRESH_13, + DMC_AUTO_REFRESH_14, + DMC_AUTO_REFRESH_15, + DMC_AUTO_REFRESH_16, +}DMC_AUTO_REFRESH_T; + +/** + * @brief Active-to-active Command Period Select + */ +typedef enum +{ + DMC_ATA_CMD_1, + DMC_ATA_CMD_2, + DMC_ATA_CMD_3, + DMC_ATA_CMD_4, + DMC_ATA_CMD_5, + DMC_ATA_CMD_6, + DMC_ATA_CMD_7, + DMC_ATA_CMD_8, + DMC_ATA_CMD_9, + DMC_ATA_CMD_10, + DMC_ATA_CMD_11, + DMC_ATA_CMD_12, + DMC_ATA_CMD_13, + DMC_ATA_CMD_14, + DMC_ATA_CMD_15, + DMC_ATA_CMD_16, +}DMC_ATA_CMD_T; + +/** + * @brief Clock PHASE + */ +typedef enum +{ + DMC_CLK_PHASE_NORMAL, + DMC_CLK_PHASE_REVERSE +}DMC_CLK_PHASE_T; + +/** + * @brief DMC Memory Size + */ +typedef enum +{ + DMC_MEMORY_SIZE_0, + DMC_MEMORY_SIZE_64KB, + DMC_MEMORY_SIZE_128KB, + DMC_MEMORY_SIZE_256KB, + DMC_MEMORY_SIZE_512KB, + DMC_MEMORY_SIZE_1MB, + DMC_MEMORY_SIZE_2MB, + DMC_MEMORY_SIZE_4MB, + DMC_MEMORY_SIZE_8MB, + DMC_MEMORY_SIZE_16MB, + DMC_MEMORY_SIZE_32MB, + DMC_MEMORY_SIZE_64MB, + DMC_MEMORY_SIZE_128MB, + DMC_MEMORY_SIZE_256MB, +}DMC_MEMORY_SIZE_T; + +/** + * @brief Open Banks Of Number + */ +typedef enum +{ + DMC_BANK_NUMBER_1, + DMC_BANK_NUMBER_2, + DMC_BANK_NUMBER_3, + DMC_BANK_NUMBER_4, + DMC_BANK_NUMBER_5, + DMC_BANK_NUMBER_6, + DMC_BANK_NUMBER_7, + DMC_BANK_NUMBER_8, + DMC_BANK_NUMBER_9, + DMC_BANK_NUMBER_10, + DMC_BANK_NUMBER_11, + DMC_BANK_NUMBER_12, + DMC_BANK_NUMBER_13, + DMC_BANK_NUMBER_14, + DMC_BANK_NUMBER_15, + DMC_BANK_NUMBER_16, +}DMC_BANK_NUMBER_T; + +/** + * @brief Full refresh type + */ +typedef enum +{ + DMC_REFRESH_ROW_ONE, //!< Refresh one row + DMC_REFRESH_ROW_ALL, //!< Refresh all row +}DMC_REFRESH_T; + +/** + * @brief Precharge type + */ +typedef enum +{ + DMC_PRECHARGE_IM, //!< Immediate precharge + DMC_PRECHARGE_DELAY, //!< Delayed precharge +}DMC_PRECHARE_T; + + +/**@} end of group DMC_Enumerations*/ + + +/** @addtogroup DMC_Structure Data Structure + @{ +*/ + +/** + * @brief Timing config definition + */ +typedef struct +{ + uint32_t latencyCAS : 2; //!< DMC_CAS_LATENCY_T + uint32_t tRAS : 4; //!< DMC_RAS_MINIMUM_T + uint32_t tRCD : 3; //!< DMC_DELAY_TIME_T + uint32_t tRP : 3; //!< DMC_PRECHARGE_T + uint32_t tWR : 2; //!< DMC_NEXT_PRECHARGE_T + uint32_t tARP : 4; //!< DMC_AUTO_REFRESH_T + uint32_t tCMD : 4; //!< DMC_ATA_CMD_T + uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF + uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF +}DMC_TimingConfig_T; + +/** + * @brief Config struct definition + */ +typedef struct +{ + DMC_MEMORY_SIZE_T memorySize; //!< Memory size(byte) + DMC_BANK_WIDTH_T bankWidth; //!< Number of bank bits + DMC_ROW_WIDTH_T rowWidth; //!< Number of row address bits + DMC_COL_WIDTH_T colWidth; //!< Number of col address bits + DMC_CLK_PHASE_T clkPhase; //!< Clock phase + DMC_TimingConfig_T timing; //!< Timing +}DMC_Config_T; + +/**@} end of group DMC_Structure*/ + + +/** @addtogroup DMC_Fuctions Fuctions + @{ +*/ + + /** Enable / Disable */ +void DMC_Enable(void); +void DMC_Disable(void); +void DMC_EnableInit(void); + +/** Global config */ +void DMC_Config(DMC_Config_T *dmcConfig); +void DMC_ConfigStructInit(DMC_Config_T *dmcConfig); + +/** Address */ +void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth); +void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth); + +/** Timing */ +void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig); +void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig); +void DMC_ConfigStableTimePowerup(uint16_t stableTime); +void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num); +void DMC_ConfigRefreshPeriod(uint16_t period); + +/** Refresh mode */ +void DMC_EixtSlefRefreshMode(void); +void DMC_EnterSlefRefreshMode(void); + +/** Config */ +void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num); +void DMC_EnableUpdateMode(void); +void DMC_EnterPowerdownMode(void); +void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh); +void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh); +void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge); +void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize); +void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase); + +/** read flag */ +uint8_t DMC_ReadSelfRefreshStatus(void); + +/**@} end of group DMC_Fuctions*/ +/**@} end of group DMC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DMC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h new file mode 100644 index 0000000000..23bedc9b02 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h @@ -0,0 +1,119 @@ +/*! + * @file apm32f10x_eint.h + * + * @brief This file contains all the functions prototypes for the EINT firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_EINT_H +#define __APM32F10X_EINT_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EINT_Driver EINT Driver + @{ +*/ + +/** @addtogroup EINT_Enumerations Enumerations + @{ +*/ + +/** + * @brief EINT mode enumeration + */ +typedef enum +{ + EINT_MODE_INTERRUPT = 0x00, + EINT_MODE_EVENT = 0x04 +} EINT_MODE_T; + +/** + * @brief EINT Trigger enumeration + */ +typedef enum +{ + EINT_TRIGGER_RISING = 0x08, + EINT_TRIGGER_FALLING = 0x0C, + EINT_TRIGGER_RISING_FALLING = 0x10 +} EINT_TRIGGER_T; + +typedef enum +{ + EINT_LINE_0 = 0x00001, //!< External interrupt line 0 + EINT_LINE_1 = 0x00002, //!< External interrupt line 1 + EINT_LINE_2 = 0x00004, //!< External interrupt line 2 + EINT_LINE_3 = 0x00008, //!< External interrupt line 3 + EINT_LINE_4 = 0x00010, //!< External interrupt line 4 + EINT_LINE_5 = 0x00020, //!< External interrupt line 5 + EINT_LINE_6 = 0x00040, //!< External interrupt line 6 + EINT_LINE_7 = 0x00080, //!< External interrupt line 7 + EINT_LINE_8 = 0x00100, //!< External interrupt line 8 + EINT_LINE_9 = 0x00200, //!< External interrupt line 9 + EINT_LINE_10 = 0x00400, //!< External interrupt line 10 + EINT_LINE_11 = 0x00800, //!< External interrupt line 11 + EINT_LINE_12 = 0x01000, //!< External interrupt line 12 + EINT_LINE_13 = 0x02000, //!< External interrupt line 13 + EINT_LINE_14 = 0x04000, //!< External interrupt line 14 + EINT_LINE_15 = 0x08000, //!< External interrupt line 15 + EINT_LINE_16 = 0x10000, //!< External interrupt line 16 Connected to the PVD Output + EINT_LINE_17 = 0x20000, //!< External interrupt line 17 Connected to the RTC Alarm event + EINT_LINE_18 = 0x40000, //!< External interrupt line 18 Connected to the USB Device +} EINT_LINE_T; + +/**@} end of group EINT_Enumerations*/ + + +/** @addtogroup EINT_Structure Data Structure + @{ +*/ + +/** + * @brief EINT Config structure definition + */ +typedef struct +{ + uint32_t line; + EINT_MODE_T mode; + EINT_TRIGGER_T trigger; + uint8_t lineCmd; +} EINT_Config_T; + +/**@} end of group EINT_Structure*/ + + +/** @addtogroup EINT_Fuctions Fuctions + @{ +*/ + +/** Reset and configuration */ +void EINT_Reset(void); +void EINT_Config( EINT_Config_T* eintConfig); + +/** Interrupt and flag */ +void EINT_SelectSWInterrupt(uint32_t line); +uint8_t EINT_ReadStatusFlag(EINT_LINE_T line); +void EINT_ClearStatusFlag(uint32_t line); +uint8_t EINT_ReadIntFlag(EINT_LINE_T line); +void EINT_ClearIntFlag(uint32_t line); + +/**@} end of group EINT_Fuctions*/ +/**@} end of group EINT_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __APM32F10X_cplusplus +} +#endif + +#endif /* __EINT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h new file mode 100644 index 0000000000..5b5c82e727 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h @@ -0,0 +1,355 @@ +/*! + * @file apm32f10x_emmc.h + * + * @brief This file contains all the functions prototypes for the EMMC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_EMMC_H +#define __APM32F10X_EMMC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EMMC_Driver EMMC Driver + @{ +*/ + +/** @addtogroup EMMC_Enumerations Enumerations + @{ +*/ + +/** + * @brief EMMC NORSRAM_Bank + */ +typedef enum +{ + EMMC_BANK1_NORSRAM_1 = 0x00000000, + EMMC_BANK1_NORSRAM_2 = 0x00000002, + EMMC_BANK1_NORSRAM_3 = 0x00000004, + EMMC_BANK1_NORSRAM_4 = 0x00000006 +} EMMC_BANK1_NORSRAM_T; + +/** + * @brief EMMC NAND and PC Card Bank + */ +typedef enum +{ + EMMC_BANK2_NAND = 0x00000010, + EMMC_BANK3_NAND = 0x00000100, + EMMC_BANK4_PCCARD = 0x00001000 +} EMMC_BANK_NAND_T; + +/** + * @brief EMMC_Data_Address_Bus_Multiplexing + */ +typedef enum +{ + EMMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000, + EMMC_DATA_ADDRESS_MUX_ENABLE = 0x00000002 +} EMMC_DATA_ADDRESS_MUX_T; + +/** + * @brief EMMC_Memory_Type + */ +typedef enum +{ + EMMC_MEMORY_TYPE_SRAM = 0x00000000, + EMMC_MEMORY_TYPE_PARAM = 0x00000004, + EMMC_MEMORY_TYPE_NOR = 0x00000008 +} EMMC_MEMORY_TYPE_T; + +/** + * @brief EMMC_Data_Width + */ +typedef enum +{ + EMMC_MEMORY_DATA_WIDTH_8BIT = 0x00000000, + EMMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010 +} EMMC_MEMORY_DATA_WIDTH_T; + +/** + * @brief EMMC_Burst_Access_Mode + */ +typedef enum +{ + EMMC_BURST_ACCESS_MODE_DISABLE = 0x00000000, + EMMC_BURST_ACCESS_MODE_ENABLE = 0x00000100 +} EMMC_BURST_ACCESS_MODE_T; + +/** + * @brief EMMC_AsynchronousWait + */ +typedef enum +{ + EMMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000, + EMMC_ASYNCHRONOUS_WAIT_ENABLE = 0x00008000 +} EMMC_ASYNCHRONOUS_WAIT_T; + +/** + * @brief EMMC_Wait_Signal_Polarity + */ +typedef enum +{ + EMMC_WAIT_SIGNAL_POLARITY_LOW = 0x00000000, + EMMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200 +} EMMC_WAIT_SIGNAL_POLARITY_T; + +/** + * @brief EMMC_Wrap_Mode + */ +typedef enum +{ + EMMC_WRAP_MODE_DISABLE = 0x00000000, + EMMC_WRAP_MODE_ENABLE = 0x00000400 +} EMMC_WRAP_MODE_T; + +/** + * @brief EMMC_Wait_Timing + */ +typedef enum +{ + EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000, + EMMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800 +} EMMC_WAIT_SIGNAL_ACTIVE_T; + +/** + * @brief EMMC_Write_Operation + */ +typedef enum +{ + EMMC_WRITE_OPERATION_DISABLE = 0x00000000, + EMMC_WRITE_OPERATION_ENABLE = 0x00001000 +} EMMC_WRITE_OPERATION_T; + +/** + * @brief EMMC_Wait_Signal + */ +typedef enum +{ + EMMC_WAITE_SIGNAL_DISABLE = 0x00000000, + EMMC_WAITE_SIGNAL_ENABLE = 0x00002000 +} EMMC_WAITE_SIGNAL_T; + +/** + * @brief EMMC_Extended_Mode + */ +typedef enum +{ + EMMC_EXTENDEN_MODE_DISABLE = 0x00000000, + EMMC_EXTENDEN_MODE_ENABLE = 0x00004000 +} EMMC_EXTENDEN_MODE_T; + +/** + * @brief EMMC_Write_Burst + */ +typedef enum +{ + EMMC_WRITE_BURST_DISABLE = 0x00000000, + EMMC_WRITE_BURST_ENABLE = 0x00080000 +} EMMC_WRITE_BURST_T; + +/** + * @brief EMMC_WAIT_FEATURE + */ +typedef enum +{ + EMMC_WAIT_FEATURE_DISABLE = 0x00000000, + EMMC_WAIT_FEATURE_ENABLE = 0x00000002 +} EMMC_WAIT_FEATURE_T; + +/** + * @brief EMMC_ECC + */ +typedef enum +{ + EMMC_ECC_DISABLE = 0x00000000, + EMMC_ECC_ENABLE = 0x00000040 +} EMMC_ECC_T; + +/** + * @brief EMMC_ECC_Page_Size + */ +typedef enum +{ + EMMC_ECC_PAGE_SIZE_BYTE_256 = 0x00000000, + EMMC_ECC_PAGE_SIZE_BYTE_512 = 0x00020000, + EMMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000, + EMMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000, + EMMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000, + EMMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000 +} EMMC_ECC_PAGE_SIZE_BYTE_T; + +/** + * @brief EMMC_Access_Mode + */ +typedef enum +{ + EMMC_ACCESS_MODE_A = 0x00000000, + EMMC_ACCESS_MODE_B = 0x10000000, + EMMC_ACCESS_MODE_C = 0x20000000, + EMMC_ACCESS_MODE_D = 0x30000000 +} EMMC_ACCESS_MODE_T; + +/** + * @brief EMMC_Interrupt_sources + */ +typedef enum +{ + EMMC_INT_EDGE_RISING = 0x00000008, + EMMC_INT_LEVEL_HIGH = 0x00000010, + EMMC_INT_EDGE_FALLING = 0x00000020 +} EMMC_INT_T; + +/** + * @brief EMMC_Flags + */ +typedef enum +{ + EMMC_FLAG_EDGE_RISING = 0x00000001, + EMMC_FLAG_LEVEL_HIGH = 0x00000002, + EMMC_FLAG_EDGE_FALLING = 0x00000004, + EMMC_FLAG_FIFO_EMPTY = 0x00000040 +} EMMC_FLAG_T; + +/**@} end of group EMMC_Enumerations*/ + + +/** @addtogroup EMMC_Structure Data Structure + @{ +*/ + +/** + * @brief Timing parameters for NOR/SRAM Banks + */ +typedef struct +{ + uint32_t addressSetupTime; + uint32_t addressHodeTime; + uint32_t dataSetupTime; + uint32_t busTurnaroundTime; + uint32_t clockDivision; + uint32_t dataLatency; + EMMC_ACCESS_MODE_T accessMode; +} EMMC_NORSRAMTimingConfig_T; + +/** + * @brief EMMC NOR/SRAM Config structure + */ +typedef struct +{ + EMMC_BANK1_NORSRAM_T bank; + EMMC_DATA_ADDRESS_MUX_T dataAddressMux; + EMMC_MEMORY_TYPE_T memoryType; + EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth; + EMMC_BURST_ACCESS_MODE_T burstAcceesMode; + EMMC_ASYNCHRONOUS_WAIT_T asynchronousWait; + EMMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity; + EMMC_WRAP_MODE_T wrapMode; + EMMC_WAIT_SIGNAL_ACTIVE_T waitSignalActive; + EMMC_WRITE_OPERATION_T writeOperation; + EMMC_WAITE_SIGNAL_T waiteSignal; + EMMC_EXTENDEN_MODE_T extendedMode; + EMMC_WRITE_BURST_T writeBurst; + EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct; + EMMC_NORSRAMTimingConfig_T* writeTimingStruct; +} EMMC_NORSRAMConfig_T; + +/** + * @brief Timing parameters for NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t setupTime; + uint32_t waitSetupTime; + uint32_t holdSetupTime; + uint32_t HiZSetupTime; +} EMMC_NAND_PCCARDTimingConfig_T; + +/** + * @brief EMMC NAND Config structure + */ +typedef struct +{ + EMMC_BANK_NAND_T bank; + EMMC_WAIT_FEATURE_T waitFeature; + EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth; + EMMC_ECC_T ECC; + EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize; + uint32_t TCLRSetupTime; + uint32_t TARSetupTime; + EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; +} EMMC_NANDConfig_T; + +/** + * @brief EMMC PCCARD Config structure + */ +typedef struct +{ + EMMC_WAIT_FEATURE_T waitFeature; + uint32_t TCLRSetupTime; + uint32_t TARSetupTime; + EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct; +} EMMC_PCCARDConfig_T; + +/**@} end of group EMMC_Structure*/ + +/** @addtogroup EMMC_Fuctions Fuctions + @{ +*/ + +/** EMMC reset */ +void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank); +void EMMC_ResetNAND(EMMC_BANK_NAND_T bank); +void EMMC_ResetPCCard(void); + +/** EMMC Configuration */ +void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig); +void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig); +void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig); +void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig); +void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig); +void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig); + +/** EMMC bank control */ +void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank); +void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank); +void EMMC_EnableNAND(EMMC_BANK_NAND_T bank); +void EMMC_DisableNAND(EMMC_BANK_NAND_T bank); +void EMMC_EnablePCCARD(void); +void EMMC_DisablePCCARD(void); +void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank); +void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank); +uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank); + +/** Interrupt and flag */ +void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt); +void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt); +uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag); +void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag); +uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag); +void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag); + +/**@} end of group EMMC_Fuctions*/ +/**@} end of group EMMC_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_EMMC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h new file mode 100644 index 0000000000..5915185f6f --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h @@ -0,0 +1,251 @@ +/*! + * @file apm32f10x_fmc.h + * + * @brief This file contains all the functions prototypes for the FMC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_FMC_H +#define __APM32F10X_FMC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_Enumerations Enumerations + @{ +*/ + +/** + * @brief Flash Latency + */ +typedef enum +{ + FMC_LATENCY_0, + FMC_LATENCY_1, + FMC_LATENCY_2 +} FMC_LATENCY_T; + +/** + * @brief FMC Status + */ +typedef enum +{ + FMC_STATUS_BUSY = 1, //!< flash busy + FMC_STATUS_ERROR_PG, //!< flash programming error + FMC_STATUS_ERROR_WRP, //!< flash write protection error + FMC_STATUS_COMPLETE, //!< flash operation complete + FMC_STATUS_TIMEOUT //!< flash time out +} FMC_STATUS_T; + +/** + * @brief Option Bytes IWatchdog + */ +typedef enum +{ + OB_IWDT_HARD = 0x0000, + OB_IWDT_SOTF = 0x0001 +} OB_IWDT_T; + +/** + * @brief Option Bytes nRST STOP + */ +typedef enum +{ + OB_STOP_RST = 0x0000, + OB_STOP_NORST = 0x0002 +} OB_STOP_T; + +/** + * @brief Option Bytes nRST STDBY + */ +typedef enum +{ + OB_STDBY_RST = 0x0000, + OB_STDBY_NORST = 0x0004 +} OB_STDBY_T; + +/** + * @brief FMC Interrupts + */ +typedef enum +{ + FMC_INT_ERR, + FMC_INT_OC +} FMC_INT_T; + +/** + * @brief FMC flag + */ +typedef enum +{ + FMC_FLAG_BUSY = 0x00000001, //!< FMC Busy flag + FMC_FLAG_OC = 0x00000020, //!< FMC End of Operation flag + FMC_FLAG_PE = 0x00000004, //!< FMC Program error flag + FMC_FLAG_WPE = 0x00000010, //!< FMC Write protected error flag + FMC_FLAG_OBE = 0x10000001, //!< FMC Option Byte error flag +} FMC_FLAG_T; + +/**@} end of group FMC_Enumerations*/ + +/** @addtogroup FMC_Macros Macros + @{ +*/ + +/** Macros description */ + +/** Values for APM32 Low and Medium density devices */ +#define FLASH_WRP_PAGE_0_3 ((uint32_t)BIT0) //!< Write protection of page 0 to 3 +#define FLASH_WRP_PAGE_4_7 ((uint32_t)BIT1) //!< Write protection of page 4 to 7 +#define FLASH_WRP_PAGE_8_11 ((uint32_t)BIT2) //!< Write protection of page 8 to 11 +#define FLASH_WRP_PAGE_12_15 ((uint32_t)BIT3) //!< Write protection of page 12 to 15 +#define FLASH_WRP_PAGE_16_19 ((uint32_t)BIT4) //!< Write protection of page 16 to 19 +#define FLASH_WRP_PAGE_20_23 ((uint32_t)BIT5) //!< Write protection of page 20 to 23 +#define FLASH_WRP_PAGE_24_27 ((uint32_t)BIT6) //!< Write protection of page 24 to 27 +#define FLASH_WRP_PAGE_28_31 ((uint32_t)BIT7) //!< Write protection of page 28 to 31 + +/** Values for APM32 Medium-density devices */ +#define FLASH_WRP_PAGE_32_35 ((uint32_t)BIT8) //!< Write protection of page 32 to 35 +#define FLASH_WRP_PAGE_36_39 ((uint32_t)BIT9) //!< Write protection of page 36 to 39 +#define FLASH_WRP_PAGE_40_43 ((uint32_t)BIT10) //!< Write protection of page 40 to 43 +#define FLASH_WRP_PAGE_44_47 ((uint32_t)BIT11) //!< Write protection of page 44 to 47 +#define FLASH_WRP_PAGE_48_51 ((uint32_t)BIT12) //!< Write protection of page 48 to 51 +#define FLASH_WRP_PAGE_52_55 ((uint32_t)BIT13) //!< Write protection of page 52 to 55 +#define FLASH_WRP_PAGE_56_59 ((uint32_t)BIT14) //!< Write protection of page 56 to 59 +#define FLASH_WRP_PAGE_60_63 ((uint32_t)BIT15) //!< Write protection of page 60 to 63 +#define FLASH_WRP_PAGE_64_67 ((uint32_t)BIT16) //!< Write protection of page 64 to 67 +#define FLASH_WRP_PAGE_68_71 ((uint32_t)BIT17) //!< Write protection of page 68 to 71 +#define FLASH_WRP_PAGE_72_75 ((uint32_t)BIT18) //!< Write protection of page 72 to 75 +#define FLASH_WRP_PAGE_76_79 ((uint32_t)BIT19) //!< Write protection of page 76 to 79 +#define FLASH_WRP_PAGE_80_83 ((uint32_t)BIT20) //!< Write protection of page 80 to 83 +#define FLASH_WRP_PAGE_84_87 ((uint32_t)BIT21) //!< Write protection of page 84 to 87 +#define FLASH_WRP_PAGE_88_91 ((uint32_t)BIT22) //!< Write protection of page 88 to 91 +#define FLASH_WRP_PAGE_92_95 ((uint32_t)BIT23) //!< Write protection of page 92 to 95 +#define FLASH_WRP_PAGE_96_99 ((uint32_t)BIT24) //!< Write protection of page 96 to 99 +#define FLASH_WRP_PAGE_100_103 ((uint32_t)BIT25) //!< Write protection of page 100 to 103 +#define FLASH_WRP_PAGE_104_107 ((uint32_t)BIT26) //!< Write protection of page 104 to 107 +#define FLASH_WRP_PAGE_108_111 ((uint32_t)BIT27) //!< Write protection of page 108 to 111 +#define FLASH_WRP_PAGE_112_115 ((uint32_t)BIT28) //!< Write protection of page 112 to 115 +#define FLASH_WRP_PAGE_116_119 ((uint32_t)BIT29) //!< Write protection of page 116 to 119 +#define FLASH_WRP_PAGE_120_123 ((uint32_t)BIT30) //!< Write protection of page 120 to 123 +#define FLASH_WRP_PAGE_124_127 ((uint32_t)BIT31) //!< Write protection of page 124 to 127 + +/** Values only for APM32 High-density devices */ +#define FLASH_WRP_PAGE_0_1 ((uint32_t)BIT0) //!< Write protection of page 0 to 1 +#define FLASH_WRP_PAGE_2_3 ((uint32_t)BIT1) //!< Write protection of page 2 to 3 +#define FLASH_WRP_PAGE_4_5 ((uint32_t)BIT2) //!< Write protection of page 4 to 5 +#define FLASH_WRP_PAGE_6_7 ((uint32_t)BIT3) //!< Write protection of page 6 to 7 +#define FLASH_WRP_PAGE_8_9 ((uint32_t)BIT4) //!< Write protection of page 8 to 9 +#define FLASH_WRP_PAGE_10_11 ((uint32_t)BIT5) //!< Write protection of page 10 to 11 +#define FLASH_WRP_PAGE_12_13 ((uint32_t)BIT6) //!< Write protection of page 12 to 13 +#define FLASH_WRP_PAGE_14_15 ((uint32_t)BIT7) //!< Write protection of page 14 to 15 +#define FLASH_WRP_PAGE_16_17 ((uint32_t)BIT8) //!< Write protection of page 16 to 17 +#define FLASH_WRP_PAGE_18_19 ((uint32_t)BIT9) //!< Write protection of page 18 to 19 +#define FLASH_WRP_PAGE_20_21 ((uint32_t)BIT10) //!< Write protection of page 20 to 21 +#define FLASH_WRP_PAGE_22_23 ((uint32_t)BIT11) //!< Write protection of page 22 to 23 +#define FLASH_WRP_PAGE_24_25 ((uint32_t)BIT12) //!< Write protection of page 24 to 25 +#define FLASH_WRP_PAGE_26_27 ((uint32_t)BIT13) //!< Write protection of page 26 to 27 +#define FLASH_WRP_PAGE_28_29 ((uint32_t)BIT14) //!< Write protection of page 28 to 29 +#define FLASH_WRP_PAGE_30_31 ((uint32_t)BIT15) //!< Write protection of page 30 to 31 +#define FLASH_WRP_PAGE_32_33 ((uint32_t)BIT16) //!< Write protection of page 32 to 33 +#define FLASH_WRP_PAGE_34_35 ((uint32_t)BIT17) //!< Write protection of page 34 to 35 +#define FLASH_WRP_PAGE_36_37 ((uint32_t)BIT18) //!< Write protection of page 36 to 37 +#define FLASH_WRP_PAGE_38_39 ((uint32_t)BIT19) //!< Write protection of page 38 to 39 +#define FLASH_WRP_PAGE_40_41 ((uint32_t)BIT20) //!< Write protection of page 40 to 41 +#define FLASH_WRP_PAGE_42_43 ((uint32_t)BIT21) //!< Write protection of page 42 to 43 +#define FLASH_WRP_PAGE_44_45 ((uint32_t)BIT22) //!< Write protection of page 44 to 45 +#define FLASH_WRP_PAGE_46_47 ((uint32_t)BIT23) //!< Write protection of page 46 to 47 +#define FLASH_WRP_PAGE_48_49 ((uint32_t)BIT24) //!< Write protection of page 48 to 49 +#define FLASH_WRP_PAGE_50_51 ((uint32_t)BIT25) //!< Write protection of page 50 to 51 +#define FLASH_WRP_PAGE_52_53 ((uint32_t)BIT26) //!< Write protection of page 52 to 53 +#define FLASH_WRP_PAGE_54_55 ((uint32_t)BIT27) //!< Write protection of page 54 to 55 +#define FLASH_WRP_PAGE_56_57 ((uint32_t)BIT28) //!< Write protection of page 56 to 57 +#define FLASH_WRP_PAGE_58_59 ((uint32_t)BIT29) //!< Write protection of page 58 to 59 +#define FLASH_WRP_PAGE_60_61 ((uint32_t)BIT30) //!< Write protection of page 60 to 61 +#define FLASH_WRP_PAGE_62_127 ((uint32_t)BIT31) //!< Write protection of page 62 to 127 +#define FMC_WRP_PAGE_ALL ((uint32_t)0xFFFFFFFF) //!< Write protection of page all */ + +/**@} end of group FMC_Macros*/ + +/** @addtogroup FMC_Structure Data Structure + @{ +*/ + +/** + * @brief User Option byte config struct definition + */ +typedef struct +{ + OB_IWDT_T iwdtSet; + OB_STOP_T stopSet; + OB_STDBY_T stdbySet; +} FMC_UserConfig_T; + +/**@} end of group FMC_Structure*/ + +/** @addtogroup FMC_Fuctions Fuctions + @{ +*/ + +/** Initialization and Configuration */ +void FMC_ConfigLatency(FMC_LATENCY_T latency); +void FMC_EnableHalfCycleAccess(void); +void FMC_DisableHalfCycleAccess(void); +void FMC_EnablePrefetchBuffer(void); +void FMC_DisablePrefetchBuffer(void); + +/** Lock management */ +void FMC_Unlock(void); +void FMC_Lock(void); + +/** Erase management */ +FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr); +FMC_STATUS_T FMC_EraseAllPage(void); +FMC_STATUS_T FMC_EraseOptionBytes(void); + +/** Read Write management */ +FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data); +FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data); +FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data); +FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page); +FMC_STATUS_T FMC_EnableReadOutProtection(void); +FMC_STATUS_T FMC_DisableReadOutProtection(void); +FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig); +uint32_t FMC_ReadUserOptionByte(void); +uint32_t FMC_ReadOptionByteWriteProtection(void); +uint8_t FMC_GetReadProtectionStatus(void); +uint8_t FMC_ReadPrefetchBufferStatus(void); + +/** Interrupts and flags */ +void FMC_EnableInterrupt(FMC_INT_T interrupt); +void FMC_DisableInterrupt(FMC_INT_T interrupt); +uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag); +void FMC_ClearStatusFlag(FMC_FLAG_T flag); + +/** Status management */ +FMC_STATUS_T FMC_ReadStatus(void); +FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut); + +/**@} end of group FMC_Fuctions*/ +/**@} end of group FMC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_FMC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h new file mode 100644 index 0000000000..e78ac91b01 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h @@ -0,0 +1,247 @@ +/*! + * @file apm32f10x_gpio.h + * + * @brief This file contains all the functions prototypes for the GPIO firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_GPIO_H +#define __APM32F10X_GPIO_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_Enumerations Enumerations + @{ +*/ + +/** + * @brief GPIO Output Maximum frequency selection + */ +typedef enum +{ + GPIO_SPEED_10MHz = 1, + GPIO_SPEED_2MHz, + GPIO_SPEED_50MHz +}GPIO_SPEED_T; + +/** + * @brief Configuration Mode enumeration + */ +typedef enum +{ + GPIO_MODE_ANALOG = 0x0, //!< Analog mode + GPIO_MODE_IN_FLOATING = 0x04, //!< Floating input + GPIO_MODE_IN_PD = 0x28, //!< Input with pull-down + GPIO_MODE_IN_PU = 0x48, //!< Input with pull-up + GPIO_MODE_OUT_PP = 0x80, //!< General purpose output push-pull + GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain + GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull + GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain +}GPIO_MODE_T; + +/** + * @brief Definition of the GPIO pins + */ +typedef enum +{ + GPIO_PIN_0 = ((uint16_t)BIT0), + GPIO_PIN_1 = ((uint16_t)BIT1), + GPIO_PIN_2 = ((uint16_t)BIT2), + GPIO_PIN_3 = ((uint16_t)BIT3), + GPIO_PIN_4 = ((uint16_t)BIT4), + GPIO_PIN_5 = ((uint16_t)BIT5), + GPIO_PIN_6 = ((uint16_t)BIT6), + GPIO_PIN_7 = ((uint16_t)BIT7), + GPIO_PIN_8 = ((uint16_t)BIT8), + GPIO_PIN_9 = ((uint16_t)BIT9), + GPIO_PIN_10 = ((uint16_t)BIT10), + GPIO_PIN_11 = ((uint16_t)BIT11), + GPIO_PIN_12 = ((uint16_t)BIT12), + GPIO_PIN_13 = ((uint16_t)BIT13), + GPIO_PIN_14 = ((uint16_t)BIT14), + GPIO_PIN_15 = ((uint16_t)BIT15), + GPIO_PIN_ALL = ((uint32_t)0XFFFF), +} GPIO_PIN_T; + +/** + * @brief GPIO remap type define + */ +typedef enum +{ + GPIO_NO_REMAP_SPI1 = 0x00000010, + GPIO_REMAP_SPI1 = 0x00000011, + + GPIO_NO_REMAP_I2C1 = 0x00000110, + GPIO_REMAP_I2C1 = 0x00000111, + + GPIO_NO_REMAP_USART1 = 0x00000210, + GPIO_REMAP_USART1 = 0x00000211, + + GPIO_NO_REMAP_USART2 = 0x00000310, + GPIO_REMAP_USART2 = 0x00000311, + + GPIO_NO_REMAP_USART3 = 0x00000430, + GPIO_PARTIAL_REMAP_USART3 = 0x00000431, + GPIO_FULL_REMAP_USART3 = 0x00000433, + + GPIO_NO_REMAP_TMR1 = 0x00000630, + GPIO_PARTIAL_REMAP_TMR1 = 0x00000631, + GPIO_FULL_REMAP_TMR1 = 0x00000633, + + GPIO_NO_REMAP_TMR2 = 0x00000830, + GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831, + GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832, + GPIO_FULL_REMAP_TMR2 = 0x00000833, + + GPIO_NO_REMAP_TMR3 = 0x00000A30, + GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32, + GPIO_FULL_REMAP_TMR3 = 0x00000A33, + + GPIO_NO_REMAP_TMR4 = 0x00000C10, + GPIO_REMAP_TMR4 = 0x00000C11, + + GPIO_NO_REMAP_CAN1 = 0x00000D30, + GPIO_REMAP1_CAN1 = 0x00000D32, + GPIO_REMAP2_CAN1 = 0x00000D33, + + GPIO_NO_REMAP_PD01 = 0x00000F10, + GPIO_REMAP_PD01 = 0x00000F11, + + GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010, + GPIO_REMAP_TMR5CH4_LSI = 0x00001011, + + GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110, + GPIO_REMAP_ADC1_ETRGINJ = 0x00001111, + + GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210, + GPIO_REMAP_ADC1_ETRGREG = 0x00001211, + + GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310, + GPIO_REMAP_ADC2_ETRGINJ = 0x00001311, + + GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410, + GPIO_REMAP_ADC2_ETRGREG = 0x00001411, + + GPIO_NO_REMAP_CAN2 = 0x00001610, + GPIO_REMAP_CAN2 = 0x00001611, + + GPIO_NO_REMAP_SWJ = 0x00001870, + GPIO_REMAP_SWJ_NOJTRST = 0x00001871, + GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872, + GPIO_REMAP_SWJ_DISABLE = 0x00001874, + + GPIO_NO_REMAP_EMMC_NADV = 0x00010A10, + GPIO_REMAP_EMMC_NADV = 0x00010A11, +}GPIO_REMAP_T; + +/** + * @brief gpio port source define + */ +typedef enum +{ + GPIO_PORT_SOURCE_A, + GPIO_PORT_SOURCE_B, + GPIO_PORT_SOURCE_C, + GPIO_PORT_SOURCE_D, + GPIO_PORT_SOURCE_E, + GPIO_PORT_SOURCE_F, + GPIO_PORT_SOURCE_G, +}GPIO_PORT_SOURCE_T; + +/** + * @brief gpio pin source define + */ +typedef enum +{ + GPIO_PIN_SOURCE_0, + GPIO_PIN_SOURCE_1, + GPIO_PIN_SOURCE_2, + GPIO_PIN_SOURCE_3, + GPIO_PIN_SOURCE_4, + GPIO_PIN_SOURCE_5, + GPIO_PIN_SOURCE_6, + GPIO_PIN_SOURCE_7, + GPIO_PIN_SOURCE_8, + GPIO_PIN_SOURCE_9, + GPIO_PIN_SOURCE_10, + GPIO_PIN_SOURCE_11, + GPIO_PIN_SOURCE_12, + GPIO_PIN_SOURCE_13, + GPIO_PIN_SOURCE_14, + GPIO_PIN_SOURCE_15, +}GPIO_PIN_SOURCE_T; + +/**@} end of group GPIO_Enumerations*/ + + +/** @addtogroup GPIO_Structure Data Structure + @{ +*/ + +/** + * @brief GPIO Config structure definition + */ +typedef struct +{ + uint16_t pin; + GPIO_SPEED_T speed; + GPIO_MODE_T mode; +}GPIO_Config_T; + +/**@} end of group GPIO_Structure*/ + +/** @addtogroup GPIO_Fuctions Fuctions + @{ +*/ + +/** Reset and common Configuration */ +void GPIO_Reset(GPIO_T* port); +void GPIO_AFIOReset(void); +void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig); +void GPIO_StructInit(GPIO_Config_T* gpioConfig); + +/** Read */ +uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin); +uint16_t GPIO_ReadInputPort(GPIO_T* port); +uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin); +uint16_t GPIO_ReadOutputPort(GPIO_T* port); + +/** Write */ +void GPIO_SetBits(GPIO_T* port, uint16_t pin); +void GPIO_ResetBits(GPIO_T* port, uint16_t pin); +void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue); +void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal); + +/** GPIO Configuration */ +void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin); +void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); +void GPIO_EnableEventOutput(void); +void GPIO_DisableEventOutput(void); +void GPIO_ConfigPinRemap(GPIO_REMAP_T remap); +void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); + +/**@} end of group GPIO_Fuctions*/ +/**@} end of group GPIO_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_GPIO_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h new file mode 100644 index 0000000000..49c6537e11 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h @@ -0,0 +1,334 @@ +/*! + * @file apm32f10x_i2c.h + * + * @brief This file contains all the functions prototypes for the I2C firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_I2C_H +#define __APM32F10X_I2C_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_Enumerations Enumerations + @{ +*/ + +/** + * @brief I2C Mode + */ +typedef enum +{ + I2C_MODE_I2C = 0x0000, + I2C_MODE_SMBUUSDEVICE = 0x0002, + I2C_MODE_SMBUSHOST = 0x000A +} I2C_MODE_T; + +/** + * @brief I2C duty cycle in fast mode + */ +typedef enum +{ + I2C_DUTYCYCLE_16_9 = 0x4000, + I2C_DUTYCYCLE_2 = 0xBFFF +} I2C_DUTYCYCLE_T; + +/** + * @brief I2C acknowledgement + */ +typedef enum +{ + I2C_ACK_DISABLE, + I2C_ACK_ENABLE +} I2C_ACK_T; + +/** + * @brief I2C acknowledged address + */ +typedef enum +{ + I2C_ACK_ADDRESS_7BIT = 0x4000, + I2C_ACK_ADDRESS_10BIT = 0xC000 +} I2C_ACK_ADDRESS_T; + +/** + * @brief I2C interrupts definition + */ +typedef enum +{ + I2C_INT_BUF = 0x0400, + I2C_INT_EVT = 0x0200, + I2C_INT_ERR = 0x0100 +} I2C_INT_T; + +/** + * @brief I2C transfer direction + */ + +typedef enum +{ + I2C_DIRECTION_TX, + I2C_DIRECTION_RX +} I2C_DIRECTION_T; + +/** + * @brief I2C Register + */ +typedef enum +{ + I2C_REGISTER_CTRL1, + I2C_REGISTER_CTRL2, + I2C_REGISTER_SADDR1, + I2C_REGISTER_SADDR2, + I2C_REGISTER_DATA, + I2C_REGISTER_STS1, + I2C_REGISTER_STS2, + I2C_REGISTER_CLKCTRL, + I2C_REGISTER_RISETMAX, + I2C_REGISTER_SWITCH +} I2C_REGISTER_T; + +/** + * @brief I2C NCAK position + */ +typedef enum +{ + I2C_NACK_POSITION_NEXT, + I2C_NACK_POSITION_CURRENT +} I2C_NACK_POSITION_T; + +/** + * @brief I2C SMBus alert pin level + */ +typedef enum +{ + I2C_SMBUSALER_LOW, + I2C_SMBUSALER_HIGH +} I2C_SMBUSALER_T; + +/** + * @brief I2C PEC position + */ +typedef enum +{ + I2C_PEC_POSITION_NEXT, + I2C_PEC_POSITION_CURRENT +} I2C_PEC_POSITION_T; + +/** + * @brief I2C Events + */ +typedef enum +{ + /** I2C Master Events */ + /** Event 5: Communication start event */ + I2C_EVENT_MASTER_MODE_SELECT = 0x00030001, //!< BUSBSYFLG, MSFLG and STARTFLG flag + + /** + * Event 6: 7-bit Address Acknowledge + * in case of master receiver + */ + I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = 0x00070082, //!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */ + I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = 0x00030002, //!< BUSBSYFLG, MSFLG and ADDRFLG flags */ + /** + * Event 9: Master has sent the first byte + * in 10-bit address mode + */ + I2C_EVENT_MASTER_MODE_ADDRESS10 = 0x00030008, //!< BUSBSYFLG, MSFLG and ADDR10FLG flags */ + + /** Master RECEIVER mode */ + /** Event 7 */ + I2C_EVENT_MASTER_BYTE_RECEIVED = 0x00030040, //!< BUSBSYFLG, MSFLG and RXBNEFLG flags */ + + /** Master TRANSMITTER mode */ + /** Event 8 */ + I2C_EVENT_MASTER_BYTE_TRANSMITTING = 0x00070080, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */ + /** Event 8_2 */ + I2C_EVENT_MASTER_BYTE_TRANSMITTED = 0x00070084, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */ + + + /** EV1 (all the events below are variants of EV1) */ + /** 1, Case of One Single Address managed by the slave */ + I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = 0x00020002, //!< BUSBSYFLG and ADDRFLG flags */ + I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = 0x00060082, //!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */ + + /** 2, Case of Dual address managed by the slave */ + I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = 0x00820000, //!< DUALF and BUSBSYFLG flags */ + I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = 0x00860080, //!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */ + + /** 3, Case of General Call enabled for the slave */ + I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = 0x00120000, //!< GENCALL and BUSBSYFLG flags */ + + + /** Slave RECEIVER mode */ + /** EV2 */ + I2C_EVENT_SLAVE_BYTE_RECEIVED = 0x00020040, //!< BUSBSYFLG and RXBNEFLG flags */ + /** EV4 */ + I2C_EVENT_SLAVE_STOP_DETECTED = 0x00000010, //!< STOPFLG flag */ + + /** Slave TRANSMITTER mode */ + /** EV3 */ + I2C_EVENT_SLAVE_BYTE_TRANSMITTED = 0x00060084, //!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */ + I2C_EVENT_SLAVE_BYTE_TRANSMITTING = 0x00060080, //!< TRFLG, BUSBSYFLG and TXBEFLG flags */ + /** EV3_2 */ + I2C_EVENT_SLAVE_ACK_FAILURE = 0x00000400, //!< AEFLG flag */ +} I2C_EVENT_T; + +/** + * @brief I2C flags + */ +typedef enum +{ + /** STS2 register flags */ + I2C_FLAG_DUALADDR, + I2C_FLAG_SMMHADDR, + I2C_FLAG_SMBDADDR, + I2C_FLAG_GENCALL, + I2C_FLAG_TR, + I2C_FLAG_BUSBSY, + I2C_FLAG_MS, + + /** STS1 register flags */ + I2C_FLAG_SMBALT, + I2C_FLAG_TTE, + I2C_FLAG_PECE, + I2C_FLAG_OVRUR, + I2C_FLAG_AE, + I2C_FLAG_AL, + I2C_FLAG_BERR, + I2C_FLAG_TXBE, + I2C_FLAG_RXBNE, + I2C_FLAG_STOP, + I2C_FLAG_ADDR10, + I2C_FLAG_BTC, + I2C_FLAG_ADDR, + I2C_FLAG_START, +} I2C_FLAG_T; + +/** + * @brief I2C interrupt + */ +typedef enum +{ + I2C_INT_FLAG_SMBALT = 0x01008000, + I2C_INT_FLAG_TTE = 0x01004000, + I2C_INT_FLAG_PECE = 0x01001000, + I2C_INT_FLAG_OVRUR = 0x01000800, + I2C_INT_FLAG_AE = 0x01000400, + I2C_INT_FLAG_AL = 0x01000200, + I2C_INT_FLAG_BERR = 0x01000100, + I2C_INT_FLAG_TXBE = 0x06000080, + I2C_INT_FLAG_RXBNE = 0x06000040, + I2C_INT_FLAG_STOP = 0x02000010, + I2C_INT_FLAG_ADDR10 = 0x02000008, + I2C_INT_FLAG_BTC = 0x02000004, + I2C_INT_FLAG_ADDR = 0x02000002, + I2C_INT_FLAG_START = 0x02000001, +} I2C_INT_FLAG_T; + +/**@} end of group I2C_Enumerations*/ + +/** @addtogroup I2C_Structure Data Structure + @{ +*/ + +/** + * @brief I2C Config structure definition + */ +typedef struct +{ + uint32_t clockSpeed; + I2C_MODE_T mode; + I2C_DUTYCYCLE_T dutyCycle; + uint16_t ownAddress1; + I2C_ACK_T ack; + I2C_ACK_ADDRESS_T ackAddress; +} I2C_Config_T; + +/**@} end of group I2C_Structure*/ + + +/** @addtogroup I2C_Fuctions Fuctions + @{ +*/ + +/** I2C reset and configuration */ +void I2C_Reset(I2C_T* i2c); +void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig); +void I2C_ConfigStructInit(I2C_Config_T* i2cConfig); +void I2C_Enable(I2C_T* i2c); +void I2C_Disable(I2C_T* i2c); +void I2C_EnableGenerateStart(I2C_T* i2c); +void I2C_DisableGenerateStart(I2C_T* i2c); +void I2C_EnableGenerateStop(I2C_T* i2c); +void I2C_DisableGenerateStop(I2C_T* i2c); +void I2C_EnableAcknowledge(I2C_T* i2c); +void I2C_DisableAcknowledge(I2C_T* i2c); +void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address); +void I2C_EnableDualAddress(I2C_T* i2c); +void I2C_DisableDualAddress(I2C_T* i2c); +void I2C_EnableGeneralCall(I2C_T* i2c); +void I2C_DisableGeneralCall(I2C_T* i2c); + +/** Transmit Configuration */ +void I2C_TxData(I2C_T* i2c, uint8_t data); +uint8_t I2C_RxData(I2C_T* i2c); +void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction); +uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister); +void I2C_EnableSoftwareReset(I2C_T* i2c); +void I2C_DisableSoftwareReset(I2C_T* i2c); +void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition); +void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState); +void I2C_EnablePECTransmit(I2C_T* i2c); +void I2C_DisablePECTransmit(I2C_T* i2c); +void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition); +void I2C_EnablePEC(I2C_T* i2c); +void I2C_DisablePEC(I2C_T* i2c); +uint8_t I2C_ReadPEC(I2C_T* i2c); +void I2C_EnableARP(I2C_T* i2c); +void I2C_DisableARP(I2C_T* i2c); +void I2C_EnableStretchClock(I2C_T* i2c); +void I2C_DisableStretchClock(I2C_T* i2c); +void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle); + +/** DMA */ +void I2C_EnableDMA(I2C_T* i2c); +void I2C_DisableDMA(I2C_T* i2c); +void I2C_EnableDMALastTransfer(I2C_T* i2c); +void I2C_DisableDMALastTransfer(I2C_T* i2c); + +/** Interrupts and flags */ +void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt); +void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt); +uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent); +uint32_t I2C_ReadLastEvent(I2C_T* i2c); +uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); +void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); +uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); +void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); + +/**@} end of group I2C_Fuctions*/ +/**@} end of group I2C_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_I2C_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h new file mode 100644 index 0000000000..45c2c34c4d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h @@ -0,0 +1,108 @@ +/*! + * @file apm32f10x_iwdt.h + * + * @brief This file contains all the functions prototypes for the IWDT firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_IWDT_H +#define __APM32F10X_IWDT_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup IWDT_Driver IWDT Driver + @{ +*/ + +/** @addtogroup IWDT_Enumerations Enumerations + @{ +*/ + +/** + * @brief IWDT KEYWORD define + */ +typedef enum +{ + IWDT_KEYWORD_RELOAD = 0xAAAA, + IWDT_KEYWORD_ENABLE = 0xCCCC +}IWDT_KEYWORD_T; + +/** + * @brief IWDT Write Access define + */ +typedef enum +{ + IWDT_WRITEACCESS_ENABLE = 0x5555, + IWDT_WRITEACCESS_DISABLE = 0x0000 +}IWDT_WRITEACCESS_T; + +/** + * @brief IWDT Divider + */ +typedef enum +{ + IWDT_DIVIDER_4 = 0x00, + IWDT_DIVIDER_8 = 0x01, + IWDT_DIVIDER_16 = 0x02, + IWDT_DIVIDER_32 = 0x03, + IWDT_DIVIDER_64 = 0x04, + IWDT_DIVIDER_128 = 0x05, + IWDT_DIVIDER_256 = 0x06 +}IWDT_DIVIDER_T; + +/** + * @brief IWDT Flag + */ +typedef enum +{ + IWDT_FLAG_PSCU = BIT0, + IWDT_FLAG_CNTU = BIT1 +}IWDT_FLAG_T; + +/**@} end of group IWDT_Enumerations*/ + + +/** @addtogroup IWDT_Fuctions Fuctions + @{ +*/ + +/** Enable IWDT */ +void IWDT_Enable(void); + +/** Refresh IWDT */ +void IWDT_Refresh(void); + +/** Counter reload */ +void IWDT_ConfigReload(uint16_t reload); + +/** Divider */ +void IWDT_ConfigDivider(uint8_t div); + +/** Write Access */ +void IWDT_EnableWriteAccess(void); +void IWDT_DisableWriteAccess(void); + +/** flag */ +uint8_t IWDT_ReadStatusFlag(uint16_t flag); + +/**@} end of group IWDT_Fuctions*/ +/**@} end of group IWDT_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_IWDT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h new file mode 100644 index 0000000000..fbc8171da0 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h @@ -0,0 +1,100 @@ +/*! + * @file apm32f10x_misc.h + * + * @brief This file provides all the miscellaneous firmware functions. + * Include NVIC,SystemTick and Power management. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_MISC_H +#define __APM32F10X_MISC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup MISC_Driver MISC Driver + @{ +*/ + +/** @addtogroup MISC_Enumerations Enumerations + @{ +*/ + +/** + * @brief NVIC Vect table + */ +typedef enum +{ + NVIC_VECT_TAB_RAM = 0x20000000, + NVIC_VECT_TAB_FLASH = 0x08000000, +}NVIC_VECT_TAB_T; + +/** + * @brief system low power mode + */ +typedef enum +{ + NVIC_LOWPOWER_SEVONPEND = 0x10, + NVIC_LOWPOWER_SLEEPDEEP = 0x04, + NVIC_LOWPOWER_SLEEPONEXIT = 0x02 +}NVIC_LOWPOWER_T; + +/** + * @brief nvic priority group + */ +typedef enum +{ + NVIC_PRIORITY_GROUP_0 = 0x700, //!< 0 bits for pre-emption priority,4 bits for subpriority + NVIC_PRIORITY_GROUP_1 = 0x600, //!< 1 bits for pre-emption priority,3 bits for subpriority + NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority + NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority + NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority +}NVIC_PRIORITY_GROUP_T; + +/** + * @brief SysTick Clock source + */ +typedef enum +{ + SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00, + SYSTICK_CLK_SOURCE_HCLK = 0x01 +}SYSTICK_CLK_SOURCE_T; + +/**@} end of group MISC_Enumerations*/ + + +/** @addtogroup MISC_Fuctions Fuctions + @{ +*/ + +/** NVIC */ +void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup); +void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority); +void NVIC_DisableIRQRequest(IRQn_Type irq); + +/** Vector Table */ +void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset); + +/** Power */ +void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode); +void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode); + +/** Systick */ +void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_MISC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h new file mode 100644 index 0000000000..873686a220 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h @@ -0,0 +1,97 @@ +/*! + * @file apm32f10x_pmu.h + * + * @brief This file contains all the functions prototypes for the PMU firmware library. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_PMU_H +#define __APM32F10X_PMU_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup PMU_Driver PMU Driver + @{ +*/ + +/** @addtogroup PMU_Enumerations Enumerations + @{ +*/ + +typedef enum +{ + PMU_PVD_LEVEL_2V2 = 0x00, //!< PVD detection level set to 2.2V + PMU_PVD_LEVEL_2V3 = 0x01, //!< PVD detection level set to 2.3V + PMU_PVD_LEVEL_2V4 = 0x02, //!< PVD detection level set to 2.4V + PMU_PVD_LEVEL_2V5 = 0x03, //!< PVD detection level set to 2.5V + PMU_PVD_LEVEL_2V6 = 0x04, //!< PVD detection level set to 2.6V + PMU_PVD_LEVEL_2V7 = 0x05, //!< PVD detection level set to 2.7V + PMU_PVD_LEVEL_2V8 = 0x06, //!< PVD detection level set to 2.8V + PMU_PVD_LEVEL_2V9 = 0x07, //!< PVD detection level set to 2.9V +} PMU_PVD_LEVEL_T; + +typedef enum +{ + PMU_REGULATOR_ON = 0x00, + PMU_REGULATOR_LOWPOWER = 0x01 +} PMU_REGULATOR_T; + +typedef enum +{ + PMU_STOP_ENTRY_WFI = 0x01, + PMU_STOP_ENTRY_WFE = 0x02 +} PMU_STOP_ENTRY_T; + +typedef enum +{ + PMU_FLAG_WUE, + PMU_FLAG_SB, + PMU_FLAG_PVDO +} PMU_FLAG_T; + +/**@} end of group PMU_Enumerations*/ + + +/** @addtogroup PMU_Fuctions Fuctions + @{ +*/ + +/** PMU Reset */ +void PMU_Reset(void); + +/** Configuration and Operation modes */ +void PMU_EnableBackupAccess(void); +void PMU_DisableBackupAccess(void); +void PMU_EnablePVD(void); +void PMU_DisablePVD(void); +void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level); +void PMU_EnableWakeUpPin(void); +void PMU_DisableWakeUpPin(void); +void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry); +void PMU_EnterSTANDBYMode(void); + +/** flags */ +uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag); +void PMU_ClearStatusFlag(PMU_FLAG_T flag); + +/**@} end of group PMU_Fuctions*/ +/**@} end of group PMU_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_PMU_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h new file mode 100644 index 0000000000..8a373eb326 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h @@ -0,0 +1,337 @@ +/*! + * @file apm32f10x_qspi.h + * + * @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_QSPI_H +#define __APM32F10X_QSPI_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_Enumerations Enumerations + @{ +*/ + +/** + * @brief Frame format + */ +typedef enum +{ + QSPI_FRF_STANDARD, //!< Standard mode + QSPI_FRF_DUAL, //!< Dual SPI + QSPI_FRF_QUAD //!< QUAD SPI +}QSPI_FRF_T; + +/** + * @brief Transmission mode + */ +typedef enum +{ + QSPI_TRANS_MODE_TX_RX, //!< TX and RX mode + QSPI_TRANS_MODE_TX, //!< TX mode only + QSPI_TRANS_MODE_RX, //!< RX mode only + QSPI_TRANS_MODE_EEPROM_READ, //!< EEPROM read mode +}QSPI_TRANS_MODE_T; + +/** + * @brief Clock polarity + */ +typedef enum +{ + QSPI_CLKPOL_LOW, + QSPI_CLKPOL_HIGH, +}QSPI_CLKPOL_T; + +/** + * @brief Clock phase + */ +typedef enum +{ + QSPI_CLKPHA_1EDGE, + QSPI_CLKPHA_2EDGE +}QSPI_CLKPHA_T; + +/** + * @brief Data format size + */ +typedef enum +{ + QSPI_DFS_4BIT = 3, + QSPI_DFS_5BIT, + QSPI_DFS_6BIT, + QSPI_DFS_7BIT, + QSPI_DFS_8BIT, + QSPI_DFS_9BIT, + QSPI_DFS_10BIT, + QSPI_DFS_11BIT, + QSPI_DFS_12BIT, + QSPI_DFS_13BIT, + QSPI_DFS_14BIT, + QSPI_DFS_15BIT, + QSPI_DFS_16BIT, + QSPI_DFS_17BIT, + QSPI_DFS_18BIT, + QSPI_DFS_19BIT, + QSPI_DFS_20BIT, + QSPI_DFS_21BIT, + QSPI_DFS_22BIT, + QSPI_DFS_23BIT, + QSPI_DFS_24BIT, + QSPI_DFS_25BIT, + QSPI_DFS_26BIT, + QSPI_DFS_27BIT, + QSPI_DFS_28BIT, + QSPI_DFS_29BIT, + QSPI_DFS_30BIT, + QSPI_DFS_31BIT, + QSPI_DFS_32BIT, +}QSPI_DFS_T; + +/** + * @brief QSPI flag + */ +typedef enum +{ + QSPI_FLAG_BUSY = BIT0, //!< Busy flag + QSPI_FLAG_TFNF = BIT1, //!< TX FIFO not full flag + QSPI_FLAG_TFE = BIT2, //!< TX FIFO empty flag + QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag + QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag + QSPI_FLAG_DCE = BIT6 //!< Data collision error +}QSPI_FLAG_T; + +/** + * @brief QSPI interrupt source + */ +typedef enum +{ + QSPI_INT_TFE = BIT0, //!< TX FIFO empty interrupt + QSPI_INT_TFO = BIT1, //!< TX FIFO overflow interrupt + QSPI_INT_RFU = BIT2, //!< RX FIFO underflow interrupt + QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt + QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt + QSPI_INT_MST = BIT5, //!< Master interrupt +}QSPI_INT_T; + +/** + * @brief QSPI interrupt flag + */ +typedef enum +{ + QSPI_INT_FLAG_TFE = BIT0, //!< TX FIFO empty interrupt flag + QSPI_INT_FLAG_TFO = BIT1, //!< TX FIFO overflow interrupt flag + QSPI_INT_FLAG_RFU = BIT2, //!< RX FIFO underflow interrupt flag + QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag + QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag + QSPI_INT_FLAG_MST = BIT5, //!< Master interrupt flag +}QSPI_INT_FLAG_T; + +/** + * @brief Reception sample edge + */ +typedef enum +{ + QSPI_RSE_RISING, + QSPI_RSE_FALLING +}QSPI_RSE_T; + +/** + * @brief Instruction length + */ +typedef enum +{ + QSPI_INST_LEN_0, + QSPI_INST_LEN_4BIT, + QSPI_INST_LEN_8BIT, + QSPI_INST_LEN_16BIT, +}QSPI_INST_LEN_T; + +/** + * @brief QSPI address length + */ +typedef enum +{ + QSPI_ADDR_LEN_0, + QSPI_ADDR_LEN_4BIT, + QSPI_ADDR_LEN_8BIT, + QSPI_ADDR_LEN_12BIT, + QSPI_ADDR_LEN_16BIT, + QSPI_ADDR_LEN_20BIT, + QSPI_ADDR_LEN_24BIT, + QSPI_ADDR_LEN_28BIT, + QSPI_ADDR_LEN_32BIT, + QSPI_ADDR_LEN_36BIT, + QSPI_ADDR_LEN_40BIT, + QSPI_ADDR_LEN_44BIT, + QSPI_ADDR_LEN_48BIT, + QSPI_ADDR_LEN_52BIT, + QSPI_ADDR_LEN_56BIT, + QSPI_ADDR_LEN_60BIT, +}QSPI_ADDR_LEN_T; + +/** + * @brief Instruction and address transmission mode + */ +typedef enum +{ + QSPI_INST_ADDR_TYPE_STANDARD, + QSPI_INST_TYPE_STANDARD, + QSPI_INST_ADDR_TYPE_FRF, +}QSPI_INST_ADDR_TYPE_T; + +/** + * @brief Slave Select Toggle + */ +typedef enum +{ + QSPI_SST_DISABLE, + QSPI_SST_ENABLE, +}QSPI_SST_T; + +/**@} end of group QSPI_Enumerations*/ + +/** @addtogroup QSPI_Macros Macros + @{ +*/ + +/** CTRL1 register reset value */ +#define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007) +/** CTRL2 register reset value */ +#define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00) +/** SSIEN register reset value */ +#define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00) +/** SLAEN register reset value */ +#define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00) +/** BR register reset value */ +#define QSPI_BR_RESET_VALUE ((uint32_t)0x00) +/** TFTL register reset value */ +#define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00) +/** RFTL register reset value */ +#define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00) +/** TFL register reset value */ +#define QSPI_TFL_RESET_VALUE ((uint32_t)0x00) +/** RFL register reset value */ +#define QSPI_RFL_RESET_VALUE ((uint32_t)0x00) +/** STS register reset value */ +#define QSPI_STS_RESET_VALUE ((uint32_t)0x06) +/** INTEN register reset value */ +#define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F) +/** RSD register reset value */ +#define QSPI_RSD_RESET_VALUE ((uint32_t)0x00) +/** CTRL3 register reset value */ +#define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200) +/** IOSW register reset value */ +#define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00) + +/**@} end of group QSPI_Macros*/ + + +/** @addtogroup QSPI_Structure Data Structure + @{ +*/ +typedef struct +{ + QSPI_SST_T selectSlaveToggle; //!< Slave Select Toggle + QSPI_FRF_T frameFormat; //!< Frame format + uint16_t clockDiv; //!< Clock divider + QSPI_CLKPOL_T clockPolarity; //!< Clock polarity + QSPI_CLKPHA_T clockPhase; //!< Clock phase + QSPI_DFS_T dataFrameSize; //!< Data frame size +}QSPI_Config_T; + +/**@} end of group QSPI_Structure*/ + + +/** @addtogroup QSPI_Fuctions Fuctions + @{ +*/ + +/** Reset */ +void QSPI_Reset(void); + +/** Configuration */ +void QSPI_Config(QSPI_Config_T *qspiConfig); +void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig); + +/** Data frame size, frame number, frame format */ +void QSPI_ConfigFrameNum(uint16_t num); +void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs); +void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat); + +/** Disable or Enable */ +void QSPI_Enable(void); +void QSPI_Disable(void); + +/** TX and RX FIFO */ +uint8_t QSPI_ReadTxFifoDataNum(void); +uint8_t QSPI_ReadRxFifoDataNum(void); +void QSPI_ConfigRxFifoThreshold(uint8_t threshold); +void QSPI_ConfigTxFifoThreshold(uint8_t threshold); +void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold); + +/** RX Sample */ +void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse); +void QSPI_ConfigRxSampleDelay(uint8_t delay); + +/** Clock stretch */ +void QSPI_EnableClockStretch(void); +void QSPI_DisableClockStretch(void); + +/** Instruction, address, Wait cycle */ +void QSPI_ConfigInstLen(QSPI_INST_LEN_T len); +void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len); +void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type); +void QSPI_ConfigWaitCycle(uint8_t cycle); + +/** IO */ +void QSPI_OpenIO(void); +void QSPI_CloseIO(void); + +/** Transmission mode */ +void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode); + +/** Rx and Tx data */ +uint32_t QSPI_RxData(void); +void QSPI_TxData(uint32_t data); + +/** Slave */ +void QSPI_EnableSlave(void); +void QSPI_DisableSlave(void); + +/** Interrupt */ +void QSPI_EnableInterrupt(uint32_t interrupt); +void QSPI_DisableInterrupt(uint32_t interrupt); + +/** Flag */ +uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag); +void QSPI_ClearStatusFlag(void); +uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag); +void QSPI_ClearIntFlag(uint32_t flag); + +/**@} end of group QSPI_Fuctions*/ +/**@} end of group QSPI_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_QSPI_H_ */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h new file mode 100644 index 0000000000..0d4ba102fa --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h @@ -0,0 +1,365 @@ +/*! + * @file apm32f10x_rcm.h + * + * @brief This file contains all the functions prototypes for the RCM firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_RCM_H +#define __APM32F10X_RCM_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RCM_Driver RCM Driver + @{ +*/ + +/** @addtogroup RCM_Enumerations Enumerations + @{ +*/ + +/** + * @brief HSE state + */ +typedef enum +{ + RCM_HSE_CLOSE, //!< CLOSE HSE + RCM_HSE_OPEN, //!< OPEN HSE + RCM_HSE_BYPASS, //!< HSE BYPASS +} RCM_HSE_T; + +/** + * @brief PLL multiplication factor + */ +typedef enum +{ + RCM_PLLMF_2, + RCM_PLLMF_3, + RCM_PLLMF_4, + RCM_PLLMF_5, + RCM_PLLMF_6, + RCM_PLLMF_7, + RCM_PLLMF_8, + RCM_PLLMF_9, + RCM_PLLMF_10, + RCM_PLLMF_11, + RCM_PLLMF_12, + RCM_PLLMF_13, + RCM_PLLMF_14, + RCM_PLLMF_15, + RCM_PLLMF_16, +} RCM_PLLMF_T; + +/** + * @brief System clock select + */ +typedef enum +{ + RCM_SYSCLK_SEL_HSI, + RCM_SYSCLK_SEL_HSE, + RCM_SYSCLK_SEL_PLL +} RCM_SYSCLK_SEL_T; + +/** + * @brief AHB divider Number + */ +typedef enum +{ + RCM_AHB_DIV_1 = 7, + RCM_AHB_DIV_2, + RCM_AHB_DIV_4, + RCM_AHB_DIV_8, + RCM_AHB_DIV_16, + RCM_AHB_DIV_64, + RCM_AHB_DIV_128, + RCM_AHB_DIV_256, + RCM_AHB_DIV_512, +} RCM_AHB_DIV_T; + +/** + * @brief APB divider Number + */ +typedef enum +{ + RCM_APB_DIV_1 = 3, + RCM_APB_DIV_2, + RCM_APB_DIV_4, + RCM_APB_DIV_8, + RCM_APB_DIV_16 +} RCM_APB_DIV_T; + +/** + * @brief USB divider Number + */ +typedef enum +{ + RCM_USB_DIV_1_5, + RCM_USB_DIV_1, + RCM_USB_DIV_2, + RCM_USB_DIV_2_5 //!< (Only for High-density devices for APM32F103xx) +} RCM_USB_DIV_T; + +/** + * @brief FPU divider Number + */ +typedef enum +{ + RCM_FPU_DIV_1, + RCM_FPU_DIV_2, +} RCM_FPU_DIV_T; + +/** + * @brief ADC divider Number + */ +typedef enum +{ + RCM_PCLK2_DIV_2, + RCM_PCLK2_DIV_4, + RCM_PCLK2_DIV_6, + RCM_PCLK2_DIV_8, +} RCM_PCLK2_DIV_T; + +/** + * @brief LSE State + */ +typedef enum +{ + RCM_LSE_CLOSE, + RCM_LSE_OPEN, + RCM_LSE_BYPASS +} RCM_LSE_T; + +/** + * @brief RTC clock select + */ +typedef enum +{ + RCM_RTCCLK_LSE = 1, + RCM_RTCCLK_LSI, + RCM_RTCCLK_HSE_DIV_128 +} RCM_RTCCLK_T; + +/** + * @brief Clock output control + */ +typedef enum +{ + RCM_MCOCLK_NO_CLOCK = 3, + RCM_MCOCLK_SYSCLK, + RCM_MCOCLK_HSI, + RCM_MCOCLK_HSE, + RCM_MCOCLK_PLLCLK_DIV_2, +} RCM_MCOCLK_T; + +/** + * @brief PLL entry clock select + */ +typedef enum +{ + RCM_PLLSEL_HSI_DIV_2 = 0, + RCM_PLLSEL_HSE = 1, + RCM_PLLSEL_HSE_DIV2 = 3, +} RCM_PLLSEL_T; + +/** + * @brief RCM Interrupt Source + */ +typedef enum +{ + RCM_INT_LSIRDY = BIT0, //!< LSI ready interrupt + RCM_INT_LSERDY = BIT1, //!< LSE ready interrupt + RCM_INT_HSIRDY = BIT2, //!< HSI ready interrupt + RCM_INT_HSERDY = BIT3, //!< HSE ready interrupt + RCM_INT_PLLRDY = BIT4, //!< PLL ready interrupt + RCM_INT_CSS = BIT7 //!< Clock security system interrupt +} RCM_INT_T; + +/** + * @brief AHB peripheral + */ +typedef enum +{ + RCM_AHB_PERIPH_DMA1 = BIT0, + RCM_AHB_PERIPH_DMA2 = BIT1, + RCM_AHB_PERIPH_SRAM = BIT2, + RCM_AHB_PERIPH_FPU = BIT3, + RCM_AHB_PERIPH_FMC = BIT4, + RCM_AHB_PERIPH_QSPI = BIT5, + RCM_AHB_PERIPH_CRC = BIT6, + RCM_AHB_PERIPH_EMMC = BIT8, + RCM_AHB_PERIPH_SDIO = BIT10, +} RCM_AHB_PERIPH_T; + +/** + * @brief AHB2 peripheral + */ +typedef enum +{ + RCM_APB2_PERIPH_AFIO = BIT0, + RCM_APB2_PERIPH_GPIOA = BIT2, + RCM_APB2_PERIPH_GPIOB = BIT3, + RCM_APB2_PERIPH_GPIOC = BIT4, + RCM_APB2_PERIPH_GPIOD = BIT5, + RCM_APB2_PERIPH_GPIOE = BIT6, + RCM_APB2_PERIPH_GPIOF = BIT7, + RCM_APB2_PERIPH_GPIOG = BIT8, + RCM_APB2_PERIPH_ADC1 = BIT9, + RCM_APB2_PERIPH_ADC2 = BIT10, + RCM_APB2_PERIPH_TMR1 = BIT11, + RCM_APB2_PERIPH_SPI1 = BIT12, + RCM_APB2_PERIPH_TMR8 = BIT13, + RCM_APB2_PERIPH_USART1 = BIT14, + RCM_APB2_PERIPH_ADC3 = BIT15, +} RCM_APB2_PERIPH_T; + +/** + * @brief AHB1 peripheral + */ +typedef enum +{ + RCM_APB1_PERIPH_TMR2 = BIT0, + RCM_APB1_PERIPH_TMR3 = BIT1, + RCM_APB1_PERIPH_TMR4 = BIT2, + RCM_APB1_PERIPH_TMR5 = BIT3, + RCM_APB1_PERIPH_TMR6 = BIT4, + RCM_APB1_PERIPH_TMR7 = BIT5, + RCM_APB1_PERIPH_WWDT = BIT11, + RCM_APB1_PERIPH_SPI2 = BIT14, + RCM_APB1_PERIPH_SPI3 = BIT15, + RCM_APB1_PERIPH_USART2 = BIT17, + RCM_APB1_PERIPH_USART3 = BIT18, + RCM_APB1_PERIPH_UART4 = BIT19, + RCM_APB1_PERIPH_UART5 = BIT20, + RCM_APB1_PERIPH_I2C1 = BIT21, + RCM_APB1_PERIPH_I2C2 = BIT22, + RCM_APB1_PERIPH_USB = BIT23, + RCM_APB1_PERIPH_CAN1 = BIT25, + RCM_APB1_PERIPH_CAN2 = BIT26, + RCM_APB1_PERIPH_BAKR = BIT27, + RCM_APB1_PERIPH_PMU = BIT28, + RCM_APB1_PERIPH_DAC = BIT29, +} RCM_APB1_PERIPH_T; + +/** + * @brief RCM FLAG define + */ +typedef enum +{ + RCM_FLAG_HSIRDY = 0x001, //!< HSI Ready Flag + RCM_FLAG_HSERDY = 0x011, //!< HSE Ready Flag + RCM_FLAG_PLLRDY = 0x019, //!< PLL Ready Flag + RCM_FLAG_LSERDY = 0x101, //!< LSE Ready Flag + RCM_FLAG_LSIRDY = 0x201, //!< LSI Ready Flag + RCM_FLAG_PINRST = 0x21A, //!< PIN reset flag + RCM_FLAG_PORRST = 0x21B, //!< POR/PDR reset flag + RCM_FLAG_SWRST = 0x21C, //!< Software reset flag + RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag + RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag + RCM_FLAG_LPRRST = 0x21F, //!< Low-power reset flag +} RCM_FLAG_T; + +/**@} end of group RCM_Enumerations*/ + + +/** @addtogroup RCM_Fuctions Fuctions + @{ +*/ + +/** Function description */ + +/** RCM Reset */ +void RCM_Reset(void); + +/** HSE clock */ +void RCM_ConfigHSE(RCM_HSE_T state); +uint8_t RCM_WaitHSEReady(void); + +/** HSI clock */ +void RCM_SetHSITrim(uint8_t HSITrim); +void RCM_EnableHSI(void); +void RCM_DisableHSI(void); + +/** LSE and LSI clock */ +void RCM_ConfigLSE(RCM_LSE_T state); +void RCM_EnableLSI(void); +void RCM_DisableLSI(void); + +/** PLL clock */ +void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf); +void RCM_EnablePLL(void); +void RCM_DisablePLL(void); + +/** Clock Security System */ +void RCM_EnableCSS(void); +void RCM_DisableCSS(void); + +void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock); +void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect); +RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void); + +/** Config clock prescaler of AHB, APB1, APB2, USB and ADC */ +void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv); +void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div); +void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div); +void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv); +void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv); +void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv); + +/** RTC clock */ +void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect); +void RCM_EnableRTCCLK(void); +void RCM_DisableRTCCLK(void); + +/** Reads the clock frequency */ +uint32_t RCM_ReadSYSCLKFreq(void); +uint32_t RCM_ReadHCLKFreq(void); +void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2); +uint32_t RCM_ReadADCCLKFreq(void); + +/** Enable or disable Periph Clock */ +void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph); +void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph); +void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph); +void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph); +void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph); +void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph); + +/** Enable or disable Periph Reset */ +void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph); +void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph); +void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph); +void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph); + +/** Backup domain reset */ +void RCM_EnableBackupReset(void); +void RCM_DisableBackupReset(void); + +/** Interrupts and flags */ +void RCM_EnableInterrupt(uint32_t interrupt); +void RCM_DisableInterrupt(uint32_t interrupt); +uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag); +void RCM_ClearStatusFlag(void); +uint8_t RCM_ReadIntFlag(RCM_INT_T flag); +void RCM_ClearIntFlag(uint32_t flag); + +/**@} end of group RCM_Fuctions*/ +/**@} end of group RCM_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_RCM_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h new file mode 100644 index 0000000000..5e243794f6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h @@ -0,0 +1,85 @@ +/*! + * @file apm32f10x_rtc.h + * + * @brief This file contains all the functions prototypes for the RTC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_RTC_H +#define __APM32F10X_RTC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_Enumerations Enumerations + @{ +*/ + +typedef enum +{ + RTC_FLAG_OC = 0x0020, //!< RTC Operation Complete flag + RTC_FLAG_RSYNC = 0x0008, //!< Registers Synchronized flag + RTC_FLAG_OVR = 0x0004, //!< Overflow flag + RTC_FLAG_ALR = 0x0002, //!< Alarm flag + RTC_FLAG_SEC = 0x0001 //!< Second flag +} RTC_FLAG_T; + +typedef enum +{ + RTC_INT_OVR = 0x0004, //!< Overflow interrupt + RTC_INT_ALR = 0x0002, //!< Alarm interrupt + RTC_INT_SEC = 0x0001 //!< Second interrupt +} RTC_INT_T; + +/**@} end of group RTC_Enumerations*/ + + +/** @addtogroup RTC_Fuctions Fuctions + @{ +*/ + +/** Operation modes */ +void RTC_EnableConfigMode(void); +void RTC_DisableConfigMode(void); + +/** Configuration */ +uint32_t RTC_ReadCounter(void); +void RTC_ConfigCounter(uint32_t value); +void RTC_ConfigPrescaler(uint32_t value); +void RTC_ConfigAlarm(uint32_t value); +uint32_t RTC_ReadDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchor(void); + +/** Interrupts and flags */ +void RTC_EnableInterrupt(uint16_t interrupt); +void RTC_DisableInterrupt(uint16_t interrupt); +uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag); +void RTC_ClearStatusFlag(uint16_t flag); +uint8_t RTC_ReadIntFlag(RTC_INT_T flag); +void RTC_ClearIntFlag(uint16_t flag); + +/**@} end of group RTC_Fuctions*/ +/**@} end of group RTC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_RTC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h new file mode 100644 index 0000000000..fe6e1a6138 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h @@ -0,0 +1,311 @@ +/*! + * @file apm32f10x_sci2c.h + * + * @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_SCI2C_H +#define __APM32F10X_SCI2C_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SCI2C_Driver SCI2C Driver + @{ +*/ + +/** @addtogroup SCI2C_Enumerations Enumerations + @{ +*/ + +/** + * @brief SCI2C speed enumeration + */ +typedef enum +{ + SCI2C_SPEED_STANDARD = 1, + SCI2C_SPEED_FAST, + SCI2C_SPEED_HIGH +}SCI2C_SPEED_T; + +/** + * @brief Address mode + */ +typedef enum +{ + SCI2C_ADDR_MODE_7BIT, + SCI2C_ADDR_MODE_10BIT +}SCI2C_ADDR_MODE_T; + +/** + * @brief SCI2C mode enumeration + */ +typedef enum +{ + SCI2C_MODE_MASTER, + SCI2C_MODE_SLAVE +}SCI2C_MODE_T; + +/** + * @brief Restart enable or disable + */ +typedef enum +{ + SCI2C_RESTART_DISABLE, + SCI2C_RESTART_ENABLE +}SCI2C_RESTART_T; + +/** + * @brief Enable or disable generate stop condition + */ +typedef enum +{ + SCI2C_STOP_DISABLE, + SCI2C_STOP_ENABLE +}SCI2C_STOP_T; +/** + * @brief Data direction + */ +typedef enum +{ + SCI2C_DATA_DIR_WRITE, + SCI2C_DATA_DIR_READ, +}SCI2C_DATA_DIR_T; + +/** + * @brief SCI2C interrupt + */ +typedef enum +{ + SCI2C_INT_RFU = BIT0, //!< Rx FIFO underflow interrupt + SCI2C_INT_RFO = BIT1, //!< Rx FIFO onverflow interrupt + SCI2C_INT_RFF = BIT2, //!< Rx FIFO full interrupt + SCI2C_INT_TFO = BIT3, //!< Tx FIFO onverflow interrupt + SCI2C_INT_TFE = BIT4, //!< Tx FIFO empty interrupt + SCI2C_INT_RR = BIT5, //!< Read request interrupt + SCI2C_INT_TA = BIT6, //!< Tx abort interrupt + SCI2C_INT_RD = BIT7, //!< Read done interrupt + SCI2C_INT_ACT = BIT8, //!< Activity interrupt + SCI2C_INT_STPD = BIT9, //!< Stop detect interrupt + SCI2C_INT_STAD = BIT10, //!< Start detect interrupt + SCI2C_INT_GC = BIT11, //!< Gernal call interrupt + SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt + SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt + SCI2C_INT_ALL = BIT15 //!< All interrupt +}SCI2C_INT_T; + +/** + * @brief Flag enumeration + */ +typedef enum +{ + SCI2C_FLAG_ACT = BIT0, //!< Activity flag + SCI2C_FLAG_TFNF = BIT1, //!< Tx FIFO not full flag + SCI2C_FLAG_TFE = BIT2, //!< Tx FIFO empty flag + SCI2C_FLAG_RFNE = BIT3, //!< Rx FIFO not empty flag + SCI2C_FLAG_RFF = BIT4, //!< Rx FIFO full flag + SCI2C_FLAG_MA = BIT5, //!< Master activity flag + SCI2C_FLAG_SA = BIT6, //!< Slave activity flag + SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag + SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag + SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag +}SCI2C_FLAG_T; + +/** + * @brief Tx abort source + */ +typedef enum +{ + SCI2C_TAS_AD7NA = BIT0, //!< 7 bit address mode NACK + SCI2C_TAS_AD10FBNA = BIT1, //!< 10 bit address mode first byte NACK + SCI2C_TAS_AD10SBNA = BIT2, //!< 10 bit address mode second byte NACK + SCI2C_TAS_TDNA = BIT3, //!< Tx data NACK + SCI2C_TAS_GCNA = BIT4, //!< Gernal call NACK + SCI2C_TAS_GCR = BIT5, //!< Gernal call read + SCI2C_TAS_HSAD = BIT6, //!< High speed ack detected + SCI2C_TAS_SNR = BIT7, //!< Start byte no restart + SCI2C_TAS_RNR10B = BIT8, //!< Read 10bit address mode when restart disable + SCI2C_TAS_MSTDIS = BIT9, //!< Master disable + SCI2C_TAS_ARBLOST = BIT10, //!< Arbitration lost + SCI2C_TAS_LFTF = BIT11, //!< Slave flush tx FIFO + SCI2C_TAS_SAL = BIT12, //!< Slave arbitration lost + SCI2C_TAS_SRI = BIT13, //!< Slave read done + SCI2C_TAS_USRARB = BIT14, //!< User abort + SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter +}SCI2C_TAS_T; + +/** + * @brief DMA Enable + */ +typedef enum +{ + SCI2C_DMA_RX = BIT0, + SCI2C_DMA_TX = BIT1, +}SCI2C_DMA_T; + +/**@} end of group SCI2C_Enumerations*/ + + +/** @addtogroup SCI2C_Macros Macros + @{ +*/ + +/** Macros description */ + +#define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E) +#define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055) +#define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55) +#define SCI2C_HSMC_RESET_VALUE ((uint32_t)0x07) +#define SCI2C_DATA_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_SSCHC_RESET_VALUE ((uint32_t)0x190) +#define SCI2C_SSCLC_RESET_VALUE ((uint32_t)0x1D6) +#define SCI2C_FSCHC_RESET_VALUE ((uint32_t)0x3C) +#define SCI2C_FSCLC_RESET_VALUE ((uint32_t)0x82) +#define SCI2C_HSCHC_RESET_VALUE ((uint32_t)0x06) +#define SCI2C_HSCLC_RESET_VALUE ((uint32_t)0x10) +#define SCI2C_INTEN_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_RFT_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_TFT_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_CTRL2_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_TFL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_RFL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_SDAHOLD_RESET_VALUE ((uint32_t)0x01) +#define SCI2C_SDNO_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_DMACTRL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_DTDL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_DRDL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_SDADLY_RESET_VALUE ((uint32_t)0x64) +#define SCI2C_GCA_RESET_VALUE ((uint32_t)0x01) +#define SCI2C_LSSSL_RESET_VALUE ((uint32_t)0x05) +#define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01) + +#define SCI2C_FIFO_DEPTH (0X08) +/**@} end of group SCI2C_Macros*/ + + +/** @addtogroup SCI2C_Structure Data Structure + @{ +*/ + +/** + * @brief Struct description + */ +typedef struct +{ + uint16_t slaveAddr; //!< Slave address. + SCI2C_MODE_T mode; //!< Specifies mode, master mode or slave mode + SCI2C_SPEED_T speed; //!< Specifies speed. Standard speed, fast speed or high speed. + uint16_t clkLowPeriod; //!< SCL high period + uint16_t clkHighPeriod; //!< SCL low period + uint8_t rxFifoThreshold; //!< Rx FIFO threshold + uint8_t txFifoThreshold; //!< Tx FIFO threshold + SCI2C_RESTART_T restart; //!< Enable or disable restart + SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode. +}SCI2C_Config_T; + +/**@} end of group SCI2C_Structure*/ + + +/** @addtogroup SCI2C_Fuctions Fuctions + @{ +*/ + +/** Reset */ +void SCI2C_Reset(SCI2C_T *i2c); + +/** Configuration */ +void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig); +void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig); + +/** Stop detect */ +void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c); +void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c); +void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c); +void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c); + +/** Restart */ +void SCI2C_EnableRestart(SCI2C_T *i2c); +void SCI2C_DisableRestart(SCI2C_T *i2c); + +/** Speed */ +void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed); + +/** Address */ +void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); +void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); + +/** Master mode and slave mode */ +void SCI2C_EnableMasterMode(SCI2C_T *i2c); +void SCI2C_DisableMasterMode(SCI2C_T *i2c); +void SCI2C_EnableSlaveMode(SCI2C_T *i2c); +void SCI2C_DisableSlaveMode(SCI2C_T *i2c); +void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code); + +/** Data */ +void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir); +void SCI2C_TxData(SCI2C_T *i2c, uint8_t data); +uint8_t SCI2C_RxData(SCI2C_T *i2c); +void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data); + +/** Rx and Tx FIFO */ +uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c); +uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c); +void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); +void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); + +/** I2C Enable, disable, abort, block */ +void SCI2C_Enable(SCI2C_T *i2c); +void SCI2C_Disable(SCI2C_T *i2c); +void SCI2C_Abort(SCI2C_T *i2c); +void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable); + +/** SCL and SDA */ +void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod); +void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold); +void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay); + +/** ACK and NACK */ +void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable); +void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable); + +/** Abort */ +uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c); + +/** DMA */ +void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); +void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); +void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt); +void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt); + +/** Spike suppression limit */ +void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit); + +/** Ingerrupt and flag */ +uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag); +void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); +uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); +uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); +void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt); +void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt); + +/**@} end of group SCI2C_Fuctions*/ +/**@} end of group SCI2C_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_SCI2C_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h new file mode 100644 index 0000000000..cc29cc3c8f --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h @@ -0,0 +1,418 @@ +/*! + * @file apm32f10x_sdio.h + * + * @brief This file contains all the functions prototypes for the SDIO firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_SDIO_H +#define __APM32F10X_SDIO_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SDIO_Driver SDIO Driver + @{ +*/ + +/** @addtogroup SDIO_Enumerations Enumerations + @{ +*/ + +/** + * @brief SDIO clock edge + */ +typedef enum +{ + SDIO_CLOCK_EDGE_RISING = 0x00000000, + SDIO_CLOCK_EDGE_FALLING = 0x00002000 +}SDIO_CLOCK_EDGE_T; + +/** + * @brief SDIO clock bypass + */ +typedef enum +{ + SDIO_CLOCK_BYPASS_DISABLE = 0x00000000, + SDIO_CLOCK_BYPASS_ENABLE = 0x00000400 +}SDIO_CLOCK_BYPASS_T; + +/** + * @brief SDIO clock power save + */ +typedef enum +{ + SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000, + SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200 +}SDIO_CLOCK_POWER_SAVE_T; + +/** + * @brief SDIO bus wide + */ +typedef enum +{ + SDIO_BUSWIDE_1B = 0x00000000, + SDIO_BUSWIDE_4B = 0x00000800, + SDIO_BUSWIDE_8B = 0x00001000 +}SDIO_BUSWIDE_T; + +/** + * @brief SDIO hardware flow control + */ +typedef enum +{ + SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000, + SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000 +}SDIO_HARDWARE_FLOW_CONTROL_T; + +/** + * @brief SDIO power state + */ +typedef enum +{ + SDIO_POWER_STATE_OFF = 0x00000000, + SDIO_POWER_STATE_ON = 0x00000003 +}SDIO_POWER_STATE_T; + +/** + * @brief SDIO interrupt sources + */ +typedef enum +{ + SDIO_INT_COMRESP = 0x00000001, + SDIO_INT_DBDR = 0x00000002, + SDIO_INT_CMDRESTO = 0x00000004, + SDIO_INT_DATATO = 0x00000008, + SDIO_INT_TXUDRER = 0x00000010, + SDIO_INT_RXOVRER = 0x00000020, + SDIO_INT_CMDRES = 0x00000040, + SDIO_INT_CMDSENT = 0x00000080, + SDIO_INT_DATAEND = 0x00000100, + SDIO_INT_SBE = 0x00000200, + SDIO_INT_DBCP = 0x00000400, + SDIO_INT_CMDACT = 0x00000800, + SDIO_INT_TXACT = 0x00001000, + SDIO_INT_RXACT = 0x00002000, + SDIO_INT_TXFHF = 0x00004000, + SDIO_INT_RXFHF = 0x00008000, + SDIO_INT_TXFF = 0x00010000, + SDIO_INT_RXFF = 0x00020000, + SDIO_INT_TXFE = 0x00040000, + SDIO_INT_RXFE = 0x00080000, + SDIO_INT_TXDA = 0x00100000, + SDIO_INT_RXDA = 0x00200000, + SDIO_INT_SDIOINT = 0x00400000, + SDIO_INT_ATAEND = 0x00800000 +}SDIO_INT_T; + +/** + * @brief SDIO response + */ +typedef enum +{ + SDIO_RESPONSE_NO = 0x00000000, + SDIO_RESPONSE_SHORT = 0x00000040, + SDIO_RESPONSE_LONG = 0x000000C0 +}SDIO_RESPONSE_T; + +/** + * @brief SDIO wait interrupt state + */ +typedef enum +{ + SDIO_WAIT_NO = 0x00000000, + SDIO_WAIT_INT = 0x00000100, + SDIO_WAIT_PEND = 0x00000200 +}SDIO_WAIT_T; + +/** + * @brief SDIO CPSM state + */ +typedef enum +{ + SDIO_CPSM_DISABLE = 0x00000000, + SDIO_CPSM_ENABLE = 0x00000400 +}SDIO_CPSM_T; + +/** + * @brief SDIO response registers + */ +typedef enum +{ + SDIO_RES1 = 0x00000000, + SDIO_RES2 = 0x00000004, + SDIO_RES3 = 0x00000008, + SDIO_RES4 = 0x0000000C +}SDIO_RES_T; + +/** + * @brief SDIO data block size + */ +typedef enum +{ + SDIO_DATA_BLOCKSIZE_1B = 0x00000000, + SDIO_DATA_BLOCKSIZE_2B = 0x00000010, + SDIO_DATA_BLOCKSIZE_4B = 0x00000020, + SDIO_DATA_BLOCKSIZE_8B = 0x00000030, + SDIO_DATA_BLOCKSIZE_16B = 0x00000040, + SDIO_DATA_BLOCKSIZE_32B = 0x00000050, + SDIO_DATA_BLOCKSIZE_64B = 0x00000060, + SDIO_DATA_BLOCKSIZE_128B = 0x00000070, + SDIO_DATA_BLOCKSIZE_256B = 0x00000080, + SDIO_DATA_BLOCKSIZE_512B = 0x00000090, + SDIO_DATA_BLOCKSIZE_1024B = 0x000000A0, + SDIO_DATA_BLOCKSIZE_2048B = 0x000000B0, + SDIO_DATA_BLOCKSIZE_496B = 0x000000C0, + SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0, + SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0 +}SDIO_DATA_BLOCKSIZE_T; + +/** + * @brief SDIO transfer direction + */ +typedef enum +{ + SDIO_TRANSFER_DIR_TOCARD = 0x00000000, + SDIO_TRANSFER_DIR_TOSDIO = 0x00000002 +}SDIO_TRANSFER_DIR_T; + +/** + * @brief SDIO transfer type + */ +typedef enum +{ + SDIO_TRANSFER_MODE_BLOCK = 0x00000000, + SDIO_TRANSFER_MODE_STREAM = 0x00000004 +}SDIO_TRANSFER_MODE_T; + +/** + * @brief SDIO DPSM state + */ +typedef enum +{ + SDIO_DPSM_DISABLE = 0x00000000, + SDIO_DPSM_ENABLE = 0x00000001 +}SDIO_DPSM_T; + +/** + * @brief SDIO flag + */ +typedef enum +{ + SDIO_FLAG_COMRESP = 0x00000001, + SDIO_FLAG_DBDR = 0x00000002, + SDIO_FLAG_CMDRESTO = 0x00000004, + SDIO_FLAG_DATATO = 0x00000008, + SDIO_FLAG_TXUDRER = 0x00000010, + SDIO_FLAG_RXOVRER = 0x00000020, + SDIO_FLAG_CMDRES = 0x00000040, + SDIO_FLAG_CMDSENT = 0x00000080, + SDIO_FLAG_DATAEND = 0x00000100, + SDIO_FLAG_SBE = 0x00000200, + SDIO_FLAG_DBCP = 0x00000400, + SDIO_FLAG_CMDACT = 0x00000800, + SDIO_FLAG_TXACT = 0x00001000, + SDIO_FLAG_RXACT = 0x00002000, + SDIO_FLAG_TXFHF = 0x00004000, + SDIO_FLAG_RXFHF = 0x00008000, + SDIO_FLAG_TXFF = 0x00010000, + SDIO_FLAG_RXFF = 0x00020000, + SDIO_FLAG_TXFE = 0x00040000, + SDIO_FLAG_RXFE = 0x00080000, + SDIO_FLAG_TXDA = 0x00100000, + SDIO_FLAG_RXDA = 0x00200000, + SDIO_FLAG_SDIOINT = 0x00400000, + SDIO_FLAG_ATAEND = 0x00800000 +}SDIO_FLAG_T; + +/** + * @brief SDIO read wait mode + */ +typedef enum +{ + SDIO_READ_WAIT_MODE_CLK = 0x00000001, + SDIO_READ_WAIT_MODE_DATA2 = 0x00000000 +}SDIO_READ_WAIT_MODE_T; + +/**@} end of group SDIO_Enumerations*/ + + +/** @addtogroup SDIO_Macros Macros + @{ +*/ + +/** ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCTRL Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSC bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSC_BitNumber 0x0B +#define CMD_SDIOSC_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4)) + +/* Alias word address of CMDCPEN bit */ +#define CMDCPEN_BitNumber 0x0C +#define CMD_CMDCPEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4)) + +/* Alias word address of INTEN bit */ +#define INTEN_BitNumber 0x0D +#define CMD_INTEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTR bit */ +#define RWSTR_BitNumber 0x08 +#define DCTRL_RWSTR_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RDWAIT bit */ +#define RDWAIT_BitNumber 0x0A +#define DCTRL_RDWAIT_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4)) + +/* Alias word address of SDIOF bit */ +#define SDIOF_BitNumber 0x0B +#define DCTRL_SDIOF_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4)) + +/**@} end of group SDIO_Macros*/ + +/** @addtogroup SDIO_Structure Data Structure + @{ +*/ + +/** + * @brief SDIO Config structure definition + */ +typedef struct +{ + SDIO_CLOCK_EDGE_T clockEdge; + SDIO_CLOCK_BYPASS_T clockBypass; + SDIO_CLOCK_POWER_SAVE_T clockPowerSave; + SDIO_BUSWIDE_T busWide; + SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl; + uint8_t clockDiv; +}SDIO_Config_T; + +/** + * @brief SDIO CMD Config structure definition + */ +typedef struct +{ + uint32_t argument; + uint32_t cmdIndex; + SDIO_RESPONSE_T response; + SDIO_WAIT_T wait; + SDIO_CPSM_T CPSM; +}SDIO_CMDConfig_T; + +/** + * @brief SDIO Data Config structure definition + */ +typedef struct +{ + uint32_t dataTimeOut; + uint32_t dataLength; + SDIO_DATA_BLOCKSIZE_T dataBlockSize; + SDIO_TRANSFER_DIR_T transferDir; + SDIO_TRANSFER_MODE_T transferMode; + SDIO_DPSM_T DPSM; +}SDIO_DataConfig_T; + +/**@} end of group SDIO_Structure*/ + + +/** @addtogroup SDIO_Fuctions Fuctions + @{ +*/ + +/** SDIO reset and configuration */ +void SDIO_Reset(void); +void SDIO_Config(SDIO_Config_T* sdioConfig); +void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig); +void SDIO_EnableClock(void); +void SDIO_DisableClock(void); +void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState); +uint32_t SDIO_ReadPowerState(void); + +/** DMA */ +void SDIO_EnableDMA(void); +void SDIO_DisableDMA(void); + +/** Command */ +void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig); +void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdconfig); +uint8_t SDIO_ReadCommandResponse(void); +uint32_t SDIO_ReadResponse(SDIO_RES_T res); + +/** SDIO data configuration */ +void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig); +void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig); +uint32_t SDIO_ReadDataCounter(void); +void SDIO_WriteData(uint32_t data); +uint32_t SDIO_ReadData(void); +uint32_t SDIO_ReadFIFOCount(void); + +/** SDIO mode */ +void SDIO_EnableStartReadWait(void); +void SDIO_DisableStartReadWait(void); +void SDIO_EnableStopReadWait(void); +void SDIO_DisableStopReadWait(void); +void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode); +void SDIO_EnableSDIO(void); +void SDIO_DisableSDIO(void); +void SDIO_EnableTxSDIOSuspend(void); +void SDIO_DisableTxSDIOSuspend(void); +void SDIO_EnableCommandCompletion(void); +void SDIO_DisableCommandCompletion(void); +void SDIO_EnableCEATAInterrupt(void); +void SDIO_DisableCEATAInterrupt(void); +void SDIO_EnableTxCEATA(void); +void SDIO_DisableTxCEATA(void); + +/** Interrupt and flags */ +void SDIO_EnableInterrupt(uint32_t interrupt); +void SDIO_DisableInterrupt(uint32_t interrupt); +uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag); +void SDIO_ClearStatusFlag(uint32_t flag); +uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag); +void SDIO_ClearIntFlag(uint32_t flag); + +/**@} end of group SDIO_Fuctions*/ +/**@} end of group SDIO_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_SDIO_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h new file mode 100644 index 0000000000..40e4afe7c0 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h @@ -0,0 +1,319 @@ +/*! + * @file apm32f10x_spi.h + * + * @brief This file contains all the functions prototypes for the SPI firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_SPI_H +#define __APM32F10X_SPI_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_Enumerations Enumerations + @{ +*/ + +/** + * @brief SPI data direction mode + */ +typedef enum +{ + SPI_DIRECTION_2LINES_FULLDUPLEX = 0x0000, + SPI_DIRECTION_2LINES_RXONLY = 0x0400, + SPI_DIRECTION_1LINE_RX = 0x8000, + SPI_DIRECTION_1LINE_TX = 0xC000 +}SPI_DIRECTION_T; + +/** + * @brief SPI mode + */ +typedef enum +{ + SPI_MODE_MASTER = 0x0104, + SPI_MODE_SLAVE = 0x0000 +}SPI_MODE_T; + +/** + * @brief SPI Data length + */ +typedef enum +{ + SPI_DATA_LENGTH_16B = 0x0800, + SPI_DATA_LENGTH_8B = 0x0000 +}SPI_DATA_LENGTH_T; + +/** + * @brief SPI Clock Polarity + */ +typedef enum +{ + SPI_CLKPOL_LOW = 0x0000, + SPI_CLKPOL_HIGH = 0x0002 +}SPI_CLKPOL_T; + +/** + * @brief SPI Clock Phase + */ +typedef enum +{ + SPI_CLKPHA_1EDGE = 0x0000, + SPI_CLKPHA_2EDGE = 0x0001 +}SPI_CLKPHA_T; + +/** + * @brief SPI Slave Select management + */ +typedef enum +{ + SPI_NSS_SOFT = 0x0200, + SPI_NSS_HARD = 0x0000 +}SPI_NSS_T; + +/** + * @brief SPI BaudRate Prescaler + */ +typedef enum +{ + SPI_BAUDRATE_DIV_2 = 0x0000, + SPI_BAUDRATE_DIV_4 = 0x0008, + SPI_BAUDRATE_DIV_8 = 0x0010, + SPI_BAUDRATE_DIV_16 = 0x0018, + SPI_BAUDRATE_DIV_32 = 0x0020, + SPI_BAUDRATE_DIV_64 = 0x0028, + SPI_BAUDRATE_DIV_128 = 0x0030, + SPI_BAUDRATE_DIV_256 = 0x0038, +}SPI_BAUDRATE_DIV_T; + +/** + * @brief SPI MSB LSB transmission + */ +typedef enum +{ + SPI_FIRSTBIT_MSB = 0x0000, + SPI_FIRSTBIT_LSB = 0x0080 +}SPI_FIRSTBIT_T; + +/** + * @brief I2S Mode + */ +typedef enum +{ + I2S_MODE_SLAVE_TX = 0x0000, + I2S_MODE_SLAVE_RX = 0x0100, + I2S_MODE_MASTER_TX = 0x0200, + I2S_MODE_MASTER_RX = 0x0300 +}I2S_MODE_T; + +/** + * @brief I2S Standard + */ +typedef enum +{ + I2S_STANDARD_PHILLIPS = 0x0000, + I2S_STANDARD_MSB = 0x0010, + I2S_STANDARD_LSB = 0x0020, + I2S_STANDARD_PCMSHORT = 0x0030, + I2S_STANDARD_PCMLONG = 0x00B0 +}I2S_STANDARD_T; + +/** + * @brief I2S data length + */ +typedef enum +{ + I2S_DATA_LENGHT_16B = 0x0000, + I2S_DATA_LENGHT_16BEX = 0x0001, + I2S_DATA_LENGHT_24B = 0x0003, + I2S_DATA_LENGHT_32B = 0x0005, +} I2S_DATA_LENGTH_T; + +/** + * @brief I2S_MCLK_Output + */ +typedef enum +{ + I2S_MCLK_OUTPUT_DISABLE = 0x0000, + I2S_MCLK_OUTPUT_ENABLE = 0x0200, +}I2S_MCLK_OUTPUT_T; + +/** + * @brief I2S Audio divider + */ +typedef enum +{ + I2S_AUDIO_DIV_192K = 192000, + I2S_AUDIO_DIV_96K = 96000, + I2S_AUDIO_DIV_48K = 48000, + I2S_AUDIO_DIV_44K = 44100, + I2S_AUDIO_DIV_32K = 32000, + I2S_AUDIO_DIV_22K = 22050, + I2S_AUDIO_DIV_16K = 16000, + I2S_AUDIO_DIV_11K = 11025, + I2S_AUDIO_DIV_8K = 8000, + I2S_AUDIO_DIV_DEFAULT = 2 +}I2S_AUDIO_DIV_T; + +/** + * @brief I2S Clock Polarity + */ +typedef enum +{ + I2S_CLKPOL_LOW = 0x0000, + I2S_CLKPOL_HIGH = 0x0008 +}I2S_CLKPOL_T; + +/** + * @brief SPI Direction select + */ +typedef enum +{ + SPI_DIRECTION_RX = 0xBFFF, + SPI_DIRECTION_TX = 0x4000 +}SPI_DIRECTION_SELECT_T; + +/** + * @brief SPI interrupts definition + */ +typedef enum +{ + SPI_I2S_INT_TXBE = 0x8002, + SPI_I2S_INT_RXBNE = 0x4001, + SPI_I2S_INT_ERR = 0x2000, + SPI_I2S_INT_OVR = 0x2040, + SPI_INT_CRCE = 0x2010, + SPI_INT_ME = 0x2020, + I2S_INT_UDR = 0x2008 +}SPI_I2S_INT_T; + +/** + * @brief SPI flags definition + */ +typedef enum +{ + SPI_FLAG_RXBNE = 0x0001, + SPI_FLAG_TXBE = 0x0002, + I2S_FLAG_SCHDIR = 0x0004, + I2S_FLAG_UDR = 0x0008, + SPI_FLAG_CRCE = 0x0010, + SPI_FLAG_ME = 0x0020, + SPI_FLAG_OVR = 0x0040, + SPI_FLAG_BSY = 0x0080 +}SPI_FLAG_T; + +/** + * @brief SPI I2S DMA requests + */ +typedef enum +{ + SPI_I2S_DMA_REQ_TX = 0x0002, + SPI_I2S_DMA_REQ_RX = 0x0001 +}SPI_I2S_DMA_REQ_T; + +/**@} end of group SPI_Enumerations*/ + + +/** @addtogroup SPI_Structure Data Structure + @{ +*/ + +/** + * @brief SPI Config structure definition + */ +typedef struct +{ + SPI_MODE_T mode; + SPI_DATA_LENGTH_T length; + SPI_CLKPHA_T phase; + SPI_CLKPOL_T polarity; + SPI_NSS_T nss; + SPI_FIRSTBIT_T firstBit; + SPI_DIRECTION_T direction; + SPI_BAUDRATE_DIV_T baudrateDiv; + uint16_t crcPolynomial; +}SPI_Config_T; + +/** + * @brief I2S Config structure definition + */ +typedef struct +{ + I2S_MODE_T mode; + I2S_STANDARD_T standard; + I2S_DATA_LENGTH_T length; + I2S_MCLK_OUTPUT_T MCLKOutput; + I2S_AUDIO_DIV_T audioDiv; + I2S_CLKPOL_T polarity; +}I2S_Config_T; + +/**@} end of group SPI_Structure*/ + +/** @addtogroup SPI_Fuctions Fuctions + @{ +*/ + +/** Reset and Configuration */ +void SPI_I2S_Reset(SPI_T* spi); +void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig); +void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig); +void SPI_ConfigStructInit(SPI_Config_T* spiConfig); +void I2S_ConfigStructInit(I2S_Config_T* i2sConfig); +void SPI_Enable(SPI_T* spi); +void SPI_Disable(SPI_T* spi); +void I2S_Enable(SPI_T* spi); +void I2S_Disable(SPI_T* spi); + +void SPI_I2S_TxData(SPI_T* spi, uint16_t data); +uint16_t SPI_I2S_RxData(SPI_T* spi); +void SPI_SetSoftwareNSS(SPI_T* spi); +void SPI_ResetSoftwareNSS(SPI_T* spi); +void SPI_EnableSSOutput(SPI_T* spi); +void SPI_DisableSSOutput(SPI_T* spi); +void SPI_ConfigDataSize(SPI_T* spi, uint16_t dataSize); + +/** DMA */ +void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); +void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); + +/** CRC */ +void SPI_TxCRC(SPI_T* spi); +void SPI_EnableCRC(SPI_T* spi); +void SPI_DisableCRC(SPI_T* spi); +uint16_t SPI_ReadTxCRC(SPI_T* spi); +uint16_t SPI_ReadRxCRC(SPI_T* spi); +uint16_t SPI_ReadCRCPolynomial(SPI_T* spi); +void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction); + +/** Interrupts and flag */ +void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); +void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); +uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag); +void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag); +uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); +void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); + +/**@} end of group SPI_Fuctions*/ +/**@} end of group SPI_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_SPI_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h new file mode 100644 index 0000000000..50313d7e08 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h @@ -0,0 +1,659 @@ +/*! + * @file apm32f10x_tmr.h + * + * @brief This file contains all the functions prototypes for the TMR firmware library. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#ifndef __APM32F10X_TMR_H +#define __APM32F10X_TMR_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup TMR_Driver TMR Driver + @{ +*/ + +/** @addtogroup TMR_Enumerations Enumerations + @{ +*/ + +/** + * @brief TMR Counter Mode + */ +typedef enum +{ + TMR_COUNTER_MODE_UP = 0x0000, + TMR_COUNTER_MODE_DOWN = 0x0010, + TMR_COUNTER_MODE_CENTERALIGNED1 = 0x0020, + TMR_COUNTER_MODE_CENTERALIGNED2 = 0x0040, + TMR_COUNTER_MODE_CENTERALIGNED3 = 0x0060 +} TMR_COUNTER_MODE_T; + +/** + * @brief TMR Clock division + */ +typedef enum +{ + TMR_CLOCK_DIV_1, + TMR_CLOCK_DIV_2, + TMR_CLOCK_DIV_4 +} TMR_CLOCK_DIV_T; + +/** + * @brief TMR Output Compare and PWM modes + */ +typedef enum +{ + TMR_OC_MODE_TMRING = 0x00, + TMR_OC_MODE_ACTIVE = 0x01, + TMR_OC_MODE_INACTIVE = 0x02, + TMR_OC_MODE_TOGGEL = 0x03, + TMR_OC_MODE_LOWLEVEL = 0x04, + TMR_OC_MODE_HIGHLEVEL = 0x05, + TMR_OC_MODE_PWM1 = 0x06, + TMR_OC_MODE_PWM2 = 0x07, +} TMR_OC_MODE_T; + +/** + * @brief TMR Output Compare state + */ +typedef enum +{ + TMR_OC_STATE_DISABLE, + TMR_OC_STATE_ENABLE +} TMR_OC_STATE_T; + +/** + * @brief TMR Output Compare N state + */ +typedef enum +{ + TMR_OC_NSTATE_DISABLE, + TMR_OC_NSTATE_ENABLE +} TMR_OC_NSTATE_T; + +/** + * @brief TMR Output Compare Polarity + */ +typedef enum +{ + TMR_OC_POLARITY_HIGH, + TMR_OC_POLARITY_LOW +} TMR_OC_POLARITY_T; + +/** + * @brief TMR Output Compare N Polarity + */ +typedef enum +{ + TMR_OC_NPOLARITY_HIGH, + TMR_OC_NPOLARITY_LOW +} TMR_OC_NPOLARITY_T; + +/** + * @brief TMR Output Compare Idle State + */ +typedef enum +{ + TMR_OC_IDLE_STATE_RESET, + TMR_OC_IDLE_STATE_SET +} TMR_OC_IDLE_STATE_T; + +/** + * @brief TMR Output Compare N Idle State + */ +typedef enum +{ + TMR_OC_NIDLE_STATE_RESET, + TMR_OC_NIDLE_STATE_SET +} TMR_OC_NIDLE_STATE_T; + +/** + * @brief TMR Input Capture Init structure definition + */ +typedef enum +{ + TMR_CHANNEL_1 = 0x0000, + TMR_CHANNEL_2 = 0x0004, + TMR_CHANNEL_3 = 0x0008, + TMR_CHANNEL_4 = 0x000C +} TMR_CHANNEL_T; + +/** + * @brief TMR Input Capture Polarity + */ +typedef enum +{ + TMR_IC_POLARITY_RISING = 0x00, + TMR_IC_POLARITY_FALLING = 0x02, + TMR_IC_POLARITY_BOTHEDGE = 0x0A +} TMR_IC_POLARITY_T; + +/** + * @brief TMR Input Capture Selection + */ +typedef enum +{ + TMR_IC_SELECTION_DIRECT_TI = 0x01, + TMR_IC_SELECTION_INDIRECT_TI = 0x02, + TMR_IC_SELECTION_TRC = 0x03 +} TMR_IC_SELECTION_T; + +/** + * @brief TMR Input Capture Prescaler + */ +typedef enum +{ + TMR_IC_PSC_1, + TMR_IC_PSC_2, + TMR_IC_PSC_4, + TMR_IC_PSC_8 +} TMR_IC_PSC_T; + +/** + * @brief TMR Specifies the Off-State selection used in Run mode + */ +typedef enum +{ + TMR_RMOS_STATE_DISABLE, + TMR_RMOS_STATE_ENABLE +} TMR_RMOS_STATE_T; + +/** + * @brief TMR Closed state configuration in idle mode + */ +typedef enum +{ + TMR_IMOS_STATE_DISABLE, + TMR_IMOS_STATE_ENABLE +} TMR_IMOS_STATE_T; + +/** + * @brief TMR Protect mode configuration values + */ +typedef enum +{ + TMR_LOCK_LEVEL_OFF, + TMR_LOCK_LEVEL_1, + TMR_LOCK_LEVEL_2, + TMR_LOCK_LEVEL_3 +} TMR_LOCK_LEVEL_T; + +/** + * @brief TMR BRK state + */ +typedef enum +{ + TMR_BRK_STATE_DISABLE, + TMR_BRK_STATE_ENABLE +} TMR_BRK_STATE_T; + +/** + * @brief TMR Specifies the Break Input pin polarity. + */ +typedef enum +{ + TMR_BRK_POLARITY_LOW, + TMR_BRK_POLARITY_HIGH +} TMR_BRK_POLARITY_T; + +/** + * @brief TMR Specifies the Break Input pin polarity. + */ +typedef enum +{ + TMR_AUTOMATIC_OUTPUT_DISABLE, + TMR_AUTOMATIC_OUTPUT_ENABLE +} TMR_AUTOMATIC_OUTPUT_T; + +/** + * @brief TMR_interrupt_sources + */ +typedef enum +{ + TMR_INT_UPDATE = 0x0001, + TMR_INT_CC1 = 0x0002, + TMR_INT_CC2 = 0x0004, + TMR_INT_CC3 = 0x0008, + TMR_INT_CC4 = 0x0010, + TMR_INT_COM = 0x0020, + TMR_INT_TRG = 0x0040, + TMR_INT_BRK = 0x0080 +} TMR_INT_T; + +/** + * @brief TMR event sources + */ +typedef enum +{ + TMR_EVENT_UPDATE = 0x001, + TMR_EVENT_CC1 = 0x002, + TMR_EVENT_CC2 = 0x004, + TMR_EVENT_CC3 = 0x008, + TMR_EVENT_CC4 = 0x010, + TMR_EVENT_COM = 0x020, + TMR_EVENT_TRG = 0x040, + TMR_EVENT_BRK = 0x080 +} TMR_EVENT_T; + +/** + * @brief TMR DMA Base Address + */ +typedef enum +{ + TMR_DMA_BASE_CTRL1 = 0x0000, + TMR_DMA_BASE_CTRL2 = 0x0001, + TMR_DMA_BASE_SMCTRL = 0x0002, + TMR_DMA_BASE_DIEN = 0x0003, + TMR_DMA_BASE_STS = 0x0004, + TMR_DMA_BASE_CEG = 0x0005, + TMR_DMA_BASE_CCM1 = 0x0006, + TMR_DMA_BASE_CCM2 = 0x0007, + TMR_DMA_BASE_CCEN = 0x0008, + TMR_DMA_BASE_CNT = 0x0009, + TMR_DMA_BASE_PSC = 0x000A, + TMR_DMA_BASE_AUTORLD = 0x000B, + TMR_DMA_BASE_REPCNT = 0x000C, + TMR_DMA_BASE_CC1 = 0x000D, + TMR_DMA_BASE_CC2 = 0x000E, + TMR_DMA_BASE_CC3 = 0x000F, + TMR_DMA_BASE_CC4 = 0x0010, + TMR_DMA_BASE_BDT = 0x0011, + TMR_DMA_BASE_DCTRL = 0x0012 +} TMR_DMA_BASE_T; + +/** + * @brief TMR DMA Burst Length + */ +typedef enum +{ + TMR_DMA_BURSTLENGTH_1TRANSFER = 0x0000, + TMR_DMA_BURSTLENGTH_2TRANSFERS = 0x0100, + TMR_DMA_BURSTLENGTH_3TRANSFERS = 0x0200, + TMR_DMA_BURSTLENGTH_4TRANSFERS = 0x0300, + TMR_DMA_BURSTLENGTH_5TRANSFERS = 0x0400, + TMR_DMA_BURSTLENGTH_6TRANSFERS = 0x0500, + TMR_DMA_BURSTLENGTH_7TRANSFERS = 0x0600, + TMR_DMA_BURSTLENGTH_8TRANSFERS = 0x0700, + TMR_DMA_BURSTLENGTH_9TRANSFERS = 0x0800, + TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900, + TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00, + TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00, + TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00, + TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00, + TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00, + TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00, + TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000, + TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100, +} TMR_DMA_BURSTLENGTH_T; + +/** + * @brief TMR DMA Soueces + */ +typedef enum +{ + TMR_DMA_SOURCE_UPDATE = 0x0100, + TMR_DMA_SOURCE_CC1 = 0x0200, + TMR_DMA_SOURCE_CC2 = 0x0400, + TMR_DMA_SOURCE_CC3 = 0x0800, + TMR_DMA_SOURCE_CC4 = 0x1000, + TMR_DMA_SOURCE_COM = 0x2000, + TMR_DMA_SOURCE_TRG = 0x4000 +} TMR_DMA_SOURCE_T; + +/** + * @brief TMR Internal Trigger Selection + */ +typedef enum +{ + TMR_TRIGGER_SOURCE_ITR0 = 0x00, + TMR_TRIGGER_SOURCE_ITR1 = 0x01, + TMR_TRIGGER_SOURCE_ITR2 = 0x02, + TMR_TRIGGER_SOURCE_ITR3 = 0x03, + TMR_TRIGGER_SOURCE_TI1F_ED = 0x04, + TMR_TRIGGER_SOURCE_TI1FP1 = 0x05, + TMR_TRIGGER_SOURCE_TI2FP2 = 0x06, + TMR_TRIGGER_SOURCE_ETRF = 0x07 +} TMR_TRIGGER_SOURCE_T; + +/** + * @brief TMR The external Trigger Prescaler. + */ +typedef enum +{ + TMR_EXTTRG_PSC_OFF = 0x00, + TMR_EXTTRG_PSC_DIV2 = 0x01, + TMR_EXTTRG_PSC_DIV4 = 0x02, + TMR_EXTTRG_PSC_DIV8 = 0x03 +} TMR_EXTTRG_PSC_T; + +/** + * @brief TMR External Trigger Polarity + */ +typedef enum +{ + TMR_EXTTGR_POL_NONINVERTED, + TMR_EXTTRG_POL_INVERTED +} TMR_EXTTRG_POL_T; + +/** + * @brief TMR Prescaler Reload Mode + */ +typedef enum +{ + TMR_PRESCALER_RELOAD_UPDATA, + TMR_PRESCALER_RELOAD_IMMEDIATE +} TMR_PRESCALER_RELOAD_T; + +/** + * @brief TMR Encoder Mode + */ +typedef enum +{ + TMR_ENCODER_MODE_TI1 = 0x01, + TMR_ENCODER_MODE_TI2 = 0x02, + TMR_ENCODER_MODE_TI12 = 0x03 +} TMR_ENCODER_MODE_T; + +/** + * @brief TMR Forced Action + */ +typedef enum +{ + TMR_FORCED_ACTION_INACTIVE = 0x04, + TMR_FORCED_ACTION_ACTIVE = 0x05 +} TMR_FORCED_ACTION_T; + +/** + * @brief TMR Output Compare Preload State + */ +typedef enum +{ + TMR_OC_PRELOAD_DISABLE, + TMR_OC_PRELOAD_ENABLE +} TMR_OC_PRELOAD_T; + +/** + * @brief TMR Output Compare Preload State + */ +typedef enum +{ + TMR_OC_FAST_DISABLE, + TMR_OC_FAST_ENABLE +} TMR_OC_FAST_T; + +/** + * @brief TMR Output Compare Preload State + */ +typedef enum +{ + TMR_OC_CLEAR_DISABLE, + TMR_OC_CLEAR_ENABLE +} TMR_OC_CLEAR_T; + +/** + * @brief TMR UpdateSource + */ +typedef enum +{ + TMR_UPDATE_SOURCE_GLOBAL, + TMR_UPDATE_SOURCE_REGULAR, +} TMR_UPDATE_SOURCE_T; + +/** + * @brief TMR Single Pulse Mode + */ +typedef enum +{ + TMR_SPM_REPETITIVE, + TMR_SPM_SINGLE, +} TMR_SPM_T; + +/** + * @brief TMR Trigger Output Source + */ +typedef enum +{ + TMR_TRGO_SOURCE_RESET, + TMR_TRGO_SOURCE_ENABLE, + TMR_TRGO_SOURCE_UPDATE, + TMR_TRGO_SOURCE_OC1, + TMR_TRGO_SOURCE_OC1REF, + TMR_TRGO_SOURCE_OC2REF, + TMR_TRGO_SOURCE_OC3REF, + TMR_TRGO_SOURCE_OC4REF +} TMR_TRGO_SOURCE_T; + +/** + * @brief TMR Slave Mode + */ +typedef enum +{ + TMR_SLAVE_MODE_RESET = 0x04, + TMR_SLAVE_MODE_GATED = 0x05, + TMR_SLAVE_MODE_TRIGGER = 0x06, + TMR_SLAVE_MODE_EXTERNALL = 0x07 +} TMR_SLAVE_MODE_T; + +/** + * @brief TMR Flag + */ +typedef enum +{ + TMR_FLAG_UPDATE = 0x0001, + TMR_FLAG_CC1 = 0x0002, + TMR_FLAG_CC2 = 0x0004, + TMR_FLAG_CC3 = 0x0008, + TMR_FLAG_CC4 = 0x0010, + TMR_FLAG_COM = 0x0020, + TMR_FLAG_TRG = 0x0040, + TMR_FLAG_BRK = 0x0080, + TMR_FLAG_CC1RC = 0x0200, + TMR_FLAG_CC2RC = 0x0400, + TMR_FLAG_CC3RC = 0x0800, + TMR_FLAG_CC4RC = 0x1000 +} TMR_FLAG_T; + +/**@} end of group TMR_Enumerations*/ + +/** @addtogroup TMR_Structure Data Structure + @{ +*/ + +/** + * @brief TMR Config struct definition + */ +typedef struct +{ + TMR_COUNTER_MODE_T countMode; + TMR_CLOCK_DIV_T clockDivision; + uint16_t period; //!< This must between 0x0000 and 0xFFFF + uint16_t division; //!< This must between 0x0000 and 0xFFFF + uint8_t repetitionCounter; //!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. +} TMR_BaseConfig_T; ; + +/** + * @brief TMR Config struct definition + */ +typedef struct +{ + TMR_OC_MODE_T mode; + TMR_OC_STATE_T outputState; + TMR_OC_NSTATE_T outputNState; + TMR_OC_POLARITY_T polarity; + TMR_OC_NPOLARITY_T nPolarity; + TMR_OC_IDLE_STATE_T idleState; + TMR_OC_NIDLE_STATE_T nIdleState; + uint16_t pulse; //!< This must between 0x0000 and 0xFFFF +} TMR_OCConfig_T; + +/** + * @brief TMR BDT structure definition + */ +typedef struct +{ + TMR_RMOS_STATE_T RMOS; + TMR_IMOS_STATE_T IMOS; + TMR_LOCK_LEVEL_T lockLevel; + uint16_t deadTime; + TMR_BRK_STATE_T BRKState; + TMR_BRK_POLARITY_T BRKPolarity; + TMR_AUTOMATIC_OUTPUT_T automaticOutput; +} TMR_BDTConfig_T; + +/** + * @brief TMR Input Capture Config struct definition + */ +typedef struct +{ + TMR_CHANNEL_T channel; + TMR_IC_POLARITY_T polarity; + TMR_IC_SELECTION_T selection; + TMR_IC_PSC_T prescaler; + uint16_t filter; //!< This must between 0x00 and 0x0F +} TMR_ICConfig_T; + +/**@} end of group TMR_Structure*/ + +/** @addtogroup TMR_Fuctions Fuctions + @{ +*/ + +/** Reset and Configuration */ +void TMR_Reset(TMR_T* tmr); +void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig); +void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OC1Config); +void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OC2Config); +void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OC3Config); +void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OC4Config); +void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig); +void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig); +void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig); +void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig); +void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig); +void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig); +void TMR_Enable(TMR_T* tmr); +void TMR_Disable(TMR_T* tmr); + +/* PWM Configuration */ +void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig); +void TMR_EnablePWMOutputs(TMR_T* tmr); +void TMR_DisablePWMOutputs(TMR_T* tmr); + +/** DMA */ +void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength); +void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource); +void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource); + +/** Configuration */ +void TMR_ConfigInternalClock(TMR_T* tmr); +void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource); +void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); +void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter); +void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter); +void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter); +void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode); +void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode); +void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce); +void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, + TMR_IC_POLARITY_T IC2Polarity); +void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_EnableAUTOReload(TMR_T* tmr); +void TMR_DisableAUTOReload(TMR_T* tmr); +void TMR_EnableSelectCOM(TMR_T* tmr); +void TMR_DisableSelectCOM(TMR_T* tmr); +void TMR_EnableCCDMA(TMR_T* tmr); +void TMR_DisableCCDMA(TMR_T* tmr); +void TMR_EnableCCPreload(TMR_T* tmr); +void TMR_DisableCCPreload(TMR_T* tmr); +void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode); +void TMR_EnableNoUpdate(TMR_T* tmr); +void TMR_DisableNoUpdate(TMR_T* tmr); +void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource); +void TMR_EnableHallSensor(TMR_T* tmr); +void TMR_DisableHallSensor(TMR_T* tmr); +void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode); +void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource); +void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode); +void TMR_EnableMasterSlaveMode(TMR_T* tmr); +void TMR_DisableMasterSlaveMode(TMR_T* tmr); +void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter); +void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload); +void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1); +void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2); +void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3); +void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4); +void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision); +uint16_t TMR_ReadCaputer1(TMR_T* tmr); +uint16_t TMR_ReadCaputer2(TMR_T* tmr); +uint16_t TMR_ReadCaputer3(TMR_T* tmr); +uint16_t TMR_ReadCaputer4(TMR_T* tmr); +uint16_t TMR_ReadCounter(TMR_T* tmr); +uint16_t TMR_ReadPrescaler(TMR_T* tmr); + +/** Interrupts and Event */ +void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt); +void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt); +void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources); + +/** flags */ +uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag); +void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag); +uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag); +void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag); + +/**@} end of group TMR_Fuctions*/ +/**@} end of group TMR_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_TMR_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h new file mode 100644 index 0000000000..fb7880c1ee --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h @@ -0,0 +1,296 @@ +/*! + * @file apm32f10x_usart.h + * + * @brief This file contains all the functions prototypes for the USART firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_USART_H +#define __APM32F10X_USART_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup USART_Driver USART Driver + @{ +*/ + +/** @addtogroup USART_Enumerations Enumerations + @{ +*/ + +/** + * @brief USART Word Length define + */ +typedef enum +{ + USART_WORD_LEN_8B = 0, + USART_WORD_LEN_9B = BIT12 +} USART_WORD_LEN_T; + +/** + * @brief USART Stop bits define + */ +typedef enum +{ + USART_STOP_BIT_1 = 0, + USART_STOP_BIT_0_5 = BIT12, + USART_STOP_BIT_2 = BIT13, + USART_STOP_BIT_1_5 = BIT12 | BIT13 +} USART_STOP_BIT_T; + +/** + * @brief USART Parity define + */ +typedef enum +{ + USART_PARITY_NONE = 0, + USART_PARITY_EVEN = BIT10, + USART_PARITY_ODD = BIT10 | BIT9 +} USART_PARITY_T; + +/** + * @brief USART mode define + */ +typedef enum +{ + USART_MODE_RX = BIT2, + USART_MODE_TX = BIT3, + USART_MODE_TX_RX = BIT2 | BIT3 +} USART_MODE_T; + +/** + * @brief USART hardware flow control define + */ +typedef enum +{ + USART_HARDWARE_FLOW_NONE = 0, + USART_HARDWARE_FLOW_RTS = BIT8, + USART_HARDWARE_FLOW_CTS = BIT9, + USART_HARDWARE_FLOW_RTS_CTS = BIT8 | BIT9 +} USART_HARDWARE_FLOW_T; + +/** + * @brief USART Clock enable + */ +typedef enum +{ + USART_CLKEN_DISABLE, + USART_CLKEN_ENABLE +} USART_CLKEN_T; + +/** + * @brief USART Clock polarity define + */ +typedef enum +{ + USART_CLKPOL_LOW, + USART_CLKPOL_HIGH +} USART_CLKPOL_T; + +/** + * @brief USART Clock phase define + */ +typedef enum +{ + USART_CLKPHA_1EDGE, + USART_CLKPHA_2EDGE +} USART_CLKPHA_T; + +/** + * @brief USART Last bit clock pulse enable + */ +typedef enum +{ + USART_LBCP_DISABLE, + USART_LBCP_ENABLE, +} USART_LBCP_T; + +/** + * @brief USART Interrupt Source + */ +typedef enum +{ + USART_INT_PE = 0x0010100, + USART_INT_TXBE = 0x7010080, + USART_INT_TXC = 0x6010040, + USART_INT_RXBNE = 0x5010020, + USART_INT_IDLE = 0x4010010, + USART_INT_LBD = 0x8020040, + USART_INT_CTS = 0x9040400, + USART_INT_ERR = 0x0040001, + USART_INT_OVRE = 0x3040001, + USART_INT_NE = 0x2040001, + USART_INT_FE = 0x1040001 +} USART_INT_T; + +/** + * @brief USART DMA enable + */ +typedef enum +{ + USART_DMA_TX = BIT7, + USART_DMA_RX = BIT6, + USART_DMA_TX_RX = BIT6 | BIT7 +} USART_DMA_T; + +/** + * @brief USART Wakeup method + */ +typedef enum +{ + USART_WAKEUP_IDLE_LINE, + USART_WAKEUP_ADDRESS_MARK +} USART_WAKEUP_T; + +/** + * @brief USART LIN break detection length + */ +typedef enum +{ + USART_LBDL_10B, + USART_LBDL_11B +} USART_LBDL_T; + +/** + * @brief USART IrDA low-power + */ +typedef enum +{ + USART_IRDALP_NORMAL, + USART_IRDALP_LOWPOWER +} USART_IRDALP_T; + +/** + * @brief USART flag define + */ +typedef enum +{ + USART_FLAG_CTS = 0x0200, + USART_FLAG_LBD = 0x0100, + USART_FLAG_TXBE = 0x0080, + USART_FLAG_TXC = 0x0040, + USART_FLAG_RXBNE = 0x0020, + USART_FLAG_IDLE = 0x0010, + USART_FLAG_OVRE = 0x0008, + USART_FLAG_NE = 0x0004, + USART_FLAG_FE = 0x0002, + USART_FLAG_PE = 0x0001 +} USART_FLAG_T; + +/**@} end of group USART_Enumerations*/ + +/** @addtogroup USART_Structure Data Structure + @{ +*/ + +/** + * @brief USART Config struct definition + */ +typedef struct +{ + uint32_t baudRate; //!< Specifies the baud rate + USART_WORD_LEN_T wordLength; //!< Specifies the word length + USART_STOP_BIT_T stopBits; //!< Specifies the stop bits + USART_PARITY_T parity; //!< Specifies the parity + USART_MODE_T mode; //!< Specifies the mode + USART_HARDWARE_FLOW_T hardwareFlow; //!< Specifies the hardware flow control +} USART_Config_T; + +/** + * @brief USART synchronous communication clock config struct definition + */ +typedef struct +{ + USART_CLKEN_T clock; //!< Enable or Disable Clock + USART_CLKPOL_T polarity; //!< Specifies the clock polarity + USART_CLKPHA_T phase; //!< Specifies the clock phase + USART_LBCP_T lastBit; //!< Enable or Disable last bit clock +} USART_ClockConfig_T; + +/**@} end of group USART_Structure*/ + +/** @addtogroup USART_Fuctions Fuctions + @{ +*/ + +/** USART Reset and Configuration */ +void USART_Reset(USART_T* usart); +void USART_Config(USART_T* uart, USART_Config_T* usartConfig); +void USART_ConfigStructInit(USART_Config_T* usartConfig); +void USART_Address(USART_T* usart, uint8_t address); +void USART_Enable(USART_T* usart); +void USART_Disable(USART_T* usart); + +/** Clock communication */ +void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig); +void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig); + +/** DMA mode */ +void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq); +void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq); + +/** Mute mode */ +void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup); +void USART_EnableMuteMode(USART_T* usart); +void USART_DisableMuteMode(USART_T* usart); + +/** LIN mode */ +void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length); +void USART_EnableLIN(USART_T* usart); +void USART_DisableLIN(USART_T* usart); + +/** Transmit and receive */ +void USART_EnableTx(USART_T* usart); +void USART_DisableTx(USART_T* usart); +void USART_EnableRx(USART_T* usart); +void USART_DisableRx(USART_T* usart); +void USART_TxData(USART_T* usart, uint16_t data); +uint16_t USART_RxData(USART_T* usart); +void USART_TxBreak(USART_T* usart); + +/** Smartcard mode */ +void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime); +void USART_ConfigPrescaler(USART_T* usart, uint8_t div); +void USART_EnableSmartCard(USART_T* usart); +void USART_DisableSmartCard(USART_T* usart); +void USART_EnableSmartCardNACK(USART_T* usart); +void USART_DisableSmartCardNACK(USART_T* usart); + +/** Half-duplex mode */ +void USART_EnableHalfDuplex(USART_T* usart); +void USART_DisableHalfDuplex(USART_T* usart); + +/** IrDA mode */ +void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode); +void USART_EnableIrDA(USART_T* usart); +void USART_DisableIrDA(USART_T* usart); + +/** Interrupt and flag */ +void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt); +void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt); +uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag); +void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag); +uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag); +void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag); + +/**@} end of group USART_Fuctions*/ +/**@} end of group USART_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_USART_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h new file mode 100644 index 0000000000..570c0e30a1 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h @@ -0,0 +1,582 @@ +/*! + * @file apm32f10x_usb.h + * + * @brief This file contains all the prototypes,enumeration and macros for USBD peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#ifndef __APM32F10X_USBD_H_ +#define __APM32F10X_USBD_H_ + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_Enumerations Enumerations + @{ +*/ + +/** + * @brief USBD Endpoint register bit definition + */ +typedef enum +{ + USBD_EP_BIT_ADDR = (uint32_t)(BIT0 | BIT1 | BIT2 | BIT3), + USBD_EP_BIT_TXSTS = (uint32_t)(BIT4 | BIT5), + USBD_EP_BIT_TXDTOG = (uint32_t)(BIT6), + USBD_EP_BIT_CTFT = (uint32_t)(BIT7), + USBD_EP_BIT_KIND = (uint32_t)(BIT8), + USBD_EP_BIT_TYPE = (uint32_t)(BIT9 | BIT10), + USBD_EP_BIT_SETUP = (uint32_t)(BIT11), + USBD_EP_BIT_RXSTS = (uint32_t)(BIT12 | BIT13), + USBD_EP_BIT_RXDTOG = (uint32_t)(BIT14), + USBD_EP_BIT_CTFR = (uint32_t)(BIT15) +}USBD_EP_BIT_T; + +/** + * @brief Endpoint id + */ +typedef enum +{ + USBD_EP_0, + USBD_EP_1, + USBD_EP_2, + USBD_EP_3, + USBD_EP_4, + USBD_EP_5, + USBD_EP_6, + USBD_EP_7, +}USBD_EP_T; + +/** + * @brief Endpoint status + */ +typedef enum +{ + USBD_EP_STATUS_DISABLE = ((uint32_t)0), + USBD_EP_STATUS_STALL = ((uint32_t)1), + USBD_EP_STATUS_NAK = ((uint32_t)2), + USBD_EP_STATUS_VALID = ((uint32_t)3), +}USBD_EP_STATUS_T; + +/** + * @brief USBD Endpoint type + */ +typedef enum +{ + USBD_EP_TYPE_BULK, + USBD_EP_TYPE_CONTROL, + USBD_EP_TYPE_ISO, + USBD_EP_TYPE_INTERRUPT +}USBD_EP_TYPE_T; + +/**@} end of group USBD_Enumerations*/ + + +/** @addtogroup USBD_Macros Macros + @{ +*/ + +/** USBD packet memory area base address */ +#define USBD_PMA_ADDR (0x40006000L) + +/** Endpoint register mask value default */ +#define USBD_EP_MASK_DEFAULT (USBD_EP_BIT_CTFR | USBD_EP_BIT_SETUP | USBD_EP_BIT_TYPE | USBD_EP_BIT_KIND | USBD_EP_BIT_CTFT |USBD_EP_BIT_ADDR) + +/** + * @brief USBD interrupt source + */ +#define USBD_INT_ESOF 0X100 +#define USBD_INT_SOF 0X200 +#define USBD_INT_RST 0X400 +#define USBD_INT_SUS 0x800 +#define USBD_INT_WKUP 0X1000 +#define USBD_INT_ERR 0X2000 +#define USBD_INT_PMAOU 0X4000 +#define USBD_INT_CTR 0X8000 +#define USBD_INT_ALL 0XFF00 + +/**@} end of group USBD_Macros*/ + + +/** @addtogroup USBD_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Set CTRL register + * + * @param val: Register value + * + * @retval None + * + */ +#define USBD_SetRegCTRL(val) (USBD->CTRL = val) + +/*! + * @brief Set INTSTS register + * + * @param val: Register value + * + * @retval None + */ +#define USBD_SetRegINTSTS(val) (USBD->INTSTS = val) + +/*! + * @brief Set force reset + * + * @param None + * + * @retval None + */ +#define USBD_SetForceReset() (USBD->CTRL_B.FORRST = BIT_SET) + +/*! + * @brief Reset force reset + * + * @param None + * + * @retval None + */ +#define USBD_ResetForceReset() (USBD->CTRL_B.FORRST = BIT_RESET) + +/*! + * @brief Set power down + * + * @param None + * + * @retval None + */ +#define USBD_SetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_SET) + +/*! + * @brief Reset power down + * + * @param None + * + * @retval None + */ +#define USBD_ResetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_RESET) + +/*! + * @brief Set low power mode + * + * @param None + * + * @retval None + */ +#define USBD_SetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_SET) + +/*! + * @brief Ret low power mode + * + * @param None + * + * @retval None + */ +#define USBD_ResetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_RESET) + +/*! + * @brief Set force suspend + * + * @param None + * + * @retval None + */ +#define USBD_SetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_SET) + +/*! + * @brief Reset force suspend + * + * @param None + * + * @retval None + */ +#define USBD_ResetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_RESET) + +/*! + * @brief Read force suspend status + * + * @param None + * + * @retval None + */ +#define USBD_ReadForceSuspend() (USBD->CTRL_B.FORSUS) + +/*! + * @brief Set resume + * + * @param None + * + * @retval None + */ +#define USBD_SetResume() (USBD->CTRL_B.WUPREQ = BIT_SET) + +/*! + * @brief Reset resume + * + * @param None + * + * @retval None + */ +#define USBD_ResetResume() (USBD->CTRL_B.WUPREQ = BIT_RESET) + +/*! + * @brief Enable interrupt + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_EnableInterrupt(int) (USBD->CTRL |= int) + +/*! + * @brief Disable interrupt + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_DisableInterrupt(int) (USBD->CTRL &= (uint32_t)~int) + +/*! + * @brief Read the specified interrupt flag status + * + * @param int: Interrupt source + * + * @retval Flag status.0 or not 0 + */ +#define USBD_ReadIntFlag(int) (USBD->INTSTS & int) + +/*! + * @brief Clear the specified interrupt flag status + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_ClearIntFlag(int) (USBD->INTSTS &= (uint32_t)~int) + +/*! + * @brief Read DOT field value in INTSTS rigister + * + * @param None + * + * @retval DOT field value + */ +#define USBD_ReadDir() (USBD->INTSTS_B.DOT) + +/*! + * @brief Read EPID field value in INTSTS rigister + * + * @param None + * + * @retval EPIDfield value + */ +#define USBD_ReadEP() ((USBD_EP_T)(USBD->INTSTS_B.EPID)) + +/*! + * @brief Read EP type + * + * @param ep: EP number + * + * @retval EP type + */ +#define USBD_ReadEPType(ep) (USBD->EP[ep].EP_B.TYPE) + +/*! + * @brief Read EP Tx status + * + * @param ep: EP number + * + * @retval EP Tx status + */ +#define USBD_ReadEPTxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.TXSTS)) + +/*! + * @brief Read EP Rx status + * + * @param ep: EP number + * + * @retval EP Rx status + */ +#define USBD_ReadEPRxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.RXSTS)) + +/*! + * @brief Read EP Tx address pointer + * + * @param ep: EP number + * + * @retval EP Tx address pointer + */ +#define USBD_ReadEPTxAddrPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR) + + +/*! + * @brief Read EP Tx count pointer + * + * @param ep: EP number + * + * @retval EP Tx count pointer + */ +#define USBD_ReadEPTxCntPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx address pointer + * + * @param ep: EP number + * + * @retval EP Rx address pointer + */ +#define USBD_ReadEPRxAddrPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx count pointer + * + * @param ep: EP number + * + * @retval EP Rx count pointer + */ +#define USBD_ReadEPRxCntPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx addr + * + * @param ep: EP number + * + * @param addr: Tx addr + * + * @retval None + */ +#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Set EP Rx addr + * + * @param ep: EP number + * + * @param addr: Rx addr + * + * @retval None + */ +#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Read EP Tx addr + * + * @param ep: EP number + * + * @retval EP Tx addr + */ +#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep)) + +/*! + * @brief Read EP Rx addr + * + * @param ep: EP number + * + * @retval EP Rx addr + */ +#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep)) + +/*! + * @brief Set EP Rx Count + * + * @param ep: EP number + * + * @param cnt: Tx count + * + * @retval None + */ +#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt) + +/*! + * @brief Read EP Tx count + * + * @param ep: EP number + * + * @retval EP Tx count + */ +#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read EP Rx count + * + * @param ep: EP number + * + * @retval EP Rx count + */ +#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read SETUP field value in EP register + * + * @param ep: EP number + * + * @retval SETUP field value + */ +#define USBD_ReadEPSetup(ep) (USBD->EP[ep].EP_B.SETUP) + +/*! + * @brief Set buffer table value + * + * @param tab: Buffer table value + * + * @retval None + */ +#define USBD_SetBufferTable(tab) (USBD->BUFFTB_B.BUFFTB = tab) + +/*! + * @brief Set device address + * + * @param addr: Device address + * + * @retval None + */ +#define USBD_SetDeviceAddr(addr) (USBD->ADDR_B.ADDR = addr) + +/*! + * @brief Read CTFR field value in EP register + * + * @param ep: Endpoint number + * + * @retval CTFR field value + */ +#define USBD_ReadEPRxFlag(ep) (USBD->EP[ep].EP_B.CTFR) + +/*! + * @brief Read CTFT field value in EP register + * + * @param ep: Endpoint number + * + * @retval CTFT field value + */ +#define USBD_ReadEPTxFlag(ep) (USBD->EP[ep].EP_B.CTFT) + +/*! + * @brief Enable USBD peripheral + * + * @param None + * + * @retval None + */ +#define USBD_Enable() (USBD->ADDR_B.USBDEN = BIT_SET) + +/*! + * @brief Disable USBD peripheral + * + * @param None + * + * @retval None + */ +#define USBD_Disable() (USBD->ADDR_B.USBDEN = BIT_RESET) + +/*! + * @brief Enable USBD2 peripheral + * + * @param None + * + * @retval None + */ +#define USBD2_Enable() (USBD->SWITCH = BIT_SET) + +/*! + * @brief Disable USBD2 peripheral + * + * @param None + * + * @retval None + */ +#define USBD2_Disable() (USBD->SWITCH = BIT_RESET) + +/*! + * @brief Read RXDPSTS field value in FRANUM register + * + * @param None + * + * @retval RXDPSTS field value + */ +#define USBD_ReadRDPS() (USBD->FRANUM_B.RXDPSTS) + +/*! + * @brief Read RXDMSTS field value in FRANUM register + * + * @param None + * + * @retval RXDMSTS field value + */ +#define USBD_ReadRDMS() (USBD->FRANUM_B.RXDMSTS) + +/*! + * @brief Read LOCK field value in FRANUM register + * + * @param None + * + * @retval LOCK field value + */ +#define USBD_ReadLOCK() (USBD->FRANUM_B.LOCK) + +/*! + * @brief Read LSOFNUM field value in FRANUM register + * + * @param None + * + * @retval LSOFNUM field value + */ +#define USBD_ReadLSOF() (USBD->FRANUM_B.LSOFNUM) + +/*! + * @brief Read FRANUM field value in FRANUM register + * + * @param None + * + * @retval FRANUM field value + */ +#define USBD_ReadFRANUM() (USBD->FRANUM_B.FRANUM) + +void USBD_SetEPType(USBD_EP_T ep, USBD_EP_TYPE_T type); + +void USBD_SetEPKind(USBD_EP_T ep); +void USBD_ResetEPKind(USBD_EP_T ep); + +void USBD_ResetEPRxFlag(USBD_EP_T ep); +void USBD_ResetEPTxFlag(USBD_EP_T ep); + +void USBD_ToggleTx(USBD_EP_T ep); +void USBD_ToggleRx(USBD_EP_T ep); +void USBD_ResetTxToggle(USBD_EP_T ep); +void USBD_ResetRxToggle(USBD_EP_T ep); + +void USBD_SetEpAddr(USBD_EP_T ep, uint8_t addr); + +void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status); +void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status); +void USBD_SetEPRxTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus); + +void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt); + +void USBD_WriteDataToEP(USBD_EP_T ep, uint8_t *wBuf, uint32_t wLen); +void USBD_ReadDataFromEP(USBD_EP_T ep, uint8_t *rBuf, uint32_t rLen); + +/**@} end of group USBD_Fuctions*/ +/**@} end of group USBD_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_USBD_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h new file mode 100644 index 0000000000..cb958d3dcb --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h @@ -0,0 +1,78 @@ +/*! + * @file apm32f10x_wwdt.h + * + * @brief This file contains all the functions prototypes for the WWDT firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_WWDT_H +#define __APM32F10X_WWDT_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_Enumerations Enumerations + @{ +*/ + +/** + * @brief WWDT Timebase(Prescaler) define + */ +typedef enum +{ + WWDT_TIME_BASE_1 = 0x00000000, + WWDT_TIME_BASE_2 = 0x00000080, + WWDT_TIME_BASE_4 = 0x00000100, + WWDT_TIME_BASE_8 = 0x00000180 +}WWDT_TIME_BASE_T; + +/**@} end of group WWDT_Enumerations*/ + +/** @addtogroup WWDT_Fuctions Fuctions + @{ +*/ + +/** WWDT reset */ +void WWDT_Reset(void); + +/** Config WWDT Timebase */ +void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase); + +/** Config Window Data */ +void WWDT_ConfigWindowData(uint8_t windowData); + +/** Config Couter */ +void WWDT_ConfigCounter(uint8_t counter); + +/** Enable WWDT and Early Wakeup interrupt */ +void WWDT_EnableEWI(void); +void WWDT_Enable(uint8_t count); + +/** Read Flag and Clear Flag */ +uint8_t WWDT_ReadFlag(void); +void WWDT_ClearFlag(void); + +/**@} end of group WWDT_Fuctions*/ +/**@} end of group WWDT_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_WWDT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c new file mode 100644 index 0000000000..c061ca94d4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c @@ -0,0 +1,1058 @@ +/*! + * @file apm32f10x_adc.c + * + * @brief This file provides all the ADC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_adc.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup ADC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset ADC peripheral registers to their default reset values. + * + * @param adc: Select ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Reset(ADC_T* adc) +{ + if(adc == ADC1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1); + } + else if(adc == ADC2) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2); + } + else if (adc == ADC3) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC3); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC3); + } +} + +/*! + * @brief Config the ADC peripheral according to the specified parameters in the adcConfig. + * + * @param adc: Select ADC peripheral. + * + * @param adcConfig: pointer to a ADC_Config_T structure. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig) +{ + uint32_t reg; + + reg = adc->CTRL1; + reg &= 0xFFF0FEFF; + reg |= (uint32_t)((adcConfig->mode) | ((uint32_t)adcConfig->scanConvMode << 8)); + adc->CTRL1 = reg; + + reg = adc->CTRL2; + reg &= 0xFFF1F7FD; + reg |= (uint32_t)(adcConfig->dataAlign | adcConfig->externalTrigConv | + ((uint32_t)adcConfig->continuosConvMode << 1)); + adc->CTRL2 = reg; + + reg = adc->REGSEQ1; + reg &= 0xFF0FFFFF; + reg |= (uint32_t)((adcConfig->nbrOfChannel - (uint8_t)1) << 20); + adc->REGSEQ1 = reg; +} + +/*! + * @brief Fills each ADC_Config_T member with its default value. + * + * @param adcConfig: pointer to a ADC_Config_T structure which will be initialized. + * + * @retval None + */ +void ADC_ConfigStructInit(ADC_Config_T* adcConfig) +{ + adcConfig->mode = ADC_MODE_INDEPENDENT; + adcConfig->scanConvMode = DISABLE; + adcConfig->continuosConvMode = DISABLE; + adcConfig->externalTrigConv = ADC_EXT_TRIG_CONV_TMR1_CC1; + adcConfig->dataAlign = ADC_DATA_ALIGN_RIGHT; + adcConfig->nbrOfChannel = 1; +} + +/*! + * @brief Enables the specified ADC peripheral. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Enable(ADC_T* adc) +{ + adc->CTRL2_B.ADCEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC peripheral. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Disable(ADC_T* adc) +{ + adc->CTRL2_B.ADCEN = BIT_RESET; +} + +/*! + * @brief Disable the specified ADC DMA request. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableDMA(ADC_T* adc) +{ + adc->CTRL2_B.DMAEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC DMA request. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableDMA(ADC_T* adc) +{ + adc->CTRL2_B.DMAEN = BIT_RESET; +} + +/*! + * @brief Reset the specified ADC calibration registers. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ResetCalibration(ADC_T* adc) +{ + adc->CTRL2_B.CALRST = BIT_SET; +} + +/*! + * @brief Reads the specified ADC calibration reset status. + * + * @param adc: Select the ADC peripheral. + * + * @retval The status of ADC calibration reset. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Starts the specified ADC calibration. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_StartCalibration(ADC_T* adc) +{ + adc->CTRL2_B.CAL = BIT_SET; +} + +/*! + * @brief Reads the specified ADC calibration start flag. + * + * @param adc: Select the ADC peripheral. + * + * @retval The status of ADC calibration start. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Enables the specified ADC software start conversion. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableSoftwareStartConv(ADC_T* adc) +{ + adc->CTRL2 |= 0x00500000; +} + +/*! + * @brief Disable the specified ADC software start conversion. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableSoftwareStartConv(ADC_T* adc) +{ + adc->CTRL2 &= 0xFFAFFFFF; +} + +/*! + * @brief Reads the specified ADC Software start conversion Status. + * + * @param adc: Select the ADC peripheral. + * + * @retval The status of ADC Software start conversion registers. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Configures the specified ADC regular discontinuous mode. + * + * @param adc: Select the ADC peripheral. + * + * @param number: The number of the discontinuous mode regular channels. + * This parameter can be between 1 and 8. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number) +{ + adc->CTRL1_B.DISCNUMCFG |= number - 1; +} + +/*! + * @brief Enable the specified ADC regular discontinuous mode. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.REGDISCEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC regular discontinuous mode. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.REGDISCEN = BIT_RESET; +} + +/*! + * @brief Configures the specified ADC regular channel. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC channel. + * This parameter can be one of the following values: + * @arg ADC_CHANNEL_0: ADC channel 0 + * @arg ADC_CHANNEL_1: ADC channel 1 + * @arg ADC_CHANNEL_2: ADC channel 2 + * @arg ADC_CHANNEL_3: ADC channel 3 + * @arg ADC_CHANNEL_4: ADC channel 4 + * @arg ADC_CHANNEL_5: ADC channel 5 + * @arg ADC_CHANNEL_6: ADC channel 6 + * @arg ADC_CHANNEL_7: ADC channel 7 + * @arg ADC_CHANNEL_8: ADC channel 8 + * @arg ADC_CHANNEL_9: ADC channel 9 + * @arg ADC_CHANNEL_10: ADC channel 10 + * @arg ADC_CHANNEL_11: ADC channel 11 + * @arg ADC_CHANNEL_12: ADC channel 12 + * @arg ADC_CHANNEL_13: ADC channel 13 + * @arg ADC_CHANNEL_14: ADC channel 14 + * @arg ADC_CHANNEL_15: ADC channel 15 + * @arg ADC_CHANNEL_16: ADC channel 16 which is connected to TempSensor + * @arg ADC_CHANNEL_17: ADC channel 17 which is connected to Vrefint + * + * @param rank: The rank in the regular group sequencer + * This parameter must be between 1 to 16. + * + * @param sampleTime: the specified ADC channel SampleTime + * The parameter can be one of following values: + * @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles + * @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles + * @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles + * @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles + * @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles + * @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles + * @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles + * @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime) +{ + uint32_t temp1 = 0; + uint32_t temp2 = 0; + if(channel > ADC_CHANNEL_9) + { + temp1 = adc->SMPTIM1; + temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10)); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3 * (channel - 10)); + temp1 |= temp2; + adc->SMPTIM1 = temp1; + } + else + { + temp1 = adc->SMPTIM2; + temp2 = SMPCYCCFG_SET_SMPTIM2 << (3 * channel); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3 * channel); + temp1 |= temp2; + adc->SMPTIM2 = temp1; + } + + if(rank < 7) + { + temp1 = adc->REGSEQ3; + temp2 = REGSEQC_SET_REGSEQ3 << (5 * (rank - 1)); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (rank - 1)); + temp1 |= temp2; + adc->REGSEQ3 = temp1; + } + else if(rank < 13) + { + temp1 = adc->REGSEQ2; + temp2 = REGSEQC_SET_REGSEQ2 << (5 * (rank - 7)); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (rank - 7)); + temp1 |= temp2; + adc->REGSEQ2 = temp1; + } + else + { + temp1 = adc->REGSEQ1; + temp2 = REGSEQC_SET_REGSEQ1 << (5 * (rank - 13)); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (rank - 13)); + temp1 |= temp2; + adc->REGSEQ1 = temp1; + } +} + +/*! + * @brief Enable the specified ADC regular channel external trigger. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableExternalTrigConv(ADC_T* adc) +{ + adc->CTRL2_B.REGEXTTRGEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC regular channel external trigger. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableExternalTrigConv(ADC_T* adc) +{ + adc->CTRL2_B.REGEXTTRGEN = BIT_RESET; +} + +/*! + * @brief Reads the specified ADC conversion result data. + * + * @param adc: Select the ADC peripheral. + * + * @retval The Data conversion value. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint16_t ADC_ReadConversionValue(ADC_T* adc) +{ + return (uint16_t) adc->REGDATA; +} + +/*! + * @brief Reads the specified ADC conversion result data in dual mode. + * + * @param adc: Select the ADC peripheral. + * + * @retval The Data conversion value. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc) +{ + return (*(__IOM uint32_t *) RDG_ADDRESS); +} + +/*! + * @brief Enable the specified ADC automatic injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableInjectedConv(ADC_T* adc) +{ + adc->CTRL1_B.INJGACEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC automatic injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableInjectedConv(ADC_T* adc) +{ + adc->CTRL1_B.INJGACEN = BIT_RESET; +} + +/*! + * @brief Enable the specified ADC discontinuous mode for injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableInjectedDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.INJDISCEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC discontinuous mode for injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableInjectedDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.INJDISCEN = BIT_RESET; +} + +/*! + * @brief Configures the specified ADC external trigger for injected channels conversion + * + * @param adc: Select the ADC peripheral + * + * @param extTrigInjecConv: Select the ADC trigger to start injected conversion + * This parameter can be one of the following values: + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO : Select Timer1 TRGO event (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4 : Select Timer1 capture compare4 (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO : Select Timer2 TRGO event (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1 : Select Timer2 capture compare1 (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4 : Select Timer3 capture compare4 (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO : Select Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4: External interrupt line 15 or Timer8 capture compare4 event + * (for ADC1 and ADC2) + * + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3 : Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2 : Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4 : Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4 : Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_NONE : Injected conversion started by software instead of external trigger + * (for ADC1, ADC2 and ADC3) + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv) +{ + adc->CTRL2_B.INJGEXTTRGSEL = RESET; + adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv; +} + +/*! + * @brief Ensable the specified ADC injected channels conversion through + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableExternalTrigInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC injected channels conversion through + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableExternalTrigInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; +} + +/*! + * @brief Enable the specified ADC start of the injected + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_SET; + adc->CTRL2_B.INJSWSC = BIT_SET; +} + +/*! + * @brief Disable the specified ADC start of the injected + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; + adc->CTRL2_B.INJSWSC = BIT_RESET; +} + +/*! + * @brief Reads the specified ADC Software start injected conversion Status + * + * @param adc: Select the ADC peripheral + * + * @retval The status of ADC Software start injected conversion + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Configures the specified ADC injected channel. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_CHANNEL_0: ADC channel 0 + * @arg ADC_CHANNEL_1: ADC channel 1 + * @arg ADC_CHANNEL_2: ADC channel 2 + * @arg ADC_CHANNEL_3: ADC channel 3 + * @arg ADC_CHANNEL_4: ADC channel 4 + * @arg ADC_CHANNEL_5: ADC channel 5 + * @arg ADC_CHANNEL_6: ADC channel 6 + * @arg ADC_CHANNEL_7: ADC channel 7 + * @arg ADC_CHANNEL_8: ADC channel 8 + * @arg ADC_CHANNEL_9: ADC channel 9 + * @arg ADC_CHANNEL_10: ADC channel 10 + * @arg ADC_CHANNEL_11: ADC channel 11 + * @arg ADC_CHANNEL_12: ADC channel 12 + * @arg ADC_CHANNEL_13: ADC channel 13 + * @arg ADC_CHANNEL_14: ADC channel 14 + * @arg ADC_CHANNEL_15: ADC channel 15 + * @arg ADC_CHANNEL_16: ADC channel 16 which is connected to TempSensor + * @arg ADC_CHANNEL_17: ADC channel 17 which is connected to Vrefint + * + * @param rank: The rank in the injected group sequencer. + * This parameter must be between 1 to 4. + * + * @param sampleTime: the specified ADC channel SampleTime + * The parameter can be one of following values: + * @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles + * @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles + * @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles + * @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles + * @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles + * @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles + * @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles + * @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) +{ + uint32_t temp1 = 0; + uint32_t temp2 = 0; + uint32_t temp3 = 0; + if (channel > ADC_CHANNEL_9) + { + temp1 = adc->SMPTIM1; + temp2 = SMPCYCCFG_SET_SMPTIM1 << (3*(channel - 10)); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3*(channel - 10)); + temp1 |= temp2; + adc->SMPTIM1 = temp1; + } + else + { + temp1 = adc->SMPTIM2; + temp2 = SMPCYCCFG_SET_SMPTIM2 << (3 * channel); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3 * channel); + temp1 |= temp2; + adc->SMPTIM2 = temp1; + } + temp1 = adc->INJSEQ; + temp3 = (temp1 & INJSEQ_SET_INJSEQLEN)>> 20; + temp2 = INJSEQ_SET_INJSEQC << (5 * (uint8_t)((rank + 3) - (temp3 + 1))); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (uint8_t)((rank + 3) - (temp3 + 1))); + temp1 |= temp2; + adc->INJSEQ = temp1; +} + +/*! + * @brief Configures the specified ADC injected channel. + * + * @param adc: Select the ADC peripheral. + * + * @param length: The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length) +{ + adc->INJSEQ_B.INJSEQLEN = RESET; + adc->INJSEQ_B.INJSEQLEN |= length - 1; +} + +/*! + * @brief Configures the specified ADC injected channel conversion value offset. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJEC_CHANNEL_1: select Injected Channel 1 + * @arg ADC_INJEC_CHANNEL_2: select Injected Channel 2 + * @arg ADC_INJEC_CHANNEL_3: select Injected Channel 3 + * @arg ADC_INJEC_CHANNEL_4: select Injected Channel 4 + * + * @param offSet: The specified ADC injected channel offset. + * This parameter must be a 12bit value. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet) +{ + __IOM uint32_t tmp = 0; + + tmp = (uint32_t)adc; + tmp += channel; + + *(__IOM uint32_t *) tmp = (uint32_t)offSet; +} + +/*! + * @brief Reads the ADC injected channel conversion value. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJEC_CHANNEL_1: select Injected Channel 1 + * @arg ADC_INJEC_CHANNEL_2: select Injected Channel 2 + * @arg ADC_INJEC_CHANNEL_3: select Injected Channel 3 + * @arg ADC_INJEC_CHANNEL_4: select Injected Channel 4 + * + * @retval The Data of conversion value. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel) +{ + __IOM uint32_t temp = 0; + + temp = (uint32_t)adc; + temp += channel + INJDATA_OFFSET; + + return (uint16_t) (*(__IOM uint32_t*) temp); +} + +/*! + * @brief Enable the specified ADC analog watchdog. + * + * @param adc: Select the ADC peripheral. + * + * @param analogWatchdog: The ADC analog watchdog configuration + * This parameter can be one of the following values: + * @arg ADC_ANALOG_WATCHDOG_SINGLE_REG : Analog watchdog on a single regular channel + * @arg ADC_ANALOG_WATCHDOG_SINGLE_INJEC : Analog watchdog on a single injected channel + * @arg ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC : Analog watchdog on a single regular or injected channel + * @arg ADC_ANALOG_WATCHDOG_ALL_REG : Analog watchdog on all regular channel + * @arg ADC_ANALOG_WATCHDOG_ALL_INJEC : Analog watchdog on all injected channel + * @arg ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC : Analog watchdog on all regular and injected channels + * @arg ADC_ANALOG_WATCHDOG_NONE : No channel guarded by the analog watchdog + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog) +{ + adc->CTRL1 &= 0xFF3FFDFF; + adc->CTRL1 |= analogWatchdog; +} + +/*! + * @brief Disable the specified ADC analog watchdog. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableAnalogWatchdog(ADC_T* adc) +{ + adc->CTRL1 &= 0xFF3FFDFF; +} + +/*! + * @brief Configures the specified ADC high and low thresholds of the analog watchdog. + * + * @param adc: Select the ADC peripheral. + * + * @param highThreshold: The ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * + * @param lowThreshold: The ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold) +{ + adc->AWDHT = highThreshold; + adc->AWDLT = lowThreshold; +} + +/*! + * @brief Configures the specified ADC analog watchdog guarded single channel + * + * @param adc: Select the ADC peripheral + * + * @param channel: Select the ADC channel + * This parameter can be one of the following values: + * @arg ADC_Channel_0: Select ADC Channel 0 + * @arg ADC_Channel_1: Select ADC Channel 1 + * @arg ADC_Channel_2: Select ADC Channel 2 + * @arg ADC_Channel_3: Select ADC Channel 3 + * @arg ADC_Channel_4: Select ADC Channel 4 + * @arg ADC_Channel_5: Select ADC Channel 5 + * @arg ADC_Channel_6: Select ADC Channel 6 + * @arg ADC_Channel_7: Select ADC Channel 7 + * @arg ADC_Channel_8: Select ADC Channel 8 + * @arg ADC_Channel_9: Select ADC Channel 9 + * @arg ADC_Channel_10: Select ADC Channel 10 + * @arg ADC_Channel_11: Select ADC Channel 11 + * @arg ADC_Channel_12: Select ADC Channel 12 + * @arg ADC_Channel_13: Select ADC Channel 13 + * @arg ADC_Channel_14: Select ADC Channel 14 + * @arg ADC_Channel_15: Select ADC Channel 15 + * @arg ADC_Channel_16: Select ADC Channel 16 which is connected to TempSensor + * @arg ADC_Channel_17: Select ADC Channel 17 which is connected to Vrefint + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel) +{ + adc->CTRL1_B.AWDCHSEL = BIT_RESET; + adc->CTRL1 |= channel; +} + +/*! + * @brief Enable the specified ADC temperature sensor and Vrefint channel. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableTempSensorVrefint(ADC_T* adc) +{ + adc->CTRL2_B.TSVREFEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC temperature sensor and Vrefint channel. + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableTempSensorVrefint(ADC_T* adc) +{ + adc->CTRL2_B.TSVREFEN = BIT_RESET; +} + +/*! + * @brief Enable the specified ADC interrupt. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt sources + * This parameter can be any combination of the following values: + * @arg ADC_INT_AWD : Enable Analog watchdog interrupt + * @arg ADC_INT_EOC : Enable End of conversion interrupt + * @arg ADC_INT_INJEOC : Enable End of injected conversion interrupt + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt) +{ + uint8_t mask; + + mask = (uint8_t)interrupt; + adc->CTRL1 |= (uint8_t)mask; +} + +/*! + * @brief Disable the specified ADC interrupt. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt sources + * This parameter can be any combination of the following values: + * @arg ADC_INT_AWD : Disable Analog watchdog interrupt + * @arg ADC_INT_EOC : Disable End of conversion interrupt + * @arg ADC_INT_INJEOC : Disable End of injected conversion interrupt + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt) +{ + uint8_t mask; + + mask = (uint8_t)interrupt; + adc->CTRL1 &= (~(uint32_t)mask); +} + +/*! + * @brief Reads the specified ADC flag + * + * @param adc: Select the ADC peripheral + * + * @param flag: Select the flag to check + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD : Analog watchdog flag + * @arg ADC_FLAG_EOC : End of conversion flag + * @arg ADC_FLAG_INJEOC: End of injected group conversion flag + * @arg ADC_FLAG_INJCS : Injected group conversion Start flag + * @arg ADC_FLAG_REGCS : Regular group conversion Start flag + * + * @retval The status of ADC flag + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag) +{ + uint8_t status = RESET; + + if ((adc->STS & flag) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the specified ADC flag + * + * @param adc: Select the ADC peripheral + * + * @param flag: Select the flag to clear + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD : Analog watchdog flag + * @arg ADC_FLAG_EOC : End of conversion flag + * @arg ADC_FLAG_INJEOC: End of injected group conversion flag + * @arg ADC_FLAG_INJCS : Injected group conversion Start flag + * @arg ADC_FLAG_REGCS : Regular group conversion Start flag + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag) +{ + adc->STS = ~(uint32_t)flag; +} + +/*! + * @brief Reads the specified ADC Interrupt flag. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt source. + * This parameter can be one of the following values: + * @arg ADC_INT_AWD : Enable Analog watchdog interrupt + * @arg ADC_INT_EOC : Enable End of conversion interrupt + * @arg ADC_INT_INJEOC : Enable End of injected conversion interrupt + * + * @retval The status of ADC interrupt + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt) +{ + uint8_t bitStatus = RESET; + uint32_t itmask = 0; + uint32_t enableStatus = 0; + + itmask = interrupt >> 8; + enableStatus = (adc->CTRL1 & (uint8_t)interrupt); + + if (((adc->STS & itmask) != (uint32_t)RESET) && enableStatus) + { + bitStatus = SET; + } + else + { + bitStatus = RESET; + } + return bitStatus; +} + +/*! + * @brief Clears the specified ADC Interrupt pending bits. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt source. + * This parameter can be any combination of the following values: + * @arg ADC_INT_AWD : Enable Analog watchdog interrupt + * @arg ADC_INT_EOC : Enable End of conversion interrupt + * @arg ADC_INT_INJEOC : Enable End of injected conversion interrupt + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt) +{ + uint8_t mask = 0; + + mask = (uint8_t)(interrupt >> 8); + adc->STS = ~(uint32_t)mask; +} + +/**@} end of group ADC_Fuctions*/ +/**@} end of group ADC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c new file mode 100644 index 0000000000..a7bfad2fdb --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c @@ -0,0 +1,234 @@ +/*! + * @file apm32f10x_bakpr.c + * + * @brief This file provides all the BAKPR firmware functions. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_bakpr.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup BAKPR_Driver ADC Driver + @{ +*/ + +/** @addtogroup BAKPR_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the BAKPR peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void BAKPR_Reset(void) +{ + RCM_EnableBackupReset(); + RCM_DisableBackupReset(); +} + +/*! + * @brief Deinitializes the BAKPR peripheral registers to their default reset values. + * + * @param value: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BAKPR_TAMPER_PIN_LEVEL_HIGH: Tamper pin active on high level + * @arg BAKPR_TAMPER_PIN_LEVEL_LOW: Tamper pin active on low level + * + * @retval None + */ +void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value) +{ + BAKPR->CTRL_B.TPALCFG = value; +} + +/*! + * @brief Enables the Tamper Pin activation. + * + * @param None + * + * @retval None + */ +void BAKPR_EnableTamperPin(void) +{ + BAKPR->CTRL_B.TPFCFG = ENABLE ; +} + +/*! + * @brief Disables the Tamper Pin activation. + * + * @param None + * + * @retval None + */ +void BAKPR_DisableTamperPin(void) +{ + BAKPR->CTRL_B.TPFCFG = DISABLE ; +} + +/*! + * @brief Enables the Tamper Pin Interrupt. + * + * @param None + * + * @retval None + */ +void BAKPR_EnableInterrupt(void) +{ + BAKPR->CSTS_B.TPIEN = ENABLE ; +} + +/*! + * @brief Disables the Tamper Pin Interrupt. + * + * @param None + * + * @retval None + */ +void BAKPR_DisableInterrupt(void) +{ + BAKPR->CSTS_B.TPIEN = DISABLE ; +} + +/*! + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param soure: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BAKPR_RTC_OUTPUT_SOURCE_NONE : no RTC output on the Tamper pin. + * @arg BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK: output the RTC clock with frequency divided by 64 on the Tamper pin. + * @arg BAKPR_RTC_OUTPUT_SOURCE_ALARM : output the RTC Alarm pulse signal on the Tamper pin. + * @arg BAKPR_RTC_OUTPUT_SOURCE_SECOND : output the RTC Second pulse signal on the Tamper pin. + * + * @retval None + */ +void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure) +{ + if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE) + { + BAKPR->CLKCAL = RESET; + } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK) + { + BAKPR->CLKCAL_B.CALCOEN = BIT_SET; + } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM) + { + BAKPR->CLKCAL_B.ASPOEN = BIT_SET; + } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND) + { + BAKPR->CLKCAL_B.ASPOSEL = BIT_SET; + } +} + +/*! + * @brief Sets RTC Clock Calibration value. + * + * @param calibrationValue: Specifies the calibration value. + * This parameter must be a number between 0 and 0x7F. + * + * @retval None + */ +void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue) +{ + BAKPR->CLKCAL_B.CALVALUE = calibrationValue; +} + +/*! + * @brief Set user data to the specified Data Backup Register. + * + * @param bakrData : specifies the Data Backup Register. + * This parameter can be BAKPR_DATAx where x is between 1 and 42. + * + * @param data : data to set + * This parameter can be a 16bit value. + * + * @retval None + */ +void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data) +{ + __IOM uint32_t tmp = 0; + + tmp = (uint32_t)BAKPR_BASE; + tmp += bakrData; + + *(__IOM uint32_t *) tmp = data; +} + +/*! + * @brief Reads user data from the specified Data Backup Register. + * + * @param bakrData : specifies the Data Backup Register. + * This parameter can be BAKPR_DATAx where x is between 1 and 42. + * + * @retval The content of the specified Data Backup Register + */ +uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData) +{ + __IOM uint32_t tmp = 0; + + tmp = (uint32_t)BAKPR_BASE; + tmp += bakrData; + + return (*(__IOM uint32_t *) tmp); +} + +/*! + * @brief Read whether the Tamper Pin Event flag is set or not. + * + * @param None + * + * @retval Tamper Pin Event flag state + */ +uint8_t BAKPR_ReadStatusFlag(void) +{ + return BAKPR->CSTS_B.TEFLG; +} + +/*! + * @brief Clears Tamper Pin Event pending flag. + * + * @param None + * + * @retval None + */ +void BAKPR_ClearStatusFlag(void) +{ + BAKPR->CSTS_B.TECLR = BIT_SET; +} + +/*! + * @brief Get whether the Tamper Pin Interrupt has occurred or not. + * + * @param None + * + * @retval Tamper Pin Interrupt State + */ +uint8_t BAKPR_ReadIntFlag(void) +{ + return BAKPR->CSTS_B.TIFLG; +} + +/*! + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @param None + * + * @retval None + */ +void BAKPR_ClearIntFlag(void) +{ + BAKPR->CSTS_B.TICLR = BIT_SET; +} + +/**@} end of group BAKPR_Fuctions*/ +/**@} end of group BAKPR_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c new file mode 100644 index 0000000000..7efff90f9d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c @@ -0,0 +1,1110 @@ +/*! + * @file apm32f10x_can.c + * + * @brief This file provides all the CAN firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_can.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset CAN registers + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_Reset(CAN_T* can) +{ + if (can == CAN1) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CAN1); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CAN1); + } + else if (can == CAN2) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CAN2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CAN2); + } +} + +/*! + * @brief Initialization parameter configuration + * + * @param can: Select the CAN peripheral which can be CAN1 or CAN2. + * + * @param canConfig: Point to a CAN_Config_T structure. + * + * @retval ERROR or SUCCEESS + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) +{ + uint8_t initStatus = ERROR; + uint32_t wait_ack = 0x00000000; + + /** Exit from sleep mode */ + can->MCTRL_B.SLEEPREQ = BIT_RESET; + /** Request initialisation */ + can->MCTRL_B.INITREQ = BIT_SET; + + /** Wait the acknowledge */ + while(((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF)) + { + wait_ack++; + } + /** Check acknowledge */ + if(((can->MSTS_B.INITFLG) != BIT_SET)) + { + initStatus = ERROR; + } + else + { + if(canConfig->timeTrigComMode == ENABLE) + { + can->MCTRL_B.TTCM = BIT_SET; + } + else + { + can->MCTRL_B.TTCM = BIT_RESET; + } + + if(canConfig->autoBusOffManage == ENABLE) + { + can->MCTRL_B.ALBOFFM = BIT_SET; + } + else + { + can->MCTRL_B.ALBOFFM = BIT_RESET; + } + + if(canConfig->autoWakeUpMode == ENABLE) + { + can->MCTRL_B.AWUPCFG = BIT_SET; + } + else + { + can->MCTRL_B.AWUPCFG = BIT_RESET; + } + + if(canConfig->nonAutoRetran == ENABLE) + { + can->MCTRL_B.ARTXMD = BIT_SET; + } + else + { + can->MCTRL_B.ARTXMD = BIT_RESET; + } + + if(canConfig->rxFIFOLockMode == ENABLE) + { + can->MCTRL_B.RXFLOCK = BIT_SET; + } + else + { + can->MCTRL_B.RXFLOCK = BIT_RESET; + } + + if(canConfig->txFIFOPriority == ENABLE) + { + can->MCTRL_B.TXFPCFG = BIT_SET; + } + else + { + can->MCTRL_B.TXFPCFG = BIT_RESET; + } + + /** Set the bit timing register */ + can->BITTIM &= (uint32_t)0x3fffffff; + can->BITTIM |= (uint32_t)canConfig->mode << 30; + can->BITTIM_B.RSYNJW = canConfig->syncJumpWidth; + can->BITTIM_B.TIMSEG1 = canConfig->timeSegment1; + can->BITTIM_B.TIMSEG2 = canConfig->timeSegment2; + can->BITTIM_B.BRPSC = canConfig->prescaler - 1; + + /** Request leave initialisation */ + can->MCTRL_B.INITREQ = BIT_RESET; + + wait_ack = 0; + /** Wait the acknowledge */ + while(((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF)) + { + wait_ack++; + } + /** Check acknowledge */ + if(((can->MSTS_B.INITFLG) != BIT_RESET)) + { + initStatus = ERROR; + } + else + { + initStatus = SUCCESS; + } + } + return initStatus; +} + +/*! + * @brief Congig the CAN peripheral according to the specified parameters in the filterConfig. + * + * @param can: Select the CAN peripheral which can be CAN1 or CAN2. + * + * @param filterConfig :Point to a CAN_FILTER_CONFIG_T structure. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig) +{ + can->FCTRL_B.FINITEN = BIT_SET; + + can->FACT &= ~(1 << filterConfig->filterNumber); + + /** Filter Scale */ + if(filterConfig->filterScale == CAN_FILTER_SCALE_16BIT) + { + /** 16-bit scale for the filter */ + can->FSCFG &= ~(1 << filterConfig->filterNumber); + + can->sFilterRegister[filterConfig->filterNumber].FBANK1 = + ((0x0000FFFF & filterConfig->filterMaskIdLow) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + can->sFilterRegister[filterConfig->filterNumber].FBANK2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdHigh); + } + + if(filterConfig->filterScale == CAN_FILTER_SCALE_32BIT) + { + can->FSCFG |= (1 << filterConfig->filterNumber); + + can->sFilterRegister[filterConfig->filterNumber].FBANK1 = + ((0x0000FFFF & filterConfig->filterIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + can->sFilterRegister[filterConfig->filterNumber].FBANK2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterMaskIdLow); + } + + /** Filter Mode */ + if(filterConfig->filterMode == CAN_FILTER_MODE_IDMASK) + { + can->FMCFG &= ~(1 << filterConfig->filterNumber); + } + else + { + can->FMCFG |= (1 << filterConfig->filterNumber); + } + + /** Filter FIFO assignment */ + if(filterConfig->filterFIFO == CAN_FILTER_FIFO_0) + { + can->FFASS &= ~(1 << filterConfig->filterNumber); + } + if(filterConfig->filterFIFO == CAN_FILTER_FIFO_1) + { + can->FFASS |= (1 << filterConfig->filterNumber); + } + + /** Filter activation */ + if(filterConfig->filterActivation == ENABLE) + { + can->FACT |= (1 << filterConfig->filterNumber); + } + can->FCTRL_B.FINITEN = BIT_RESET; +} + +/*! + * @brief Initialize a CAN_Config_T structure with the initial value. + * + * @param canConfig :Point to a CAN_Config_T structure. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ConfigStructInit(CAN_Config_T* canConfig) +{ + canConfig->timeTrigComMode = DISABLE; + canConfig->autoBusOffManage = DISABLE; + canConfig->autoWakeUpMode = DISABLE; + canConfig->nonAutoRetran = DISABLE; + canConfig->rxFIFOLockMode = DISABLE; + canConfig->txFIFOPriority = DISABLE; + canConfig->mode = CAN_MODE_NORMAL; + canConfig->syncJumpWidth = CAN_SJW_1; + canConfig->timeSegment1 = CAN_TIME_SEGMENT1_4; + canConfig->timeSegment2 = CAN_TIME_SEGMENT2_3; + canConfig->prescaler = 1; +} + +/*! + * @brief Enables the DBG Freeze for CAN. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_EnableDBGFreeze(CAN_T* can) +{ + can->MCTRL_B.DBGFRZE = ENABLE; +} + +/*! + * @brief Disable the DBG Freeze for CAN. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_DisableDBGFreeze(CAN_T* can) +{ + can->MCTRL_B.DBGFRZE = DISABLE; +} + +/*! + * @brief Enables the CAN Time TriggerOperation communication mode. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_EnableTTCComMode(CAN_T* can) +{ + can->MCTRL_B.TTCM = ENABLE; + + can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_SET; + can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_SET; + can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_SET; +} + +/*! + * @brief Disable the CAN Time TriggerOperation communication mode. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_DisableTTCComMode(CAN_T* can) +{ + can->MCTRL_B.TTCM = DISABLE; + + can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_RESET; + can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_RESET; + can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_RESET; +} + +/*! + * @brief Initiates the transmission of a message. + * + * @param can: Select the CAN peripheral. + * + * @param TxMessage: pointer to a CAN_TX_MESSAGE_T structure. + * + * @retval The number of the mailbox which is used for transmission or 3 if No mailbox is empty. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage) +{ + uint8_t transmit_milbox = 0; + + /** Select one empty transmit mailbox */ + if((can->TXSTS & 0x04000000) == 0x04000000) + { + transmit_milbox = 0; + } + else if((can->TXSTS & 0x08000000) == 0x08000000) + { + transmit_milbox = 1; + } + else if((can->TXSTS & 0x10000000) == 0x10000000) + { + transmit_milbox = 2; + } else + { + return 3; //!< No mailbox is empty + } + + /** Set up the Id */ + can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001; + if(TxMessage->typeID == CAN_TYPEID_STD) + { + can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->stdID << 21) | (TxMessage->remoteTxReq); + } else + { + can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq); + } + + /** Set up the TXDLEN */ + TxMessage->dataLengthCode &= 0x0F; + can->sTxMailBox[transmit_milbox].TXDLEN &= (uint32_t)0xFFFFFFF0; + can->sTxMailBox[transmit_milbox].TXDLEN |= TxMessage->dataLengthCode; + + /** Set up the data field */ + can->sTxMailBox[transmit_milbox].TXMDL = ((uint32_t)TxMessage->data[3] << 24) | ((uint32_t)TxMessage->data[2] << 16) + | ((uint32_t)TxMessage->data[1] << 8) | ((uint32_t)TxMessage->data[0]); + can->sTxMailBox[transmit_milbox].TXMDH = ((uint32_t)TxMessage->data[7] << 24) | ((uint32_t)TxMessage->data[6] << 16) + | ((uint32_t)TxMessage->data[5] << 8) | ((uint32_t)TxMessage->data[4]); + /** Request transmission */ + can->sTxMailBox[transmit_milbox].TXMID |= 0x00000001; + + return transmit_milbox; +} + +/*! + * @brief Checks the transmission of a message. + * + * @param can: Select the CAN peripheral. + * + * @param transmitMailbox: the number of the mailbox + * + * @retval state: 0: Status of transmission is Failed + * 1: Status of transmission is Ok + * 2: transmit pending + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) +{ + uint32_t state = 0; + + switch (TxMailbox) + { + case (CAN_TX_MAILBIX_0): + state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000); + break; + case (CAN_TX_MAILBIX_1): + state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000); + break; + case (CAN_TX_MAILBIX_2): + state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000); + break; + default: + state = 0; + break; + } + switch (state) + { + /** transmit pending */ + case (0x0): state = 2; + break; + /* transmit failed */ + case (0x00000001 | 0x04000000): state = 0; + break; + case (0x00000100 | 0x08000000): state = 0; + break; + case (0x00010000 | 0x10000000): state = 0; + break; + /* transmit succeeded */ + case (0x00000001 | 0x00000002 | 0x04000000):state = 1; + break; + case (0x00000100 | 0x00000200 | 0x08000000):state = 1; + break; + case (0x00010000 | 0x00020000 | 0x10000000):state = 1; + break; + default: state = 0; + break; + } + return (uint8_t) state; +} + +/*! + * @brief Cancels a transmit request. + * + * @param can: Select the CAN peripheral. + * + * @param mailBox: the number of the mailbox + * This parameter can be one of the following values: + * @arg CAN_TX_MAILBIX_0 : Tx mailbox 0 + * @arg CAN_TX_MAILBIX_1 : Tx mailbox 1 + * @arg CAN_TX_MAILBIX_2 : Tx mailbox 2 + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) +{ + switch (TxMailbox) + { + case CAN_TX_MAILBIX_0: + can->TXSTS_B.ABREQFLG0 = BIT_SET; + break; + case CAN_TX_MAILBIX_1: + can->TXSTS_B.ABREQFLG1 = BIT_SET; + break; + case CAN_TX_MAILBIX_2: + can->TXSTS_B.ABREQFLG2 = BIT_SET; + break; + default: + break; + } +} + +/*! + * @brief Receives a message and save to a CAN_RX_MESSAGE_T structure. + * + * @param can: Select the CAN peripheral. + * + * @param FIFONumber: Receive FIFO number. + * This parameter can be one of the following values: + * @arg CAN_RX_FIFO_0 : Receive FIFO 0 + * @arg CAN_RX_FIFO_1 : Receive FIFO 1 + * + * @param RxMessage: pointer to a structure to receive the message. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage) +{ + /* Get the Id */ + RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID)); + if(RxMessage->typeID == CAN_TYPEID_STD) + { + RxMessage->stdID = (can->sRxMailBox[FIFONumber].RXMID >> 21) & 0x000007FF; + } + else + { + RxMessage->extID = (can->sRxMailBox[FIFONumber].RXMID >> 3) & 0x1FFFFFFF; + } + + RxMessage->remoteTxReq = can->sRxMailBox[FIFONumber].RXMID_B.RFTXREQ; + RxMessage->dataLengthCode = can->sRxMailBox[FIFONumber].RXDLEN_B.DLCODE; + RxMessage->filterMatchIndex = can->sRxMailBox[FIFONumber].RXDLEN_B.FMIDX; + /** Get the data field */ + RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1; + RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2; + RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE3; + RxMessage->data[3] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE4; + RxMessage->data[4] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE5; + RxMessage->data[5] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6; + RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7; + RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE8; + + if(FIFONumber == CAN_RX_FIFO_0) + { + can->RXF0_B.RFOM0 = BIT_SET; + } + else + { + can->RXF1_B.RFOM1 = BIT_SET; + } +} + +/*! + * @brief Releases the specified FIFO. + * + * @param can: Select the CAN peripheral. + * + * @param FIFONumber: Receive FIFO number + * This parameter can be one of the following values: + * @arg CAN_RX_FIFO_0 : Receive FIFO 0 + * @arg CAN_RX_FIFO_1 : Receive FIFO 1 + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber) +{ + if(FIFONumber == CAN_RX_FIFO_0) + { + can->RXF0_B.RFOM0 = BIT_SET; + } + else + { + can->RXF1_B.RFOM1 = BIT_SET; + } +} + +/*! + * @brief Returns the number of pending messages. + * + * @param can: Select the CAN peripheral. + * + * @param FIFONumber: Receive FIFO number + * This parameter can be one of the following values: + * @arg CAN_RX_FIFO_0 : Receive FIFO 0 + * @arg CAN_RX_FIFO_1 : Receive FIFO 1 + * + * @retval The number of pending message. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber) +{ + if(FIFONumber == CAN_RX_FIFO_0) + { + return can->RXF0 & 0x03; + } + else + { + return can->RXF1 & 0x03; + } +} + +/*! + * @brief Select the CAN Operation mode + * + * @param can: Select the CAN peripheral. + * + * @param operatingMode: CAN Operating Mode + * This parameter can be one of the following values: + * @arg CAN_OPERATING_MODE_INIT : Initialization mode + * @arg CAN_OPERATING_MODE_NORMAL: Normal mode + * @arg CAN_OPERATING_MODE_SLEEP : sleep mode + * + * @retval modeState:status of the requested mode + * 0:CAN failed entering the specific mode + * 1:CAN Succeed entering the specific mode + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode) +{ + uint8_t states = 0; + uint32_t time_out = 0x0000FFFF; + + if(operatingMode == CAN_OPERATING_MODE_INIT) + { + can->MCTRL_B.SLEEPREQ = BIT_RESET; + can->MCTRL_B.INITREQ = BIT_SET; + + while((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + { + time_out --; + } + if((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET)) + { + states = 1; + } + } + else if(operatingMode == CAN_OPERATING_MODE_NORMAL) + { + can->MCTRL_B.SLEEPREQ = BIT_RESET; + can->MCTRL_B.INITREQ = BIT_RESET; + + time_out = 0x0000FFFF; + + while((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + { + time_out --; + } + if((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET)) + { + states = 1; + } + } + else if(operatingMode == CAN_OPERATING_MODE_SLEEP) + { + can->MCTRL_B.SLEEPREQ = BIT_SET; + can->MCTRL_B.INITREQ = BIT_RESET; + + time_out = 0x0000FFFF; + + while((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0)) + { + time_out --; + } + if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) + { + states = 1; + } + } + return states ; +} + +/*! + * @brief Into the low power mode. + * + * @param can: Select the CAN peripheral. + * + * @retval status: Status of entering sleep mode. + * 0: Enter sleep fail + * 1: Enter sleep success + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_SleepMode(CAN_T* can) +{ + can->MCTRL_B.SLEEPREQ = BIT_SET; + can->MCTRL_B.INITREQ = BIT_RESET; + + if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) + { + return 1; + } + return 0; +} + +/*! + * @brief Wakes the CAN up. + * + * @param can: Select the CAN peripheral. + * + * @retval status: Status of waking the CAN up + * 0: WakeUp CAN fail, + * 1: WakeUp CAN success + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_WakeUpMode(CAN_T* can) +{ + uint32_t time_out = 0x0000FFFF; + + can->MCTRL_B.SLEEPREQ = BIT_RESET; + while((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + { + time_out --; + } + if(can->MSTS_B.SLEEPFLG == BIT_RESET) + { + return 1; + } + return 0; +} + +/*! + * @brief Read the can's last error code (LERRC) + * + * @param can: Select the CAN peripheral. + * + * @retval The Last Error Code. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadLastErrorCode(CAN_T* can) +{ + return can->ERRSTS_B.LERRC; +} + +/*! + * @brief Read the can Receive Error Counter(RXERRCNT) + * + * @param can: Select the CAN peripheral. + * + * @retval CAN Receive Error Counter. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadRxErrorCounter(CAN_T* can) +{ + return can->ERRSTS_B.RXERRCNT; +} + +/*! + * @brief Read the LSB of the 9-bit can Transmit Error Counter(TXERRCNT). + * + * @param can: Select the CAN peripheral. + * + * @retval Least Significant Byte Of The 9-Bit Transmit Error Counter. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can) +{ + return can->ERRSTS_B.TXERRCNT; +} + +/*! + * @brief Enables the specified can interrupts. + * + * @param can: Select the CAN peripheral. + * + * @param interrupts: specifies the CAN interrupt sources + * This parameter can be any combination of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts) +{ + can->INTEN |= interrupts; +} + +/*! + * @brief Disable the specified can interrupts. + * + * @param can: Select the CAN peripheral. + * + * @param interrupts: specifies the CAN interrupt sources + * This parameter can be any combination of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts) +{ + can->INTEN &= ~interrupts; +} + +/*! + * @brief Read whether the specified CAN flag is set or not. + * + * @param can: Select the CAN peripheral. + * + * @param flag: specifies the CAN flag. + * This parameter can be one of the following values: + * @arg CAN_FLAG_ERRW : Error Warning Flag + * @arg CAN_FLAG_ERRP : Error Passive Flag + * @arg CAN_FLAG_BOF : Bus-Off Flag + * @arg CAN_FLAG_LERRC : Last error record code Flag + * @arg CAN_FLAG_WUPI : Wake up Flag + * @arg CAN_FLAG_SLEEP : Sleep acknowledge Flag + * @arg CAN_FLAG_F0MP : FIFO 0 Message Pending Flag + * @arg CAN_FLAG_F0FULL : FIFO 0 Full Flag + * @arg CAN_FLAG_F0OVR : FIFO 0 Overrun Flag + * @arg CAN_FLAG_F1MP : FIFO 1 Message Pending Flag + * @arg CAN_FLAG_F1FULL : FIFO 1 Full Flag + * @arg CAN_FLAG_F1OVR : FIFO 1 Overrun Flag + * @arg CAN_FLAG_REQC0 : Request MailBox0 Flag + * @arg CAN_FLAG_REQC1 : Request MailBox1 Flag + * @arg CAN_FLAG_REQC2 : Request MailBox2 Flag + * + * @retval flag staus: RESET or SET + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) +{ + uint8_t status = 0; + + if((flag & 0x00F00000) != RESET ) + { + if((can->ERRSTS & (flag & 0x000FFFFF)) != RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + else if((flag & 0x01000000) != RESET ) + { + if((can->MSTS & (flag & 0x000FFFFF)) != RESET ) + { + status = SET; + } + else + { + status = RESET ; + } + } + else if((flag & 0x08000000) != RESET ) + { + if((can->TXSTS & (flag & 0x000FFFFF)) != RESET ) + { + status = SET; + } + else + { + status = RESET; + } + } + else if((flag & 0x02000000) != RESET ) + { + if((can->RXF0 & (flag & 0x000FFFFF)) != RESET ) + { + status = SET; + } + else + { + status = RESET; + } + } + else + { + if((can->RXF1 & (flag & 0x000FFFFF)) != RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + return status; +} + +/*! + * @brief Clears the CAN's pending flags. + * + * @param can: Select the CAN peripheral. + * + * @param flag: specifies the CAN flag. + * This parameter can be one of the following values: + * @arg CAN_FLAG_LERRC : Last error record code Flag + * @arg CAN_FLAG_WUPI : Wake up Flag + * @arg CAN_FLAG_SLEEP : Sleep acknowledge Flag + * @arg CAN_FLAG_F0FULL: FIFO 0 Full Flag + * @arg CAN_FLAG_F0OVR : FIFO 0 Overrun Flag + * @arg CAN_FLAG_F1FULL: FIFO 1 Full Flag + * @arg CAN_FLAG_F1OVR : FIFO 1 Overrun Flag + * @arg CAN_FLAG_REQC0 : Request MailBox0 Flag + * @arg CAN_FLAG_REQC1 : Request MailBox1 Flag + * @arg CAN_FLAG_REQC2 : Request MailBox2 Flag + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag) +{ + uint32_t flagtmp = 0; + + /** ERRSTS register */ + if(flag == 0x30F00070) + { + can->ERRSTS = RESET; + } + else + { + flagtmp = flag & 0x000FFFFF; + if((flag & 0x02000000) != RESET) + { + can->RXF0 = flagtmp; + } + else if((flag & 0x04000000) != RESET) + { + can->RXF1 = flagtmp; + } + else if((flag & 0x08000000) != RESET) + { + can->TXSTS = flagtmp; + } + else + { + can->MSTS = flagtmp; + } + } +} + +/*! + * @brief Read whether the specified can interrupt has occurred or not. + * + * @param can: Select the CAN peripheral. + * + * @param flag: specifies the CAN interrupt sources + * This parameter can be one of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval status : SET or RESET + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag) +{ + uint8_t status = 0; + + if((can->INTEN & flag) != RESET) + { + switch (flag) + { + case CAN_INT_TXME: + status = can->TXSTS_B.REQCFLG0 | can->TXSTS_B.REQCFLG1 | can->TXSTS_B.REQCFLG2; + break; + case CAN_INT_F0MP: + status = can->RXF0_B.FMNUM0; + break; + case CAN_INT_F0FULL: + status = can->RXF0_B.FFULLFLG0; + break; + case CAN_INT_F0OVR: + status = can->RXF0_B.FOVRFLG0; + break; + case CAN_INT_F1MP: + status = can->RXF1_B.FMNUM1; + break; + case CAN_INT_F1FULL: + status = can->RXF1_B.FFULLFLG1; + break; + case CAN_INT_F1OVR: + status = can->RXF1_B.FOVRFLG1; + break; + case CAN_INT_WUP: + status = can->MSTS_B.WUPIFLG; + break; + case CAN_INT_SLEEP: + status = can->MSTS_B.SLEEPIFLG; + break; + case CAN_INT_ERRW: + status = can->ERRSTS_B.ERRWFLG; + break; + case CAN_INT_ERRP: + status = can->ERRSTS_B.ERRPFLG; + break; + case CAN_INT_BOF: + status = can->ERRSTS_B.BOFLG; + break; + case CAN_INT_LEC: + status = can->ERRSTS_B.LERRC; + break; + case CAN_INT_ERR: + status = can->MSTS_B.ERRIFLG; + break; + default: + status = RESET; + break; + } + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the can's interrupt flag. + * + * @param can: Select the CAN peripheral. + * + * @param flag: Interrupt pending bit to clear + * This parameter can be one of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag) +{ + switch (flag) + { + case CAN_INT_TXME: + can->TXSTS_B.REQCFLG0 = BIT_SET; + can->TXSTS_B.REQCFLG1 = BIT_SET; + can->TXSTS_B.REQCFLG2 = BIT_SET; + break; + case CAN_INT_F0FULL: + can->RXF0_B.FFULLFLG0 = BIT_SET; + break; + case CAN_INT_F0OVR: + can->RXF0_B.FOVRFLG0 = BIT_SET; + break; + case CAN_INT_F1FULL: + can->RXF1_B.FFULLFLG1 = BIT_SET; + break; + case CAN_INT_F1OVR: + can->RXF1_B.FOVRFLG1 = BIT_SET; + break; + case CAN_INT_WUP: + can->MSTS_B.WUPIFLG = BIT_SET; + break; + case CAN_INT_SLEEP: + can->MSTS_B.SLEEPIFLG = BIT_SET; + break; + case CAN_INT_ERRW: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_ERRP: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_BOF: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_LEC: + can->ERRSTS_B.LERRC = BIT_RESET; + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_ERR: + can->ERRSTS_B.LERRC = BIT_RESET; + can->MSTS_B.ERRIFLG = BIT_SET; + break; + default: + break; + } +} + +/**@} end of group CAN_Fuctions*/ +/**@} end of group CAN_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c new file mode 100644 index 0000000000..fd0d7b28a6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c @@ -0,0 +1,112 @@ +/*! + * @file apm32f10x_crc.c + * + * @brief This file provides all the CRC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_crc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset CRC data register. + * + * @param None + * + * @retval None + * + * @note + */ +void CRC_ResetDATA(void) +{ + CRC->CTRL_B.RST = BIT_SET; +} + +/*! + * @brief Calculate CRC of a 32bit data word. + * + * @param data: a data word to compute its CRC. + * This parameter can be a 32bit value: + * + * @retval A 32-bit CRC value + */ +uint32_t CRC_CalculateCRC(uint32_t data) +{ + CRC->DATA = data; + + return (CRC->DATA); +} + +/*! + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param buf: Pointer to the buffer containing the data to be computed. + * + * @param bufLen: The length of buffer which is computed. + * + * @retval A 32-bit CRC value + */ +uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen) +{ + while(bufLen--) + { + CRC->DATA = *buf++; + } + + return (CRC->DATA); +} + +/*! + * @brief Returns the current CRC value. + * + * @param None + * + * @retval A 32-bit CRC value + */ +uint32_t CRC_ReadCRC(void) +{ + return (CRC->DATA); +} + +/*! + * @brief Saves a 8bit data in the Independent Data register(INDATA). + * + * @param inData: a 8-bit value to be stored in the ID register + * + * @retval None + */ +void CRC_WriteIDRegister(uint8_t inData) +{ + CRC->INDATA = inData; +} + +/*! + * @brief Reads a 8-bit data saved in the Independent Data register(INDATA). + * + * @param None + * + * @retval a 8-bit value from the INDATA register + */ +uint8_t CRC_ReadIDRegister(void) +{ + return (CRC->INDATA); +} + +/**@} end of group CRC_Fuctions*/ +/**@} end of group CRC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c new file mode 100644 index 0000000000..e66cd77463 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c @@ -0,0 +1,393 @@ +/*! + * @file apm32f10x_dac.c + * + * @brief This file provides all the DAC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_dac.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset dac peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void DAC_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_DAC); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_DAC); +} + +/*! + * @brief Config the DAC peripheral according to the specified parameters in the configStruct + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @param configStruct: pointer to a DAC_ConfigStruct_T structure + * + * @retval None + */ +void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + tmp1 = DAC->CTRL; + + tmp1 &= ~(((uint32_t)0x00000FFE) << channel); + + tmp2 = (configStruct->trigger | configStruct->waveGeneration | configStruct->maskAmplitudeSelect | configStruct->outputBuffer); + tmp1 |= tmp2 << channel; + + DAC->CTRL = tmp1; +} + +/*! + * @brief Fills each DAC_ConfigStruct_T member with its default value + * + * @param configStruct: pointer to a DAC_ConfigStruct_T structure which will be initialized + * + * @retval None + */ +void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct) +{ + /* Initialize the DAC_Trigger member */ + configStruct->trigger = DAC_TRIGGER_NONE; + /* Initialize the DAC_WaveGeneration member */ + configStruct->waveGeneration = DAC_WAVE_GENERATION_NONE; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + configStruct->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1; + /* Initialize the DAC_OutputBuffer member */ + configStruct->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE; +} + +/*! + * @brief Enables the specified DAC peripheral + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_Enable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.ENCH1 = BIT_SET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.ENCH2 = BIT_SET; + } +} + +/*! + * @brief Disables the specified DAC peripheral + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_Disable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.ENCH1 = BIT_RESET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.ENCH2 = BIT_RESET; + } +} + + +/*! + * @brief Enables the specified DAC channel DMA request + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_DMA_Enable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAENCH1 = BIT_SET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.DMAENCH2 = BIT_SET; + } +} + +/*! + * @brief Disables the specified DAC channel DMA request + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_DMA_Disable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAENCH1 = BIT_RESET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.DMAENCH2 = BIT_RESET; + } +} + +/*! + * @brief Enables the selected DAC channel software trigger + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->SWTRG_B.SWTRG1 = BIT_SET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->SWTRG_B.SWTRG2 = BIT_SET; + } +} + +/*! + * @brief Disable the selected DAC channel software trigger + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->SWTRG_B.SWTRG1 = BIT_RESET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->SWTRG_B.SWTRG2 = BIT_RESET; + } +} +/*! + * @brief Enables simultaneously the two DAC channels software + * + * @param None + * + * @retval None + */ +void DAC_EnableDualSoftwareTrigger(void) +{ + DAC->SWTRG_B.SWTRG1 = BIT_SET; + DAC->SWTRG_B.SWTRG2 = BIT_SET; +} + +/*! + * @brief Disables simultaneously the two DAC channels software + * + * @param None + * + * @retval None + */ +void DAC_DisableDualSoftwareTrigger(void) +{ + DAC->SWTRG_B.SWTRG1 = BIT_RESET; + DAC->SWTRG_B.SWTRG2 = BIT_RESET; +} + +/*! + * @brief Enables the selected DAC channel wave generation + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @param wave: Select the wave + * This parameter can be one of the following values: + * @arg DAC_WAVE_GENERATION_NONE : no wave generation + * @arg DAC_WAVE_GENERATION_NOISE : Noise wave generation + * @arg DAC_WAVE_GENERATION_TRIANGLE : Triangle wave generation + * + * @retval None + */ +void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave) +{ + DAC->CTRL &= 0xFF3FFF3F; + DAC->CTRL |= wave << channel; +} + +/*! + * @brief Disables the selected DAC channel wave generation + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @param wave: Select the wave + * This parameter can be one of the following values: + * @arg DAC_WAVE_GENERATION_NONE : no wave generation + * @arg DAC_WAVE_GENERATION_NOISE : Noise wave generation + * @arg DAC_WAVE_GENERATION_TRIANGLE : Triangle wave generation + * + * @retval None + */ +void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave) +{ + DAC->CTRL &= ~(wave << channel); +} + +/*! + * @brief Set the specified data holding register value for DAC channel 1 + * + * @param align: DAC channel 1 data alignment + * This parameter can be one of the following values: + * @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data + * @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data + * @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data + * + * @param data: The data to be loaded in the selected data register. + * + * @retval None + */ +void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += 0x00000008 + align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = data; +} + +/*! + * @brief Set the specified data holding register value for DAC channel 2 + * + * @param align: DAC channel 2 data alignment + * This parameter can be one of the following values: + * @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data + * @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data + * @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data + * + * @param data: The data to be loaded in the selected data register. + * + * @retval None + */ +void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += 0x00000014 + align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = data; +} + +/*! + * @brief Set the specified data holding register value for dual DAC channel + * + * @param align: Dual DAC channel data alignment + * This parameter can be one of the following values: + * @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data + * @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data + * @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data + * + * @param data2: Data for channel2 to be loaded in the selected data register. + * + * @param data1: Data for channel1 to be loaded in the selected data register + * + * @retval None + */ +void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1) +{ + uint32_t data = 0, tmp = 0; + + /* Calculate and set dual DAC data holding register value */ + if (align == DAC_ALIGN_8BIT_R) + { + data = ((uint32_t)data2 << 8) | data1; + } + else + { + data = ((uint32_t)data2 << 16) | data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += 0x00000020 + align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/*! + * @brief Reads the specified DAC channel data output value. + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval The data output value of the specified DAC channel. + */ +uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t) DAC_BASE ; + tmp += 0x0000002C + ((uint32_t)channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/**@} end of group DAC_Fuctions*/ +/**@} end of group DAC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c new file mode 100644 index 0000000000..985f9f215d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c @@ -0,0 +1,132 @@ +/*! + * @file apm32f10x_dbgmcu.c + * + * @brief This file provides all the DEBUG firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_dbgmcu.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DBGMCU_Driver DBGMCU Driver + @{ +*/ + +/** @addtogroup DBGMCU_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Returns the device identifier. + * + * @param None + * + * @retval Device identifier + */ +uint32_t DBGMCU_ReadDEVID(void) +{ + return(DBGMCU->IDCODE_B.EQR); +} + +/*! + * @brief Returns the device revision identifier. + * + * @param None + * + * @retval Device revision identifier + */ +uint32_t DBGMCU_ReadREVID(void) +{ + return(DBGMCU->IDCODE_B.WVR); +} + +/*! + * @brief Enable the specified peripheral and low power mode behavior + * when the MCU under Debug mode + * + * @param periph: Specifies the peripheral and low power mode + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP : Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP : Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY : Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDT_STOP : Debug IWDT stopped when Core is halted + * @arg DBGMCU_WWDT_STOP : Debug WWDT stopped when Core is halted + * @arg DBGMCU_TMR1_STOP : TMR1 counter stopped when Core is halted + * @arg DBGMCU_TMR2_STOP : TMR2 counter stopped when Core is halted + * @arg DBGMCU_TMR3_STOP : TMR3 counter stopped when Core is halted + * @arg DBGMCU_TMR4_STOP : TMR4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP : Debug CAN1 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TMR5_STOP : TMR5 counter stopped when Core is halted + * @arg DBGMCU_TMR6_STOP : TMR6 counter stopped when Core is halted + * @arg DBGMCU_TMR7_STOP : TMR7 counter stopped when Core is halted + * @arg DBGMCU_TMR8_STOP : TMR8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP : Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TMR15_STOP : TMR15 counter stopped when Core is halted + * @arg DBGMCU_TMR16_STOP : TMR16 counter stopped when Core is halted + * @arg DBGMCU_TMR17_STOP : TMR17 counter stopped when Core is halted + * @arg DBGMCU_TMR9_STOP : TMR9 counter stopped when Core is halted + * @arg DBGMCU_TMR10_STOP : TMR10 counter stopped when Core is halted + * @arg DBGMCU_TMR11_STOP : TMR11 counter stopped when Core is halted + * @arg DBGMCU_TMR12_STOP : TMR12 counter stopped when Core is halted + * @arg DBGMCU_TMR13_STOP : TMR13 counter stopped when Core is halted + * @arg DBGMCU_TMR14_STOP : TMR14 counter stopped when Core is halted + * + * @retval None + */ +void DBGMCU_Enable(uint32_t periph) +{ + DBGMCU->CFG |= periph; +} + +/*! + * @brief Enable the specified peripheral and low power mode behavior + * when the MCU under Debug mode + * + * @param periph: Specifies the peripheral and low power mode + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP : Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP : Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY : Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDT_STOP : Debug IWDT stopped when Core is halted + * @arg DBGMCU_WWDT_STOP : Debug WWDT stopped when Core is halted + * @arg DBGMCU_TMR1_STOP : TMR1 counter stopped when Core is halted + * @arg DBGMCU_TMR2_STOP : TMR2 counter stopped when Core is halted + * @arg DBGMCU_TMR3_STOP : TMR3 counter stopped when Core is halted + * @arg DBGMCU_TMR4_STOP : TMR4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP : Debug CAN1 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TMR5_STOP : TMR5 counter stopped when Core is halted + * @arg DBGMCU_TMR6_STOP : TMR6 counter stopped when Core is halted + * @arg DBGMCU_TMR7_STOP : TMR7 counter stopped when Core is halted + * @arg DBGMCU_TMR8_STOP : TMR8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP : Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TMR15_STOP : TMR15 counter stopped when Core is halted + * @arg DBGMCU_TMR16_STOP : TMR16 counter stopped when Core is halted + * @arg DBGMCU_TMR17_STOP : TMR17 counter stopped when Core is halted + * @arg DBGMCU_TMR9_STOP : TMR9 counter stopped when Core is halted + * @arg DBGMCU_TMR10_STOP : TMR10 counter stopped when Core is halted + * @arg DBGMCU_TMR11_STOP : TMR11 counter stopped when Core is halted + * @arg DBGMCU_TMR12_STOP : TMR12 counter stopped when Core is halted + * @arg DBGMCU_TMR13_STOP : TMR13 counter stopped when Core is halted + * @arg DBGMCU_TMR14_STOP : TMR14 counter stopped when Core is halted + * + * @retval None + */ +void DBGMCU_Disable(uint32_t periph) +{ + DBGMCU->CFG &= ~periph; +} + +/**@} end of group DBGMCU_Fuctions*/ +/**@} end of group DBGMCU_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c new file mode 100644 index 0000000000..0df9c93fa7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c @@ -0,0 +1,546 @@ +/*! + * @file apm32f10x_dma.c + * + * @brief This file provides all the DMA firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_dma.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMA_Driver DMA Driver + @{ +*/ + +/** @addtogroup DMA_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset specified DMA Channel registers to their default reset + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5). + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Reset(DMA_Channel_T *channel) +{ + channel->CHCFG_B.CHEN = BIT_RESET; + channel->CHCFG = 0; + channel->CHNDATA = 0; + channel->CHMADDR = 0; + channel->CHPADDR = 0; + + if(channel == DMA1_Channel1) + { + DMA1->INTFCLR |= 0xFFFFFFF0; + } + else if(channel == DMA1_Channel2) + { + DMA1->INTFCLR |= 0xFFFFFF0F; + } + else if(channel == DMA1_Channel3) + { + DMA1->INTFCLR |= 0xFFFFF0FF; + } + else if(channel == DMA1_Channel4) + { + DMA1->INTFCLR |= 0xFFFF0FFF; + } + else if(channel == DMA1_Channel5) + { + DMA1->INTFCLR |= 0xFFF0FFFF; + } + else if(channel == DMA1_Channel6) + { + DMA1->INTFCLR |= 0xFF0FFFFF; + } + else if(channel == DMA1_Channel7) + { + DMA1->INTFCLR |= 0xF0FFFFFF; + } + else if(channel == DMA2_Channel1) + { + DMA2->INTFCLR |= 0xFFFFFFF0; + } + else if(channel == DMA2_Channel2) + { + DMA2->INTFCLR |= 0xFFFFFF0F; + } + else if(channel == DMA2_Channel3) + { + DMA2->INTFCLR |= 0xFFFFF0FF; + } + else if(channel == DMA2_Channel4) + { + DMA2->INTFCLR |= 0xFFFF0FFF; + } + else if(channel == DMA2_Channel5) + { + DMA2->INTFCLR |= 0xFFF0FFFF; + } +} + +/*! + * @brief Configs specified DMA Channel through a structure. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param dmaConfig: Point to a DMA_Config_T structure + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig) +{ + channel->CHCFG_B.DIRCFG = dmaConfig->dir; + channel->CHCFG_B.CIRMODE = dmaConfig->loopMode; + channel->CHCFG_B.PERIMODE = dmaConfig->peripheralInc; + channel->CHCFG_B.MIMODE = dmaConfig->memoryInc; + channel->CHCFG_B.PERSIZE = dmaConfig->peripheralDataSize; + channel->CHCFG_B.MEMSIZE = dmaConfig->memoryDataSize; + channel->CHCFG_B.CHPL = dmaConfig->priority; + channel->CHCFG_B.M2MMODE = dmaConfig->M2M; + + channel->CHNDATA = dmaConfig->bufferSize; + channel->CHPADDR = dmaConfig->peripheralBaseAddr; + channel->CHMADDR = dmaConfig->memoryBaseAddr; +} + +/*! + * @brief Populate the structure with default values. + * + * @param dmaConfig: Point to a DMA_Config_T structure. + * + * @retval None + */ +void DMA_ConfigStructInit( DMA_Config_T* dmaConfig) +{ + dmaConfig->peripheralBaseAddr = 0; + dmaConfig->memoryBaseAddr = 0; + dmaConfig->dir = DMA_DIR_PERIPHERAL_SRC; + dmaConfig->bufferSize = 0; + dmaConfig->peripheralInc = DMA_PERIPHERAL_INC_DISABLE; + dmaConfig->memoryInc = DMA_MEMORY_INC_DISABLE; + dmaConfig->peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_BYTE; + dmaConfig->memoryDataSize = DMA_MEMORY_DATA_SIZE_BYTE; + dmaConfig->loopMode = DMA_MODE_NORMAL; + dmaConfig->priority = DMA_PRIORITY_LOW; + dmaConfig->M2M = DMA_M2MEN_DISABLE; +} + +/*! + * @brief Enable the specified DMA Channel + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Enable(DMA_Channel_T *channel) +{ + channel->CHCFG_B.CHEN = ENABLE; +} + +/*! + * @brief Disable the specified DMA Channel + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Disable(DMA_Channel_T *channel) +{ + channel->CHCFG_B.CHEN = DISABLE; +} + +/*! + * @brief Configs the number of data units in the channel. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param dataNumber:The number of data units in the current DMA Channel transfer. + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber) +{ + channel->CHNDATA = dataNumber; +} + +/*! + * @brief Read the number of data units in the channel + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @retval The number of CHNDATA value + * + * @note DMA2 Channel only for APM32 High density devices. + */ +uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel) +{ + return channel->CHNDATA; +} + +/*! + * @brief Enables the specified DMA Channel interrupts. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param interrupt: DMA interrupts sources to selsct + * This parameter can be any combination of the following values: + * @arg DMA_INT_TC : All Transfer Complete Interrupt + * @arg DMA_INT_HT : Half Transfer Complete Interrupt + * @arg DMA_INT_TERR : Transfer Error Occur Interrupt + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) +{ + channel->CHCFG |= interrupt; +} + +/*! + * @brief Disable the specified DMA Channel interrupts. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param interrupt: DMA interrupts sources to selsct + * This parameter can be any combination of the following values: + * @arg DMA_INT_TC : All Transfer Complete Interrupt + * @arg DMA_INT_HT : Half Transfer Complete Interrupt + * @arg DMA_INT_TERR : Transfer Error Occur Interrupt + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) +{ + channel->CHCFG &= ~interrupt; +} + +/*! + * @brief Read whether the specifie DMA Channel flag is set or not. + * + * @param flag: the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag. + * @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag. + * @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag. + * + * @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag. + * @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag. + * @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag. + * @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag. + * @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag. + * @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag. + * @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag. + * @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag. + * @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag. + * @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag. + * + * @retval Flag State + * + * @note DMA2 Channel only for APM32 High density devices. + */ +uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag) +{ + if((flag & 0x10000000) != RESET ) + { + if((DMA2->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } + else + { + if((DMA1->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } +} + +/*! + * @brief Clears the specifie DMA Channel's flags. + * + * @param flag:the flag to Clear. + * This parameter can be any combination of the following values: + * @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag. + * @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag. + * @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag. + + * @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag. + * @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag. + * @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag. + * @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag. + * @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag. + * @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag. + * @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag. + * @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag. + * @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag. + * @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag. + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_ClearStatusFlag(uint32_t flag) +{ + if((flag & 0x10000000) != RESET) + { + DMA2->INTFCLR = flag; + } else + { + DMA1->INTFCLR = flag; + } +} + +/*! + * @brief Read whether the specified DMA Channel interrupts is set or not. + * + * @param interrupt: interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt. + * @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt. + * @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt. + * @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt. + * @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt. + * @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt. + * @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt. + * @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt. + + * @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt. + * @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt. + * @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt. + * @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt. + * @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt. + * @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt. + * + * @retval interrupt State + * + * @note DMA2 Channel only for APM32 High density devices. + */ +uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag) +{ + if((flag & 0x10000000) != RESET ) + { + if((DMA2->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } else + { + if((DMA1->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } +} +/*! + * @brief Clears the specified DMA Channel's interrupts. + * + * @param flag: the interrupt flag to Clear. + * This parameter can be any combination of the following values: + * @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt. + * @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt. + * @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt. + * @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt. + * @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt. + * @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt. + * @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt. + * @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt. + + * @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt. + * @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt. + * @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt. + * @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt. + * @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt. + * @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt. + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_ClearIntFlag(uint32_t flag) +{ + if((flag & 0x10000000) != RESET) + { + DMA2->INTFCLR = flag; + } else + { + DMA1->INTFCLR = flag; + } +} + +/**@} end of group DMA_Fuctions*/ +/**@} end of group DMA_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c new file mode 100644 index 0000000000..619550794f --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c @@ -0,0 +1,409 @@ +/*! + * @file apm32f10x_dmc.c + * + * @brief This file contains all the functions for the DMC controler peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#include "apm32f10x_dmc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMC_Driver DMC Driver + @{ +*/ + +/** @addtogroup DMC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief DMC controler configuration + * + * @param dmcConfig: pointer to a DMC_Config_T structure + * + * @retval None + */ +void DMC_Config(DMC_Config_T * dmcConfig) +{ + DMC->SW_B.MCSW = 1; + while(!DMC->CTRL1_B.INIT); + + DMC->CFG_B.BAWCFG = dmcConfig->bankWidth; + DMC->CFG_B.RAWCFG = dmcConfig->rowWidth; + DMC->CFG_B.CAWCFG = dmcConfig->colWidth; + + DMC->MASK_B.MSIZESEL = dmcConfig->memorySize; + DMC->CTRL2_B.CPHACFG = dmcConfig->clkPhase; + + DMC_ConfigTiming(&dmcConfig->timing); + + DMC->CTRL1_B.MODESET = 1; + while(!DMC->CTRL1_B.MODESET); + + DMC->CTRL2_B.RDDEN = 1; + DMC->CTRL2_B.RDDCFG = 7; +} + +/*! + * @brief Fills each dmcConfig member with its default value + * + * @param dmcConfig: pointer to a DMC_Config_T structure + * + * @retval None + */ +void DMC_ConfigStructInit(DMC_Config_T * dmcConfig) +{ + dmcConfig->bankWidth = DMC_BANK_WIDTH_2; + dmcConfig->clkPhase = DMC_CLK_PHASE_REVERSE; + dmcConfig->colWidth = DMC_COL_WIDTH_10; + dmcConfig->rowWidth = DMC_ROW_WIDTH_13; + dmcConfig->memorySize = DMC_MEMORY_SIZE_8MB; + + DMC_ConfigTimingStructInit(&dmcConfig->timing); +} + +/*! + * @brief Timing configuration + * + * @param timingConfig: pointer to a DMC_TimingConfig_T structure + * + * @retval None + */ +void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig) +{ + DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS; + DMC->TIM0_B.DTIMSEL = timingConfig->tRCD; + DMC->TIM0_B.PCPSEL = timingConfig->tRP; + DMC->TIM0_B.WRTIMSEL = timingConfig->tWR; + DMC->TIM0_B.ARPSEL = timingConfig->tARP; + DMC->TIM0_B.ATACP = timingConfig->tCMD; + + DMC->TIM0_B.CASLSEL0 = timingConfig->latencyCAS & 0x03; + DMC->TIM0_B.ECASLSEL1 = (timingConfig->latencyCAS >> 2) & 0x01; + + DMC->TIM0_B.XSR0 = timingConfig->tXSR & 0X0F; + DMC->TIM0_B.EXSR1 = (timingConfig->tXSR >> 4) & 0X1F; + + DMC->REF_B.RCYCCFG = timingConfig->tRFP; +} + +/*! + * @brief Fills each config member with its default value + * + * @param timingConfig: pointer to a DMC_TimingConfig_T structure + * + * @retval None + */ +void DMC_ConfigTimingStructInit(DMC_TimingConfig_T * timingConfig) +{ + timingConfig->latencyCAS = DMC_CAS_LATENCY_3; + timingConfig->tARP = DMC_AUTO_REFRESH_10; + timingConfig->tRAS = DMC_RAS_MINIMUM_5; + timingConfig->tCMD = DMC_ATA_CMD_7; + timingConfig->tRCD = DMC_DELAY_TIME_2; + timingConfig->tRP = DMC_PRECHARGE_2; + timingConfig->tWR = DMC_NEXT_PRECHARGE_2; + timingConfig->tXSR = 6; + timingConfig->tRFP = 0xC3; +} + +/*! + * @brief Set number of bank bits + * + * @param bankWidth: Specifies the bank bits number + * This parameter can be one of the following values: + * @arg DMC_BANK_WIDTH_1 + * @arg DMC_BANK_WIDTH_2 + * @retval None + */ +void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth) +{ + DMC->CFG_B.BAWCFG = bankWidth; +} + +/*! + * @brief Set address bus width + * + * @param rowWidth: Specifies the row address bits number + * This parameter can be one of the following values: + * @arg DMC_ROW_WIDTH_11 + * @arg DMC_ROW_WIDTH_12 + * @arg DMC_ROW_WIDTH_13 + * @arg DMC_ROW_WIDTH_14 + * @arg DMC_ROW_WIDTH_15 + * @arg DMC_ROW_WIDTH_16 + * @param colWidth: Specifies the column address bits number + * This parameter can be one of the following values: + * @arg DMC_COL_WIDTH_8 + * @arg DMC_COL_WIDTH_9 + * @arg DMC_COL_WIDTH_10 + * @arg DMC_COL_WIDTH_11 + * @arg DMC_COL_WIDTH_12 + * @arg DMC_COL_WIDTH_13 + * @arg DMC_COL_WIDTH_14 + * @arg DMC_COL_WIDTH_15 + * @retval None + */ +void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth) +{ + DMC->CFG_B.RAWCFG = rowWidth; + DMC->CFG_B.CAWCFG = colWidth; +} + +/*! + * @brief Set stable time after power up + * + * @param stableTime: Numper of the clock, can be 0x0000 to 0xFFFF + * + * @retval None + */ +void DMC_ConfigStableTimePowerup(uint16_t stableTime) +{ + DMC->TIM1_B.STBTIM = stableTime; +} + +/*! + * @brief Number of auto-refreshes during initialization + * + * @param num: Number of auto-refreshes can 1 to 16 + * This parameter can be one of the following values: + * @arg DMC_AUTO_REFRESH_1 + * @arg DMC_AUTO_REFRESH_2 + * ...... + * @arg DMC_AUTO_REFRESH_15 + * @arg DMC_AUTO_REFRESH_16 + * + * @retval None + */ +void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num) +{ + DMC->TIM1_B.ARNUMCFG = num; +} + +/*! + * @brief Number of DMC internal banks to be open at any time; + * + * @param num: Number of banks can 1 to 16 + * This parameter can be one of the following values: + * @arg DMC_BANK_NUMBER_1 + * @arg DMC_BANK_NUMBER_2 + * ...... + * @arg DMC_BANK_NUMBER_15 + * @arg DMC_BANK_NUMBER_16 + * @retval None + */ +void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num) +{ + DMC->CTRL1_B.BANKNUMCFG = num; +} + +/*! + * @brief Read self-refresh status + * + * @param None + * + * @retval The status of self-refresh (SET or RESET) + */ +uint8_t DMC_ReadSelfRefreshStatus(void) +{ + uint8_t ret; + + ret = DMC->CTRL1_B.SRMFLG ? SET : RESET; + + return ret; +} + +/*! + * @brief Set update mode bit + * + * @param None + * + * @retval None + */ +void DMC_EnableUpdateMode(void) +{ + DMC->CTRL1_B.MODESET = 1; +} + +/*! + * @brief Enter power down mode + * + * @param None + * + * @retval None + */ +void DMC_EnterPowerdownMode(void) +{ + DMC->CTRL1_B.PDMEN = 1; +} + +/*! + * @brief Exit self-refresh mode + * + * @param None + * + * @retval None + */ +void DMC_EixtSlefRefreshMode(void) +{ + DMC->CTRL1_B.SRMEN = 0; +} + +/*! + * @brief Enter self-refresh mode + * + * @param None + * + * @retval None + */ +void DMC_EnterSlefRefreshMode(void) +{ + DMC->CTRL1_B.SRMEN = 1; +} + +/*! + * @brief Init DMC + * + * @param None + * + * @retval None + */ +void DMC_EnableInit(void) +{ + DMC->CTRL1_B.INIT = 1; +} + +/*! + * @brief Set refresh type before enter self-refresh + * + * @param refresh: Specifies the refresh type + * The parameter can be one of following values: + * @arg DMC_REFRESH_ROW_ONE: Refresh one row + * @arg DMC_REFRESH_ROW_ALL: Refresh all row + * + * @retval None + */ +void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh) +{ + DMC->CTRL1_B.FRBSREN = refresh; +} + +/*! + * @brief Set refresh type after exit self-refresh + * + * @param refresh: Specifies the refresh type + * The parameter can be one of following values: + * @arg DMC_REFRESH_ROW_ONE: Refresh one row + * @arg DMC_REFRESH_ROW_ALL: Refresh all row + * + * @retval None + */ +void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh) +{ + DMC->CTRL1_B.FRASREN = refresh; +} + +/*! + * @brief Config precharge type + * + * @param precharge: Specifies the precharge type + * The parameter can be one of following values: + * @arg DMC_PRECHARGE_IM: Immediate precharge + * @arg DMC_PRECHARGE_DELAY: Delayed precharge + * + * @retval None + */ +void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge) +{ + DMC->CTRL1_B.PCACFG = precharge; +} + +/*! + * @brief Config refresh period + * + * @param period: Specifies the refresh period, can be 0x0000 to 0xFFFF + * + * @retval None + */ +void DMC_ConfigRefreshPeriod(uint16_t period) +{ + DMC->REF_B.RCYCCFG = period; +} + +/*! + * @brief Config memory size + * + * @param memorySize: Specifies memory size + * The parameter can be one of following values: + * @arg DMC_MEMORY_SIZE_0: Memory size is no link + * @arg DMC_MEMORY_SIZE_64KB: Memory size is 64KB + * @arg DMC_MEMORY_SIZE_128KB: Memory size is 128KB + * @arg DMC_MEMORY_SIZE_256KB: Memory size is 256KB + * @arg DMC_MEMORY_SIZE_512KB: Memory size is 512KB + * @arg DMC_MEMORY_SIZE_1MB: Memory size is 1MB + * @arg DMC_MEMORY_SIZE_2MB: Memory size is 2MB + * @arg DMC_MEMORY_SIZE_4MB: Memory size is 4MB + * @arg DMC_MEMORY_SIZE_8MB: Memory size is 8MB + * @arg DMC_MEMORY_SIZE_16MB: Memory size is 16MB + * @arg DMC_MEMORY_SIZE_32MB: Memory size is 32MB + * @arg DMC_MEMORY_SIZE_64MB: Memory size is 64MB + * @arg DMC_MEMORY_SIZE_128MB: Memory size is 128MB + * @arg DMC_MEMORY_SIZE_256MB: Memory size is 256MB + * + * @retval None + */ +void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize) +{ + DMC->MASK_B.MSIZESEL = memorySize; +} + +/*! + * @brief Enable DMC controler + * + * @param None + * + * @retval None + */ +void DMC_Enable(void) +{ + DMC->SW_B.MCSW = 1; +} + +/*! + * @brief Disable DMC controler + * + * @param None + * + * @retval None + */ +void DMC_Disable(void) +{ + DMC->SW_B.MCSW = 0; +} + +/*! + * @brief Set DMC clock phase + * + * @param clkPhase: Specifies clock phase + * The parameter can be one of following values: + * @arg DMC_CLK_PHASE_NORMAL: Clock phase is normal + * @arg DMC_CLK_PHASE_REVERSE: Clock phase is reverse + * + * @retval None + * + */ +void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase) +{ + DMC->CTRL2_B.CPHACFG = clkPhase; +} + +/**@} end of group DMC_Fuctions*/ +/**@} end of group DMC_Driver */ +/**@} end of group Peripherals_Library*/ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c new file mode 100644 index 0000000000..cc0eafe579 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c @@ -0,0 +1,176 @@ +/*! + * @file apm32f10x_eint.c + * + * @brief This file provides all the EINT firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_eint.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EINT_Driver EINT Driver + @{ +*/ + +/** @addtogroup EINT_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the EINT peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void EINT_Reset(void) +{ + EINT->IMASK = 0x00000000; + EINT->EMASK = 0x00000000; + EINT->RTEN = 0x00000000; + EINT->FTEN = 0x00000000; + EINT->IPEND = 0x000FFFFF; +} + +/*! + * @brief Configure the EINT + * + * @param eintConfig: pointer to a EINT_Config_T structure. + * + * @retval None + */ +void EINT_Config(EINT_Config_T* eintConfig) +{ + uint32_t temp = 0; + temp = (uint32_t)EINT_BASE; + + if(eintConfig->lineCmd != DISABLE) + { + EINT->IMASK &= ~eintConfig->line; + EINT->EMASK &= ~eintConfig->line; + + temp += eintConfig->mode; + *(__IOM uint32_t *) temp |= eintConfig->line; + + EINT->RTEN &= ~eintConfig->line; + EINT->FTEN &= ~eintConfig->line; + + if (eintConfig->trigger == EINT_TRIGGER_RISING_FALLING) + { + EINT->RTEN |= eintConfig->line; + EINT->FTEN |= eintConfig->line; + } + else + { + temp = (uint32_t)EINT_BASE; + temp += eintConfig->trigger; + + *(__IOM uint32_t *) temp |= eintConfig->line; + } + } + else + { + temp += eintConfig->mode; + + *(__IOM uint32_t *) temp &= ~eintConfig->line; + } +} + +/*! + * @brief Select Software interrupt on EINT line + * + * @param line: specifies the EINT lines. + * This parameter can be any combination of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +void EINT_SelectSWInterrupt(uint32_t line) +{ + EINT->SWINTE |= line; +} + +/*! + * @brief Read the specified EINT_Line flag + * + * @param line: Select the EINT_Line. + * This parameter can be one of EINT_LINE_T(can be from 0 to 18) + * + * @retval status: The new state of flag (SET or RESET) + */ +uint8_t EINT_ReadStatusFlag(EINT_LINE_T line) +{ + uint8_t status = RESET; + + if((EINT->IPEND & line) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the EINT_Line pending bits + * + * @param line: Select the EINT_Line. + * This parameter can be any combination of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +void EINT_ClearStatusFlag(uint32_t line) +{ + EINT->IPEND = line; +} + +/*! + * @brief Read the specified EINT_Line Interrupt Flag. + * + * @param line: Select the EINT_Line. + * This parameter can be one of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +uint8_t EINT_ReadIntFlag(EINT_LINE_T line) +{ + uint8_t status = RESET; + uint32_t enablestatus = 0; + + enablestatus = EINT->IMASK & line; + + if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the EINT_Line pending bits + * + * @param line: Select the EINT_Line + * This parameter can be any combination of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +void EINT_ClearIntFlag(uint32_t line) +{ + EINT->IPEND = line; +} + +/**@} end of group EINT_Fuctions*/ +/**@} end of group EINT_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c new file mode 100644 index 0000000000..8d79d213d8 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c @@ -0,0 +1,735 @@ +/*! + * @file apm32f10x_emmc.c + * + * @brief This file provides all the EMMC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_emmc.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EMMC_Driver EMMC Driver + @{ +*/ + +/** @addtogroup EMMC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Rest the EMMMC NOR/SRAM Banks registers + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1 + * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2 + * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3 + * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank) +{ + /** EMMC_BANK1_NORSRAM_1 */ + if(bank == EMMC_BANK1_NORSRAM_1) + { + EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB; + } + /** EMMC_BANK1_NORSRAM_2, EMMC_BANK1_NORSRAM_3 or EMMC_BANK1_NORSRAM_4 */ + else + { + EMMC_Bank1->SNCTRL_T[bank] = 0x000030D2; + } + EMMC_Bank1->SNCTRL_T[bank + 1] = 0x0FFFFFFF; + EMMC_Bank1E->WRTTIM[bank] = 0x0FFFFFFF; +} + +/*! + * @brief Rest the EMMMC NAND Banks registers + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_ResetNAND(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + /** Set the EMMC_Bank2 registers to their reset values */ + EMMC_Bank2->CTRL2 = 0x00000018; + EMMC_Bank2->STSINT2 = 0x00000040; + EMMC_Bank2->CMSTIM2 = 0xFCFCFCFC; + EMMC_Bank2->AMSTIM2 = 0xFCFCFCFC; + } + /** EMMC_BANK3_NAND */ + else + { + /* Set the EMMC_Bank3 registers to their reset values */ + EMMC_Bank3->CTRL3 = 0x00000018; + EMMC_Bank3->STSINT3 = 0x00000040; + EMMC_Bank3->CMSTIM3 = 0xFCFCFCFC; + EMMC_Bank3->AMSTIM3 = 0xFCFCFCFC; + } +} + +/*! + * @brief Reset the EMMMC PCCARD Banks registers + * + * @param None + * + * @retval None + */ +void EMMC_ResetPCCard(void) +{ + /** Set the EMMC_Bank4 registers to their reset values */ + EMMC_Bank4->CTRL4 = 0x00000018; + EMMC_Bank4->STSINT4 = 0x00000040; + EMMC_Bank4->CMSTIM4 = 0xFCFCFCFC; + EMMC_Bank4->AMSTIM4 = 0xFCFCFCFC; + EMMC_Bank4->IOSTIM4 = 0xFCFCFCFC; +} + +/*! + * @brief Config the EMMC NOR/SRAM Banks according to the specified parameters in the emmcNORSRAMConfig. + * + * @param emmcNORSRAMConfig: Point to a EMMC_NORSRAMConfig_T structure + * + * @retval None + */ +void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) +{ + /* Bank1 NOR/SRAM control register configuration */ + EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] = + (uint32_t)emmcNORSRAMConfig->dataAddressMux | + emmcNORSRAMConfig->memoryType | + emmcNORSRAMConfig->memoryDataWidth | + emmcNORSRAMConfig->burstAcceesMode | + emmcNORSRAMConfig->asynchronousWait | + emmcNORSRAMConfig->waitSignalPolarity | + emmcNORSRAMConfig->wrapMode | + emmcNORSRAMConfig->waitSignalActive | + emmcNORSRAMConfig->writeOperation | + emmcNORSRAMConfig->waiteSignal | + emmcNORSRAMConfig->extendedMode | + emmcNORSRAMConfig->writeBurst; + + if(emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR) + { + EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040; + } + + /* Bank1 NOR/SRAM timing register configuration */ + EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank + 1] = + (uint32_t)emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime | + (emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) | + (emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime << 8) | + (emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime << 16) | + (emmcNORSRAMConfig->readWriteTimingStruct->clockDivision << 20) | + (emmcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) | + emmcNORSRAMConfig->readWriteTimingStruct->accessMode; + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE) + { + EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] = + (uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime | + (emmcNORSRAMConfig->writeTimingStruct->addressHodeTime << 4) | + (emmcNORSRAMConfig->writeTimingStruct->dataSetupTime << 8) | + (emmcNORSRAMConfig->writeTimingStruct->clockDivision << 20) | + (emmcNORSRAMConfig->writeTimingStruct->dataLatency << 24) | + emmcNORSRAMConfig->writeTimingStruct->accessMode; + } + else + { + EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] = 0x0FFFFFFF; + } +} + +/*! + * @brief Config the EMMC NAND Banks according to the specified parameters in the emmcNANDConfig. + * + * @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Set the tmppcr value according to EMMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)emmcNANDConfig->waitFeature | 0x00000008 | + emmcNANDConfig->memoryDataWidth | + emmcNANDConfig->ECC | + emmcNANDConfig->ECCPageSize | + (emmcNANDConfig->TCLRSetupTime << 9) | + (emmcNANDConfig->TARSetupTime << 13); + + /* Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)emmcNANDConfig->commonSpaceTimingStruct->setupTime | + (emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) | + (emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) | + (emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24); + + /* Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)emmcNANDConfig->attributeSpaceTimingStruct->setupTime | + (emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | + (emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | + (emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); + + if(emmcNANDConfig->bank == EMMC_BANK2_NAND) + { + /* EMMC_BANK2_NAND registers configuration */ + EMMC_Bank2->CTRL2 = tmppcr; + EMMC_Bank2->CMSTIM2 = tmppmem; + EMMC_Bank2->AMSTIM2 = tmppatt; + } + else + { + /* EMMC_BANK3_NAND registers configuration */ + EMMC_Bank3->CTRL3 = tmppcr; + EMMC_Bank3->CMSTIM3 = tmppmem; + EMMC_Bank3->AMSTIM3 = tmppatt; + } + +} + +/*! + * @brief Config the EMMC PCCARD according to the specified parameters in the emmcPCCardConfig. + * + * @param emmcPCCardConfig: Point to a EMMC_PCCARDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig) +{ + /* Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */ + EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT | + (emmcPCCardConfig->TCLRSetupTime << 9) | + (emmcPCCardConfig->TARSetupTime << 13); + + /* Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */ + EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime | + (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24); + + /* Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */ + EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime | + (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); + + /* Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */ + EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime | + (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24); +} + +/*! + * @brief Fills each emmcNORSRAMConfig member with its default value. + * + * @param emmcNORSRAMConfig : Point to a EMMC_NORSRAMConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) +{ + /* Reset NOR/SRAM Init structure parameters values */ + emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1; + emmcNORSRAMConfig->dataAddressMux = EMMC_DATA_ADDRESS_MUX_ENABLE; + emmcNORSRAMConfig->memoryType = EMMC_MEMORY_TYPE_SRAM; + emmcNORSRAMConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT; + emmcNORSRAMConfig->burstAcceesMode = EMMC_BURST_ACCESS_MODE_DISABLE; + emmcNORSRAMConfig->asynchronousWait = EMMC_ASYNCHRONOUS_WAIT_DISABLE; + emmcNORSRAMConfig->waitSignalPolarity = EMMC_WAIT_SIGNAL_POLARITY_LOW; + emmcNORSRAMConfig->wrapMode = EMMC_WRAP_MODE_DISABLE; + emmcNORSRAMConfig->waitSignalActive = EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT; + emmcNORSRAMConfig->writeOperation = EMMC_WRITE_OPERATION_ENABLE; + emmcNORSRAMConfig->waiteSignal = EMMC_WAITE_SIGNAL_ENABLE; + emmcNORSRAMConfig->extendedMode = EMMC_EXTENDEN_MODE_DISABLE; + emmcNORSRAMConfig->writeBurst = EMMC_WRITE_BURST_DISABLE; + emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF; + emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->accessMode = EMMC_ACCESS_MODE_A; + emmcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF; + emmcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF; + emmcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF; + emmcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF; + emmcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF; + emmcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF; + emmcNORSRAMConfig->writeTimingStruct->accessMode = EMMC_ACCESS_MODE_A; + +} + +/*! + * @brief Fills each emmcNANDConfig member with its default value. + * + * @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig) +{ + /* Reset NAND Init structure parameters values */ + emmcNANDConfig->bank = EMMC_BANK2_NAND; + emmcNANDConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE; + emmcNANDConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT; + emmcNANDConfig->ECC = EMMC_ECC_DISABLE; + emmcNANDConfig->ECCPageSize = EMMC_ECC_PAGE_SIZE_BYTE_256; + emmcNANDConfig->TCLRSetupTime = 0x0; + emmcNANDConfig->TARSetupTime = 0x0; + emmcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC; + emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC; + emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC; + emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC; +} + +/*! + * @brief Fills each emmcPCCardConfig member with its default value. + * + * @param emmcPCCardConfig : Point to a EMMC_PCCARDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig) +{ + /* Reset PCCARD Init structure parameters values */ + emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE; + emmcPCCardConfig->TCLRSetupTime = 0x0; + emmcPCCardConfig->TARSetupTime = 0x0; + emmcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC; + emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC; + emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC; + emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC; +} + +/*! + * @brief Enables the specified NOR/SRAM Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1 + * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2 + * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3 + * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank) +{ + EMMC_Bank1->SNCTRL_T[bank] |= 0x00000001; +} + +/*! + * @brief Disbles the specified NOR/SRAM Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1 + * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2 + * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3 + * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank) +{ + EMMC_Bank1->SNCTRL_T[bank] &= 0x000FFFFE; +} + +/*! + * @brief Enables the specified NAND Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_EnableNAND(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET; + } + else + { + EMMC_Bank3->CTRL3_B.MBKEN = BIT_SET; + } +} + +/*! + * @brief Disbles the specified NAND Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_DisableNAND(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET; + } + else + { + EMMC_Bank3->CTRL3_B.MBKEN = BIT_RESET; + } +} + +/*! + * @brief Enables the specified PC Card Memory Bank. + * + * @param None + * + * @retval None + */ +void EMMC_EnablePCCARD(void) +{ + EMMC_Bank4->CTRL4_B.MBKEN = BIT_SET; +} + +/*! + * @brief Disables the specified PC Card Memory Bank. + * + * @param None + * + * @retval None + */ +void EMMC_DisablePCCARD(void) +{ + EMMC_Bank4->CTRL4_B.MBKEN = BIT_RESET; +} + +/*! + * @brief Enbles the EMMC NAND ECC feature. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2 |= 0x00000040; + } + else + { + EMMC_Bank3->CTRL3 |= 0x00000040; + } +} + +/*! + * @brief Disbles or disables the EMMC NAND ECC feature. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + * + * @note + */ +void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2 &= 0x000FFFBF; + } + else + { + EMMC_Bank3->CTRL3 &= 0x000FFFBF; + } +} + +/*! + * @brief Read the error correction code register value. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval The value of Error Correction Code (ECC). + */ +uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank) +{ + uint32_t eccval = 0x00000000; + + if(bank == EMMC_BANK2_NAND) + { + eccval = EMMC_Bank2->ECCRS2; + } + else + { + eccval = EMMC_Bank3->ECCRS3; + } + return eccval; +} + +/*! + * @brief Enables the specified EMMC interrupts. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 |= interrupt; + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 |= interrupt; + } + else + { + EMMC_Bank4->STSINT4 |= interrupt; + } +} + +/*! + * @brief Enables the specified EMMC interrupts. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 &= ~interrupt; + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 &= ~interrupt; + } + else + { + EMMC_Bank4->STSINT4 &= ~interrupt; + } +} + +/*! + * @brief Read the status of specified EMMC flag. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param flag: Select the EMMC interrupt sources. + * This parameter can be one of the following values: + * @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag. + * @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag. + * @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag. + * @arg EMMC_FLAG_FIFO_EMPTY : FIFO empty Flag. + * + * @retval SET or RESET + * + * @note + */ +uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag) +{ + uint32_t tmpsr = 0x00000000; + + if(bank == EMMC_BANK2_NAND) + { + tmpsr = EMMC_Bank2->STSINT2; + } + else if(bank == EMMC_BANK3_NAND) + { + tmpsr = EMMC_Bank3->STSINT3; + } + else + { + tmpsr = EMMC_Bank4->STSINT4; + } + /* Get the flag status */ + if((tmpsr & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the EMMC's pending flags. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param flag: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag. + * @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag. + * @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag. + * + * @retval None + */ +void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 &= ~flag; + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 &= ~flag; + } + else + { + EMMC_Bank4->STSINT4 &= ~flag; + } +} + +/*! + * @brief Read the specified EMMC interrupt has occurred or not. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt source. + * This parameter can be one of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval The status of specified EMMC interrupt source. + */ +uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag) +{ + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + if(bank == EMMC_BANK2_NAND) + { + tmpsr = EMMC_Bank2->STSINT2; + } + else if(bank == EMMC_BANK3_NAND) + { + tmpsr = EMMC_Bank3->STSINT3; + } + else + { + tmpsr = EMMC_Bank4->STSINT4; + } + + itstatus = tmpsr & flag; + itenable = tmpsr & (flag >> 3); + + if((itstatus != RESET) && (itenable != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the EMMC's interrupt Flag. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 &= ~(flag >> 3); + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 &= ~(flag >> 3); + } + else + { + EMMC_Bank4->STSINT4 &= ~(flag >> 3); + } +} + +/**@} end of group EMMC_Fuctions*/ +/**@} end of group EMMC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c new file mode 100644 index 0000000000..357ecf637a --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c @@ -0,0 +1,753 @@ +/*! + * @file apm32f10x_fmc.c + * + * @brief This file provides all the FMC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_fmc.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Configs the code latency value. + * + * @param latency: the FMC Latency value. + * + * @retval None + */ +void FMC_ConfigLatency(FMC_LATENCY_T latency) +{ + FMC->CTRL1_B.WS = latency; +} + +/*! + * @brief Enables the Half cycle flash access. + * + * @param None + * + * @retval None + */ +void FMC_EnableHalfCycleAccess(void) +{ + FMC->CTRL1_B.HCAEN = BIT_SET; +} + +/*! + * @brief Disable the Half cycle flash access. + * + * @param None + * + * @retval None + */ +void FMC_DisableHalfCycleAccess(void) +{ + FMC->CTRL1_B.HCAEN = BIT_RESET; +} + +/*! + * @brief Enables the Prefetch Buffer. + * + * @param None + * + * @retval None + */ +void FMC_EnablePrefetchBuffer(void) +{ + FMC->CTRL1_B.PBEN = ENABLE; +} + +/*! + * @brief Disables the Prefetch Buffer. + * + * @param None + * + * @retval None + */ +void FMC_DisablePrefetchBuffer(void) +{ + FMC->CTRL1_B.PBEN = DISABLE; +} + +/*! + * @brief Unlocks the FMC Program Erase Controller + * + * @param None + * + * @retval None + */ +void FMC_Unlock(void) +{ + FMC->KEY = 0x45670123; + FMC->KEY = 0xCDEF89AB; +} + +/*! + * @brief Locks the FMC Program Erase Controller. + * + * @param None + * + * @retval None + */ +void FMC_Lock(void) +{ + FMC->CTRL2_B.LOCK = BIT_SET; +} + +/*! + * @brief Erases a specified FMC page. + * + * @param pageAddr: The page address to be erased. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_BUSY + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.PAGEERA = BIT_SET; + FMC->ADDR = pageAddr; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.PAGEERA = BIT_RESET; + } + return status; +} + +/*! + * @brief Erases all FMC pages. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EraseAllPage(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.MASSERA = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.MASSERA = BIT_RESET; + } + return status; +} + +/*! + * @brief Erases the FMC option bytes. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EraseOptionBytes(void) +{ + uint16_t rdtemp = 0x00A5; + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + if(FMC_GetReadProtectionStatus() != RESET) + { + rdtemp = 0x00; + } + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + FMC->CTRL2_B.OBP = BIT_SET; + OB->RDP = rdtemp; + status = FMC_WaitForLastOperation(0x000B0000); + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Programs a word at a specified address. + * + * @param address:the address to be programmed. + * + * @param data: the data to be programmed. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + __IOM uint32_t temp = 0; + + #ifdef APM32F10X_HD + __set_PRIMASK(1); + #endif + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.PG = BIT_SET; + + *(__IOM uint16_t *)address = data; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + temp = address + 2; + + *(__IOM uint16_t*) temp = data >> 16; + + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.PG = BIT_RESET; + } + else + { + FMC->CTRL2_B.PG = BIT_RESET; + } + } + + #ifdef APM32F10X_HD + __set_PRIMASK(0); + #endif + + return status; +} + +/*! + * @brief Programs a half word at a specified address. + * + * @param address:the address to be programmed. + * + * @param data: the data to be programmed. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + #ifdef APM32F10X_HD + __set_PRIMASK(1); + #endif + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.PG = BIT_SET; + *(__IOM uint16_t *)address = data; + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.PG = BIT_RESET; + } + + #ifdef APM32F10X_HD + __set_PRIMASK(0); + #endif + + return status; +} + +/*! + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param address:the address to be programmed. + * + * @param data: the data to be programmed. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + FMC->CTRL2_B.OBP = BIT_SET; + *(__IOM uint16_t *)address = data; + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Write protects the desired pages + * + * @param page:the address of the pages to be write protection + * This parameter can be any combination of the following values: + * for APM32F10X_LD �� + * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31 + * for APM32F10X_MD �� + * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127 + * for APM32F10X_HD �� + * @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127 + * @arg FMC_WRP_PAGE_ALL + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page) +{ + uint16_t WPP0_Data = 0xFFFF, WPP1_Data = 0xFFFF, WPP2_Data = 0xFFFF, WPP3_Data = 0xFFFF; + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + page = ~page; + WPP0_Data = (page & 0x000000FF); + WPP1_Data = (page & 0x0000FF00) >> 8; + WPP2_Data = (page & 0x00FF0000) >> 16; + WPP3_Data = (page & 0xFF000000) >> 24; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + FMC->CTRL2_B.OBP = BIT_SET; + + if(WPP0_Data != 0xFF) + { + OB->WRP0 = WPP0_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + if((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF)) + { + OB->WRP1 = WPP1_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + if((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF)) + { + OB->WRP2 = WPP2_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + if((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF)) + { + OB->WRP3 = WPP3_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Enables the read out protection. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EnableReadOutProtection(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + FMC->CTRL2_B.OBP = BIT_SET; + OB->RDP = 0x00A5; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBE = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Disables the read out protection. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_DisableReadOutProtection(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + FMC->CTRL2_B.OBP = BIT_SET; + OB->RDP = 0x00; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBE = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Programs the FMC User Option Byte. + * + * @param userConfig: Point to a FMC_UserConfig_T structure. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + OB->USER = userConfig->iwdtSet | userConfig->stopSet | userConfig->stdbySet | 0xF8; + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Read the FMC User Option Bytes values. + * + * @param None + * + * @retval Returns User Option Bytes values + */ +uint32_t FMC_ReadUserOptionByte(void) +{ + return (FMC->OBCS_B.UOB >> 2); +} + +/*! + * @brief Read the FMC Write Protection Option Bytes Register value. + * + * @param None + * + * @retval Returns the value of Option Bytes Write Protection Register. + */ +uint32_t FMC_ReadOptionByteWriteProtection(void) +{ + return FMC->WRTPROT; +} + +/*! + * @brief Get the FMC Read Out Protection Status is set or not. + * + * @param None + * + * @retval status : set or reset. + */ +uint8_t FMC_GetReadProtectionStatus(void) +{ + uint8_t flagstatus = RESET; + + if(FMC->OBCS_B.READPROT != RESET) + { + flagstatus = SET; + } + else + { + flagstatus = RESET; + } + return flagstatus; +} + +/*! + * @brief FMC Prefetch Buffer status is set or not. + * + * @param None + * + * @retval status : set or reset. + */ +uint8_t FMC_ReadPrefetchBufferStatus(void) +{ + return FMC->CTRL1_B.PBSF; +} + +/*! + * @brief Enables the specified FMC interrupts. + * + * @param interrupt: Select the FMC interrupt sources + * This parameter can be one of the following values: + * @arg FMC_INT_ERR : Error Interrupt + * @arg FMC_INT_OC : Operation Complete Interrupt + * + * @retval None + */ +void FMC_EnableInterrupt(FMC_INT_T interrupt) +{ + if(interrupt == FMC_INT_ERR) + { + FMC->CTRL2_B.ERRIE = ENABLE; + } + else + { + FMC->CTRL2_B.OCIE = ENABLE; + } +} + +/*! + * @brief Disable the specified FMC interrupts. + * + * @param interrupt: Select the FMC interrupt sources + * This parameter can be one of the following values: + * @arg FMC_INT_ERR : Error Interrupt + * @arg FMC_INT_OC : Operation Complete Interrupt + * + * @retval None + */ +void FMC_DisableInterrupt(FMC_INT_T interrupt) +{ + if(interrupt == FMC_INT_ERR) + { + FMC->CTRL2_B.ERRIE = DISABLE; + } + else + { + FMC->CTRL2_B.OCIE = DISABLE; + } +} + +/*! + * @brief Read FMC flag is set or not + * + * @param flag: status flag of FMC + * This parameter can be one of the following values: + * @arg FMC_FLAG_BUSY : FMC Busy flag + * @arg FMC_FLAG_OC : FMC Operation Complete flag + * @arg FMC_FLAG_PE : FMC Program error flag + * @arg FMC_FLAG_WPE : FMC Write protected error flag + * @arg FMC_FLAG_OBE : FMC Option Byte error flag + * + * @retval flag status : set or reset + */ +uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag) +{ + if(flag == FMC_FLAG_OBE) + { + return FMC->OBCS_B.OBE; + } + else if((FMC->STS & flag ) != RESET) + { + return SET; + } + return RESET; +} + +/*! + * @brief Clears the FMC's flag. + * + * @param flag: status flag of FMC + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_OC : FMC Operation Complete flag + * @arg FMC_FLAG_PE : FMC Program error flag + * @arg FMC_FLAG_WPE : FMC Write protected error flag + * + * @retval None + * + * @note + */ +void FMC_ClearStatusFlag(FMC_FLAG_T flag) +{ + FMC->STS = flag; +} + +/*! + * @brief Read the FMC Status. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_BUSY + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + */ +FMC_STATUS_T FMC_ReadStatus(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + if(FMC->STS_B.BUSYF == BIT_SET) + { + status = FMC_STATUS_BUSY; + } + else if(FMC->STS_B.PEF == BIT_SET) + { + status = FMC_STATUS_ERROR_PG; + } + else if(FMC->STS_B.WPEF == BIT_SET) + { + status = FMC_STATUS_ERROR_WRP; + } + else + { + status = FMC_STATUS_COMPLETE; + } + return status; +} + +/*! + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param timeOut:FMC programming timeout value. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + /** Check for the Flash Status */ + status = FMC_ReadStatus(); + + /** Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FMC_STATUS_BUSY) && (timeOut !=0)) + { + status = FMC_ReadStatus(); + timeOut--; + } + if(timeOut == 0x00) + { + status = FMC_STATUS_TIMEOUT; + } + return status; +} + +/**@} end of group FMC_Fuctions*/ +/**@} end of group FMC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c new file mode 100644 index 0000000000..9182ae9290 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c @@ -0,0 +1,531 @@ +/*! + * @file apm32f10x_gpio.c + * + * @brief This file provides all the GPIO firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_gpio.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset GPIO peripheral registers to their default reset values + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @retval None + */ +void GPIO_Reset(GPIO_T* port) +{ + RCM_APB2_PERIPH_T APB2Periph; + + if (port == GPIOA) + { + APB2Periph = RCM_APB2_PERIPH_GPIOA; + } + else if (port == GPIOB) + { + APB2Periph = RCM_APB2_PERIPH_GPIOB; + } + else if (port == GPIOC) + { + APB2Periph = RCM_APB2_PERIPH_GPIOC; + } + else if (port == GPIOD) + { + APB2Periph = RCM_APB2_PERIPH_GPIOD; + } + else if (port == GPIOE) + { + APB2Periph = RCM_APB2_PERIPH_GPIOE; + } + else if (port == GPIOF) + { + APB2Periph = RCM_APB2_PERIPH_GPIOF; + } + else if (port == GPIOG) + { + APB2Periph = RCM_APB2_PERIPH_GPIOG; + } + + RCM_EnableAPB2PeriphReset(APB2Periph); + RCM_DisableAPB2PeriphReset(APB2Periph); +} + +/*! + * @brief Reset Alternate Functions registers to their default reset values + * + * @param None + * + * @retval None + */ +void GPIO_AFIOReset(void) +{ + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_AFIO); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_AFIO); +} + +/*! + * @brief Config the GPIO peripheral according to the specified parameters in the gpioConfig + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param gpioConfig: pointer to a GPIO_Config_T structure + * + * @retval None + */ +void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig) +{ + uint8_t i; + uint32_t mode; + uint32_t CR; + uint32_t temp; + uint32_t shift; + + mode = gpioConfig->mode & 0x0f; + + if (gpioConfig->mode & 0x80) + { + mode |= gpioConfig->speed; + } + + if (gpioConfig->pin & 0xff) + { + CR = port->CFGLOW; + + for (i = 0, shift = 0x01; i < 8; i++, shift <<= 1) + { + if (gpioConfig->pin & shift) + { + temp = i << 2; + CR &= (uint32_t)~(0x0f << temp); + CR |= mode << temp; + + if (gpioConfig->mode == GPIO_MODE_IN_PD) + { + port->BC = shift; + } + else if (gpioConfig->mode == GPIO_MODE_IN_PU) + { + port->BSC = shift; + } + } + } + + port->CFGLOW = CR; + } + + if (gpioConfig->pin & 0xff00) + { + CR = port->CFGHIG; + + for (i = 8, shift = 0x100; i < 16; i++, shift <<= 1) + { + if (gpioConfig->pin & shift) + { + temp = (i - 8) << 2; + CR &= (uint32_t)~(0x0f << temp); + CR |= mode << temp; + + if (gpioConfig->mode == GPIO_MODE_IN_PD) + { + port->BC = shift; + } + else if (gpioConfig->mode == GPIO_MODE_IN_PU) + { + port->BSC = shift; + } + } + } + + port->CFGHIG = CR; + } +} + +/*! + * @brief Fills each gpioConfig member with its default value. + * + * @param gpioConfig : pointer to a GPIO_Config_T structure which will be initialized. + * + * @retval None + */ +void GPIO_StructInit(GPIO_Config_T* gpioConfig) +{ + gpioConfig->pin = GPIO_PIN_ALL; + gpioConfig->speed = GPIO_SPEED_2MHz; + gpioConfig->mode = GPIO_MODE_IN_FLOATING; +} + +/*! + * @brief Reads the specified input port pin + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to read. + * This parameter can be one of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval The input port pin value + */ +uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin) +{ + uint8_t ret; + + ret = (port->IDATA & pin) ? BIT_SET : BIT_RESET; + + return ret; +} + +/*! + * @brief Reads the specified GPIO input data port + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @retval GPIO input data port value + */ +uint16_t GPIO_ReadInputPort(GPIO_T* port) +{ + return ((uint16_t)port->IDATA); +} + +/*! + * @brief Reads the specified output data port bit + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to read. + * This parameter can be one of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval The output port pin value + */ +uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin) +{ + + uint8_t ret; + + ret = (port->ODATA & pin) ? BIT_SET : BIT_RESET; + + return ret; +} + +/*! + * @brief Reads the specified GPIO output data port + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @retval output data port value + */ +uint16_t GPIO_ReadOutputPort(GPIO_T* port) +{ + return ((uint16_t)port->ODATA); +} + +/*! + * @brief Sets the selected data port bits + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to be written. + * This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_SetBits(GPIO_T* port, uint16_t pin) +{ + port->BSC = (uint32_t)pin; +} + +/*! + * @brief Clears the selected data port bits + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to be cleared. + * This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ResetBits(GPIO_T* port, uint16_t pin) +{ + port->BC = (uint32_t)pin; +} + +/*! + * @brief Writes data to the specified GPIO data port bit + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : Select specifies pin. + * This parameter can be one of GPIO_PIN_x( x can be from 0 to 15). + * + * + * @param bitVal : specifies the value to be written to the port output data register + * This parameter can be one of the following values: + * @arg BIT_RESET: Reset the port pin + * @arg BIT_SET : Set the port pin + * + * @retval None + */ +void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal) +{ + if (bitVal != BIT_RESET) + { + port->BSC = pin; + } + else + { + port->BC = pin ; + } +} + +/*! + * @brief Writes data to the specified GPIO data port + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param portValue : specifies the value to be written to the port output data register. + * + * @retval None + */ +void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue) +{ + port->ODATA = (uint32_t)portValue; +} + +/*! + * @brief Locks GPIO Pins configuration registers + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : Select specifies pin. + * This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin) +{ + uint32_t val = 0x00010000; + + val |= pin; + /* Set LCKK bit */ + port->LOCK = val ; + /* Reset LCKK bit */ + port->LOCK = pin; + /* Set LCKK bit */ + port->LOCK = val; + /* Read LCKK bit*/ + val = port->LOCK; + /* Read LCKK bit*/ + val = port->LOCK; +} + +/*! + * @brief Selects the GPIO pin used as Event output + * + * @param portSource : selects the GPIO port to be used as source for Event output. + * This parameter can be one of GPIO_PORT_SOURCE_x( x can be from A to E). + * + * @param pinSource specifies the pin for the Event output + * This parameter can be GPIO_PIN_SOURCE_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource) +{ + AFIO->EVCTRL_B.PORTSEL = portSource; + AFIO->EVCTRL_B.PINSEL = pinSource; +} + +/*! + * @brief Enables the Event Output + * + * @param None + * + * @retval None + */ +void GPIO_EnableEventOutput(void) +{ + AFIO->EVCTRL_B.EVOEN = BIT_SET; +} + +/*! + * @brief Disable the Event Output + * + * @param None + * + * @retval None + */ +void GPIO_DisableEventOutput(void) +{ + AFIO->EVCTRL_B.EVOEN = BIT_RESET; +} + +/*! + * @brief Changes the mapping of the specified pin + * + * @param remap : selects the pin to remap + * This parameter can be one of the following values: + * @arg GPIO_NO_REMAP_SPI1 : No SPI1 Alternate Function mapping + * @arg GPIO_REMAP_SPI1 : SPI1 Alternate Function mapping + * @arg GPIO_NO_REMAP_I2C1 : No I2C1 Alternate Function mapping + * @arg GPIO_REMAP_I2C1 : I2C1 Alternate Function mapping + * @arg GPIO_NO_REMAP_USART1 : No USART1 Alternate Function mapping + * @arg GPIO_REMAP_USART1 : USART1 Alternate Function mapping + * @arg GPIO_NO_REMAP_USART2 : No USART2 Alternate Function mapping + * @arg GPIO_REMAP_USART2 : USART2 Alternate Function mapping + * @arg GPIO_NO_REMAP_USART3 : No USART3 Partial Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP_USART3 : USART3 Partial Alternate Function mapping + * @arg GPIO_FULL_REMAP_USART3 : USART3 Full Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR1 : No TIM1 Partial Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP_TMR1 : TIM1 Partial Alternate Function mapping + * @arg GPIO_FULL_REMAP_TMR1 : TIM1 Full Alternate Function mapping + * @arg GPIO_NO_REMAP1_TMR2 : No TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP1_TMR2 : TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP2_TMR2 : TIM2 Partial2 Alternate Function mapping + * @arg GPIO_FULL_REMAP_TMR2 : TIM2 Full Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR3 : No TIM3 Partial Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP_TMR3 : TIM3 Partial Alternate Function mapping + * @arg GPIO_FULL_REMAP_TMR3 : TIM3 Full Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR4 : No TIM4 Alternate Function mapping + * @arg GPIO_REMAP_TMR4 : TIM4 Alternate Function mapping + * @arg GPIO_NO_REMAP_CAN1 : No CAN1 Alternate Function mapping + * @arg GPIO_REMAP1_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_REMAP2_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_NO_REMAP_PD01 : No PD01 Alternate Function mapping + * @arg GPIO_REMAP_PD01 : PD01 Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR5CH4_LSI : No LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_REMAP_TMR5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_NO_REMAP_ADC1_ETRGINJ : No ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_REMAP_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_NO_REMAP_ADC1_ETRGREG : No ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_REMAP_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_NO_REMAP_ADC2_ETRGINJ : No ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_REMAP_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_NO_REMAP_ADC2_ETRGREG : No ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_REMAP_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_NO_REMAP_CAN2 : No CAN2 Alternate Function mapping + * @arg GPIO_REMAP_CAN2 : CAN2 Alternate Function mapping + * @arg GPIO_NO_REMAP_SWJ : Full SWJ Enabled (JTAG-DP + SW-DP) + * @arg GPIO_REMAP_SWJ_NOJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_REMAP_SWJ_JTAGDISABLE : JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_REMAP_SWJ_DISABLE : Full SWJ Disabled (JTAG-DP + SW-DP) + * + * @retval When you use GPIO_REMAP_CAN2, you must put this function last of all other ConfigPinRemap Function. + */ +void GPIO_ConfigPinRemap(GPIO_REMAP_T remap) +{ + uint32_t val, mask, bitOffset, regOffset; + uint32_t regVal; + + val = remap & 0x0f; + mask = (remap >> 4) & 0x0f; + bitOffset = (remap >> 8) & 0xff; + regOffset = (remap >> 16) & 0x0f; + + if (regOffset) + { + regVal = AFIO->REMAP2; + } + else + { + regVal = AFIO->REMAP1; + } + + if(remap >> 8 == 0x18) + { + regVal &= 0xF0FFFFFF; + AFIO->REMAP1 &= 0xF0FFFFFF; + } + else + { + regVal |= 0x0F000000; + } + + mask <<= bitOffset; + regVal &= (uint32_t)~mask; + val <<= bitOffset; + regVal |= val; + + if (regOffset) + { + AFIO->REMAP2 = regVal; + } + else + { + AFIO->REMAP1 = regVal; + } +} + +/*! + * @brief Selects the GPIO pin used as EINT Line + * + * @param portSource : selects the GPIO port to be used as source for EINT line. + * This parameter can be one of GPIO_PORT_SOURCE_x( x can be from A to G). + * + * @param pinSource : Specifies the EINT line to be configured. + * This parameter can be GPIO_PIN_SOURCE_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource) +{ + uint32_t shift; + + if (pinSource <= GPIO_PIN_SOURCE_3) + { + shift = pinSource << 2; + AFIO->EINTSEL1 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL1 |= portSource << shift; + } + + else if (pinSource <= GPIO_PIN_SOURCE_7) + { + shift = (pinSource - GPIO_PIN_SOURCE_4) << 2; + AFIO->EINTSEL2 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL2 |= portSource << shift; + } + + else if (pinSource <= GPIO_PIN_SOURCE_11) + { + shift = (pinSource - GPIO_PIN_SOURCE_8) << 2; + AFIO->EINTSEL3 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL3 |= portSource << shift; + } + + else if (pinSource <= GPIO_PIN_SOURCE_15) + { + shift = (pinSource - GPIO_PIN_SOURCE_12) << 2; + AFIO->EINTSEL4 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL4 |= portSource << shift; + } +} + +/**@} end of group GPIO_Fuctions*/ +/**@} end of group GPIO_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c new file mode 100644 index 0000000000..319866723b --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c @@ -0,0 +1,1013 @@ +/*! + * @file apm32f10x_i2c.c + * + * @brief This file provides all the I2C firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_i2c.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset I2C + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_Reset(I2C_T* i2c) +{ + if(i2c == I2C1) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + } + else + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + } +} + +/*! + * @brief Configure I2C by configuring the structure + * + * @param i2c: I2C selet 1 or 2 + * + * @param i2cConfig: pointer to a I2C_Config_T structure + * + * @retval None + */ +void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint32_t PCLK1 = 8000000, PCLK2 = 0; + uint16_t result = 0x04; + + i2c->SWITCH = 0; + + /** I2C CTRL2 Configuration */ + RCM_ReadPCLKFreq(&PCLK1, &PCLK2); + freqrange = PCLK1 / 1000000; + i2c->CTRL2_B.CLKFCFG= freqrange; + + /** I2C CLKCTRL Configuration */ + i2c->CTRL1_B.I2CEN = BIT_RESET; + + if(i2cConfig->clockSpeed <= 100000) + { + result = (PCLK1 / (i2cConfig->clockSpeed << 1)); + if(result < 0x04) + { + result = 0x04; + } + i2c->RISETMAX = freqrange + 1; + tmpreg |= result; + } + /** Configure speed in fast mode */ + else + { + if(i2cConfig->dutyCycle == I2C_DUTYCYCLE_2) + { + result = (PCLK1 / (i2cConfig->clockSpeed * 3)); + } + else + { + result = (PCLK1 / (i2cConfig->clockSpeed * 25)); + result |= I2C_DUTYCYCLE_16_9; + } + + if((result & 0x0FFF) == 0) + { + result |= 0x0001; + } + + tmpreg |= (uint16_t)(result | 0x8000); + i2c->RISETMAX = ((((freqrange) * 300) / 1000) + 1); + } + i2c->CLKCTRL = tmpreg; + i2c->CTRL1_B.I2CEN = BIT_SET; + + /** i2c CTRL1 Configuration */ + i2c->CTRL1_B.ACKEN = BIT_RESET; + i2c->CTRL1_B.SMBTCFG = BIT_RESET; + i2c->CTRL1_B.SMBEN = BIT_RESET; + + i2c->CTRL1 |= i2cConfig->mode; + i2c->CTRL1_B.ACKEN = i2cConfig->ack; + + i2c->SADDR1 = i2cConfig->ackAddress | i2cConfig->ownAddress1; +} + +/*! + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param i2cConfig: pointer to a I2C_Config_T structure + * + * @retval None + */ +void I2C_ConfigStructInit(I2C_Config_T* i2cConfig) +{ + i2cConfig->clockSpeed = 5000; + i2cConfig->mode = I2C_MODE_I2C; + i2cConfig->dutyCycle = I2C_DUTYCYCLE_2; + i2cConfig->ownAddress1 = 0; + i2cConfig->ack = I2C_ACK_DISABLE; + i2cConfig->ackAddress = I2C_ACK_ADDRESS_7BIT; +} + +/*! + * @brief Enable I2C + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_Enable(I2C_T* i2c) +{ + i2c->CTRL1_B.I2CEN = ENABLE; +} + +/*! + * @brief Disable I2C + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_Disable(I2C_T* i2c) +{ + i2c->CTRL1_B.I2CEN = DISABLE; +} + +/*! + * @brief Enable Generates i2c communication START condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableGenerateStart(I2C_T* i2c) +{ + i2c->CTRL1_B.START = BIT_SET; +} + +/*! + * @brief Disable Generates i2c communication START condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableGenerateStart(I2C_T* i2c) +{ + i2c->CTRL1_B.START = BIT_RESET; +} + +/*! + * @brief Enable Generates i2c communication STOP condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableGenerateStop(I2C_T* i2c) +{ + i2c->CTRL1_B.STOP = BIT_SET; +} + +/*! + * @brief Disable Generates i2c communication STOP condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableGenerateStop(I2C_T* i2c) +{ + i2c->CTRL1_B.STOP = BIT_RESET; +} + +/*! + * @brief Enables the specified I2C acknowledge feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableAcknowledge(I2C_T* i2c) +{ + i2c->CTRL1_B.ACKEN = ENABLE; +} + +/*! + * @brief Disables the specified I2C acknowledge feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableAcknowledge(I2C_T* i2c) +{ + i2c->CTRL1_B.ACKEN = DISABLE; +} + +/*! + * @brief Config the specified I2C own address2. + * + * @param i2c: I2C selet 1 or 2 + * + * @param address:specifies the 7bit I2C own address2. + * + * @retval None + */ +void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address) +{ + i2c->SADDR2_B.ADDR2 = address; +} + +/*! + * @brief Enables the specified I2C dual addressing mode. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableDualAddress(I2C_T* i2c) +{ + i2c->SADDR2_B.ADDRNUM = ENABLE; +} + +/*! + * @brief Disables the specified I2C dual addressing mode. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableDualAddress(I2C_T* i2c) +{ + i2c->SADDR2_B.ADDRNUM = DISABLE; +} + +/*! + * @brief Enables the specified I2C general call feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableGeneralCall(I2C_T* i2c) +{ + i2c->CTRL1_B.SRBEN = ENABLE; +} + +/*! + * @brief Disables the specified I2C general call feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableGeneralCall(I2C_T* i2c) +{ + i2c->CTRL1_B.SRBEN = DISABLE; +} + +/*! + * @brief Send one byte + * + * @param i2c: I2C selet 1 or 2 + * + * @param data: data to send + * + * @retval None + */ +void I2C_TxData(I2C_T* i2c, uint8_t data) +{ + i2c->DATA_B.DATA = data; +} + +/*! + * @brief Returns the recevie data + * + * @param i2c: I2C selet 1 or 2 + * + * @retval received data + */ +uint8_t I2C_RxData(I2C_T* i2c) +{ + return i2c->DATA_B.DATA; +} + +/*! + * @brief Transmits the address byte to select the slave device. + * + * @param i2c: I2C selet 1 or 2 + * + * @param address: slave address which will be transmitted + * + * @param direction: Direction mode + * The parameter can be one of following values: + * @arg I2C_DIRECTION_TX: Transmitter mode + * @arg I2C_DIRECTION_RX: Receiver mode + * @retval None + */ +void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction) +{ + if(direction != I2C_DIRECTION_TX) + { + i2c->DATA_B.DATA = address | 0x0001; + } + else + { + i2c->DATA_B.DATA = address & 0xFFFE; + } +} + +/*! + * @brief Reads the I2C register and returns its value. + * + * @param i2c: I2C selet 1 or 2 + * + * @param i2cRegister : register to read + * The parameter can be one of following values: + * @arg I2C_REGISTER_CTRL1: CTRL1 register + * @arg I2C_REGISTER_CTRL2: CTRL2 register + * @arg I2C_REGISTER_SADDR1: SADDR1 register + * @arg I2C_REGISTER_SADDR2: SADDR2 register + * @arg I2C_REGISTER_DATA: DATA register + * @arg I2C_REGISTER_STS1: STS1 register + * @arg I2C_REGISTER_STS2: STS2 register + * @arg I2C_REGISTER_CLKCTRL: CLKCTRL register + * @arg I2C_REGISTER_RISETMAX: RISETMAX register + * @arg I2C_REGISTER_SWITCH: SWITCH register + * + * @retval The value of the read register + */ +uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister) +{ + switch (i2cRegister) + { + case I2C_REGISTER_CTRL1: + return i2c->CTRL1; + case I2C_REGISTER_CTRL2: + return i2c->CTRL2; + case I2C_REGISTER_SADDR1: + return i2c->SADDR1; + case I2C_REGISTER_SADDR2: + return i2c->SADDR2; + case I2C_REGISTER_DATA: + return i2c->DATA; + case I2C_REGISTER_STS1: + return i2c->STS1; + case I2C_REGISTER_STS2: + return i2c->STS2; + case I2C_REGISTER_CLKCTRL: + return i2c->CLKCTRL; + case I2C_REGISTER_RISETMAX: + return i2c->RISETMAX; + case I2C_REGISTER_SWITCH: + return i2c->SWITCH; + default: + return 0; + } +} + +/*! + * @brief Enables the I2C software reset. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableSoftwareReset(I2C_T* i2c) +{ + i2c->CTRL1_B.SWRST = ENABLE; +} + +/*! + * @brief Disables the I2C software reset. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableSoftwareReset(I2C_T* i2c) +{ + i2c->CTRL1_B.SWRST = DISABLE; +} + +/*! + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param i2c: I2C selet 1 or 2 + * + * @param NACKPosition: specifies the NACK position. + * + * @retval None + */ +void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition) +{ + if(NACKPosition == I2C_NACK_POSITION_NEXT) + { + i2c->CTRL1_B.ACKPOS = BIT_SET; + } + else + { + i2c->CTRL1_B.ACKPOS = BIT_RESET; + } +} + +/*! + * @brief Control the height of pin of SMBusAlert + * + * @param i2c: I2C selet 1 or 2 + * + * @param SMBusState: SMBAlert pin level. + * The parameter can be one of following values: + * @arg I2C_SMBUSALER_LOW: SMBus Alert pin low + * @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high + * @retval None + */ +void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState) +{ + if(SMBusState == I2C_SMBUSALER_LOW) + { + i2c->CTRL1_B.ALERTEN = BIT_SET; + } + else + { + i2c->CTRL1_B.ALERTEN = BIT_RESET; + } +} + +/*! + * @brief Enables the I2C PEC transfer. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnablePECTransmit(I2C_T* i2c) +{ + i2c->CTRL1_B.PEC = BIT_SET; +} + +/*! + * @brief Disables the I2C PEC transfer. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisablePECTransmit(I2C_T* i2c) +{ + i2c->CTRL1_B.PEC = BIT_RESET; +} + +/*! + * @brief Selects the I2C PEC position. + * + * @param i2c: I2C selet 1 or 2 + * + * @param PECPosition: PEC position + * The parameter can be one of following values: + * @arg I2C_PEC_POSITION_NEXT: indicates that the next byte is PEC + * @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC + * @retval None + */ +void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition) +{ + if(PECPosition == I2C_PEC_POSITION_NEXT) + { + i2c->CTRL1_B.ACKPOS = BIT_SET; + } + else + { + i2c->CTRL1_B.ACKPOS = BIT_RESET; + } +} + +/*! + * @brief Enables the PEC value calculation of the transferred bytes. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnablePEC(I2C_T* i2c) +{ + i2c->CTRL1_B.PECEN = BIT_SET; +} + +/*! + * @brief Disables the PEC value calculation of the transferred bytes. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisablePEC(I2C_T* i2c) +{ + i2c->CTRL1_B.PECEN = BIT_RESET; +} + +/*! + * @brief Read the PEC value for the I2C. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval value of PEC + */ +uint8_t I2C_ReadPEC(I2C_T* i2c) +{ + return i2c->STS2_B.PECVALUE; +} + +/*! + * @brief Enables the I2C ARP. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableARP(I2C_T* i2c) +{ + i2c->CTRL1_B.ARPEN = BIT_SET; +} + +/*! +* @brief Disables the I2C ARP. +* +* @param i2c: I2C selet 1 or 2 +* +* @retval None +*/ +void I2C_DisableARP(I2C_T* i2c) +{ + i2c->CTRL1_B.ARPEN = BIT_RESET; +} + +/*! + * @brief Enables the I2C Clock stretching. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableStretchClock(I2C_T* i2c) +{ + i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET; +} + +/*! + * @brief Disables the I2C Clock stretching. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableStretchClock(I2C_T* i2c) +{ + i2c->CTRL1_B.CLKSTRETCHD = BIT_SET; +} + +/*! + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param i2c: I2C selet 1 or 2 + * + * @param dutyCycle: the fast mode duty cycle. + * The parameter can be one of following values: + * @arg I2C_DUTYCYCLE_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2 + * @retval None + */ +void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle) +{ + if(dutyCycle == I2C_DUTYCYCLE_16_9) + { + i2c->CLKCTRL_B.FDUTYCFG = BIT_SET; + } + else + { + i2c->CLKCTRL_B.FDUTYCFG = BIT_RESET; + } +} + +/*! + * @brief Enables the specified I2C DMA requests. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableDMA(I2C_T* i2c) +{ + i2c->CTRL2_B.DMAEN = ENABLE; +} + +/*! + * @brief Disable the specified I2C DMA requests. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableDMA(I2C_T* i2c) +{ + i2c->CTRL2_B.DMAEN = DISABLE; +} + +/*! + * @brief Enable DMA to receive the last transfer + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableDMALastTransfer(I2C_T* i2c) +{ + i2c->CTRL2_B.LTCFG = BIT_SET; +} + +/*! + * @brief Disable DMA to receive the last transfer + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableDMALastTransfer(I2C_T* i2c) +{ + i2c->CTRL2_B.LTCFG = BIT_RESET; +} + +/*! + * @brief Enables the specified I2C interrupts. + * + * @param i2c: I2C selet 1 or 2 + * + * @param interrupt:I2C interrupts sources + * The parameter can be any combination of following values: + * @arg I2C_INT_BUF: Buffer interrupt + * @arg I2C_INT_EVT: Event interrupt + * @arg I2C_INT_ERR: Error interrupt + * + * @retval None + */ +void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt) +{ + i2c->CTRL2 |= interrupt; +} + +/*! + * @brief Disable the specified I2C interrupts. + * + * @param i2c: I2C selet 1 or 2 + * + * @param interrupt:I2C interrupts sources + * The parameter can be any combination of following values: + * @arg I2C_INT_BUF: Buffer interrupt + * @arg I2C_INT_EVT: Event interrupt + * @arg I2C_INT_ERR: Error interrupt + * + * @retval None + */ +void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt) +{ + i2c->CTRL2 &= ~interrupt; +} + +/*! + * @brief Check that the last event is equal to the last passed event + * + * @param i2c: I2C selet 1 or 2 + * + * @param i2cEvent: the event to be checked. + * The parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @retval Status: SUCCESS or ERROR + */ +uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = i2c->STS1 & 0x0000FFFF; + flag2 = i2c->STS2 & 0x0000FFFF; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & 0x00FFFFFF; + + if((lastevent & i2cEvent) == i2cEvent) + { + return SUCCESS; + } + return ERROR; +} + +/*! + * @brief Read the last i2c Event. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval The last event + */ +uint32_t I2C_ReadLastEvent(I2C_T* i2c) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = i2c->STS1 & 0x0000FFFF; + flag2 = i2c->STS2 & 0x0000FFFF; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & 0x00FFFFFF; + + return lastevent; +} + +/*! + * @brief Check whether the I2C flag is set + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C flag + * The parameter can be one of the following values: + * @arg I2C_FLAG_DUALADDR: Dual flag (Slave mode) + * @arg I2C_FLAG_SMMHADDR: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDADDR: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TR: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSBSY: Bus busy flag + * @arg I2C_FLAG_MS: Master/Slave flag + * @arg I2C_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_FLAG_PECE: PEC error in reception flag + * @arg I2C_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AE: Acknowledge error flag + * @arg I2C_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXBE: Transmitter data register empty flag + * @arg I2C_FLAG_RXBNE: Receiver data register not empty flag + * @arg I2C_FLAG_STOP: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADDR10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTC: Byte transfer complete flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) + * @arg I2C_FLAG_START: Start bit flag (Master mode) + * + * @retval Status: flag SET or RESET + */ +uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) +{ + + uint8_t status = 0; + switch (flag) + { + case I2C_FLAG_DUALADDR: + status = i2c->STS2_B.DUALADDRFLG; + break; + case I2C_FLAG_SMMHADDR: + status = i2c->STS2_B.SMMHADDR; + break; + case I2C_FLAG_SMBDADDR: + status = i2c->STS2_B.SMBDADDRFLG; + break; + case I2C_FLAG_GENCALL: + status = i2c->STS2_B.GENCALLFLG; + break; + case I2C_FLAG_TR: + status = i2c->STS2_B.TRFLG; + break; + case I2C_FLAG_BUSBSY: + status = i2c->STS2_B.BUSBSYFLG; + break; + case I2C_FLAG_MS: + status = i2c->STS2_B.MSFLG; + break; + case I2C_FLAG_SMBALT: + status = i2c->STS1_B.SMBALTFLG; + break; + case I2C_FLAG_TTE: + status = i2c->STS1_B.TTEFLG; + break; + case I2C_FLAG_PECE: + status = i2c->STS1_B.PECEFLG; + break; + case I2C_FLAG_OVRUR: + status = i2c->STS1_B.OVRURFLG; + break; + case I2C_FLAG_AE: + status = i2c->STS1_B.AEFLG; + break; + case I2C_FLAG_AL: + status = i2c->STS1_B.ALFLG; + break; + case I2C_FLAG_BERR: + status = i2c->STS1_B.BERRFLG; + break; + case I2C_FLAG_TXBE: + status = i2c->STS1_B.TXBEFLG; + break; + case I2C_FLAG_RXBNE: + status = i2c->STS1_B.RXBNEFLG; + break; + case I2C_FLAG_STOP: + status = i2c->STS1_B.STOPFLG; + break; + case I2C_FLAG_ADDR10: + status = i2c->STS1_B.ADDR10FLG; + break; + case I2C_FLAG_BTC: + status = i2c->STS1_B.BTCFLG; + break; + case I2C_FLAG_ADDR: + status = i2c->STS1_B.ADDRFLG; + break; + case I2C_FLAG_START: + status = i2c->STS1_B.STARTFLG; + break; + default: + break; + } + return status; +} + +/*! + * @brief Clear the I2C flag + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C flag + * The parameter can be one of the following values: + * @arg I2C_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_FLAG_PECE: PEC error in reception flag + * @arg I2C_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AE: Acknowledge error flag + * @arg I2C_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @retval None + * + * @note 1)I2C_FLAG_STOP: Stop detection flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a write operation to I2C_CRTL1 register (I2C_Enable()). + * 2)I2C_FLAG_ADDR10: 10-bit header sent flag is cleared by software sequence: + * a read operation to I2C_STS1 (I2C_ReadStatusFlag()) + * followed by writing the second byte of the address in I2C_DATA register. + * 3)I2C_FLAG_BTC: Byte transfer complete flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a read/write to I2C_DATA register (I2C_TxData()). + * 4)I2C_FLAG_ADDR: Address sent flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a read operation to I2C_STS2 register ((void)(I2Cx->STS2)). + * 5)I2C_FLAG_START: Start bit flag is cleared software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a write operation to I2C_DATA register (I2C_TxData()). + */ +void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) +{ + switch (flag) + { + case I2C_FLAG_SMBALT: + i2c->STS1_B.SMBALTFLG = BIT_RESET; + break; + case I2C_FLAG_TTE: + i2c->STS1_B.TTEFLG = BIT_RESET; + break; + case I2C_FLAG_PECE: + i2c->STS1_B.PECEFLG = BIT_RESET; + break; + case I2C_FLAG_OVRUR: + i2c->STS1_B.OVRURFLG = BIT_RESET; + break; + case I2C_FLAG_AE: + i2c->STS1_B.AEFLG = BIT_RESET; + break; + case I2C_FLAG_AL: + i2c->STS1_B.ALFLG = BIT_RESET; + break; + case I2C_FLAG_BERR: + i2c->STS1_B.BERRFLG = BIT_RESET; + break; + default: + break; + } +} + +/*! + * @brief Check whether the I2C interrupts is set + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C interrupts + * The parameter can be one of the following values: + * @arg I2C_INT_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_INT_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_INT_FLAG_PECE: PEC error in reception flag + * @arg I2C_INT_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_FLAG_AE: Acknowledge error flag + * @arg I2C_INT_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_INT_FLAG_BERR: Bus error flag + * @arg I2C_INT_FLAG_TXBE: Transmitter data register empty flag + * @arg I2C_INT_FLAG_RXBNE: Receiver data register not empty flag + * @arg I2C_INT_FLAG_STOP: Stop detection flag (Slave mode) + * @arg I2C_INT_FLAG_ADDR10: 10-bit header sent flag (Master mode) + * @arg I2C_INT_FLAG_BTC: Byte transfer complete flag + * @arg I2C_INT_FLAG_ADDR: Address sent flag (Master mode) + * @arg I2C_INT_FLAG_START: Start bit flag (Master mode) + * + * @retval Status: flag SET or RESET + */ +uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) +{ + uint32_t enablestatus = 0; + + enablestatus = ((flag & 0x07000000) >> 16) & (i2c->CTRL2); + flag &= 0x00FFFFFF; + if(((i2c->STS1 & flag) != RESET) && enablestatus) + { + return SET; + } + return RESET; +} + +/*! + * @brief Clears the I2C interrupt flag bits. + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C flag + * The parameter can be one of the following values: + * @arg I2C_INT_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_INT_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_INT_FLAG_PECE: PEC error in reception flag + * @arg I2C_INT_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_FLAG_AE: Acknowledge error flag + * @arg I2C_INT_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_INT_FLAG_BERR: Bus error flag + * + * @retval None + * + * @note 1)I2C_INT_FLAG_STOP: Stop detection flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a write operation to I2C_CRTL1 register (I2C_Enable()). + * 2)I2C_INT_FLAG_ADDR10: 10-bit header sent flag is cleared by software sequence: + * a read operation to I2C_STS1 (I2C_ReadIntFlag()) + * followed by writing the second byte of the address in I2C_DATA register. + * 3)I2C_INT_FLAG_BTC: Byte transfer complete flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a read/write to I2C_DATA register (I2C_TxData()). + * 4)I2C_INT_FLAG_ADDR: Address sent flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a read operation to I2C_STS2 register ((void)(I2Cx->STS2)). + * 5)I2C_INT_FLAG_START: Start bit flag is cleared software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a write operation to I2C_DATA register (I2C_TxData()). + */ +void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) +{ + uint32_t flagpos = 0; + + flagpos = flag & 0x00FFFFFF; + i2c->STS1 = ~flagpos; +} + +/**@} end of group I2C_Fuctions*/ +/**@} end of group I2C_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c new file mode 100644 index 0000000000..a4a743749c --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c @@ -0,0 +1,135 @@ +/*! + * @file apm32f10x_iwdt.c + * + * @brief This file provides all the IWDT firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_iwdt.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup IWDT_Driver IWDT Driver + @{ +*/ + +/** @addtogroup IWDT_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Enable IWDT + * + * @param None + * + * @retval None + */ +void IWDT_Enable(void) +{ + IWDT->KEY = IWDT_KEYWORD_ENABLE; +} + +/*! + * @brief Reload the IWDT counter with value + * + * @param None + * + * @retval None + */ +void IWDT_Refresh(void) +{ + IWDT->KEY = IWDT_KEYWORD_RELOAD; +} + +/*! + * @brief Set IWDT count reload values + * + * @param reload: IWDT count reload values + * + * @retval None + */ +void IWDT_ConfigReload(uint16_t reload) +{ + IWDT->CNTRLD = reload; +} + +/*! + * @brief Enable the IWDT write access + * + * @param None + * + * @retval None + */ +void IWDT_EnableWriteAccess(void) +{ + IWDT->KEY_B.KEY = IWDT_WRITEACCESS_ENABLE; +} + +/*! + * @brief Disable the IWDT write access + * + * @param None + * + * @retval None + */ +void IWDT_DisableWriteAccess(void) +{ + IWDT->KEY_B.KEY = IWDT_WRITEACCESS_DISABLE; +} + +/*! + * @brief Set IWDT frequency divider values + * + * @param div: IWDT frequency divider values + * This parameter can be one of the following values: + * @arg IWDT_DIVIDER_4 : prescaler divider equal to 4 + * @arg IWDT_DIVIDER_8 : prescaler divider equal to 8 + * @arg IWDT_DIVIDER_16 : prescaler divider equal to 16 + * @arg IWDT_DIVIDER_32 : prescaler divider equal to 32 + * @arg IWDT_DIVIDER_64 : prescaler divider equal to 64 + * @arg IWDT_DIVIDER_128: prescaler divider equal to 128 + * @arg IWDT_DIVIDER_256: prescaler divider equal to 256 + * + * @retval None + */ +void IWDT_ConfigDivider(uint8_t div) +{ + IWDT->PSC = div; +} + +/*! + * @brief Read the specified IWDT flag + * + * @param flag: specifies the flag to read + * This parameter can be one of the following values: + * @arg IWDT_FLAG_PSCU : Watchdog Prescaler Factor Update flag + * @arg IWDT_FLAG_CNTU : Watchdog Counter Reload Value Update flag + * + * @retval status of IWDT_FLAG (SET or RESET) + * + * @note + */ +uint8_t IWDT_ReadStatusFlag(uint16_t flag) +{ + uint8_t bitStatus = RESET; + + if((IWDT->STS & flag) != (uint32_t)RESET) + { + bitStatus = SET; + } + else + { + bitStatus = RESET; + } + return bitStatus; +} + +/**@} end of group IWDT_Fuctions*/ +/**@} end of group IWDT_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c new file mode 100644 index 0000000000..92b925b937 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c @@ -0,0 +1,207 @@ +/*! + * @file apm32f10x_misc.c + * + * @brief This file provides all the miscellaneous firmware functions. + * Include NVIC,SystemTick and Power management. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_misc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup MISC_Driver MISC Driver + @{ +*/ + +/** @addtogroup MISC_Macros Macros + @{ +*/ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/**@} end of group I2C_Macros*/ + + +/** @addtogroup MISC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * + * @param priorityGroup : specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITY_GROUP_0 + * @arg NVIC_PRIORITY_GROUP_1 + * @arg NVIC_PRIORITY_GROUP_2 + * @arg NVIC_PRIORITY_GROUP_3 + * @arg NVIC_PRIORITY_GROUP_4 + * + * @retval None + */ +void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup; +} + +/*! + * @brief Enable NVIC request + * + * @param irq: the NVIC interrupt request, detailed in IRQn_Type + * For the complete APM32 Devices IRQ Channels list,please refer to apm32f10x.h file + * + * @param preemptionPriority: the pre-emption priority needed to set + * + * @param subPriority: the subpriority needed to set + * + * @retval None + */ +void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority) +{ + uint32_t tempPriority, tempPrePri, tempSubPri; + uint32_t priorityGrp; + + /** Get priority group */ + priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U; + + /** get pre-emption priority and subpriority */ + switch(priorityGrp) + { + case NVIC_PRIORITY_GROUP_0: + tempPrePri = 0; + tempSubPri = 4; + break; + + case NVIC_PRIORITY_GROUP_1: + tempPrePri = 1; + tempSubPri = 3; + break; + + case NVIC_PRIORITY_GROUP_2: + tempPrePri = 2; + tempSubPri = 2; + break; + + case NVIC_PRIORITY_GROUP_3: + tempPrePri = 3; + tempSubPri = 1; + break; + + case NVIC_PRIORITY_GROUP_4: + tempPrePri = 4; + tempSubPri = 0; + break; + + default: + NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0); + tempPrePri = 0; + tempSubPri = 4; + break; + } + + tempPrePri = 4 - tempPrePri; + tempSubPri = 4 - tempSubPri; + tempPriority = preemptionPriority << tempPrePri; + tempPriority |= subPriority & (0x0f >> tempSubPri); + tempPriority <<= 4; + NVIC->IP[irq] = (uint8_t)tempPriority; + + /* enable the selected IRQ */ + NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); +} + +/*! + * @brief Disable NVIC request + * + * @param irq: the NVIC interrupt request, detailed in IRQn_Type + * + * @retval None + */ +void NVIC_DisableIRQRequest(IRQn_Type irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); +} + +/*! + * @brief Configs the vector table location and Offset. + * + * @param vectTab: specifies if the vector table is in RAM or FLASH memory + * This parameter can be one of the following values: + * @arg NVIC_VECT_TAB_RAM + * @arg NVIC_VECT_TAB_FLASH + * + * @param Offset Vector Table base offset field. This value must be a multiple of 0x200 + * + * @retval None + */ +void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset) +{ + SCB->VTOR = vectTab | (offset & (uint32_t)0x1FFFFF80); +} + +/*! + * @brief set the state of the low power mode + * + * @param lowPowerMode: the low power mode state + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * + * @retval None + */ +void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode) +{ + SCB->SCR |= lowPowerMode; +} + + +/*! + * @brief reset the state of the low power mode + * + * @param lowPowerMode: the low power mode state + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * + * @retval None + */ +void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode) +{ + SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode); +} + +/*! + * @brief Configures the SysTick clock source + * + * @param clkSource: specifies the SysTick clock source + * This parameter can be one of the following values: + * @arg SYSTICK_CLK_SOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLK_SOURCE_HCLK: AHB clock selected as SysTick clock source. + * + * @retval None + */ +void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource) +{ + if (clkSource == SYSTICK_CLK_SOURCE_HCLK) + { + SysTick->CTRL |= (uint32_t)BIT2; + } + else + { + SysTick->CTRL &= (uint32_t)(~BIT2); + } +} + +/**@} end of group MISC_Fuctions*/ +/**@} end of group MISC_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c new file mode 100644 index 0000000000..2398ebe0e4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c @@ -0,0 +1,249 @@ +/*! + * @file apm32f10x_pmu.c + * + * @brief This file provides all the PMU firmware functions. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_pmu.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup PMU_Driver PMU Driver + @{ +*/ + +/** @addtogroup PMU_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the PMU peripheral register. + * + * @param None + * + * @retval None + */ +void PMU_Reset(void) +{ + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); + RCM_DisableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); +} + +/*! + * @brief Enables access to the RTC and backup registers. + * + * @param None + * + * @retval None + */ +void PMU_EnableBackupAccess(void) +{ + PMU->CTRL_B.BPWEN = ENABLE ; +} + +/*! + * @brief Disables access to the RTC and backup registers. + * + * @param None + * + * @retval None + */ +void PMU_DisableBackupAccess(void) +{ + PMU->CTRL_B.BPWEN = DISABLE; +} + +/*! + * @brief Enables the Power Voltage Detector(PVD). + * + * @param None + * + * @retval None + */ +void PMU_EnablePVD(void) +{ + PMU->CTRL_B.PVDEN = ENABLE; +} + +/*! + * @brief Disables the Power Voltage Detector(PVD). + * + * @param None + * + * @retval None + */ +void PMU_DisablePVD(void) +{ + PMU->CTRL_B.PVDEN = DISABLE; +} + +/*! + * @brief Configure a voltage threshold detected by a power supply voltage detector (PVD). + * + * @param level��specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V + * @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V + * @arg PMU_PVD_LEVEL_2V4 : Config PVD detection level to 2.4V + * @arg PMU_PVD_LEVEL_2V5 : Config PVD detection level to 2.5V + * @arg PMU_PVD_LEVEL_2V6 : Config PVD detection level to 2.6V + * @arg PMU_PVD_LEVEL_2V7 : Config PVD detection level to 2.7V + * @arg PMU_PVD_LEVEL_2V8 : Config PVD detection level to 2.8V + * @arg PMU_PVD_LEVEL_2V9 : Config PVD detection level to 2.9V + * + * @retval None + */ +void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level) +{ + + /* Clear PLS[7:5] bits */ + PMU->CTRL_B.PLSEL = 0x0000; + /* Store the new value */ + PMU->CTRL_B.PLSEL = level; +} + +/*! + * @brief Enables the WakeUp Pin functionality. + * + * @param None + * + * @retval None + */ +void PMU_EnableWakeUpPin(void) +{ + PMU->CSTS_B.WKUPCFG = ENABLE ; +} + +/*! + * @brief Diaables the WakeUp Pin functionality. + * + * @param None + * + * @retval None + */ +void PMU_DisableWakeUpPin(void) +{ + PMU->CSTS_B.WKUPCFG = DISABLE ; +} + +/*! + * @brief Enters STOP mode. + * + * @param regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PMU_REGULATOR_ON : STOP mode with regulator ON + * @arg PMU_REGULATOR_LOWPOWER: STOP mode with regulator in low power mode + * + * @param entry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PMU_STOP_ENTRY_WFI: Enter STOP mode with WFI instruction + * @arg PMU_STOP_ENTRY_WFE: Enter STOP mode with WFE instruction + * + * @retval None + */ +void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry) +{ + /** Clear PLS and LPSM bits */ + PMU->CTRL_B.PDDSCFG = 0x00; + PMU->CTRL_B.LPDSCFG = 0x00; + /** Set LPSM bit according to PWR_Regulator value */ + PMU->CTRL_B.PDDSCFG = regulator; + /** Select STOP mode entry*/ + if(entry == PMU_STOP_ENTRY_WFI) + { + /** Request Wait For Interrupt */ + __WFI(); + } else + { + /** Request Wait For Event */ + __WFE(); + } + + /** Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)0x04); + +} + +/*! + * @brief Enters STANDBY mode. + * + * @param None + * + * @retval None + */ +void PMU_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PMU->CTRL_B.WUFLGCLR = BIT_SET; + /* Select STANDBY mode */ + PMU->CTRL_B.PDDSCFG = BIT_SET; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= (uint8_t )0x04; +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); + +} + +/*! + * @brief Read the specified PWR flag is set or not. + * + * @param flag��Reads the status of specifies the flag. + * This parameter can be one of the following values: + * @arg PMU_FLAG_WUE : Wake Up flag + * @arg PMU_FLAG_SB : StandBy flag + * @arg PMU_FLAG_PVDO: PVD Output flag + * + * @retval The new state of PMU_FLAG (SET or RESET). + */ +uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag) +{ + uint8_t BitStatus = BIT_RESET; + + if(flag == PMU_FLAG_WUE) + { + BitStatus = PMU->CSTS_B.WUEFLG; + } else if(flag == PMU_FLAG_SB) + { + BitStatus = PMU->CSTS_B.SBFLG; + } else if(flag == PMU_FLAG_PVDO) + { + BitStatus = PMU->CSTS_B.PVDOFLG; + } + return BitStatus; +} + +/*! + * @brief Clears the PWR's pending flags. + * + * @param flag��Clears the status of specifies the flag. + * This parameter can be one of the following values: + * @arg PMU_FLAG_WUE : Wake Up flag + * @arg PMU_FLAG_SB : StandBy flag + * + * @retval None + */ +void PMU_ClearStatusFlag(PMU_FLAG_T flag) +{ + if(flag == PMU_FLAG_WUE) + { + PMU->CTRL_B.WUFLGCLR = BIT_SET; + } else if(flag == PMU_FLAG_SB) + { + PMU->CTRL_B.SBFLGCLR = BIT_SET; + } +} + +/**@} end of group PMU_Fuctions*/ +/**@} end of group PMU_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c new file mode 100644 index 0000000000..5706b95e1a --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c @@ -0,0 +1,594 @@ +/*! + * @file qpm32f10x_qspi.c + * + * @brief This file contains all the functions for the QSPI peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_qspi.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset QSPI peripheral registers to their default values + * + * @param None + * + * @retval None + */ +void QSPI_Reset(void) +{ + volatile uint32_t dummy = 0; + + QSPI->IOSW = QSPI_IOSW_RESET_VALUE; + QSPI->SSIEN = QSPI_SSIEN_RESET_VALUE; + QSPI->INTEN = QSPI_INTEN_RESET_VALUE; + dummy = QSPI->ICF; + QSPI->CTRL1 = QSPI_CTRL1_RESET_VALUE; + QSPI->CTRL2 = QSPI_CTRL2_RESET_VALUE; + QSPI->CTRL3 = QSPI_CTRL3_RESET_VALUE; + QSPI->SLAEN = QSPI_SLAEN_RESET_VALUE; + QSPI->BR = QSPI_BR_RESET_VALUE; + QSPI->TFL = QSPI_TFL_RESET_VALUE; + QSPI->RFL = QSPI_RFL_RESET_VALUE; + QSPI->TFTL = QSPI_TFTL_RESET_VALUE; + QSPI->RFTL = QSPI_RFTL_RESET_VALUE; + QSPI->STS = QSPI_STS_RESET_VALUE; + QSPI->RSD = QSPI_RSD_RESET_VALUE; +} + +/*! + * @brief Config the QSPI peripheral according to the specified parameters in the qspiConfig + * + * @param qspiConfig: Pointer to a QSPI_Config_T structure that contains the configuration information + * + * @retval None + */ +void QSPI_Config(QSPI_Config_T * qspiConfig) +{ + QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase; + QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity; + QSPI->CTRL1_B.FRF = qspiConfig->frameFormat; + QSPI->CTRL1_B.DFS = qspiConfig->dataFrameSize;; + QSPI->CTRL1_B.SSTEN = qspiConfig->selectSlaveToggle; + + QSPI->BR = qspiConfig->clockDiv; + +} + +/*! + * @brief Fills each qspiConfig member with its default value + * + * @param qspiConfig: Pointer to a QSPI_Config_T structure which will be initialized + * + * @retval None + */ +void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig) +{ + qspiConfig->clockPhase = QSPI_CLKPHA_2EDGE; + qspiConfig->clockPolarity = QSPI_CLKPOL_LOW; + qspiConfig->clockDiv = 0; + + qspiConfig->frameFormat = QSPI_FRF_STANDARD; + qspiConfig->dataFrameSize = QSPI_DFS_8BIT; + qspiConfig->selectSlaveToggle = QSPI_SST_DISABLE; +} + +/*! + * @brief Configs frame number + * + * @param num: Configs a 16bit frame number + * + * @retval None + */ +void QSPI_ConfigFrameNum(uint16_t num) +{ + QSPI->CTRL2_B.NDF = num; +} + +/*! + * @brief Configs data frame size + * + * @param dfs: Specifies the data frame size + * The parameter can be one of following values: + * @arg QSPI_DFS_4BIT : Specifies data frame size to 4bit + * @arg QSPI_DFS_5BIT : Specifies data frame size to 5bit + * @arg QSPI_DFS_6BIT : Specifies data frame size to 6bit + * @arg QSPI_DFS_7BIT : Specifies data frame size to 7bit + * @arg QSPI_DFS_8BIT : Specifies data frame size to 8bit + * @arg QSPI_DFS_9BIT : Specifies data frame size to 9bit + * @arg QSPI_DFS_10BIT : Specifies data frame size to 10bit + * @arg QSPI_DFS_11BIT : Specifies data frame size to 11bit + * @arg QSPI_DFS_12BIT : Specifies data frame size to 12bit + * @arg QSPI_DFS_13BIT : Specifies data frame size to 13bit + * @arg QSPI_DFS_14BIT : Specifies data frame size to 14bit + * @arg QSPI_DFS_15BIT : Specifies data frame size to 15bit + * @arg QSPI_DFS_16BIT : Specifies data frame size to 16bit + * @arg QSPI_DFS_17BIT : Specifies data frame size to 17bit + * @arg QSPI_DFS_18BIT : Specifies data frame size to 18bit + * @arg QSPI_DFS_19BIT : Specifies data frame size to 19bit + * @arg QSPI_DFS_20BIT : Specifies data frame size to 20bit + * @arg QSPI_DFS_21BIT : Specifies data frame size to 21bit + * @arg QSPI_DFS_22BIT : Specifies data frame size to 22bit + * @arg QSPI_DFS_23BIT : Specifies data frame size to 23bit + * @arg QSPI_DFS_24BIT : Specifies data frame size to 24bit + * @arg QSPI_DFS_25BIT : Specifies data frame size to 25bit + * @arg QSPI_DFS_26BIT : Specifies data frame size to 26bit + * @arg QSPI_DFS_27BIT : Specifies data frame size to 27bit + * @arg QSPI_DFS_28BIT : Specifies data frame size to 28bit + * @arg QSPI_DFS_29BIT : Specifies data frame size to 29bit + * @arg QSPI_DFS_30BIT : Specifies data frame size to 30bit + * @arg QSPI_DFS_31BIT : Specifies data frame size to 31bit + * @arg QSPI_DFS_32BIT : Specifies data frame size to 32bit + * + * @retval None + */ +void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs) +{ + QSPI->CTRL1_B.DFS = dfs; +} + +/*! + * @brief Configs frame format + * + * @param frameFormat + * + * @retval None + */ +void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat) +{ + QSPI->CTRL1_B.FRF = frameFormat; +} + +/*! + * @brief Enable QSPI + * + * @param None + * + * @retval None + */ +void QSPI_Enable(void) +{ + QSPI->SSIEN_B.EN = BIT_SET; +} + +/*! + * @brief Disable QSPI + * + * @param None + * + * @retval None + */ +void QSPI_Disable(void) +{ + QSPI->SSIEN_B.EN = BIT_RESET; +} + +/*! + * @brief Read Tx FIFO number of data + * + * @param None + * + * @retval None + */ +uint8_t QSPI_ReadTxFifoDataNum(void) +{ + return (uint8_t)QSPI->TFL_B.TFL; +} + +/*! + * @brief Read Rx FIFO number of data + * + * @param None + * + * @retval Returns Rx FIFO number of data + */ +uint8_t QSPI_ReadRxFifoDataNum(void) +{ + return (uint8_t)QSPI->RFL_B.RFL; +} + +/*! + * @brief Configs rx FIFO threshold + * + * @param threshold: Speicifes rx FIFO threshold with a 3bit value + * + * @retval None + */ +void QSPI_ConfigRxFifoThreshold(uint8_t threshold) +{ + QSPI->RFTL_B.RFT = threshold; +} + +/*! + * @brief Congfigs Tx FIFO threshold + * + * @param threshold: Speicifes Tx FIFO threshold with a 3bit value + * + * @retval None + */ +void QSPI_ConfigTxFifoThreshold(uint8_t threshold) +{ + QSPI->TFTL_B.TFTH = threshold; +} + +/*! + * @brief Congfigs Tx FIFO empty threshold + * + * @param threshold: Speicifes Tx FIFO empty threshold with a 3bit value + * + * @retval None + */ +void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold) +{ + QSPI->TFTL_B.TFT = threshold; +} + +/*! + * @brief Configs RX sample edge + * + * @param rse: Specifies the sample edge + * The parameter can be one of following values: + * @arg QSPI_RSE_RISING : rising edge sample + * @arg QSPI_RSE_FALLING: falling edge sample + * + * @retval None + */ +void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse) +{ + QSPI->RSD_B.RSE = rse; +} + +/*! + * @brief Set RX sample delay + * + * @param delay: Specifies the sample delay with a 8-bit value + * + * @retval None + */ +void QSPI_ConfigRxSampleDelay(uint8_t delay) +{ + QSPI->RSD_B.RSD = delay; +} + +/*! + * @brief Clock stretch enable + * + * @param None + * + * @retval None + */ +void QSPI_EnableClockStretch(void) +{ + QSPI->CTRL3_B.CSEN = BIT_SET; +} + +/*! + * @brief Clock stretch disable + * + * @param None + * + * @retval None + */ +void QSPI_DisableClockStretch(void) +{ + QSPI->CTRL3_B.CSEN = BIT_RESET; +} + +/*! + * @brief Configs instruction length + * + * @param len: Specifies the length of instruction + * The parameter can be one of following values: + * @arg QSPI_INST_LEN_0 : no instruction + * @arg QSPI_INST_LEN_4BIT : 4-bit instruction + * @arg QSPI_INST_LEN_8BIT : 8-bit instruction + * @arg QSPI_INST_LEN_16BIT : 16-bit instruction + * + * @retval None + */ +void QSPI_ConfigInstLen(QSPI_INST_LEN_T len) +{ + QSPI->CTRL3_B.INSLEN = len; +} + +/*! + * @brief Configs address length + * + * @param len: Specifies the address length + * The parameter can be one of following values: + * @arg QSPI_ADDR_LEN_0 : no address + * @arg QSPI_ADDR_LEN_4BIT : 4-bit address length + * @arg QSPI_ADDR_LEN_8BIT, : 8-bit address length + * @arg QSPI_ADDR_LEN_12BIT : 12-bit address length + * @arg QSPI_ADDR_LEN_16BIT : 16-bit address length + * @arg QSPI_ADDR_LEN_20BIT : 20-bit address length + * @arg QSPI_ADDR_LEN_24BIT : 24-bit address length + * @arg QSPI_ADDR_LEN_28BIT : 28-bit address length + * @arg QSPI_ADDR_LEN_32BIT : 32-bit address length + * @arg QSPI_ADDR_LEN_36BIT : 36-bit address length + * @arg QSPI_ADDR_LEN_40BIT : 40-bit address length + * @arg QSPI_ADDR_LEN_44BIT : 44-bit address length + * @arg QSPI_ADDR_LEN_48BIT : 48-bit address length + * @arg QSPI_ADDR_LEN_52BIT : 52-bit address length + * @arg QSPI_ADDR_LEN_56BIT : 56-bit address length + * @arg QSPI_ADDR_LEN_60BIT : 60-bit address length + * + * @retval None + */ +void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len) +{ + QSPI->CTRL3_B.ADDRLEN = len; +} + +/*! + * @brief Configs instruction and address type + * + * @param type: Specifies the instruction and address type + * The parameter can be one of following values: + * @arg QSPI_INST_ADDR_TYPE_STANDARD : Tx instruction in standard SPI mode, + * Tx address in standard SPI mode + * @arg QSPI_INST_TYPE_STANDARD : Tx instruction in standard SPI mode, + * Tx address in mode of SPI_FRF + * @arg QSPI_INST_ADDR_TYPE_FRF : Tx instruction in mode of SPI_FRF, + * Tx address in mode of SPI_FRF + * + * @retval None + */ +void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type) +{ + QSPI->CTRL3_B.IAT = type; +} + +/*! + * @brief Configs wait cycle number + * + * @param cycle: Specifies the wait cycle number with a 5-bit value + * + * @retval None + */ +void QSPI_ConfigWaitCycle(uint8_t cycle) +{ + QSPI->CTRL3_B.WAITCYC = cycle; +} + +/*! + * @brief Open QSPI GPIO + * + * @param None + * + * @retval None + */ +void QSPI_OpenIO(void) +{ + QSPI->IOSW_B.IOSW = BIT_SET; +} + +/*! + * @brief Close QSPI GPIO + * + * @param None + * + * @retval None + */ +void QSPI_CloseIO(void) +{ + QSPI->IOSW_B.IOSW = BIT_RESET; +} + +/*! + * @brief Set transmission mode + * + * @param mode: Specifies the transmission mode + * The parameter can be one of following values: + * @arg QSPI_TRANS_MODE_TX_RX : TX and RX mode + * @arg QSPI_TRANS_MODE_TX : TX mode only + * @arg QSPI_TRANS_MODE_RX : RX mode only + * @arg QSPI_TRANS_MODE_EEPROM_READ : EEPROM read mode + * + * @retval None + */ +void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode) +{ + QSPI->CTRL1_B.TXMODE = mode; +} + +/*! + * @brief Transmit data + * + * @param data: Data to be transmited + * + * @retval None + */ +void QSPI_TxData(uint32_t data) +{ + QSPI->DATA = data; +} + +/*! + * @brief Returns the most recent received data + * + * @param None + * + * @retval The received data + */ +uint32_t QSPI_RxData(void) +{ + return (uint32_t)QSPI->DATA; +} + +/*! + * @brief Enable Slave + * + * @param None + * + * @retval None + */ +void QSPI_EnableSlave(void) +{ + QSPI->SLAEN_B.SLAEN = BIT_SET; +} + +/*! + * @brief Disable slave + * + * @param None + * + * @retval None + */ +void QSPI_DisableSlave(void) +{ + QSPI->SLAEN_B.SLAEN = BIT_RESET; +} + +/*! + * @brief Enable the specified QSPI interrupts + * + * @param interrupt: Specifies the QSPI interrupt sources + * The parameter can be combination of following values: + * @arg QSPI_INT_TFE: TX FIFO empty interrupt + * @arg QSPI_INT_TFO: TX FIFO overflow interrupt + * @arg QSPI_INT_RFU: RX FIFO underflow interrupt + * @arg QSPI_INT_RFO: RX FIFO overflow interrupt + * @arg QSPI_INT_RFF: RX FIFO full interrupt + * @arg QSPI_INT_MST: Master interrupt + * + * @retval None + */ +void QSPI_EnableInterrupt(uint32_t interrupt) +{ + QSPI->INTEN |= interrupt; +} + +/*! + * @brief Disable the specified QSPI interrupts + * + * @param interrupt: Specifies the QSPI interrupt sources + * The parameter can be combination of following values: + * @arg QSPI_INT_TFE: TX FIFO empty interrupt + * @arg QSPI_INT_TFO: TX FIFO overflow interrupt + * @arg QSPI_INT_RFU: RX FIFO underflow interrupt + * @arg QSPI_INT_RFO: RX FIFO overflow interrupt + * @arg QSPI_INT_RFF: RX FIFO full interrupt + * @arg QSPI_INT_MST: Master interrupt + * + * @retval None + */ +void QSPI_DisableInterrupt(uint32_t interrupt) +{ + QSPI->INTEN &= (uint32_t)~interrupt; +} + +/*! + * @brief Read specified QSPI flag + * + * @param flag: Specifies the flag to be checked + * The parameter can be one of following values: + * @arg QSPI_FLAG_BUSY: Busy flag + * @arg QSPI_FLAG_TFNF: TX FIFO not full flag + * @arg QSPI_FLAG_TFE: TX FIFO empty flag + * @arg QSPI_FLAG_RFNE: RX FIFO not empty flag + * @arg QSPI_FLAG_RFF: RX FIFO full flag + * @arg QSPI_FLAG_DCE: Data collision error + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag) +{ + uint8_t ret = RESET; + + ret = QSPI->STS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Clear specified QSPI flag + * + * @param None + * + * @retval None + * + * @note This funtion only clear Data collision error flag(QSPI_FLAG_DCE) + */ +void QSPI_ClearStatusFlag(void) +{ + volatile uint32_t dummy = 0; + + dummy = QSPI->STS; +} + +/*! + * @brief Read specified QSPI interrupt flag + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg QSPI_INT_FLAG_TFE: TX FIFO empty interrupt flag + * @arg QSPI_INT_FLAG_TFO: TX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_RFU: RX FIFO underflow interrupt flag + * @arg QSPI_INT_FLAG_RFO: RX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_RFF: RX FIFO full interrupt flag + * @arg QSPI_INT_FLAG_MST: Master interrupt flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag) +{ + uint8_t ret = RESET; + + ret = QSPI->ISTS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Clear specified QSPI interrupt flag + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg QSPI_INT_FLAG_TFO: TX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_RFU: RX FIFO underflow interrupt flag + * @arg QSPI_INT_FLAG_RFO: RX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_MST: Master interrupt flag + * + * @retval None + */ +void QSPI_ClearIntFlag(uint32_t flag) +{ + volatile uint32_t dummy = 0; + + if(flag & QSPI_INT_FLAG_TFO) + { + dummy = QSPI->TFOIC; + } + else if(flag & QSPI_INT_FLAG_RFO) + { + dummy = QSPI->RFOIC; + } + else if(flag & QSPI_INT_FLAG_RFU) + { + dummy = QSPI->RFUIC; + } + else if(flag & QSPI_INT_FLAG_MST) + { + dummy = QSPI->MIC; + } +} + +/**@} end of group QSPI_Fuctions*/ +/**@} end of group QSPI_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c new file mode 100644 index 0000000000..71151193e2 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c @@ -0,0 +1,1078 @@ +/*! + * @file apm32f10x_rcm.c + * + * @brief This file provides all the RCM firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RCM_Driver RCM Driver + @{ +*/ + +/** @addtogroup RCM_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Resets the clock configuration to the default state + * + * @param None + * + * @retval None + */ +void RCM_Reset(void) +{ + /** Open HSI clock */ + RCM->CTRL_B.HSIEN = BIT_SET; + /** Config HSI to system clock and Reset AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ + RCM->CFG &= (uint32_t)0xF8FF0000; + /** Reset HSEEN, CSSEN and PLLEN bits */ + RCM->CTRL &= (uint32_t)0xFEF6FFFF; + /** Reset HSEBCFG bit */ + RCM->CTRL_B.HSEBCFG = BIT_RESET; + /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ + RCM->CFG &= (uint32_t)0xFF00FFFF; + /** Disable all interrupts and clear pending bits */ + RCM->INT = 0x009F0000; +} + +/*! + * @brief Configs the HSE oscillator + * + * @param state: state of the HSE + * This parameter can be one of the following values: + * @arg RCM_HSE_CLOSE: Turn off the HSE oscillator + * @arg RCM_HSE_OPEN: Turn on the HSE oscillator + * @arg RCM_HSE_BYPASS: HSE oscillator bypassed with external clock + * + * @retval None + * + * @note When HSE is not used directly or through the PLL as system clock, it can be stopped. + */ +void RCM_ConfigHSE(RCM_HSE_T state) +{ + /** Reset HSEEN bit */ + RCM->CTRL_B.HSEEN = BIT_RESET; + + /** Reset HSEBCFG bit */ + RCM->CTRL_B.HSEBCFG = BIT_RESET; + + if (state == RCM_HSE_OPEN) + { + RCM->CTRL_B.HSEEN = BIT_SET; + } + else if (state == RCM_HSE_BYPASS) + { + RCM->CTRL_B.HSEBCFG = BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; + } +} + +/*! + * @brief Waits for HSE to be ready + * + * @param None + * + * @retval SUCCESS: HSE oscillator is ready + * ERROR : HSE oscillator is not ready + */ +uint8_t RCM_WaitHSEReady(void) +{ + __IO uint32_t cnt; + + for (cnt = 0; cnt < HSE_STARTUP_TIMEOUT; cnt++) + { + if (RCM->CTRL_B.HSERDYFLG == BIT_SET) + { + return SUCCESS; + } + } + + return ERROR; +} + +/*! + * @brief Set HSI trimming value + * + * @param HSITrim: HSI trimming value + * This parameter must be a number between 0 and 0x1F. + * + * @retval None + */ +void RCM_SetHSITrim(uint8_t HSITrim) +{ + RCM->CTRL_B.HSITRIM = HSITrim; +} + +/*! + * @brief Enable the HSI + * + * @param None + * + * @retval None + */ +void RCM_EnableHSI(void) +{ + RCM->CTRL_B.HSIEN = BIT_SET; +} + +/*! + * @brief Disable the HSI + * + * @param None + * + * @retval None + * + * @note When HSI is not used directly or through the PLL as system clock, it can be stopped. + */ + +void RCM_DisableHSI(void) +{ + RCM->CTRL_B.HSIEN = BIT_RESET; +} + +/*! + * @brief Configures the External Low Speed oscillator (LSE) + * + * @param state : Specifies the new state of the LSE + * + * @retval None + * + * @note + */ +void RCM_ConfigLSE(RCM_LSE_T state) +{ + RCM->BDCTRL_B.LSEEN = BIT_RESET; + RCM->BDCTRL_B.LSEBCFG = BIT_RESET; + + if (state == RCM_LSE_OPEN) + { + RCM->BDCTRL_B.LSEEN = BIT_SET; + } + else if (state == RCM_LSE_BYPASS) + { + RCM->BDCTRL_B.LSEBCFG = BIT_SET; + RCM->BDCTRL_B.LSEEN = BIT_SET; + } +} + +/*! + * @brief Enables the Internal Low Speed oscillator (LSI) + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_EnableLSI(void) +{ + RCM->CSTS_B.LSIEN = BIT_SET; +} + +/*! + * @brief Disables the Internal Low Speed oscillator (LSI) + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_DisableLSI(void) +{ + RCM->CSTS_B.LSIEN = BIT_RESET; +} + +/*! + * @brief Configs the PLL clock source and multiplication factor + * + * @param pllSelect: PLL entry clock source select + * This parameter can be one of the following values: + * @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source + * @arg RCM_PLLSEL_HSE: HSE clock selected as PLL clock source + * @arg RCM_PLLSEL_HSE_DIV2: HSE clock divided by 2 selected as PLL clock source + * + * @param pllMf: PLL multiplication factor + * This parameter can be RCM_PLLMF_x where x can be a value from 2 to 16. + * + * @retval None + * + * @note PLL should be disabled while use this function. + */ +void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf) +{ + RCM->CFG_B.PLLMULCFG = pllMf; + RCM->CFG_B.PLLSRCSEL = pllSelect & 0x01; + RCM->CFG_B.PLLHSEPSC = (pllSelect >> 1) & 0x01; +} + +/*! + * @brief Enables the PLL + * + * @param None + * + * @retval None + */ +void RCM_EnablePLL(void) +{ + RCM->CTRL_B.PLLEN = BIT_SET; +} + +/*! +* @brief Disable the PLL +* +* @param None +* +* @retval None +* +* @note When PLL is not used as system clock, it can be stopped. +*/ +void RCM_DisablePLL(void) +{ + RCM->CTRL_B.PLLEN = BIT_RESET; +} + +/*! + * @brief Enable the Clock Security System + * + * @param None + * + * @retval None + */ +void RCM_EnableCSS(void) +{ + RCM->CTRL_B.CSSEN = BIT_SET; +} + +/*! + * @brief Disable the Clock Security System + * + * @param None + * + * @retval None + */ +void RCM_DisableCSS(void) +{ + RCM->CTRL_B.CSSEN = BIT_RESET; +} + +/*! + * @brief Selects the MCO pin clock ouput source + * + * @param mcoClock: specifies the clock source to output + * This parameter can be one of the following values: + * @arg RCM_MCOCLK_NO_CLOCK : No clock selected. + * @arg RCM_MCOCLK_SYSCLK : HSI14 oscillator clock selected. + * @arg RCM_MCOCLK_HSI : LSI oscillator clock selected. + * @arg RCM_MCOCLK_HSE : LSE oscillator clock selected. + * @arg RCM_MCOCLK_PLLCLK_DIV_2 : System clock selected. + * + * @retval None + * + * @note + */ +void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock) +{ + RCM->CFG_B.MCOSEL = mcoClock; +} + +/*! + * @brief Configures the system clock source + * + * @param sysClkSelect: specifies the clock source used as system clock + * This parameter can be one of the following values: + * @arg RCM_SYSCLK_SEL_HSI: HSI is selected as system clock source + * @arg RCM_SYSCLK_SEL_HSE: HSE is selected as system clock source + * @arg RCM_SYSCLK_SEL_PLL: PLL is selected as system clock source + * + * @retva None + */ +void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect) +{ + RCM->CFG_B.SCLKSW = sysClkSelect; +} + +/*! + * @brief Returns the clock source which is used as system clock + * + * @param None + * + * @retval The clock source used as system clock + */ +RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void) +{ + RCM_SYSCLK_SEL_T sysClock; + + sysClock = (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSWSTS; + + return sysClock; +} + +/*! + * @brief Configs the AHB clock prescaler. + * + * @param AHBDiv : Specifies the AHB clock prescaler from the system clock. + * This parameter can be one of the following values: + * @arg RCM_AHB_DIV_1 : HCLK = SYSCLK + * @arg RCM_AHB_DIV_2 : HCLK = SYSCLK / 2 + * @arg RCM_AHB_DIV_4 : HCLK = SYSCLK / 4 + * @arg RCM_AHB_DIV_8 : HCLK = SYSCLK / 8 + * @arg RCM_AHB_DIV_16 : HCLK = SYSCLK / 16 + * @arg RCM_AHB_DIV_64 : HCLK = SYSCLK / 64 + * @arg RCM_AHB_DIV_128 : HCLK = SYSCLK / 128 + * @arg RCM_AHB_DIV_256 : HCLK = SYSCLK / 256 + * @arg RCM_AHB_DIV_512 : HCLK = SYSCLK / 512 + * + * @retval None + * + * @note + */ +void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv) +{ + RCM->CFG_B.AHBPSC = AHBDiv; +} + +/*! + * @brief Configs the APB1 clock prescaler. + * + * @param APB1Div: Specifies the APB1 clock prescaler from the AHB clock. + * This parameter can be one of the following values: + * @arg RCM_APB_DIV_1 : PCLK1 = HCLK + * @arg RCM_APB_DIV_2 : PCLK1 = HCLK / 2 + * @arg RCM_APB_DIV_4 : PCLK1 = HCLK / 4 + * @arg RCM_APB_DIV_8 : PCLK1 = HCLK / 8 + * @arg RCM_APB_DIV_16 : PCLK1 = HCLK / 16 + * + * @retval None + */ +void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div) +{ + RCM->CFG_B.APB1PSC = APB1Div; +} + +/*! + * @brief Configs the APB2 clock prescaler + * + * @param APB2Div: Specifies the APB2 clock prescaler from the AHB clock. + * This parameter can be one of the following values: + * @arg RCM_APB_DIV_1 : PCLK2 = HCLK + * @arg RCM_APB_DIV_2 : PCLK2 = HCLK / 2 + * @arg RCM_APB_DIV_4 : PCLK2 = HCLK / 4 + * @arg RCM_APB_DIV_8 : PCLK2 = HCLK / 8 + * @arg RCM_APB_DIV_16 : PCLK2 = HCLK / 16 + * + * @retval None + */ +void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div) +{ + RCM->CFG_B.APB2PSC = APB2Div; +} + +/*! + * @brief Configs the USB clock prescaler + * + * @param USBDiv: Specifies the USB clock prescaler from the PLL clock. + * This parameter can be one of the following values: + * @arg RCM_USB_DIV_1_5 : USBCLK = PLL clock /1.5 + * @arg RCM_USB_DIV_1 : USBCLK = PLL clock + * @arg RCM_USB_DIV_2 : USBCLK = PLL clock / 2 + * @arg RCM_USB_DIV_2_5 : USBCLK = PLL clock / 2.5 (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv) +{ + RCM->CFG_B.USBDPSC = USBDiv; +} + +/*! + * @brief Configs the FPU clock prescaler + * + * @param FPUDiv: Specifies the FPU clock prescaler from the AHB clock. + * This parameter can be one of the following values: + * @arg RCM_FPU_DIV_1 : FPUCLK = HCLK + * @arg RCM_FPU_DIV_2 : FPUCLK = HCLK /2 + * + * @retval None + */ +void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv) +{ + RCM->CFG_B.FPUPSC = FPUDiv; +} + +/*! + * @brief Configs the ADC clock prescaler + * + * @param ADCDiv : Specifies the ADC clock prescaler from the APB2 clock. + * This parameter can be one of the following values: + * @arg RCM_PCLK2_DIV_2: ADCCLK = PCLK2 / 2 + * @arg RCM_PCLK2_DIV_4: ADCCLK = PCLK2 / 4 + * @arg RCM_PCLK2_DIV_6: ADCCLK = PCLK2 / 6 + * @arg RCM_PCLK2_DIV_8: ADCCLK = PCLK2 / 8 + * + * @retval None + */ +void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv) +{ + RCM->CFG_B.ADCPSC = ADCDiv; +} + +/*! + * @brief Configures the RTC clock source + * + * @param rtcClkSelect : specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCM_RTCCLK_LSE : RTCCLK = LSE clock + * @arg RCM_RTCCLK_LSI : RTCCLK = LSI clock + * @arg RCM_RTCCLK_HSE_DIV_128: RTCCLK = HSE clock / 128 + * + * @retval None + * + * @note Once the RTC clock is configed it can't be changed unless reset the Backup domain. + */ +void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect) +{ + RCM->BDCTRL_B.RTCSRCSEL = rtcClkSelect; +} + +/*! + * @brief Enables the RTC clock + * + * @param None + * + * @retval None + */ +void RCM_EnableRTCCLK(void) +{ + RCM->BDCTRL_B.RTCCLKEN = BIT_SET; +} + +/*! + * @brief Disables the RTC clock + * + * @param None + * + * @retval None + */ +void RCM_DisableRTCCLK(void) +{ + RCM->BDCTRL_B.RTCCLKEN = BIT_RESET; +} + +/*! + * @brief Reads the frequency of SYSCLK + * + * @param None + * + * @retval Return the frequency of SYSCLK + */ +uint32_t RCM_ReadSYSCLKFreq(void) +{ + uint32_t sysClock, pllMull, pllSource; + + /** get sys clock */ + sysClock = RCM->CFG_B.SCLKSW; + + switch (sysClock) + { + /** sys clock is HSI */ + case RCM_SYSCLK_SEL_HSI: + sysClock = HSI_VALUE; + break; + + /** sys clock is HSE */ + case RCM_SYSCLK_SEL_HSE: + sysClock = HSE_VALUE; + break; + + /** sys clock is PLL */ + case RCM_SYSCLK_SEL_PLL: + pllMull = RCM->CFG_B.PLLMULCFG + 2; + pllSource = RCM->CFG_B.PLLSRCSEL; + + /** PLL entry clock source is HSE */ + if (pllSource == BIT_SET) + { + sysClock = HSE_VALUE * pllMull; + + /** HSE clock divided by 2 */ + if (pllSource == RCM->CFG_B.PLLHSEPSC) + { + sysClock >>= 1; + } + } + /** PLL entry clock source is HSI/2 */ + else + { + sysClock = (HSI_VALUE >> 1) * pllMull; + } + + break; + + default: + sysClock = HSI_VALUE; + break; + } + + return sysClock; +} + +/*! + * @brief Reads the frequency of HCLK(AHB) + * + * @param None + * + * @retval Return the frequency of HCLK + */ +uint32_t RCM_ReadHCLKFreq(void) +{ + uint32_t divider; + uint32_t sysClk, hclk; + uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sysClk = RCM_ReadSYSCLKFreq(); + divider = AHBPrescTable[RCM->CFG_B.AHBPSC]; + hclk = sysClk >> divider; + + return hclk; +} + +/*! + * @brief Reads the frequency of PCLK1 And PCLK2 + * + * @param PCLK1 : Return the frequency of PCLK1 + * + * @param PCLK1 : Return the frequency of PCLK2 + * + * @retval None + */ +void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2) +{ + uint32_t hclk, divider; + uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + hclk = RCM_ReadHCLKFreq(); + + if (PCLK1) + { + divider = APBPrescTable[RCM->CFG_B.APB1PSC]; + *PCLK1 = hclk >> divider; + } + + if (PCLK2) + { + divider = APBPrescTable[RCM->CFG_B.APB2PSC]; + *PCLK2 = hclk >> divider; + } +} + +/*! + * @brief Reads the frequency of ADCCLK + * + * @param None + * + * @retval Return the frequency of ADCCLK + */ +uint32_t RCM_ReadADCCLKFreq(void) +{ + uint32_t adcClk, pclk2, divider; + uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + + RCM_ReadPCLKFreq(NULL, &pclk2); + + /** Get ADC CLK */ + divider = ADCPrescTable[RCM->CFG_B.ADCPSC]; + adcClk = pclk2 / divider; + + return adcClk; +} + +/*! + * @brief Enables AHB peripheral clock. + * + * @param AHBPeriph : Enable the specifies clock of AHB peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_DMA1 : Enable DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2 : Enable DMA2 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SRAM : Enable SRAM clock + * @arg RCM_AHB_PERIPH_FPU : Enable FPU clock + * @arg RCM_AHB_PERIPH_FMC : Enable FMC clock + * @arg RCM_AHB_PERIPH_QSPI : Enable QSPI clock + * @arg RCM_AHB_PERIPH_CRC : Enable CRC clock + * @arg RCM_AHB_PERIPH_EMMC : Enable EMMC clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SDIO : Enable SDIO clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph) +{ + RCM->AHBCLKEN |= AHBPeriph; +} + +/*! + * @brief Disable AHB peripheral clock. + * + * @param AHBPeriph : Disable the specifies clock of AHB peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_DMA1 : Disable DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2 : Disable DMA2 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SRAM : Disable SRAM clock + * @arg RCM_AHB_PERIPH_FPU : Disable FPU clock + * @arg RCM_AHB_PERIPH_FMC : Disable FMC clock + * @arg RCM_AHB_PERIPH_QSPI : Disable QSPI clock + * @arg RCM_AHB_PERIPH_CRC : Disable CRC clock + * @arg RCM_AHB_PERIPH_EMMC : Disable EMMC clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SDIO : Disable SDIO clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph) +{ + RCM->AHBCLKEN &= (uint32_t)~AHBPeriph; +} + +/*! + * @brief Enable the High Speed APB (APB2) peripheral clock + * + * @param APB2Periph : Enable specifies clock of the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Enable AFIO clock + * @arg RCM_APB2_PERIPH_GPIOA : Enable GPIOA clock + * @arg RCM_APB2_PERIPH_GPIOB : Enable GPIOB clock + * @arg RCM_APB2_PERIPH_GPIOC : Enable GPIOC clock + * @arg RCM_APB2_PERIPH_GPIOD : Enable GPIOD clock + * @arg RCM_APB2_PERIPH_GPIOE : Enable GPIOE clock + * @arg RCM_APB2_PERIPH_GPIOF : Enable GPIOF clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Enable GPIOG clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Enable ADC1 clock + * @arg RCM_APB2_PERIPH_ADC2 : Enable ADC2 clock + * @arg RCM_APB2_PERIPH_TMR1 : Enable TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1 : Enable SPI1 clock + * @arg RCM_APB2_PERIPH_TMR8 : Enable TMR8 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Enable USART1 clock + * @arg RCM_APB2_PERIPH_ADC3 : Enable ADC3 clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph) +{ + RCM->APB2CLKEN |= APB2Periph; +} + +/*! + * @brief Disable the High Speed APB (APB2) peripheral clock + * + * @param APB2Periph : Disable specifies clock of the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Disable AFIO clock + * @arg RCM_APB2_PERIPH_GPIOA : Disable GPIOA clock + * @arg RCM_APB2_PERIPH_GPIOB : Disable GPIOB clock + * @arg RCM_APB2_PERIPH_GPIOC : Disable GPIOC clock + * @arg RCM_APB2_PERIPH_GPIOD : Disable GPIOD clock + * @arg RCM_APB2_PERIPH_GPIOE : Disable GPIOE clock + * @arg RCM_APB2_PERIPH_GPIOF : Disable GPIOF clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Disable GPIOG clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Disable ADC1 clock + * @arg RCM_APB2_PERIPH_ADC2 : Disable ADC2 clock + * @arg RCM_APB2_PERIPH_TMR1 : Disable TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1 : Disable SPI1 clock + * @arg RCM_APB2_PERIPH_TMR8 : Disable TMR8 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Disable USART1 clock + * @arg RCM_APB2_PERIPH_ADC3 : Disable ADC3 clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph) +{ + RCM->APB2CLKEN &= (uint32_t)~APB2Periph; +} + +/*! + * @brief Enable the Low Speed APB (APB1) peripheral clock + * + * @param APB1Periph : Enable specifies clock of the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 clock + * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 clock + * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 clock + * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT clock + * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 clock + * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 clock + * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 clock + * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 clock + * @arg RCM_APB1_PERIPH_USB : Enable USB clock + * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 clock + * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 clock (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Enable BAKR clock + * @arg RCM_APB1_PERIPH_PMU : Enable PMU clock + * @arg RCM_APB1_PERIPH_DAC : Enable DAC clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph) +{ + RCM->APB1CLKEN |= APB1Periph; +} + +/*! + * @brief Disable the Low Speed APB (APB1) peripheral clock + * + * @param APB1Periph : Disable specifies clock of the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 clock + * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 clock + * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 clock + * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT clock + * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 clock + * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 clock + * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 clock + * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 clock + * @arg RCM_APB1_PERIPH_USB : Disable USB clock + * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 clock + * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 clock (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Disable BAKR clock + * @arg RCM_APB1_PERIPH_PMU : Disable PMU clock + * @arg RCM_APB1_PERIPH_DAC : Disable DAC clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph) +{ + RCM->APB1CLKEN &= (uint32_t)~APB1Periph; +} + +/*! + * @brief Enable High Speed APB (APB2) peripheral reset + * + * @param APB2Periph : Enable specifies APB2 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Enable AFIO reset + * @arg RCM_APB2_PERIPH_GPIOA : Enable GPIOA reset + * @arg RCM_APB2_PERIPH_GPIOB : Enable GPIOB reset + * @arg RCM_APB2_PERIPH_GPIOC : Enable GPIOC reset + * @arg RCM_APB2_PERIPH_GPIOD : Enable GPIOD reset + * @arg RCM_APB2_PERIPH_GPIOE : Enable GPIOE reset + * @arg RCM_APB2_PERIPH_GPIOF : Enable GPIOF reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Enable GPIOG reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Enable ADC1 reset + * @arg RCM_APB2_PERIPH_ADC2 : Enable ADC2 reset + * @arg RCM_APB2_PERIPH_TMR1 : Enable TMR1 reset + * @arg RCM_APB2_PERIPH_SPI1 : Enable SPI1 reset + * @arg RCM_APB2_PERIPH_TMR8 : Enable TMR8 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Enable USART1 reset + * @arg RCM_APB2_PERIPH_ADC3 : Enable ADC3 reset (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph) +{ + RCM->APB2RST |= APB2Periph; +} + +/*! + * @brief Disable High Speed APB (APB2) peripheral reset + * + * @param APB2Periph : Disable specifies APB2 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Disable AFIO reset + * @arg RCM_APB2_PERIPH_GPIOA : Disable GPIOA reset + * @arg RCM_APB2_PERIPH_GPIOB : Disable GPIOB reset + * @arg RCM_APB2_PERIPH_GPIOC : Disable GPIOC reset + * @arg RCM_APB2_PERIPH_GPIOD : Disable GPIOD reset + * @arg RCM_APB2_PERIPH_GPIOE : Disable GPIOE reset + * @arg RCM_APB2_PERIPH_GPIOF : Disable GPIOF reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Disable GPIOG reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Disable ADC1 reset + * @arg RCM_APB2_PERIPH_ADC2 : Disable ADC2 reset + * @arg RCM_APB2_PERIPH_TMR1 : Disable TMR1 reset + * @arg RCM_APB2_PERIPH_SPI1 : Disable SPI1 reset + * @arg RCM_APB2_PERIPH_TMR8 : Disable TMR8 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Disable USART1 reset + * @arg RCM_APB2_PERIPH_ADC3 : Disable ADC3 reset (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph) +{ + RCM->APB2RST &= (uint32_t)~APB2Periph; +} + +/*! + * @brief Enable Low Speed APB (APB1) peripheral reset + * + * @param APB1Periph : Enable specifies APB1 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 reset + * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 reset + * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 reset + * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT reset + * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 reset + * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 reset + * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 reset + * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 reset + * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 reset + * @arg RCM_APB1_PERIPH_USB : Enable USB reset + * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 reset + * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 reset (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Enable BAKR reset + * @arg RCM_APB1_PERIPH_PMU : Enable PMU reset + * @arg RCM_APB1_PERIPH_DAC : Enable DAC reset + * + * @retval None + */ +void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph) +{ + RCM->APB1RST |= APB1Periph; +} + +/*! + * @brief Disable Low Speed APB (APB1) peripheral reset + * + * @param APB1Periph : Disable specifies APB1 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 reset + * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 reset + * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 reset + * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT reset + * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 reset + * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 reset + * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 reset + * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 reset + * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 reset + * @arg RCM_APB1_PERIPH_USB : Disable USB reset + * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 reset + * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 reset (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Disable BAKR reset + * @arg RCM_APB1_PERIPH_PMU : Disable PMU reset + * @arg RCM_APB1_PERIPH_DAC : Disable DAC reset + * + * @retval None + */ +void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph) +{ + RCM->APB1RST &= (uint32_t)~APB1Periph; +} + +/*! + * @brief Enable the Backup domain reset + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_EnableBackupReset(void) +{ + RCM->BDCTRL_B.BDRST = BIT_SET; +} + +/*! + * @brief Disable the Backup domain reset + * + * @param None + * + * @retval None + */ +void RCM_DisableBackupReset(void) +{ + RCM->BDCTRL_B.BDRST = BIT_RESET; +} + +/*! + * @brief Enable RCM interrupts + * + * @param interrupt : Enable specifies RCM interrupt sources. + * This parameter can be any combination of the following values: + * @arg RCM_INT_LSIRDY : LSI ready interrupt + * @arg RCM_INT_LSERDY : LSE ready interrupt + * @arg RCM_INT_HSIRDY : HSI ready interrupt + * @arg RCM_INT_HSERDY : HSE ready interrupt + * @arg RCM_INT_PLLRDY : PLL ready interrupt + * + * @retval None + */ +void RCM_EnableInterrupt(uint32_t interrupt) +{ + uint32_t temp; + + temp = interrupt << 8; + + RCM->INT |= temp; +} + +/*! + * @brief Disable RCM interrupts + * + * @param interrupt : Disable specifies RCM interrupt sources. + * This parameter can be any combination of the following values: + * @arg RCM_INT_LSIRDY : LSI ready interrupt + * @arg RCM_INT_LSERDY : LSE ready interrupt + * @arg RCM_INT_HSIRDY : HSI ready interrupt + * @arg RCM_INT_HSERDY : HSE ready interrupt + * @arg RCM_INT_PLLRDY : PLL ready interrupt +RCM_DisableInterrupt(RCM_INT_LSIRDY) * + * @retval None + */ +void RCM_DisableInterrupt(uint32_t interrupt) +{ + uint32_t temp; + + temp = interrupt << 8; + + RCM->INT &= (uint32_t)~temp; +} + +/*! + * @brief Read the specified RCM flag status + * + * @param flag : Returns specifies the flag status. + * This parameter can be one of the following values: + * @arg RCM_FLAG_HSIRDY : HSI ready flag + * @arg RCM_FLAG_HSERDY : HSE ready flag + * @arg RCM_FLAG_PLLRDY : PLL ready flag + * @arg RCM_FLAG_LSERDY : LSE ready flag + * @arg RCM_FLAG_LSIRDY : LSI ready flag + * @arg RCM_FLAG_PINRST : NRST PIN Reset Occur Flag + * @arg RCM_FLAG_PORRST : POR/PDR Reset Occur Flag + * @arg RCM_FLAG_SWRST : Software Reset Occur Flag + * @arg RCM_FLAG_IWDTRST : Independent Watchdog Reset Occur Flag + * @arg RCM_FLAG_WWDTRST : Window Watchdog Reset Occur Flag + * @arg RCM_FLAG_LPRRST : Low Power Reset Occur Flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag) +{ + uint32_t reg, bit; + + bit = (uint32_t)(1 << (flag & 0xff)); + + reg = (flag >> 8) & 0xff; + + switch (reg) + { + case 0: + reg = RCM->CTRL; + break; + + case 1: + reg = RCM->BDCTRL; + break; + + case 2: + reg = RCM->CSTS; + break; + + default: + break; + } + + if (reg & bit) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears all the RCM reset flags + * + * @param None + * + * @retval None + * + * @note The reset flags are: + * RCM_FLAG_PINRST, RCM_FLAG_PWRST, RCM_FLAG_SWRST + * RCM_FLAG_IWDTRST, RCM_FLAG_WWDTRST, RCM_FLAG_LPRRST + */ +void RCM_ClearStatusFlag(void) +{ + RCM->CSTS_B.RSTFLGCLR = BIT_SET; +} + +/*! + * @brief Reads the specified RCM interrupt Flag + * + * @param flag ��Reads specifies RCM interrupt flag. + * This parameter can be one of the following values: + * @arg RCM_INT_LSIRDY : LSI ready interrupt flag + * @arg RCM_INT_LSERDY : LSE ready interrupt flag + * @arg RCM_INT_HSIRDY : HSI ready interrupt flag + * @arg RCM_INT_HSERDY : HSE ready interrupt flag + * @arg RCM_INT_PLLRDY : PLL ready interrupt flag + * @arg RCM_INT_CSS : Clock Security System interrupt flag + * + * @retval The new state of intFlag (SET or RESET) + */ +uint8_t RCM_ReadIntFlag(RCM_INT_T flag) +{ + uint8_t ret; + + ret = (RCM->INT& flag) ? SET : RESET; + + return ret; +} + +/*! + * @brief Clears the interrupt flag + * + * @param flag : Clears specifies interrupt flag. + * @arg RCM_INT_LSIRDY : Clear LSI ready interrupt flag + * @arg RCM_INT_LSERDY : Clear LSE ready interrupt flag + * @arg RCM_INT_HSIRDY : Clear HSI ready interrupt flag + * @arg RCM_INT_HSERDY : Clear HSE ready interrupt flag + * @arg RCM_INT_PLLRDY : Clear PLL ready interrupt flag + * @arg RCM_INT_CSS : Clear Clock Security System interrupt flag + * + * @retval None + */ +void RCM_ClearIntFlag(uint32_t flag) +{ + uint32_t temp; + + temp = flag << 16; + RCM->INT |= temp; +} + +/**@} end of group RCM_Fuctions*/ +/**@} end of group RCM_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c new file mode 100644 index 0000000000..71db57ceb7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c @@ -0,0 +1,221 @@ +/*! + * @file apm32f10x_rtc.c + * + * @brief This file provides all the RTC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#include "apm32f10x_rtc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Enter RTC configuration mode. + * + * @param None + * + * @retval None + */ +void RTC_EnableConfigMode(void) +{ + RTC->CSTS_B.CFGMFLG = BIT_SET; +} + +/*! + * @brief Exit RTC configuration mode. + * + * @param None + * + * @retval None + */ +void RTC_DisableConfigMode(void) +{ + RTC->CSTS_B.CFGMFLG = BIT_RESET; +} + +/*! + * @brief Read the RTC counter value. + * + * @param None + * + * @retval RTC counter value. + */ +uint32_t RTC_ReadCounter(void) +{ + return (((RTC->CNTH_B.CNTH) << 16) | (RTC->CNTL_B.CNTL)); +} + +/*! + * @brief Config the RTC counter value. + * + * @param value: RTC counter new value. + * + * @retval None + */ +void RTC_ConfigCounter(uint32_t value) +{ + RTC_EnableConfigMode(); + RTC->CNTH_B.CNTH = value >> 16; + RTC->CNTL_B.CNTL = value & 0x0000FFFF; + RTC_DisableConfigMode(); +} + +/*! + * @brief Config the RTC prescaler value. + * + * @param value: RTC prescaler new value. + * + * @retval None + */ +void RTC_ConfigPrescaler(uint32_t value) +{ + RTC_EnableConfigMode(); + RTC->PSCRLDH_B.PSCRLDH = value >> 16; + RTC->PSCRLDL_B.PSCRLDL = value & 0x0000FFFF; + RTC_DisableConfigMode(); +} + +/*! + * @brief Config the RTC alarm value. + * + * @param value: RTC alarm new value. + * + * @retval None + */ +void RTC_ConfigAlarm(uint32_t value) +{ + RTC_EnableConfigMode(); + RTC->ALRH_B.ALRH = value >> 16; + RTC->ALRL_B.ALRL = value & 0x0000FFFF; + RTC_DisableConfigMode(); +} + +/*! + * @brief Reads the RTC divider value. + * + * @param None + * + * @retval RTC Divider value. + */ +uint32_t RTC_ReadDivider(void) +{ + return ((RTC->PSCH_B.PSCH & 0x000F) << 16 ) | (RTC->PSCL_B.PSCL); +} + +/*! + * @brief Waits until last write operation on RTC registers has finished. + * + * @param None + * + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + while(RTC->CSTS_B.OCFLG == BIT_RESET) + { + } +} + +/*! + * @brief Waits until the RTC registers + * + * @param None + * + * @retval None + */ +void RTC_WaitForSynchor(void) +{ + RTC->CSTS_B.RSYNCFLG = BIT_RESET; + while(RTC->CSTS_B.RSYNCFLG == BIT_RESET) + { + } +} + +/*! + * @brief Enable RTC interrupts. + * + * @param interrupt: RTC interrupt + * + * @retval None + */ +void RTC_EnableInterrupt(uint16_t interrupt) +{ + RTC->CTRL |= interrupt; +} + +/*! + * @brief Disable RTC interrupts. + * + * @param interrupt: RTC interrupt + * + * @retval None + */ +void RTC_DisableInterrupt(uint16_t interrupt) +{ + RTC->CTRL &= (uint32_t )~interrupt; +} + +/*! + * @brief Read flag bit + * + * @param flag: Flags to read + * + * @retval flag bit + */ +uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag) +{ + return (RTC->CSTS & flag) ? SET : RESET; +} + +/*! + * @brief Clear flag bit + * + * @param flag: Flags to clear + * + * @retval None + */ +void RTC_ClearStatusFlag(uint16_t flag) +{ + RTC->CSTS &= (uint32_t)~flag; +} + +/*! + * @brief Read interrupt flag bit is set + * + * @param flag:Flag bit to check + * + * @retval None + */ +uint8_t RTC_ReadIntFlag(RTC_INT_T flag) +{ + return (RTC->CSTS & flag) ? SET : RESET; +} + +/*! + * @brief Clear RTC interrupt flag bit + * + * @param flag: Clears the specified interrupt flag bit + * + * @retval None + */ +void RTC_ClearIntFlag(uint16_t flag) +{ + RTC->CSTS &= (uint32_t)~flag; +} + +/**@} end of group RTC_Fuctions*/ +/**@} end of group RTC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c new file mode 100644 index 0000000000..4b5ea1276a --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c @@ -0,0 +1,898 @@ +/*! + * @file apm32f10x_sci2c.c + * + * @brief This file contains all the functions for the SCI2C peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_sci2c.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SCI2C_Driver SCI2C Driver + @{ +*/ + +/** @addtogroup SCI2C_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Set I2C peripheral registers to their default reset values + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_Reset(SCI2C_T *i2c) +{ + if(i2c == I2C3) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + } + else + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + } + + i2c->SW = 0; + i2c->SW = 1; + i2c->INTEN = 0; +} + +/*! + * @brief Config the I2C peripheral according to the specified parameters in the sci2cConfig + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param sci2cConfig: pointer to a SCI2C_Config_T structure + * + * @retval None + */ +void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig) +{ + i2c->SW = BIT_SET; + + i2c->CTRL2_B.I2CEN = BIT_RESET; + + if(sci2cConfig->mode == SCI2C_MODE_MASTER) + { + i2c->CTRL1_B.MST = BIT_SET; + i2c->CTRL1_B.SLADIS = BIT_SET; + } + else + { + i2c->CTRL1_B.MST = BIT_RESET; + } + + i2c->CTRL1_B.SPD = sci2cConfig->speed; + i2c->CTRL1_B.RSTAEN = sci2cConfig->restart; + + i2c->TFT = sci2cConfig->txFifoThreshold; + i2c->RFT = sci2cConfig->rxFifoThreshold; + + i2c->TARADDR_B.MAM = sci2cConfig->addrMode; + i2c->CTRL1_B.SAM = sci2cConfig->addrMode; + i2c->SLAADDR = sci2cConfig->slaveAddr; + + if(sci2cConfig->speed == SCI2C_SPEED_STANDARD) + { + i2c->SSCLC = sci2cConfig->clkLowPeriod; + i2c->SSCHC = sci2cConfig->clkHighPeriod; + } + else if(sci2cConfig->speed == SCI2C_SPEED_FAST) + { + i2c->FSCLC = sci2cConfig->clkLowPeriod; + i2c->FSCHC = sci2cConfig->clkHighPeriod; + } + else if(sci2cConfig->speed == SCI2C_SPEED_HIGH) + { + i2c->HSCLC = sci2cConfig->clkLowPeriod; + i2c->HSCHC = sci2cConfig->clkHighPeriod; + } +} + +/*! + * @brief Fills each sci2cConfig member with its default value + * + * @param sci2cConfig: pointer to a SCI2C_Config_T structure + * + * @retval None + */ +void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig) +{ + sci2cConfig->addrMode = SCI2C_ADDR_MODE_7BIT; + sci2cConfig->slaveAddr = 0x55; + sci2cConfig->clkHighPeriod = 0x3C; + sci2cConfig->clkLowPeriod = 0x82; + sci2cConfig->mode = SCI2C_MODE_MASTER; + sci2cConfig->restart = SCI2C_RESTART_ENABLE; + sci2cConfig->rxFifoThreshold = 0; + sci2cConfig->txFifoThreshold = 0; + sci2cConfig->speed = SCI2C_SPEED_FAST; +} + +/*! + * @brief Read specified flag + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_FLAG_ACT: Activity flag + * @arg SCI2C_FLAG_TFNF: Tx FIFO not full flag + * @arg SCI2C_FLAG_TFE: TX FIFO empty flag + * @arg SCI2C_FLAG_RFNE: Rx FIFO not empty flag + * @arg SCI2C_FLAG_RFF: Rx FIFO full flag + * @arg SCI2C_FLAG_MA: Master activity flag + * @arg SCI2C_FLAG_SA: Slave activity flag + * @arg SCI2C_FLAG_I2CEN: I2C enable flag + * @arg SCI2C_FLAG_SDWB: Slave disable while busy flag + * @arg SCI2C_FLAG_SRDL: Slave receive data lost flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag) +{ + uint8_t ret = RESET; + + if(flag & BIT8) + { + ret = i2c->STS2 & flag ? SET : RESET; + } + else + { + ret = i2c->STS1 & flag ? SET : RESET; + } + + return ret; +} + +/*! + * @brief Read specified interrupt flag + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt flag + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt flag + * @arg SCI2C_INT_RR: Read request interrupt flag + * @arg SCI2C_INT_TA: Tx abort interrupt flag + * @arg SCI2C_INT_RD: Read done interrupt flag + * @arg SCI2C_INT_ACT: Activity interrupt flag + * @arg SCI2C_INT_STPD: Stop detect interrupt flag + * @arg SCI2C_INT_STAD: Start detect interrupt flag + * @arg SCI2C_INT_GC: Gernal call interrupt flag + * @arg SCI2C_INT_RSTAD: Restart detect interrupt flag + * @arg SCI2C_INT_MOH: Master on hold interrupt flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +{ + uint8_t ret = RESET; + + ret = i2c->INTSTS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Clear specified interrupt flag + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag + * @arg SCI2C_INT_RR: Read request interrupt flag + * @arg SCI2C_INT_TA: Tx abort interrupt flag + * @arg SCI2C_INT_RD: Read done interrupt flag + * @arg SCI2C_INT_ACT: Activity interrupt flag + * @arg SCI2C_INT_STPD: Stop detect interrupt flag + * @arg SCI2C_INT_STAD: Start detect interrupt flag + * @arg SCI2C_INT_GC: Gernal call interrupt flag + * @arg SCI2C_INT_ALL: All interrupt flag + * @retval The new state of flag (SET or RESET) + */ +void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +{ + volatile uint32_t dummy = 0; + + if(flag == SCI2C_INT_ALL) + { + dummy = i2c->INTCLR; + } + else if(flag == SCI2C_INT_RFU) + { + dummy = i2c->RFUIC; + } + else if(flag == SCI2C_INT_RFO) + { + dummy = i2c->RFOIC; + } + else if(flag == SCI2C_INT_TFO) + { + dummy = i2c->TFOIC; + } + else if(flag == SCI2C_INT_RR) + { + dummy = i2c->RRIC; + } + else if(flag == SCI2C_INT_TA) + { + dummy = i2c->TAIC; + } + else if(flag == SCI2C_INT_RD) + { + dummy = i2c->RDIC; + } + else if(flag == SCI2C_INT_ACT) + { + dummy = i2c->AIC; + } + else if(flag == SCI2C_INT_STPD) + { + dummy = i2c->STPDIC; + } + else if(flag == SCI2C_INT_STAD) + { + dummy = i2c->STADIC; + } + else if(flag == SCI2C_INT_GC) + { + dummy = i2c->GCIC; + } +} + +/*! + * @brief Read specified interrupt flag(Raw register) + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt flag + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt flag + * @arg SCI2C_INT_RR: Read request interrupt flag + * @arg SCI2C_INT_TA: Tx abort interrupt flag + * @arg SCI2C_INT_RD: Read done interrupt flag + * @arg SCI2C_INT_ACT: Activity interrupt flag + * @arg SCI2C_INT_STPD: Stop detect interrupt flag + * @arg SCI2C_INT_STAD: Start detect interrupt flag + * @arg SCI2C_INT_GC: Gernal call interrupt flag + * @arg SCI2C_INT_RSTAD: Restart detect interrupt flag + * @arg SCI2C_INT_MOH: Master on hold interrupt flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +{ + uint8_t ret = RESET; + + ret = i2c->RIS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Enable the specified interrupts + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param interrupt: Specifies the interrupt sources + * The parameter can be any combination of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt + * @arg SCI2C_INT_RR: Read request interrupt + * @arg SCI2C_INT_TA: Tx abort interrupt + * @arg SCI2C_INT_RD: Read done interrupt + * @arg SCI2C_INT_ACT: Activity interrupt + * @arg SCI2C_INT_STPD: Stop detect interrupt + * @arg SCI2C_INT_STAD: Start detect interrupt + * @arg SCI2C_INT_GC: Gernal call interrupt + * @arg SCI2C_INT_RSTAD: Restart detect interrupt + * @arg SCI2C_INT_MOH: Master on hold interrupt + * + * @retval None + */ +void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt) +{ + i2c->INTEN |= interrupt; +} + +/*! + * @brief Disable the specified interrupts + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param interrupt: Specifies the interrupt sources + * The parameter can be any combination of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt + * @arg SCI2C_INT_RR: Read request interrupt + * @arg SCI2C_INT_TA: Tx abort interrupt + * @arg SCI2C_INT_RD: Read done interrupt + * @arg SCI2C_INT_ACT: Activity interrupt + * @arg SCI2C_INT_STPD: Stop detect interrupt + * @arg SCI2C_INT_STAD: Start detect interrupt + * @arg SCI2C_INT_GC: Gernal call interrupt + * @arg SCI2C_INT_RSTAD: Restart detect interrupt + * @arg SCI2C_INT_MOH: Master on hold interrupt + * + * @retval None + */ +void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt) +{ + i2c->INTEN &= ~interrupt; +} + +/*! + * @brief Enable stop detected only master in activity. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSMA = BIT_SET; +} + +/*! + * @brief Disable stop detected only master in activity. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSMA = BIT_RESET; +} + +/*! + * @brief Enable stop detected only address is matched in slave mode. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSA = BIT_SET; +} + +/*! + * @brief Disable stop detected only address is matched in slave mode. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSA = BIT_RESET; +} + +/*! + * @brief Enable restart + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_EnableRestart(SCI2C_T *i2c) +{ + i2c->CTRL1_B.RSTAEN = BIT_SET; +} + +/*! + * @brief Disable restart + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_DisableRestart(SCI2C_T *i2c) +{ + i2c->CTRL1_B.RSTAEN = BIT_RESET; +} + +/*! + * @brief Config speed. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param speed: Specifies the speed. + * @arg SCI2C_SPEED_STANDARD: Standard speed. + * @arg SCI2C_SPEED_FAST: Fast speed. + * @arg SCI2C_SPEED_HIGH: High speed. + * + * @retval None + */ +void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed) +{ + i2c->CTRL1_B.SPD = speed; +} + +/*! + * @brief Config master address. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param mode: Specifies the address mode. + * @arg SCI2C_ADDR_MODE_7BIT: 7-bit address mode. + * @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode. + * + * @param addr: Specifies the address. + + * @retval None + */ +void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) +{ + i2c->TARADDR_B.MAM = mode; + i2c->TARADDR_B.ADDR = addr; +} + + +/*! + * @brief Config slave address. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param mode: Specifies the address mode. + * @arg SCI2C_ADDR_MODE_7BIT: 7-bit address mode. + * @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode. + * + * @param addr: Specifies the address. + + * @retval None + */ +void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) +{ + i2c->CTRL1_B.SAM = mode; + i2c->SLAADDR = addr; +} + +/*! + * @brief Enable master mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_EnableMasterMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.MST = BIT_SET; +} + +/*! + * @brief Disable master mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_DisableMasterMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.MST = BIT_RESET; +} + +/*! + * @brief Enable slave mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_EnableSlaveMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.SLADIS = BIT_RESET; +} + +/*! + * @brief Disable slave mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_DisableSlaveMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.SLADIS = BIT_SET; +} + +/*! + * @brief Config master code + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param code: Master code + * + * @retval None + */ +void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code) +{ + i2c->HSMC = code; +} + +/*! + * @brief Config data direction + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param dir: Data direction + * @arg SCI2C_DATA_DIR_WRITE: Write data + * @arg SCI2C_DATA_DIR_READ: Read data + * + * @retval None + */ +void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir) +{ + i2c->DATA = (uint32_t)(dir << 8); +} + +/*! + * @brief Transmit data + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param data: Data to be transmited + * + * @retval None + */ +void SCI2C_TxData(SCI2C_T *i2c, uint8_t data) +{ + i2c->DATA_B.DATA = data; +} + +/*! + * @brief Returns the most recent received data + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval Received data + * + * @note + */ +uint8_t SCI2C_RxData(SCI2C_T *i2c) +{ + return (uint8_t)(i2c->DATA & 0XFF); +} + +/*! + * @brief Config data register + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param stop: Enable or disable generate stop condition + * + * @param dataDir: Data direction. Read or write + * @arg SCI2C_DATA_DIR_WRITE: Write data + * @arg SCI2C_DATA_DIR_READ: Read data + * + * @param data: Data to be transmited + * + * @retval None + */ +void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data) +{ + i2c->DATA = (uint32_t)((stop << 9) | (dataDir << 8) | data); +} + +/*! + * @brief Read Rx FIFO data number + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c) +{ + return (uint8_t)i2c->RFL; +} + +/*! + * @brief Read Tx FIFO data number + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c) +{ + return (uint8_t)i2c->TFL; +} + +/*! + * @brief Config Rx FIFO threshold + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param threshold: FIFO threshold + * + * @retval None + */ +void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold) +{ + i2c->RFT = threshold; +} + +/*! + * @brief Config Tx FIFO threshold + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param threshold: FIFO threshold + * + * @retval None + */ +void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold) +{ + i2c->TFT = threshold; +} + +/*! + * @brief Enable I2C peripheral + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + + */ +void SCI2C_Enable(SCI2C_T *i2c) +{ + i2c->CTRL2_B.I2CEN = BIT_SET; +} + +/*! + * @brief Disable I2C peripheral + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_Disable(SCI2C_T *i2c) +{ + i2c->CTRL2_B.I2CEN = BIT_RESET; +} + +/*! + * @brief Abort I2C transmit + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_Abort(SCI2C_T *i2c) +{ + i2c->CTRL2_B.ABR = BIT_SET; +} + +/*! + * @brief Tx command block + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param enable: ENABLE or DISABLE + * + * @retval None + */ +void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable) +{ + i2c->CTRL2_B.TCB = enable; +} + +/*! + * @brief Config SCL high and low period + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param speed: Specifies the speed. + * @arg SCI2C_SPEED_STANDARD: Standard speed. + * @arg SCI2C_SPEED_FAST: Fast speed. + * @arg SCI2C_SPEED_HIGH: High speed. + * + * @param highPeriod: SCL high period + * + * @param lowPeriod: SCL low period + * + * @retval None + */ +void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod) +{ + if(speed == SCI2C_SPEED_STANDARD) + { + i2c->SSCLC = lowPeriod; + i2c->SSCHC = highPeriod; + } + else if(speed == SCI2C_SPEED_FAST) + { + i2c->FSCLC = lowPeriod; + i2c->FSCHC = highPeriod; + } + else if(speed == SCI2C_SPEED_HIGH) + { + i2c->HSCLC = lowPeriod; + i2c->HSCHC = highPeriod; + } +} + +/*! + * @brief Config SDA hold time length + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param txHold: Tx SDA hold time length + * + * @param rxHold: Rx SDA hold time length + * + * @retval None + */ +void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold) +{ + i2c->SDAHOLD_B.TXHOLD = txHold; + i2c->SDAHOLD_B.RXHOLD = rxHold; +} + +/*! + * @brief Config SDA delay time + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param delay: SDA delay time + * + * @retval None + */ +void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay) +{ + i2c->SDADLY = delay; +} + +/*! + * @brief Enable or disable generate gernal call ack + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param enable: SDA delay time + * + * @retval None + */ +void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable) +{ + i2c->GCA = enable; +} + +/*! + * @brief When received data no ack generated in slave mode. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param enable: ENABLE or DISABLE + * + * @retval None + */ +void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable) +{ + i2c->SDNO = enable; +} + +/*! + * @brief Read Tx abort source + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval Return Tx abort source + */ +uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c) +{ + return (uint32_t)i2c->TAS; +} + +/*! + * @brief Enable DMA + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param dma: DMA requst source + * @arg SCI2C_DMA_RX: DMA RX channel + * @arg SCI2C_DMA_TX: DMA TX channel + * + * @retval None + */ +void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) +{ + i2c->DMACTRL |= dma; +} + +/*! + * @brief Disable DMA + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param dma: DMA requst source + * @arg SCI2C_DMA_RX: DMA RX channel + * @arg SCI2C_DMA_TX: DMA TX channel + * + * @retval None + */ +void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) +{ + i2c->DMACTRL &= (uint32_t)~dma; +} + +/*! + * @brief Config DMA Tx data level + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param cnt: DMA Tx data level + * + * @retval None + */ +void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt) +{ + i2c->DTDL = cnt; +} + +/*! + * @brief Config DMA Rx data level + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param cnt: DMA Rx data level + * + * @retval None + */ +void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt) +{ + i2c->DRDL = cnt; +} + +/*! + * @brief Config spike suppressio limit + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param speed: I2C speed mode + * @arg SCI2C_SPEED_STANDARD: Standard speed. + * @arg SCI2C_SPEED_FAST: Fast speed. + * @arg SCI2C_SPEED_HIGH: High speed. + * + * @param limit: Spike suppressio limit value + * + * @retval None + */ +void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit) +{ + if(speed == SCI2C_SPEED_HIGH) + { + i2c->HSSSL = limit; + } + else + { + i2c->LSSSL = limit; + } +} + +/**@} end of group SCI2C_Fuctions*/ +/**@} end of group SCI2C_Driver*/ +/**@} end of group Peripherals_Library*/ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c new file mode 100644 index 0000000000..3c76e77076 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c @@ -0,0 +1,730 @@ +/*! + * @file apm32f10x_sdio.c + * + * @brief This file provides all the SDIO firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_sdio.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SDIO_Driver SDIO Driver + @{ +*/ + +/** @addtogroup SDIO_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset sdio peripheral registers to their default reset values + * + * @param None + * + * @retval None + */ +void SDIO_Reset(void) +{ + SDIO->PWRCTRL = 0x00000000; + SDIO->CLKCTRL = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DATATIME = 0x00000000; + SDIO->DATALEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICF = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/*! + * @brief Config the SDIO peripheral according to the specified parameters in the sdioConfig + * + * @param sdioConfig: pointer to a SDIO_Config_T structure + * + * @retval None + */ +void SDIO_Config(SDIO_Config_T* sdioConfig) +{ + uint32_t tmp = 0; + + tmp = SDIO->CLKCTRL; + tmp &= 0xFFFF8100; + + tmp |= (sdioConfig->clockDiv | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide | + sdioConfig->clockEdge | sdioConfig->hardwareFlowControl); + + SDIO->CLKCTRL = tmp; +} + +/*! + * @brief Fills each SDIO_Config_T member with its default value + * + * @param sdioConfig: pointer to a SDIO_Config_T structure + * + * @retval None + */ +void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig) +{ + sdioConfig->clockDiv = 0x00; + sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING; + sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE; + sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + sdioConfig->busWide = SDIO_BUSWIDE_1B; + sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; +} + +/*! + * @brief Enables the SDIO clock + * + * @param None + * + * @retval None + */ +void SDIO_EnableClock(void) +{ + *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)SET; +} + +/*! + * @brief Disables the SDIO clock + * + * @param None + * + * @retval None + */ +void SDIO_DisableClock(void) +{ + *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)RESET; +} + +/*! + * @brief Sets the power status of the controller + * + * @param powerState: new state of the Power state + * The parameter can be one of following values: + * @arg SDIO_POWER_STATE_OFF + * @arg SDIO_POWER_STATE_ON + * @retval None + */ +void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState) +{ + SDIO->PWRCTRL &= 0xFFFFFFFC; + SDIO->PWRCTRL |= powerState; +} + +/*! + * @brief Reads the SDIO power state + * + * @param None + * + * @retval The new state SDIO power + * + * @note 0x00:Power OFF, 0x02:Power UP, 0x03:Power ON + */ +uint32_t SDIO_ReadPowerState(void) +{ + return (SDIO->PWRCTRL & (~0xFFFFFFFC)); +} + +/*! + * @brief Enables the SDIO DMA request + * + * @param None + * + * @retval None + */ +void SDIO_EnableDMA(void) +{ + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)SET; +} + +/*! + * @brief Disables the SDIO DMA request + * + * @param None + * + * @retval None + */ +void SDIO_DisableDMA(void) +{ + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)RESET; +} + +/*! + * @brief Configs the SDIO Command and send the command + * + * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure + * + * @retval None + * + * @note + */ +void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig) +{ + uint32_t tmpreg = 0; + + SDIO->ARG = cmdConfig->argument; + tmpreg = SDIO->CMD; + tmpreg &= 0xFFFFF800; + tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response + | cmdConfig->wait | cmdConfig->CPSM; + SDIO->CMD = tmpreg; +} + +/*! + * @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value + * + * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure + * + * @retval None + * + * @note + */ +void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdConfig) +{ + cmdConfig->argument = 0x00; + cmdConfig->cmdIndex = 0x00; + cmdConfig->response = SDIO_RESPONSE_NO; + cmdConfig->wait = SDIO_WAIT_NO; + cmdConfig->CPSM = SDIO_CPSM_DISABLE; +} + +/*! + * @brief Reads the SDIO command response + * + * @param None + * + * @retval The command index of the last command response received + * + * @note + */ +uint8_t SDIO_ReadCommandResponse(void) +{ + return (uint8_t)(SDIO->CMDRES); +} + +/*! + * @brief Reads the SDIO response + * + * @param res: Specifies the SDIO response register + * The parameter can be one of following values: + * @arg SDIO_RES1: Response Register 1 + * @arg SDIO_RES2: Response Register 2 + * @arg SDIO_RES3: Response Register 3 + * @arg SDIO_RES4: Response Register 4 + * + * @retval The Corresponding response register value + */ +uint32_t SDIO_ReadResponse(SDIO_RES_T res) +{ + __IO uint32_t tmp = 0; + + tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res; + + return (*(__IO uint32_t *) tmp); +} + +/*! + * @brief Configs the SDIO Dataaccording to the specified parameters in the dataConfig + * + * @param dataConfig: pointer to a SDIO_DataConfig_T structure + * + * @retval None + */ +void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) +{ + uint32_t tmpreg = 0; + + SDIO->DATATIME = dataConfig->dataTimeOut; + + SDIO->DATALEN = dataConfig->dataLength; + + tmpreg = SDIO->DCTRL; + + tmpreg &= 0xFFFFFF08; + + tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir + | dataConfig->transferMode | dataConfig->DPSM; + + SDIO->DCTRL = tmpreg; +} + +/*! + * @brief Fills each SDIO_DataConfig_T member with its default value + * + * @param dataConfig: pointer to a SDIO_DataConfig_T structure + * + * @retval None + */ +void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig) +{ + dataConfig->dataTimeOut = 0xFFFFFFFF; + dataConfig->dataLength = 0x00; + dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B; + dataConfig->transferDir = SDIO_TRANSFER_DIR_TOCARD; + dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK; + dataConfig->DPSM = SDIO_DPSM_DISABLE; +} + +/*! + * @brief Reads the SDIO Data counter + * + * @param None + * + * @retval The SDIO Data counter value + */ +uint32_t SDIO_ReadDataCounter(void) +{ + return SDIO->DCNT; +} + +/*! + * @brief Write the SDIO Data + * + * @param Data��Write 32-bit data + * + * @retval None + */ +void SDIO_WriteData(uint32_t data) +{ + SDIO->FIFODATA = data; +} + +/*! + * @brief Reads the SDIO Data + * + * @param None + * + * @retval The SDIO FIFO Data value + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFODATA; +} + +/*! + * @brief Reads the SDIO FIFO count value + * + * @param None + * + * @retval The SDIO FIFO count value + */ +uint32_t SDIO_ReadFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/*! + * @brief Enables SDIO start read wait + * + * @param None + * + * @retval None + */ +void SDIO_EnableStartReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) SET; +} + +/*! + * @brief Disables SDIO start read wait + * + * @param None + * + * @retval None + */ +void SDIO_DisableStopReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) RESET; +} + +/*! + * @brief Enables SDIO stop read wait + * + * @param None + * + * @retval None + */ +void SDIO_EnableStopReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) SET; +} + +/*! + * @brief Disables SDIO stop read wait + * + * @param None + * + * @retval None + */ +void SDIO_DisableStartReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) RESET; +} + +/*! + * @brief Sets the read wait interval + * + * @param readWaitMode: SDIO read Wait Mode + * The parameter can be one of following values: + * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 + * + * @retval None + * + * @note + */ +void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode) +{ + *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode; +} +/*! + * @brief Enables SDIO SD I/O Mode Operation + * + * @param None + * + * @retval None + */ +void SDIO_EnableSDIO(void) +{ + *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET; +} + +/*! + * @brief Disables SDIO SD I/O Mode Operation + * + * @param None + * + * @retval None + */ +void SDIO_DisableSDIO(void) +{ + *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET; +} + +/*! + * @brief Ensables SDIO SD I/O Mode suspend command sending + * + * @param None + * + * @retval None + */ +void SDIO_EnableTxSDIOSuspend(void) +{ + *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)SET; +} + +/*! + * @brief Disables SDIO SD I/O Mode suspend command sending + * + * @param None + * + * @retval None + */ +void SDIO_DisableTxSDIOSuspend(void) +{ + *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)RESET; +} + +/*! + * @brief Enables the command completion signal + * + * @param None + * + * @retval None + */ +void SDIO_EnableCommandCompletion(void) +{ + *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)SET; +} + +/*! + * @brief Disables the command completion signal + * + * @param None + * + * @retval None + */ +void SDIO_DisableCommandCompletion(void) +{ + *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)RESET; +} + +/*! + * @brief Enables the CE-ATA interrupt + * + * @param None + * + * @retval None + */ +void SDIO_EnableCEATAInterrupt(void) +{ + *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1)); +} + +/*! + * @brief Disables the CE-ATA interrupt + * + * @param None + * + * @retval None + */ +void SDIO_DisableCEATAInterrupt(void) +{ + *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1)); +} + +/*! + * @brief Ensables Sends CE-ATA command + * + * @param None + * + * @retval None + */ +void SDIO_EnableTxCEATA(void) +{ + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)SET; +} + +/*! + * @brief Disables Sends CE-ATA command + * + * @param None + * + * @retval None + */ +void SDIO_DisableTxCEATA(void) +{ + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)RESET; +} + +/*! + * @brief Enables the specified SDIO interrupt + * + * @param interrupt: Select the SDIO interrupt source + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +void SDIO_EnableInterrupt(uint32_t interrupt) +{ + SDIO->MASK |= interrupt; +} + +/*! + * @brief Disables the specified SDIO interrupt + * + * @param interrupt: Select the SDIO interrupt source + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +void SDIO_DisableInterrupt(uint32_t interrupt) +{ + SDIO->MASK &= ~interrupt; +} + +/*! + * @brief Reads the specified SDIO flag + * + * @param flag: Select the flag to read + * The parameter can be one of following values: + * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag + * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag + * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag + * @arg SDIO_FLAG_DATATO: Data timeout flag + * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag + * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag + * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag + * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag + * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag + * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag + * @arg SDIO_FLAG_CMDACT: Command transfer in progress flag + * @arg SDIO_FLAG_TXACT: Data transmit in progress flag + * @arg SDIO_FLAG_RXACT: Data receive in progress flag + * @arg SDIO_FLAG_TXFHF: Transmit FIFO Half Empty flag + * @arg SDIO_FLAG_RXFHF: Receive FIFO Half Full flag + * @arg SDIO_FLAG_TXFF: Transmit FIFO full flag + * @arg SDIO_FLAG_RXFF: Receive FIFO full flag + * @arg SDIO_FLAG_TXFE: Transmit FIFO empty flag + * @arg SDIO_FLAG_RXFE: Receive FIFO empty flag + * @arg SDIO_FLAG_TXDA: Data available in transmit FIFO flag + * @arg SDIO_FLAG_RXDA: Data available in receive FIFO flag + * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag + * + * @retval SET or RESET + */ +uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag) +{ + uint8_t bitstatus = RESET; + + if ((SDIO->STS & flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/*! + * @brief Clears the specified SDIO flag + * + * @param flag: Select the flag to clear + * The parameter can be any combination of following values: + * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag + * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag + * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag + * @arg SDIO_FLAG_DATATO: Data timeout flag + * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag + * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag + * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag + * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag + * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag + * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag + * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag + * + * @retval None + */ +void SDIO_ClearStatusFlag(uint32_t flag) +{ + SDIO->ICF = flag; +} + +/*! + * @brief Reads the specified SDIO Interrupt flag + * + * @param flag: Select the SDIO interrupt source + * The parameter can be one of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * + * @retval SET or RESET + */ +uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag) +{ + uint32_t intEnable; + uint32_t intStatus; + + intEnable = (uint32_t)(SDIO->MASK & flag); + intStatus = (uint32_t)(SDIO->STS & flag); + + if (intEnable && intStatus) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the specified SDIO Interrupt pending bits + * + * @param flag: Select the SDIO interrupt source + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * + * @retval None + */ +void SDIO_ClearIntFlag(uint32_t flag) +{ + SDIO->ICF = flag; +} + +/**@} end of group SDIO_Fuctions*/ +/**@} end of group SDIO_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c new file mode 100644 index 0000000000..079685b148 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c @@ -0,0 +1,598 @@ +/*! + * @file apm32f10x_spi.c + * + * @brief This file provides all the SPI firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_spi.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the specified SPIx peripheral + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_I2S_Reset(SPI_T* spi) +{ + if(spi == SPI1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); + } + else if(spi == SPI2) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); + } + else if(spi == SPI3) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3); + } +} + +/*! + * @brief Config the SPI peripheral according to the specified parameters in the spiConfig + * + * @param spi: The SPIx can be 1,2,3 + * + * @param spiConfig: pointer to a SPI_Config_T structure + * + * @retval None + */ +void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig) +{ + spi->CTRL1 &= 0x3040; + spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode | + spiConfig->length | spiConfig->polarity | + spiConfig->phase | spiConfig->nss | + spiConfig->baudrateDiv | spiConfig->firstBit); + spi->CRCPOLY = spiConfig->crcPolynomial; +} + +/*! + * @brief Config the I2S peripheral according to the specified parameters in the spiConfig + * + * @param spi: The SPIx can be 2,3 + * + * @param i2sConfig: pointer to a I2S_Config_T structure + * + * @retval None + */ +void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) +{ + uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1; + uint32_t tmp = 0; + uint32_t sysClock = 0; + + /* Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */ + spi->I2SCFG &= 0xF040; + spi->I2SPSC = 0x0002; + + if(i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT) + { + spi->I2SPSC_B.ODDPSC = 0; + spi->I2SPSC_B.I2SPSC = 2; + } + else + { + if(i2sConfig->length == I2S_DATA_LENGHT_16B) + { + packetSize = 1; + } + else + { + packetSize = 2; + } + + sysClock = RCM_ReadSYSCLKFreq(); + + if(i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE) + { + tmp = (uint16_t)(((((sysClock / 256) * 10) / i2sConfig ->audioDiv)) + 5); + } + else + { + tmp = (uint16_t)(((((sysClock / (32 * packetSize)) *10 ) / i2sConfig ->audioDiv )) + 5); + } + tmp = tmp / 10; + + i2sOdd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sDiv = (uint16_t)((tmp - i2sOdd) / 2); + + if ((i2sDiv < 2) || (i2sDiv > 0xFF)) + { + i2sDiv = 2; + i2sOdd = 0; + } + } + + spi->I2SPSC_B.I2SPSC = i2sDiv; + spi->I2SPSC_B.ODDPSC = i2sOdd; + spi->I2SPSC |= i2sConfig->MCLKOutput; + + spi->I2SCFG = i2sConfig->mode | i2sConfig->standard | i2sConfig->length | i2sConfig->polarity; + + /** select I2S mode */ + spi->I2SCFG_B.MODESEL = BIT_SET; +} + +/*! + * @brief Fills each SPI_Config_T member with its default value + * + * @param spiConfig: pointer to a SPI_Config_T structure + * + * @retval None + */ +void SPI_ConfigStructInit(SPI_Config_T* spiConfig) +{ + spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX; + spiConfig->mode = SPI_MODE_SLAVE; + spiConfig->length = SPI_DATA_LENGTH_8B; + spiConfig->polarity = SPI_CLKPOL_LOW; + spiConfig->phase = SPI_CLKPHA_1EDGE; + spiConfig->nss = SPI_NSS_HARD; + spiConfig->baudrateDiv = SPI_BAUDRATE_DIV_2; + spiConfig->firstBit = SPI_FIRSTBIT_MSB; + spiConfig->crcPolynomial = 7; +} + +/*! + * @brief Fills each I2S_Config_T member with its default value + * + * @param i2sConfig: pointer to a I2S_Config_T structure + * + * @retval None + */ +void I2S_ConfigStructInit(I2S_Config_T* i2sConfig) +{ + i2sConfig->mode = I2S_MODE_SLAVE_TX; + i2sConfig->standard = I2S_STANDARD_PHILLIPS; + i2sConfig->length = I2S_DATA_LENGHT_16B; + i2sConfig->MCLKOutput = I2S_MCLK_OUTPUT_DISABLE; + i2sConfig->audioDiv = I2S_AUDIO_DIV_DEFAULT; + i2sConfig->polarity = I2S_CLKPOL_LOW; +} +/*! + * @brief Enables the specified SPI peripheral + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_Enable(SPI_T* spi) +{ + spi->CTRL1_B.SPIEN = BIT_SET; +} + +/*! + * @brief Disable the specified SPI peripheral + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_Disable(SPI_T* spi) +{ + spi->CTRL1_B.SPIEN = BIT_RESET; +} + +/*! + * @brief Enables the specified I2S peripheral + * + * @param spi: The I2S can be SPI2,SPI3 + * + * @retval None + */ +void I2S_Enable(SPI_T* spi) +{ + spi->I2SCFG_B.I2SEN = BIT_SET; +} + +/*! + * @brief Disable the specified I2S peripheral + * + * @param spi: The I2S can be SPI2,SPI3 + * + * @retval None + */ +void I2S_Disable(SPI_T* spi) +{ + spi->I2SCFG_B.I2SEN = BIT_RESET; +} + +/*! + * @brief Enables the SPIx/I2Sx DMA interface. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param dmaReq: specifies the SPI/I2S DMA transfer request + * The parameter can be one of following values: + * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request + * @retval None + */ +void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) +{ + if(dmaReq == SPI_I2S_DMA_REQ_TX) + { + spi->CTRL2_B.TXDEN = ENABLE; + } + else + { + spi->CTRL2_B.RXDEN = ENABLE; + } +} + +/*! + * @brief Disables the SPIx/I2Sx DMA interface. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param dmaReq: specifies the SPI/I2S DMA transfer request + * The parameter can be one of following values: + * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request + * @retval None + */ +void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) +{ + if(dmaReq == SPI_I2S_DMA_REQ_TX) + { + spi->CTRL2_B.TXDEN = DISABLE; + } + else + { + spi->CTRL2_B.RXDEN = DISABLE; + } +} + +/*! + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param data: Data to be transmitted + * + * @retval None + */ +void SPI_I2S_TxData(SPI_T* spi, uint16_t data) +{ + spi->DATA = data; +} + +/*! + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @retval data :The value of the received data + * + * @retval None + */ +uint16_t SPI_I2S_RxData(SPI_T* spi) +{ + return spi->DATA; +} + +/*! + * @brief Set the SPI NSS internal by Software + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_SetSoftwareNSS(SPI_T* spi) +{ + spi->CTRL1_B.ISSEL = BIT_SET; +} + +/*! + * @brief Reset the SPI NSS internal by Software + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_ResetSoftwareNSS(SPI_T* spi) +{ + spi->CTRL1_B.ISSEL = BIT_RESET; +} + +/*! + * @brief Enables the specified SPI SS output + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_EnableSSOutput(SPI_T* spi) +{ + spi->CTRL2_B.SSOEN = BIT_SET; +} + +/*! + * @brief Disable the specified SPI SS output + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_DisableSSOutput(SPI_T* spi) +{ + spi->CTRL2_B.SSOEN = BIT_RESET; +} + +/*! + * @brief Configures the specified SPI data size + * + * @param spi: The SPIx can be 1,2,3 + * + * @param length: Select the SPI data Size + * + * @retval None + */ +void SPI_ConfigDataSize(SPI_T* spi, uint16_t length) +{ + spi->CTRL1_B.DFLSEL = BIT_RESET; + spi->CTRL1 |= length; +} + +/*! + * @brief Transmit CRC value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_TxCRC(SPI_T* spi) +{ + spi->CTRL1_B.CECNXT = BIT_SET; +} + +/*! + * @brief Enables the specified SPI CRC value calculation of the transferred bytes + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_EnableCRC(SPI_T* spi) +{ + spi->CTRL1_B.CRCEN = BIT_SET; +} + +/*! + * @brief Disable the specified SPI CRC value calculation of the transferred bytes + * + * @param spi: The SPIx can be 1,2,3 + * + */ +void SPI_DisableCRC(SPI_T* spi) +{ + spi->CTRL1_B.CRCEN = BIT_RESET; +} + +/*! + * @brief Reads the specified SPI transmit CRC register value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval The SPI transmit CRC register value + */ +uint16_t SPI_ReadTxCRC(SPI_T* spi) +{ + return spi->TXCRC_B.TXCRC; +} + +/*! + * @brief Reads the specified SPI receive CRC register value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval The SPI receive CRC register value + */ +uint16_t SPI_ReadRxCRC(SPI_T* spi) +{ + return spi->RXCRC_B.RXCRC; +} + +/*! + * @brief Reads the specified SPI CRC Polynomial register value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval The SPI CRC Polynomial register value + */ +uint16_t SPI_ReadCRCPolynomial(SPI_T* spi) +{ + return spi->CRCPOLY_B.CRCPOLY; +} + +/*! + * @brief Configures the specified SPI data transfer direction + * + * @param spi: The SPIx can be 1,2,3 + * + * @param direction: Select the SPI data transfer direction + * The parameter can be one of following values: + * @arg SPI_DIRECTION_RX: Selects Rx receive direction + * @arg SPI_DIRECTION_TX: Selects Tx transmission direction + * @retval None + */ +void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction) +{ + if(direction == SPI_DIRECTION_TX) + { + spi->CTRL1 |= SPI_DIRECTION_TX; + } + else + { + spi->CTRL1 &= SPI_DIRECTION_RX; + } +} + +/*! + * @brief Enables the specified SPI/I2S interrupts. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be one of following values: + * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt + * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt + * @arg SPI_I2S_INT_ERR: Error interrupt + * @retval None + */ +void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) +{ + spi->CTRL2 |= (interrupt >> 8); +} + +/*! + * @brief Disables the specified SPI/I2S interrupts. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be one of following values: + * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt + * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt + * @arg SPI_I2S_INT_ERR: Error interrupt + * @retval None + */ +void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) +{ + spi->CTRL2 &= ~(interrupt >> 8); +} + +/*! + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param flag: specifies the SPI/I2S flag to check + * The parameter can be one of following values: + * @arg SPI_FLAG_RXBNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXBE: Transmit buffer empty flag + * @arg I2S_FLAG_SCHDIR: Side Channel flag + * @arg I2S_FLAG_UDR: Underrun Error flag + * @arg SPI_FLAG_CRCE: CRC Error flag + * @arg SPI_FLAG_ME: Mode Error flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * + * @retval SET or RESET + */ +uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag) +{ + if((spi->STS & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the SPIx CRC Error flag + * + * @param spi: The SPIx can be 1,2,3 + * + * @param flag: only clears SPI_FLAG_CRCE(CRC Error flag) + * + * @retval None + * + * @note 1)SPI_FLAG_OVR: (OverRun error) flag is cleared by software sequence: + * a read operation to SPI_DATA register (SPI_I2S_RxData()) + * followed by a read operation to SPI_STS register (SPI_I2S_ReadStatusFlag()). + * 2)I2S_FLAG_UDR: (UnderRun error) flag is cleared: + * a read operation to SPI_STS register (SPI_I2S_ReadStatusFlag()). + * 3)SPI_FLAG_ME: (Mode Fault) flag is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). + */ +void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag) +{ + spi->STS_B.CRCEFLG = BIT_RESET; +} + +/*! + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param flag: specifies the SPI/I2S interrupt flag to check. + * The parameter can be one of following values: + * @arg SPI_I2S_INT_RXBNE: Receive buffer not empty interrupt flag + * @arg SPI_I2S_INT_TXBE: Transmit buffer empty interrupt flag + * @arg SPI_I2S_INT_OVR: Overrun interrupt flag + * @arg SPI_INT_CRCE: CRC Error interrupt flag + * @arg SPI_INT_ME: Mode Error interrupt flag + * @arg I2S_INT_UDR: Underrun Error interrupt flag + * + * @retval SET or RESET + */ +uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) +{ + uint32_t intEnable; + uint32_t intStatus; + + intEnable = (uint32_t)(spi->CTRL2 & (flag>>8)); + intStatus = (uint32_t)(spi->STS & flag); + + if (intEnable && intStatus) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the SPIx CRC Error interrupt flag + * + * @param spi: The SPIx can be 1,2,3 + * + * @param flag: only clears SPI_INT_CRCE(CRC Error interrupt flag) + * + * @retval None + * + * @note 1)SPI_I2S_INT_OVR: (OverRun interrupt error) flag is cleared by software sequence: + * a read operation to SPI_DATA register (SPI_I2S_RxData()) + * followed by a read operation to SPI_STS register (SPI_I2S_ReadIntFlag()). + * 2)I2S_INT_UDR: (UnderRun interrupt error) flag is cleared: + * a read operation to SPI_STS register (SPI_I2S_ReadIntFlag()). + * 3)SPI_INT_ME: (Mode interrupt Fault) flag is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). + */ +void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) +{ + spi->STS_B.CRCEFLG = BIT_RESET; +} + +/**@} end of group SPI_Fuctions*/ +/**@} end of group SPI_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c new file mode 100644 index 0000000000..343cb19770 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c @@ -0,0 +1,2133 @@ +/*! + * @file apm32f10x_tmr.c + * + * @brief This file provides all the TMR firmware functions. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_tmr.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup TMR_Driver TMR Driver + @{ +*/ + +/** @addtogroup TMR_Fuctions Fuctions + @{ +*/ + +static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); + +/*! + * @brief Deinitializes the TMRx peripheral registers to their default reset values. + * + * @param tmr: Select TMRx peripheral, The x can be 1 to 8 + * + * @retval None + * + * @note + */ +void TMR_Reset(TMR_T* tmr) +{ + if (tmr == TMR1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); + } + else if (tmr == TMR2) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); + } + else if (tmr == TMR3) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); + } + else if (tmr == TMR4) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR4); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR4); + } + else if (tmr == TMR5) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR5); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR5); + } + else if (tmr == TMR6) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); + } + else if (tmr == TMR7) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); + } + else if (tmr == TMR8) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR8); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR8); + } +} + +/*! + * @brief Initializes the base timer through the structure + * + * @param tmr: Select TMRx peripheral, The x can be 1 to 8 + * + * @param baseConfig: Pointer to a TMR_BaseConfig_T structure + * + * @retval None + */ +void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig) +{ + uint16_t temp; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + temp = tmr->CTRL1; + temp &= 0x038F; + temp |= baseConfig->countMode; + tmr->CTRL1 = temp; + } + + if ((tmr != TMR6) && (tmr != TMR7)) + { + tmr->CTRL1_B.CLKDIV = baseConfig->clockDivision; + } + + tmr->AUTORLD = baseConfig->period; + tmr->PSC = baseConfig->division; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->REPCNT = baseConfig->repetitionCounter; + } + tmr->CEG_B.BEG = 0x01; +} + +/*! + * @brief Configure channel 1 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC1Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OC1Config) +{ + tmr->CCEN_B.CC1EN = BIT_RESET; + + tmr->CCM1_COMPARE_B.CC1SEL = BIT_RESET; + tmr->CCM1_COMPARE_B.OC1MOD = OC1Config->mode; + + tmr->CCEN_B.CC1POL = OC1Config->polarity; + tmr->CCEN_B.CC1EN = OC1Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CCEN_B.CC1NPOL = OC1Config->nPolarity; + tmr->CCEN_B.CC1NEN = OC1Config->outputNState; + + tmr->CTRL2_B.OC1OIS = BIT_RESET; + tmr->CTRL2_B.OC1NOIS = BIT_RESET; + tmr->CTRL2_B.OC1OIS = OC1Config->idleState; + tmr->CTRL2_B.OC1NOIS = OC1Config->nIdleState; + } + tmr->CC1 = OC1Config->pulse; +} + +/*! + * @brief Configure channel 2 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC2Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OC2Config) +{ + tmr->CCEN_B.CC2EN = BIT_RESET; + + tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; + tmr->CCM1_COMPARE_B.CC2SEL = BIT_RESET; + tmr->CCM1_COMPARE_B.OC2MOD = OC2Config->mode; + + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN_B.CC2POL = OC2Config->polarity; + tmr->CCEN_B.CC2EN = OC2Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CCEN_B.CC2NPOL = BIT_RESET; + tmr->CCEN_B.CC2NPOL = OC2Config->nPolarity; + + tmr->CCEN_B.CC2NEN = BIT_RESET; + tmr->CCEN_B.CC2NEN = OC2Config->outputNState; + + tmr->CTRL2_B.OC2OIS = BIT_RESET; + tmr->CTRL2_B.OC2NOIS = BIT_RESET; + tmr->CTRL2_B.OC2OIS = OC2Config->idleState; + tmr->CTRL2_B.OC2NOIS = OC2Config->nIdleState; + } + tmr->CC2 = OC2Config->pulse; +} + +/*! + * @brief Configure channel 3 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC3Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OC3Config) +{ + tmr->CCEN_B.CC3EN = BIT_RESET; + + tmr->CCM2_COMPARE_B.OC3MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.CC3SEL = BIT_RESET; + tmr->CCM2_COMPARE_B.OC3MODE = OC3Config->mode; + + tmr->CCEN_B.CC3POL = BIT_RESET; + tmr->CCEN_B.CC3POL = OC3Config->polarity; + tmr->CCEN_B.CC3EN = OC3Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CCEN_B.CC3NPOL = BIT_RESET; + tmr->CCEN_B.CC3NPOL = OC3Config->nPolarity; + tmr->CCEN_B.CC3NEN = BIT_RESET; + tmr->CCEN_B.CC3NEN = OC3Config->outputNState; + + tmr->CTRL2_B.OC3OIS = BIT_RESET; + tmr->CTRL2_B.OC3NOIS = BIT_RESET; + tmr->CTRL2_B.OC3OIS = OC3Config->idleState; + tmr->CTRL2_B.OC3NOIS = OC3Config->nIdleState; + } + tmr->CC3 = OC3Config->pulse; +} + +/*! + * @brief Configure channel 4 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC4Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OC4Config) +{ + tmr->CCEN_B.CC4EN = BIT_RESET; + + tmr->CCM2_COMPARE_B.OC4MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.CC4SEL = BIT_RESET; + tmr->CCM2_COMPARE_B.OC4MODE = OC4Config->mode; + + tmr->CCEN_B.CC4POL = BIT_RESET; + tmr->CCEN_B.CC4POL = OC4Config->polarity; + tmr->CCEN_B.CC4EN = OC4Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CTRL2_B.OC4OIS = BIT_RESET; + tmr->CTRL2_B.OC4OIS = OC4Config->idleState; + } + tmr->CC4 = OC4Config->pulse; +} + +/*! + * @brief Configure Peripheral equipment + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICConfig: Pointer to a TMR_ICConfig_T structure + * + * @retval None + */ +void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig) +{ + if (ICConfig->channel == TMR_CHANNEL_1) + { + TI1Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC1Prescal(tmr, ICConfig->prescaler); + } + else if (ICConfig->channel == TMR_CHANNEL_2) + { + TI2Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC2Prescal(tmr, ICConfig->prescaler); + } + else if (ICConfig->channel == TMR_CHANNEL_3) + { + TI3Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC3Prescal(tmr, ICConfig->prescaler); + } + else if (ICConfig->channel == TMR_CHANNEL_4) + { + TI4Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC4Prescal(tmr, ICConfig->prescaler); + } +} + +/*! + * @brief Configures the: Break feature, dead time, Lock level, the IMOS + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param BDTConfig: Pointer to a TMR_BDTConfig_T structure + * + * @retval None + */ +void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig) +{ + tmr->BDT = (BDTConfig->IMOS)<<10 |\ + (BDTConfig->RMOS)<<11 |\ + (BDTConfig->lockLevel)<<8 |\ + (BDTConfig->deadTime) |\ + (BDTConfig->BRKState)<<12 |\ + (BDTConfig->BRKPolarity)<<13 |\ + (BDTConfig->automaticOutput)<<14; +} + +/*! + * @brief Initialize the Base timer with its default value. + * + * @param baseConfig: pointer to a TMR_BaseConfig_T + * + * @retval None + */ +void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig) +{ + baseConfig->period = 0xFFFF; + baseConfig->division = 0x0000; + baseConfig->clockDivision = TMR_CLOCK_DIV_1; + baseConfig->countMode = TMR_COUNTER_MODE_UP; + baseConfig->repetitionCounter = 0x0000; +} + +/*! + * @brief Initialize the OC timer with its default value. + * + * @param OCConfig: pointer to a TMR_OCConfig_T + * + * @retval None + */ +void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig) +{ + OCConfig->mode = TMR_OC_MODE_TMRING; + OCConfig->outputState = TMR_OC_STATE_DISABLE; + OCConfig->outputNState = TMR_OC_NSTATE_DISABLE; + OCConfig->pulse = 0x0000; + OCConfig->polarity = TMR_OC_POLARITY_HIGH; + OCConfig->nPolarity = TMR_OC_NPOLARITY_HIGH; + OCConfig->idleState = TMR_OC_IDLE_STATE_RESET; + OCConfig->nIdleState = TMR_OC_NIDLE_STATE_RESET; +} + +/*! + * @brief Initialize the IC timer with its default value. + * + * @param ICConfig: pointer to a TMR_ICConfig_T + * + * @retval None + */ +void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig) +{ + ICConfig->channel = TMR_CHANNEL_1; + ICConfig->polarity = TMR_IC_POLARITY_RISING; + ICConfig->selection = TMR_IC_SELECTION_DIRECT_TI; + ICConfig->prescaler = TMR_IC_PSC_1; + ICConfig->filter = 0x00; +} + +/*! + * @brief Initialize the BDT timer with its default value. + * + * @param BDTConfig: pointer to a TMR_BDTConfig_T + * + * @retval None + */ +void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig) +{ + BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE; + BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE; + BDTConfig->lockLevel = TMR_LOCK_LEVEL_OFF; + BDTConfig->deadTime = 0x00; + BDTConfig->BRKState = TMR_BRK_STATE_DISABLE; + BDTConfig->BRKPolarity = TMR_BRK_POLARITY_LOW; + BDTConfig->automaticOutput = TMR_AUTOMATIC_OUTPUT_DISABLE; +} + +/*! + * @brief Enable the specified TMR peripheral + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_Enable(TMR_T* tmr) +{ + tmr->CTRL1_B.CNTEN = ENABLE; +} + +/*! + * @brief Disable the specified TMR peripheral + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_Disable(TMR_T* tmr) +{ + tmr->CTRL1_B.CNTEN = DISABLE; +} + +/*! + * @brief Config of TMR to PWM + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param PWMConfig: pointer to a TMR_ICConfig_T + * + * @retval None + */ +void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig) +{ + uint16_t icpolarity = TMR_IC_POLARITY_RISING; + uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI; + + if (PWMConfig->polarity == TMR_IC_POLARITY_RISING) + { + icpolarity = TMR_IC_POLARITY_FALLING; + } + else + { + icpolarity = TMR_IC_POLARITY_RISING; + } + + if (PWMConfig->selection == TMR_IC_SELECTION_DIRECT_TI) + { + icselection = TMR_IC_SELECTION_INDIRECT_TI; + } + else + { + icselection = TMR_IC_SELECTION_DIRECT_TI; + } + + if (PWMConfig->channel == TMR_CHANNEL_1) + { + TI1Config(tmr, PWMConfig->polarity, PWMConfig->selection, PWMConfig->filter); + TMR_ConfigIC1Prescal(tmr, PWMConfig->prescaler); + TI2Config(tmr, icpolarity, icselection, PWMConfig->filter); + TMR_ConfigIC2Prescal(tmr, PWMConfig->prescaler); + } + else + { + TI2Config(tmr, PWMConfig->polarity, PWMConfig->selection, PWMConfig->filter); + TMR_ConfigIC2Prescal(tmr, PWMConfig->prescaler); + TI1Config(tmr, icpolarity, icselection, PWMConfig->filter); + TMR_ConfigIC1Prescal(tmr, PWMConfig->prescaler); + } +} + +/*! + * @brief Enable TMRx PWM output + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_EnablePWMOutputs(TMR_T* tmr) +{ + tmr->BDT_B.MOEN = ENABLE; +} + +/*! + * @brief Disable TMRx PWM output. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_DisablePWMOutputs(TMR_T* tmr) +{ + tmr->BDT_B.MOEN = DISABLE; +} + +/*! + * @brief Configures the TMRx's DMA interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param baseAddress: pointer to a TMR_DMA_BASE_T + * + * @param burstLength: pointer to a TMR_DMA_BURSTLENGTH_T + * + * @retval None + */ +void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength) +{ + tmr->DCTRL = baseAddress | burstLength; +} + +/*! + * @brief Enable TMRx Requests. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param souces: specifies the TMR DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces + * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces + * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces + * @retval None + * + * @note + */ +void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource) +{ + tmr->DIEN |= dmaSource; +} + +/*! + * @brief Disable TMRx Requests. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param souces: specifies the TMR DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces + * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces + * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces + * @retval None + * + * @note + */ +void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource) +{ + tmr->DIEN &= ~dmaSource; +} + +/*! + * @brief Configures the TMRx internal Clock + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_ConfigInternalClock(TMR_T* tmr) +{ + tmr->SMCTRL_B.SMFSEL = DISABLE; +} + +/*! + * @brief Configures the TMRx Internal Trigger as External Clock + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param triggerSource: specifies the TMR trigger souces + * The parameter can be one of following values: + * @arg TMR_TRIGGER_SOURCE_ITR0: TMR Internal Trigger 0 + * @arg TMR_TRIGGER_SOURCE_ITR1: TMR Internal Trigger 1 + * @arg TMR_TRIGGER_SOURCE_ITR2: TMR Internal Trigger 2 + * @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3 + * @retval None + */ +void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) +{ + TMR_SelectInputTrigger(tmr, triggerSource); + tmr->SMCTRL_B.SMFSEL = 0x07; +} + +/*! + * @brief Configures the TMRx Trigger as External Clock + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param triggerSource: specifies the TMR trigger souces + * The parameter can be one of following values: + * @arg TMR_TRIGGER_SOURCE_TI1F_ED: TI1 Edge Detector + * @arg TMR_TRIGGER_SOURCE_TI1FP1: Filtered Timer Input 1 + * @arg TMR_TRIGGER_SOURCE_TI2FP2: Filtered Timer Input 2 + * + * @param ICpolarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_IC_POLARITY_RISING: TMR IC polarity rising + * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter) +{ + if (triggerSource == 0x06) + { + TI2Config(tmr, ICpolarity, TMR_IC_SELECTION_DIRECT_TI, ICfilter); + } + else + { + TI1Config(tmr, ICpolarity, TMR_IC_SELECTION_DIRECT_TI, ICfilter); + } + + TMR_SelectInputTrigger(tmr, triggerSource); + tmr->SMCTRL_B.SMFSEL = 0x07; +} + +/*! + * @brief Configures the External clock Mode1 + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the external Trigger Prescaler + * The parameter can be one of following values: + * @arg TMR_EXTTRG_PSC_OFF: ETRP Prescaler OFF + * @arg TMR_EXTTRG_PSC_DIV2: ETRP frequency divided by 2 + * @arg TMR_EXTTRG_PSC_DIV4: ETRP frequency divided by 4 + * @arg TMR_EXTTRG_PSC_DIV8: ETRP frequency divided by 8 + * + * @param polarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_EXTTRG_POL_INVERTED: Active low or falling edge active + * @arg TMR_EXTTGR_POL_NONINVERTED: Active high or rising edge active + * + * @param filter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter) +{ + TMR_ConfigETR(tmr, prescaler, polarity, filter); + tmr->SMCTRL_B.SMFSEL = BIT_RESET; + tmr->SMCTRL_B.SMFSEL = 0x07; + tmr->SMCTRL_B.TRGSEL = 0x07; +} + +/*! + * @brief Configures the External clock Mode2 + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the external Trigger Prescaler + * The parameter can be one of following values: + * @arg TMR_EXTTRG_PSC_OFF: ETRP Prescaler OFF + * @arg TMR_EXTTRG_PSC_DIV2: ETRP frequency divided by 2 + * @arg TMR_EXTTRG_PSC_DIV4: ETRP frequency divided by 4 + * @arg TMR_EXTTRG_PSC_DIV8: ETRP frequency divided by 8 + * + * @param polarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_EXTTRG_POL_INVERTED: Active low or falling edge active + * @arg TMR_EXTTGR_POL_NONINVERTED: Active high or rising edge active + * + * @param filter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter) +{ + TMR_ConfigETR(tmr, prescaler, polarity, filter); + tmr->SMCTRL_B.ECEN = ENABLE; +} +/*! + * @brief Configures the TMRx External Trigger (ETR). + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the external Trigger Prescaler + * The parameter can be one of following values: + * @arg TMR_EXTTRG_PSC_OFF: ETRP Prescaler OFF + * @arg TMR_EXTTRG_PSC_DIV2: ETRP frequency divided by 2 + * @arg TMR_EXTTRG_PSC_DIV4: ETRP frequency divided by 4 + * @arg TMR_EXTTRG_PSC_DIV8: ETRP frequency divided by 8 + * + * @param polarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_EXTTRG_POL_INVERTED: Active low or falling edge active + * @arg TMR_EXTTGR_POL_NONINVERTED: Active high or rising edge active + * + * @param filter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter) +{ + tmr->SMCTRL &= 0x00FF; + tmr->SMCTRL_B.ETPCFG = prescaler; + tmr->SMCTRL_B.ETPOL = polarity; + tmr->SMCTRL_B.ETFCFG = filter; +} + +/*! + * @brief Configures the TMRx prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the prescaler Register value + * + * @param pscReloadMode: specifies the TMR prescaler Reload mode + * The parameter can be one of following values: + * @arg TMR_PRESCALER_RELOAD_UPDATA: The Prescaler is loaded at the update event + * @arg TMR_PRESCALER_RELOAD_IMMEDIATE: The Prescaler is loaded immediately + * @retval None + */ +void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode) +{ + tmr->PSC = prescaler; + tmr->CEG_B.UEG = pscReloadMode; +} + +/*! + * @brief Config counter mode + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param countMode:specifies the Counter Mode to be used + * The parameter can be one of following values: + * @arg TMR_COUNTER_MODE_UP: Timer Up Counting Mode + * @arg TMR_COUNTER_MODE_DOWN: Timer Down Counting Mode + * @arg TMR_COUNTER_MODE_CENTERALIGNED1: Timer Center Aligned Mode1 + * @arg TMR_COUNTER_MODE_CENTERALIGNED2: Timer Center Aligned Mode2 + * @arg TMR_COUNTER_MODE_CENTERALIGNED3: Timer Center Aligned Mode3 + * @retval None + */ +void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode) +{ + tmr->CTRL1_B.CNTDIR = BIT_RESET; + tmr->CTRL1_B.CAMSEL = BIT_RESET; + tmr->CTRL1 |= countMode; +} + +/*! + * @brief Selects the Input Trigger source + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param triggerSource: specifies the Input Trigger source + * The parameter can be one of following values: + * @arg TMR_TRIGGER_SOURCE_ITR0: Internal Trigger 0 + * @arg TMR_TRIGGER_SOURCE_ITR1: Internal Trigger 1 + * @arg TMR_TRIGGER_SOURCE_ITR2: Internal Trigger 2 + * @arg TMR_TRIGGER_SOURCE_ITR3: Internal Trigger 3 + * @arg TMR_TRIGGER_SOURCE_TI1F_ED: TI1 Edge Detector + * @arg TMR_TRIGGER_SOURCE_TI1FP1: Filtered Timer Input 1 + * @arg TMR_TRIGGER_SOURCE_TI2FP2: Filtered Timer Input 2 + * @arg TMR_TRIGGER_SOURCE_ETRF: External Trigger input + * + * @retval None + */ +void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) +{ + tmr->SMCTRL_B.TRGSEL = BIT_RESET; + tmr->SMCTRL_B.TRGSEL = triggerSource; +} + +/*! + * @brief Configures the Encoder Interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param encodeMode: specifies the Encoder Mode + * The parameter can be one of following values: + * @arg TMR_ENCODER_MODE_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level + * @arg TMR_ENCODER_MODE_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level + * @arg TMR_ENCODER_MODE_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input + * + * @param IC1Polarity: specifies the TMR IC1 polarity + * The parameter can be one of following values: + * @arg TMR_IC_POLARITY_RISING: TMR IC polarity rising + * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling + * + * @param IC2Polarity: specifies the TMR IC2 polarity + * The parameter can be one of following values: + * @arg TMR_IC_POLARITY_RISING: TMR IC polarity rising + * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling + * @retval None + */ +void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, + TMR_IC_POLARITY_T IC2Polarity) +{ + tmr->SMCTRL_B.SMFSEL = BIT_RESET; + tmr->SMCTRL_B.SMFSEL = encodeMode; + + tmr->CCM1_CAPTURE_B.CC1SEL = BIT_RESET ; + tmr->CCM1_CAPTURE_B.CC2SEL = BIT_RESET ; + tmr->CCM1_CAPTURE_B.CC1SEL = 0x01 ; + tmr->CCM1_CAPTURE_B.CC2SEL = 0x01 ; + + tmr->CCEN_B.CC1POL = BIT_RESET; + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN |= ((IC1Polarity | (IC2Polarity << 4))); +} + +/*! + * @brief Forces the output 1 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * @retval None + */ +void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM1_COMPARE_B.OC1MOD = BIT_RESET; + tmr->CCM1_COMPARE_B.OC1MOD = forcesAction; +} + +/*! + * @brief Forces the output 2 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * @retval None + */ +void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; + tmr->CCM1_COMPARE_B.OC2MOD = forcesAction; +} + +/*! + * @brief Forces the output 3 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * + * @retval None + */ +void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM2_COMPARE_B.OC3MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.OC3MODE = forcesAction; +} + +/*! + * @brief Forces the output 4 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * + * @retval None + */ +void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM2_COMPARE_B.OC4MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.OC4MODE = forcesAction; +} + +/*! + * @brief Enables peripheral Preload register on AUTORLD. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_EnableAUTOReload(TMR_T* tmr) +{ + tmr->CTRL1_B.ARPEN = ENABLE; +} + +/*! + * @brief Disable peripheral Preload register on AUTORLD. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_DisableAUTOReload(TMR_T* tmr) +{ + tmr->CTRL1_B.ARPEN = DISABLE; +} + +/*! + * @brief Enable Selects the TMR peripheral Commutation event. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_EnableSelectCOM(TMR_T* tmr) +{ + tmr->CTRL2_B.CCUSEL = ENABLE; +} +/*! + * @brief Disable Selects the TMR peripheral Commutation event. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_DisableSelectCOM(TMR_T* tmr) +{ + tmr->CTRL2_B.CCUSEL = DISABLE; +} + +/*! + * @brief Enable Capture Compare DMA source. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_EnableCCDMA(TMR_T* tmr) +{ + tmr->CTRL2_B.CCDSEL = ENABLE; +} + +/*! + * @brief Disable Capture Compare DMA source. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_DisableCCDMA(TMR_T* tmr) +{ + tmr->CTRL2_B.CCDSEL = DISABLE; +} + +/*! + * @brief Enable Capture Compare Preload Control bit. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_EnableCCPreload(TMR_T* tmr) +{ + tmr->CTRL2_B.CCPEN = ENABLE; +} + +/*! + * @brief Disable Capture Compare Preload Control bit. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_DisableCCPreload(TMR_T* tmr) +{ + tmr->CTRL2_B.CCPEN = DISABLE; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM1. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + */ +void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM1_COMPARE_B.OC1PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM2. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + */ +void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM1_COMPARE_B.OC2PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM3. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + */ +void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM2_COMPARE_B.OC3PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM4. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval Nonee + */ +void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM2_COMPARE_B.OC4PEN = OCPreload; +} + +/*! + * @brief Configures the Output Compare 1 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM1_COMPARE_B.OC1FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 2 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM1_COMPARE_B.OC2FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 2 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM2_COMPARE_B.OC3FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 4 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM2_COMPARE_B.OC4FEN = OCFast; +} + +/*! + * @brief Clears or safeguards the OCREF1 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM1_COMPARE_B.OC1CEN = OCClear; +} + +/*! + * @brief Clears or safeguards the OCREF2 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM1_COMPARE_B.OC2CEN = OCClear; +} + +/*! + * @brief Clears or safeguards the OCREF3 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM2_COMPARE_B.OC3CEN = OCClear; +} + +/*! + * @brief Clears or safeguards the OCREF4 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM2_COMPARE_B.OC4CEN = OCClear; +} + +/*! + * @brief Configures the channel 1 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC1 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval Nonee + */ +void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC1POL = polarity; +} + +/*! + * @brief Configures the channel 1 nPolarity. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param nPolarity: specifies the OC1 nPolarity + * The parameter can be one of following values: + * @arg TMR_OC_NPOLARITY_HIGH: Output Compare active high + * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +{ + tmr->CCEN_B.CC1NPOL = nPolarity; +} + +/*! + * @brief Configures the channel 2 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC2 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC2POL = polarity; +} + +/*! + * @brief Configures the channel 2 nPolarity. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param nPolarity: specifies the OC2 nPolarity + * The parameter can be one of following values: + * @arg TMR_OC_NPOLARITY_HIGH: Output Compare active high + * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +{ + tmr->CCEN_B.CC2NPOL = nPolarity; +} + +/*! + * @brief Configures the channel 3 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC3 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC3POL = polarity; +} + +/*! + * @brief Configures the channel 3 nPolarity. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param nPolarity: specifies the OC3 nPolarity + * The parameter can be one of following values: + * @arg TMR_OC_NPOLARITY_HIGH: Output Compare active high + * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +{ + tmr->CCEN_B.CC3NPOL = nPolarity; +} + +/*! + * @brief Configures the channel 4 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC4 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC4POL = polarity; +} + +/*! + * @brief Enables the Capture Compare Channel x. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @arg TMR_CHANNEL_4: Timer Channel 4 + * @retval None + */ +void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN |= BIT_SET << channel; +} + +/*! + * @brief Disables the Capture Compare Channel x. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @arg TMR_CHANNEL_4: Timer Channel 4 + * @retval None + */ +void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN &= BIT_RESET << channel; +} + +/*! + * @brief Enables the Capture Compare Channelx N. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @retval None + */ +void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN |= 0x04 << channel; +} + +/*! + * @brief Disables the Capture Compare Channelx N. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @retval None + */ +void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN &= BIT_RESET << channel; +} + +/*! + * @brief Selects the Output Compare Mode. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @arg TMR_CHANNEL_4: Timer Channel 4 + * + * @param mode: specifies the Output Compare Mode + * The parameter can be one of following values: + * @arg TMR_OC_MODE_TMRING + * @arg TMR_OC_MODE_ACTIVE + * @arg TMR_OC_MODE_INACTIVE + * @arg TMR_OC_MODE_TOGGEL + * @arg TMR_OC_MODE_LOWLEVEL + * @arg TMR_OC_MODE_HIGHLEVEL + * @arg TMR_OC_MODE_PWM1 + * @arg TMR_OC_MODE_PWM2 + * @retval None + */ +void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) +{ + tmr->CCEN &= BIT_RESET << channel; + + if (channel == TMR_CHANNEL_1) + { + tmr->CCM1_COMPARE_B.OC1MOD = mode; + } + else if (channel == TMR_CHANNEL_2) + { + tmr->CCM1_COMPARE_B.OC2MOD = mode; + } + else if (channel == TMR_CHANNEL_3) + { + tmr->CCM2_COMPARE_B.OC3MODE = mode; + } + else if (channel == TMR_CHANNEL_4) + { + tmr->CCM2_COMPARE_B.OC4MODE = mode; + } +} + +/*! + * @brief Enable the TMRx update event + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_EnableNoUpdate(TMR_T* tmr) +{ + tmr->CTRL1_B.UD = ENABLE; +} + +/*! + * @brief Disable the TMRx update event + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_DisableNoUpdate(TMR_T* tmr) +{ + tmr->CTRL1_B.UD = DISABLE; +} + +/*! + * @brief Configures the Update Request Interrupt source + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param updateSource: Config the Update source + * The parameter can be one of following values: + * @arg TMR_UPDATE_SOURCE_GLOBAL + * @arg TMR_UPDATE_SOURCE_REGULAR + * @retval None + */ +void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource) +{ + if (updateSource != TMR_UPDATE_SOURCE_GLOBAL) + { + tmr->CTRL1_B.URSSEL = BIT_SET; + } + else + { + tmr->CTRL1_B.URSSEL = BIT_RESET; + } +} + +/*! + * @brief Enables Hall sensor interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_EnableHallSensor(TMR_T* tmr) +{ + tmr->CTRL2_B.TI1SEL = ENABLE; +} + +/*! + * @brief Disable Hall sensor interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_DisableHallSensor(TMR_T* tmr) +{ + tmr->CTRL2_B.TI1SEL = DISABLE; +} + +/*! + * @brief Selects the Sing pulse Mode. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param singlePulseMode: specifies the Single Pulse Mode + * The parameter can be one of following values: + * @arg TMR_SPM_REPETITIVE + * @arg TMR_SPM_SINGLE + * @retval None + */ +void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode) +{ + tmr->CTRL1_B.SPMEN = singlePulseMode; +} + +/*! + * @brief Selects the Trigger Output Mode. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param TRGOSource: specifies the Trigger Output source + * The parameter can be one of following values: + * @arg TMR_TRGO_SOURCE_RESET + * @arg TMR_TRGO_SOURCE_ENABLE + * @arg TMR_TRGO_SOURCE_UPDATE + * The under is not for TMR6 and TMR7 + * @arg TMR_TRGO_SOURCE_OC1 + * @arg TMR_TRGO_SOURCE_OC1REF + * @arg TMR_TRGO_SOURCE_OC2REF + * @arg TMR_TRGO_SOURCE_OC3REF + * @arg TMR_TRGO_SOURCE_OC4REF + * @retval None + */ +void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource) +{ + tmr->CTRL2_B.MMSEL = TRGOSource; +} + +/*! + * @brief Selects the Slave Mode. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param slaveMode: specifies the Timer Slave Mode. + * The parameter can be one of following values: + * @arg TMR_SLAVE_MODE_RESET + * @arg TMR_SLAVE_MODE_GATED + * @arg TMR_SLAVE_MODE_TRIGGER + * @arg TMR_SLAVE_MODE_EXTERNALL + * @retval None + */ +void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode) +{ + tmr->SMCTRL_B.SMFSEL = slaveMode; +} + +/*! + * @brief Enable the Master Slave Mode + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_EnableMasterSlaveMode(TMR_T* tmr) +{ + tmr->SMCTRL_B.MSMEN = ENABLE; +} + +/*! + * @brief Disable the Master Slave Mode + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_DisableMasterSlaveMode(TMR_T* tmr) +{ + tmr->SMCTRL_B.MSMEN = DISABLE; +} + +/*! + * @brief Configs the Counter Register value + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param counter: Counter register new value + * + * @retval None + */ +void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter) +{ + tmr->CNT = counter; +} + +/*! + * @brief Configs the AutoReload Register value + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param autoReload: autoReload register new value + * + * @retval None + */ +void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload) +{ + tmr->AUTORLD = autoReload; +} + +/*! + * @brief Configs the Capture Compare1 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare1: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1) +{ + tmr->CC1 = compare1; +} + +/*! + * @brief Configs the Capture Compare2 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare2: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2) +{ + tmr->CC2 = compare2; +} + +/*! + * @brief Configs the Capture Compare3 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare3: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3) +{ + tmr->CC3 = compare3; +} + +/*! + * @brief Configs the Capture Compare4 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare4: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4) +{ + tmr->CC4 = compare4; +} + +/*! + * @brief Configs the TMRx Input Capture 1 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel1 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM1_CAPTURE_B.IC1PSC = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC1PSC = prescaler; +} +/*! + * @brief Sets the TMRx Input Capture 2 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel2 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM1_CAPTURE_B.IC2PSC = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC2PSC = prescaler; +} + +/*! + * @brief Configs the TMRx Input Capture 3 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel3 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM2_CAPTURE_B.IC3PSC = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC3PSC = prescaler; +} + +/*! + * @brief Configs the TMRx Input Capture 4 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel4 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM2_CAPTURE_B.IC4PSC = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC4PSC = prescaler; +} + +/*! + * @brief Configs the Clock Division value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param clockDivision: specifies the clock division value. + * The parameter can be one of following values: + * @arg TMR_CLOCK_DIV_1: TDTS = Tck_tim + * @arg TMR_CLOCK_DIV_2: TDTS = 2*Tck_tim + * @arg TMR_CLOCK_DIV_4: TDTS = 4*Tck_tim + * @retval None + */ +void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision) +{ + tmr->CTRL1_B.CLKDIV = clockDivision; +} + +/*! + * @brief Read Input Capture 1 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 1 Register value. + */ +uint16_t TMR_ReadCaputer1(TMR_T* tmr) +{ + return tmr->CC1; +} + +/*! + * @brief Read Input Capture 2 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 2 Register value. + */ +uint16_t TMR_ReadCaputer2(TMR_T* tmr) +{ + return tmr->CC2; +} + +/*! + * @brief Read Input Capture 3 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 3 Register value. + */ +uint16_t TMR_ReadCaputer3(TMR_T* tmr) +{ + return tmr->CC3; +} + +/*! + * @brief Read Input Capture 4 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 4 Register value. + */ +uint16_t TMR_ReadCaputer4(TMR_T* tmr) +{ + return tmr->CC4; +} + +/*! + * @brief Read the TMRx Counter value. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval Counter Register value. + */ +uint16_t TMR_ReadCounter(TMR_T* tmr) +{ + return tmr->CNT; +} + +/*! + * @brief Read the TMRx Prescaler value. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval Prescaler Register value. + */ +uint16_t TMR_ReadPrescaler(TMR_T* tmr) +{ + return tmr->PSC; +} + +/*! + * @brief Enable intterupts + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt) +{ + tmr->DIEN |= interrupt; +} + +/*! + * @brief Disable intterupts + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt) +{ + tmr->DIEN &= ~interrupt; +} + +/*! + * @brief Configures the TMRx event to be generate by software. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param eventSources: specifies the TMR event sources + * The parameter can be any combination of following values: + * @arg TMR_EVENT_UPDATE: Timer update Interrupt source + * @arg TMR_EVENT_CC1: Timer Capture Compare 1 Event source + * @arg TMR_EVENT_CC2: Timer Capture Compare 1 Event source + * @arg TMR_EVENT_CC3: Timer Capture Compare 3 Event source + * @arg TMR_EVENT_CC4: Timer Capture Compare 4 Event source + * @arg TMR_EVENT_COM: Timer Commutation Event source (Only for TMR1 and TMR8) + * @arg TMR_EVENT_TRG: Timer Trigger Event source + * @arg TMR_EVENT_BRK: Timer Break Event source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE. + */ +void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources) +{ + tmr->CEG = eventSources; +} + +/*! + * @brief Check whether the flag is set or reset + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_FLAG_UPDATE: Timer update Flag + * @arg TMR_FLAG_CC1: Timer Capture Compare 1 Flag + * @arg TMR_FLAG_CC2: Timer Capture Compare 2 Flag + * @arg TMR_FLAG_CC3: Timer Capture Compare 3 Flag + * @arg TMR_FLAG_CC4: Timer Capture Compare 4 Flag + * @arg TMR_FLAG_COM: Timer Commutation Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_TRG: Timer Trigger Flag + * @arg TMR_FLAG_BRK: Timer Break Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_CC1RC: Timer Capture Compare 1 Repetition Flag + * @arg TMR_FLAG_CC2RC: Timer Capture Compare 2 Repetition Flag + * @arg TMR_FLAG_CC3RC: Timer Capture Compare 3 Repetition Flag + * @arg TMR_FLAG_CC4RC: Timer Capture Compare 4 Repetition Flag + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. + */ +uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag) +{ + if ((tmr->STS & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the TMR's pending flags. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_FLAG_UPDATE: Timer update Flag + * @arg TMR_FLAG_CC1: Timer Capture Compare 1 Flag + * @arg TMR_FLAG_CC2: Timer Capture Compare 2 Flag + * @arg TMR_FLAG_CC3: Timer Capture Compare 3 Flag + * @arg TMR_FLAG_CC4: Timer Capture Compare 4 Flag + * @arg TMR_FLAG_COM: Timer Commutation Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_TRG: Timer Trigger Flag + * @arg TMR_FLAG_BRK: Timer Break Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_CC1RC: Timer Capture Compare 1 Repetition Flag + * @arg TMR_FLAG_CC2RC: Timer Capture Compare 2 Repetition Flag + * @arg TMR_FLAG_CC3RC: Timer Capture Compare 3 Repetition Flag + * @arg TMR_FLAG_CC4RC: Timer Capture Compare 4 Repetition Flag + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. + */ +void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag) +{ + tmr->STS = ~flag; +} + +/*! + * @brief Check whether the ITflag is set or reset + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be one of following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag) +{ + if (((tmr->STS & flag) != RESET ) && ((tmr->DIEN & flag) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the TMR's interrupt pending bits. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag) +{ + tmr->STS = ~flag; +} + +/*! + * @brief Configure the TI1 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC1EN = BIT_RESET; + + tmr->CCM1_CAPTURE_B.CC1SEL = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC1F = BIT_RESET; + tmr->CCM1_CAPTURE_B.CC1SEL = ICselection; + tmr->CCM1_CAPTURE_B.IC1F = ICfilter; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + tmr->CCEN_B.CC1POL = BIT_RESET; + tmr->CCEN_B.CC1EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= ICpolarity; + tmr->CCEN = tmpchctrl; + } + else + { + tmr->CCEN_B.CC1POL = BIT_RESET; + tmr->CCEN_B.CC1NPOL = BIT_RESET; + tmr->CCEN_B.CC1EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= ICpolarity; + tmr->CCEN = tmpchctrl; + } +} + +/*! + * @brief Configure the TI2 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC2EN = BIT_RESET; + + tmr->CCM1_CAPTURE_B.CC2SEL = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC2F = BIT_RESET; + tmr->CCM1_CAPTURE_B.CC2SEL = ICselection; + tmr->CCM1_CAPTURE_B.IC2F = ICfilter; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN_B.CC2EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 4); + tmr->CCEN = tmpchctrl; + } + else + { + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN_B.CC2NPOL = BIT_RESET; + tmr->CCEN_B.CC2EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 4); + tmr->CCEN = tmpchctrl; + } +} + +/*! + * @brief Configure the TI3 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC3EN = BIT_RESET; + + tmr->CCM2_CAPTURE_B.CC3SEL = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC3F = BIT_RESET; + tmr->CCM2_CAPTURE_B.CC3SEL = ICselection; + tmr->CCM2_CAPTURE_B.IC3F = ICfilter; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + tmr->CCEN_B.CC3POL = BIT_RESET; + tmr->CCEN_B.CC3EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 8); + tmr->CCEN = tmpchctrl; + } + else + { + tmr->CCEN_B.CC3POL = BIT_RESET; + tmr->CCEN_B.CC3NPOL = BIT_RESET; + tmr->CCEN_B.CC3EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 8); + tmr->CCEN = tmpchctrl; + } +} + +/*! + * @brief Configure the TI4 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC4EN = BIT_RESET; + + tmr->CCM2_CAPTURE_B.CC4SEL = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC4F = BIT_RESET; + tmr->CCM2_CAPTURE_B.CC4SEL = ICselection; + tmr->CCM2_CAPTURE_B.IC4F = ICfilter; + + tmr->CCEN_B.CC4POL = BIT_RESET; + tmr->CCEN_B.CC4EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 12); + tmr->CCEN = tmpchctrl; +} + +/**@} end of group TMR_Fuctions*/ +/**@} end of group TMR_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c new file mode 100644 index 0000000000..23eb7fa355 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c @@ -0,0 +1,816 @@ +/*! + * @file apm32f10x_usart.c + * + * @brief This file provides all the USART firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_usart.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup USART_Driver USART Driver + @{ +*/ + +/** @addtogroup USART_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset usart peripheral registers to their default reset values + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Reset(USART_T* usart) +{ + if (USART1 == usart) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_USART1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_USART1); + } + else if (USART2 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART2); + } + else if (USART3 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART3); + } + else if (UART4 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_UART4); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_UART4); + } + else if (UART5 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_UART5); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_UART5); + } +} + +/*! + * @brief Config the USART peripheral according to the specified parameters in the usartConfig + * + * @param uart: Select the USART or the UART peripheral + * + * @param usartConfig: pointer to a USART_Config_T structure + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Config(USART_T* uart, USART_Config_T* usartConfig) +{ + uint32_t temp, fCLK, intDiv, fractionalDiv; + + temp = uart->CTRL1; + temp &= 0xE9F3; + temp |= usartConfig->mode | usartConfig->parity | usartConfig->wordLength; + uart->CTRL1 = temp; + + temp = uart->CTRL2; + temp &= 0xCFFF; + temp |= usartConfig->stopBits; + uart->CTRL2 = temp; + + temp = uart->CTRL3; + temp &= 0xFCFF; + temp |= (uint32_t)usartConfig->hardwareFlow; + uart->CTRL3 = temp; + + if (uart == USART1) + { + RCM_ReadPCLKFreq(NULL, &fCLK); + } + else + { + RCM_ReadPCLKFreq(&fCLK, NULL); + } + + intDiv = ((25 * fCLK) / (4 * (usartConfig->baudRate))); + temp = (intDiv / 100) << 4; + fractionalDiv = intDiv - (100 * (temp >> 4)); + temp |= ((((fractionalDiv * 16) + 50) / 100)) & ((uint8_t)0x0F); + + uart->BR = temp; +} + +/*! + * @brief Fills each USART_InitStruct member with its default value + * + * @param usartConfig: pointer to a USART_Config_T structure which will be initialized + * + * @retval None + */ +void USART_ConfigStructInit(USART_Config_T* usartConfig) +{ + usartConfig->baudRate = 9600; + usartConfig->wordLength = USART_WORD_LEN_8B; + usartConfig->stopBits = USART_STOP_BIT_1; + usartConfig->parity = USART_PARITY_NONE ; + usartConfig->mode = USART_MODE_TX_RX; + usartConfig->hardwareFlow = USART_HARDWARE_FLOW_NONE; +} + +/*! + * @brief Configuration communication clock + * + * @param usart: Select the USART or the UART peripheral + * + * @param clockConfig: Pointer to a USART_clockConfig_T structure + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3 + */ +void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig) +{ + usart->CTRL2_B.CLKEN = clockConfig->clock; + usart->CTRL2_B.CPHA = clockConfig->phase; + usart->CTRL2_B.CPOL = clockConfig->polarity; + usart->CTRL2_B.LBCPOEN = clockConfig->lastBit; +} + +/*! + * @brief Fills each clockConfig member with its default value + * + * @param clockConfig: Pointer to a USART_clockConfig_T structure + * + * @retval None + * + * @note + */ +void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig) +{ + clockConfig->clock = USART_CLKEN_DISABLE; + clockConfig->phase = USART_CLKPHA_1EDGE; + clockConfig->polarity = USART_CLKPOL_LOW; + clockConfig->lastBit = USART_LBCP_DISABLE; +} + +/*! + * @brief Enables the specified USART peripheral + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Enable(USART_T* usart) +{ + usart->CTRL1_B.UEN = BIT_SET; +} + +/*! + * @brief Disable the specified USART peripheral + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Disable(USART_T* usart) +{ + usart->CTRL1_B.UEN = BIT_RESET; +} + +/*! + * @brief Enables the USART DMA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @param dmaReq: Specifies the DMA request + * This parameter can be one of the following values: + * @arg USART_DMA_TX: USART DMA receive request + * @arg USART_DMA_RX: USART DMA transmit request + * @arg USART_DMA_TX_RX: USART DMA transmit/receive request + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq) +{ + usart->CTRL3 |= dmaReq; +} + +/*! + * @brief Disable the USART DMA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @param dmaReq: Specifies the DMA request + * This parameter can be one of the following values: + * @arg USART_DMA_TX: USART DMA receive request + * @arg USART_DMA_RX: USART DMA transmit request + * @arg USART_DMA_TX_RX: USART DMA transmit/receive request + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq) +{ + usart->CTRL3 &= (uint32_t)~dmaReq; +} + +/*! + * @brief Configures the address of the USART node + * + * @param usart: Select the USART or the UART peripheral + * + * @param address: Indicates the address of the USART node + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Address(USART_T* usart, uint8_t address) +{ + usart->CTRL2_B.ADDR = address; +} + +/*! + * @brief Selects the USART WakeUp method. + * + * @param usart: Select the USART or the UART peripheral + * + * @param wakeup: Specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_WAKEUP_IDLE_LINE: WakeUp by an idle line detection + * @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup) +{ + usart->CTRL1_B.WUPMCFG = wakeup; +} + +/*! + * @brief Enable USART Receiver in mute mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableMuteMode(USART_T* usart) +{ + usart->CTRL1_B.RXMUTEEN = BIT_SET; +} + +/*! + * @brief Disable USART Receiver in active mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableMuteMode(USART_T* usart) +{ + usart->CTRL1_B.RXMUTEEN = BIT_RESET; +} + +/*! + * @brief Sets the USART LIN Break detection length + * + * @param usart: Select the USART or the UART peripheral + * + * @param length: Specifies the LIN break detection length + * This parameter can be one of the following values: + * @arg USART_LBDL_10B: 10-bit break detection + * @arg USART_LBDL_10B: 11-bit break detection + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length) +{ + usart->CTRL2_B.LBDLCFG = length; +} + +/*! + * @brief Enables the USART LIN MODE + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableLIN(USART_T* usart) +{ + usart->CTRL2_B.LINMEN = BIT_SET; +} + +/*! + * @brief Disable the USART LIN MODE + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableLIN(USART_T* usart) +{ + usart->CTRL2_B.LINMEN = BIT_RESET; +} + +/*! + * @brief Transmitter Enable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableTx(USART_T* usart) +{ + usart->CTRL1_B.TXEN = BIT_SET; +} + +/*! + * @brief Transmitter Disable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableTx(USART_T* usart) +{ + usart->CTRL1_B.TXEN = BIT_RESET; +} + +/*! + * @brief Receiver enable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableRx(USART_T* usart) +{ + usart->CTRL1_B.RXEN = BIT_SET; +} + +/*! + * @brief Receiver disable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableRx(USART_T* usart) +{ + usart->CTRL1_B.RXEN = BIT_RESET; +} + +/*! + * @brief Transmits single data + * + * @param usart: Select the USART or the UART peripheral + * + * @param data: the data to transmit + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_TxData(USART_T* usart, uint16_t data) +{ + usart->DATA_B.DATA = data; +} + +/*! + * @brief Returns the most recent received data + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +uint16_t USART_RxData(USART_T* usart) +{ + return (uint16_t)(usart->DATA_B.DATA); +} + +/*! + * @brief Transmits break characters + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_TxBreak(USART_T* usart) +{ + usart->CTRL1_B.TXBF = BIT_SET; +} + +/*! + * @brief Sets the specified USART guard time + * + * @param usart: Select the USART or the UART peripheral + * + * @param guardTime: Specifies the guard time + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3 + */ +void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime) +{ + usart->GTPSC_B.GRDT = guardTime; +} + +/*! + * @brief Sets the system clock divider number + * + * @param usart: Select the USART or the UART peripheral + * + * @param div: specifies the divider number + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3 + */ +void USART_ConfigPrescaler(USART_T* usart, uint8_t div) +{ + usart->GTPSC_B.PSC = div; +} + +/*! + * @brief Enables the USART Smart Card mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_EnableSmartCard(USART_T* usart) +{ + usart->CTRL3_B.SCEN = BIT_SET; +} + +/*! + * @brief Disable the USART Smart Card mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_DisableSmartCard(USART_T* usart) +{ + usart->CTRL3_B.SCEN = BIT_RESET; +} + +/*! + * @brief Enables NACK transmission + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_EnableSmartCardNACK(USART_T* usart) +{ + usart->CTRL3_B.SCNACKEN = BIT_SET; +} + +/*! + * @brief Disable NACK transmission + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_DisableSmartCardNACK(USART_T* usart) +{ + usart->CTRL3_B.SCNACKEN = BIT_RESET; +} + +/*! + * @brief Enables USART Half Duplex communication + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableHalfDuplex(USART_T* usart) +{ + usart->CTRL3_B.HDEN = BIT_SET; +} + +/*! + * @brief Disable USART Half Duplex communication + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableHalfDuplex(USART_T* usart) +{ + usart->CTRL3_B.HDEN = BIT_RESET; +} + +/*! + * @brief Configures the USART's IrDA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @param IrDAMode: Specifies the IrDA mode + * This parameter can be one of the following values: + * @arg USART_IRDALP_NORMAL: Normal + * @arg USART_IRDALP_LOWPOWER: Low-Power + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode) +{ + usart->CTRL3_B.IRLPEN = IrDAMode; +} + +/*! + * @brief Enables the USART's IrDA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableIrDA(USART_T* usart) +{ + usart->CTRL3_B.IREN = BIT_SET; +} + +/*! + * @brief Disable the USART's IrDA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableIrDA(USART_T* usart) +{ + usart->CTRL3_B.IREN = BIT_RESET; +} + +/*! + * @brief Enable the specified USART interrupts + * + * @param usart: Select the USART or the UART peripheral + * + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_PE: Parity error interrupt + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt) +{ + uint32_t temp; + + temp = (uint32_t)(interrupt & 0xffff); + + if (interrupt & 0X10000) + { + usart->CTRL1 |= temp; + } + + if (interrupt & 0X20000) + { + usart->CTRL2 |= temp; + } + + if (interrupt & 0X40000) + { + usart->CTRL3 |= temp; + } +} + +/*! + * @brief Disables the specified USART interrupts + * + * @param usart: Select the USART or the UART peripheral + * + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_PE: Parity error interrupt + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt) +{ + uint32_t temp; + + temp = (uint32_t)~(interrupt & 0xffff); + + if (interrupt & 0X10000) + { + usart->CTRL1 &= temp; + } + + if (interrupt & 0X20000) + { + usart->CTRL2 &= temp; + } + + if (interrupt & 0X40000) + { + usart->CTRL3 &= temp; + } +} + +/*! + * @brief Read the specified USART flag + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the flag to check + * The parameter can be one of following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXBE: Transmit data buffer empty flag + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_OVRE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * + * @retval The new state of flag (SET or RESET) + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag) +{ + return (usart->STS & flag) ? SET : RESET; +} + +/*! + * @brief Clears the USARTx's pending flags + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the flag to clear + * The parameter can be one of following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag) +{ + usart->STS &= (uint32_t)~flag; +} + +/*! + * @brief Read the specified USART interrupt flag + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the USART interrupt source to check + * The parameter can be one of following values: + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_OVRE: OverRun Error interruptpt + * @arg USART_INT_NE: Noise Error interrupt + * @arg USART_INT_FE: Framing Error interrupt + * @arg USART_INT_PE: Parity error interrupt + * + * @retval The new state of flag (SET or RESET) + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag) +{ + uint32_t itFlag, srFlag; + + if (flag & 0x10000) + { + itFlag = usart->CTRL1 & flag & 0xffff; + } + else if (flag & 0x20000) + { + itFlag = usart->CTRL2 & flag & 0xffff; + } + else + { + itFlag = usart->CTRL3 & flag & 0xffff; + } + + srFlag = flag >> 24; + srFlag = (uint32_t)(1 << srFlag); + srFlag = usart->STS & srFlag; + + if (srFlag && itFlag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the USART interrupt pending bits + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the interrupt pending bit to clear + * The parameter can be one of following values: + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag) +{ + uint32_t srFlag; + + srFlag = flag >> 24; + srFlag = (uint32_t)(1 << srFlag); + + usart->STS &= (uint32_t)~srFlag; +} + +/**@} end of group USART_Fuctions*/ +/**@} end of group USART_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c new file mode 100644 index 0000000000..fb8fee5481 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c @@ -0,0 +1,378 @@ +/*! + * @file apm32f10x_usb.c + * + * @brief This file contains all the functions for the USBD peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_usb.h" + +/*! + * @brief Set Endpoint type + * + * @param ep: Endpoint number + * + * @param type: Endpoint type + * + * @retval None + */ +void USBD_SetEPType(USBD_EP_T ep, USBD_EP_TYPE_T type) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_TYPE; + reg |= type << 9; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP kind + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_SetEPKind(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_KIND; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset EP kind + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPKind(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_KIND; + + USBD->EP[ep].EP = reg; +} + + +/*! + * @brief Reset EP CTFR bit + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPRxFlag(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_CTFR; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset EP CTFT bit + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPTxFlag(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_CTFT; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Toggle Tx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ToggleTx(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_TXDTOG; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Toggle Rx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ToggleRx(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_RXDTOG; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset Toggle Tx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetTxToggle(USBD_EP_T ep) +{ + if(USBD->EP[ep].EP_B.TXDTOG) + { + USBD_ToggleTx(ep); + } +} + +/*! + * @brief Reset Toggle Rx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetRxToggle(USBD_EP_T ep) +{ + if(USBD->EP[ep].EP_B.RXDTOG) + { + USBD_ToggleRx(ep); + } +} + +/*! + * @brief Set EP address + * + * @param ep: Endpoint number + * + * @param addr: Address + * + * @retval None + */ +void USBD_SetEpAddr(USBD_EP_T ep, uint8_t addr) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_ADDR; + reg |= addr; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Tx status + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) +{ + __IOM uint32_t reg; + + status <<= 4; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_TXSTS); + reg ^= (status & USBD_EP_BIT_TXSTS); + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Rx status + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) +{ + __IOM uint32_t reg; + uint32_t tmp; + + tmp = status << 12; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS); + reg ^= (tmp & USBD_EP_BIT_RXSTS); + + USBD->EP[ep].EP = reg; +} + + +/*! + * @brief Set EP Rx and Txstatus + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPRxTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus) +{ + __IOM uint32_t reg; + uint32_t tmp; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS | USBD_EP_BIT_TXSTS); + + tmp = rxStatus << 12; + reg ^= (tmp & USBD_EP_BIT_RXSTS); + + tmp = txStatus << 4; + reg ^= (tmp & USBD_EP_BIT_TXSTS); + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Rx Count + * + * @param ep: Endpoint number + * + * @param cnt: Rx count + * + * @retval None + */ +void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt) +{ + __IOM uint32_t *p; + __IOM uint32_t block = 0; + + p = USBD_ReadEPRxCntPointer(ep); + + if(cnt > 62) + { + block = cnt >> 5; + + if(!(cnt & 0x1f)) + { + block -= 1; + } + + *p = (block << 10) | 0x8000; + } + else + { + block = cnt >> 1; + + if(cnt & 0x01) + { + block += 1; + } + + *p = (block << 10); + } +} + +/*! + * @brief Write a buffer of data to a selected endpoint + * + * @param ep: Endpoint number + * + * @retval wBuf: The pointer to the buffer of data to be written to the endpoint + * + * @param wLen: Number of data to be written (in bytes) + * + * @retval None + */ +void USBD_WriteDataToEP(USBD_EP_T ep, uint8_t *wBuf, uint32_t wLen) +{ + uint32_t i; + uint32_t *addrEP; + uint32_t tmp; + + wLen = (wLen + 1) >> 1; + + addrEP = (uint32_t *)USBD_ReadEPTxAddr(ep); + addrEP = (uint32_t *)(((uint32_t)addrEP << 1) + USBD_PMA_ADDR); + + for(i = 0; i < wLen; i++) + { + tmp = *wBuf++; + tmp = ((*wBuf++) << 8) | tmp; + + *addrEP++ = tmp; + } +} + +/*! + * @brief Read a buffer of data to a selected endpoint + * + * @param ep: Endpoint number + * + * @retval wBuf: The pointer to the buffer of data to be read to the endpoint + * + * @param wLen: Number of data to be read (in bytes) + * + * @retval None + */ +void USBD_ReadDataFromEP(USBD_EP_T ep, uint8_t *rBuf, uint32_t rLen) +{ + uint32_t i; + uint32_t *addrEP; + uint32_t tmp; + + rLen = (rLen + 1) >> 1; + + addrEP = (uint32_t *)USBD_ReadEPRxAddr(ep); + addrEP = (uint32_t *)(((uint32_t)addrEP << 1) + USBD_PMA_ADDR); + + for(i = 0; i < rLen; i++) + { + tmp = *addrEP++; + *rBuf++ = tmp & 0XFF; + *rBuf++ = (tmp >> 8) & 0xff; + } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c new file mode 100644 index 0000000000..6e374cd5b4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c @@ -0,0 +1,145 @@ +/*! + * @file apm32f10x_wwdt.c + * + * @brief This file contains all the functions for the WWDT peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_wwdt.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the WWDT peripheral registers + * + * @param None + * + * @retval None + */ +void WWDT_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT); +} + +/*! + * @brief Config the WWDT Timebase + * + * @param timebase: WWDT Prescaler + * The parameter can be one of following values: + * @arg WWDT_TIME_BASE_1: WWDT counter clock = (PCLK1/4096)/1 + * @arg WWDT_TIME_BASE_2: WWDT counter clock = (PCLK1/4096)/2 + * @arg WWDT_TIME_BASE_4: WWDT counter clock = (PCLK1/4096)/4 + * @arg WWDT_TIME_BASE_8: WWDT counter clock = (PCLK1/4096)/8 + * + * @retval None + */ +void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase) +{ + __IO uint32_t reg; + + reg = WWDT->CFG & 0xFFFFFE7F; + reg |= timeBase; + WWDT->CFG = reg; +} + +/*! + * @brief Config the WWDT Window data + * + * @param windowdata: window data which compare with the downcounter + * + * @retval None + * + * @note The windowdata must be lower than 0x80 + */ +void WWDT_ConfigWindowData(uint8_t windowData) +{ + __IO uint32_t reg; + + reg = WWDT->CFG & 0xFFFFFF80; + reg |= windowData & 0x7F; + WWDT->CFG = reg; +} + +/*! + * @brief Config the WWDT counter value + * + * @param counter: Specifies the watchdog counter value + * + * @retval None + * + * @note The counter between 0x40 and 0x7F + */ +void WWDT_ConfigCounter(uint8_t counter) +{ + WWDT->CTRL = counter & 0x7F; +} + +/*! + * @brief Enable the WWDT Early Wakeup interrupt + * + * @param None + * + * @retval None + */ +void WWDT_EnableEWI(void) +{ + WWDT->CFG_B.EWIEN = SET; +} + +/*! + * @brief Enable WWDT and set the counter value + * + * @param counter: the window watchdog counter value + * + * @retval None + * + * @note The counter between 0x40 and 0x7F + */ +void WWDT_Enable(uint8_t counter) +{ + WWDT->CTRL = counter | 0x00000080; +} + +/*! + * @brief Read the Early Wakeup interrupt flag + * + * @param None + * + * @retval the state of the Early Wakeup interrupt flagte + */ +uint8_t WWDT_ReadFlag(void) +{ + return (uint8_t) (WWDT->STS); +} + +/*! + * @brief Clear the Early Wakeup interrupt flag + * + * @param None + * + * @retval None + */ +void WWDT_ClearFlag(void) +{ + WWDT->STS_B.EWIFLG = RESET; +} + +/**@} end of group WWDT_Fuctions*/ +/**@} end of group WWDT_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..a19425d9fe --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/**@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..ef919934c5 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/**@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..356182c5f9 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/**@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include <stdint.h> + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include <cmsis_iccarm.h> + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include <cmsis_ccs.h> + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include <cmsis_csm.h> + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h new file mode 100644 index 0000000000..f5edd39559 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h @@ -0,0 +1,6158 @@ +/*! + * @file apm32f10x.h + * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * + * @details This file contains all the peripheral register's definitions, bits definitions and memory mapping + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10x_H +#define __APM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*! + * APM32F10X_LD: APM32 Low density devices, the Flash memory density ranges between 16 and 32 Kbytes. + * APM32F10X_MD: APM32 Medium density devices, the Flash memory density ranges between 64 and 128 Kbytes. + * APM32F10X_HD: APM32 High density devices, the Flash memory density ranges between 256 and 512 Kbytes. + */ +#if !defined (APM32F10X_LD) && !defined (APM32F10X_MD) && !defined (APM32F10X_HD) +#error "Please select a the target APM32F10x device used in your application (in apm32f10x.h file)" +#endif + +/** + * @brief Define Value of the External oscillator in Hz + */ +#ifndef HSE_VALUE + #define HSE_VALUE ((uint32_t)8000000) +#endif + +/** Time out for HSE start up */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) + +/** Value of the Internal oscillator in Hz */ +#define HSI_VALUE ((uint32_t)8000000) + +/** + * @brief APM32F10x Standard Peripheral Library version number + */ +#define __APM32F10X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __APM32F10X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __APM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __APM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __APM32F10X_STDPERIPH_VERSION ( (__APM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__APM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__APM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__APM32F10X_STDPERIPH_VERSION_RC)) + + +/** APM32 devices does not provide an MPU */ + #define __MPU_PRESENT 0 +/** APM32 uses 4 Bits for the Priority Levels */ +#define __NVIC_PRIO_BITS 4 +/** Set to 1 if different SysTick Config is used */ +#define __Vendor_SysTickConfig 0 + +/** + * @brief APM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** APM32 specific Interrupt Numbers *********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EINT Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FMC_IRQn = 4, /*!< FMC global Interrupt */ + RCM_IRQn = 5, /*!< RCM global Interrupt */ + EINT0_IRQn = 6, /*!< EINT Line0 Interrupt */ + EINT1_IRQn = 7, /*!< EINT Line1 Interrupt */ + EINT2_IRQn = 8, /*!< EINT Line2 Interrupt */ + EINT3_IRQn = 9, /*!< EINT Line3 Interrupt */ + EINT4_IRQn = 10, /*!< EINT Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#if defined (APM32F10X_LD) + /** APM32F10X Low-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + +#elif defined (APM32F10X_MD) + /** APM32F10X Medium-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + +#elif defined (APM32F10X_HD) + /** APM32F10X High-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + TMR8_BRK_IRQn = 43, /*!< TMR8 Break Interrupt */ + TMR8_UP_IRQn = 44, /*!< TMR8 Update Interrupt */ + TMR8_TRG_COM_IRQn = 45, /*!< TMR8 Trigger and Commutation Interrupt */ + TMR8_CC_IRQn = 46, /*!< TMR8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + EMMC_IRQn = 48, /*!< EMMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TMR5_IRQn = 50, /*!< TMR5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TMR6_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + USBD2_HP_CAN2_TX_IRQn = 61, /*!< USB Device 2 High Priority or CAN2 TX Interrupts */ + USBD2_LP_CAN2_RX0_IRQn = 62, /*!< USB Device 2 Low Priority or CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 63, /*!< CAN2 RX1 Interrupts */ + CAN2_SCE_IRQn = 64, /*!< CAN2 SCE Interrupts */ +#endif +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_apm32f10x.h" +#include <stdint.h> + + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; +typedef const int16_t sc16; +typedef const int8_t sc8; + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; +typedef __I int16_t vsc16; +typedef __I int8_t vsc8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; +typedef const uint16_t uc16; +typedef const uint8_t uc8; + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; +typedef __I uint16_t vuc16; +typedef __I uint8_t vuc8; + +#ifndef __IM + #define __IM __I +#endif +#ifndef __OM + #define __OM __O +#endif +#ifndef __IOM + #define __IOM __IO +#endif + +enum {BIT_RESET, BIT_SET}; +enum {RESET, SET}; +enum {DISABLE, ENABLE}; +enum {ERROR, SUCCESS}; + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#if defined (__CC_ARM ) +#pragma anon_unions +#endif + +/** + * @brief Reset and clock management unit (RCM) + */ +typedef struct +{ + /** Clock control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t HSIEN : 1; + __IM uint32_t HSIRDYFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t HSITRIM : 5; + __IM uint32_t HSICAL : 8; + __IOM uint32_t HSEEN : 1; + __IM uint32_t HSERDYFLG : 1; + __IOM uint32_t HSEBCFG : 1; + __IOM uint32_t CSSEN : 1; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t PLLEN : 1; + __IM uint32_t PLLRDYFLG : 1; + __IM uint32_t RESERVED3 : 6; + } CTRL_B; + }; + + /** Clock configuration register */ + union + { + __IOM uint32_t CFG; + + struct + { + __IOM uint32_t SCLKSW : 2; + __IM uint32_t SCLKSWSTS : 2; + __IOM uint32_t AHBPSC : 4; + __IOM uint32_t APB1PSC : 3; + __IOM uint32_t APB2PSC : 3; + __IOM uint32_t ADCPSC : 2; + __IOM uint32_t PLLSRCSEL : 1; + __IOM uint32_t PLLHSEPSC : 1; + __IOM uint32_t PLLMULCFG : 4; + __IOM uint32_t USBDPSC : 2; + __IOM uint32_t MCOSEL : 3; + __IOM uint32_t FPUPSC : 1; + __IM uint32_t RESERVED : 4; + } CFG_B; + } ; + + /** Clock interrupt control register */ + union + { + __IOM uint32_t INT; + + struct + { + __IM uint32_t LSIRDYFLG : 1; + __IM uint32_t LSERDYFLG : 1; + __IM uint32_t HSIRDYFLG : 1; + __IM uint32_t HSERDYFLG : 1; + __IM uint32_t PLLRDYFLG : 1; + __IM uint32_t RESERVED1 : 2; + __IM uint32_t CSSIF : 1; + __IOM uint32_t LSIRDYEN : 1; + __IOM uint32_t LSERDYEN : 1; + __IOM uint32_t HSIRDYEN : 1; + __IOM uint32_t HSERDYEN : 1; + __IOM uint32_t PLLRDYEN : 1; + __IM uint32_t RESERVED2 : 3; + __OM uint32_t LSIRDYCLR : 1; + __OM uint32_t LSERDYCLR : 1; + __OM uint32_t HSIRDYCLR : 1; + __OM uint32_t HSERDYCLR : 1; + __OM uint32_t PLLRDYCLR : 1; + __IM uint32_t RESERVED3 : 2; + __OM uint32_t CSSCLR : 1; + __IM uint32_t RESERVED4 : 8; + } INT_B; + } ; + + /** APB2 peripheral reset register */ + union + { + __IOM uint32_t APB2RST; + + struct + { + __IOM uint32_t AFIO : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PA : 1; + __IOM uint32_t PB : 1; + __IOM uint32_t PC : 1; + __IOM uint32_t PD : 1; + __IOM uint32_t PE : 1; + __IOM uint32_t PF : 1; + __IOM uint32_t PG : 1; + __IOM uint32_t ADC1 : 1; + __IOM uint32_t ADC2 : 1; + __IOM uint32_t TMR1 : 1; + __IOM uint32_t SPI1 : 1; + __IOM uint32_t TMR8 : 1; + __IOM uint32_t USART1 : 1; + __IOM uint32_t ADC3 : 1; + __IM uint32_t RESERVED2 : 16; + } APB2RST_B; + } ; + + /** APB1 peripheral reset register */ + union + { + __IOM uint32_t APB1RST; + + struct + { + __IOM uint32_t TMR2 : 1; + __IOM uint32_t TMR3 : 1; + __IOM uint32_t TMR4 : 1; + __IOM uint32_t TMR5 : 1; + __IOM uint32_t TMR6 : 1; + __IOM uint32_t TMR7 : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t WWDT : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t SPI2 : 1; + __IOM uint32_t SPI3 : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t USART2 : 1; + __IOM uint32_t USART3 : 1; + __IOM uint32_t UART4 : 1; + __IOM uint32_t UART5 : 1; + __IOM uint32_t I2C1 : 1; + __IOM uint32_t I2C2 : 1; + __IOM uint32_t USBD : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t CAN1 : 1; + __IM uint32_t CAN2 : 1; + __IOM uint32_t BAKP : 1; + __IOM uint32_t PMU : 1; + __IOM uint32_t DAC : 1; + __IM uint32_t RESERVED5 : 2; + } APB1RST_B; + } ; + + /** AHB clock enable register */ + union + { + __IOM uint32_t AHBCLKEN; + + struct + { + __IOM uint32_t DMA1 : 1; + __IOM uint32_t DMA2 : 1; + __IOM uint32_t SRAM : 1; + __IOM uint32_t FPU : 1; + __IOM uint32_t FMC : 1; + __IOM uint32_t QSPI : 1; + __IOM uint32_t CRC : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t EMMC : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t SDIO : 1; + __IM uint32_t RESERVED3 : 21; + } AHBCLKEN_B; + } ; + + /** APB2 clock enable register */ + union + { + __IOM uint32_t APB2CLKEN; + + struct + { + __IOM uint32_t AFIO : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PA : 1; + __IOM uint32_t PB : 1; + __IOM uint32_t PC : 1; + __IOM uint32_t PD : 1; + __IOM uint32_t PE : 1; + __IOM uint32_t PF : 1; + __IOM uint32_t PG : 1; + __IOM uint32_t ADC1 : 1; + __IOM uint32_t ADC2 : 1; + __IOM uint32_t TMR1 : 1; + __IOM uint32_t SPI1 : 1; + __IOM uint32_t TMR8 : 1; + __IOM uint32_t USART1 : 1; + __IOM uint32_t ADC3 : 1; + __IM uint32_t RESERVED2 : 16; + } APB2CLKEN_B; + }; + + /** APB1 clock enable register */ + union + { + __IOM uint32_t APB1CLKEN; + + struct + { + __IOM uint32_t TMR2 : 1; + __IOM uint32_t TMR3 : 1; + __IOM uint32_t TMR4 : 1; + __IOM uint32_t TMR5 : 1; + __IOM uint32_t TMR6 : 1; + __IOM uint32_t TMR7 : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t WWDT : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t SPI2 : 1; + __IOM uint32_t SPI3 : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t USART2 : 1; + __IOM uint32_t USART3 : 1; + __IOM uint32_t UART4 : 1; + __IOM uint32_t UART5 : 1; + __IOM uint32_t I2C1 : 1; + __IOM uint32_t I2C2 : 1; + __IOM uint32_t USBD : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t CAN1 : 1; + __IM uint32_t CAN2 : 1; + __IOM uint32_t BAKP : 1; + __IOM uint32_t PMU : 1; + __IOM uint32_t DAC : 1; + __IM uint32_t RESERVED5 : 2; + } APB1CLKEN_B; + } ; + + /** Backup domain control register */ + union + { + __IOM uint32_t BDCTRL; + + struct + { + __IOM uint32_t LSEEN : 1; + __IM uint32_t LSERDYFLG : 1; + __IOM uint32_t LSEBCFG : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t RTCSRCSEL : 2; + __IM uint32_t RESERVED2 : 5; + __IOM uint32_t RTCCLKEN : 1; + __IOM uint32_t BDRST : 1; + __IM uint32_t RESERVED3 : 15; + } BDCTRL_B; + } ; + + /** Control/status register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IOM uint32_t LSIEN : 1; + __IM uint32_t LSIRDYFLG : 1; + __IM uint32_t RESERVED1 : 22; + __IOM uint32_t RSTFLGCLR : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t NRSTFLG : 1; + __IOM uint32_t PODRSTFLG : 1; + __IOM uint32_t SWRSTFLG : 1; + __IOM uint32_t IWDTRSTFLG : 1; + __IOM uint32_t WWDTRSTFLG : 1; + __IOM uint32_t LPWRRSTFLG : 1; + } CSTS_B; + } ; +} RCM_T; + +/** + * @brief General purpose I/O (GPIO) + */ +typedef struct +{ + /** Port configure register low */ + union + { + __IOM uint32_t CFGLOW; + + struct + { + __IOM uint32_t MODE0 : 2; + __IOM uint32_t CFG0 : 2; + __IOM uint32_t MODE1 : 2; + __IOM uint32_t CFG1 : 2; + __IOM uint32_t MODE2 : 2; + __IOM uint32_t CFG2 : 2; + __IOM uint32_t MODE3 : 2; + __IOM uint32_t CFG3 : 2; + __IOM uint32_t MODE4 : 2; + __IOM uint32_t CFG4 : 2; + __IOM uint32_t MODE5 : 2; + __IOM uint32_t CFG5 : 2; + __IOM uint32_t MODE6 : 2; + __IOM uint32_t CFG6 : 2; + __IOM uint32_t MODE7 : 2; + __IOM uint32_t CFG7 : 2; + } CFGLOW_B; + } ; + + /** Port configure register high */ + union + { + __IOM uint32_t CFGHIG; + + struct + { + __IOM uint32_t MODE8 : 2; + __IOM uint32_t CFG8 : 2; + __IOM uint32_t MODE9 : 2; + __IOM uint32_t CFG9 : 2; + __IOM uint32_t MODE10 : 2; + __IOM uint32_t CFG10 : 2; + __IOM uint32_t MODE11 : 2; + __IOM uint32_t CFG11 : 2; + __IOM uint32_t MODE12 : 2; + __IOM uint32_t CFG12 : 2; + __IOM uint32_t MODE13 : 2; + __IOM uint32_t CFG13 : 2; + __IOM uint32_t MODE14 : 2; + __IOM uint32_t CFG14 : 2; + __IOM uint32_t MODE15 : 2; + __IOM uint32_t CFG15 : 2; + } CFGHIG_B; + } ; + + /** Port data in register */ + union + { + __IM uint32_t IDATA; + + struct + { + __IM uint32_t IDATA0 : 1; + __IM uint32_t IDATA1 : 1; + __IM uint32_t IDATA2 : 1; + __IM uint32_t IDATA3 : 1; + __IM uint32_t IDATA4 : 1; + __IM uint32_t IDATA5 : 1; + __IM uint32_t IDATA6 : 1; + __IM uint32_t IDATA7 : 1; + __IM uint32_t IDATA8 : 1; + __IM uint32_t IDATA9 : 1; + __IM uint32_t IDATA10 : 1; + __IM uint32_t IDATA11 : 1; + __IM uint32_t IDATA12 : 1; + __IM uint32_t IDATA13 : 1; + __IM uint32_t IDATA14 : 1; + __IM uint32_t IDATA15 : 1; + __IM uint32_t RESERVED : 16; + } IDATA_B; + } ; + + /** Port data output register */ + union + { + __IOM uint32_t ODATA; + + struct + { + __IOM uint32_t ODATA0 : 1; + __IOM uint32_t ODATA1 : 1; + __IOM uint32_t ODATA2 : 1; + __IOM uint32_t ODATA3 : 1; + __IOM uint32_t ODATA4 : 1; + __IOM uint32_t ODATA5 : 1; + __IOM uint32_t ODATA6 : 1; + __IOM uint32_t ODATA7 : 1; + __IOM uint32_t ODATA8 : 1; + __IOM uint32_t ODATA9 : 1; + __IOM uint32_t ODATA10 : 1; + __IOM uint32_t ODATA11 : 1; + __IOM uint32_t ODATA12 : 1; + __IOM uint32_t ODATA13 : 1; + __IOM uint32_t ODATA14 : 1; + __IOM uint32_t ODATA15 : 1; + __IM uint32_t RESERVED : 16; + } ODATA_B; + } ; + + /** Port bit set/clear register */ + union + { + __OM uint32_t BSC; + + struct + { + __OM uint32_t BS0 : 1; + __OM uint32_t BS1 : 1; + __OM uint32_t BS2 : 1; + __OM uint32_t BS3 : 1; + __OM uint32_t BS4 : 1; + __OM uint32_t BS5 : 1; + __OM uint32_t BS6 : 1; + __OM uint32_t BS7 : 1; + __OM uint32_t BS8 : 1; + __OM uint32_t BS9 : 1; + __OM uint32_t BS10 : 1; + __OM uint32_t BS11 : 1; + __OM uint32_t BS12 : 1; + __OM uint32_t BS13 : 1; + __OM uint32_t BS14 : 1; + __OM uint32_t BS15 : 1; + __OM uint32_t BR0 : 1; + __OM uint32_t BC1 : 1; + __OM uint32_t BC2 : 1; + __OM uint32_t BR3 : 1; + __OM uint32_t BC4 : 1; + __OM uint32_t BC5 : 1; + __OM uint32_t BC6 : 1; + __OM uint32_t BC7 : 1; + __OM uint32_t BC8 : 1; + __OM uint32_t BC9 : 1; + __OM uint32_t BC10 : 1; + __OM uint32_t BC11 : 1; + __OM uint32_t BC12 : 1; + __OM uint32_t BC13 : 1; + __OM uint32_t BC14 : 1; + __OM uint32_t BC15 : 1; + } BSC_B; + } ; + + /** Port bit clear register */ + union + { + __OM uint32_t BC; + + struct + { + __OM uint32_t BC0 : 1; + __OM uint32_t BC1 : 1; + __OM uint32_t BC2 : 1; + __OM uint32_t BC3 : 1; + __OM uint32_t BC4 : 1; + __OM uint32_t BC5 : 1; + __OM uint32_t BC6 : 1; + __OM uint32_t BC7 : 1; + __OM uint32_t BC8 : 1; + __OM uint32_t BC9 : 1; + __OM uint32_t BC10 : 1; + __OM uint32_t BC11 : 1; + __OM uint32_t BC12 : 1; + __OM uint32_t BC13 : 1; + __OM uint32_t BC14 : 1; + __OM uint32_t BC15 : 1; + __IM uint32_t RESERVED : 16; + } BC_B; + } ; + + /** Port configuration lock register */ + union + { + __IOM uint32_t LOCK; + + struct + { + __IOM uint32_t LOCK0 : 1; + __IOM uint32_t LOCK1 : 1; + __IOM uint32_t LOCK2 : 1; + __IOM uint32_t LOCK3 : 1; + __IOM uint32_t LOCK4 : 1; + __IOM uint32_t LOCK5 : 1; + __IOM uint32_t LOCK6 : 1; + __IOM uint32_t LOCK7 : 1; + __IOM uint32_t LOCK8 : 1; + __IOM uint32_t LOCK9 : 1; + __IOM uint32_t LOCK10 : 1; + __IOM uint32_t LOCK11 : 1; + __IOM uint32_t LOCK12 : 1; + __IOM uint32_t LOCK13 : 1; + __IOM uint32_t LOCK14 : 1; + __IOM uint32_t LOCK15 : 1; + __IOM uint32_t LOCKKEY : 1; + __IM uint32_t RESERVED : 16; + } LOCK_B; + } ; +} GPIO_T; + +/** + * @brief Alternate function I/O (AFIO) + */ +typedef struct +{ + /** Event control register */ + union + { + __IOM uint32_t EVCTRL; + + struct + { + __IOM uint32_t PINSEL : 4; + __IOM uint32_t PORTSEL : 3; + __IOM uint32_t EVOEN : 1; + __IM uint32_t RESERVED : 24; + } EVCTRL_B; + } ; + + /** Alternate function IO remap and Serial wire JTAG configuration register */ + union + { + __IOM uint32_t REMAP1; + + struct + { + __IOM uint32_t SPI1RMP : 1; + __IOM uint32_t I2C1RMP : 1; + __IOM uint32_t USART1RMP : 1; + __IOM uint32_t USART2RMP : 1; + __IOM uint32_t USART3RMP : 2; + __IOM uint32_t TMR1RMP : 2; + __IOM uint32_t TMR2RMP : 2; + __IOM uint32_t TMR3RMP : 2; + __IOM uint32_t TMR4RMP : 1; + __IOM uint32_t CAN1RMP : 2; + __IOM uint32_t PD01RMP : 1; + __IOM uint32_t TMR5CH4IRMP : 1; + __IOM uint32_t ADC1_ETRGINJC_RMP : 1; + __IOM uint32_t ADC1_ETRGREGC_RMP : 1; + __IOM uint32_t ADC2_ETRGINJC_RMP : 1; + __IOM uint32_t ADC2_ETRGREGC_RMP : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CAN2RMP : 1; + __IM uint32_t RESERVED2 : 1; + __OM uint32_t SWJCFG : 3; + __IM uint32_t RESERVED3 : 5; + } REMAP1_B; + } ; + + /** External interrupt select register1 */ + union + { + __IOM uint32_t EINTSEL1; + + struct + { + __IOM uint32_t EINT0 : 4; + __IOM uint32_t EINT1 : 4; + __IOM uint32_t EINT2 : 4; + __IOM uint32_t EINT3 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL1_B; + } ; + + /** External interrupt select register2 */ + union + { + __IOM uint32_t EINTSEL2; + + struct + { + __IOM uint32_t EINT4 : 4; + __IOM uint32_t EINT5 : 4; + __IOM uint32_t EINT6 : 4; + __IOM uint32_t EINT7 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL2_B; + } ; + + /** External interrupt select register3 */ + union + { + __IOM uint32_t EINTSEL3; + + struct + { + __IOM uint32_t EINT8 : 4; + __IOM uint32_t EINT9 : 4; + __IOM uint32_t EINT10 : 4; + __IOM uint32_t EINT11 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL3_B; + } ; + + /** External interrupt select register4 */ + union + { + __IOM uint32_t EINTSEL4; + + struct + { + __IOM uint32_t EINT12 : 4; + __IOM uint32_t EINT13 : 4; + __IOM uint32_t EINT14 : 4; + __IOM uint32_t EINT15 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL4_B; + } ; + __IM uint32_t RESERVED; + + /** Alternate function IO remap register2 */ + union + { + __IOM uint32_t REMAP2; + + struct + { + __IM uint32_t RESERVED1 : 10; + __IOM uint32_t EMMCNADV : 1; + __IM uint32_t RESERVED2 : 21; + } REMAP2_B; + } ; +} AFIO_T; + +/** + * @brief Universal synchronous asynchronous receiver transmitter (USART) + */ +typedef struct +{ + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t PEFLG : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t NEFLG : 1; + __IM uint32_t OVREFLG : 1; + __IM uint32_t IDLEFLG : 1; + __IOM uint32_t RXBNEFLG : 1; + __IOM uint32_t TXCFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IOM uint32_t LBDFLG : 1; + __IOM uint32_t CTSFLG : 1; + __IM uint32_t RESERVED : 22; + } STS_B; + } ; + + /** TX Buffer Data Register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 9; + __IM uint32_t RESERVED : 23; + } DATA_B; + } ; + + /** Baud rate register */ + union + { + __IOM uint32_t BR; + + struct + { + __IOM uint32_t FBR : 4; + __IOM uint32_t IBR : 12; + __IM uint32_t RESERVED : 16; + } BR_B; + } ; + + /** Control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t TXBF : 1; + __IOM uint32_t RXMUTEEN : 1; + __IOM uint32_t RXEN : 1; + __IOM uint32_t TXEN : 1; + __IOM uint32_t IDLEIEN : 1; + __IOM uint32_t RXBNEIEN : 1; + __IOM uint32_t TXCIEN : 1; + __IOM uint32_t TXBEIEN : 1; + __IOM uint32_t PEIEN : 1; + __IOM uint32_t PCFG : 1; + __IOM uint32_t PCEN : 1; + __IOM uint32_t WUPMCFG : 1; + __IOM uint32_t DBLCFG : 1; + __IOM uint32_t UEN : 1; + __IM uint32_t RESERVED : 18; + } CTRL1_B; + } ; + + /** Control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t ADDR : 4; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t LBDLCFG : 1; + __IOM uint32_t LBDIEN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t LBCPOEN : 1; + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t CLKEN : 1; + __IOM uint32_t STOPCFG : 2; + __IOM uint32_t LINMEN : 1; + __IM uint32_t RESERVED3 : 17; + } CTRL2_B; + } ; + + /** Control register 3 */ + union + { + __IOM uint32_t CTRL3; + + struct + { + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t IREN : 1; + __IOM uint32_t IRLPEN : 1; + __IOM uint32_t HDEN : 1; + __IOM uint32_t SCNACKEN : 1; + __IOM uint32_t SCEN : 1; + __IOM uint32_t DMARXEN : 1; + __IOM uint32_t DMATXEN : 1; + __IOM uint32_t RTSEN : 1; + __IOM uint32_t CTSEN : 1; + __IOM uint32_t CTSIEN : 1; + __IM uint32_t RESERVED : 21; + } CTRL3_B; + } ; + + /** Guard TMRe and divider number register */ + union + { + __IOM uint32_t GTPSC; + + struct + { + __IOM uint32_t PSC : 8; + __IOM uint32_t GRDT : 8; + __IM uint32_t RESERVED : 16; + } GTPSC_B; + } ; +} USART_T; + +/** + * @brief Flash memory controller(FMC) + */ +typedef struct +{ + /** FMC access control register */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t WS : 3; + __IOM uint32_t HCAEN : 1; + __IOM uint32_t PBEN : 1; + __IM uint32_t PBSF : 1; + __IM uint32_t RESERVED : 26; + } CTRL1_B; + } ; + + /** key register */ + union + { + __OM uint32_t KEY; + + struct + { + __OM uint32_t KEY : 32; + } KEY_B; + } ; + + /** option byte key register */ + union + { + __OM uint32_t OBKEY; + + struct + { + __OM uint32_t OBKEY : 32; + } OBKEY_B; + }; + + /** status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t BUSYF : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PEF : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t WPEF : 1; + __IOM uint32_t OCF : 1; + __IM uint32_t RESERVED3 : 26; + } STS_B; + }; + + /** status register */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t PG : 1; + __IOM uint32_t PAGEERA : 1; + __IOM uint32_t MASSERA : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t OBP : 1; + __IOM uint32_t OBE : 1; + __IOM uint32_t STA : 1; + __IOM uint32_t LOCK : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t OBWEN : 1; + __IOM uint32_t ERRIE : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t OCIE : 1; + __IM uint32_t RESERVED4 : 19; + } CTRL2_B; + } ; + + /** address register */ + union + { + __OM uint32_t ADDR; + + struct + { + __OM uint32_t ADDR : 32; + } ADDR_B; + }; + + __IM uint32_t RESERVED; + + /** Option byte register */ + union + { + __IOM uint32_t OBCS; + + struct + { + __IM uint32_t OBE : 1; + __IM uint32_t READPROT : 1; + __IM uint32_t WDTSEL : 1; + __IM uint32_t RSTSTOP : 1; + __IM uint32_t RSTSTDB : 1; + __IM uint32_t UOB : 5; + __IM uint32_t DATA0 : 8; + __IM uint32_t DATA1 : 8; + __IM uint32_t RESERVED : 6; + } OBCS_B; + }; + + /** Write protection register */ + union + { + __IM uint32_t WRTPROT; + + struct + { + __IM uint32_t WRTPORT : 32; + } WRTPORT_B; + }; +} FMC_T; + +/** + * @brief CRC calculation unit (CRC) + */ +typedef struct +{ + /** @brief DATA register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 32; + } DATA_B; + } ; + + /** @brief independent DATA register */ + union + { + __IOM uint32_t INDATA; + + struct + { + __IOM uint32_t INDATA : 8; + __IM uint32_t RESERVED : 24; + } INDATA_B; + }; + + /** @brief Countrol register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t RST : 1; + __IM uint32_t RESERVED : 31; + } CTRL_B; + }; +} CRC_T; + +/** + * @brief Real time clock (RTC) + */ +typedef struct +{ + /** @brief Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t SECIEN : 1; + __IOM uint32_t ALRIEN : 1; + __IOM uint32_t OVRIEN : 1; + __IM uint32_t RESERVED : 29; + } CTRL_B; + }; + + /** @brief Control and State register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IOM uint32_t SECFLG : 1; + __IOM uint32_t ALRFLG : 1; + __IOM uint32_t OVRFLG : 1; + __IOM uint32_t RSYNCFLG : 1; + __IOM uint32_t CFGMFLG : 1; + __IM uint32_t OCFLG : 1; + __IM uint32_t RESERVED : 26; + } CSTS_B; + }; + + /** @brief RTC predivision loading register High Bit */ + union + { + __OM uint32_t PSCRLDH; + + struct + { + __OM uint32_t PSCRLDH : 4; + __IM uint32_t RESERVED : 28; + } PSCRLDH_B; + }; + + /** @brief RTC predivision loading register Low Bit */ + union + { + __OM uint32_t PSCRLDL; + + struct + { + __OM uint32_t PSCRLDL : 16; + __IM uint32_t RESERVED : 16; + } PSCRLDL_B; + }; + + /** @brief RTC predivider remainder register High Bit */ + union + { + __IM uint32_t PSCH; + + struct + { + __IM uint32_t PSCH : 4; + __IM uint32_t RESERVED : 28; + } PSCH_B; + }; + + /** @brief RTC predivider remainder register Low Bit */ + union + { + __IM uint32_t PSCL; + + struct + { + __IM uint32_t PSCL : 16; + __IM uint32_t RESERVED : 16; + } PSCL_B; + }; + + /** @brief RTC count register High Bit */ + union + { + __IOM uint32_t CNTH; + + struct + { + __IOM uint32_t CNTH : 16; + __IM uint32_t RESERVED : 16; + } CNTH_B; + }; + + /** @brief RTC count register Low Bit */ + union + { + __IOM uint32_t CNTL; + + struct + { + __IOM uint32_t CNTL : 16; + __IM uint32_t RESERVED : 16; + } CNTL_B; + }; + + /** @brief RTC alarm clock register High Bit */ + union + { + __OM uint32_t ALRH; + + struct + { + __OM uint32_t ALRH : 16; + __IM uint32_t RESERVED : 16; + } ALRH_B; + }; + + /** @brief RTC alarm clock register Low Bit */ + union + { + __OM uint32_t ALRL; + + struct + { + __OM uint32_t ALRL : 16; + __IM uint32_t RESERVED : 16; + } ALRL_B; + }; +} RTC_T; + +/** + * @brief Power Management Unit(PMU) + */ +typedef struct +{ + /** @brief Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t LPDSCFG : 1; + __IOM uint32_t PDDSCFG : 1; + __IOM uint32_t WUFLGCLR : 1; + __IOM uint32_t SBFLGCLR : 1; + __IOM uint32_t PVDEN : 1; + __IOM uint32_t PLSEL : 3; + __IOM uint32_t BPWEN : 1; + __IM uint32_t RESERVED : 23; + } CTRL_B; + }; + + /** @brief PMU Status register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IM uint32_t WUEFLG : 1; + __IM uint32_t SBFLG : 1; + __IM uint32_t PVDOFLG : 1; + __IM uint32_t RESERVED : 5; + __IOM uint32_t WKUPCFG : 1; + __IM uint32_t RESERVED2 : 23; + } CSTS_B; + }; +} PMU_T; + +/** + * @brief Backup register (BAKPR) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + /** @brief BAKPR DATA1 register */ + union + { + __IOM uint32_t DATA1; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA1_B; + }; + + /** @brief BAKPR DATA2 register */ + union + { + __IOM uint32_t DATA2; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA2_B; + }; + + /** @brief BAKPR DATA3 register */ + union + { + __IOM uint32_t DATA3; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA3_B; + }; + + /** @brief BAKPR DATA4 register */ + union + { + __IOM uint32_t DATA4; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA4_B; + }; + + /** @brief BAKPR DATA5 register */ + union + { + __IOM uint32_t DATA5; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA5_B; + }; + + /** @brief BAKPR DATA6 register */ + union + { + __IOM uint32_t DATA6; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA6_B; + }; + + /** @brief BAKPR DATA7 register */ + union + { + __IOM uint32_t DATA7; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA7_B; + }; + + /** @brief BAKPR DATA8 register */ + union + { + __IOM uint32_t DATA8; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA8_B; + }; + + /** @brief BAKPR DATA9 register */ + union + { + __IOM uint32_t DATA9; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA9_B; + }; + + /** @brief BAKPR DATA10 register */ + union + { + __IOM uint32_t DATA10; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA10_B; + }; + + /** @brief BAKPR Clock Calibration register */ + union + { + __IOM uint32_t CLKCAL; + + struct + { + __IOM uint32_t CALVALUE : 7; + __IOM uint32_t CALCOEN : 1; + __IOM uint32_t ASPOEN : 1; + __IOM uint32_t ASPOSEL : 1; + __IM uint32_t RESERVED : 22; + } CLKCAL_B; + } ; + + /** @brief BAKPR Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t TPFCFG : 1; + __IOM uint32_t TPALCFG : 1; + __IM uint32_t RESERVED : 30; + } CTRL_B; + }; + + /** @brief BAKPR Control register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __OM uint32_t TECLR : 1; + __OM uint32_t TICLR : 1; + __IOM uint32_t TPIEN : 1; + __IM uint32_t RESERVED1 : 5; + __IM uint32_t TEFLG : 1; + __IM uint32_t TIFLG : 1; + __IM uint32_t RESERVED2 : 22; + } CSTS_B; + }; + + __IM uint32_t RESERVED1[2]; + + /** @briefBAKPR DATA11 register */ + union + { + __IOM uint32_t DATA11; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA11_B; + }; + + /** @briefBAKPR DATA12 register */ + union + { + __IOM uint32_t DATA12; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA12_B; + }; + + /** @briefBAKPR DATA13 register */ + union + { + __IOM uint32_t DATA13; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA13_B; + }; + + /** @briefBAKPR DATA14 register */ + union + { + __IOM uint32_t DATA14; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA14_B; + }; + + /** @briefBAKPR DATA15 register */ + union + { + __IOM uint32_t DATA15; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA15_B; + }; + + /** @briefBAKPR DATA16 register */ + union + { + __IOM uint32_t DATA16; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA16_B; + }; + + /** @briefBAKPR DATA17 register */ + union + { + __IOM uint32_t DATA17; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA17_B; + }; + + /** @briefBAKPR DATA18 register */ + union + { + __IOM uint32_t DATA18; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA18_B; + }; + + /** @briefBAKPR DATA19 register */ + union + { + __IOM uint32_t DATA19; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA19_B; + }; + + /** @briefBAKPR DATA20 register */ + union + { + __IOM uint32_t DATA20; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA20_B; + }; + + /** @briefBAKPR DATA21 register */ + union + { + __IOM uint32_t DATA21; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA21_B; + }; + + /** @briefBAKPR DATA22 register */ + union + { + __IOM uint32_t DATA22; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA22_B; + }; + + /** @briefBAKPR DATA23 register */ + union + { + __IOM uint32_t DATA23; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA23_B; + }; + + /** @briefBAKPR DATA24 register */ + union + { + __IOM uint32_t DATA24; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA24_B; + }; + + /** @briefBAKPR DATA25 register */ + union + { + __IOM uint32_t DATA25; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA25_B; + }; + + /** @briefBAKPR DATA26 register */ + union + { + __IOM uint32_t DATA26; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA26_B; + }; + + /** @briefBAKPR DATA27 register */ + union + { + __IOM uint32_t DATA27; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA27_B; + }; + + /** @briefBAKPR DATA28 register */ + union + { + __IOM uint32_t DATA28; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA28_B; + }; + + /** @briefBAKPR DATA29 register */ + union + { + __IOM uint32_t DATA29; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA29_B; + }; + + /** @briefBAKPR DATA30 register */ + union + { + __IOM uint32_t DATA30; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA30_B; + }; + + /** @briefBAKPR DATA31 register */ + union + { + __IOM uint32_t DATA31; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA31_B; + }; + + /** @briefBAKPR DATA32 register */ + union + { + __IOM uint32_t DATA32; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA32_B; + }; + + /** @briefBAKPR DATA33 register */ + union + { + __IOM uint32_t DATA33; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA33_B; + }; + + /** @briefBAKPR DATA34 register */ + union + { + __IOM uint32_t DATA34; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA34_B; + }; + + /** @briefBAKPR DATA35 register */ + union + { + __IOM uint32_t DATA35; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA35_B; + }; + + /** @briefBAKPR DATA36 register */ + union + { + __IOM uint32_t DATA36; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA36_B; + }; + + /** @briefBAKPR DATA37 register */ + union + { + __IOM uint32_t DATA37; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA37_B; + }; + + /** @briefBAKPR DATA38 register */ + union + { + __IOM uint32_t DATA38; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA38_B; + }; + + /** @briefBAKPR DATA39 register */ + union + { + __IOM uint32_t DATA39; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA39_B; + }; + + /** @briefBAKPR DATA40 register */ + union + { + __IOM uint32_t DATA40; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA40_B; + }; + + /** @briefBAKPR DATA41 register */ + union + { + __IOM uint32_t DATA41; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA41_B; + }; + + /** @briefBAKPR DATA42 register */ + union + { + __IOM uint32_t DATA42; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA42_B; + }; +} BAKPR_T; + +/** + * @brief Timer register(TMR) + */ +typedef struct +{ + /** @brief Countrol register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t CNTEN : 1; + __IOM uint32_t UD : 1; + __IOM uint32_t URSSEL : 1; + __IOM uint32_t SPMEN : 1; + __IOM uint32_t CNTDIR : 1; + __IOM uint32_t CAMSEL : 2; + __IOM uint32_t ARPEN : 1; + __IOM uint32_t CLKDIV : 2; + __IM uint32_t RESERVED : 22; + } CTRL1_B; + }; + + /** @brief Countrol register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t CCPEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CCUSEL : 1; + __IOM uint32_t CCDSEL : 1; + __IOM uint32_t MMSEL : 3; + __IOM uint32_t TI1SEL : 1; + __IOM uint32_t OC1OIS : 1; + __IOM uint32_t OC1NOIS : 1; + __IOM uint32_t OC2OIS : 1; + __IOM uint32_t OC2NOIS : 1; + __IOM uint32_t OC3OIS : 1; + __IOM uint32_t OC3NOIS : 1; + __IOM uint32_t OC4OIS : 1; + __IM uint32_t RESERVED2 : 17; + } CTRL2_B; + }; + + /** @brief Control register from mode */ + union + { + __IOM uint32_t SMCTRL; + + struct + { + __IOM uint32_t SMFSEL : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t TRGSEL : 3; + __IOM uint32_t MSMEN : 1; + __IOM uint32_t ETFCFG : 4; + __IOM uint32_t ETPCFG : 2; + __IOM uint32_t ECEN : 1; + __IOM uint32_t ETPOL : 1; + __IM uint32_t RESERVED2 : 16; + } SMCTRL_B; + }; + + /** @brief DMA and Interrupt enable register */ + union + { + __IOM uint32_t DIEN; + + struct + { + __IOM uint32_t UIEN : 1; + __IOM uint32_t CC1IEN : 1; + __IOM uint32_t CC2IEN : 1; + __IOM uint32_t CC3IEN : 1; + __IOM uint32_t CC4IEN : 1; + __IOM uint32_t COMIEN : 1; + __IOM uint32_t TRGIEN : 1; + __IOM uint32_t BRKIEN : 1; + __IOM uint32_t UDIEN : 1; + __IOM uint32_t CC1DEN : 1; + __IOM uint32_t CC2DEN : 1; + __IOM uint32_t CC3DEN : 1; + __IOM uint32_t CC4DEN : 1; + __IOM uint32_t COMDEN : 1; + __IOM uint32_t TRGDEN : 1; + __IM uint32_t RESERVED : 17; + } DIEN_B; + }; + + /** @brief Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t UIFLG : 1; + __IOM uint32_t CC1IFLG : 1; + __IOM uint32_t CC2IFLG : 1; + __IOM uint32_t CC3IFLG : 1; + __IOM uint32_t CC4IFLG : 1; + __IOM uint32_t COMIFLG : 1; + __IOM uint32_t TRGIFLG : 1; + __IOM uint32_t BRKIFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CC1RCFLG : 1; + __IOM uint32_t CC2RCFLG : 1; + __IOM uint32_t CC3RCFLG : 1; + __IOM uint32_t CC4RCFLG : 1; + __IM uint32_t RESERVED2 : 19; + } STS_B; + }; + + /** @brief Software controls event generation registers */ + union + { + __OM uint32_t CEG; + + struct + { + __OM uint32_t UEG : 1; + __OM uint32_t CC1EG : 1; + __OM uint32_t CC2EG : 1; + __OM uint32_t CC3EG : 1; + __OM uint32_t CC4EG : 1; + __OM uint32_t COMG : 1; + __OM uint32_t TEG : 1; + __OM uint32_t BEG : 1; + __OM uint32_t RESERVED : 24; + } CEG_B; + }; + + /** @brief Capture the compare mode register 1 */ + union + { + __IOM uint32_t CCM1; + + /** @brief Compare mode */ + struct + { + __IOM uint32_t CC1SEL : 2; + __IOM uint32_t OC1FEN : 1; + __IOM uint32_t OC1PEN : 1; + __IOM uint32_t OC1MOD : 3; + __IOM uint32_t OC1CEN : 1; + __IOM uint32_t CC2SEL : 2; + __IOM uint32_t OC2FEN : 1; + __IOM uint32_t OC2PEN : 1; + __IOM uint32_t OC2MOD : 3; + __IOM uint32_t OC2CEN : 1; + __IM uint32_t RESERVED : 16; + } CCM1_COMPARE_B; + + /** @brief Capture mode */ + struct + { + __IOM uint32_t CC1SEL : 2; + __IOM uint32_t IC1PSC : 2; + __IOM uint32_t IC1F : 4; + __IOM uint32_t CC2SEL : 2; + __IOM uint32_t IC2PSC : 2; + __IOM uint32_t IC2F : 4; + __IM uint32_t RESERVED : 16; + } CCM1_CAPTURE_B; + }; + + /** @brief Capture the compare mode register 2 */ + union + { + __IOM uint32_t CCM2; + + /** @brief Compare mode */ + struct + { + __IOM uint32_t CC3SEL : 2; + __IOM uint32_t OC3FEN : 1; + __IOM uint32_t OC3PEN : 1; + __IOM uint32_t OC3MODE : 3; + __IOM uint32_t OC3CEN : 1; + __IOM uint32_t CC4SEL : 2; + __IOM uint32_t OC4FEN : 1; + __IOM uint32_t OC4PEN : 1; + __IOM uint32_t OC4MODE : 3; + __IOM uint32_t OC4CEN : 1; + __IM uint32_t RESERVED : 16; + } CCM2_COMPARE_B; + + /** @brief Capture mode */ + struct + { + __IOM uint32_t CC3SEL : 2; + __IOM uint32_t IC3PSC : 2; + __IOM uint32_t IC3F : 4; + __IOM uint32_t CC4SEL : 2; + __IOM uint32_t IC4PSC : 2; + __IOM uint32_t IC4F : 4; + __IM uint32_t RESERVED : 16; + } CCM2_CAPTURE_B; + }; + + /** @brief Channel control register */ + union + { + __IOM uint32_t CCEN; + + struct + { + __IOM uint32_t CC1EN : 1; + __IOM uint32_t CC1POL : 1; + __IOM uint32_t CC1NEN : 1; + __IOM uint32_t CC1NPOL : 1; + __IOM uint32_t CC2EN : 1; + __IOM uint32_t CC2POL : 1; + __IOM uint32_t CC2NEN : 1; + __IOM uint32_t CC2NPOL : 1; + __IOM uint32_t CC3EN : 1; + __IOM uint32_t CC3POL : 1; + __IOM uint32_t CC3NEN : 1; + __IOM uint32_t CC3NPOL : 1; + __IOM uint32_t CC4EN : 1; + __IOM uint32_t CC4POL : 1; + __IM uint32_t RESERVED : 18; + } CCEN_B; + }; + + /** @brief Counting register */ + union + { + __IOM uint32_t CNT; + + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + } CNT_B; + }; + + /** @brief Division register */ + union + { + __IOM uint32_t PSC; + + struct + { + __IOM uint32_t PSC : 16; + __IM uint32_t RESERVED : 16; + } PSC_B; + }; + + /** @brief Automatic reload register */ + union + { + __IOM uint32_t AUTORLD; + + struct + { + __IOM uint32_t AUTORLD : 16; + __IM uint32_t RESERVED : 16; + } AUTORLD_B; + }; + + /** @brief Repeat count register */ + union + { + __IOM uint32_t REPCNT; + + struct + { + __IOM uint32_t REPCNT : 8; + __IM uint32_t RESERVED : 24; + } REPCNT_B; + }; + + /** @brief Capture comparison register channel 1 */ + union + { + __IOM uint32_t CC1; + + struct + { + __IOM uint32_t CC1 : 16; + __IM uint32_t RESERVED : 16; + } CC1_B; + }; + + /** @brief Capture comparison register channel 2 */ + union + { + __IOM uint32_t CC2; + + struct + { + __IOM uint32_t CC2 : 16; + __IM uint32_t RESERVED : 16; + } CC2_B; + }; + + /** @brief Capture comparison register channel 3 */ + union + { + __IOM uint32_t CC3; + + struct + { + __IOM uint32_t CC3 : 16; + __IM uint32_t RESERVED : 16; + } CC3_B; + }; + + /** @brief Capture comparison register channel 4 */ + union + { + __IOM uint32_t CC4; + + struct + { + __IOM uint32_t CC4 : 16; + __IM uint32_t RESERVED : 16; + } CC4_B; + }; + + /** @brief Brake and dead zone registers */ + union + { + __IOM uint32_t BDT; + + struct + { + __IOM uint32_t DTS : 8; + __IOM uint32_t LOCKCFG : 2; + __IOM uint32_t IMOS : 1; + __IOM uint32_t RMOS : 1; + __IOM uint32_t BRKEN : 1; + __IOM uint32_t BRKPOL : 1; + __IOM uint32_t AOEN : 1; + __IOM uint32_t MOEN : 1; + __IM uint32_t RESERVED : 16; + } BDT_B; + }; + + /** @brief DMA control register */ + union + { + __IOM uint32_t DCTRL; + + struct + { + __IOM uint32_t DBADDR : 5; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t DBLEN : 5; + __IM uint32_t RESERVED2 : 19; + } DCTRL_B; + }; + + /** @brief Consecutive DMA addresses */ + union + { + __IOM uint32_t DMADDR; + struct + { + __IOM uint32_t DMADDR : 16; + __IM uint32_t RESERVED2 : 16; + } DMADDR_B; + }; +} TMR_T; + +/** + * @brief Direct Memory Access register(DMA) + */ +typedef struct +{ + /** @brief Interrupt status register */ + union + { + __IM uint32_t INTSTS; + + struct + { + __IM uint32_t GINTFLG1 : 1; + __IM uint32_t TCFLG1 : 1; + __IM uint32_t HTFLG1 : 1; + __IM uint32_t TERRFLG1 : 1; + __IM uint32_t GINTFLG2 : 1; + __IM uint32_t TCFLG2 : 1; + __IM uint32_t HTFLG2 : 1; + __IM uint32_t TERRFLG2 : 1; + __IM uint32_t GINTFLG3 : 1; + __IM uint32_t TCFLG3 : 1; + __IM uint32_t HTFLG3 : 1; + __IM uint32_t TERRFLG3 : 1; + __IM uint32_t GINTFLG4 : 1; + __IM uint32_t TCFLG4 : 1; + __IM uint32_t HTFLG4 : 1; + __IM uint32_t TERRFLG4 : 1; + __IM uint32_t GINTFLG5 : 1; + __IM uint32_t TCFLG5 : 1; + __IM uint32_t HTFLG5 : 1; + __IM uint32_t TERRFLG5 : 1; + __IM uint32_t GINTFLG6 : 1; + __IM uint32_t TCFLG6 : 1; + __IM uint32_t HTFLG6 : 1; + __IM uint32_t TERRFLG6 : 1; + __IM uint32_t GINTFLG7 : 1; + __IM uint32_t TCFLG7 : 1; + __IM uint32_t HTFLG7 : 1; + __IM uint32_t TERRFLG7 : 1; + __IM uint32_t RESERVED : 4; + } INTSTS_B; + }; + + /** @brief Interrupt reset register */ + union + { + __OM uint32_t INTFCLR; + + struct + { + __OM uint32_t GINTCLR1 : 1; + __OM uint32_t TCCLR1 : 1; + __OM uint32_t HTCLR1 : 1; + __OM uint32_t TERRCLR1 : 1; + __OM uint32_t GINTCLR2 : 1; + __OM uint32_t TCCLR2 : 1; + __OM uint32_t HTCLR2 : 1; + __OM uint32_t TERRCLR2 : 1; + __OM uint32_t GINTCLR3 : 1; + __OM uint32_t TCCLR3 : 1; + __OM uint32_t HTCLR3 : 1; + __OM uint32_t TERRCLR3 : 1; + __OM uint32_t GINTCLR4 : 1; + __OM uint32_t TCCLR4 : 1; + __OM uint32_t HTCLR4 : 1; + __OM uint32_t TERRCLR4 : 1; + __OM uint32_t GINTCLR5 : 1; + __OM uint32_t TCCLR5 : 1; + __OM uint32_t HTCLR5 : 1; + __OM uint32_t TERRCLR5 : 1; + __OM uint32_t GINTCLR6 : 1; + __OM uint32_t TCCLR6 : 1; + __OM uint32_t HTCLR6 : 1; + __OM uint32_t TERRCLR6 : 1; + __OM uint32_t GINTCLR7 : 1; + __OM uint32_t TCCLR7 : 1; + __OM uint32_t HTCLR7 : 1; + __OM uint32_t TERRCLR7 : 1; + __IM uint32_t RESERVED : 4; + } INTFCLR_B; + }; +} DMA_T; + +/** + * @brief DMA Channel register + */ +typedef struct +{ + /** @brief DMA Channel setup register */ + union + { + + __IOM uint32_t CHCFG; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MEMSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED : 17; + } CHCFG_B; + }; + + /** @brief DMA Channel transfer number register*/ + union + { + __IOM uint32_t CHNDATA; + + struct + { + __IOM uint32_t NDATA : 16; + __IM uint32_t RESERVED : 16; + } CHNDATA_B; + }; + + /** @brief DMA Channel peripheral address register */ + union + { + __IOM uint32_t CHPADDR; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR_B; + }; + + /** @brief DMA Channel memory address register */ + union + { + __IOM uint32_t CHMADDR; + + struct + { + __IOM uint32_t MEMADDR : 32; + } CHMADDR_B; + }; +} DMA_Channel_T; + +/** + * @brief CAN sending mailbox + */ +typedef struct +{ + /** @brief CAN Each mailbox contains the sending mailbox identifier register */ + union + { + __IOM uint32_t TXMID; + + struct + { + __IOM uint32_t TXMREQ : 1; + __IOM uint32_t TXRFREQ : 1; + __IOM uint32_t IDTYPESEL : 1; + __IOM uint32_t EXTID : 18; + __IOM uint32_t STDID : 11; + } TXMID_B; + }; + + /** @brief CAN Send the mailbox data length and timestamp register */ + union + { + __IOM uint32_t TXDLEN; + + struct + { + __IOM uint32_t DLCODE : 4; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t TXTS : 1; + __IM uint32_t RESERVED2 : 7; + __IOM uint32_t MTS : 16; + } TXDLEN_B; + }; + + /** @brief CAN Send mailbox low byte data register */ + union + { + __IOM uint32_t TXMDL; + + struct + { + __IOM uint32_t DATABYTE0 : 8; + __IOM uint32_t DATABYTE1 : 8; + __IOM uint32_t DATABYTE2 : 8; + __IOM uint32_t DATABYTE3 : 8; + } TXMDL_B; + }; + + /** @brief CAN Send mailbox High byte data register */ + union + { + __IOM uint32_t TXMDH; + + struct + { + __IOM uint32_t DATABYTE4 : 8; + __IOM uint32_t DATABYTE5 : 8; + __IOM uint32_t DATABYTE6 : 8; + __IOM uint32_t DATABYTE7 : 8; + } TXMDH_B; + }; +} CAN_TxMailBox_T; + +/** + * @brief CAN receive mailbox + */ +typedef struct +{ + /** @brief CAN Each mailbox contains the receive mailbox identifier register */ + union + { + __IM uint32_t RXMID; + + struct + { + __IM uint32_t RESERVED : 1; + __IM uint32_t RFTXREQ : 1; + __IM uint32_t IDTYPESEL : 1; + __IM uint32_t EXTID : 18; + __IM uint32_t STDID : 11; + } RXMID_B; + }; + + /** @brief CAN receive the mailbox data length and timestamp register */ + union + { + __IM uint32_t RXDLEN; + + struct + { + __IM uint32_t DLCODE : 4; + __IM uint32_t RESERVED : 4; + __IM uint32_t FMIDX : 8; + __IM uint32_t MTS : 16; + } RXDLEN_B; + }; + + /** @brief CAN receive mailbox low byte data register */ + union + { + __IM uint32_t RXMDL; + + struct + { + __IM uint32_t DATABYTE1 : 8; + __IM uint32_t DATABYTE2 : 8; + __IM uint32_t DATABYTE3 : 8; + __IM uint32_t DATABYTE4 : 8; + } RXMDL_B; + }; + + /** @briefCAN receive mailbox High byte data register */ + union + { + __IOM uint32_t RXMDH; + + struct + { + __IM uint32_t DATABYTE5 : 8; + __IM uint32_t DATABYTE6 : 8; + __IM uint32_t DATABYTE7 : 8; + __IM uint32_t DATABYTE8 : 8; + } RXMDH_B; + }; +} CAN_RxMailBox_T; + +/** + * @brief CAN Filter bank register + */ +typedef struct +{ + /** @brief CAN Filter bank register 1 */ + union + { + __IOM uint32_t FBANK1; + + struct + { + __IOM uint32_t FBIT0 : 1; + __IOM uint32_t FBIT1 : 1; + __IOM uint32_t FBIT2 : 1; + __IOM uint32_t FBIT3 : 1; + __IOM uint32_t FBIT4 : 1; + __IOM uint32_t FBIT5 : 1; + __IOM uint32_t FBIT6 : 1; + __IOM uint32_t FBIT7 : 1; + __IOM uint32_t FBIT8 : 1; + __IOM uint32_t FBIT9 : 1; + __IOM uint32_t FBIT10 : 1; + __IOM uint32_t FBIT11 : 1; + __IOM uint32_t FBIT12 : 1; + __IOM uint32_t FBIT13 : 1; + __IOM uint32_t FBIT14 : 1; + __IOM uint32_t FBIT15 : 1; + __IOM uint32_t FBIT16 : 1; + __IOM uint32_t FBIT17 : 1; + __IOM uint32_t FBIT18 : 1; + __IOM uint32_t FBIT19 : 1; + __IOM uint32_t FBIT20 : 1; + __IOM uint32_t FBIT21 : 1; + __IOM uint32_t FBIT22 : 1; + __IOM uint32_t FBIT23 : 1; + __IOM uint32_t FBIT24 : 1; + __IOM uint32_t FBIT25 : 1; + __IOM uint32_t FBIT26 : 1; + __IOM uint32_t FBIT27 : 1; + __IOM uint32_t FBIT28 : 1; + __IOM uint32_t FBIT29 : 1; + __IOM uint32_t FBIT30 : 1; + __IOM uint32_t FBIT31 : 1; + } FBANK1_B; + }; + + /** @brief CAN Filter bank register 1 */ + union + { + __IOM uint32_t FBANK2; + + struct + { + __IOM uint32_t FBIT0 : 1; + __IOM uint32_t FBIT1 : 1; + __IOM uint32_t FBIT2 : 1; + __IOM uint32_t FBIT3 : 1; + __IOM uint32_t FBIT4 : 1; + __IOM uint32_t FBIT5 : 1; + __IOM uint32_t FBIT6 : 1; + __IOM uint32_t FBIT7 : 1; + __IOM uint32_t FBIT8 : 1; + __IOM uint32_t FBIT9 : 1; + __IOM uint32_t FBIT10 : 1; + __IOM uint32_t FBIT11 : 1; + __IOM uint32_t FBIT12 : 1; + __IOM uint32_t FBIT13 : 1; + __IOM uint32_t FBIT14 : 1; + __IOM uint32_t FBIT15 : 1; + __IOM uint32_t FBIT16 : 1; + __IOM uint32_t FBIT17 : 1; + __IOM uint32_t FBIT18 : 1; + __IOM uint32_t FBIT19 : 1; + __IOM uint32_t FBIT20 : 1; + __IOM uint32_t FBIT21 : 1; + __IOM uint32_t FBIT22 : 1; + __IOM uint32_t FBIT23 : 1; + __IOM uint32_t FBIT24 : 1; + __IOM uint32_t FBIT25 : 1; + __IOM uint32_t FBIT26 : 1; + __IOM uint32_t FBIT27 : 1; + __IOM uint32_t FBIT28 : 1; + __IOM uint32_t FBIT29 : 1; + __IOM uint32_t FBIT30 : 1; + __IOM uint32_t FBIT31 : 1; + } FBANK2_B; + }; +} CAN_FilterRegister_T; + +/** + * @brief Controller Area Network(CAN) + */ +typedef struct +{ + /** @brief CAN Master control register */ + union + { + __IOM uint32_t MCTRL; + + struct + { + __IOM uint32_t INITREQ : 1; + __IOM uint32_t SLEEPREQ : 1; + __IOM uint32_t TXFPCFG : 1; + __IOM uint32_t RXFLOCK : 1; + __IOM uint32_t ARTXMD : 1; + __IOM uint32_t AWUPCFG : 1; + __IOM uint32_t ALBOFFM : 1; + __IOM uint32_t TTCM : 1; + __IM uint32_t RESERVED1 : 7; + __IOM uint32_t SWRST : 1; + __IOM uint32_t DBGFRZE : 1; + __IM uint32_t RESERVED2 : 15; + } MCTRL_B; + }; + + /** @brief CAN Master States register */ + union + { + __IOM uint32_t MSTS; + + struct + { + __IM uint32_t INITFLG : 1; + __IM uint32_t SLEEPFLG : 1; + __IOM uint32_t ERRIFLG : 1; + __IOM uint32_t WUPIFLG : 1; + __IOM uint32_t SLEEPIFLG : 1; + __IM uint32_t RESERVED1 : 3; + __IM uint32_t TXMFLG : 1; + __IM uint32_t RXMFLG : 1; + __IM uint32_t LSAMVALUE : 1; + __IM uint32_t RXSIGL : 1; + __IM uint32_t RESERVED2 : 20; + } MSTS_B; + }; + + /** @brief CAN Send States register */ + union + { + __IOM uint32_t TXSTS; + + struct + { + __IOM uint32_t REQCFLG0 : 1; + __IOM uint32_t TXSUSFLG0 : 1; + __IOM uint32_t ARBLSTFLG0 : 1; + __IOM uint32_t TXERRFLG0 : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ABREQFLG0 : 1; + __IOM uint32_t REQCFLG1 : 1; + __IOM uint32_t TXSUSFLG1 : 1; + __IOM uint32_t ARBLSTFLG1 : 1; + __IOM uint32_t TXERRFLG1 : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t ABREQFLG1 : 1; + __IOM uint32_t REQCFLG2 : 1; + __IOM uint32_t TXSUSFLG2 : 1; + __IOM uint32_t ARBLSTFLG2 : 1; + __IOM uint32_t TXERRFLG2 : 1; + __IM uint32_t RESERVED3 : 3; + __IOM uint32_t ABREQFLG2 : 1; + __IM uint32_t EMNUM : 2; + __IM uint32_t TXMEFLG0 : 1; + __IM uint32_t TXMEFLG1 : 1; + __IM uint32_t TXMEFLG2 : 1; + __IM uint32_t LOWESTP0 : 1; + __IM uint32_t LOWESTP1 : 1; + __IM uint32_t LOWESTP2 : 1; + } TXSTS_B; + }; + + /** @brief CAN Receive FIFO 0 register */ + union + { + __IOM uint32_t RXF0; + + struct + { + __IM uint32_t FMNUM0 : 2; + __IM uint32_t RESERVED : 1; + __IOM uint32_t FFULLFLG0 : 1; + __IOM uint32_t FOVRFLG0 : 1; + __IOM uint32_t RFOM0 : 1; + __IM uint32_t RESERVED2 : 26; + } RXF0_B; + }; + + /** @brief CAN Receive FIFO 1 register */ + union + { + __IOM uint32_t RXF1; + + struct + { + __IM uint32_t FMNUM1 : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t FFULLFLG1 : 1; + __IOM uint32_t FOVRFLG1 : 1; + __IOM uint32_t RFOM1 : 1; + __IM uint32_t RESERVED2 : 26; + } RXF1_B; + }; + + /** @brief CAN Interrupts register */ + union + { + __IOM uint32_t INTEN; + + struct + { + __IOM uint32_t TXMEIEN : 1; + __IOM uint32_t FMIEN0 : 1; + __IOM uint32_t FFULLIEN0 : 1; + __IOM uint32_t FOVRIEN0 : 1; + __IOM uint32_t FMIEN1 : 1; + __IOM uint32_t FFULLIEN1 : 1; + __IOM uint32_t FOVRIEN1 : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t ERRWIEN : 1; + __IOM uint32_t ERRPIEN : 1; + __IOM uint32_t BOFFIEN : 1; + __IOM uint32_t LECIEN : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t WUPIEN : 1; + __IOM uint32_t SLEEPIEN : 1; + __IM uint32_t RESERVED3 : 14; + } INTEN_B; + }; + + /** @brief CAN Error States register */ + union + { + __IOM uint32_t ERRSTS; + + struct + { + __IM uint32_t ERRWFLG : 1; + __IM uint32_t ERRPFLG : 1; + __IM uint32_t BOFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t LERRC : 3; + __IM uint32_t RESERVED2 : 9; + __IM uint32_t TXERRCNT : 8; + __IM uint32_t RXERRCNT : 8; + } ERRSTS_B; + }; + + /** @brief CAN Bit Time register */ + union + { + __IOM uint32_t BITTIM; + + struct + { + __IOM uint32_t BRPSC : 10; + __IM uint32_t RESERVED1 : 6; + __IOM uint32_t TIMSEG1 : 4; + __IOM uint32_t TIMSEG2 : 3; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t RSYNJW : 2; + __IM uint32_t RESERVED3 : 4; + __IOM uint32_t LBKMEN : 1; + __IOM uint32_t SILMEN : 1; + } BITTIM_B; + }; + + __IM uint32_t RESERVED0[88]; + + CAN_TxMailBox_T sTxMailBox[3]; + CAN_RxMailBox_T sRxMailBox[2]; + + __IM uint32_t RESERVED1[12]; + + /** @brief CAN Filter the master control register */ + union + { + __IOM uint32_t FCTRL; + + struct + { + __IOM uint32_t FINITEN : 1; + __IM uint32_t RESERVED : 31; + } FCTRL_B; + }; + + /** @brief CAN Filter register */ + union + { + __IOM uint32_t FMCFG; + + struct + { + __IOM uint32_t FMCFG0 : 1; + __IOM uint32_t FMCFG1 : 1; + __IOM uint32_t FMCFG2 : 1; + __IOM uint32_t FMCFG3 : 1; + __IOM uint32_t FMCFG4 : 1; + __IOM uint32_t FMCFG5 : 1; + __IOM uint32_t FMCFG6 : 1; + __IOM uint32_t FMCFG7 : 1; + __IOM uint32_t FMCFG8 : 1; + __IOM uint32_t FMCFG9 : 1; + __IOM uint32_t FMCFG10 : 1; + __IOM uint32_t FMCFG11 : 1; + __IOM uint32_t FMCFG12 : 1; + __IOM uint32_t FMCFG13 : 1; + __IM uint32_t RESERVED : 18; + } FMCFG_B; + }; + + __IM uint32_t RESERVED2; + + /** @brief CAN Filter bit scale register */ + union + { + __IOM uint32_t FSCFG; + + struct + { + __IOM uint32_t FSCFG0 : 1; + __IOM uint32_t FSCFG1 : 1; + __IOM uint32_t FSCFG2 : 1; + __IOM uint32_t FSCFG3 : 1; + __IOM uint32_t FSCFG4 : 1; + __IOM uint32_t FSCFG5 : 1; + __IOM uint32_t FSCFG6 : 1; + __IOM uint32_t FSCFG7 : 1; + __IOM uint32_t FSCFG8 : 1; + __IOM uint32_t FSCFG9 : 1; + __IOM uint32_t FSCFG10 : 1; + __IOM uint32_t FSCFG11 : 1; + __IOM uint32_t FSCFG12 : 1; + __IOM uint32_t FSCFG13 : 1; + __IM uint32_t RESERVED : 18; + }FSCFG_B; + }; + + __IM uint32_t RESERVED3; + + /** @brief CAN Filter FIFO associated registers */ + union + { + __IOM uint32_t FFASS; + + struct + { + __IOM uint32_t FFASS0 : 1; + __IOM uint32_t FFASS1 : 1; + __IOM uint32_t FFASS2 : 1; + __IOM uint32_t FFASS3 : 1; + __IOM uint32_t FFASS4 : 1; + __IOM uint32_t FFASS5 : 1; + __IOM uint32_t FFASS6 : 1; + __IOM uint32_t FFASS7 : 1; + __IOM uint32_t FFASS8 : 1; + __IOM uint32_t FFASS9 : 1; + __IOM uint32_t FFASS10 : 1; + __IOM uint32_t FFASS11 : 1; + __IOM uint32_t FFASS12 : 1; + __IOM uint32_t FFASS13 : 1; + __IM uint32_t RESERVED : 18; + } FFASS_B; + }; + + __IM uint32_t RESERVED4; + + /** @brief CAN Filter activation register */ + union + { + __IOM uint32_t FACT; + + struct + { + __IOM uint32_t FACT0 : 1; + __IOM uint32_t FACT1 : 1; + __IOM uint32_t FACT2 : 1; + __IOM uint32_t FACT3 : 1; + __IOM uint32_t FACT4 : 1; + __IOM uint32_t FACT5 : 1; + __IOM uint32_t FACT6 : 1; + __IOM uint32_t FACT7 : 1; + __IOM uint32_t FACT8 : 1; + __IOM uint32_t FACT9 : 1; + __IOM uint32_t FACT10 : 1; + __IOM uint32_t FACT11 : 1; + __IOM uint32_t FACT12 : 1; + __IOM uint32_t FACT13 : 1; + __IM uint32_t RESERVED : 18; + } FACT_B; + }; + + __IM uint32_t RESERVED5[8]; + + CAN_FilterRegister_T sFilterRegister[14]; + +} CAN_T; + +/** + * @brief I2C register (I2C) + */ +typedef struct +{ + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t I2CEN : 1; + __IOM uint32_t SMBEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t SMBTCFG : 1; + __IOM uint32_t ARPEN : 1; + __IOM uint32_t PECEN : 1; + __IOM uint32_t SRBEN : 1; + __IOM uint32_t CLKSTRETCHD : 1; + __IOM uint32_t START : 1; + __IOM uint32_t STOP : 1; + __IOM uint32_t ACKEN : 1; + __IOM uint32_t ACKPOS : 1; + __IOM uint32_t PEC : 1; + __IOM uint32_t ALERTEN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t SWRST : 1; + __IM uint32_t RESERVED3 : 16; + } CTRL1_B; + } ; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t CLKFCFG : 6; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t EVIEN : 1; + __IOM uint32_t BUFIEN : 1; + __IOM uint32_t DMAEN : 1; + __IOM uint32_t LTCFG : 1; + __IM uint32_t RESERVED2 : 19; + } CTRL2_B; + } ; + + /** @brief Slave machine address register 1 */ + union + { + __IOM uint32_t SADDR1; + + struct + { + __IOM uint32_t ADDR0 : 1; + __IOM uint32_t ADDR1_7 : 7; + __IOM uint32_t ADDR8_9 : 2; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t ADDRLEN : 1; + __IM uint32_t RESERVED2 : 16; + } SADDR1_B; + }; + + /** @brief Slave machine address register 2 */ + union + { + __IOM uint32_t SADDR2; + + struct + { + __IOM uint32_t ADDRNUM : 1; + __IOM uint32_t ADDR2 : 7; + __IM uint32_t RESERVED : 24; + } SADDR2_B; + }; + + /** @brief Cache data register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED : 24; + } DATA_B; + }; + + /** @brief Status register 1 */ + union + { + __IOM uint32_t STS1; + + struct + { + __IM uint32_t STARTFLG : 1; + __IM uint32_t ADDRFLG : 1; + __IM uint32_t BTCFLG : 1; + __IM uint32_t ADDR10FLG : 1; + __IM uint32_t STOPFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t RXBNEFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IOM uint32_t BERRFLG : 1; + __IOM uint32_t ALFLG : 1; + __IOM uint32_t AEFLG : 1; + __IOM uint32_t OVRURFLG : 1; + __IOM uint32_t PECEFLG : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t TTEFLG : 1; + __IOM uint32_t SMBALTFLG : 1; + __IM uint32_t RESERVED3 : 16; + } STS1_B; + }; + + /** @brief Status register 2 */ + union + { + __IOM uint32_t STS2; + + struct + { + __IM uint32_t MSFLG : 1; + __IM uint32_t BUSBSYFLG : 1; + __IM uint32_t TRFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t GENCALLFLG : 1; + __IM uint32_t SMBDADDRFLG : 1; + __IM uint32_t SMMHADDR : 1; + __IM uint32_t DUALADDRFLG : 1; + __IM uint32_t PECVALUE : 8; + __IM uint32_t RESERVED2 : 16; + } STS2_B; + }; + + /** @brief Clock control register */ + union + { + __IOM uint32_t CLKCTRL; + + struct + { + __IOM uint32_t CLKS : 12; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t FDUTYCFG : 1; + __IOM uint32_t SPEEDCFG : 1; + __IM uint32_t RESERVED2 : 16; + } CLKCTRL_B; + }; + + /** @brief Maximum rise time */ + union + { + __IOM uint32_t RISETMAX; + + struct + { + __IOM uint32_t RISETMAX : 6; + __IM uint32_t RESERVED : 26; + } RISETMAX_B; + }; + + __IM uint32_t RESERVED[55]; + + /** @brief I2C Switching register */ + union + { + __IOM uint32_t SWITCH; + + struct + { + __IOM uint32_t SWITCH : 1; + __IM uint32_t RESERVED1 : 31; + } SWITCH_B; + }; +} I2C_T; + + +typedef struct +{ + __IOM uint16_t RDP; + __IOM uint16_t USER; + __IOM uint16_t Data0; + __IOM uint16_t Data1; + __IOM uint16_t WRP0; + __IOM uint16_t WRP1; + __IOM uint16_t WRP2; + __IOM uint16_t WRP3; +} OB_T; + +/** + * @brief Analog to Digital Converter(ADC) + */ +typedef struct +{ + + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t AWDFLG : 1; + __IOM uint32_t EOCFLG : 1; + __IOM uint32_t INJEOCFLG : 1; + __IOM uint32_t INJCSFLG : 1; + __IOM uint32_t REGCSFLG : 1; + __IM uint32_t RESERVED : 27; + } STS_B; + }; + + /** Control register1*/ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t AWDCHSEL : 5; + __IOM uint32_t EOCIEN : 1; + __IOM uint32_t AWDIEN : 1; + __IOM uint32_t INJEOCIEN : 1; + __IOM uint32_t SCANEN : 1; + __IOM uint32_t AWDSGLEN : 1; + __IOM uint32_t INJGACEN : 1; + __IOM uint32_t REGDISCEN : 1; + __IOM uint32_t INJDISCEN : 1; + __IOM uint32_t DISCNUMCFG : 3; + __IOM uint32_t DUALMCFG : 4; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t INJAWDEN : 1; + __IOM uint32_t REGAWDEN : 1; + __IM uint32_t RESERVED2 : 8; + } CTRL1_B; + }; + + /** Control register2*/ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t ADCEN : 1; + __IOM uint32_t CONTCEN : 1; + __IOM uint32_t CAL : 1; + __IOM uint32_t CALRST : 1; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DMAEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t DALIGNCFG : 1; + __IOM uint32_t INJGEXTTRGSEL : 3; + __IOM uint32_t INJEXTTRGEN : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t REGEXTTRGSEL : 3; + __IOM uint32_t REGEXTTRGEN : 1; + __IOM uint32_t INJSWSC : 1; + __IOM uint32_t REGSWSC : 1; + __IOM uint32_t TSVREFEN : 1; + __IM uint32_t RESERVED4 : 8; + } CTRL2_B; + }; + + /** Sample time register1*/ + union + { + __IOM uint32_t SMPTIM1; + + struct + { + __IOM uint32_t SMPCYCCFG10 : 3; + __IOM uint32_t SMPCYCCFG11 : 3; + __IOM uint32_t SMPCYCCFG12 : 3; + __IOM uint32_t SMPCYCCFG13 : 3; + __IOM uint32_t SMPCYCCFG14 : 3; + __IOM uint32_t SMPCYCCFG15 : 3; + __IOM uint32_t SMPCYCCFG16 : 3; + __IOM uint32_t SMPCYCCFG17 : 3; + __IM uint32_t RESERVED : 8; + } SMPTIM1_B; + }; + + /** Sample time register2*/ + union + { + __IOM uint32_t SMPTIM2; + + struct + { + __IOM uint32_t SMPCYCCFG0 : 3; + __IOM uint32_t SMPCYCCFG1 : 3; + __IOM uint32_t SMPCYCCFG2 : 3; + __IOM uint32_t SMPCYCCFG3 : 3; + __IOM uint32_t SMPCYCCFG4 : 3; + __IOM uint32_t SMPCYCCFG5 : 3; + __IOM uint32_t SMPCYCCFG6 : 3; + __IOM uint32_t SMPCYCCFG7 : 3; + __IOM uint32_t SMPCYCCFG8 : 3; + __IOM uint32_t SMPCYCCFG9 : 3; + __IM uint32_t RESERVED : 2; + } SMPTIM2_B; + }; + + /** Injected channel Data offset register1*/ + union + { + __IOM uint32_t INJDOF1; + + struct + { + __IOM uint32_t INJDOF1 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF1_B; + }; + + /** Injected channel Data offset register2*/ + union + { + __IOM uint32_t INJDOF2; + + struct + { + __IOM uint32_t INJDOF2 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF2_B; + }; + + /** Injected channel Data offset register3*/ + union + { + __IOM uint32_t INJDOF3; + + struct + { + __IOM uint32_t INJDOF3 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF3_B; + }; + + /** Injected channel Data offset register4*/ + union + { + __IOM uint32_t INJDOF4; + + struct + { + __IOM uint32_t INJDOF4 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF4_B; + }; + + /** Analog watchdog high threshold register*/ + union + { + __IOM uint32_t AWDHT; + + struct + { + __IOM uint32_t AWDHT : 12; + __IM uint32_t RESERVED : 20; + } AWDHT_B; + }; + + /** Analog watchdog low threshold register*/ + union + { + __IOM uint32_t AWDLT; + + struct + { + __IOM uint32_t AWDLT : 12; + __IM uint32_t RESERVED : 20; + } AWDLT_B; + }; + + /** Regular channel sequence register1*/ + union + { + __IOM uint32_t REGSEQ1; + + struct + { + __IOM uint32_t REGSEQC13 : 5; + __IOM uint32_t REGSEQC14 : 5; + __IOM uint32_t REGSEQC15 : 5; + __IOM uint32_t REGSEQC16 : 5; + __IOM uint32_t REGSEQLEN : 4; + __IM uint32_t RESERVED : 8; + } REGSEQ1_B; + }; + + /** Regular channel sequence register2*/ + union + { + __IOM uint32_t REGSEQ2; + + struct + { + __IOM uint32_t REGSEQC7 : 5; + __IOM uint32_t REGSEQC8 : 5; + __IOM uint32_t REGSEQC9 : 5; + __IOM uint32_t REGSEQC10 : 5; + __IOM uint32_t REGSEQC11 : 5; + __IOM uint32_t REGSEQC12 : 5; + __IM uint32_t RESERVED : 2; + } REGSEQ2_B; + }; + + /** Regular channel sequence register3*/ + union + { + __IOM uint32_t REGSEQ3; + + struct + { + __IOM uint32_t REGSEQC1 : 5; + __IOM uint32_t REGSEQC2 : 5; + __IOM uint32_t REGSEQC3 : 5; + __IOM uint32_t REGSEQC4 : 5; + __IOM uint32_t REGSEQC5 : 5; + __IOM uint32_t REGSEQC6 : 5; + __IM uint32_t RESERVED : 2; + } REGSEQ3_B; + }; + + /** Injected sequence register*/ + union + { + __IOM uint32_t INJSEQ; + + struct + { + __IOM uint32_t INJSEQC1 : 5; + __IOM uint32_t INJSEQC2 : 5; + __IOM uint32_t INJSEQC3 : 5; + __IOM uint32_t INJSEQC4 : 5; + __IOM uint32_t INJSEQLEN : 2; + __IM uint32_t RESERVED : 10; + } INJSEQ_B; + }; + + /** Injected Data register1*/ + union + { + __IM uint32_t INJDATA1; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA1_B; + }; + + /** Injected Data register2*/ + union + { + __IM uint32_t INJDATA2; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA2_B; + }; + + /** Injected Data register3*/ + union + { + __IM uint32_t INJDATA3; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA3_B; + }; + + /** Injected Data register4*/ + union + { + __IM uint32_t INJDATA4; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA4_B; + }; + + /** Regular Data register*/ + union + { + __IOM uint32_t REGDATA; + + struct + { + __IM uint32_t REGDATA : 16; + __IM uint32_t ADC2DATA : 16; + } REGDATA_B; + }; +}ADC_T; + +/** + * @brief External Interrupt(EINT) + */ +typedef struct +{ + /** Interrupt mask register */ + union + { + __IOM uint32_t IMASK; + + struct + { + __IOM uint32_t IMASK0 : 1; + __IOM uint32_t IMASK1 : 1; + __IOM uint32_t IMASK2 : 1; + __IOM uint32_t IMASK3 : 1; + __IOM uint32_t IMASK4 : 1; + __IOM uint32_t IMASK5 : 1; + __IOM uint32_t IMASK6 : 1; + __IOM uint32_t IMASK7 : 1; + __IOM uint32_t IMASK8 : 1; + __IOM uint32_t IMASK9 : 1; + __IOM uint32_t IMASK10 : 1; + __IOM uint32_t IMASK11 : 1; + __IOM uint32_t IMASK12 : 1; + __IOM uint32_t IMASK13 : 1; + __IOM uint32_t IMASK14 : 1; + __IOM uint32_t IMASK15 : 1; + __IOM uint32_t IMASK16 : 1; + __IOM uint32_t IMASK17 : 1; + __IOM uint32_t IMASK18 : 1; + __IM uint32_t RESERVED : 12; + } IMASK_B; + }; + + /** Event mask register */ + union + { + __IOM uint32_t EMASK; + + struct + { + __IOM uint32_t EMASK0 : 1; + __IOM uint32_t EMASK1 : 1; + __IOM uint32_t EMASK2 : 1; + __IOM uint32_t EMASK3 : 1; + __IOM uint32_t EMASK4 : 1; + __IOM uint32_t EMASK5 : 1; + __IOM uint32_t EMASK6 : 1; + __IOM uint32_t EMASK7 : 1; + __IOM uint32_t EMASK8 : 1; + __IOM uint32_t EMASK9 : 1; + __IOM uint32_t EMASK10 : 1; + __IOM uint32_t EMASK11 : 1; + __IOM uint32_t EMASK12 : 1; + __IOM uint32_t EMASK13 : 1; + __IOM uint32_t EMASK14 : 1; + __IOM uint32_t EMASK15 : 1; + __IOM uint32_t EMASK16 : 1; + __IOM uint32_t EMASK17 : 1; + __IOM uint32_t EMASK18 : 1; + __IM uint32_t RESERVED : 12; + } EEN_B; + }; + + /** Rising Trigger Event Enable register */ + union + { + __IOM uint32_t RTEN; + + struct + { + __IOM uint32_t PTEN0 : 1; + __IOM uint32_t PTEN1 : 1; + __IOM uint32_t PTEN2 : 1; + __IOM uint32_t PTEN3 : 1; + __IOM uint32_t PTEN4 : 1; + __IOM uint32_t PTEN5 : 1; + __IOM uint32_t PTEN6 : 1; + __IOM uint32_t PTEN7 : 1; + __IOM uint32_t PTEN8 : 1; + __IOM uint32_t PTEN9 : 1; + __IOM uint32_t PTEN10 : 1; + __IOM uint32_t PTEN11 : 1; + __IOM uint32_t PTEN12 : 1; + __IOM uint32_t PTEN13 : 1; + __IOM uint32_t PTEN14 : 1; + __IOM uint32_t PTEN15 : 1; + __IOM uint32_t PTEN16 : 1; + __IOM uint32_t PTEN17 : 1; + __IOM uint32_t PTEN18 : 1; + __IM uint32_t RESERVED : 12; + } RTEN_B; + }; + + /** Falling Trigger Event Enable register */ + union + { + __IOM uint32_t FTEN; + + struct + { + __IOM uint32_t FTEN0 : 1; + __IOM uint32_t FTEN1 : 1; + __IOM uint32_t FTEN2 : 1; + __IOM uint32_t FTEN3 : 1; + __IOM uint32_t FTEN4 : 1; + __IOM uint32_t FTEN5 : 1; + __IOM uint32_t FTEN6 : 1; + __IOM uint32_t FTEN7 : 1; + __IOM uint32_t FTEN8 : 1; + __IOM uint32_t FTEN9 : 1; + __IOM uint32_t FTEN10 : 1; + __IOM uint32_t FTEN11 : 1; + __IOM uint32_t FTEN12 : 1; + __IOM uint32_t FTEN13 : 1; + __IOM uint32_t FTEN14 : 1; + __IOM uint32_t FTEN15 : 1; + __IOM uint32_t FTEN16 : 1; + __IOM uint32_t FTEN17 : 1; + __IOM uint32_t FTEN18 : 1; + __IM uint32_t RESERVED : 12; + } FTEN_B; + }; + + /** Software Interrupt Enable register */ + union + { + __IOM uint32_t SWINTE; + + struct + { + __IOM uint32_t SWINTE0 : 1; + __IOM uint32_t SWINTE1 : 1; + __IOM uint32_t SWINTE2 : 1; + __IOM uint32_t SWINTE3 : 1; + __IOM uint32_t SWINTE4 : 1; + __IOM uint32_t SWINTE5 : 1; + __IOM uint32_t SWINTE6 : 1; + __IOM uint32_t SWINTE7 : 1; + __IOM uint32_t SWINTE8 : 1; + __IOM uint32_t SWINTE9 : 1; + __IOM uint32_t SWINTE10 : 1; + __IOM uint32_t SWINTE11 : 1; + __IOM uint32_t SWINTE12 : 1; + __IOM uint32_t SWINTE13 : 1; + __IOM uint32_t SWINTE14 : 1; + __IOM uint32_t SWINTE15 : 1; + __IOM uint32_t SWINTE16 : 1; + __IOM uint32_t SWINTE17 : 1; + __IOM uint32_t SWINTE18 : 1; + __IM uint32_t RESERVED : 12; + } SWINTE_B; + }; + + /** Interrupt Flag Enable register */ + union + { + __IOM uint32_t IPEND; + + struct + { + __IOM uint32_t IPEND0 : 1; + __IOM uint32_t IPEND1 : 1; + __IOM uint32_t IPEND2 : 1; + __IOM uint32_t IPEND3 : 1; + __IOM uint32_t IPEND4 : 1; + __IOM uint32_t IPEND5 : 1; + __IOM uint32_t IPEND6 : 1; + __IOM uint32_t IPEND7 : 1; + __IOM uint32_t IPEND8 : 1; + __IOM uint32_t IPEND9 : 1; + __IOM uint32_t IPEND10 : 1; + __IOM uint32_t IPEND11 : 1; + __IOM uint32_t IPEND12 : 1; + __IOM uint32_t IPEND13 : 1; + __IOM uint32_t IPEND14 : 1; + __IOM uint32_t IPEND15 : 1; + __IOM uint32_t IPEND16 : 1; + __IOM uint32_t IPEND17 : 1; + __IOM uint32_t IPEND18 : 1; + __IM uint32_t RESERVED : 12; + } IF_B; + }; +}EINT_T; + +/** + * @brief Independent watchdog(IWDT) + */ +typedef struct +{ + + /** Keyword register */ + union + { + __OM uint32_t KEY; + + struct + { + __OM uint32_t KEY : 16; + __IM uint32_t RESERVED : 16; + } KEY_B; + }; + + /** Frequency Divider register */ + union + { + __IOM uint32_t PSC; + + struct + { + __IOM uint32_t PSC : 3; + __IM uint32_t RESERVED : 29; + } DIV_B; + }; + + /** Reload values register */ + union + { + __IOM uint32_t CNTRLD; + + struct + { + __IOM uint32_t CNTRLD : 12; + __IM uint32_t RESERVED : 20; + } CNTRLD_B; + }; + + /** Status register */ + union + { + __IM uint32_t STS; + + struct + { + __IM uint32_t PSCUFLG : 1; + __IM uint32_t CNTUFLG : 1; + __IM uint32_t RESERVED : 30; + } STS_B; + }; +}IWDT_T; + +/** + * @brief Serial peripheral interface(SPI) + */ +typedef struct +{ + /** Control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t MSMCFG : 1; + __IOM uint32_t BRSEL : 3; + __IOM uint32_t SPIEN : 1; + __IOM uint32_t LSBSEL : 1; + __IOM uint32_t ISSEL : 1; + __IOM uint32_t SSEN : 1; + __IOM uint32_t RXOMEN : 1; + __IOM uint32_t DFLSEL : 1; + __IOM uint32_t CECNXT : 1; + __IOM uint32_t CRCEN : 1; + __IOM uint32_t BMOEN : 1; + __IOM uint32_t BMEN : 1; + __IM uint32_t RESERVED : 16; + } CTRL1_B; + }; + + /** Control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t RXDEN : 1; + __IOM uint32_t TXDEN : 1; + __IOM uint32_t SSOEN : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t RXBNEIEN : 1; + __IOM uint32_t TXBEIEN : 1; + __IM uint32_t RESERVED2 : 24; + } CTRL2_B; + }; + + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t RXBNEFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IM uint32_t SCHDIR : 1; + __IM uint32_t UDRFLG : 1; + __IOM uint32_t CRCEFLG : 1; + __IM uint32_t MEFLG : 1; + __IM uint32_t OVRFLG : 1; + __IM uint32_t BSYFLG : 1; + __IM uint32_t RESERVED : 24; + } STS_B; + }; + + /** Data register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA_B; + }; + + /** CRC polynomial register */ + union + { + __IOM uint32_t CRCPOLY; + + struct + { + __IOM uint32_t CRCPOLY : 16; + __IM uint32_t RESERVED : 16; + } CRCPOLY_B; + }; + + /** Receive CRC register */ + union + { + __IM uint32_t RXCRC; + + struct + { + __IM uint32_t RXCRC : 16; + __IM uint32_t RESERVED : 16; + }RXCRC_B; + }; + + /** Transmit CRC register */ + union + { + __IM uint32_t TXCRC; + + struct + { + __IM uint32_t TXCRC : 16; + __IM uint32_t RESERVED : 16; + }TXCRC_B; + }; + + /** Transmit I2S CTRL register */ + union + { + __IOM uint32_t I2SCFG; + + struct + { + __IOM uint32_t CHLEN : 1; + __IOM uint32_t DATLEN : 2; + __IOM uint32_t CPOL : 1; + __IOM uint32_t I2SSSEL : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PFSSEL : 1; + __IOM uint32_t I2SMOD : 2; + __IOM uint32_t I2SEN : 1; + __IOM uint32_t MODESEL : 1; + __IM uint32_t RESERVED2 : 20; + }I2SCFG_B; + }; + + /** Transmit I2S DIV register */ + union + { + __IOM uint32_t I2SPSC; + + struct + { + __IOM uint32_t I2SPSC : 8; + __IOM uint32_t ODDPSC : 1; + __IOM uint32_t MCIEN : 1; + __IM uint32_t RESERVED1 : 22; + }I2SPSC_B; + }; +}SPI_T; + +/** + * @brief Window watchdog (WWDT) + */ +typedef struct +{ + + /** Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t CNT : 7; + __IOM uint32_t WWDTEN : 1; + __IM uint32_t RESERVED : 24; + } CTRL_B; + }; + + /** Configure register */ + union + { + __IOM uint32_t CFG; + + struct + { + __IOM uint32_t WIN : 7; + __IOM uint32_t TBPSC : 2; + __IOM uint32_t EWIEN : 1; + __IM uint32_t RESERVED : 22; + } CFG_B; + }; + + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t EWIFLG : 1; + __IM uint32_t RESERVED : 31; + } STS_B; + }; +}WWDT_T; + +/** + * @brief Secure digital input/output interface (SDIO) + */ +typedef struct +{ + /** Power control register */ + union + { + __IOM uint32_t PWRCTRL; + + struct + { + __IOM uint32_t PWRCTRL : 2; + __IM uint32_t RESERVED : 30; + } PWRCTRL_B; + }; + + /** Clock control register */ + union + { + __IOM uint32_t CLKCTRL; + + struct + { + __IOM uint32_t CLKDIV : 8; + __IOM uint32_t CLKEN : 1; + __IOM uint32_t PWRSAV : 1; + __IOM uint32_t BYPASSEN : 1; + __IOM uint32_t WBSEL : 2; + __IOM uint32_t DEPSEL : 1; + __IOM uint32_t HFCEN : 1; + __IM uint32_t RESERVED : 17; + } CLKCTRL_B; + }; + + /** Argument register */ + union + { + __IOM uint32_t ARG; + + struct + { + __IOM uint32_t CMDARG : 32; + } ARG_B; + }; + + /** Command register */ + union + { + __IOM uint32_t CMD; + + struct + { + __IOM uint32_t CMDINDEX : 6; + __IOM uint32_t WAITRES : 2; + __IOM uint32_t WAITINT : 1; + __IOM uint32_t WENDDATA : 1; + __IOM uint32_t CPSMEN : 1; + __IOM uint32_t SDIOSC : 1; + __IOM uint32_t CMDCPEN : 1; + __IOM uint32_t INTEN : 1; + __IOM uint32_t ATACMD : 1; + __IM uint32_t RESERVED : 17; + } CMD_B; + }; + + /** Command response register */ + union + { + __IM uint32_t CMDRES; + + struct + { + __IM uint32_t CMDRES : 6; + __IM uint32_t RESERVED : 26; + } CMDRES_B; + }; + + /** SDIO response register1 */ + union + { + __IM uint32_t RES1; + + struct + { + __IM uint32_t CARDSTS1 : 32; + } RES1_B; + }; + + /** SDIO response register2 */ + union + { + __IM uint32_t RES2; + + struct + { + __IM uint32_t CARDSTS2 : 32; + } RES2_B; + }; + + /** SDIO response register3 */ + union + { + __IM uint32_t RES3; + + struct + { + __IM uint32_t CARDSTS3 : 32; + } RES3_B; + }; + + /** SDIO response register4 */ + union + { + __IM uint32_t RES4; + + struct + { + __IM uint32_t CARDSTS4 : 32; + } RES4_B; + }; + + /** Data timer register */ + union + { + __IOM uint32_t DATATIME; + + struct + { + __IOM uint32_t DATATIME : 32; + } DTMR_B; + }; + + /** Data length register */ + union + { + __IOM uint32_t DATALEN; + + struct + { + __IOM uint32_t DATALEN : 25; + __IM uint32_t RESERVED : 7; + } DLEN_B; + }; + + /** Data control register */ + union + { + __IOM uint32_t DCTRL; + + struct + { + __IOM uint32_t DTEN : 1; + __IOM uint32_t DTDRCFG : 1; + __IOM uint32_t DTSEL : 1; + __IOM uint32_t DMAEN : 1; + __IOM uint32_t DBSIZE : 4; + __IOM uint32_t RWSTR : 1; + __IOM uint32_t PWSTOP : 1; + __IOM uint32_t RDWAIT : 1; + __IOM uint32_t SDIOF : 1; + __IM uint32_t RESERVED : 20; + } DCTRL_B; + }; + + /** Data count register */ + union + { + __IM uint32_t DCNT; + + struct + { + __IM uint32_t DATACNT : 25; + __IM uint32_t RESERVED : 7; + } DCNT_B; + }; + + /** SDIO status register */ + union + { + __IM uint32_t STS; + + struct + { + __IM uint32_t COMRESP : 1; + __IM uint32_t DBDR : 1; + __IM uint32_t CMDRESTO : 1; + __IM uint32_t DATATO : 1; + __IM uint32_t TXUDRER : 1; + __IM uint32_t RXOVRER : 1; + __IM uint32_t CMDRES : 1; + __IM uint32_t CMDSENT : 1; + __IM uint32_t DATAEND : 1; + __IM uint32_t SBE : 1; + __IM uint32_t DBCP : 1; + __IM uint32_t CMDACT : 1; + __IM uint32_t TXACT : 1; + __IM uint32_t RXACT : 1; + __IM uint32_t TXFHF : 1; + __IM uint32_t RXFHF : 1; + __IM uint32_t TXFF : 1; + __IM uint32_t RXFF : 1; + __IM uint32_t TXFE : 1; + __IM uint32_t RXFE : 1; + __IM uint32_t TXDA : 1; + __IM uint32_t RXDA : 1; + __IM uint32_t SDIOINT : 1; + __IM uint32_t ATAEND : 1; + __IM uint32_t RESERVED : 8; + } STS_B; + }; + + /** SDIO interrupt clear register */ + union + { + __IOM uint32_t ICF; + + struct + { + __IOM uint32_t DBCE : 1; + __IOM uint32_t CRCE : 1; + __IOM uint32_t CRTO : 1; + __IOM uint32_t DTO : 1; + __IOM uint32_t TXFUE : 1; + __IOM uint32_t RXFOE : 1; + __IOM uint32_t CMDRES : 1; + __IOM uint32_t CMDSENT : 1; + __IOM uint32_t DATAEND : 1; + __IOM uint32_t SBE : 1; + __IOM uint32_t DBCP : 1; + __IM uint32_t RESERVED1 : 11; + __IOM uint32_t SDIOIT : 1; + __IOM uint32_t ATAEND : 1; + __IM uint32_t RESERVED2 : 8; + } ICF_B; + }; + + /** SDIO interrupt mask register */ + union + { + __IOM uint32_t MASK; + + struct + { + __IOM uint32_t CCRCFAIL : 1; + __IOM uint32_t DCRCFAIL : 1; + __IOM uint32_t CMDTO : 1; + __IOM uint32_t DATATO : 1; + __IOM uint32_t TXURER : 1; + __IOM uint32_t RXORER : 1; + __IOM uint32_t CMDRESRC : 1; + __IOM uint32_t CMDSENT : 1; + __IOM uint32_t DATAEND : 1; + __IOM uint32_t STRTER : 1; + __IOM uint32_t DBEND : 1; + __IOM uint32_t CMDACT : 1; + __IOM uint32_t TXACT : 1; + __IOM uint32_t RXACT : 1; + __IOM uint32_t TXHFERT : 1; + __IOM uint32_t RXHFFUL : 1; + __IOM uint32_t TXFUL : 1; + __IOM uint32_t RXFUL : 1; + __IOM uint32_t TXEPT : 1; + __IOM uint32_t RXFEIE : 1; + __IOM uint32_t TXDAVB : 1; + __IOM uint32_t RXDAVB : 1; + __IOM uint32_t SDIOINTREC : 1; + __IOM uint32_t ATACLPREC : 1; + __IM uint32_t RESERVEDIE : 8; + } MASK_B; + }; + + __IM uint32_t RESERVED[2]; + + /** SDIO FIFO count register */ + union + { + __IM uint32_t FIFOCNT; + + struct + { + __IM uint32_t FIFOCNT : 24; + __IM uint32_t RESERVED : 8; + } FIFOCNT_B; + }; + + __IM uint32_t RESERVED1[13]; + + /** SDIO data FIFO register */ + union + { + __IOM uint32_t FIFODATA; + + struct + { + __IOM uint32_t FIFODATA : 32; + } FIFODATA_B; + }; +}SDIO_T; + +/** + * @brief Digital to Analog Converter(DAC) + */ +typedef struct +{ + /** Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t ENCH1 : 1; + __IOM uint32_t BUFFDCH1 : 1; + __IOM uint32_t TRGENCH1 : 1; + __IOM uint32_t TRGSELCH1 : 3; + __IOM uint32_t WAVENCH1 : 2; + __IOM uint32_t MAMPSELCH1 : 4; + __IOM uint32_t DMAENCH1 : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ENCH2 : 1; + __IOM uint32_t BUFFDCH2 : 1; + __IOM uint32_t TRGENCH2 : 1; + __IOM uint32_t TRGSELCH2 : 3; + __IOM uint32_t WAVENCH2 : 2; + __IOM uint32_t MAMPSELCH2 : 4; + __IOM uint32_t DMAENCH2 : 1; + __IM uint32_t RESERVED2 : 3; + } CTRL_B; + }; + + /** Software trigger register */ + union + { + __IOM uint32_t SWTRG; + + struct + { + __IOM uint32_t SWTRG1 : 1; + __IOM uint32_t SWTRG2 : 1; + __IM uint32_t RESERVED : 30; + } SWTRG_B; + }; + + /** Channel1 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12R1; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DH12R1_B; + }; + + /** Channel1 12-bit left-aligned register */ + union + { + __IOM uint32_t DH12L1; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED2 : 16; + } DH12L1_B; + }; + + /** Channel1 8-bit right-aligned register */ + union + { + __IOM uint32_t DH8R1; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED : 24; + } DH8R1_B; + }; + + /** Channel2 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12R2; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DH12R2_B; + }; + + /** Channel2 12-bit left-aligned register */ + union + { + __IOM uint32_t DH12L2; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED2 : 16; + }DH12L2_B; + }; + + /** Channel2 8-bit right-aligned register */ + union + { + __IOM uint32_t DH8R2; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED : 24; + } DH8R2_B; + }; + + /** Channel1,Channel2 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12RDUAL; + + struct + { + __IOM uint32_t DATACH1 : 12; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATACH2 : 12; + __IM uint32_t RESERVED2 : 4; + } DH12RDUAL_B; + }; + + /** Channel1,Channel2 12-bit left-aligned register */ + union + { + __IOM uint32_t DH12LDUAL; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATACH1 : 12; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t DATACH2 : 12; + } DH12LDUAL_B; + }; + + /** Channel1,Channel2 8-bit right-aligned register */ + union + { + __IOM uint32_t DH8RDUAL; + + struct + { + __IOM uint32_t CH1DH : 8; + __IOM uint32_t CH2DH : 8; + __IM uint32_t RESERVED : 16; + } DH8RDUAL_B; + }; + + /** Channel1 data output register */ + union + { + __IOM uint32_t DATAOCH1; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DATAOCH1_B; + }; + + /** Channel2 data output register */ + union + { + __IOM uint32_t DATAOCH2; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DATAOCH2_B; + }; +}DAC_T; + +/** + * @brief EMMC Register + */ +typedef struct +{ + /** SRAM/NOR-Flash chip-select control register */ + union + { + __IOM uint32_t CSCTRL; + + struct + { + __IOM uint32_t MBKEN : 1; + __IOM uint32_t ADMUXEN : 1; + __IOM uint32_t MTYPECFG : 2; + __IOM uint32_t MDBWIDCFG : 2; + __IOM uint32_t NORFMACCEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t BURSTEN : 1; + __IOM uint32_t WSPOLCFG : 1; + __IOM uint32_t WRAPBEN : 1; + __IOM uint32_t WTIMCFG : 1; + __IOM uint32_t WREN : 1; + __IOM uint32_t WAITEN : 1; + __IOM uint32_t EXTMODEEN : 1; + __IOM uint32_t WSASYNCEN : 1; + __IOM uint32_t CRAMPSIZECFG : 3; + __IOM uint32_t WRBURSTEN : 1; + __IOM uint32_t RESERVED2 : 12; + }CSCTRL_B; + }; +}SNCTRL_T; + +typedef struct +{ + /** SRAM/NOR-Flash write timing registers */ + union + { + __IOM uint32_t WRTTIM; + + struct + { + __IOM uint32_t ADDRSETCFG : 4; + __IOM uint32_t ADDRHLDCFG : 4; + __IOM uint32_t DATASETCFG : 8; + __IOM uint32_t BUSTURNCFG : 4; + __IOM uint32_t CLKDIVCFG : 4; + __IOM uint32_t DATALATCFG : 4; + __IOM uint32_t ACCMODECFG : 2; + __IM uint32_t RESERVED2 : 2; + }WRTTIM_T; + }; +}SNWCLK_T; + +/** + * @brief Flexible Static Memory Controller + */ +typedef struct +{ + __IO uint32_t SNCTRL_T[8]; +} EMMC_Bank1_T; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t WRTTIM[7]; +} EMMC_Bank1E_T; + +/** + * @brief Flexible Static Memory Controller Bank 2 + */ +typedef struct +{ + /** PC Card/NAND Flash control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t WAITFEN : 1; + __IOM uint32_t MBKEN : 1; + __IOM uint32_t MTYPECFG : 1; + __IOM uint32_t DBWIDCFG : 2; + __IOM uint32_t ECCEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t C2RDCFG : 4; + __IOM uint32_t A2RDCFG : 4; + __IOM uint32_t ECCPSCFG : 3; + __IM uint32_t RESERVED3 : 12; + }CTRL2_B; + }; + + /** FIFO status and interrupt register 2 */ + union + { + __IOM uint32_t STSINT2; + + struct + { + __IOM uint32_t IREFLG : 1; + __IOM uint32_t IHLFLG : 1; + __IOM uint32_t IFEFLG : 1; + __IOM uint32_t IREDEN : 1; + __IOM uint32_t IHLDEN : 1; + __IOM uint32_t IFEDEN : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t RESERVED :25; + }STSINT2_B; + }; + /** Common memory space timing register 2 */ + union + { + __IOM uint32_t CMSTIM2; + + struct + { + __IOM uint32_t SET2 : 8; + __IOM uint32_t WAIT2 : 8; + __IOM uint32_t HLD2 : 8; + __IOM uint32_t HIZ2 : 8; + }CMSTIM2_B; + }; + + /** Attribute memory space timing register 2 */ + union + { + __IOM uint32_t AMSTIM2; + + struct + { + __IOM uint32_t SET2 : 8; + __IOM uint32_t WAIT2 : 8; + __IOM uint32_t HLD2 : 8; + __IOM uint32_t HIZ2 : 8; + }AMSTIM2_B; + }; + + __IOM uint32_t RESERVED; + + /** ECC result register 2 */ + union + { + __IM uint32_t ECCRS2; + + struct + { + __IM uint32_t ECCRS2 : 32; + } ECCRS2_B; + }; +}EMMC_Bank2_T; + +/** + * @brief Flexible Static Memory Controller Bank 3 + */ +typedef struct +{ + /** PC Card/NAND Flash control register 3 */ + union + { + __IOM uint32_t CTRL3; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t WAITFEN : 1; + __IOM uint32_t MBKEN : 1; + __IOM uint32_t MTYPECFG : 1; + __IOM uint32_t DBWIDCFG : 2; + __IOM uint32_t ECCEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t C2RDCFG : 4; + __IOM uint32_t A2RDCFG : 4; + __IOM uint32_t ECCPSCFG : 3; + __IM uint32_t RESERVED3 : 12; + }CTRL3_B; + }; + + /** FIFO status and interrupt register 3 */ + union + { + __IOM uint32_t STSINT3; + + struct + { + __IOM uint32_t IREFLG : 1; + __IOM uint32_t IHLFLG : 1; + __IOM uint32_t IFEFLG : 1; + __IOM uint32_t IREDEN : 1; + __IOM uint32_t IHLDEN : 1; + __IOM uint32_t IFEDEN : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t RESERVED :16; + }STSINT3_B; + }; + + /** Common memory space timing register 3 */ + union + { + __IOM uint32_t CMSTIM3; + + struct + { + __IOM uint32_t SET3 : 8; + __IOM uint32_t WAIT3 : 8; + __IOM uint32_t HLD3 : 8; + __IOM uint32_t HIZ3 : 8; + }CMSTIM3_B; + }; + + /** Attribute memory space timing register 3 */ + union + { + __IOM uint32_t AMSTIM3; + + struct + { + __IOM uint32_t SET3 : 8; + __IOM uint32_t WAIT3 : 8; + __IOM uint32_t HLD3 : 8; + __IOM uint32_t HIZ3 : 8; + }AMSTIM3_B; + }; + + __IOM uint32_t RESERVED; + + /** ECC result register 3 */ + union + { + __IM uint32_t ECCRS3; + + struct + { + __IM uint32_t ECCRS3 : 32; + } ECCRS3_B; + }; +}EMMC_Bank3_T; + +/** + * @brief Flexible Static Memory Controller Bank 4 + */ +typedef struct +{ + /** PC Card/NAND Flash control register 4 */ + union + { + __IOM uint32_t CTRL4; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t WAITFEN : 1; + __IOM uint32_t MBKEN : 1; + __IOM uint32_t MTYPECFG : 1; + __IOM uint32_t DBWIDCFG : 2; + __IOM uint32_t ECCEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t C2RDCFG : 4; + __IOM uint32_t A2RDCFG : 4; + __IOM uint32_t ECCPSCFG : 3; + __IM uint32_t RESERVED3 : 12; + }CTRL4_B; + }; + + /** FIFO status and interrupt register 4 */ + union + { + __IOM uint32_t STSINT4; + + struct + { + __IOM uint32_t IREFLG : 1; + __IOM uint32_t IHLFLG : 1; + __IOM uint32_t IFEFLG : 1; + __IOM uint32_t IREDEN : 1; + __IOM uint32_t IHLDEN : 1; + __IOM uint32_t IFEDEN : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t RESERVED :16; + }STSINT4_B; + }; + + /** Common memory space timing register 4 */ + union + { + __IOM uint32_t CMSTIM4; + + struct + { + __IOM uint32_t SET4 : 8; + __IOM uint32_t WAIT4 : 8; + __IOM uint32_t HLD4 : 8; + __IOM uint32_t HIZ4 : 8; + }CMSTIM4_B; + }; + + /** Attribute memory space timing register 4 */ + union + { + __IOM uint32_t AMSTIM4; + + struct + { + __IOM uint32_t SET4 : 8; + __IOM uint32_t WAIT4 : 8; + __IOM uint32_t HLD4 : 8; + __IOM uint32_t HIZ4 : 8; + }AMSTIM4_B; + }; + + /** I/O space timing register 4 */ + union + { + __IOM uint32_t IOSTIM4; + + struct + { + __IOM uint32_t SET4 : 8; + __IOM uint32_t WAIT4 : 8; + __IOM uint32_t HLD4 : 8; + __IOM uint32_t HIZ4 : 8; + }IOSTIM4_B; + }; +}EMMC_Bank4_T; + +/** + * @brief Queued serial peripheral interface(QSPI) + */ +typedef struct +{ + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + struct + { + __IOM uint32_t DFS : 5; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t TXMODE : 2; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t SSTEN : 1; + __IM uint32_t RESERVED3 : 7; + __IOM uint32_t FRF : 2; + __IM uint32_t RESERVED4 : 8; + }CTRL1_B; + }; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + struct + { + __IOM uint32_t NDF : 16; + __IM uint32_t RESERVED : 16; + }CTRL2_B; + }; + + /** @brief QSPI Enable register */ + union + { + __IOM uint32_t SSIEN; + struct + { + __IOM uint32_t EN : 1; + __IM uint32_t RESERVED : 31; + }SSIEN_B; + }; + + __IM uint32_t RESERVED; + + /** @brief QSPI Slave enable register */ + union + { + __IOM uint32_t SLAEN; + struct + { + __IOM uint32_t SLAEN : 1; + __IM uint32_t RESERVED : 31; + }SLAEN_B; + }; + + /** @brief Baudrate register */ + union + { + __IOM uint32_t BR; + struct + { + __IOM uint32_t CLKDIV : 16; + __IM uint32_t RESERVED : 16; + }BR_B; + }; + + /** @brief Transmission FIFO threshhold level register */ + union + { + __IOM uint32_t TFTL; + struct + { + __IOM uint32_t TFT : 3; + __IM uint32_t RESERVED1 : 13; + __IOM uint32_t TFTH : 3; + __IM uint32_t RESERVED2 : 13; + }TFTL_B; + }; + + /** @brief Reception FIFO threshhold level register */ + union + { + __IOM uint32_t RFTL; + struct + { + __IOM uint32_t RFT : 3; + __IM uint32_t RESERVED : 29; + }RFTL_B; + }; + + /** @brief Transmission FIFO level register */ + union + { + __IOM uint32_t TFL; + struct + { + __IOM uint32_t TFL : 3; + __IM uint32_t RESERVED : 29; + }TFL_B; + }; + + /** @brief Reception FIFO level register */ + union + { + __IOM uint32_t RFL; + struct + { + __IOM uint32_t RFL : 3; + __IM uint32_t RESERVED : 29; + }RFL_B; + }; + + /** @brief Status register */ + union + { + __IOM uint32_t STS; + struct + { + __IOM uint32_t BUSYF : 1; + __IOM uint32_t TFNF : 1; + __IOM uint32_t TFEF : 1; + __IOM uint32_t RFNEF : 1; + __IOM uint32_t RFFF : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t DCEF : 1; + __IM uint32_t RESERVED2 : 25; + }STS_B; + }; + + /** @brief Interrupt enable register */ + union + { + __IOM uint32_t INTEN; + struct + { + __IOM uint32_t TFEIE : 1; + __IOM uint32_t TFOIE : 1; + __IOM uint32_t RFUIE : 1; + __IOM uint32_t RFOIE : 1; + __IOM uint32_t RFFIE : 1; + __IOM uint32_t MSTIE : 1; + __IM uint32_t RESERVED : 26; + }INTEN_B; + }; + + /** @brief Interrupt status register */ + union + { + __IM uint32_t ISTS; + struct + { + __IM uint32_t TFEIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t RFUIF : 1; + __IM uint32_t RFOIF : 1; + __IM uint32_t RFFIF : 1; + __IM uint32_t MSTIF : 1; + __IM uint32_t RESERVED : 26; + }ISTS_B; + }; + + /** @brief Raw interrupt register */ + union + { + __IM uint32_t RIS; + struct + { + __IM uint32_t TFEIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t RFUIF : 1; + __IM uint32_t RXOIR : 1; + __IM uint32_t RXFIR : 1; + __IM uint32_t MSTIR : 1; + __IM uint32_t RESERVED : 26; + }RIS_B; + }; + + /** @brief Transmission FIFO overflow interrupt clear register */ + union + { + __IM uint32_t TFOIC; + struct + { + __IM uint32_t TFOIC : 1; + __IM uint32_t RESERVED : 31; + }TFOIC_B; + }; + + /** @brief Reception FIFO overflow interrupt clear register */ + union + { + __IM uint32_t RFOIC; + struct + { + __IM uint32_t RFOIC : 1; + __IM uint32_t RESERVED : 31; + }RFOIC_B; + }; + + /** @brief Reception FIFO underflow interrupt clear register */ + union + { + __IM uint32_t RFUIC; + struct + { + __IM uint32_t RFUIC : 1; + __IM uint32_t RESERVED : 31; + }RFUIC_B; + }; + + /** @brief Master interrupt clear register */ + union + { + __IM uint32_t MIC; + struct + { + __IM uint32_t MIC : 1; + __IM uint32_t RESERVED : 31; + }MIC_B; + }; + + /** @brief Interrupt clear register */ + union + { + __IM uint32_t ICF; + struct + { + __IM uint32_t ICF : 1; + __IM uint32_t RESERVED : 31; + }ICF_B; + }; + + __IM uint32_t RESERVED1[5]; + + /** @brief Data register */ + union + { + __IOM uint32_t DATA; + struct + { + __IOM uint32_t DATA : 32; + }DATA_B; + }; + + __IM uint32_t RESERVED2[35]; + + /** @brief Reception sample register */ + union + { + __IOM uint32_t RSD; + struct + { + __IOM uint32_t RSD : 8; + __IM uint32_t RESERVED1 : 8; + __IOM uint32_t RSE : 1; + __IM uint32_t RESERVED2 : 15; + }RSD_B; + }; + + /** @brief Reception sample register */ + union + { + __IOM uint32_t CTRL3; + struct + { + __IOM uint32_t IAT : 2; + __IOM uint32_t ADDRLEN : 4; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t INSLEN : 2; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t WAITCYC : 5; + __IM uint32_t RESERVED3 : 14; + __IOM uint32_t CSEN : 1; + __IM uint32_t RESERVED4 : 1; + }CTRL3_B; + }; + + __IM uint32_t RESERVED3[66]; + + /** @brief IO switch register */ + union + { + __IOM uint32_t IOSW; + struct + { + __IOM uint32_t IOSW : 1; + __IM uint32_t RESERVED : 31; + }IOSW_B; + }; +}QSPI_T; + +/** + * @brief SEC Inter-integrated circuit (SCI2C) + */ +typedef struct +{ + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + struct + { + __IOM uint32_t MST : 1; + __IOM uint32_t SPD : 2; + __IOM uint32_t SAM : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t RSTAEN : 1; + __IOM uint32_t SLADIS : 1; + __IOM uint32_t DSA : 1; + __IOM uint32_t TFEIC : 1; + __IOM uint32_t RFFIE : 1; + __IOM uint32_t DSMA : 1; + __IM uint32_t RESERVED2 : 21; + }CTRL1_B; + }; + + /** @brief Master address register */ + union + { + __IOM uint32_t TARADDR; + struct + { + __IOM uint32_t ADDR : 10; + __IOM uint32_t STA : 1; + __IOM uint32_t GCEN : 1; + __IOM uint32_t MAM : 1; + __IM uint32_t RESERVED : 19; + }TARADDR_B; + }; + + /** @brief Slave address register */ + union + { + __IOM uint32_t SLAADDR; + struct + { + __IOM uint32_t ADDR : 10; + __IM uint32_t RESERVED : 22; + }SLAADDR_B; + }; + + /** @brief High speed master code register */ + union + { + __IOM uint32_t HSMC; + struct + { + __IOM uint32_t HSMC : 4; + __IM uint32_t RESERVED : 28; + }HSMC_B; + }; + + /** @brief Data register */ + union + { + __IOM uint32_t DATA; + struct + { + __IOM uint32_t DATA : 8; + __IOM uint32_t CMD : 1; + __IOM uint32_t STOP : 1; + __IM uint32_t RESERVED : 22; + }DATA_B; + }; + + /** @brief Standard speed clock high counter register */ + union + { + __IOM uint32_t SSCHC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }SSCHC_B; + }; + + /** @brief Standard speed clock low counter register */ + union + { + __IOM uint32_t SSCLC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }SSCLC_B; + }; + + /** @brief Fast speed clock high counter register */ + union + { + __IOM uint32_t FSCHC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }FSCHC_B; + }; + + /** @brief Fast speed clock low counter register */ + union + { + __IOM uint32_t FSCLC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }FSCLC_B; + }; + + /** @brief High speed clock high counter */ + union + { + __IOM uint32_t HSCHC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }HSCHC_B; + }; + + /** @brief High speed clock low counter register */ + union + { + __IOM uint32_t HSCLC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }HSCLC_B; + }; + + /** @brief Interrupt status register */ + union + { + __IM uint32_t INTSTS; + struct + { + __IM uint32_t RFUIF : 1; + __IM uint32_t RFOIF : 1; + __IM uint32_t RFFIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t TFEIF : 1; + __IM uint32_t RRIF : 1; + __IM uint32_t TAIF : 1; + __IM uint32_t RDIF : 1; + __IM uint32_t ACTIF : 1; + __IM uint32_t STPDIF : 1; + __IM uint32_t STADIF : 1; + __IM uint32_t GCIF : 1; + __IM uint32_t RSTADIF : 1; + __IM uint32_t MOHIF : 1; + __IM uint32_t RESERVED : 18; + }INTSTS_B; + }; + + /** @brief Interrupt enable register */ + union + { + __IOM uint32_t INTEN; + struct + { + __IOM uint32_t RFUIE : 1; + __IOM uint32_t RFOIE : 1; + __IOM uint32_t RFFIE : 1; + __IOM uint32_t TFOIE : 1; + __IOM uint32_t TFEIE : 1; + __IOM uint32_t RRIE : 1; + __IOM uint32_t TAIE : 1; + __IOM uint32_t RDIE : 1; + __IOM uint32_t ACTIE : 1; + __IOM uint32_t STPDIE : 1; + __IOM uint32_t STADIE : 1; + __IOM uint32_t GCIE : 1; + __IOM uint32_t RSTADIE : 1; + __IOM uint32_t MOHIE : 1; + __IM uint32_t RESERVED : 18; + }INTEN_B; + }; + + /** @brief Raw interrupt status register */ + union + { + __IM uint32_t RIS; + struct + { + __IM uint32_t RFUIF : 1; + __IM uint32_t RFOIF : 1; + __IM uint32_t RFFIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t TFEIF : 1; + __IM uint32_t RRIF : 1; + __IM uint32_t TAIF : 1; + __IM uint32_t RDIF : 1; + __IM uint32_t ACTIF : 1; + __IM uint32_t STPDIF : 1; + __IM uint32_t STADIF : 1; + __IM uint32_t GCIF : 1; + __IM uint32_t RSTADIF : 1; + __IM uint32_t RESERVED : 18; + }RIS_B; + }; + + /** @brief Reception FIFO threshold register */ + union + { + __IOM uint32_t RFT; + struct + { + __IOM uint32_t RFT : 8; + __IM uint32_t RESERVED : 24; + }RFT_B; + }; + + /** @brief Transmission FIFO threshold register */ + union + { + __IOM uint32_t TFT; + struct + { + __IOM uint32_t TFT : 8; + __IM uint32_t RESERVED : 24; + }TFT_B; + }; + + /** @brief Interruption clear register */ + union + { + __IM uint32_t INTCLR; + struct + { + __IM uint32_t INTCLR : 1; + __IM uint32_t RESERVED : 31; + }INTCLR_B; + }; + + /** @brief Reception FIFO underflow interruption clear register */ + union + { + __IM uint32_t RFUIC; + struct + { + __IM uint32_t RFUIC : 1; + __IM uint32_t RESERVED : 31; + }RFUIC_B; + }; + + /** @brief Reception FIFO overflow interruption clear register */ + union + { + __IM uint32_t RFOIC; + struct + { + __IM uint32_t RFOIC : 1; + __IM uint32_t RESERVED : 31; + }RFOIC_B; + }; + + /** @brief Transmission FIFO overflow interruption clear register */ + union + { + __IM uint32_t TFOIC; + struct + { + __IM uint32_t TFOIC : 1; + __IM uint32_t RESERVED : 31; + }TFOIC_B; + }; + + /** @brief Reception request interruption clear register */ + union + { + __IM uint32_t RRIC; + struct + { + __IM uint32_t RRIC : 1; + __IM uint32_t RESERVED : 31; + }RRIC_B; + }; + + /** @brief Transmission abort interruption clear register */ + union + { + __IM uint32_t TAIC; + struct + { + __IM uint32_t TAIC : 1; + __IM uint32_t RESERVED : 31; + }TAIC_B; + }; + + /** @brief Receive done interruption clear register */ + union + { + __IM uint32_t RDIC; + struct + { + __IM uint32_t RDIC : 1; + __IM uint32_t RESERVED : 31; + }RDIC_B; + }; + + /** @brief Activity interruption clear register */ + union + { + __IM uint32_t AIC; + struct + { + __IM uint32_t AIC : 1; + __IM uint32_t RESERVED : 31; + }AIC_B; + }; + + /** @brief Stop detection interruption clear register */ + union + { + __IM uint32_t STPDIC; + struct + { + __IM uint32_t STPDIC : 1; + __IM uint32_t RESERVED : 31; + }STPDIC_B; + }; + + /** @brief Start detection interruption clear register */ + union + { + __IM uint32_t STADIC; + struct + { + __IM uint32_t STADIC : 1; + __IM uint32_t RESERVED : 31; + }STADIC_B; + }; + + /** @brief General call interruption clear register */ + union + { + __IM uint32_t GCIC; + struct + { + __IM uint32_t GCIC : 1; + __IM uint32_t RESERVED : 31; + }GCIC_B; + }; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + struct + { + __IOM uint32_t I2CEN : 1; + __IOM uint32_t ABR : 1; + __IOM uint32_t TCB : 1; + __IM uint32_t RESERVED : 29; + }CTRL2_B; + }; + + /** @brief Status register 1 */ + union + { + __IM uint32_t STS1; + struct + { + __IM uint32_t ACTF : 1; + __IM uint32_t TFNFF : 1; + __IM uint32_t TFEF : 1; + __IM uint32_t RFNEF : 1; + __IM uint32_t RFFF : 1; + __IM uint32_t MAF : 1; + __IM uint32_t SAF : 1; + __IM uint32_t RESERVED : 24; + }STS1_B; + }; + + /** @brief Transmission FIFO level */ + union + { + __IOM uint32_t TFL; + struct + { + __IOM uint32_t TFL : 4; + __IM uint32_t RESERVED : 28; + }TFL_B; + }; + + /** @brief Reception FIFO level */ + union + { + __IOM uint32_t RFL; + struct + { + __IOM uint32_t RFL : 4; + __IM uint32_t RESERVED : 28; + }RFL_B; + }; + + /** @brief SDA hold time length register */ + union + { + __IOM uint32_t SDAHOLD; + struct + { + __IOM uint32_t TXHOLD : 16; + __IOM uint32_t RXHOLD : 8; + __IM uint32_t RESERVED : 8; + }SDAHOLD_B; + }; + + /** @brief Transmission abort source register */ + union + { + __IM uint32_t TAS; + struct + { + __IM uint32_t AD7NA : 1; + __IM uint32_t AD10NA1 : 1; + __IM uint32_t AD10NA2 : 1; + __IM uint32_t TDNA : 1; + __IM uint32_t GCNA : 1; + __IM uint32_t GCR : 1; + __IM uint32_t HSAD : 1; + __IM uint32_t SNR : 1; + __IM uint32_t RNR10B : 1; + __IM uint32_t MSTDIS : 1; + __IM uint32_t ARBLOST : 1; + __IM uint32_t LFTF : 1; + __IM uint32_t SAL : 1; + __IM uint32_t SRI : 1; + __IM uint32_t USRARB : 1; + __IM uint32_t FLUCNT : 1; + __IM uint32_t RESERVED : 16; + }TAS_B; + }; + + /** @brief Slave data NACK only register */ + union + { + __IOM uint32_t SDNO; + struct + { + __IOM uint32_t NACK : 1; + __IM uint32_t RESERVED : 31; + }SDNO_B; + }; + + /** @brief DMA control register */ + union + { + __IOM uint32_t DMACTRL; + struct + { + __IOM uint32_t RXEN : 1; + __IOM uint32_t TXEN : 1; + __IM uint32_t RESERVED : 30; + }DMACTRL_B; + }; + + /** @brief DMA transmission data level register */ + union + { + __IOM uint32_t DTDL; + struct + { + __IOM uint32_t DTDL : 4; + __IM uint32_t RESERVED : 28; + }DTDL_B; + }; + + /** @brief DMA teception data level register */ + union + { + __IOM uint32_t DRDL; + struct + { + __IOM uint32_t DRDL : 4; + __IM uint32_t RESERVED : 28; + }DRDL_B; + }; + + /** @brief SDA delay register */ + union + { + __IOM uint32_t SDADLY; + struct + { + __IOM uint32_t SDADLY : 8; + __IM uint32_t RESERVED : 24; + }SDADLY_B; + }; + + /** @brief Genernal call ACK register */ + union + { + __IOM uint32_t GCA; + struct + { + __IOM uint32_t GCA : 1; + __IM uint32_t RESERVED : 31; + }GCA_B; + }; + + /** @brief Status register 2 */ + union + { + __IM uint32_t STS2; + struct + { + __IM uint32_t I2CEN : 1; + __IM uint32_t SDWB : 1; + __IM uint32_t SRDL : 1; + __IM uint32_t RESERVED : 29; + }STS2_B; + }; + + /** @brief Low speed spike suppression limit */ + union + { + __IOM uint32_t LSSSL; + struct + { + __IOM uint32_t LSSSL : 8; + __IM uint32_t RESERVED : 24; + }LSSSL_B; + }; + + /** @brief High speed spike suppression limit */ + union + { + __IOM uint32_t HSSSL; + struct + { + __IOM uint32_t HSSSL : 8; + __IM uint32_t RESERVED : 24; + }HSSSL_B; + }; + + uint32_t RESERVED[22]; + + /** @brief Switch register */ + union + { + __IOM uint32_t SW; + struct + { + __IOM uint32_t SW : 1; + __IM uint32_t RESERVED : 31; + }SW_B; + }; +}SCI2C_T; + +/** + * @brief Dynamic memory controler (DMC) + */ +typedef struct +{ + /** @brief Configuraion register */ + union + { + __IOM uint32_t CFG; + struct + { + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t BAWCFG : 2; + __IOM uint32_t RAWCFG : 4; + __IOM uint32_t CAWCFG : 4; + __IOM uint32_t DWCFG : 2; + __IM uint32_t RESERVED2 : 16; + }CFG_B; + }; + + /** @brief Timing register 0 */ + union + { + __IOM uint32_t TIM0; + struct + { + __IOM uint32_t CASLSEL0 : 2; + __IOM uint32_t RASMINTSEL : 4; + __IOM uint32_t DTIMSEL : 3; + __IOM uint32_t PCPSEL : 3; + __IOM uint32_t WRTIMSEL : 2; + __IOM uint32_t ARPSEL : 4; + __IOM uint32_t XSR0 : 4; + __IOM uint32_t ATACP : 4; + __IOM uint32_t ECASLSEL1 : 1; + __IOM uint32_t EXSR1 : 5; + }TIM0_B; + }; + + /** @brief Timing register 1 */ + union + { + __IOM uint32_t TIM1; + struct + { + __IOM uint32_t STBTIM : 16; + __IOM uint32_t ARNUMCFG : 4; + __IM uint32_t RESERVED : 12; + }TIM1_B; + }; + + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + struct + { + __IOM uint32_t INIT : 1; + __IOM uint32_t SRMEN : 1; + __IOM uint32_t PDMEN : 1; + __IOM uint32_t PCACFG : 1; + __IOM uint32_t FRBSREN : 1; + __IOM uint32_t FRASREN : 1; + __IOM uint32_t RDNUMMCFG : 3; + __IOM uint32_t MODESET : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t SRMFLG : 1; + __IOM uint32_t BANKNUMCFG : 5; + __IM uint32_t RESERVED2 : 15; + }CTRL1_B; + }; + + /** @brief Refresh register */ + union + { + __IOM uint32_t REF; + struct + { + __IOM uint32_t RCYCCFG : 16; + __IM uint32_t RESERVED : 16; + }REF_B; + }; + + /** @brief Chip select register */ + union + { + __IOM uint32_t CHIPSEL; + struct + { + __IM uint32_t RESERVED : 16; + __IOM uint32_t BACHIPSEL : 16; + + }CHIPSEL_B; + }; + + __IM uint32_t RESERVED[15]; + + /** @brief Mask register */ + union + { + __IOM uint32_t MASK; + struct + { + __IOM uint32_t MSIZESEL : 5; + __IOM uint32_t MTYPESEL : 3; + __IM uint32_t RESERVED : 24; + }MASK_B; + }; + + __IM uint32_t RESERVED1[234]; + + /** @brief Switch register */ + union + { + __IOM uint32_t SW; + struct + { + __IOM uint32_t MCSW : 1; + __IM uint32_t RESERVED : 31; + }SW_B; + }; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + struct + { + __IOM uint32_t CPHACFG : 1; + __IOM uint32_t RDDEN : 1; + __IOM uint32_t RDDCFG : 3; + __IOM uint32_t WPEN : 1; + __IM uint32_t RESERVED : 26; + }CTRL2_B; + }; +}DMC_T; + +/** + * @brief Debug MCU(DBGMCU) + */ +typedef struct +{ + /** @brief ID register */ + union + { + __IOM uint32_t IDCODE; + struct + { + __IOM uint32_t EQR : 12; + __IM uint32_t RESERVED : 4; + __IOM uint32_t WVR : 16; + }IDCODE_B; + }; + + /** @brief Control register */ + union + { + __IOM uint32_t CFG; + struct + { + __IOM uint32_t SLEEP_CLK_STS : 1; + __IOM uint32_t STOP_CLK_STS : 1; + __IOM uint32_t STANDBY_CLK_STS : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t IOEN : 1; + __IOM uint32_t MODE : 2; + __IOM uint32_t IWDT_STS : 1; + __IOM uint32_t WWDT_STS : 1; + __IOM uint32_t TMR1_STS : 1; + __IOM uint32_t TMR2_STS : 1; + __IOM uint32_t TMR3_STS : 1; + __IOM uint32_t TMR4_STS : 1; + __IOM uint32_t CAN1_STS : 1; + __IOM uint32_t I2C1_SMBUS_TIMEOUT_STS : 1; + __IOM uint32_t I2C2_SMBUS_TIMEOUT_STS : 1; + __IOM uint32_t TMR8_STS : 1; + __IOM uint32_t TMR5_STS : 1; + __IOM uint32_t TMR6_STS : 1; + __IOM uint32_t TMR7_STS : 1; + __IOM uint32_t CAN2_STS : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t TMR12_STS : 1; + __IOM uint32_t TMR13_STS : 1; + __IOM uint32_t TMR14_STS : 1; + __IOM uint32_t TMR9_STS : 1; + __IOM uint32_t TMR10_STS : 1; + __IOM uint32_t TMR11_STS : 1; + __IM uint32_t RESERVED3 : 1; + }CFG_B; + }; +}DBGMCU_T; + +/** + * @brief USB Device controler(USBD) + */ +typedef union +{ + __IOM uint32_t EP; + + struct + { + __IOM uint32_t ADDR : 4; + __IOM uint32_t TXSTS : 2; + __IOM uint32_t TXDTOG : 1; + __IOM uint32_t CTFT : 1; + __IOM uint32_t KIND : 1; + __IOM uint32_t TYPE : 2; + __IOM uint32_t SETUP : 1; + __IOM uint32_t RXSTS : 2; + __IOM uint32_t RXDTOG : 1; + __IOM uint32_t CTFR : 1; + __IM uint32_t RESERVED : 16; + }EP_B; +}USB_EP_REG_T; + +typedef struct +{ + /** Endpoint */ + USB_EP_REG_T EP[8]; + + __IM uint32_t RESERVED[8]; + + /** @brief Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t FORRST : 1; + __IOM uint32_t PWRDOWN : 1; + __IOM uint32_t LPWREN : 1; + __IOM uint32_t FORSUS : 1; + __IOM uint32_t WUPREQ : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ESOFIEN : 1; + __IOM uint32_t SOFIEN : 1; + __IOM uint32_t RSTIEN : 1; + __IOM uint32_t SUSIEN : 1; + __IOM uint32_t WUPIEN : 1; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t PMAOUIEN : 1; + __IOM uint32_t CTRIEN : 1; + __IM uint32_t RESERVED2 : 16; + }CTRL_B; + }; + + /** @brief Interrupt status register */ + union + { + __IOM uint32_t INTSTS; + + struct + { + __IOM uint32_t EPID : 4; + __IOM uint32_t DOT : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ESOFFLG : 1; + __IOM uint32_t SOFFLG : 1; + __IOM uint32_t RSTREQ : 1; + __IOM uint32_t SUSREQ : 1; + __IOM uint32_t WUPREQ : 1; + __IOM uint32_t ERRFLG : 1; + __IOM uint32_t PMOFLG : 1; + __IOM uint32_t CTFLG : 1; + __IM uint32_t RESERVED2 : 16; + }INTSTS_B; + }; + + /** @brief Frame number register */ + union + { + __IM uint32_t FRANUM; + + struct + { + __IM uint32_t FRANUM : 11; + __IM uint32_t LSOFNUM : 2; + __IM uint32_t LOCK : 1; + __IM uint32_t RXDMSTS : 1; + __IM uint32_t RXDPSTS : 1; + __IM uint32_t RESERVED : 16; + }FRANUM_B; + }; + + /** @brief Device address register */ + union + { + __IOM uint32_t ADDR; + + struct + { + __IOM uint32_t ADDR : 7; + __IOM uint32_t USBDEN : 1; + __IM uint32_t RESERVED : 24; + }ADDR_B; + }; + + /** @brief Buffer table address register */ + union + { + __IOM uint32_t BUFFTB; + + struct + { + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t BUFFTB : 13; + __IM uint32_t RESERVED2 : 16; + }BUFFTB_B; + }; + + __IM uint32_t RESERVED1[43]; + + /** @brief Buffer table address register */ + union + { + __IOM uint32_t SWITCH; + + struct + { + __IOM uint32_t SWITCH : 1; + __IM uint32_t RESERVED : 31; + }SWITCH_B; + }; +}USBD_T; + +/** FMC base address in the alias region */ +#define FMC_BASE ((uint32_t)0x08000000) +/** SRAM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) +/** Peripheral base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) + +/** SRAM base address in the bit-band region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) +/** Peripheral base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) + +/** EMMC registers base address */ +#define EMMC_R_BASE ((uint32_t)0xA0000000) +/** QSPI registers base address */ +#define QSPI_BASE ((uint32_t)0xA0000000) +/** DMC registers base address */ +#define DMC_BASE ((uint32_t)0xA0000000) + +/** Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TMR2_BASE (APB1PERIPH_BASE + 0x0000) +#define TMR3_BASE (APB1PERIPH_BASE + 0x0400) +#define TMR4_BASE (APB1PERIPH_BASE + 0x0800) +#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TMR6_BASE (APB1PERIPH_BASE + 0x1000) +#define TMR7_BASE (APB1PERIPH_BASE + 0x1400) +#define TMR12_BASE (APB1PERIPH_BASE + 0x1800) +#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TMR14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDT_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define USBD_BASE (APB1PERIPH_BASE + 0X5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BAKPR_BASE (APB1PERIPH_BASE + 0x6C00) +#define PMU_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EINT_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TMR1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TMR8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TMR15_BASE (APB2PERIPH_BASE + 0x4000) +#define TMR16_BASE (APB2PERIPH_BASE + 0x4400) +#define TMR17_BASE (APB2PERIPH_BASE + 0x4800) +#define TMR9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TMR10_BASE (APB2PERIPH_BASE + 0x5000) +#define TMR11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCM_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +/** FMC registers base address */ +#define FMC_R_BASE (AHBPERIPH_BASE + 0x2000) +/** FMC Option Bytes base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) + +/** EMMC Bank1 registers base address */ +#define EMMC_Bank1_R_BASE (EMMC_R_BASE + 0x0000) +/** EMMC Bank1E registers base address */ +#define EMMC_Bank1E_R_BASE (EMMC_R_BASE + 0x0104) +/** EMMC Bank2 registers base address */ +#define EMMC_Bank2_R_BASE (EMMC_R_BASE + 0x0060) +/** EMMC Bank3 registers base address */ +#define EMMC_Bank3_R_BASE (EMMC_R_BASE + 0x0080) +/**EMMC Bank4 registers base address */ +#define EMMC_Bank4_R_BASE (EMMC_R_BASE + 0x00A0) + +/** Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t)0xE0042000) + +#define CRC ((CRC_T *) CRC_BASE) +#define RTC ((RTC_T *) RTC_BASE) +#define PMU ((PMU_T *) PMU_BASE) +#define BAKPR ((BAKPR_T *) BAKPR_BASE) +#define TMR1 ((TMR_T *) TMR1_BASE) +#define TMR2 ((TMR_T *) TMR2_BASE) +#define TMR3 ((TMR_T *) TMR3_BASE) +#define TMR4 ((TMR_T *) TMR4_BASE) +#define TMR5 ((TMR_T *) TMR5_BASE) +#define TMR6 ((TMR_T *) TMR6_BASE) +#define TMR7 ((TMR_T *) TMR7_BASE) +#define TMR8 ((TMR_T *) TMR8_BASE) +#define TMR9 ((TMR_T *) TMR9_BASE) +#define TMR10 ((TMR_T *) TMR10_BASE) +#define TMR11 ((TMR_T *) TMR11_BASE) +#define TMR12 ((TMR_T *) TMR12_BASE) +#define TMR13 ((TMR_T *) TMR13_BASE) +#define TMR14 ((TMR_T *) TMR14_BASE) +#define TMR15 ((TMR_T *) TMR15_BASE) +#define TMR16 ((TMR_T *) TMR16_BASE) +#define TMR17 ((TMR_T *) TMR17_BASE) + +#define DMA1 ((DMA_T *) DMA1_BASE) +#define DMA2 ((DMA_T *) DMA2_BASE) + +#define DMA1_Channel1 ((DMA_Channel_T *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_T *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_T *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_T *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_T *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_T *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_T *) DMA1_Channel7_BASE) + +#define DMA2_Channel1 ((DMA_Channel_T *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_T *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_T *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_T *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_T *) DMA2_Channel5_BASE) + +#define CAN1 ((CAN_T *) CAN1_BASE) +#define CAN2 ((CAN_T *) CAN2_BASE) + +#define I2C1 ((I2C_T *) I2C1_BASE) +#define I2C2 ((I2C_T *) I2C2_BASE) + +#define OB ((OB_T *) OB_BASE) + +#define ADC1 ((ADC_T *) ADC1_BASE) +#define ADC2 ((ADC_T *) ADC2_BASE) +#define ADC3 ((ADC_T *) ADC3_BASE) + +#define EINT ((EINT_T *) EINT_BASE) + +#define IWDT ((IWDT_T *) IWDT_BASE) +#define SDIO ((SDIO_T *) SDIO_BASE) +#define DAC ((DAC_T *) DAC_BASE) + +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) + +#define WWDT ((WWDT_T *) WWDT_BASE) +#define USART2 ((USART_T *) USART2_BASE) +#define USART3 ((USART_T *) USART3_BASE) +#define UART4 ((USART_T *) UART4_BASE) +#define UART5 ((USART_T *) UART5_BASE) +#define AFIO ((AFIO_T *) AFIO_BASE) +#define GPIOA ((GPIO_T *) GPIOA_BASE) +#define GPIOB ((GPIO_T *) GPIOB_BASE) +#define GPIOC ((GPIO_T *) GPIOC_BASE) +#define GPIOD ((GPIO_T *) GPIOD_BASE) +#define GPIOE ((GPIO_T *) GPIOE_BASE) +#define GPIOF ((GPIO_T *) GPIOF_BASE) +#define GPIOG ((GPIO_T *) GPIOG_BASE) +#define USART1 ((USART_T *) USART1_BASE) +#define RCM ((RCM_T *) RCM_BASE) +#define FMC ((FMC_T *) FMC_R_BASE) +#define USBD ((USBD_T *)USBD_BASE) + +#define EMMC_Bank1 ((EMMC_Bank1_T *) EMMC_Bank1_R_BASE) +#define EMMC_Bank1E ((EMMC_Bank1E_T *)EMMC_Bank1E_R_BASE) +#define EMMC_Bank2 ((EMMC_Bank2_T *) EMMC_Bank2_R_BASE) +#define EMMC_Bank3 ((EMMC_Bank3_T *) EMMC_Bank3_R_BASE) +#define EMMC_Bank4 ((EMMC_Bank4_T *) EMMC_Bank4_R_BASE) + +#define DBGMCU ((DBGMCU_T *) DBGMCU_BASE) + +#define I2C3 ((SCI2C_T *)(I2C1_BASE)) +#define I2C4 ((SCI2C_T *)(I2C2_BASE)) + +#if defined (APM32F10X_MD) || defined (APM32F10X_LD) +#define QSPI ((QSPI_T *)QSPI_BASE) +#elif defined (APM32F10X_HD) +#define DMC ((DMC_T *)DMC_BASE) +#endif + +/* Define one bit mask */ +#define BIT0 ((uint32_t)0x00000001) +#define BIT1 ((uint32_t)0x00000002) +#define BIT2 ((uint32_t)0x00000004) +#define BIT3 ((uint32_t)0x00000008) +#define BIT4 ((uint32_t)0x00000010) +#define BIT5 ((uint32_t)0x00000020) +#define BIT6 ((uint32_t)0x00000040) +#define BIT7 ((uint32_t)0x00000080) +#define BIT8 ((uint32_t)0x00000100) +#define BIT9 ((uint32_t)0x00000200) +#define BIT10 ((uint32_t)0x00000400) +#define BIT11 ((uint32_t)0x00000800) +#define BIT12 ((uint32_t)0x00001000) +#define BIT13 ((uint32_t)0x00002000) +#define BIT14 ((uint32_t)0x00004000) +#define BIT15 ((uint32_t)0x00008000) +#define BIT16 ((uint32_t)0x00010000) +#define BIT17 ((uint32_t)0x00020000) +#define BIT18 ((uint32_t)0x00040000) +#define BIT19 ((uint32_t)0x00080000) +#define BIT20 ((uint32_t)0x00100000) +#define BIT21 ((uint32_t)0x00200000) +#define BIT22 ((uint32_t)0x00400000) +#define BIT23 ((uint32_t)0x00800000) +#define BIT24 ((uint32_t)0x01000000) +#define BIT25 ((uint32_t)0x02000000) +#define BIT26 ((uint32_t)0x04000000) +#define BIT27 ((uint32_t)0x08000000) +#define BIT28 ((uint32_t)0x10000000) +#define BIT29 ((uint32_t)0x20000000) +#define BIT30 ((uint32_t)0x40000000) +#define BIT31 ((uint32_t)0x80000000) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10x_H */ + + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h new file mode 100644 index 0000000000..2054757063 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h @@ -0,0 +1,29 @@ +/*! + * @file system_apm32f10x.h + * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __SYSTEM_APM32F10X_H +#define __SYSTEM_APM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_APM32F10X_H */ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s new file mode 100644 index 0000000000..d82311b15e --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s @@ -0,0 +1,354 @@ +;/*! +; * @file startup_apm32f10x_hd.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd +; * +; * @version V1.0.1 +; * +; * @date 2021-03-23 +; * +; */ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FMC_IRQHandler ; Flash + DCD RCM_IRQHandler ; RCM + DCD EINT0_IRQHandler ; EINT Line 0 + DCD EINT1_IRQHandler ; EINT Line 1 + DCD EINT2_IRQHandler ; EINT Line 2 + DCD EINT3_IRQHandler ; EINT Line 3 + DCD EINT4_IRQHandler ; EINT Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX + DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EINT9_5_IRQHandler ; EINT Line 9..5 + DCD TMR1_BRK_IRQHandler ; TMR1 Break + DCD TMR1_UP_IRQHandler ; TMR1 Update + DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR4_IRQHandler ; TMR4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EINT15_10_IRQHandler ; EINT Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line + DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend + DCD TMR8_BRK_IRQHandler ; TMR8 Break + DCD TMR8_UP_IRQHandler ; TMR8 Update + DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation + DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD EMMC_IRQHandler ; EMMC + DCD SDIO_IRQHandler ; SDIO + DCD TMR5_IRQHandler ; TMR5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD 0 ; Reserved + DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX + DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EINT9_5_IRQHandler [WEAK] + EXPORT TMR1_BRK_IRQHandler [WEAK] + EXPORT TMR1_UP_IRQHandler [WEAK] + EXPORT TMR1_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EINT15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBDWakeUp_IRQHandler [WEAK] + EXPORT TMR8_BRK_IRQHandler [WEAK] + EXPORT TMR8_UP_IRQHandler [WEAK] + EXPORT TMR8_TRG_COM_IRQHandler [WEAK] + EXPORT TMR8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT EMMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TMR5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TMR6_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + EXPORT USBD2_HP_CAN2_TX_IRQHandler [WEAK] + EXPORT USBD2_LP_CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + +WWDT_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCM_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USBD1_HP_CAN1_TX_IRQHandler +USBD1_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EINT9_5_IRQHandler +TMR1_BRK_IRQHandler +TMR1_UP_IRQHandler +TMR1_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EINT15_10_IRQHandler +RTCAlarm_IRQHandler +USBDWakeUp_IRQHandler +TMR8_BRK_IRQHandler +TMR8_UP_IRQHandler +TMR8_TRG_COM_IRQHandler +TMR8_CC_IRQHandler +ADC3_IRQHandler +EMMC_IRQHandler +SDIO_IRQHandler +TMR5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TMR6_IRQHandler +TMR7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler +USBD2_HP_CAN2_TX_IRQHandler +USBD2_LP_CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;*******************************END OF FILE************************************ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s new file mode 100644 index 0000000000..95ea8f5f22 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s @@ -0,0 +1,301 @@ +;/*! +; * @file startup_apm32f10x_md.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md +; * +; * @version V1.0.1 +; * +; * @date 2021-03-23 +; * +; */ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FMC_IRQHandler ; Flash + DCD RCM_IRQHandler ; RCM + DCD EINT0_IRQHandler ; EINT Line 0 + DCD EINT1_IRQHandler ; EINT Line 1 + DCD EINT2_IRQHandler ; EINT Line 2 + DCD EINT3_IRQHandler ; EINT Line 3 + DCD EINT4_IRQHandler ; EINT Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX + DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EINT9_5_IRQHandler ; EINT Line 9..5 + DCD TMR1_BRK_IRQHandler ; TMR1 Break + DCD TMR1_UP_IRQHandler ; TMR1 Update + DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR4_IRQHandler ; TMR4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EINT15_10_IRQHandler ; EINT Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line + DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend + DCD FPU_IRQHandler ; FPU + DCD QSPI_IRQHandler ; QSPI + DCD USBD2_HP_IRQHandler ; USBD2 High Priority + DCD USBD2_LP_IRQHandler ; USBD2 Low Priority +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EINT9_5_IRQHandler [WEAK] + EXPORT TMR1_BRK_IRQHandler [WEAK] + EXPORT TMR1_UP_IRQHandler [WEAK] + EXPORT TMR1_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EINT15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBDWakeUp_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USBD2_HP_IRQHandler [WEAK] + EXPORT USBD2_LP_IRQHandler [WEAK] + +WWDT_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCM_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USBD1_HP_CAN1_TX_IRQHandler +USBD1_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EINT9_5_IRQHandler +TMR1_BRK_IRQHandler +TMR1_UP_IRQHandler +TMR1_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EINT15_10_IRQHandler +RTCAlarm_IRQHandler +USBDWakeUp_IRQHandler +FPU_IRQHandler +QSPI_IRQHandler +USBD2_HP_IRQHandler +USBD2_LP_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;*******************************END OF FILE************************************ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c new file mode 100644 index 0000000000..aad3575613 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c @@ -0,0 +1,557 @@ +/*! + * @file system_apm32f10x.c + * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x.h" + +//#define SYSTEM_CLOCK_HSE HSE_VALUE +//#define SYSTEM_CLOCK_24MHz (24000000) +//#define SYSTEM_CLOCK_36MHz (36000000) +//#define SYSTEM_CLOCK_48MHz (48000000) +//#define SYSTEM_CLOCK_56MHz (56000000) +#define SYSTEM_CLOCK_72MHz (72000000) +//#define SYSTEM_CLOCK_96MHz (96000000) + + +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 + +#ifdef SYSTEM_CLOCK_HSE +uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE; +#elif defined SYSTEM_CLOCK_24MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz; +#elif defined SYSTEM_CLOCK_36MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz; +#elif defined SYSTEM_CLOCK_48MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz; +#elif defined SYSTEM_CLOCK_56MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz; +#elif defined SYSTEM_CLOCK_72MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz; +#else +uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz; +#endif + + +static void SystemClockConfig(void); + +#ifdef SYSTEM_CLOCK_HSE +static void SystemClockHSE(void); +#elif defined SYSTEM_CLOCK_24MHz +static void SystemClock24M(void); +#elif defined SYSTEM_CLOCK_36MHz +static void SystemClock36M(void); +#elif defined SYSTEM_CLOCK_48MHz +static void SystemClock48M(void); +#elif defined SYSTEM_CLOCK_56MHz +static void SystemClock56M(void); +#elif defined SYSTEM_CLOCK_72MHz +static void SystemClock72M(void); +#elif defined SYSTEM_CLOCK_96MHz +static void SystemClock96M(void); +#endif + +/*! + * @brief Setup the microcontroller system + * + * @param None + * + * @retval None + * + * @note + */ +void SystemInit (void) +{ + /** Set HSIEN bit */ + RCM->CTRL_B.HSIEN = BIT_SET; + /** Reset SCLKSW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ + RCM->CFG &= (uint32_t)0xF8FF0000; + /** Reset HSEEN, CSSEN and PLLEN bits */ + RCM->CTRL &= (uint32_t)0xFEF6FFFF; + /** Reset HSEBCFG bit */ + RCM->CTRL_B.HSEBCFG = BIT_RESET; + /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ + RCM->CFG &= (uint32_t)0xFF80FFFF; + /** Disable all interrupts and clear pending bits */ + RCM->INT = 0x009F0000; + + SystemClockConfig(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; +#else + SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET; +#endif +} + +/*! + * @brief Update SystemCoreClock variable according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK) + * + * @param None + * + * @retval None + * + * @note + */ +void SystemCoreClockUpdate (void) +{ + uint32_t sysClock, pllMull, pllSource, Prescaler; + uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sysClock = RCM->CFG_B.SCLKSWSTS; + + switch(sysClock) + { + /** sys clock is HSI */ + case 0: + SystemCoreClock = HSI_VALUE; + break; + + /** sys clock is HSE */ + case 1: + SystemCoreClock = HSE_VALUE; + break; + + /** sys clock is PLL */ + case 2: + pllMull = RCM->CFG_B.PLLMULCFG + 2; + pllSource = RCM->CFG_B.PLLSRCSEL; + + /** PLL entry clock source is HSE */ + if(pllSource == BIT_SET) + { + SystemCoreClock = HSE_VALUE * pllMull; + + /** HSE clock divided by 2 */ + if(pllSource == RCM->CFG_B.PLLHSEPSC) + { + SystemCoreClock >>= 1; + } + } + /** PLL entry clock source is HSI/2 */ + else + { + SystemCoreClock = (HSI_VALUE >> 1) * pllMull; + } + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + Prescaler = AHBPrescTable[RCM->CFG_B.AHBPSC]; + SystemCoreClock >>= Prescaler; +} + +/*! + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClockConfig(void) +{ +#ifdef SYSTEM_CLOCK_HSE + SystemClockHSE(); +#elif defined SYSTEM_CLOCK_24MHz + SystemClock24M(); +#elif defined SYSTEM_CLOCK_36MHz + SystemClock36M(); +#elif defined SYSTEM_CLOCK_48MHz + SystemClock48M(); +#elif defined SYSTEM_CLOCK_56MHz + SystemClock56M(); +#elif defined SYSTEM_CLOCK_72MHz + SystemClock72M(); +#elif defined SYSTEM_CLOCK_96MHz + SystemClock96M(); +#endif +} + +#if defined SYSTEM_CLOCK_HSE +/*! + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClockHSE(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 0 wait state */ + FMC->CTRL1_B.WS = 0; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK */ + RCM->CFG_B.APB1PSC = 0; + + /* Select HSE as system clock source */ + RCM->CFG_B.SCLKSW = 1; + + /** Wait till HSE is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x01); + } +} + + +#elif defined SYSTEM_CLOCK_24MHz +/*! + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock24M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 0 wait state */ + FMC->CTRL1_B.WS = 0; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK */ + RCM->CFG_B.APB1PSC = 0; + + /** PLL: (HSE / 2) * 6 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLHSEPSC = 1; + RCM->CFG_B.PLLMULCFG = 4; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} + +#elif defined SYSTEM_CLOCK_36MHz +/*! + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock36M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK */ + RCM->CFG_B.APB1PSC = 0; + + /** PLL: (HSE / 2) * 9 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLHSEPSC = 1; + RCM->CFG_B.PLLMULCFG = 7; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS != 0x02); + } +} + +#elif defined SYSTEM_CLOCK_48MHz +/*! + * @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock48M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 6 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 4; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} + +#elif defined SYSTEM_CLOCK_56MHz +/*! + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock56M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 2 wait state */ + FMC->CTRL1_B.WS = 2; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 7 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 5; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} + +#elif defined SYSTEM_CLOCK_72MHz +/*! + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock72M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 2 wait state */ + FMC->CTRL1_B.WS = 2; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 9 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 7; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } + +} + +#elif defined SYSTEM_CLOCK_96MHz +/*! + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock96M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 3 wait state */ + FMC->CTRL1_B.WS = 3; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 12 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 10; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} +#endif + diff --git a/bsp/apm32/libraries/APM32F10x_Library/SConscript b/bsp/apm32/libraries/APM32F10x_Library/SConscript new file mode 100644 index 0000000000..84a2e5e2f6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/SConscript @@ -0,0 +1,25 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +Device/Geehy/APM32F10x/Source/system_apm32f10x.c +APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c +APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c +APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c +APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c +APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c +""") + +path = [cwd + '/Device/Geehy/APM32F10x/Include', + cwd + '/APM32F10x_StdPeriphDriver/inc', + cwd + '/CMSIS/Include'] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/apm32/libraries/Drivers/SConscript b/bsp/apm32/libraries/Drivers/SConscript new file mode 100644 index 0000000000..aa3dcad878 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/SConscript @@ -0,0 +1,27 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + if GetDepend(['RT_USING_SERIAL_V2']): + src += ['drv_usart_v2.c'] + else: + src += ['drv_usart.c'] + +src += ['drv_common.c'] + +path = [cwd] +path += [cwd + '/config'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/apm32/libraries/Drivers/drv_common.c b/bsp/apm32/libraries/Drivers/drv_common.c new file mode 100644 index 0000000000..dd029321f8 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_common.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include "drv_common.h" +#include "board.h" + +#ifdef RT_USING_SERIAL +#ifdef RT_USING_SERIAL_V2 +#include "drv_usart_v2.h" +#else +#include "drv_usart.h" +#endif +#endif + +#ifdef RT_USING_FINSH +#include <finsh.h> +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + SysTick_Config(RCM_ReadHCLKFreq()/RT_TICK_PER_SECOND); + + /* AHB clock selected as SysTick clock source. */ + SysTick->CTRL |= 0x00000004U; + + NVIC_SetPriority(SysTick_IRQn, 0xFF); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function will initial STM32 board. + */ +RT_WEAK void rt_hw_board_init() +{ + /* Systick initialization */ + rt_hw_systick_init(); + + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* Pin driver initialization is open by default */ +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + diff --git a/bsp/apm32/libraries/Drivers/drv_common.h b/bsp/apm32/libraries/Drivers/drv_common.h new file mode 100644 index 0000000000..5218b1189b --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_common.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include <rtthread.h> +#include <rthw.h> +#ifdef RT_USING_DEVICE +#include <rtdevice.h> +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + +void _Error_Handler(char *s, int num); + +#ifndef Error_Handler +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#endif + +#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.c b/bsp/apm32/libraries/Drivers/drv_gpio.c new file mode 100644 index 0000000000..7f8413d7fb --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_gpio.c @@ -0,0 +1,573 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include <board.h> +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_APMPORT(pin) ((GPIO_T *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) + +#define PIN_APMPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + +#if defined(GPIOZ) + #define __APM32_PORT_MAX 12u +#elif defined(GPIOK) + #define __APM32_PORT_MAX 11u +#elif defined(GPIOJ) + #define __APM32_PORT_MAX 10u +#elif defined(GPIOI) + #define __APM32_PORT_MAX 9u +#elif defined(GPIOH) + #define __APM32_PORT_MAX 8u +#elif defined(GPIOG) + #define __APM32_PORT_MAX 7u +#elif defined(GPIOF) + #define __APM32_PORT_MAX 6u +#elif defined(GPIOE) + #define __APM32_PORT_MAX 5u +#elif defined(GPIOD) + #define __APM32_PORT_MAX 4u +#elif defined(GPIOC) + #define __APM32_PORT_MAX 3u +#elif defined(GPIOB) + #define __APM32_PORT_MAX 2u +#elif defined(GPIOA) + #define __APM32_PORT_MAX 1u +#else + #define __APM32_PORT_MAX 0u + #error Unsupported APM32 GPIO peripheral. +#endif + +#define PIN_APMPORT_MAX __APM32_PORT_MAX + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EINT0_IRQn}, + {GPIO_PIN_1, EINT1_IRQn}, + {GPIO_PIN_2, EINT2_IRQn}, + {GPIO_PIN_3, EINT3_IRQn}, + {GPIO_PIN_4, EINT4_IRQn}, + {GPIO_PIN_5, EINT9_5_IRQn}, + {GPIO_PIN_6, EINT9_5_IRQn}, + {GPIO_PIN_7, EINT9_5_IRQn}, + {GPIO_PIN_8, EINT9_5_IRQn}, + {GPIO_PIN_9, EINT9_5_IRQn}, + {GPIO_PIN_10, EINT15_10_IRQn}, + {GPIO_PIN_11, EINT15_10_IRQn}, + {GPIO_PIN_12, EINT15_10_IRQn}, + {GPIO_PIN_13, EINT15_10_IRQn}, + {GPIO_PIN_14, EINT15_10_IRQn}, + {GPIO_PIN_15, EINT15_10_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static rt_base_t _pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 4) || (name_len >= 6)) + { + return -RT_EINVAL; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + return -RT_EINVAL; + } + + if ((name[1] >= 'A') && (name[1] <= 'Z')) + { + hw_port_num = (int)(name[1] - 'A'); + } + else + { + return -RT_EINVAL; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; +} + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + GPIO_T *gpio_port; + uint16_t gpio_pin; + + if (PIN_PORT(pin) < PIN_APMPORT_MAX) + { + gpio_port = PIN_APMPORT(pin); + gpio_pin = PIN_APMPIN(pin); + + GPIO_WriteBitValue(gpio_port, gpio_pin, (uint8_t)value); + } +} + +static int _pin_read(rt_device_t dev, rt_base_t pin) +{ + GPIO_T *gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (PIN_PORT(pin) < PIN_APMPORT_MAX) + { + gpio_port = PIN_APMPORT(pin); + gpio_pin = PIN_APMPIN(pin); + value = GPIO_ReadInputBit(gpio_port, gpio_pin); + } + + return value; +} + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + GPIO_Config_T gpioConfig; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return; + } + + /* Configure gpioConfigure */ + gpioConfig.pin = PIN_APMPIN(pin); + gpioConfig.mode = GPIO_MODE_OUT_PP; + gpioConfig.speed = GPIO_SPEED_50MHz; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpioConfig.mode = GPIO_MODE_OUT_PP; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpioConfig.mode = GPIO_MODE_IN_PU; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpioConfig.mode = GPIO_MODE_IN_PU; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpioConfig.mode = GPIO_MODE_IN_PD; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpioConfig.mode = GPIO_MODE_OUT_OD; + } + + GPIO_Config(PIN_APMPORT(pin), &gpioConfig); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_APMPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_APMPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_Config_T gpioConfig; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return -RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(PIN_APMPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + /* Configure gpioConfigure */ + gpioConfig.pin = PIN_APMPIN(pin); + gpioConfig.speed = GPIO_SPEED_50MHz; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + gpioConfig.mode = GPIO_MODE_IN_PD; + break; + case PIN_IRQ_MODE_FALLING: + gpioConfig.mode = GPIO_MODE_IN_PU; + break; + case PIN_IRQ_MODE_RISING_FALLING: + gpioConfig.mode = GPIO_MODE_IN_FLOATING; + break; + } + GPIO_Config(PIN_APMPORT(pin), &gpioConfig); + + NVIC_EnableIRQRequest(irqmap->irqno, 5, 0); + pin_irq_enable_mask |= irqmap->pinbit; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(PIN_APMPIN(pin)); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + pin_irq_enable_mask &= ~irqmap->pinbit; + + if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _apm32_pin_ops = +{ + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_dettach_irq, + _pin_irq_enable, + _pin_get, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + + +void GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + pin_irq_hdr(bit2bitno(GPIO_Pin)); +} + + +void EINT0_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (EINT_ReadIntFlag(EINT_LINE_0)) + { + EINT_ClearIntFlag(EINT_LINE_0); + GPIO_EXTI_IRQHandler(GPIO_PIN_0); + } + + rt_interrupt_leave(); +} + +void EINT1_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_1)) + { + EINT_ClearIntFlag(EINT_LINE_1); + GPIO_EXTI_IRQHandler(GPIO_PIN_1); + } + rt_interrupt_leave(); +} + +void EINT2_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_2)) + { + EINT_ClearIntFlag(EINT_LINE_2); + GPIO_EXTI_IRQHandler(GPIO_PIN_2); + } + rt_interrupt_leave(); +} + +void EINT3_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_3)) + { + EINT_ClearIntFlag(EINT_LINE_3); + GPIO_EXTI_IRQHandler(GPIO_PIN_3); + } + rt_interrupt_leave(); +} + +void EINT4_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_4)) + { + EINT_ClearIntFlag(EINT_LINE_4); + GPIO_EXTI_IRQHandler(GPIO_PIN_4); + } + rt_interrupt_leave(); +} + +void EINT9_5_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_5)) + { + EINT_ClearIntFlag(EINT_LINE_5); + GPIO_EXTI_IRQHandler(GPIO_PIN_5); + } + if (EINT_ReadIntFlag(EINT_LINE_6)) + { + EINT_ClearIntFlag(EINT_LINE_6); + GPIO_EXTI_IRQHandler(GPIO_PIN_6); + } + if (EINT_ReadIntFlag(EINT_LINE_7)) + { + EINT_ClearIntFlag(EINT_LINE_7); + GPIO_EXTI_IRQHandler(GPIO_PIN_7); + } + if (EINT_ReadIntFlag(EINT_LINE_8)) + { + EINT_ClearIntFlag(EINT_LINE_8); + GPIO_EXTI_IRQHandler(GPIO_PIN_8); + } + if (EINT_ReadIntFlag(EINT_LINE_9)) + { + EINT_ClearIntFlag(EINT_LINE_9); + GPIO_EXTI_IRQHandler(GPIO_PIN_9); + } + rt_interrupt_leave(); +} + +void EINT15_10_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_10)) + { + EINT_ClearIntFlag(EINT_LINE_10); + GPIO_EXTI_IRQHandler(GPIO_PIN_10); + } + if (EINT_ReadIntFlag(EINT_LINE_11)) + { + EINT_ClearIntFlag(EINT_LINE_11); + GPIO_EXTI_IRQHandler(GPIO_PIN_11); + } + if (EINT_ReadIntFlag(EINT_LINE_12)) + { + EINT_ClearIntFlag(EINT_LINE_12); + GPIO_EXTI_IRQHandler(GPIO_PIN_12); + } + if (EINT_ReadIntFlag(EINT_LINE_13)) + { + EINT_ClearIntFlag(EINT_LINE_13); + GPIO_EXTI_IRQHandler(GPIO_PIN_13); + } + if (EINT_ReadIntFlag(EINT_LINE_14)) + { + EINT_ClearIntFlag(EINT_LINE_14); + GPIO_EXTI_IRQHandler(GPIO_PIN_14); + } + if (EINT_ReadIntFlag(EINT_LINE_15)) + { + EINT_ClearIntFlag(EINT_LINE_15); + GPIO_EXTI_IRQHandler(GPIO_PIN_15); + } + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ +#ifdef GPIOA + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); +#endif +#ifdef GPIOB + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB); +#endif +#ifdef GPIOC + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOC); +#endif +#ifdef GPIOD + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOD); +#endif +#ifdef GPIOE + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOE); +#endif +#ifdef GPIOF + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOF); +#endif +#ifdef GPIOG + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOG); +#endif + + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO); + + return rt_device_pin_register("pin", &_apm32_pin_ops, RT_NULL); +} + +#endif /* RT_USING_PIN */ diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.h b/bsp/apm32/libraries/Drivers/drv_gpio.h new file mode 100644 index 0000000000..1da4fdb97b --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_gpio.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include <drv_common.h> +#include <board.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define __APM32_PORT(port) GPIO##port##_BASE + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__APM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +int rt_hw_pin_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/apm32/libraries/Drivers/drv_usart.c b/bsp/apm32/libraries/Drivers/drv_usart.c new file mode 100644 index 0000000000..c3141be55c --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_usart.c @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include "board.h" +#include "drv_usart.h" + + +#ifdef RT_USING_SERIAL +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +/* stm32 config class */ +struct apm32_usart +{ + const char *name; + USART_T *usartx; + IRQn_Type irq_type; + struct rt_serial_device serial; +}; + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +}; + +static struct apm32_usart usart_config[] = +{ +#ifdef BSP_USING_UART1 + { + "uart1", + USART1, + USART1_IRQn, + }, +#endif +#ifdef BSP_USING_UART2 + { + "uart2", + USART2, + USART2_IRQn, + }, +#endif +}; + +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + USART_Config_T USART_ConfigStruct; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + struct apm32_usart *usart_instance = (struct apm32_usart *) serial->parent.user_data; + + apm32_usart_init(); + + USART_ConfigStruct.baudRate = cfg->baud_rate;; + USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_NONE; + USART_ConfigStruct.mode = USART_MODE_TX_RX; + USART_ConfigStruct.parity = USART_PARITY_NONE; + + switch (cfg->data_bits) + { + case DATA_BITS_8: + if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) + USART_ConfigStruct.wordLength = USART_WORD_LEN_9B; + else + USART_ConfigStruct.wordLength = USART_WORD_LEN_8B; + break; + case DATA_BITS_9: + USART_ConfigStruct.wordLength = USART_WORD_LEN_9B; + break; + default: + USART_ConfigStruct.wordLength = USART_WORD_LEN_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_ConfigStruct.stopBits = USART_STOP_BIT_1; + break; + case STOP_BITS_2: + USART_ConfigStruct.stopBits = USART_STOP_BIT_2; + break; + default: + USART_ConfigStruct.stopBits = USART_STOP_BIT_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + USART_ConfigStruct.parity = USART_PARITY_NONE; + break; + case PARITY_ODD: + USART_ConfigStruct.parity = USART_PARITY_ODD; + break; + case PARITY_EVEN: + USART_ConfigStruct.parity = USART_PARITY_EVEN; + break; + default: + USART_ConfigStruct.parity = USART_PARITY_NONE; + break; + } + + USART_Config(usart_instance->usartx, &USART_ConfigStruct); + USART_Enable(usart_instance->usartx); + + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct apm32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + + usart = (struct apm32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + + /* disable rx irq */ + NVIC_DisableIRQRequest(usart->irq_type); + + /* disable interrupt */ + USART_DisableInterrupt(usart->usartx, USART_INT_RXBNE); + + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQRequest(usart->irq_type, 1, 0); + + /* enable interrupt */ + USART_EnableInterrupt(usart->usartx, USART_INT_RXBNE); + break; + + } + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char c) +{ + struct apm32_usart *usart; + RT_ASSERT(serial != RT_NULL); + + usart = (struct apm32_usart *) serial->parent.user_data; + + RT_ASSERT(usart != RT_NULL); + + USART_TxData(usart->usartx, (uint8_t) c); + + while (USART_ReadStatusFlag(usart->usartx, USART_FLAG_TXC) == RESET); + + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct apm32_usart *usart; + RT_ASSERT(serial != RT_NULL); + usart = (struct apm32_usart *) serial->parent.user_data; + + RT_ASSERT(usart != RT_NULL); + + ch = -1; + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) + { + ch = USART_RxData(usart->usartx); + } + return ch; +} + +/** + * Uart common interrupt process. This need add to usart ISR. + * + * @param serial serial device + */ +static void usart_isr(struct rt_serial_device *serial) +{ + struct apm32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); + usart = (struct apm32_usart *) serial->parent.user_data; + + RT_ASSERT(usart != RT_NULL); + + /* UART in mode Receiver -------------------------------------------------*/ + if ((USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) && + (USART_ReadIntFlag(usart->usartx, USART_INT_RXBNE) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + USART_ClearStatusFlag(usart->usartx, USART_FLAG_RXBNE); + USART_ClearIntFlag(usart->usartx, USART_INT_RXBNE); + } + + else + { + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_CTS) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_CTS); + } + + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_LBD) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_LBD); + } + + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_TXBE) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_TXBE); + } + } +} + + + +#if defined(BSP_USING_UART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART2_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART2 */ + +static const struct rt_uart_ops apm32_usart_ops = +{ + .configure = _uart_configure, + .control = _uart_control, + .putc = _uart_putc, + .getc = _uart_getc, + .dma_transmit = RT_NULL +}; + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num; + int index; + + obj_num = sizeof(usart_config) / sizeof(struct apm32_usart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (index = 0; index < obj_num; index++) + { + usart_config[index].serial.ops = &apm32_usart_ops; + usart_config[index].serial.config = config; + + /* register USART device */ + result = rt_hw_serial_register(&usart_config[index].serial, + usart_config[index].name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX, &usart_config[index]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/apm32/libraries/Drivers/drv_usart.h b/bsp/apm32/libraries/Drivers/drv_usart.h new file mode 100644 index 0000000000..a9040cc14c --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_usart.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include <rtthread.h> +#include "rtdevice.h" +#include <rthw.h> +#include <drv_common.h> +#include <board.h> + +int rt_hw_usart_init(void); + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/apm32/libraries/Kconfig b/bsp/apm32/libraries/Kconfig new file mode 100644 index 0000000000..bb335315fa --- /dev/null +++ b/bsp/apm32/libraries/Kconfig @@ -0,0 +1,8 @@ +config SOC_FAMILY_APM32 + bool + +config SOC_SERIES_APM32F1 + bool + select ARCH_ARM_CORTEX_M3 + select SOC_FAMILY_APM32 + |
