diff options
| author | Meco Jianting Man <[email protected]> | 2021-03-14 12:30:42 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-03-14 12:30:42 +0800 |
| commit | c3ffe18688a3696a486855ae98002714546bd836 (patch) | |
| tree | 5636e6cd556bae6e052846080184182f487ca7b3 /bsp | |
| parent | 849c99d2fa8aff996cf0a54a88e67a47ed52999e (diff) | |
| parent | ca867e8c0620af7e48f4bfa6ea82d4e271b5ce4a (diff) | |
Merge pull request #27 from RT-Thread/master
pr
Diffstat (limited to 'bsp')
96 files changed, 1588 insertions, 1588 deletions
diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c index 734b224377..ec128bb1f0 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -65,16 +65,16 @@ void timer0_isr(int vector, void *param) void timer0_init(void) { - TMR0CON = BIT(7); //TIE - TMR0CNT = 0; + TMR0CON = BIT(7); //TIE + TMR0CNT = 0; - rt_hw_interrupt_install(IRQ_TMR0_VECTOR, timer0_isr, RT_NULL, "tick"); + rt_hw_interrupt_install(IRQ_TMR0_VECTOR, timer0_isr, RT_NULL, "tick"); } void timer0_cfg(uint32_t ticks) { - TMR0PR = (uint32_t)(ticks - 1UL); //1ms interrupt - TMR0CON |= BIT(0); // EN + TMR0PR = (uint32_t)(ticks - 1UL); //1ms interrupt + TMR0CON |= BIT(0); // EN } void hal_mdelay(uint32_t ms) @@ -127,3 +127,8 @@ void rt_hw_board_init(void) rt_components_board_init(); #endif } + +void rt_hw_us_delay(rt_uint32_t us) +{ + +} diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h index a4ad7daed4..37383063ba 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -12,7 +12,13 @@ #define BOARD_H__ #include <rtthread.h> -#include "ab32vgx.h" -#include "drv_gpio.h" +#include <ab32vgx.h> +#ifdef RT_USING_PIN +#include <drv_gpio.h> +#endif +#ifdef RT_USING_WDT +#include <drv_wdt.h> +#endif + #endif diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c index 10307cb325..10dbcf63fb 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes @@ -139,7 +139,7 @@ void saia_volume_set(rt_uint8_t volume) { if (volume > 100) volume = 100; - + uint32_t dvol = volume * 327; // max is 0x7ffff LOG_D("dvol=0x%x", dvol); DACVOLCON = dvol | (0x02 << 16); // dac fade in @@ -155,7 +155,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap rt_err_t result = RT_EOK; struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; switch (caps->main_type) @@ -231,7 +231,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap break; } - return RT_EOK; + return RT_EOK; } static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) @@ -320,14 +320,14 @@ static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_c break; } - return RT_EOK; + return RT_EOK; } static rt_err_t sound_init(struct rt_audio_device *audio) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; adpll_init(0); @@ -337,14 +337,14 @@ static rt_err_t sound_init(struct rt_audio_device *audio) saia_frequency_set(snd_dev->replay_config.samplerate); saia_channels_set(snd_dev->replay_config.channels); - return RT_EOK; + return RT_EOK; } static rt_err_t sound_start(struct rt_audio_device *audio, int stream) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; if (stream == AUDIO_STREAM_REPLAY) @@ -369,8 +369,8 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); - snd_dev = (struct sound_device *)audio->parent.user_data; + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; if (stream == AUDIO_STREAM_REPLAY) { @@ -387,7 +387,7 @@ rt_size_t sound_transmit(struct rt_audio_device *audio, const void *writeBuf, vo rt_size_t tmp_size = size / 4; rt_size_t count = 0; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; while (tmp_size-- > 0) { @@ -395,14 +395,14 @@ rt_size_t sound_transmit(struct rt_audio_device *audio, const void *writeBuf, vo AUBUFDATA = ((const uint32_t *)writeBuf)[count++]; } - return size; + return size; } static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; /** @@ -425,7 +425,7 @@ static struct rt_audio_ops ops = .init = sound_init, .start = sound_start, .stop = sound_stop, - .transmit = sound_transmit, + .transmit = sound_transmit, .buffer_info = sound_buffer_info, }; @@ -443,11 +443,11 @@ void audio_isr(int vector, void *param) static int rt_hw_sound_init(void) { - rt_uint8_t *tx_fifo = RT_NULL; - rt_uint8_t *rx_fifo = RT_NULL; + rt_uint8_t *tx_fifo = RT_NULL; + rt_uint8_t *rx_fifo = RT_NULL; - /* 分配 DMA 搬运 buffer */ - tx_fifo = rt_calloc(1, TX_FIFO_SIZE); + /* 分配 DMA 搬运 buffer */ + tx_fifo = rt_calloc(1, TX_FIFO_SIZE); if(tx_fifo == RT_NULL) { return -RT_ENOMEM; @@ -455,8 +455,8 @@ static int rt_hw_sound_init(void) snd_dev.tx_fifo = tx_fifo; - /* 分配 DMA 搬运 buffer */ - rx_fifo = rt_calloc(1, TX_FIFO_SIZE); + /* 分配 DMA 搬运 buffer */ + rx_fifo = rt_calloc(1, TX_FIFO_SIZE); if(rx_fifo == RT_NULL) { return -RT_ENOMEM; diff --git a/bsp/bluetrum/libcpu/cpu/cpuport.c b/bsp/bluetrum/libcpu/cpu/cpuport.c index ec3f9cdbc9..a2d405ccdd 100644 --- a/bsp/bluetrum/libcpu/cpu/cpuport.c +++ b/bsp/bluetrum/libcpu/cpu/cpuport.c @@ -41,9 +41,9 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, stk--; *stk = (rt_uint32_t)0x10003; /* Start address */ stk--; - *stk = (rt_uint32_t)tentry; /* Start address */ + *stk = (rt_uint32_t)tentry; /* Start address */ stk -= 22; - *stk = (rt_uint32_t)parameter; /* Register a0 parameter*/ + *stk = (rt_uint32_t)parameter; /* Register a0 parameter*/ stk -= 6; *stk = (rt_uint32_t)tp; /* Register thread pointer */ stk --; diff --git a/bsp/bluetrum/libcpu/cpu/interrupt.c b/bsp/bluetrum/libcpu/cpu/interrupt.c index 3e7dbdb553..64fedde2f9 100644 --- a/bsp/bluetrum/libcpu/cpu/interrupt.c +++ b/bsp/bluetrum/libcpu/cpu/interrupt.c @@ -24,16 +24,16 @@ void set_cpu_irq_comm(void (*irq_hook)(void)) void cpu_irq_comm_do(void) { - void (*pfnct)(void); + void (*pfnct)(void); uint32_t irq_pend = PICPND & irq_mask; - for (int i = 0; i < IRQ_TOTAL_NUM; i++) { + for (int i = 0; i < IRQ_TOTAL_NUM; i++) { if (irq_pend & BIT(i)) { pfnct = tbl_irq_vector[i]; if (pfnct) { - pfnct(); /* call ISR */ + pfnct(); /* call ISR */ } } - } + } } void rt_hw_irq_enable(int vector) @@ -56,12 +56,12 @@ void rt_hw_interrupt_init(void) /** * @brief This function will install a interrupt service routine to a interrupt. - * - * @param vector - * @param handler - * @param param - * @param name - * @return rt_isr_handler_t + * + * @param vector + * @param handler + * @param param + * @param name + * @return rt_isr_handler_t */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, diff --git a/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h b/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h index 9fc2df3a8a..22cd84da5b 100644 --- a/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h +++ b/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h b/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h index c9f192a9de..b1c29ae1e8 100644 --- a/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h +++ b/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_adc.c b/bsp/bluetrum/libraries/hal_drivers/drv_adc.c index 5f300ebe58..d9c5bf768d 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_adc.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_adc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -45,7 +45,7 @@ static rt_err_t ab32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann { RT_ASSERT(device != RT_NULL); - hal_adc_enable(enabled); + hal_adc_enable(enabled); return RT_EOK; } @@ -53,7 +53,7 @@ static rt_err_t ab32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann static rt_uint32_t ab32_adc_get_channel(rt_uint32_t channel) { rt_uint32_t ab32_channel = 0; - + switch (channel) { case 0: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_common.h b/bsp/bluetrum/libraries/hal_drivers/drv_common.h index 93c77a9d93..0696bb17f3 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_common.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c index d8bc51d91e..4e0f96a794 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h index 525702e75a..7955a47d11 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c b/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c index 0015afbc5d..aaa3ddbea2 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_log.h b/bsp/bluetrum/libraries/hal_drivers/drv_log.h index 0491ee177e..398014a527 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_log.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_log.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c index 5fe2bf8d1e..a9ca1a2b6d 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h index 0a8360db7d..09c1d04f52 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c b/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c index 94dfa6c5f1..d2045b863f 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c @@ -235,8 +235,8 @@ int rt_hw_i2c_init(void) ab32_i2c_bus_unlock(&soft_i2c_config[i]); LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, soft_i2c_config[i].sda); } diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_usart.c b/bsp/bluetrum/libraries/hal_drivers/drv_usart.c index ee6c5791a3..8758058c85 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_usart.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_usart.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_usart.h b/bsp/bluetrum/libraries/hal_drivers/drv_usart.h index 8bcf9c3bcc..1c48cf77d2 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_usart.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_usart.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c index fc2bc0279b..28299897d1 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -12,6 +12,8 @@ #ifdef RT_USING_WDT +#include <drv_wdt.h> + // #define DRV_DEBUG #define LOG_TAG "drv.wdt" #include <drv_log.h> @@ -49,35 +51,35 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) switch (*((rt_uint32_t *)arg)) { - case 0: + case AB32_WDT_TIMEOUT_1MS: LOG_I("The watchdog timeout is set to 1ms"); tmp |= (0xa << 24) | (0x00 << 20); break; - case 1: + case AB32_WDT_TIMEOUT_256MS: LOG_I("The watchdog timeout is set to 256ms"); tmp |= (0xa << 24) | (0x01 << 20); break; - case 2: + case AB32_WDT_TIMEOUT_512MS: LOG_I("The watchdog timeout is set to 512ms"); tmp |= (0xa << 24) | (0x02 << 20); break; - case 3: + case AB32_WDT_TIMEOUT_1024MS: LOG_I("The watchdog timeout is set to 1024ms"); tmp |= (0xa << 24) | (0x03 << 20); break; - case 4: + case AB32_WDT_TIMEOUT_2048MS: LOG_I("The watchdog timeout is set to 2048ms"); tmp |= (0xa << 24) | (0x04 << 20); break; - case 5: + case AB32_WDT_TIMEOUT_4096MS: LOG_I("The watchdog timeout is set to 4096ms"); tmp |= (0xa << 24) | (0x05 << 20); break; - case 6: + case AB32_WDT_TIMEOUT_8192MS: LOG_I("The watchdog timeout is set to 8192ms"); tmp |= (0xa << 24) | (0x06 << 20); break; - case 7: + case AB32_WDT_TIMEOUT_16384MS: LOG_I("The watchdog timeout is set to 16384ms"); tmp |= (0xa << 24) | (0x07 << 20); break; @@ -92,28 +94,28 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: switch ((WDTCON >> 20) & 0x7) { - case 0: + case AB32_WDT_TIMEOUT_1MS: LOG_D("The watchdog timeout is set to 1ms"); break; - case 1: + case AB32_WDT_TIMEOUT_256MS: LOG_D("The watchdog timeout is set to 256ms"); break; - case 2: + case AB32_WDT_TIMEOUT_512MS: LOG_D("The watchdog timeout is set to 512ms"); break; - case 3: + case AB32_WDT_TIMEOUT_1024MS: LOG_D("The watchdog timeout is set to 1024ms"); break; - case 4: + case AB32_WDT_TIMEOUT_2048MS: LOG_D("The watchdog timeout is set to 2048ms"); break; - case 5: + case AB32_WDT_TIMEOUT_4096MS: LOG_D("The watchdog timeout is set to 4096ms"); break; - case 6: + case AB32_WDT_TIMEOUT_8192MS: LOG_D("The watchdog timeout is set to 8192ms"); break; - case 7: + case AB32_WDT_TIMEOUT_16384MS: LOG_D("The watchdog timeout is set to 16384ms"); break; default: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_wdt.h b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.h new file mode 100644 index 0000000000..5f8d61aaff --- /dev/null +++ b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020-2021, Bluetrum Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-11 Meco Man first version + */ + +#ifndef DRV_WDT_H__ +#define DRV_WDT_H__ + +#define AB32_WDT_TIMEOUT_1MS 0 +#define AB32_WDT_TIMEOUT_256MS 1 +#define AB32_WDT_TIMEOUT_512MS 2 +#define AB32_WDT_TIMEOUT_1024MS 3 +#define AB32_WDT_TIMEOUT_2048MS 4 +#define AB32_WDT_TIMEOUT_4096MS 5 +#define AB32_WDT_TIMEOUT_8192MS 6 +#define AB32_WDT_TIMEOUT_16384MS 7 + +#endif diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h index 0383558646..b1b68b844b 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h @@ -31,28 +31,28 @@ #define ADC_CHANNEL_15 (1u << 15) /** * @} - * + * */ /** * @brief Enable ADC - * - * @param enable + * + * @param enable */ void hal_adc_enable(uint8_t enable); /** * @brief Starts conversion of the channels - * + * * @param channel @ref ADC_channels */ void hal_adc_start(uint32_t channel); /** * @brief Poll for conversion complete - * + * * @param timeout Timeout value in millisecond - * @return hal_error_t + * @return hal_error_t */ hal_error_t hal_adc_poll_for_conversion(uint32_t timeout); diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h index ea039cbbd2..0202566e70 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h @@ -13,7 +13,7 @@ struct gpio_init { uint8_t pin; uint8_t dir; - uint8_t de; + uint8_t de; uint8_t pull; uint32_t alternate; uint32_t af_con; /*!< Alternate function control diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h index f2a94d65ac..9f41619be8 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h @@ -28,7 +28,7 @@ * G5: tx:PA1 rx:PA0 * G6: tx:PE0 rx:PE1 * G7: tx:PF2 rx:map to tx - * + * * UART1: * G1: tx:PA7 rx:PA6 * G2: tx:PA4 rx:PA3 @@ -52,17 +52,17 @@ * G1: PE7 * G2: PF2 * G3: PA3 - * + * * LPWM2: * G1: PE6 * G2: PE0 * G3: PA2 - * + * * LPWM1: * G1: PE5 * G2: PB4 * G3: PA1 - * + * * LPWM0: * G1: PE4 * G2: PB3 @@ -76,10 +76,10 @@ /** * TMR5: * G1: PE1 PE2 PE3 - * + * * TMR4: * G1: PA5 PA6 PA7 - * + * * TMR3: * G1: PB0 PB1 PB2 */ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h index 6802bfc61f..c2eed3c51e 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h @@ -39,7 +39,7 @@ struct uart_init /** * @brief UART handle struction definition - * + * */ struct uart_handle { @@ -76,8 +76,8 @@ struct uart_handle /** @defgroup UART_Mode UART Transfer Mode * @{ */ -#define UART_MODE_TX (0x00u) /*!< TX mode */ -#define UART_MODE_TX_RX (0x01u) /*!< RX and TX mode */ +#define UART_MODE_TX (0x00u) /*!< TX mode */ +#define UART_MODE_TX_RX (0x01u) /*!< RX and TX mode */ /** * @} diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c index 3e06595986..0a3fe31844 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c @@ -105,7 +105,7 @@ void hal_gpio_init(hal_sfr_t gpiox, gpio_init_t gpio_init) /** * @brief Read the specified input port pin. - * + * * @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN). * @param pin This parameter can be GPIO_PIN_x where x can be (0.15). * @return uint8_t The input port pin value. @@ -117,7 +117,7 @@ uint8_t hal_gpio_read(hal_sfr_t gpiox, uint8_t pin) /** * @brief Set or clear the selected data port bit. - * + * * @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN). * @param pin This parameter can be GPIO_PIN_x where x can be (0.15). * @param state specifies the value to be written to the selected bit. @@ -135,7 +135,7 @@ void hal_gpio_write(hal_sfr_t gpiox, uint8_t pin, uint8_t state) /** * @brief Toggle the specified GPIO pin. - * + * * @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN). * @param pin This parameter can be GPIO_PIN_x where x can be (0.15). */ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c index 6ed02005df..e0d3a54950 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c @@ -232,7 +232,7 @@ static bool sd_go_ready_try(sd_handle_t hsd) case CARD_V1: sdmmc_acmd_op_cond(hsd, 0x00ff8000); break; - + case CARD_V2: sdmmc_acmd_op_cond(hsd, 0x40ff8000); break; @@ -389,8 +389,8 @@ bool hal_sd_read(sd_handle_t hsd, void *buf, uint32_t lba) return true; } } - hsd->sdcard.state = HAL_SD_STATE_INVAL; - + hsd->sdcard.state = HAL_SD_STATE_INVAL; + hal_mdelay(20); } diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c index bef740f89f..3d3ecc3fe0 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c @@ -18,7 +18,7 @@ enum /** * @brief Set the UART baud rate. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). * @param baud Baud rate. */ @@ -33,9 +33,9 @@ void hal_uart_setbaud(hal_sfr_t uartx, uint32_t baud) /** * @brief Initialize the UART mode. - * + * * @param huart UART handle. - * @return hal_error_t + * @return hal_error_t */ hal_error_t hal_uart_init(struct uart_handle *huart) { @@ -51,7 +51,7 @@ hal_error_t hal_uart_init(struct uart_handle *huart) /** * @brief DeInitialize the UART peripheral. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). */ void hal_uart_deinit(hal_sfr_t uartx) @@ -61,7 +61,7 @@ void hal_uart_deinit(hal_sfr_t uartx) /** * @brief Initialize the UART MSP. - * + * * @param huart UART handle. */ WEAK void HAL_UART_MspInit(struct uart_handle *huart) @@ -69,9 +69,9 @@ WEAK void HAL_UART_MspInit(struct uart_handle *huart) /** * @brief Control the UART peripheral. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). - * @param cntl + * @param cntl * @arg UART_MODULE_ENABLE * @arg UART_BIT9_ENABLE * @arg UART_RXIT_ENABLE @@ -80,7 +80,7 @@ WEAK void HAL_UART_MspInit(struct uart_handle *huart) * @arg UART_CLK_SRC1 * @arg UART_1LINE_ENABLE * @arg UART_RX_ENABLE - * @param param + * @param param * @arg HAL_DISABLE * @arg HAL_ENABLE */ @@ -95,7 +95,7 @@ void hal_uart_control(hal_sfr_t uartx, uint32_t cntl, uint32_t param) /** * @brief Send a character - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). * @param data The characters that need to be sent */ @@ -106,7 +106,7 @@ void hal_uart_write(hal_sfr_t uartx, uint8_t data) /** * @brief Receive a character. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). * @return uint8_t Received character. */ @@ -117,12 +117,12 @@ uint8_t hal_uart_read(hal_sfr_t uartx) /** * @brief Get the UART flag. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). - * @param flag + * @param flag * @arg UART_FLAG_RXPND * @arg UART_FLAG_TXPND - * @return uint32_t + * @return uint32_t */ uint32_t hal_uart_getflag(hal_sfr_t uartx, uint32_t flag) { @@ -132,9 +132,9 @@ uint32_t hal_uart_getflag(hal_sfr_t uartx, uint32_t flag) /** * @brief Clear the UART flag. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). - * @param flag + * @param flag * @arg UART_FLAG_RXPND * @arg UART_FLAG_TXPND */ @@ -145,7 +145,7 @@ void hal_uart_clrflag(hal_sfr_t uartx, uint32_t flag) /** * @brief Configure the UART peripheral. - * + * * @param huart UART handle. */ void uart_config_all(struct uart_handle *huart) diff --git a/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h b/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h index 9830369288..c436572b34 100644 --- a/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h +++ b/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h @@ -17,18 +17,18 @@ typedef enum IRQ_SW_VECTOR = 2, IRQ_TMR0_VECTOR = 3, IRQ_TMR1_VECTOR = 4, - IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */ - IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */ + IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */ + IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */ IRQ_USB_VECTOR = 7, IRQ_SD_VECTOR = 8, - IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */ + IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */ IRQ_SDADC_VECTOR = 10, IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */ - IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */ - IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */ - IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */ + IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */ + IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */ + IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */ IRQ_HSUART_VECTOR = 15, - IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */ + IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */ IRQ_I2S_VECTOR = 17, IRQ_TOTAL_NUM = 23, } irq_type; diff --git a/bsp/gd32103c-eval/drivers/drv_gpio.h b/bsp/gd32103c-eval/drivers/drv_gpio.h index 1240cc4cb2..34d30d63d4 100644 --- a/bsp/gd32103c-eval/drivers/drv_gpio.h +++ b/bsp/gd32103c-eval/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32303e-eval/drivers/board.c b/bsp/gd32303e-eval/drivers/board.c index 9ca024ec48..d4091d32dc 100644 --- a/bsp/gd32303e-eval/drivers/board.c +++ b/bsp/gd32303e-eval/drivers/board.c @@ -79,7 +79,7 @@ void rt_hw_board_init() rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif -#ifdef RT_USING_HEAP +#ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif } diff --git a/bsp/gd32303e-eval/drivers/board.h b/bsp/gd32303e-eval/drivers/board.h index 5e1f15cd5d..4e97fce727 100644 --- a/bsp/gd32303e-eval/drivers/board.h +++ b/bsp/gd32303e-eval/drivers/board.h @@ -19,7 +19,7 @@ #include <gd32f30x.h> // <o> Internal SRAM memory size[Kbytes] <8-64> -// <i>Default: 64 +// <i>Default: 64 #ifdef __ICCARM__ // Use *.icf ram symbal, to avoid hardcode. extern char __ICFEDIT_region_RAM_end__; diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.c b/bsp/gd32303e-eval/drivers/drv_gpio.c index b7285513d3..700a11d3df 100644 --- a/bsp/gd32303e-eval/drivers/drv_gpio.c +++ b/bsp/gd32303e-eval/drivers/drv_gpio.c @@ -261,7 +261,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) /* GPIO Periph clock enable */ rcu_periph_clock_enable(index->clk); pin_mode = GPIO_MODE_OUT_PP; - + switch(mode) { case PIN_MODE_OUTPUT: @@ -442,7 +442,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ return RT_EINVAL; } irqmap = &pin_irq_map[hdr_index]; - + switch (pin_irq_hdr_tab[hdr_index].mode) { case PIN_IRQ_MODE_RISING: @@ -463,14 +463,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ /* enable and set interrupt priority */ nvic_irq_enable(irqmap->irqno, 5U, 0U); - + /* connect EXTI line to GPIO pin */ gpio_exti_source_select(index->port_src, index->pin_src); /* configure EXTI line */ exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - + rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) @@ -505,7 +505,7 @@ int rt_hw_pin_init(void) int result; result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); - + return result; } INIT_BOARD_EXPORT(rt_hw_pin_init); @@ -524,7 +524,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) { pin_irq_hdr(exti_line); exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } + } } void EXTI0_IRQHandler(void) { diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.c b/bsp/gd32303e-eval/drivers/drv_i2c.c index 059b211c01..0cca20e1d0 100644 --- a/bsp/gd32303e-eval/drivers/drv_i2c.c +++ b/bsp/gd32303e-eval/drivers/drv_i2c.c @@ -168,7 +168,7 @@ static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_u *p_buffer = i2c_data_receive(i2c_periph); /* point to the next location where the byte read will be saved */ - p_buffer++; + p_buffer++; /* decrement the read bytes counter */ data_byte--; @@ -277,7 +277,7 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg } } } - + ret = i; out: @@ -287,7 +287,7 @@ out: } static const struct rt_i2c_bus_device_ops i2c_ops = -{ +{ gd32_i2c_xfer, RT_NULL, RT_NULL @@ -324,7 +324,7 @@ int rt_hw_i2c_init(void) i2c_device.priv = (void *)&_i2c_bit_ops; rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); - } + } #else /* register hardware I2C */ diff --git a/bsp/gd32303e-eval/drivers/drv_spi.c b/bsp/gd32303e-eval/drivers/drv_spi.c index e5df557ae8..78ff99d423 100644 --- a/bsp/gd32303e-eval/drivers/drv_spi.c +++ b/bsp/gd32303e-eval/drivers/drv_spi.c @@ -119,7 +119,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat spi_init_struct.prescale = SPI_PSC_256; } } /* baudrate */ - + switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: @@ -135,7 +135,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; break; } - + /* MSB or LSB */ if(configuration->mode & RT_SPI_MSB) { @@ -145,7 +145,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat { spi_init_struct.endian = SPI_ENDIAN_LSB; } - + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_init_struct.device_mode = SPI_MASTER; spi_init_struct.nss = SPI_NSS_SOFT; @@ -181,7 +181,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes const rt_uint8_t * send_ptr = message->send_buf; rt_uint8_t * recv_ptr = message->recv_buf; rt_uint32_t size = message->length; - + DEBUG_PRINTF("spi poll transfer start: %d\n", size); while(size--) @@ -192,7 +192,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes { data = *send_ptr++; } - + // Todo: replace register read/write by gd32f3 lib //Wait until the transmit buffer is empty while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); @@ -267,8 +267,8 @@ int gd32_hw_spi_init(void) rcu_periph_clock_enable(RCU_SPI0); /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */ gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); - gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); - + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + #endif #ifdef RT_USING_SPI1 static struct rt_spi_bus spi_bus1; @@ -287,7 +287,7 @@ int gd32_hw_spi_init(void) static struct rt_spi_bus spi_bus2; spi_bus2.parent.user_data = (void *)SPI2; - result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); + result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); rcu_periph_clock_enable(RCU_SPI2); rcu_periph_clock_enable(RCU_GPIOB); diff --git a/bsp/gd32303e-eval/drivers/drv_spi_flash.c b/bsp/gd32303e-eval/drivers/drv_spi_flash.c index 54e6be30ef..d4a3dafc1b 100644 --- a/bsp/gd32303e-eval/drivers/drv_spi_flash.c +++ b/bsp/gd32303e-eval/drivers/drv_spi_flash.c @@ -30,7 +30,7 @@ static int rt_hw_gd25q40_init(void) static rt_base_t gd25q_cs_pin; /* SPI设备CS片选引脚 */ gd25q_cs_pin = GD25Q_SPI_CS_PIN; - + rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP); res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin); diff --git a/bsp/gd32303e-eval/drivers/drv_usart.c b/bsp/gd32303e-eval/drivers/drv_usart.c index 436f86fcb6..33430a5a31 100644 --- a/bsp/gd32303e-eval/drivers/drv_usart.c +++ b/bsp/gd32303e-eval/drivers/drv_usart.c @@ -44,7 +44,7 @@ struct gd32_uart uint32_t tx_port; uint16_t tx_pin; uint32_t rx_port; - uint16_t rx_pin; + uint16_t rx_pin; struct rt_serial_device * serial; char *device_name; @@ -143,7 +143,7 @@ static const struct gd32_uart uarts[] = { "uart0", }, #endif - + #ifdef RT_USING_USART1 { USART1, // uart peripheral index @@ -155,7 +155,7 @@ static const struct gd32_uart uarts[] = { "uart1", }, #endif - + #ifdef RT_USING_USART2 { USART2, // uart peripheral index @@ -167,7 +167,7 @@ static const struct gd32_uart uarts[] = { "uart2", }, #endif - + #ifdef RT_USING_UART3 { UART3, // uart peripheral index @@ -179,7 +179,7 @@ static const struct gd32_uart uarts[] = { "uart3", }, #endif - + #ifdef RT_USING_UART4 { UART4, // uart peripheral index @@ -228,9 +228,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co RT_ASSERT(cfg != RT_NULL); uart = (struct gd32_uart *)serial->parent.user_data; - + gd32_uart_gpio_init(uart); - + usart_baudrate_set(uart->uart_periph, cfg->baud_rate); switch (cfg->data_bits) @@ -310,7 +310,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch) usart_data_transmit(uart->uart_periph, ch); while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - + return 1; } diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_eval.c b/bsp/gd32303e-eval/drivers/gd32f303e_eval.c index 0829f0bf00..c8982455a2 100644 --- a/bsp/gd32303e-eval/drivers/gd32f303e_eval.c +++ b/bsp/gd32303e-eval/drivers/gd32f303e_eval.c @@ -23,15 +23,15 @@ static uint32_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; static uint32_t COM_GPIO_PORT[COMn] = {EVAL_COM1_GPIO_PORT, EVAL_COM2_GPIO_PORT}; static rcu_periph_enum COM_GPIO_CLK[COMn] = {EVAL_COM1_GPIO_CLK, EVAL_COM2_GPIO_CLK}; -static rcu_periph_enum GPIO_CLK[LEDn] = {LED2_GPIO_CLK, LED3_GPIO_CLK, +static rcu_periph_enum GPIO_CLK[LEDn] = {LED2_GPIO_CLK, LED3_GPIO_CLK, LED4_GPIO_CLK, LED5_GPIO_CLK}; -static uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT, +static uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT, TAMPER_KEY_GPIO_PORT, USER_KEY1_GPIO_PORT, USER_KEY2_GPIO_PORT}; static uint32_t KEY_PIN[KEYn] = {WAKEUP_KEY_PIN, TAMPER_KEY_PIN,USER_KEY1_PIN,USER_KEY2_PIN}; -static rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK, +static rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK, TAMPER_KEY_GPIO_CLK, USER_KEY1_GPIO_CLK, USER_KEY2_GPIO_CLK}; @@ -47,7 +47,7 @@ static uint8_t KEY_PIN_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PIN_SOURCE, TAMPER_KEY_EXTI_PIN_SOURCE, USER_KEY1_EXTI_PIN_SOURCE, USER_KEY2_EXTI_PIN_SOURCE}; -static uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn, +static uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn, TAMPER_KEY_EXTI_IRQn, USER_KEY1_EXTI_IRQn, USER_KEY2_EXTI_IRQn}; @@ -66,7 +66,7 @@ void gd_eval_led_init (led_typedef_enum lednum) { /* enable the led clock */ rcu_periph_clock_enable(GPIO_CLK[lednum]); - /* configure led GPIO port */ + /* configure led GPIO port */ gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,GPIO_PIN[lednum]); GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; @@ -114,7 +114,7 @@ void gd_eval_led_off(led_typedef_enum lednum) */ void gd_eval_led_toggle(led_typedef_enum lednum) { - gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum], + gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum], (bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum]))); } @@ -184,7 +184,7 @@ void gd_eval_com_init(uint32_t com) }else if(EVAL_COM2 == com){ com_id = 1U; } - + /* enable GPIO clock */ rcu_periph_clock_enable(COM_GPIO_CLK[com_id]); diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_eval.h b/bsp/gd32303e-eval/drivers/gd32f303e_eval.h index e841fb00f4..932102cbd7 100644 --- a/bsp/gd32303e-eval/drivers/gd32f303e_eval.h +++ b/bsp/gd32303e-eval/drivers/gd32f303e_eval.h @@ -17,9 +17,9 @@ #endif #include "gd32f30x.h" - + /* exported types */ -typedef enum +typedef enum { LED2 = 0, LED3 = 1, @@ -27,7 +27,7 @@ typedef enum LED5 = 3 } led_typedef_enum; -typedef enum +typedef enum { KEY_WAKEUP = 0, KEY_TAMPER = 1, @@ -35,7 +35,7 @@ typedef enum KEY_USER2 = 3 } key_typedef_enum; -typedef enum +typedef enum { KEY_MODE_GPIO = 0, KEY_MODE_EXTI = 1 @@ -47,15 +47,15 @@ typedef enum #define LED2_PIN GPIO_PIN_0 #define LED2_GPIO_PORT GPIOF #define LED2_GPIO_CLK RCU_GPIOF - + #define LED3_PIN GPIO_PIN_1 #define LED3_GPIO_PORT GPIOF #define LED3_GPIO_CLK RCU_GPIOF - + #define LED4_PIN GPIO_PIN_2 #define LED4_GPIO_PORT GPIOF #define LED4_GPIO_CLK RCU_GPIOF - + #define LED5_PIN GPIO_PIN_3 #define LED5_GPIO_PORT GPIOF #define LED5_GPIO_CLK RCU_GPIOF @@ -85,7 +85,7 @@ typedef enum #define WAKEUP_KEY_EXTI_LINE EXTI_0 #define WAKEUP_KEY_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA #define WAKEUP_KEY_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0 -#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn +#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn /* tamper push-button */ #define TAMPER_KEY_PIN GPIO_PIN_13 diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c index 228feafdf8..3ca126e87e 100644 --- a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c +++ b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c @@ -15,7 +15,7 @@ /*! \brief lcd peripheral initialize - \param[in] none + \param[in] none \param[out] none \retval none */ @@ -37,15 +37,15 @@ void exmc_lcd_init(void) gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); - /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), + /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */ - gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | - GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - /* configure PE2(EXMC_A23) */ + /* configure PE2(EXMC_A23) */ gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); - + /* configure NOE and NWE */ gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); @@ -106,7 +106,7 @@ uint16_t lcd_register_read(uint8_t register_id) { uint16_t data; *(__IO uint16_t *) (BANK0_LCD_C)= register_id; - data = *(__IO uint16_t *) (BANK0_LCD_D); + data = *(__IO uint16_t *) (BANK0_LCD_D); return data; } @@ -154,13 +154,13 @@ void lcd_gram_write(uint16_t rgb_code) uint16_t lcd_gram_read(void) { uint16_t data; - + /* write GRAM register (R22h) */ *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022; /* dummy read (invalid data) */ - *(__IO uint16_t *) (BANK0_LCD_D); + *(__IO uint16_t *) (BANK0_LCD_D); - data = *(__IO uint16_t *) (BANK0_LCD_D); + data = *(__IO uint16_t *) (BANK0_LCD_D); return data; } @@ -219,7 +219,7 @@ void lcd_init(void) }else{ return; } - + for(i=50000;i>0;i--); } @@ -277,16 +277,16 @@ void lcd_point_set(uint16_t x,uint16_t y,uint16_t point) \param[in] x: the row-coordinate \param[in] y: the column-coordinate \param[out] none - \retval GRAM value of point + \retval GRAM value of point */ uint16_t lcd_point_get(uint16_t x,uint16_t y) { uint16_t data; - + if ((x > 240)||(y > 320)){ return 0; } - + lcd_cursor_set(x,y); data = lcd_gram_read(); @@ -410,7 +410,7 @@ void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t y = start_y; total = (end_x - start_x + 1) * (end_y - start_y + 1); - + for(i = 0; i < total; i ++){ /* set point according to the specified position and color */ lcd_point_set(x,y,*picturepointer++); @@ -441,7 +441,7 @@ void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_forma uint16_t i = 0, j = 0; uint8_t temp_char = 0; uint16_t temp_char_16 = 0; - + if(CHAR_FONT_8_16 == c_format.font){ /* 8x16 ASCII */ for (i = 0; i < 16; i++) { temp_char = ascii_8x16[((c - 0x20) * 16) + i]; diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h index 800a02c8c5..db76bc17d5 100644 --- a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h +++ b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h @@ -155,7 +155,7 @@ /* char format struct definitions */ typedef struct -{ +{ uint16_t font; /*!< the type of font */ uint16_t direction; /*!< the direction of char */ uint16_t char_color; /*!< the color of char */ diff --git a/bsp/gd32450z-eval/drivers/board.h b/bsp/gd32450z-eval/drivers/board.h index d6384ae820..49e9bf56c4 100644 --- a/bsp/gd32450z-eval/drivers/board.h +++ b/bsp/gd32450z-eval/drivers/board.h @@ -22,7 +22,7 @@ #define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ // <o> Internal SRAM memory size[Kbytes] <8-64> -// <i>Default: 64 +// <i>Default: 64 #ifdef __ICCARM__ // Use *.icf ram symbal, to avoid hardcode. extern char __ICFEDIT_region_RAM_end__; diff --git a/bsp/gd32450z-eval/drivers/drv_enet.c b/bsp/gd32450z-eval/drivers/drv_enet.c index b1bf632f54..66a6f9d516 100644 --- a/bsp/gd32450z-eval/drivers/drv_enet.c +++ b/bsp/gd32450z-eval/drivers/drv_enet.c @@ -35,16 +35,16 @@ //#define EMAC_TX_DUMP #ifdef EMAC_DEBUG -#define EMAC_TRACE rt_kprintf +#define EMAC_TRACE rt_kprintf #else #define EMAC_TRACE(...) #endif -#define EMAC_RXBUFNB 4 -#define EMAC_TXBUFNB 2 +#define EMAC_RXBUFNB 4 +#define EMAC_TXBUFNB 2 -#define EMAC_PHY_AUTO 0 -#define EMAC_PHY_10MBIT 1 +#define EMAC_PHY_AUTO 0 +#define EMAC_PHY_10MBIT 1 #define EMAC_PHY_100MBIT 2 #define MAX_ADDR_LEN 6 @@ -55,14 +55,14 @@ struct gd32_emac rt_uint8_t phy_mode; /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ struct rt_synopsys_eth * ETHERNET_MAC; IRQn_Type ETHER_MAC_IRQ; - + EMAC_DMADESCTypeDef *DMATxDescToSet; EMAC_DMADESCTypeDef *DMARxDescToGet; - + #pragma pack(4) EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB]; #pragma pack(4) @@ -71,7 +71,7 @@ struct gd32_emac rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE]; #pragma pack(4) rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE]; - + struct rt_semaphore tx_buf_free; }; @@ -548,14 +548,14 @@ static void enet_gpio_config(void) rcu_periph_clock_enable(RCU_GPIOG); rcu_periph_clock_enable(RCU_GPIOH); rcu_periph_clock_enable(RCU_GPIOI); - + gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8); gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8); gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8); - + /* enable SYSCFG clock */ rcu_periph_clock_enable(RCU_SYSCFG); - + /* choose DIV2 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */ rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4); syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII); @@ -563,31 +563,31 @@ static void enet_gpio_config(void) /* PA1: ETH_RMII_REF_CLK */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); - + /* PA2: ETH_MDIO */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2); gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2); - + /* PA7: ETH_RMII_CRS_DV */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7); - + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7); + gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1); gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2); gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7); - + /* PB11: ETH_RMII_TX_EN */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11); - + /* PB12: ETH_RMII_TXD0 */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12); gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_12); - + /* PB13: ETH_RMII_TXD1 */ gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13); - + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13); + gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11); gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12); gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13); @@ -599,11 +599,11 @@ static void enet_gpio_config(void) /* PC4: ETH_RMII_RXD0 */ gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4); - + /* PC5: ETH_RMII_RXD1 */ gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); - + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); + gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1); gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4); gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5); @@ -613,17 +613,17 @@ static void enet_gpio_config(void) int rt_hw_gd32_eth_init(void) { rt_kprintf("rt_gd32_eth_init...\n"); - + /* enable ethernet clock */ rcu_periph_clock_enable(RCU_ENET); rcu_periph_clock_enable(RCU_ENETTX); rcu_periph_clock_enable(RCU_ENETRX); - + nvic_configuration(); - + /* configure the GPIO ports for ethernet pins */ enet_gpio_config(); - + /* set autonegotiation mode */ gd32_emac_device0.phy_mode = EMAC_PHY_AUTO; gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0; @@ -638,16 +638,16 @@ int rt_hw_gd32_eth_init(void) gd32_emac_device0.dev_addr[4] = 0x34; gd32_emac_device0.dev_addr[5] = 0x56; - gd32_emac_device0.parent.parent.init = gd32_emac_init; - gd32_emac_device0.parent.parent.open = gd32_emac_open; - gd32_emac_device0.parent.parent.close = gd32_emac_close; - gd32_emac_device0.parent.parent.read = gd32_emac_read; - gd32_emac_device0.parent.parent.write = gd32_emac_write; - gd32_emac_device0.parent.parent.control = gd32_emac_control; + gd32_emac_device0.parent.parent.init = gd32_emac_init; + gd32_emac_device0.parent.parent.open = gd32_emac_open; + gd32_emac_device0.parent.parent.close = gd32_emac_close; + gd32_emac_device0.parent.parent.read = gd32_emac_read; + gd32_emac_device0.parent.parent.write = gd32_emac_write; + gd32_emac_device0.parent.parent.control = gd32_emac_control; gd32_emac_device0.parent.parent.user_data = RT_NULL; - gd32_emac_device0.parent.eth_rx = gd32_emac_rx; - gd32_emac_device0.parent.eth_tx = gd32_emac_tx; + gd32_emac_device0.parent.eth_rx = gd32_emac_rx; + gd32_emac_device0.parent.eth_tx = gd32_emac_tx; /* init tx buffer free semaphore */ rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO); diff --git a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c b/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c index 41355987b5..3fe8866dfb 100644 --- a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c +++ b/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c @@ -47,7 +47,7 @@ static void delay_1ms(volatile uint32_t count) /*! \brief sdram peripheral initialize - \param[in] sdram_device: specifie the SDRAM device + \param[in] sdram_device: specifie the SDRAM device \param[out] none \retval none */ @@ -71,7 +71,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) rcu_periph_clock_enable(RCU_GPIOH); /* common GPIO configuration */ - /* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */ + /* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */ gpio_af_set(GPIOC, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3); gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3); gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3); @@ -107,11 +107,11 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); /* A10(PG0),A11(PG1),A12(PG2),A14(PG4),A15(PG5),SDCLK(PG8),NCAS(PG15) pin configuration */ - gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | + gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15); - gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | + gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15); - gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | + gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15); /* specify which SDRAM to read and write */ @@ -126,7 +126,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) /* LMRD: 2 clock cycles */ sdram_timing_init_struct.load_mode_register_delay = 2; /* XSRD: min = 67ns */ - sdram_timing_init_struct.exit_selfrefresh_delay = 7; + sdram_timing_init_struct.exit_selfrefresh_delay = 7; /* RASD: min=42ns , max=120k (ns) */ sdram_timing_init_struct.row_address_select_delay = 5; /* ARFD: min=60ns */ @@ -144,9 +144,9 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) sdram_init_struct.row_address_width = EXMC_SDRAM_ROW_ADDRESS_13; sdram_init_struct.data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK; - sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK; + sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK; sdram_init_struct.write_protection = DISABLE; - sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK; + sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK; sdram_init_struct.brust_read_switch = ENABLE; sdram_init_struct.pipeline_read_delay = EXMC_PIPELINE_DELAY_1_HCLK; sdram_init_struct.timing = &sdram_timing_init_struct; @@ -158,7 +158,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) sdram_command_init_struct.bank_select = bank_select; sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; sdram_command_init_struct.mode_register_content = 0; - /* wait until the SDRAM controller is ready */ + /* wait until the SDRAM controller is ready */ while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ timeout--; } @@ -174,7 +174,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; sdram_command_init_struct.mode_register_content = 0; /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; + timeout = SDRAM_TIMEOUT; while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ timeout--; } @@ -186,8 +186,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) sdram_command_init_struct.bank_select = bank_select; sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_8_SDCLK; sdram_command_init_struct.mode_register_content = 0; - /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; + /* wait until the SDRAM controller is ready */ + timeout = SDRAM_TIMEOUT; while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ timeout--; } @@ -207,8 +207,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; sdram_command_init_struct.mode_register_content = command_content; - /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; + /* wait until the SDRAM controller is ready */ + timeout = SDRAM_TIMEOUT; while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ timeout--; } @@ -221,8 +221,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) /* (7.81 us * SDCLK_Freq) - 20 */ exmc_sdram_refresh_count_set(761); - /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; + /* wait until the SDRAM controller is ready */ + timeout = SDRAM_TIMEOUT; while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ timeout--; } @@ -258,20 +258,20 @@ void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t offset) void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writeaddr, uint32_t numbytetowrite) { uint32_t temp_addr; - + /* Select the base address according to EXMC_Bank */ if(sdram_device == EXMC_SDRAM_DEVICE0){ temp_addr = SDRAM_DEVICE0_ADDR; }else{ temp_addr = SDRAM_DEVICE1_ADDR; } - + /* While there is data to write */ for(; numbytetowrite != 0; numbytetowrite--) { /* Transfer data to the memory */ *(uint8_t *) (temp_addr + writeaddr) = *pbuffer++; - /* Increment the address*/ + /* Increment the address*/ writeaddr += 1; } } @@ -288,19 +288,19 @@ void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writea void sdram_readbuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t readaddr, uint32_t numbytetoread) { uint32_t temp_addr; - + /* select the base address according to EXMC_Bank */ if(sdram_device == EXMC_SDRAM_DEVICE0){ temp_addr = SDRAM_DEVICE0_ADDR; }else{ temp_addr = SDRAM_DEVICE1_ADDR; } - + /* while there is data to read */ for(; numbytetoread != 0; numbytetoread--){ /* read a byte from the memory */ *pbuffer++ = *(uint8_t*) (temp_addr + readaddr); - + /* increment the address */ readaddr += 1; } diff --git a/bsp/gd32450z-eval/drivers/drv_lcd.c b/bsp/gd32450z-eval/drivers/drv_lcd.c index 50d5c685c5..8f9e65c266 100644 --- a/bsp/gd32450z-eval/drivers/drv_lcd.c +++ b/bsp/gd32450z-eval/drivers/drv_lcd.c @@ -41,7 +41,7 @@ static struct rt_device_graphic_info _lcd_info; static struct rt_device lcd; /*! - \brief configure TLI GPIO + \brief configure TLI GPIO \param[in] none \param[out] none \retval none @@ -57,34 +57,34 @@ static void tli_gpio_config(void) rcu_periph_clock_enable(RCU_GPIOG); /* configure HSYNC(PC6), VSYNC(PA4), PCLK(PG7), DE(PF10) */ - /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0), + /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0), LCD_G7(PD3), LCD_G6(PC7), LCD_G5(PB11), LCD_G4(PB10), LCD_G3(PG10), LCD_G2(PA6), LCD_B7(PB9), LCD_B6(PB8), LCD_B5(PA3), LCD_B4(PG12), LCD_B3(PG11) */ - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3); gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_4); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8); - - gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0); - gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11); + gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8); + + gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0); + gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10); //gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8); + gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8); gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9); - - gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6); + + gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6); gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_7); - - gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3); - gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10); - - gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6); + gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3); + + gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10); + + gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6); gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_7); gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_10); - gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12); + gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11); + gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12); gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_6 |GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12); @@ -123,15 +123,15 @@ static void lcd_config(void) lcd_ctrl_line_config(); lcd_disable(); lcd_enable(); - + /* configure the GPIO of TLI */ tli_gpio_config(); /* configure the LCD_SPI */ - lcd_spi_config(); + lcd_spi_config(); /* power on the LCD */ //lcd_power_on(); - lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21 + lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21 } /*! @@ -144,7 +144,7 @@ static void tli_config(void) { tli_parameter_struct tli_init_struct; tli_layer_parameter_struct tli_layer_init_struct; - + rcu_periph_clock_enable(RCU_TLI); /* configure the PLLSAI clock to generate lcd clock */ @@ -156,52 +156,52 @@ static void tli_config(void) if(ERROR == rcu_osci_stab_wait(RCU_PLLSAI_CK)){ while(1); } - + /* TLI initialization */ tli_init_struct.signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; tli_init_struct.signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; tli_init_struct.signalpolarity_de = TLI_DE_ACTLIVE_LOW; tli_init_struct.signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; - + /* LCD display timing configuration */ tli_init_struct.synpsz_hpsz = LCD_480_320_HSYNC; tli_init_struct.synpsz_vpsz = LCD_480_320_VSYNC; - tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP; - tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP; + tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP; + tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP; tli_init_struct.activesz_hasz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP; tli_init_struct.activesz_vasz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP; - tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP; + tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP; tli_init_struct.totalsz_vtsz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP + LCD_480_320_VFP; - + /* LCD background color configure*/ tli_init_struct.backcolor_red = 0x00; tli_init_struct.backcolor_green = 0x00; - tli_init_struct.backcolor_blue = 0x00; + tli_init_struct.backcolor_blue = 0x00; tli_init(&tli_init_struct); - + lcd_framebuffer = rt_malloc(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH); RT_ASSERT(lcd_framebuffer != NULL); rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT); /* TLI layer0 configuration */ tli_layer_init_struct.layer_window_leftpos = tli_init_struct.backpsz_hbpsz + 1; - tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH; + tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH; tli_layer_init_struct.layer_window_toppos = tli_init_struct.backpsz_vbpsz + 1; tli_layer_init_struct.layer_window_bottompos = tli_init_struct.backpsz_vbpsz + RT_HW_LCD_HEIGHT; - + tli_layer_init_struct.layer_ppf = LAYER_PPF_RGB565; tli_layer_init_struct.layer_sa = 0xFF; - tli_layer_init_struct.layer_default_blue = 0x00; - tli_layer_init_struct.layer_default_green = 0x00; - tli_layer_init_struct.layer_default_red = 0x00; + tli_layer_init_struct.layer_default_blue = 0x00; + tli_layer_init_struct.layer_default_green = 0x00; + tli_layer_init_struct.layer_default_red = 0x00; tli_layer_init_struct.layer_default_alpha = 0x00; - tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA; + tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA; tli_layer_init_struct.layer_acf2 = LAYER_ACF2_PASA; - tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer; - tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3); + tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer; + tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3); tli_layer_init_struct.layer_frame_buf_stride_offset = (RT_HW_LCD_WIDTH * 2); - tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT; - + tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT; + tli_layer_init(LAYER0, &tli_layer_init_struct); } @@ -210,21 +210,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case RTGRAPHIC_CTRL_RECT_UPDATE: - { + { memcpy((void *)lcd_framebuffer, _rt_framebuffer, sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH); } break; - + case RTGRAPHIC_CTRL_POWERON: break; - + case RTGRAPHIC_CTRL_POWEROFF: break; - + case RTGRAPHIC_CTRL_GET_INFO: memcpy(args, &_lcd_info, sizeof(_lcd_info)); break; - + case RTGRAPHIC_CTRL_SET_MODE: break; } @@ -235,21 +235,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args) int gd32_hw_lcd_init(void) { _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT, 32); - if (_rt_framebuffer == RT_NULL) + if (_rt_framebuffer == RT_NULL) return -1; /* no memory yet */ - + lcd_config(); tli_config(); - tli_layer_enable(LAYER0); + tli_layer_enable(LAYER0); tli_reload_config(TLI_FRAME_BLANK_RELOAD_EN); tli_enable(); - + _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; _lcd_info.framebuffer = (void *)_rt_framebuffer; _lcd_info.width = RT_HW_LCD_WIDTH; _lcd_info.height = RT_HW_LCD_HEIGHT; - + lcd.type = RT_Device_Class_Graphic; lcd.init = NULL; lcd.open = NULL; @@ -258,10 +258,10 @@ int gd32_hw_lcd_init(void) lcd.write = NULL; lcd.control = rt_lcd_control; lcd.user_data = (void *)&_lcd_info; - + /* register lcd device to RT-Thread */ rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR); - + return 0; } INIT_DEVICE_EXPORT(gd32_hw_lcd_init); diff --git a/bsp/gd32450z-eval/drivers/drv_spi.c b/bsp/gd32450z-eval/drivers/drv_spi.c index f4e56e1a8c..a1fc143cf2 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi.c +++ b/bsp/gd32450z-eval/drivers/drv_spi.c @@ -11,7 +11,7 @@ * Date Author Notes * 2017-06-05 tanek first implementation. */ - + #include "drv_spi.h" #include <board.h> @@ -32,7 +32,7 @@ #ifdef DEBUG #define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) #else -#define DEBUG_PRINTF(...) +#define DEBUG_PRINTF(...) #endif /* private rt-thread spi ops function */ @@ -48,16 +48,16 @@ static struct rt_spi_ops gd32_spi_ops = static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) { - struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; + struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data; - + spi_parameter_struct spi_init_struct; uint32_t spi_periph = f4_spi->spi_periph; - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); /* data_width */ if(configuration->data_width <= 8) @@ -129,7 +129,7 @@ static rt_err_t configure(struct rt_spi_device* device, spi_init_struct.prescale = SPI_PSC_256; } } /* baudrate */ - + switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: @@ -137,15 +137,15 @@ static rt_err_t configure(struct rt_spi_device* device, break; case RT_SPI_MODE_1: spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; + break; case RT_SPI_MODE_2: spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; + break; case RT_SPI_MODE_3: spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; break; } - + /* MSB or LSB */ if(configuration->mode & RT_SPI_MSB) { @@ -155,18 +155,18 @@ static rt_err_t configure(struct rt_spi_device* device, { spi_init_struct.endian = SPI_ENDIAN_LSB; } - + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_init_struct.device_mode = SPI_MASTER; spi_init_struct.nss = SPI_NSS_SOFT; - + spi_crc_off(spi_periph); /* init SPI */ spi_init(spi_periph, &spi_init_struct); /* Enable SPI_MASTER */ - spi_enable(spi_periph); - + spi_enable(spi_periph); + return RT_EOK; }; @@ -178,9 +178,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data; uint32_t spi_periph = f4_spi->spi_periph; - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + /* take CS */ if(message->cs_take) { @@ -194,7 +194,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes const rt_uint8_t * send_ptr = message->send_buf; rt_uint8_t * recv_ptr = message->recv_buf; rt_uint32_t size = message->length; - + DEBUG_PRINTF("spi poll transfer start: %d\n", size); while(size--) @@ -205,12 +205,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes { data = *send_ptr++; } - + // Todo: replace register read/write by gd32f4 lib //Wait until the transmit buffer is empty while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); // Send the byte - spi_i2s_data_transmit(spi_periph, data); + spi_i2s_data_transmit(spi_periph, data); //Wait until a data is received while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); @@ -242,7 +242,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes //Wait until the transmit buffer is empty while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); // Send the byte - spi_i2s_data_transmit(spi_periph, data); + spi_i2s_data_transmit(spi_periph, data); //Wait until a data is received while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); @@ -260,7 +260,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes /* release CS */ if(message->cs_release) { - gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin); + gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin); DEBUG_PRINTF("spi release cs\n"); } @@ -274,7 +274,7 @@ static const struct gd32f4_spi spis[] = { #ifdef RT_USING_SPI0 {SPI0, RCU_SPI0, &spi_bus[0]}, #endif - + #ifdef RT_USING_SPI1 {SPI1, RCU_SPI1, &spi_bus[1]}, #endif @@ -286,11 +286,11 @@ static const struct gd32f4_spi spis[] = { #ifdef RT_USING_SPI3 {SPI3, RCU_SPI3, &spi_bus[3]}, #endif - + #ifdef RT_USING_SPI4 {SPI4, RCU_SPI4, &spi_bus[4]}, #endif - + #ifdef RT_USING_SPI5 {SPI5, RCU_SPI5, &spi_bus[5]}, #endif @@ -310,9 +310,9 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph, const char * spi_bus_name) { int i; - + RT_ASSERT(spi_bus_name != RT_NULL); - + for (i = 0; i < ARR_LEN(spis); i++) { if (spi_periph == spis[i].spi_periph) @@ -323,7 +323,7 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph, return RT_EOK; } } - + return RT_ERROR; } #endif diff --git a/bsp/gd32450z-eval/drivers/drv_spi.h b/bsp/gd32450z-eval/drivers/drv_spi.h index c97cbba880..692da41cbe 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi.h +++ b/bsp/gd32450z-eval/drivers/drv_spi.h @@ -36,7 +36,7 @@ struct gd32_spi_cs /* public function */ rt_err_t gd32_spi_bus_register(uint32_t spi_periph, - //struct gd32_spi_bus * gd32_spi, - const char * spi_bus_name); + //struct gd32_spi_bus * gd32_spi, + const char * spi_bus_name); #endif // gd32F20X_40X_SPI_H_INCLUDED diff --git a/bsp/gd32450z-eval/drivers/drv_spi_flash.c b/bsp/gd32450z-eval/drivers/drv_spi_flash.c index 9b60753472..1731d1499b 100644 --- a/bsp/gd32450z-eval/drivers/drv_spi_flash.c +++ b/bsp/gd32450z-eval/drivers/drv_spi_flash.c @@ -32,8 +32,8 @@ static int rt_hw_spi5_init(void) { /* register spi bus */ { - rt_err_t result; - + rt_err_t result; + rcu_periph_clock_enable(RCU_GPIOG); rcu_periph_clock_enable(RCU_SPI5); @@ -42,36 +42,36 @@ static int rt_hw_spi5_init(void) gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); - result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME); + result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME); if (result != RT_EOK) - { - return result; - } + { + return result; + } } /* attach cs */ { static struct rt_spi_device spi_device; static struct gd32_spi_cs spi_cs; - rt_err_t result; - + rt_err_t result; + spi_cs.GPIOx = GPIOG; spi_cs.GPIO_Pin = GPIO_PIN_9; - + /* SPI5_CS(PG9) GPIO pin configuration */ gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9); gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); - + gpio_bit_set(GPIOG,GPIO_PIN_9); result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs); - if (result != RT_EOK) - { - return result; - } + if (result != RT_EOK) + { + return result; + } } - return RT_EOK; + return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_spi5_init); @@ -83,7 +83,7 @@ static int rt_hw_spi_flash_with_sfud_init(void) return RT_ERROR; }; - return RT_EOK; + return RT_EOK; } INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init) #endif diff --git a/bsp/gd32450z-eval/drivers/drv_usart.c b/bsp/gd32450z-eval/drivers/drv_usart.c index 2b0b9c84b0..226c6fd121 100644 --- a/bsp/gd32450z-eval/drivers/drv_usart.c +++ b/bsp/gd32450z-eval/drivers/drv_usart.c @@ -37,7 +37,7 @@ struct gd32_uart { uint32_t uart_periph; //Todo: 3bits - IRQn_Type irqn; //Todo: 7bits + IRQn_Type irqn; //Todo: 7bits rcu_periph_enum per_clk; //Todo: 5bits rcu_periph_enum tx_gpio_clk; //Todo: 5bits rcu_periph_enum rx_gpio_clk; //Todo: 5bits @@ -48,7 +48,7 @@ struct gd32_uart uint16_t rx_af; //Todo: 4bits uint16_t rx_pin; //Todo: 4bits - struct rt_serial_device * serial; + struct rt_serial_device * serial; char *device_name; }; @@ -193,7 +193,7 @@ static const struct gd32_uart uarts[] = { "uart0", }, #endif - + #ifdef BSP_USING_UART1 { USART1, // uart peripheral index @@ -205,7 +205,7 @@ static const struct gd32_uart uarts[] = { "uart1", }, #endif - + #ifdef BSP_USING_UART2 { USART2, // uart peripheral index @@ -217,7 +217,7 @@ static const struct gd32_uart uarts[] = { "uart2", }, #endif - + #ifdef BSP_USING_UART3 { UART3, // uart peripheral index @@ -229,7 +229,7 @@ static const struct gd32_uart uarts[] = { "uart3", }, #endif - + #ifdef BSP_USING_UART4 { UART4, // uart peripheral index @@ -253,7 +253,7 @@ static const struct gd32_uart uarts[] = { "uart5", }, #endif - + #ifdef BSP_USING_UART6 { UART6, // uart peripheral index @@ -309,7 +309,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart) /* configure USART Rx as alternate function push-pull */ gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin); - + NVIC_SetPriority(uart->irqn, 0); NVIC_EnableIRQ(uart->irqn); } @@ -322,9 +322,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co RT_ASSERT(cfg != RT_NULL); uart = (struct gd32_uart *)serial->parent.user_data; - + gd32_uart_gpio_init(uart); - + usart_baudrate_set(uart->uart_periph, cfg->baud_rate); switch (cfg->data_bits) @@ -404,7 +404,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch) usart_data_transmit(uart->uart_periph, ch); while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - + return 1; } @@ -456,7 +456,7 @@ int gd32_hw_usart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; int i; - + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { uarts[i].serial->ops = &gd32_uart_ops; diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_eval.h b/bsp/gd32450z-eval/drivers/gd32f450z_eval.h index 73ea9baaa4..6eb91aee01 100644 --- a/bsp/gd32450z-eval/drivers/gd32f450z_eval.h +++ b/bsp/gd32450z-eval/drivers/gd32f450z_eval.h @@ -17,23 +17,23 @@ #endif #include "gd32f4xx.h" - + /* exported types */ -typedef enum +typedef enum { LED1 = 0, LED2 = 1, LED3 = 2 } led_typedef_enum; -typedef enum +typedef enum { KEY_WAKEUP = 0, KEY_TAMPER = 1, KEY_USER = 2 } key_typedef_enum; -typedef enum +typedef enum { KEY_MODE_GPIO = 0, KEY_MODE_EXTI = 1 @@ -45,11 +45,11 @@ typedef enum #define LED1_PIN GPIO_PIN_4 #define LED1_GPIO_PORT GPIOD #define LED1_GPIO_CLK RCU_GPIOD - + #define LED2_PIN GPIO_PIN_5 #define LED2_GPIO_PORT GPIOD #define LED2_GPIO_CLK RCU_GPIOD - + #define LED3_PIN GPIO_PIN_3 #define LED3_GPIO_PORT GPIOG #define LED3_GPIO_CLK RCU_GPIOG @@ -83,7 +83,7 @@ typedef enum #define WAKEUP_KEY_EXTI_LINE EXTI_0 #define WAKEUP_KEY_EXTI_PORT_SOURCE EXTI_SOURCE_GPIOA #define WAKEUP_KEY_EXTI_PIN_SOURCE EXTI_SOURCE_PIN0 -#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn +#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn /* user push-button */ #define USER_KEY_PIN GPIO_PIN_14 diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c index 8a309a1a75..b71005b6dd 100644 --- a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c +++ b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c @@ -108,8 +108,8 @@ void lcd_spi_config(void) gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13|GPIO_PIN_14); gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13|GPIO_PIN_14); spi_i2s_deinit(SPI5); - - if(0 == (SPI_CTL0(LCD_SPI) & SPI_CTL0_SPIEN)){ + + if(0 == (SPI_CTL0(LCD_SPI) & SPI_CTL0_SPIEN)){ spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_init_struct.device_mode = SPI_MASTER; spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; @@ -155,7 +155,7 @@ void lcd_data_write(uint8_t value) /* set LCD_RS to send data */ lcd_ctrl_line_set(LCD_RS_GPIO_PORT, LCD_RS_PIN); - /* reset LCD control line and send data */ + /* reset LCD control line and send data */ lcd_disable(); while(RESET == spi_i2s_flag_get(LCD_SPI, SPI_FLAG_TBE)) ; @@ -228,80 +228,80 @@ void lcd_power_on(void) } /** * @brief New Version 3.5" TFT RGB Hardware needs add this initilize funtion ---By xufei 2016.10.21 - Modified by GAO HAIYANG, test pass, 17, Nov, 2016 + Modified by GAO HAIYANG, test pass, 17, Nov, 2016 * @param None * @retval None */ void lcd_power_on3(void) { - lcd_command_write(0xC0);//power control1 command/w/ - lcd_data_write(0x0A); // P-Gamma level//4.1875v - lcd_data_write(0x0A); // N-Gamma level - lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/ - lcd_data_write(0x41); - lcd_data_write(0x07); // VCI1 = 2.5V - lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode - lcd_data_write(0x33); - lcd_command_write(0xC5);//VCOM control - lcd_data_write(0x00); //NV memory is not programmed - lcd_data_write(0x42); // VCM Setting - lcd_data_write(0x80); // VCM Register Enable - lcd_command_write(0xB0); //interface mode control //Polarity Setting - lcd_data_write(0x02); - lcd_command_write(0xB1);//frame rate control for normal mode - lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks - lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface - lcd_command_write(0xB4);//dispaly inversion control - lcd_data_write(0x00); // disable Z-inversion , column inversion - lcd_command_write(0xB6); //display function control// RM.DM Setting - lcd_data_write(0x70);////0xF0 - lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area - lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480 - lcd_command_write(0xB7); // Entry Mode - lcd_data_write(0x07); // disable low voltage detection, normal display, - lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting - lcd_data_write(0x36); - lcd_data_write(0xA5); - lcd_data_write(0xD3); - lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting - lcd_data_write(0x80); - lcd_command_write(0xE5); // Page 1 - lcd_data_write(0x01); - lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors - lcd_data_write(0x00); - lcd_command_write(0xE5); // Page 0 - lcd_data_write(0x00); - lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting - lcd_data_write(0x36); - lcd_data_write(0xA5); - lcd_data_write(0x53); - lcd_command_write(0xE0); // Gamma setting - //y fine adjustment register for positive polarity - lcd_data_write(0x00); - lcd_data_write(0x35); - lcd_data_write(0x33); - //y gradient adjustment register for positive polarity - lcd_data_write(0x00); - //y amplitude adjustment register for positive polarity - lcd_data_write(0x00); - lcd_data_write(0x00); - //y fine adjustment register for negative polarity - lcd_data_write(0x00); - lcd_data_write(0x35); - lcd_data_write(0x33); - //y gradient adjustment register for negative polarity - lcd_data_write(0x00); - //y amplitude adjustment register for negative polarity - lcd_data_write(0x00); - lcd_data_write(0x00); - lcd_command_write(0x36); // memory data access control // - lcd_data_write(0x48);// - lcd_command_write(0x3A); // interface pixel format setting - lcd_data_write(0x55);//16-bits - lcd_command_write(0x11); // Exit sleep mode - lcd_command_write(0x29); // Display on + lcd_command_write(0xC0);//power control1 command/w/ + lcd_data_write(0x0A); // P-Gamma level//4.1875v + lcd_data_write(0x0A); // N-Gamma level + lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/ + lcd_data_write(0x41); + lcd_data_write(0x07); // VCI1 = 2.5V + lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode + lcd_data_write(0x33); + lcd_command_write(0xC5);//VCOM control + lcd_data_write(0x00); //NV memory is not programmed + lcd_data_write(0x42); // VCM Setting + lcd_data_write(0x80); // VCM Register Enable + lcd_command_write(0xB0); //interface mode control //Polarity Setting + lcd_data_write(0x02); + lcd_command_write(0xB1);//frame rate control for normal mode + lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks + lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface + lcd_command_write(0xB4);//dispaly inversion control + lcd_data_write(0x00); // disable Z-inversion , column inversion + lcd_command_write(0xB6); //display function control// RM.DM Setting + lcd_data_write(0x70);////0xF0 + lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area + lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480 + lcd_command_write(0xB7); // Entry Mode + lcd_data_write(0x07); // disable low voltage detection, normal display, + lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting + lcd_data_write(0x36); + lcd_data_write(0xA5); + lcd_data_write(0xD3); + lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting + lcd_data_write(0x80); + lcd_command_write(0xE5); // Page 1 + lcd_data_write(0x01); + lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors + lcd_data_write(0x00); + lcd_command_write(0xE5); // Page 0 + lcd_data_write(0x00); + lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting + lcd_data_write(0x36); + lcd_data_write(0xA5); + lcd_data_write(0x53); + lcd_command_write(0xE0); // Gamma setting + //y fine adjustment register for positive polarity + lcd_data_write(0x00); + lcd_data_write(0x35); + lcd_data_write(0x33); + //y gradient adjustment register for positive polarity + lcd_data_write(0x00); + //y amplitude adjustment register for positive polarity + lcd_data_write(0x00); + lcd_data_write(0x00); + //y fine adjustment register for negative polarity + lcd_data_write(0x00); + lcd_data_write(0x35); + lcd_data_write(0x33); + //y gradient adjustment register for negative polarity + lcd_data_write(0x00); + //y amplitude adjustment register for negative polarity + lcd_data_write(0x00); + lcd_data_write(0x00); + lcd_command_write(0x36); // memory data access control // + lcd_data_write(0x48);// + lcd_command_write(0x3A); // interface pixel format setting + lcd_data_write(0x55);//16-bits + lcd_command_write(0x11); // Exit sleep mode + lcd_command_write(0x29); // Display on - delay(10); + delay(10); } /*! \brief insert a delay time diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h index 815925a170..00b7f51cb2 100644 --- a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h +++ b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h @@ -13,10 +13,10 @@ #define GD32F450Z_LCD_EVAL_H #include "gd32f450z_eval.h" - + #define LCD_CS_PIN GPIO_PIN_11 #define LCD_CS_GPIO_PORT GPIOD -#define LCD_CS_GPIO_CLK RCU_GPIOD +#define LCD_CS_GPIO_CLK RCU_GPIOD #define LCD_RS_PIN GPIO_PIN_3 #define LCD_RS_GPIO_PORT GPIOE @@ -28,7 +28,7 @@ #define LCD_SPI_MOSI_PIN GPIO_PIN_14 #define LCD_SPI_MOSI_GPIO_PORT GPIOG -#define LCD_SPI_MOSI_GPIO_CLK RCU_GPIOG +#define LCD_SPI_MOSI_GPIO_CLK RCU_GPIOG #define LCD_SPI SPI5 #define LCD_SPI_CLK RCU_SPI5 @@ -52,4 +52,4 @@ void lcd_data_write(uint8_t value); /* configure the LCD based on the power on sequence */ void lcd_power_on(void); void lcd_power_on3(void); -#endif /* GD32F450Z_LCD_EVAL_H */ +#endif /* GD32F450Z_LCD_EVAL_H */ diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.h b/bsp/gd32450z-eval/drivers/synopsys_emac.h index cb0d62122f..1610f19540 100644 --- a/bsp/gd32450z-eval/drivers/synopsys_emac.h +++ b/bsp/gd32450z-eval/drivers/synopsys_emac.h @@ -22,7 +22,7 @@ #define __SYNOPSYS_EMAC_H__ #include <rtthread.h> - + /******************************************************************************/ /* Ethernet MAC Registers bits definitions */ @@ -48,8 +48,8 @@ #define EMAC_MACCR_RD ((rt_uint32_t)0x00000200) /* Retry disable */ #define EMAC_MACCR_APCS ((rt_uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ #define EMAC_MACCR_BL ((rt_uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ -#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */ + a transmission attempt during retries after a collision: 0 =< r <2^k */ +#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */ #define EMAC_MACCR_BL_8 ((rt_uint32_t)0x00000020) /* k = min (n, 8) */ #define EMAC_MACCR_BL_4 ((rt_uint32_t)0x00000040) /* k = min (n, 4) */ #define EMAC_MACCR_BL_1 ((rt_uint32_t)0x00000060) /* k = min (n, 1) */ @@ -60,45 +60,45 @@ /* Bit definition for Ethernet MAC Frame Filter Register */ #define EMAC_MACFFR_RA ((rt_uint32_t)0x80000000) /* Receive all */ #define EMAC_MACFFR_HPF ((rt_uint32_t)0x00000400) /* Hash or perfect filter */ -#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */ +#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */ #define EMAC_MACFFR_SAIF ((rt_uint32_t)0x00000100) /* SA inverse filtering */ #define EMAC_MACFFR_PCF ((rt_uint32_t)0x000000C0) /* Pass control frames: 3 cases */ #define EMAC_MACFFR_PCF_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ #define EMAC_MACFFR_PCF_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ #define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ #define EMAC_MACFFR_BFD ((rt_uint32_t)0x00000020) /* Broadcast frame disable */ -#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */ +#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */ #define EMAC_MACFFR_DAIF ((rt_uint32_t)0x00000008) /* DA Inverse filtering */ -#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */ -#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */ -#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */ +#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */ +#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */ +#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */ /* Bit definition for Ethernet MAC Hash Table High Register */ -#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */ +#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */ /* Bit definition for Ethernet MAC Hash Table Low Register */ -#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */ +#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */ /* Bit definition for Ethernet MAC MII Address Register */ -#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */ -#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */ +#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */ +#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */ #define EMAC_MACMIIAR_CR_Div42 ((rt_uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ #define EMAC_MACMIIAR_CR_Div62 ((rt_uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ #define EMAC_MACMIIAR_CR_Div16 ((rt_uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define EMAC_MACMIIAR_CR_Div26 ((rt_uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ #define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010) /* HCLK:150-250 MHz; MDC clock= HCLK/102 */ #define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014) /* HCLK:250-300 MHz; MDC clock= HCLK/122*/ -#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */ -#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */ +#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */ +#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */ /* Bit definition for Ethernet MAC MII Data Register */ -#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ /* Bit definition for Ethernet MAC Flow Control Register */ -#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */ -#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */ +#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */ +#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */ #define EMAC_MACFCR_PLT_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */ #define EMAC_MACFCR_PLT_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */ #define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */ @@ -441,7 +441,7 @@ #define EMAC_DMACHRBAR_HRBAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ //typedef enum { -// RESET = 0, SET = !RESET +// RESET = 0, SET = !RESET //} FlagStatus, ITStatus; //typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; @@ -450,165 +450,165 @@ */ typedef struct { - /** - * MAC - */ - rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref EMAC_AutoNegotiation */ + /** + * MAC + */ + rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref EMAC_AutoNegotiation */ - rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref EMAC_watchdog */ + rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref EMAC_watchdog */ - rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref EMAC_Jabber */ + rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref EMAC_Jabber */ - rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission - This parameter can be a value of @ref EMAC_Inter_Frame_Gap */ + rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref EMAC_Inter_Frame_Gap */ - rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense - This parameter can be a value of @ref EMAC_Carrier_Sense */ + rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense + This parameter can be a value of @ref EMAC_Carrier_Sense */ - rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps - This parameter can be a value of @ref EMAC_Speed */ + rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref EMAC_Speed */ - rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode - This parameter can be a value of @ref EMAC_Receive_Own */ + rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref EMAC_Receive_Own */ - rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode - This parameter can be a value of @ref EMAC_Loop_Back_Mode */ + rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref EMAC_Loop_Back_Mode */ - rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref EMAC_Duplex_Mode */ + rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref EMAC_Duplex_Mode */ - rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref EMAC_Checksum_Offload */ + rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref EMAC_Checksum_Offload */ - rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a colision occurs (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Retry_Transmission */ + rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref EMAC_Retry_Transmission */ - rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping - This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */ + rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */ - rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value - This parameter can be a value of @ref EMAC_Back_Off_Limit */ + rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value + This parameter can be a value of @ref EMAC_Back_Off_Limit */ - rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Deferral_Check */ + rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref EMAC_Deferral_Check */ - rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) - This parameter can be a value of @ref EMAC_Receive_All */ + rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref EMAC_Receive_All */ - rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode - This parameter can be a value of @ref EMAC_Source_Addr_Filter */ + rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode + This parameter can be a value of @ref EMAC_Source_Addr_Filter */ - rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref EMAC_Pass_Control_Frames */ + rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref EMAC_Pass_Control_Frames */ - rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames - This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */ + rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */ - rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames - This parameter can be a value of @ref EMAC_Destination_Addr_Filter */ + rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref EMAC_Destination_Addr_Filter */ - rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode - This parameter can be a value of @ref EMAC_Promiscuous_Mode */ + rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode + This parameter can be a value of @ref EMAC_Promiscuous_Mode */ - rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */ + rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */ - rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */ + rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */ - rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ + rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ - rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ + rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ - rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the - transmit control frame */ + rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the + transmit control frame */ - rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames - This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */ + rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */ - rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame - This parameter can be a value of @ref EMAC_Pause_Low_Threshold */ + rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref EMAC_Pause_Low_Threshold */ - rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address) - This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */ + rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */ - rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref EMAC_Receive_Flow_Control */ + rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref EMAC_Receive_Flow_Control */ - rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Transmit_Flow_Control */ + rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref EMAC_Transmit_Flow_Control */ - rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering - This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */ + rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */ - rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ + rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ - /** - * DMA - */ + /** + * DMA + */ - rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames - This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */ + rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */ - rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode - This parameter can be a value of @ref EMAC_Receive_Store_Forward */ + rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode + This parameter can be a value of @ref EMAC_Receive_Store_Forward */ - rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames - This parameter can be a value of @ref EMAC_Flush_Received_Frame */ + rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames + This parameter can be a value of @ref EMAC_Flush_Received_Frame */ - rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode - This parameter can be a value of @ref EMAC_Transmit_Store_Forward */ + rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode + This parameter can be a value of @ref EMAC_Transmit_Store_Forward */ - rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control - This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */ + rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control + This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */ - rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames - This parameter can be a value of @ref EMAC_Forward_Error_Frames */ + rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref EMAC_Forward_Error_Frames */ - rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */ + rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */ - rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO - This parameter can be a value of @ref EMAC_Receive_Threshold_Control */ + rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref EMAC_Receive_Threshold_Control */ - rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref EMAC_Second_Frame_Operate */ + rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref EMAC_Second_Frame_Operate */ - rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats - This parameter can be a value of @ref EMAC_Address_Aligned_Beats */ + rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats + This parameter can be a value of @ref EMAC_Address_Aligned_Beats */ - rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers - This parameter can be a value of @ref EMAC_Fixed_Burst */ + rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref EMAC_Fixed_Burst */ - rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction - This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */ + rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */ - rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction - This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */ + rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */ - rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */ + rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */ - rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration - This parameter can be a value of @ref EMAC_DMA_Arbitration */ + rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref EMAC_DMA_Arbitration */ } EMAC_InitTypeDef; /**--------------------------------------------------------------------------**/ @@ -622,10 +622,10 @@ typedef struct */ typedef struct { - rt_uint32_t Status; /* Status */ - rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ - rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */ - rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ + rt_uint32_t Status; /* Status */ + rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */ + rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ } EMAC_DMADESCTypeDef; /**--------------------------------------------------------------------------**/ @@ -634,14 +634,14 @@ typedef struct */ /**--------------------------------------------------------------------------**/ -#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */ -#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define EMAC_CRC 4 /* Ethernet CRC */ -#define EMAC_EXTRA 2 /* Extra bytes in some cases */ -#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ -#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */ -#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */ -#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ +#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */ +#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define EMAC_CRC 4 /* Ethernet CRC */ +#define EMAC_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ /**--------------------------------------------------------------------------**/ /** @@ -1098,7 +1098,7 @@ struct rt_synopsys_eth volatile rt_uint32_t FCR; volatile rt_uint32_t VTR; rt_uint8_t RESERVED0[8]; - + volatile rt_uint32_t RWFFR; volatile rt_uint32_t PMTR; volatile rt_uint32_t LPICSR; diff --git a/bsp/gd32e230k-start/applications/main.c b/bsp/gd32e230k-start/applications/main.c index cabddf36d6..999becd329 100644 --- a/bsp/gd32e230k-start/applications/main.c +++ b/bsp/gd32e230k-start/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32e230k-start/drivers/board.c b/bsp/gd32e230k-start/drivers/board.c index ea91fd7eb8..5910ec4124 100644 --- a/bsp/gd32e230k-start/drivers/board.c +++ b/bsp/gd32e230k-start/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -75,7 +75,7 @@ void rt_hw_board_init() rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif -#ifdef RT_USING_HEAP +#ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif } diff --git a/bsp/gd32e230k-start/drivers/board.h b/bsp/gd32e230k-start/drivers/board.h index abc8743562..7d491aeaa8 100644 --- a/bsp/gd32e230k-start/drivers/board.h +++ b/bsp/gd32e230k-start/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,7 @@ #include <gd32e230.h> // <o> Internal SRAM memory size[Kbytes] <8-64> -// <i>Default: 64 +// <i>Default: 64 #ifdef __ICCARM__ // Use *.icf ram symbal, to avoid hardcode. extern char __ICFEDIT_region_RAM_end__; diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.c b/bsp/gd32e230k-start/drivers/drv_gpio.c index 4176798cfd..752f1489d7 100644 --- a/bsp/gd32e230k-start/drivers/drv_gpio.c +++ b/bsp/gd32e230k-start/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,8 +29,8 @@ struct pin_index rcu_periph_enum clk; rt_uint32_t gpio_periph; rt_uint32_t pin; - rt_uint32_t port_src; - rt_uint32_t pin_src; + rt_uint32_t port_src; + rt_uint32_t pin_src; }; static const struct pin_index pins[] = @@ -38,8 +38,8 @@ static const struct pin_index pins[] = __GD32_PIN_DEFAULT, __GD32_PIN(2, F, 0), __GD32_PIN(3, F, 1), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, + __GD32_PIN_DEFAULT, + __GD32_PIN_DEFAULT, __GD32_PIN(6, A, 0), __GD32_PIN(7, A, 1), __GD32_PIN(8, A, 2), @@ -51,7 +51,7 @@ static const struct pin_index pins[] = __GD32_PIN(14, B, 0), __GD32_PIN(15, B, 1), __GD32_PIN(16, B, 2), - __GD32_PIN_DEFAULT, + __GD32_PIN_DEFAULT, __GD32_PIN(18, A, 8), __GD32_PIN(19, A, 9), __GD32_PIN(20, A, 10), @@ -136,8 +136,8 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { const struct pin_index *index; rt_uint32_t pin_mode; - rt_uint32_t otype; - rt_uint32_t pull_up_down; + rt_uint32_t otype; + rt_uint32_t pull_up_down; index = get_pin(pin); if (index == RT_NULL) { @@ -147,9 +147,9 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) /* GPIO Periph clock enable */ rcu_periph_clock_enable(index->clk); pin_mode = GPIO_MODE_OUTPUT; - otype = GPIO_OTYPE_PP; - pull_up_down = GPIO_PUPD_NONE; - + otype = GPIO_OTYPE_PP; + pull_up_down = GPIO_PUPD_NONE; + switch(mode) { case PIN_MODE_OUTPUT: @@ -157,7 +157,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) break; case PIN_MODE_OUTPUT_OD: /* output setting: od. */ - otype = GPIO_OTYPE_OD; + otype = GPIO_OTYPE_OD; break; case PIN_MODE_INPUT: /* input setting: not pull. */ @@ -166,20 +166,20 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) case PIN_MODE_INPUT_PULLUP: /* input setting: pull up. */ pin_mode = GPIO_MODE_INPUT; - pull_up_down = GPIO_PUPD_PULLUP; + pull_up_down = GPIO_PUPD_PULLUP; break; case PIN_MODE_INPUT_PULLDOWN: /* input setting: pull down. */ - pin_mode = GPIO_MODE_INPUT; - pull_up_down = GPIO_PUPD_PULLDOWN; + pin_mode = GPIO_MODE_INPUT; + pull_up_down = GPIO_PUPD_PULLDOWN; break; default: break; } - gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin); + gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin); gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin); - + } void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) @@ -333,7 +333,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ return RT_EINVAL; } irqmap = &pin_irq_map[hdr_index]; - + switch (pin_irq_hdr_tab[hdr_index].mode) { case PIN_IRQ_MODE_RISING: @@ -354,14 +354,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_ /* enable and set interrupt priority */ nvic_irq_enable(irqmap->irqno, 5U); - + /* connect EXTI line to GPIO pin */ - syscfg_exti_line_config(index->port_src, index->pin_src); + syscfg_exti_line_config(index->port_src, index->pin_src); /* configure EXTI line */ exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - + rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) @@ -396,7 +396,7 @@ int rt_hw_pin_init(void) int result; result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); - + return result; } INIT_BOARD_EXPORT(rt_hw_pin_init); @@ -415,7 +415,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) { pin_irq_hdr(exti_line); exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } + } } void EXTI0_IRQHandler(void) { diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.h b/bsp/gd32e230k-start/drivers/drv_gpio.h index 3c758b2713..ae9bda7dce 100644 --- a/bsp/gd32e230k-start/drivers/drv_gpio.h +++ b/bsp/gd32e230k-start/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.c b/bsp/gd32e230k-start/drivers/drv_i2c.c index 57f49e4633..62cd4eb973 100644 --- a/bsp/gd32e230k-start/drivers/drv_i2c.c +++ b/bsp/gd32e230k-start/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -155,7 +155,7 @@ static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_u *p_buffer = i2c_data_receive(i2c_periph); /* point to the next location where the byte read will be saved */ - p_buffer++; + p_buffer++; /* decrement the read bytes counter */ data_byte--; @@ -264,7 +264,7 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg } } } - + ret = i; out: @@ -274,7 +274,7 @@ out: } static const struct rt_i2c_bus_device_ops i2c_ops = -{ +{ gd32_i2c_xfer, RT_NULL, RT_NULL @@ -311,7 +311,7 @@ int rt_hw_i2c_init(void) i2c_device.priv = (void *)&_i2c_bit_ops; rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); - } + } #else /* register hardware I2C */ diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.h b/bsp/gd32e230k-start/drivers/drv_i2c.h index 6e7de45260..c4b321594c 100644 --- a/bsp/gd32e230k-start/drivers/drv_i2c.h +++ b/bsp/gd32e230k-start/drivers/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32e230k-start/drivers/drv_spi.c b/bsp/gd32e230k-start/drivers/drv_spi.c index 706756d3de..8efc2a4664 100644 --- a/bsp/gd32e230k-start/drivers/drv_spi.c +++ b/bsp/gd32e230k-start/drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -115,7 +115,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat spi_init_struct.prescale = SPI_PSC_256; } } /* baudrate */ - + switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: @@ -131,7 +131,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; break; } - + /* MSB or LSB */ if(configuration->mode & RT_SPI_MSB) { @@ -141,7 +141,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat { spi_init_struct.endian = SPI_ENDIAN_LSB; } - + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_init_struct.device_mode = SPI_MASTER; spi_init_struct.nss = SPI_NSS_SOFT; @@ -177,7 +177,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes const rt_uint8_t * send_ptr = message->send_buf; rt_uint8_t * recv_ptr = message->recv_buf; rt_uint32_t size = message->length; - + DEBUG_PRINTF("spi poll transfer start: %d\n", size); while(size--) @@ -188,7 +188,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes { data = *send_ptr++; } - + // Todo: replace register read/write by gd32f3 lib //Wait until the transmit buffer is empty while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); diff --git a/bsp/gd32e230k-start/drivers/drv_spi.h b/bsp/gd32e230k-start/drivers/drv_spi.h index 01bafb9964..ba8e55916a 100644 --- a/bsp/gd32e230k-start/drivers/drv_spi.h +++ b/bsp/gd32e230k-start/drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32e230k-start/drivers/drv_usart.c b/bsp/gd32e230k-start/drivers/drv_usart.c index bf1f6b68a7..204ffa1ca1 100644 --- a/bsp/gd32e230k-start/drivers/drv_usart.c +++ b/bsp/gd32e230k-start/drivers/drv_usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ struct gd32_uart uint16_t tx_pin; uint32_t rx_port; uint32_t rx_af; - uint16_t rx_pin; + uint16_t rx_pin; struct rt_serial_device * serial; char *device_name; @@ -93,7 +93,7 @@ static const struct gd32_uart uarts[] = { "uart0", }, #endif - + #ifdef RT_USING_USART1 { USART1, // uart peripheral index @@ -122,18 +122,18 @@ void gd32_uart_gpio_init(struct gd32_uart *uart) /* enable USART clock */ rcu_periph_clock_enable(uart->tx_gpio_clk); rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); + rcu_periph_clock_enable(uart->per_clk); /* connect port to USARTx_Tx */ gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin); gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->tx_pin); gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->tx_pin); - + /* connect port to USARTx_Rx */ gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin); gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->rx_pin); gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->rx_pin); - + NVIC_SetPriority(uart->irqn, 0); NVIC_EnableIRQ(uart->irqn); } @@ -146,9 +146,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co RT_ASSERT(cfg != RT_NULL); uart = (struct gd32_uart *)serial->parent.user_data; - + gd32_uart_gpio_init(uart); - + usart_baudrate_set(uart->uart_periph, cfg->baud_rate); switch (cfg->data_bits) @@ -228,7 +228,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch) usart_data_transmit(uart->uart_periph, ch); while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - + return 1; } diff --git a/bsp/gd32e230k-start/drivers/drv_usart.h b/bsp/gd32e230k-start/drivers/drv_usart.h index 0fb15bee6f..4059092706 100644 --- a/bsp/gd32e230k-start/drivers/drv_usart.h +++ b/bsp/gd32e230k-start/drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32e230k-start/drivers/gd32e230_libopt.h b/bsp/gd32e230k-start/drivers/gd32e230_libopt.h index 61010d794f..767e929d8f 100644 --- a/bsp/gd32e230k-start/drivers/gd32e230_libopt.h +++ b/bsp/gd32e230k-start/drivers/gd32e230_libopt.h @@ -1,7 +1,7 @@ /*! \file gd32e230_libopt.h \brief library optional for gd32e230 - + \version 2018-06-19, V1.0.0, firmware for GD32E230 */ @@ -10,27 +10,27 @@ All rights reserved. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32vf103v-eval/applications/main.c b/bsp/gd32vf103v-eval/applications/main.c index c411937c18..9d7d2edafe 100644 --- a/bsp/gd32vf103v-eval/applications/main.c +++ b/bsp/gd32vf103v-eval/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32vf103v-eval/board/board.c b/bsp/gd32vf103v-eval/board/board.c index de2907c79b..5df6fa722f 100644 --- a/bsp/gd32vf103v-eval/board/board.c +++ b/bsp/gd32vf103v-eval/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32vf103v-eval/board/board.h b/bsp/gd32vf103v-eval/board/board.h index 422634fc38..860d71698b 100644 --- a/bsp/gd32vf103v-eval/board/board.h +++ b/bsp/gd32vf103v-eval/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h b/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h index ca292d2659..58ef886900 100644 --- a/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h +++ b/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h @@ -8,27 +8,27 @@ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.c b/bsp/gd32vf103v-eval/drivers/drv_gpio.c index 95393cd4f2..ca56bf54a2 100644 --- a/bsp/gd32vf103v-eval/drivers/drv_gpio.c +++ b/bsp/gd32vf103v-eval/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,7 @@ #define EXTI_(x) BIT(x) -static const struct pin_index pins[] = +static const struct pin_index pins[] = { #if defined(GPIOA) __GD32VF_PIN(0 , A, 0 ), @@ -126,7 +126,7 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_PIN_12, EXTI10_15_IRQn}, {GPIO_PIN_13, EXTI10_15_IRQn}, {GPIO_PIN_14, EXTI10_15_IRQn}, - {GPIO_PIN_15, EXTI10_15_IRQn}, + {GPIO_PIN_15, EXTI10_15_IRQn}, }; static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = @@ -406,11 +406,11 @@ static rt_err_t gd32vf_pin_irq_enable(struct rt_device *device, rt_base_t pin, gpio_bit_reset(index->gpio_periph, index->pin); pin_irq_enable_mask &= ~irqmap->pinbit; - + eclic_irq_disable(irqmap->irqno); exti_interrupt_flag_clear(EXTI_(index->pin)); - - rt_hw_interrupt_enable(level); + + rt_hw_interrupt_enable(level); } else { diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.h b/bsp/gd32vf103v-eval/drivers/drv_gpio.h index ccb8ea92a3..af1094e97d 100644 --- a/bsp/gd32vf103v-eval/drivers/drv_gpio.h +++ b/bsp/gd32vf103v-eval/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,4 +38,4 @@ int rt_hw_gpio_init(void); #endif /* __DRV_GPIO__H__ */ -/******************* end of file *******************/
\ No newline at end of file +/******************* end of file *******************/ diff --git a/bsp/gd32vf103v-eval/drivers/drv_usart.c b/bsp/gd32vf103v-eval/drivers/drv_usart.c index 9a15eca933..313440329c 100644 --- a/bsp/gd32vf103v-eval/drivers/drv_usart.c +++ b/bsp/gd32vf103v-eval/drivers/drv_usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,7 @@ #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \ && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) #error "Please define at least one BSP_USING_UARTx" - /* this driver can be disabled at menuconfig �� RT-Thread Components �� Device Drivers */ + /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ #endif struct gd32_usart { diff --git a/bsp/maxim/MAX32660_EVSYS/board/board.c b/bsp/maxim/MAX32660_EVSYS/board/board.c index 5bc5a5f679..d34b786c98 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/board.c +++ b/bsp/maxim/MAX32660_EVSYS/board/board.c @@ -66,3 +66,16 @@ void rt_hw_board_init(void) #endif } +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + do + { + now = SysTick->VAL; + delta = start >= now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} diff --git a/bsp/maxim/MAX32660_EVSYS/rtconfig.py b/bsp/maxim/MAX32660_EVSYS/rtconfig.py index 70faf43ff9..48273268f4 100644 --- a/bsp/maxim/MAX32660_EVSYS/rtconfig.py +++ b/bsp/maxim/MAX32660_EVSYS/rtconfig.py @@ -62,6 +62,7 @@ if PLATFORM == 'gcc': elif PLATFORM == 'armcc': # toolchains CC = 'armcc' + CXX = 'armcc' AS = 'armasm' AR = 'armar' LINK = 'armlink' diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c index 3e58cb7c54..2b8a4e1b3e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c @@ -9,6 +9,7 @@ * 2019-3-2 jinsheng add Macro judgment * 2020-1-6 duminmin support single bank mode * 2020-5-17 yufanyufan77 support support H7 + * 2021-3-3 zhuyf233 fix some bugs */ #include "board.h" @@ -24,110 +25,6 @@ //#define DRV_DEBUG #define LOG_TAG "drv.flash" #include <drv_log.h> -#define ADDR_FLASH_SECTOR_0 ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_1 ((rt_uint32_t)0x08020000) /* Base address of Sector 1, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_2 ((rt_uint32_t)0x08040000) /* Base address of Sector 2, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_3 ((rt_uint32_t)0x08060000) /* Base address of Sector 3, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_4 ((rt_uint32_t)0x08080000) /* Base address of Sector 4, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_5 ((rt_uint32_t)0x080A0000) /* Base address of Sector 5, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_6 ((rt_uint32_t)0x080C0000) /* Base address of Sector 6, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_7 ((rt_uint32_t)0x080E0000) /* Base address of Sector 7, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_8 ((rt_uint32_t)0x08100000) /* Base address of Sector 8, 128 Kbytes */ - -#define FLASH_SECTOR_0 0U /* Sector Number 0 */ -#define FLASH_SECTOR_1 1U /* Sector Number 1 */ -#define FLASH_SECTOR_2 2U /* Sector Number 2 */ -#define FLASH_SECTOR_3 3U /* Sector Number 3 */ -#define FLASH_SECTOR_4 4U /* Sector Number 4 */ -#define FLASH_SECTOR_5 5U /* Sector Number 5 */ -#define FLASH_SECTOR_6 6U /* Sector Number 6 */ -#define FLASH_SECTOR_7 7U /* Sector Number 7 */ -/** - * @brief Gets the sector of a given address - * @param addr flash address - * @param flash bank - * @param flash sector - * @retval The sector of a given address - */ -static void GetSector(rt_uint32_t Address,uint32_t* bank,uint32_t* sector) -{ -#if defined (FLASH_OPTCR_nDBANK) - FLASH_OBProgramInitTypeDef OBInit; - uint32_t nbank = 0; - - /* get duel bank ability:nDBANK(Bit29) */ - HAL_FLASHEx_OBGetConfig(&OBInit); - nbank = ((OBInit.USERConfig & 0x20000000U) >> 29); - /* 1:single bank mode */ - if (1 == nbank) - { - if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0)) - { - sector = FLASH_SECTOR_0; - } - else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1)) - { - sector = FLASH_SECTOR_1; - } - else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2)) - { - sector = FLASH_SECTOR_2; - } - else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3)) - { - sector = FLASH_SECTOR_3; - } - else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4)) - { - sector = FLASH_SECTOR_4; - } - else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5)) - { - sector = FLASH_SECTOR_5; - } - else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6)) - { - sector = FLASH_SECTOR_6; - } - else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7)) - { - sector = FLASH_SECTOR_7; - } - else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8)) - { - sector = FLASH_SECTOR_8; - } - else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9)) - { - sector = FLASH_SECTOR_9; - } - else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10)) - { - sector = FLASH_SECTOR_10; - } - else - { - sector = FLASH_SECTOR_11; - } - } - else /* 0:dual bank mode */ - { - LOG_E("rtthread doesn't support duel bank mode yet!"); - RT_ASSERT(0); - } -#else /* no dual bank ability */ - *sector = (Address&0xffffff)/FLASH_SIZE_GRANULARITY_128K; - if(*sector>7) - { - *bank = FLASH_BANK_1; - *sector = *sector/2; - } - else - { - *bank = FLASH_BANK_2; - } -#endif -} /** * Read data from flash. @@ -137,16 +34,16 @@ static void GetSector(rt_uint32_t Address,uint32_t* bank,uint32_t* sector) * @param buf buffer to store read data * @param size read bytes size * - * @return result + * @retval The length of bytes that have been read */ int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) { size_t i; - if ((addr + size) > STM32_FLASH_END_ADDRESS) + if ((addr + size - 1) > FLASH_END) { LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size)); - return -1; + return -RT_ERROR; } for (i = 0; i < size; i++, buf++, addr++) @@ -166,47 +63,68 @@ int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) * @param buf the write data buffer * @param size write bytes size * - * @return result + * @return The length of bytes that have been written */ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) { rt_err_t result = RT_EOK; - rt_uint32_t end_addr = addr + size; - rt_uint32_t bank = addr/ADDR_FLASH_SECTOR_8;; + rt_uint32_t end_addr = addr + size - 1, write_addr; + rt_uint32_t write_granularity = FLASH_NB_32BITWORD_IN_FLASHWORD * 4; + rt_uint32_t write_size = write_granularity; + rt_uint8_t write_buffer[32] = {0}; - if ((end_addr) > STM32_FLASH_END_ADDRESS) + if ((end_addr) > FLASH_END) { LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size)); return -RT_EINVAL; } + + if(addr % 32 != 0) + { + LOG_E("write addr must be 32-byte alignment"); + return -RT_EINVAL; + } if (size < 1) { return -RT_EINVAL; } - /* Unlock the Flash to enable the flash control register access */ HAL_FLASH_Unlock(); - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR ); - - for (size_t i = 0; i < size/32; i++, addr+=32, buf+=32) + write_addr = (uint32_t)buf; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR); + while (addr < end_addr) { - /* write data to flash */ - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, addr, (uint64_t)((uint32_t)buf)) == HAL_OK) + if(end_addr - addr + 1 < write_granularity) { - if (*(rt_uint8_t *)addr != *buf) + write_size = end_addr - addr + 1; + for(size_t i = 0; i < write_size; i++) { - result = -RT_ERROR; - break; + write_buffer[i] = *((uint8_t *)(write_addr + i)); } + write_addr = (uint32_t)((rt_uint32_t *)write_buffer); + } + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, addr, write_addr) == HAL_OK) + { + for(rt_uint8_t i = 0; i < write_size; i++) + { + if (*(rt_uint8_t *)(addr + i) != *(rt_uint8_t *)(write_addr + i)) + { + result = -RT_ERROR; + goto __exit; + } + } + addr += write_granularity; + write_addr += write_granularity; } else { result = -RT_ERROR; - break; + goto __exit; } } +__exit: HAL_FLASH_Lock(); if (result != RT_EOK) @@ -230,42 +148,74 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) int stm32_flash_erase(rt_uint32_t addr, size_t size) { rt_err_t result = RT_EOK; - rt_uint32_t FirstSector = 0, NbOfSectors = 0; rt_uint32_t SECTORError = 0; - rt_uint32_t bank = 0; - if ((addr + size) > STM32_FLASH_END_ADDRESS) + if ((addr + size - 1) > FLASH_END) { LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size)); return -RT_EINVAL; } + rt_uint32_t addr_bank1 = 0; + rt_uint32_t size_bank1 = 0; + rt_uint32_t addr_bank2 = 0; + rt_uint32_t size_bank2 = 0; + + if((addr + size) < FLASH_BANK2_BASE) + { + addr_bank1 = addr; + size_bank1 = size; + size_bank2 = 0; + } + else if(addr >= FLASH_BANK2_BASE) + { + size_bank1 = 0; + addr_bank2 = addr; + size_bank2 = size; + } + else + { + addr_bank1 = addr; + size_bank1 = FLASH_BANK2_BASE - addr_bank1; + addr_bank2 = FLASH_BANK2_BASE; + size_bank2 = addr + size - FLASH_BANK2_BASE; + } + /*Variable used for Erase procedure*/ FLASH_EraseInitTypeDef EraseInitStruct; - /* Unlock the Flash to enable the flash control register access */ HAL_FLASH_Unlock(); - - /* Get the 1st sector to erase */ - GetSector(addr,&bank,&FirstSector); - /* Get the number of sector to erase from 1st sector */ - GetSector(addr + size,0,&NbOfSectors); - NbOfSectors = NbOfSectors - FirstSector + 1; - /* Fill EraseInit structure */ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; - EraseInitStruct.Sector = FirstSector; - EraseInitStruct.NbSectors = NbOfSectors; - EraseInitStruct.Banks = bank; + SCB_DisableDCache(); + + if(size_bank1) + { + EraseInitStruct.Sector = (addr_bank1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE; + EraseInitStruct.NbSectors = (addr_bank1 + size_bank1 -1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE - EraseInitStruct.Sector + 1; + EraseInitStruct.Banks = FLASH_BANK_1; + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK) + { + result = -RT_ERROR; + goto __exit; + } + } - if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK) + if(size_bank2) { - result = -RT_ERROR; - goto __exit; + EraseInitStruct.Sector = (addr_bank2 - FLASH_BANK2_BASE) / FLASH_SECTOR_SIZE; + EraseInitStruct.NbSectors = (addr_bank2 + size_bank2 -1 - FLASH_BANK2_BASE) / FLASH_SECTOR_SIZE - EraseInitStruct.Sector + 1; + EraseInitStruct.Banks = FLASH_BANK_2; + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK) + { + result = -RT_ERROR; + goto __exit; + } } __exit: + SCB_EnableDCache(); HAL_FLASH_Lock(); if (result != RT_EOK) diff --git a/bsp/w60x/drivers/board.c b/bsp/w60x/drivers/board.c index e4e2ccde47..188c698ba9 100644 --- a/bsp/w60x/drivers/board.c +++ b/bsp/w60x/drivers/board.c @@ -98,14 +98,14 @@ void disp_version_info(void) void wm_gpio_config(void) { - /* must call first */ - wm_gpio_af_disable(); + /* must call first */ + wm_gpio_af_disable(); - /*MASTER SPI configuratioin*/ - wm_spi_cs_config(WM_IO_PA_02); - wm_spi_ck_config(WM_IO_PA_11); - wm_spi_di_config(WM_IO_PA_03); - wm_spi_do_config(WM_IO_PA_09); + /*MASTER SPI configuratioin*/ + wm_spi_cs_config(WM_IO_PA_02); + wm_spi_ck_config(WM_IO_PA_11); + wm_spi_di_config(WM_IO_PA_03); + wm_spi_do_config(WM_IO_PA_09); } static int wm_infsl_init(void) diff --git a/bsp/w60x/drivers/drv_crypto.c b/bsp/w60x/drivers/drv_crypto.c index 4335e42b50..1e0db82cde 100644 --- a/bsp/w60x/drivers/drv_crypto.c +++ b/bsp/w60x/drivers/drv_crypto.c @@ -465,25 +465,25 @@ static rt_err_t _bignum_exptmod(struct hwcrypto_bignum *bignum_ctx, const struct hw_bignum_mpi *b, const struct hw_bignum_mpi *c) { - pstm_int pa, pb, pm, pres; + pstm_int pa, pb, pm, pres; u32 * buff_a = NULL; - u32 * buff_b = NULL; - u32 * buff_m = NULL; - int err = -1; + u32 * buff_b = NULL; + u32 * buff_m = NULL; + int err = -1; void *buff; int buff_len; pstm_init(NULL, &pres); buff_a = tls_mem_alloc(a->total); - if(buff_a == NULL) - goto out; - buff_b = tls_mem_alloc(b->total); - if(buff_b == NULL) - goto out; - buff_m = tls_mem_alloc(c->total); - if(buff_m == NULL) - goto out; + if(buff_a == NULL) + goto out; + buff_b = tls_mem_alloc(b->total); + if(buff_b == NULL) + goto out; + buff_m = tls_mem_alloc(c->total); + if(buff_m == NULL) + goto out; memset(buff_a, 0, a->total); memset(buff_b, 0, b->total); @@ -494,29 +494,29 @@ static rt_err_t _bignum_exptmod(struct hwcrypto_bignum *bignum_ctx, memcpy(buff_m, c->p, c->total); pstm_reverse((unsigned char *)buff_a, a->total); - pstm_reverse((unsigned char *)buff_b, b->total); - pstm_reverse((unsigned char *)buff_m, c->total); + pstm_reverse((unsigned char *)buff_b, b->total); + pstm_reverse((unsigned char *)buff_m, c->total); // *((volatile unsigned int *)0x40000710) = *((volatile unsigned int *)0x40000710) | (0x1 << 28); - if ((err = pstm_init_for_read_unsigned_bin(NULL, &pa, a->total)) != PS_SUCCESS){ - goto out; - } - if ((err = pstm_read_unsigned_bin(&pa, (unsigned char *)buff_a, a->total)) != PS_SUCCESS) { - goto out; - } - if ((err = pstm_init_for_read_unsigned_bin(NULL, &pb, b->total)) != PS_SUCCESS){ - goto out; - } - if ((err = pstm_read_unsigned_bin(&pb, (unsigned char *)buff_b, b->total)) != PS_SUCCESS) { - goto out; - } - if ((err = pstm_init_for_read_unsigned_bin(NULL, &pm, c->total)) != PS_SUCCESS){ - goto out; - } - if ((err = pstm_read_unsigned_bin(&pm, (unsigned char *)buff_m, c->total)) != PS_SUCCESS) { - goto out; - } + if ((err = pstm_init_for_read_unsigned_bin(NULL, &pa, a->total)) != PS_SUCCESS){ + goto out; + } + if ((err = pstm_read_unsigned_bin(&pa, (unsigned char *)buff_a, a->total)) != PS_SUCCESS) { + goto out; + } + if ((err = pstm_init_for_read_unsigned_bin(NULL, &pb, b->total)) != PS_SUCCESS){ + goto out; + } + if ((err = pstm_read_unsigned_bin(&pb, (unsigned char *)buff_b, b->total)) != PS_SUCCESS) { + goto out; + } + if ((err = pstm_init_for_read_unsigned_bin(NULL, &pm, c->total)) != PS_SUCCESS){ + goto out; + } + if ((err = pstm_read_unsigned_bin(&pm, (unsigned char *)buff_m, c->total)) != PS_SUCCESS) { + goto out; + } tls_crypto_exptmod(&pa, &pb, &pm, &pres); buff_len = pstm_unsigned_bin_size(&pres); @@ -528,16 +528,16 @@ static rt_err_t _bignum_exptmod(struct hwcrypto_bignum *bignum_ctx, out: if(buff_a) - tls_mem_free(buff_a); - if(buff_b) - tls_mem_free(buff_b); - if(buff_m) - tls_mem_free(buff_m); + tls_mem_free(buff_a); + if(buff_b) + tls_mem_free(buff_b); + if(buff_m) + tls_mem_free(buff_m); - pstm_clear(&pa); - pstm_clear(&pb); - pstm_clear(&pm); - pstm_clear(&pres); + pstm_clear(&pa); + pstm_clear(&pb); + pstm_clear(&pm); + pstm_clear(&pres); if (a->sign < 0) { @@ -583,7 +583,7 @@ static const struct hwcrypto_crc_ops crc_ops = .update = _crc_update, }; -static const struct hwcrypto_bignum_ops bignum_ops = +static const struct hwcrypto_bignum_ops bignum_ops = { .add = RT_NULL, .sub = RT_NULL, @@ -722,7 +722,7 @@ int wm_hw_crypto_device_init(void) _crypto_dev.dev.ops = &_ops; _crypto_dev.dev.id = 0; - rt_memcpy(&_crypto_dev.dev.id, wpa_supplicant_get_mac(), + rt_memcpy(&_crypto_dev.dev.id, wpa_supplicant_get_mac(), sizeof(_crypto_dev.dev.id) > 6 ? 6 : sizeof(_crypto_dev.dev.id)); _crypto_dev.dev.user_data = &_crypto_dev; diff --git a/bsp/w60x/drivers/drv_rtc.c b/bsp/w60x/drivers/drv_rtc.c index fa0aee498c..38da5aec58 100644 --- a/bsp/w60x/drivers/drv_rtc.c +++ b/bsp/w60x/drivers/drv_rtc.c @@ -172,7 +172,7 @@ static rt_size_t wm_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops _ops = +const static struct rt_device_ops _ops = { .init = wm_rtc_init, .open = wm_rtc_open, diff --git a/bsp/w60x/drivers/drv_soft_i2c.c b/bsp/w60x/drivers/drv_soft_i2c.c index b2e0b5b508..1e44d52662 100644 --- a/bsp/w60x/drivers/drv_soft_i2c.c +++ b/bsp/w60x/drivers/drv_soft_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -198,8 +198,8 @@ int rt_soft_i2c_init(void) w60x_i2c_bus_unlock(&soft_i2c_config[i]); LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, soft_i2c_config[i].sda); } diff --git a/bsp/w60x/drivers/drv_soft_i2c.h b/bsp/w60x/drivers/drv_soft_i2c.h index ee50abea71..9901a5958f 100644 --- a/bsp/w60x/drivers/drv_soft_i2c.h +++ b/bsp/w60x/drivers/drv_soft_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/w60x/drivers/drv_standby.c b/bsp/w60x/drivers/drv_standby.c index 1c3de4bc3a..dfe699bf32 100644 --- a/bsp/w60x/drivers/drv_standby.c +++ b/bsp/w60x/drivers/drv_standby.c @@ -33,7 +33,7 @@ extern void standby_idr(void); #if (1 == GCC_COMPILE) void wm_pm_standby(void) { - __asm volatile ( + __asm volatile ( " cpsid i \n" /* disable irq*/ " dsb \n" " ldr r0, =0X499 \n" @@ -76,7 +76,7 @@ void sys_start_standby(int ms) { return; } - tls_irq_enable(PMU_GPIO_WAKEUP_INT); //Open interrupt by default to clear the interrupt flag for IO wake-up + tls_irq_enable(PMU_GPIO_WAKEUP_INT); //Open interrupt by default to clear the interrupt flag for IO wake-up val = tls_reg_read32(HR_PMU_PS_CR); val |= 0x01; tls_reg_write32(HR_PMU_PS_CR, val); diff --git a/bsp/w60x/drivers/drv_uart.c b/bsp/w60x/drivers/drv_uart.c index 6a3c4c40fc..e2c0f0d192 100644 --- a/bsp/w60x/drivers/drv_uart.c +++ b/bsp/w60x/drivers/drv_uart.c @@ -208,7 +208,7 @@ static int wm_uart_flow_ctrl_set(TLS_UART_REGS_T *UARTx, TLS_UART_FLOW_CTRL_MODE case TLS_UART_FLOW_CTRL_HARDWARE: UARTx->UR_FC = (1UL << 0) | (6UL << 2); - break; + break; default: break; diff --git a/bsp/w60x/drivers/pin_config.h b/bsp/w60x/drivers/pin_config.h index cf1eb774c3..c704fafb22 100644 --- a/bsp/w60x/drivers/pin_config.h +++ b/bsp/w60x/drivers/pin_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/w60x/oneshot/oneshot.c b/bsp/w60x/oneshot/oneshot.c index ee60a0b907..21beeeb90d 100644 --- a/bsp/w60x/oneshot/oneshot.c +++ b/bsp/w60x/oneshot/oneshot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,37 +16,37 @@ /* start oneshot */ int wm_oneshot_start(WM_ONESHOT_MODE mode, wm_oneshot_callback callback) { - tls_wifi_oneshot_callback_register(callback); - if(mode == WM_UDP) - { - tls_wifi_set_oneshot_config_mode(0); - } + tls_wifi_oneshot_callback_register(callback); + if(mode == WM_UDP) + { + tls_wifi_set_oneshot_config_mode(0); + } else if (mode == WM_APSOCKET) { tls_wifi_set_oneshot_config_mode(1); - } - else if(mode == WM_APWEB) - { - tls_wifi_set_oneshot_config_mode(2); - } - else - { - return -1; - } - tls_wifi_set_oneshot_flag(1); - return 0; + } + else if(mode == WM_APWEB) + { + tls_wifi_set_oneshot_config_mode(2); + } + else + { + return -1; + } + tls_wifi_set_oneshot_flag(1); + return 0; } /* stop oneshot */ int wm_oneshot_stop(void) { - tls_wifi_oneshot_callback_delete(); - tls_wifi_set_oneshot_flag(0); - return 0; + tls_wifi_oneshot_callback_delete(); + tls_wifi_set_oneshot_flag(0); + return 0; } /* get status */ int wm_oneshot_get(void) { - return tls_wifi_get_oneshot_flag(); + return tls_wifi_get_oneshot_flag(); } diff --git a/bsp/w60x/oneshot/oneshot.h b/bsp/w60x/oneshot/oneshot.h index f9bd638c1a..26f25d0735 100644 --- a/bsp/w60x/oneshot/oneshot.h +++ b/bsp/w60x/oneshot/oneshot.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,9 +12,9 @@ #define DRV_ONESHOT_H__ typedef enum{ - WM_UDP, + WM_UDP, WM_APSOCKET, - WM_APWEB + WM_APWEB }WM_ONESHOT_MODE; diff --git a/bsp/w60x/oneshot/oneshot_demo.c b/bsp/w60x/oneshot/oneshot_demo.c index 7012b5af5b..b40e121f16 100644 --- a/bsp/w60x/oneshot/oneshot_demo.c +++ b/bsp/w60x/oneshot/oneshot_demo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/x86/drivers/console.c b/bsp/x86/drivers/console.c index b783872bae..4fe1daeeed 100644 --- a/bsp/x86/drivers/console.c +++ b/bsp/x86/drivers/console.c @@ -87,7 +87,7 @@ static void rt_cga_putc(int c) break; case '\n': crt_pos += CRT_COLS; - /* cascade */ + /* cascade */ case '\r': crt_pos -= (crt_pos % CRT_COLS); break; @@ -99,7 +99,7 @@ static void rt_cga_putc(int c) rt_console_putc(' '); break; default: - crt_buf[crt_pos++] = c; /* write the character */ + crt_buf[crt_pos++] = c; /* write the character */ break; } @@ -289,14 +289,14 @@ int rt_hw_console_init(void) rt_hw_interrupt_install(INTUART0_RX, rt_console_isr, RT_NULL, "COM1"); rt_hw_interrupt_umask(INTUART0_RX); - console_device.type = RT_Device_Class_Char; + console_device.type = RT_Device_Class_Char; console_device.rx_indicate = RT_NULL; console_device.tx_complete = RT_NULL; - console_device.init = rt_console_init; - console_device.open = rt_console_open; - console_device.close = rt_console_close; - console_device.read = rt_console_read; - console_device.write = rt_console_write; + console_device.init = rt_console_init; + console_device.open = rt_console_open; + console_device.close = rt_console_close; + console_device.read = rt_console_read; + console_device.write = rt_console_write; console_device.control = rt_console_control; console_device.user_data = RT_NULL; @@ -316,8 +316,8 @@ INIT_DEVICE_EXPORT(rt_hw_console_init); * @param str the displayed string * * Modified: - * caoxl 2009-10-14 - * the name is change to rt_hw_console_output in the v0.3.0 + * caoxl 2009-10-14 + * the name is change to rt_hw_console_output in the v0.3.0 * */ void rt_hw_console_output(const char* str) diff --git a/bsp/x86/drivers/dma.h b/bsp/x86/drivers/dma.h index 3e5e9b08d1..9b87a309bb 100644 --- a/bsp/x86/drivers/dma.h +++ b/bsp/x86/drivers/dma.h @@ -101,7 +101,7 @@ static __inline__ void ClearDmaFF(unsigned int dmanr) OUTB(0, DMA2_CLEAR_FF_REG); } -/* +/* * 清空DMA 晶体计数器 */ static __inline__ void SetDmaMode(unsigned int dmanr, char mode) diff --git a/bsp/x86/drivers/floppy.c b/bsp/x86/drivers/floppy.c index f4675b9194..c144eb02eb 100644 --- a/bsp/x86/drivers/floppy.c +++ b/bsp/x86/drivers/floppy.c @@ -31,7 +31,7 @@ typedef rt_int32_t s32; static u8 floppy_buffer[512]; /* 软盘高速缓冲区地址指针 */ -#define MAX_REPLIES 7 +#define MAX_REPLIES 7 static u8 floppy_reply_buffer[MAX_REPLIES]; /* 软驱回应缓冲区 */ #define ST0 (floppy_reply_buffer[0]) /* 软驱回应0号字节 */ #define ST1 (floppy_reply_buffer[1]) /* 软驱回应1号字节 */ @@ -114,7 +114,7 @@ u32 floppy_get_info(void) u8 CmType, FdType; floppy_sendbyte(0x10); - i = floppy_getbyte(); + i = floppy_getbyte(); switch (i) { @@ -180,7 +180,7 @@ void floppy_motorOff( void ) void floppy_setmode(void) -{ +{ floppy_sendbyte (FD_SPECIFY); floppy_sendbyte (0xcf); floppy_sendbyte (0x06); @@ -197,7 +197,7 @@ void block_to_hts(u32 block, u32 *head, u32 *track, u32 *sector ) void floppy_setupDMA(void) -{ +{ u32 eflags; _local_irq_save(eflags); DisableDma(2); @@ -235,7 +235,7 @@ void floppy_read_cmd(u32 blk) floppy_sendbyte (18); //floppy_sendbyte (sector+secs-1); /* Last sector in track:here are sectors count */ floppy_sendbyte (0x1B); - floppy_sendbyte (0xff); + floppy_sendbyte (0xff); return; } @@ -282,12 +282,12 @@ static rt_size_t rt_floppy_read(rt_device_t device, rt_off_t position, void *buf { panic("ST0 %d ST1 %d ST2 %d\n",ST0,ST1,ST2); } - + rt_memcpy(buffer, floppy_buffer, 512); floppy_motorOff(); io_delay(); - + position += 1; size -= 1; } diff --git a/bsp/x86/drivers/include/bsp.h b/bsp/x86/drivers/include/bsp.h index 93e409dbfa..fecb884ee8 100644 --- a/bsp/x86/drivers/include/bsp.h +++ b/bsp/x86/drivers/include/bsp.h @@ -15,127 +15,127 @@ #ifdef __cplusplus extern "C" { #endif - + /*******************************************************************/ /* Timer Register */ /*******************************************************************/ -#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ -#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ -#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ -#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ -#define TIMER_SEL0 0x00 /* select counter 0 */ -#define TIMER_SEL1 0x40 /* select counter 1 */ -#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ -#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ -#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ -#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ -#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ -#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ -#define TIMER_LATCH 0x00 /* latch counter for reading */ -#define TIMER_LSB 0x10 /* r/w counter LSB */ -#define TIMER_MSB 0x20 /* r/w counter MSB */ -#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ -#define TIMER_BCD 0x01 /* count in BCD */ +#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ +#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ +#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ +#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ +#define TIMER_SEL0 0x00 /* select counter 0 */ +#define TIMER_SEL1 0x40 /* select counter 1 */ +#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ +#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ +#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ +#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ +#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ +#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ +#define TIMER_LATCH 0x00 /* latch counter for reading */ +#define TIMER_LSB 0x10 /* r/w counter LSB */ +#define TIMER_MSB 0x20 /* r/w counter MSB */ +#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ +#define TIMER_BCD 0x01 /* count in BCD */ -#define TIMER_FREQ 1193182 -#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x)) +#define TIMER_FREQ 1193182 +#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x)) -#define IO_TIMER1 0x040 /* 8253 Timer #1 */ +#define IO_TIMER1 0x040 /* 8253 Timer #1 */ /*******************************************************************/ /* Interrupt Controller */ /*******************************************************************/ /* these are processor defined */ -#define T_DIVIDE 0 /* divide error */ -#define T_DEBUG 1 /* debug exception */ -#define T_NMI 2 /* non-maskable interrupt */ -#define T_BRKPT 3 /* breakpoint */ -#define T_OFLOW 4 /* overflow */ -#define T_BOUND 5 /* bounds check */ -#define T_ILLOP 6 /* illegal opcode */ -#define T_DEVICE 7 /* device not available */ -#define T_DBLFLT 8 /* double fault */ +#define T_DIVIDE 0 /* divide error */ +#define T_DEBUG 1 /* debug exception */ +#define T_NMI 2 /* non-maskable interrupt */ +#define T_BRKPT 3 /* breakpoint */ +#define T_OFLOW 4 /* overflow */ +#define T_BOUND 5 /* bounds check */ +#define T_ILLOP 6 /* illegal opcode */ +#define T_DEVICE 7 /* device not available */ +#define T_DBLFLT 8 /* double fault */ /* 9 is reserved */ -#define T_TSS 10 /* invalid task switch segment */ -#define T_SEGNP 11 /* segment not present */ -#define T_STACK 12 /* stack exception */ -#define T_GPFLT 13 /* genernal protection fault */ -#define T_PGFLT 14 /* page fault */ +#define T_TSS 10 /* invalid task switch segment */ +#define T_SEGNP 11 /* segment not present */ +#define T_STACK 12 /* stack exception */ +#define T_GPFLT 13 /* genernal protection fault */ +#define T_PGFLT 14 /* page fault */ /* 15 is reserved */ -#define T_FPERR 16 /* floating point error */ -#define T_ALIGN 17 /* aligment check */ -#define T_MCHK 18 /* machine check */ -#define T_DEFAULT 500 /* catchall */ +#define T_FPERR 16 /* floating point error */ +#define T_ALIGN 17 /* aligment check */ +#define T_MCHK 18 /* machine check */ +#define T_DEFAULT 500 /* catchall */ -#define INTTIMER0 0 -#define INTKEYBOARD 1 -#define INTUART0_RX 4 -#define CLOCK_IRQ 0 -#define KEYBOARD_IRQ 1 -#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ -#define ETHER_IRQ 3 /* default ethernet interrupt vector */ -#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ -#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ -#define XT_WINI_IRQ 5 /* xt winchester */ -#define FLOPPY_IRQ 6 /* floppy disk */ -#define PRINTER_IRQ 7 -#define AT_WINI_IRQ 14 /* at winchester */ +#define INTTIMER0 0 +#define INTKEYBOARD 1 +#define INTUART0_RX 4 +#define CLOCK_IRQ 0 +#define KEYBOARD_IRQ 1 +#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ +#define ETHER_IRQ 3 /* default ethernet interrupt vector */ +#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ +#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ +#define XT_WINI_IRQ 5 /* xt winchester */ +#define FLOPPY_IRQ 6 /* floppy disk */ +#define PRINTER_IRQ 7 +#define AT_WINI_IRQ 14 /* at winchester */ /* I/O Addresses of the two 8259A programmable interrupt controllers */ -#define IO_PIC1 0x20 /* Master(IRQs 0-7) */ -#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ -#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ -#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ +#define IO_PIC1 0x20 /* Master(IRQs 0-7) */ +#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ +#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ +#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ -#define MAX_HANDLERS 16 /*max number of isr handler*/ +#define MAX_HANDLERS 16 /*max number of isr handler*/ /*******************************************************************/ /* CRT Register */ /*******************************************************************/ -#define MONO_BASE 0x3b4 -#define MONO_BUF 0xb0000 -#define CGA_BASE 0x3d4 -#define CGA_BUF 0xb8000 +#define MONO_BASE 0x3b4 +#define MONO_BUF 0xb0000 +#define CGA_BASE 0x3d4 +#define CGA_BUF 0xb8000 -#define CRT_ROWS 25 -#define CRT_COLS 80 -#define CRT_SIZE (CRT_ROWS * CRT_COLS) +#define CRT_ROWS 25 +#define CRT_COLS 80 +#define CRT_SIZE (CRT_ROWS * CRT_COLS) /*******************************************************************/ /* Keyboard Register */ /*******************************************************************/ -#define KBSTATP 0x64 /* kbd controller status port(I) */ -#define KBS_DIB 0x01 /* kbd data in buffer */ -#define KBDATAP 0x60 /* kbd data port(I) */ +#define KBSTATP 0x64 /* kbd controller status port(I) */ +#define KBS_DIB 0x01 /* kbd data in buffer */ +#define KBDATAP 0x60 /* kbd data port(I) */ /* AT keyboard */ /* 8042 ports */ -#define KB_DATA 0x60 /* I/O port for keyboard data - * Read : Read Output Buffer +#define KB_DATA 0x60 /* I/O port for keyboard data + * Read : Read Output Buffer * Write: Write Input Buffer(8042 Data&8048 Command) */ -#define KB_CMD 0x64 /* I/O port for keyboard command +#define KB_CMD 0x64 /* I/O port for keyboard command * Read : Read Status Register * Write: Write Input Buffer(8042 Command) */ -#define LED_CODE 0xED -#define KB_ACK 0xFA +#define LED_CODE 0xED +#define KB_ACK 0xFA /*******************************************************************/ /* Serial Register */ /*******************************************************************/ /*Serial I/O code */ -#define COM1 0x3F8 -#define COMSTATUS 5 -#define COMDATA 0x01 -#define COMREAD 0 -#define COMWRITE 0 +#define COM1 0x3F8 +#define COMSTATUS 5 +#define COMDATA 0x01 +#define COMREAD 0 +#define COMWRITE 0 /* Bits definition of the Line Status Register (LSR)*/ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* Transmitter Holding Register Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define ERFIFO 0x80 /* Error receive Fifo */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ #ifdef __cplusplus } diff --git a/bsp/x86/drivers/include/grub.h b/bsp/x86/drivers/include/grub.h index d5a84a48da..96d4533c3f 100644 --- a/bsp/x86/drivers/include/grub.h +++ b/bsp/x86/drivers/include/grub.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2006-10-09 Bernard the grub related definitions + * 2006-10-09 Bernard the grub related definitions * (multiboot) */ @@ -13,13 +13,13 @@ #define __GRUB_H__ /* the magic number for the multiboot header. */ -#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 /* the flags for the multiboot header. */ -#define MULTIBOOT_HEADER_FLAGS 0x00000003 +#define MULTIBOOT_HEADER_FLAGS 0x00000003 /* the magic number passed by a multiboot-compliant boot loader. */ -#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 +#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 #ifndef __ASM__ /* the multiboot header. */ diff --git a/bsp/x86/drivers/include/i386.h b/bsp/x86/drivers/include/i386.h index bde4a95c3b..7d002393e7 100644 --- a/bsp/x86/drivers/include/i386.h +++ b/bsp/x86/drivers/include/i386.h @@ -44,9 +44,9 @@ static __inline unsigned int inl(int port) static __inline void insl(int port, void *addr, int cnt) { - __asm __volatile("cld\n\trepne\n\tinsl" : - "=D" (addr), "=c" (cnt) : - "d" (port), "0" (addr), "1" (cnt) : + __asm __volatile("cld\n\trepne\n\tinsl" : + "=D" (addr), "=c" (cnt) : + "d" (port), "0" (addr), "1" (cnt) : "memory", "cc"); } diff --git a/bsp/x86/drivers/keyboard.c b/bsp/x86/drivers/keyboard.c index b4ae626261..4890db380b 100644 --- a/bsp/x86/drivers/keyboard.c +++ b/bsp/x86/drivers/keyboard.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,290 +19,290 @@ #define FALSE RT_FALSE #define TRUE RT_TRUE #define PRIVATE static -#define PUBLIC +#define PUBLIC #define t_bool rt_bool_t #define t_8 rt_uint8_t #define t_32 rt_uint32_t -PRIVATE KB_INPUT kb_in; -PRIVATE t_bool code_with_E0 = FALSE; -PRIVATE t_bool shift_l; /* l shift state */ -PRIVATE t_bool shift_r; /* r shift state */ -PRIVATE t_bool alt_l; /* l alt state */ -PRIVATE t_bool alt_r; /* r left state */ -PRIVATE t_bool ctrl_l; /* l ctrl state */ -PRIVATE t_bool ctrl_r; /* l ctrl state */ -PRIVATE t_bool caps_lock; /* Caps Lock */ -PRIVATE t_bool num_lock; /* Num Lock */ -PRIVATE t_bool scroll_lock; /* Scroll Lock */ -PRIVATE int column = 0; /* keyrow[column] is one value of keymap */ +PRIVATE KB_INPUT kb_in; +PRIVATE t_bool code_with_E0 = FALSE; +PRIVATE t_bool shift_l; /* l shift state */ +PRIVATE t_bool shift_r; /* r shift state */ +PRIVATE t_bool alt_l; /* l alt state */ +PRIVATE t_bool alt_r; /* r left state */ +PRIVATE t_bool ctrl_l; /* l ctrl state */ +PRIVATE t_bool ctrl_r; /* l ctrl state */ +PRIVATE t_bool caps_lock; /* Caps Lock */ +PRIVATE t_bool num_lock; /* Num Lock */ +PRIVATE t_bool scroll_lock; /* Scroll Lock */ +PRIVATE int column = 0; /* keyrow[column] is one value of keymap */ -PRIVATE t_8 get_byte_from_kb_buf(); -PRIVATE void set_leds(); -PRIVATE void kb_wait(); -PRIVATE void kb_ack(); +PRIVATE t_8 get_byte_from_kb_buf(); +PRIVATE void set_leds(); +PRIVATE void kb_wait(); +PRIVATE void kb_ack(); PUBLIC void init_keyboard() { - kb_in.count = 0; - kb_in.p_head = kb_in.p_tail = kb_in.buf; + kb_in.count = 0; + kb_in.p_head = kb_in.p_tail = kb_in.buf; - caps_lock = 0; - num_lock = 1; - scroll_lock = 0; + caps_lock = 0; + num_lock = 1; + scroll_lock = 0; - set_leds(); + set_leds(); } PUBLIC rt_bool_t keyboard_read(rt_uint32_t *pkey) { - t_8 scan_code; - t_bool make; /* TRUE : make */ - /* FALSE: break */ - t_32 key = 0; - t_32* keyrow; + t_8 scan_code; + t_bool make; /* TRUE : make */ + /* FALSE: break */ + t_32 key = 0; + t_32* keyrow; - if(kb_in.count > 0){ - code_with_E0 = FALSE; - scan_code = get_byte_from_kb_buf(); + if(kb_in.count > 0){ + code_with_E0 = FALSE; + scan_code = get_byte_from_kb_buf(); - /* start scan */ - if (scan_code == 0xE1) { - int i; - static const t_8 pausebreak_scan_code[] = {0xE1, 0x1D, 0x45, 0xE1, 0x9D, 0xC5}; - t_bool is_pausebreak = TRUE; - for(i=1;i<6;i++){ - if (get_byte_from_kb_buf() != pausebreak_scan_code[i]) { - is_pausebreak = FALSE; - break; - } - } - if (is_pausebreak) { - key = PAUSEBREAK; - } - } - else if (scan_code == 0xE0) { - code_with_E0 = TRUE; - scan_code = get_byte_from_kb_buf(); + /* start scan */ + if (scan_code == 0xE1) { + int i; + static const t_8 pausebreak_scan_code[] = {0xE1, 0x1D, 0x45, 0xE1, 0x9D, 0xC5}; + t_bool is_pausebreak = TRUE; + for(i=1;i<6;i++){ + if (get_byte_from_kb_buf() != pausebreak_scan_code[i]) { + is_pausebreak = FALSE; + break; + } + } + if (is_pausebreak) { + key = PAUSEBREAK; + } + } + else if (scan_code == 0xE0) { + code_with_E0 = TRUE; + scan_code = get_byte_from_kb_buf(); - /* PrintScreen pressed */ - if (scan_code == 0x2A) { - code_with_E0 = FALSE; - if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { - code_with_E0 = TRUE; - if ((scan_code = get_byte_from_kb_buf()) == 0x37) { - key = PRINTSCREEN; - make = TRUE; - } - } - } - /* PrintScreen released */ - else if (scan_code == 0xB7) { - code_with_E0 = FALSE; - if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { - code_with_E0 = TRUE; - if ((scan_code = get_byte_from_kb_buf()) == 0xAA) { - key = PRINTSCREEN; - make = FALSE; - } - } - } - } /* if is not PrintScreen, scan_code is the one after 0xE0 */ - if ((key != PAUSEBREAK) && (key != PRINTSCREEN)) { - /* is Make Code or Break Code */ - make = (scan_code & FLAG_BREAK ? FALSE : TRUE); - - keyrow = &keymap[(scan_code & 0x7F) * MAP_COLS]; + /* PrintScreen pressed */ + if (scan_code == 0x2A) { + code_with_E0 = FALSE; + if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { + code_with_E0 = TRUE; + if ((scan_code = get_byte_from_kb_buf()) == 0x37) { + key = PRINTSCREEN; + make = TRUE; + } + } + } + /* PrintScreen released */ + else if (scan_code == 0xB7) { + code_with_E0 = FALSE; + if ((scan_code = get_byte_from_kb_buf()) == 0xE0) { + code_with_E0 = TRUE; + if ((scan_code = get_byte_from_kb_buf()) == 0xAA) { + key = PRINTSCREEN; + make = FALSE; + } + } + } + } /* if is not PrintScreen, scan_code is the one after 0xE0 */ + if ((key != PAUSEBREAK) && (key != PRINTSCREEN)) { + /* is Make Code or Break Code */ + make = (scan_code & FLAG_BREAK ? FALSE : TRUE); - column = 0; + keyrow = &keymap[(scan_code & 0x7F) * MAP_COLS]; - t_bool caps = shift_l || shift_r; - if (caps_lock) { - if ((keyrow[0] >= 'a') && (keyrow[0] <= 'z')){ - caps = !caps; - } - } - if (caps) { - column = 1; - } + column = 0; - if (code_with_E0) { - column = 2; - } + t_bool caps = shift_l || shift_r; + if (caps_lock) { + if ((keyrow[0] >= 'a') && (keyrow[0] <= 'z')){ + caps = !caps; + } + } + if (caps) { + column = 1; + } - key = keyrow[column]; + if (code_with_E0) { + column = 2; + } - switch(key) { - case SHIFT_L: - shift_l = make; - break; - case SHIFT_R: - shift_r = make; - break; - case CTRL_L: - ctrl_l = make; - break; - case CTRL_R: - ctrl_r = make; - break; - case ALT_L: - alt_l = make; - break; - case ALT_R: - alt_l = make; - break; - case CAPS_LOCK: - if (make) { - caps_lock = !caps_lock; - set_leds(); - } - break; - case NUM_LOCK: - if (make) { - num_lock = !num_lock; - set_leds(); - } - break; - case SCROLL_LOCK: - if (make) { - scroll_lock = !scroll_lock; - set_leds(); - } - break; - default: - break; - } - } + key = keyrow[column]; - if(make){ /* ignore Break Code */ - t_bool pad = FALSE; + switch(key) { + case SHIFT_L: + shift_l = make; + break; + case SHIFT_R: + shift_r = make; + break; + case CTRL_L: + ctrl_l = make; + break; + case CTRL_R: + ctrl_r = make; + break; + case ALT_L: + alt_l = make; + break; + case ALT_R: + alt_l = make; + break; + case CAPS_LOCK: + if (make) { + caps_lock = !caps_lock; + set_leds(); + } + break; + case NUM_LOCK: + if (make) { + num_lock = !num_lock; + set_leds(); + } + break; + case SCROLL_LOCK: + if (make) { + scroll_lock = !scroll_lock; + set_leds(); + } + break; + default: + break; + } + } - /* handle the small pad first */ - if ((key >= PAD_SLASH) && (key <= PAD_9)) { - pad = TRUE; - switch(key) { /* '/', '*', '-', '+', and 'Enter' in num pad */ - case PAD_SLASH: - key = '/'; - break; - case PAD_STAR: - key = '*'; - break; - case PAD_MINUS: - key = '-'; - break; - case PAD_PLUS: - key = '+'; - break; - case PAD_ENTER: - key = ENTER; - break; - default: /* keys whose value depends on the NumLock */ - if (num_lock) { /* '0' ~ '9' and '.' in num pad */ - if ((key >= PAD_0) && (key <= PAD_9)) { - key = key - PAD_0 + '0'; - } - else if (key == PAD_DOT) { - key = '.'; - } - } - else{ - switch(key) { - case PAD_HOME: - key = HOME; - break; - case PAD_END: - key = END; - break; - case PAD_PAGEUP: - key = PAGEUP; - break; - case PAD_PAGEDOWN: - key = PAGEDOWN; - break; - case PAD_INS: - key = INSERT; - break; - case PAD_UP: - key = UP; - break; - case PAD_DOWN: - key = DOWN; - break; - case PAD_LEFT: - key = LEFT; - break; - case PAD_RIGHT: - key = RIGHT; - break; - case PAD_DOT: - key = DELETE; - break; - default: - break; - } - } - break; - } - } - key |= shift_l ? FLAG_SHIFT_L : 0; - key |= shift_r ? FLAG_SHIFT_R : 0; - key |= ctrl_l ? FLAG_CTRL_L : 0; - key |= ctrl_r ? FLAG_CTRL_R : 0; - key |= alt_l ? FLAG_ALT_L : 0; - key |= alt_r ? FLAG_ALT_R : 0; - key |= pad ? FLAG_PAD : 0; + if(make){ /* ignore Break Code */ + t_bool pad = FALSE; - *pkey = key; - return TRUE; - } - } + /* handle the small pad first */ + if ((key >= PAD_SLASH) && (key <= PAD_9)) { + pad = TRUE; + switch(key) { /* '/', '*', '-', '+', and 'Enter' in num pad */ + case PAD_SLASH: + key = '/'; + break; + case PAD_STAR: + key = '*'; + break; + case PAD_MINUS: + key = '-'; + break; + case PAD_PLUS: + key = '+'; + break; + case PAD_ENTER: + key = ENTER; + break; + default: /* keys whose value depends on the NumLock */ + if (num_lock) { /* '0' ~ '9' and '.' in num pad */ + if ((key >= PAD_0) && (key <= PAD_9)) { + key = key - PAD_0 + '0'; + } + else if (key == PAD_DOT) { + key = '.'; + } + } + else{ + switch(key) { + case PAD_HOME: + key = HOME; + break; + case PAD_END: + key = END; + break; + case PAD_PAGEUP: + key = PAGEUP; + break; + case PAD_PAGEDOWN: + key = PAGEDOWN; + break; + case PAD_INS: + key = INSERT; + break; + case PAD_UP: + key = UP; + break; + case PAD_DOWN: + key = DOWN; + break; + case PAD_LEFT: + key = LEFT; + break; + case PAD_RIGHT: + key = RIGHT; + break; + case PAD_DOT: + key = DELETE; + break; + default: + break; + } + } + break; + } + } + key |= shift_l ? FLAG_SHIFT_L : 0; + key |= shift_r ? FLAG_SHIFT_R : 0; + key |= ctrl_l ? FLAG_CTRL_L : 0; + key |= ctrl_r ? FLAG_CTRL_R : 0; + key |= alt_l ? FLAG_ALT_L : 0; + key |= alt_r ? FLAG_ALT_R : 0; + key |= pad ? FLAG_PAD : 0; - return FALSE; + *pkey = key; + return TRUE; + } + } + + return FALSE; } PRIVATE t_8 get_byte_from_kb_buf() { - t_8 scan_code; + t_8 scan_code; - RT_ASSERT(kb_in.count>0); - scan_code = *(kb_in.p_tail); - kb_in.p_tail++; - if (kb_in.p_tail == kb_in.buf + KB_IN_BYTES) { - kb_in.p_tail = kb_in.buf; - } - kb_in.count--; + RT_ASSERT(kb_in.count>0); + scan_code = *(kb_in.p_tail); + kb_in.p_tail++; + if (kb_in.p_tail == kb_in.buf + KB_IN_BYTES) { + kb_in.p_tail = kb_in.buf; + } + kb_in.count--; - return scan_code; + return scan_code; } PRIVATE void kb_wait() /* wait inpit cache of 8042 */ { - t_8 kb_stat; + t_8 kb_stat; - do { - kb_stat = inb(KB_CMD); - } while (kb_stat & 0x02); + do { + kb_stat = inb(KB_CMD); + } while (kb_stat & 0x02); } PRIVATE void kb_ack() { - t_8 kb_read; + t_8 kb_read; - do { - kb_read = inb(KB_DATA); - } while (kb_read != KB_ACK); + do { + kb_read = inb(KB_DATA); + } while (kb_read != KB_ACK); } PRIVATE void set_leds() { - t_8 leds = (caps_lock << 2) | (num_lock << 1) | scroll_lock; + t_8 leds = (caps_lock << 2) | (num_lock << 1) | scroll_lock; - kb_wait(); - outb(KB_DATA, LED_CODE); - kb_ack(); + kb_wait(); + outb(KB_DATA, LED_CODE); + kb_ack(); - kb_wait(); - outb(KB_DATA, leds); - kb_ack(); + kb_wait(); + outb(KB_DATA, leds); + kb_ack(); } /** @@ -312,51 +312,51 @@ PRIVATE void set_leds() void rt_keyboard_isr(void) { - rt_uint8_t data; + rt_uint8_t data; - if ((inb(KBSTATP) & KBS_DIB) == 0) - return ; + if ((inb(KBSTATP) & KBS_DIB) == 0) + return ; - data = inb(KBDATAP); + data = inb(KBDATAP); - if (kb_in.count < KB_IN_BYTES) { - *(kb_in.p_head) = data; - kb_in.p_head++; - if (kb_in.p_head == kb_in.buf + KB_IN_BYTES) { - kb_in.p_head = kb_in.buf; - } - kb_in.count++; - } + if (kb_in.count < KB_IN_BYTES) { + *(kb_in.p_head) = data; + kb_in.p_head++; + if (kb_in.p_head == kb_in.buf + KB_IN_BYTES) { + kb_in.p_head = kb_in.buf; + } + kb_in.count++; + } } /* generally, this should be called in task level for all key inpit support, but here only support a key that is composed of 2 bytes */ rt_bool_t rt_keyboard_getc(char* c) { - if(kb_in.count>=2) - { - rt_uint32_t key = 0; - rt_bool_t rv=keyboard_read(&key); + if(kb_in.count>=2) + { + rt_uint32_t key = 0; + rt_bool_t rv=keyboard_read(&key); - switch(key) - { - case TAB: - *c = '\t'; - break; - case ENTER: - *c = '\n'; - break; - case BACKSPACE: - *c = '\b'; - break; - default: - *c = key; - break; - } + switch(key) + { + case TAB: + *c = '\t'; + break; + case ENTER: + *c = '\n'; + break; + case BACKSPACE: + *c = '\b'; + break; + default: + *c = key; + break; + } - return rv; - } + return rv; + } - return RT_FALSE; + return RT_FALSE; } /*@}*/ diff --git a/bsp/x86/drivers/keyboard.h b/bsp/x86/drivers/keyboard.h index 437d9dfc9f..3fec24c4e8 100644 --- a/bsp/x86/drivers/keyboard.h +++ b/bsp/x86/drivers/keyboard.h @@ -12,115 +12,115 @@ Forrest Yu, 2005 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#ifndef _TINIX_KEYBOARD_H_ -#define _TINIX_KEYBOARD_H_ +#ifndef _TINIX_KEYBOARD_H_ +#define _TINIX_KEYBOARD_H_ /************************************************************************/ /* Macros Declaration */ /************************************************************************/ -#define KB_IN_BYTES 32 /* size of keyboard input buffer */ -#define MAP_COLS 3 /* Number of columns in keymap */ -#define NR_SCAN_CODES 0x80 /* Number of scan codes (rows in keymap) */ +#define KB_IN_BYTES 32 /* size of keyboard input buffer */ +#define MAP_COLS 3 /* Number of columns in keymap */ +#define NR_SCAN_CODES 0x80 /* Number of scan codes (rows in keymap) */ -#define FLAG_BREAK 0x0080 /* Break Code */ -#define FLAG_EXT 0x0100 /* Normal function keys */ -#define FLAG_SHIFT_L 0x0200 /* Shift key */ -#define FLAG_SHIFT_R 0x0400 /* Shift key */ -#define FLAG_CTRL_L 0x0800 /* Control key */ -#define FLAG_CTRL_R 0x1000 /* Control key */ -#define FLAG_ALT_L 0x2000 /* Alternate key */ -#define FLAG_ALT_R 0x4000 /* Alternate key */ -#define FLAG_PAD 0x8000 /* keys in num pad */ +#define FLAG_BREAK 0x0080 /* Break Code */ +#define FLAG_EXT 0x0100 /* Normal function keys */ +#define FLAG_SHIFT_L 0x0200 /* Shift key */ +#define FLAG_SHIFT_R 0x0400 /* Shift key */ +#define FLAG_CTRL_L 0x0800 /* Control key */ +#define FLAG_CTRL_R 0x1000 /* Control key */ +#define FLAG_ALT_L 0x2000 /* Alternate key */ +#define FLAG_ALT_R 0x4000 /* Alternate key */ +#define FLAG_PAD 0x8000 /* keys in num pad */ -#define MASK_RAW 0x01FF /* raw key value = code passed to tty & MASK_RAW - the value can be found either in the keymap column 0 - or in the list below */ +#define MASK_RAW 0x01FF /* raw key value = code passed to tty & MASK_RAW + the value can be found either in the keymap column 0 + or in the list below */ /* Special keys */ -#define ESC (0x01 + FLAG_EXT) /* Esc */ -#define TAB (0x02 + FLAG_EXT) /* Tab */ -#define ENTER (0x03 + FLAG_EXT) /* Enter */ -#define BACKSPACE (0x04 + FLAG_EXT) /* BackSpace */ +#define ESC (0x01 + FLAG_EXT) /* Esc */ +#define TAB (0x02 + FLAG_EXT) /* Tab */ +#define ENTER (0x03 + FLAG_EXT) /* Enter */ +#define BACKSPACE (0x04 + FLAG_EXT) /* BackSpace */ -#define GUI_L (0x05 + FLAG_EXT) /* L GUI */ -#define GUI_R (0x06 + FLAG_EXT) /* R GUI */ -#define APPS (0x07 + FLAG_EXT) /* APPS */ +#define GUI_L (0x05 + FLAG_EXT) /* L GUI */ +#define GUI_R (0x06 + FLAG_EXT) /* R GUI */ +#define APPS (0x07 + FLAG_EXT) /* APPS */ /* Shift, Ctrl, Alt */ -#define SHIFT_L (0x08 + FLAG_EXT) /* L Shift */ -#define SHIFT_R (0x09 + FLAG_EXT) /* R Shift */ -#define CTRL_L (0x0A + FLAG_EXT) /* L Ctrl */ -#define CTRL_R (0x0B + FLAG_EXT) /* R Ctrl */ -#define ALT_L (0x0C + FLAG_EXT) /* L Alt */ -#define ALT_R (0x0D + FLAG_EXT) /* R Alt */ +#define SHIFT_L (0x08 + FLAG_EXT) /* L Shift */ +#define SHIFT_R (0x09 + FLAG_EXT) /* R Shift */ +#define CTRL_L (0x0A + FLAG_EXT) /* L Ctrl */ +#define CTRL_R (0x0B + FLAG_EXT) /* R Ctrl */ +#define ALT_L (0x0C + FLAG_EXT) /* L Alt */ +#define ALT_R (0x0D + FLAG_EXT) /* R Alt */ /* Lock keys */ -#define CAPS_LOCK (0x0E + FLAG_EXT) /* Caps Lock */ -#define NUM_LOCK (0x0F + FLAG_EXT) /* Number Lock */ -#define SCROLL_LOCK (0x10 + FLAG_EXT) /* Scroll Lock */ +#define CAPS_LOCK (0x0E + FLAG_EXT) /* Caps Lock */ +#define NUM_LOCK (0x0F + FLAG_EXT) /* Number Lock */ +#define SCROLL_LOCK (0x10 + FLAG_EXT) /* Scroll Lock */ /* Function keys */ -#define F1 (0x11 + FLAG_EXT) /* F1 */ -#define F2 (0x12 + FLAG_EXT) /* F2 */ -#define F3 (0x13 + FLAG_EXT) /* F3 */ -#define F4 (0x14 + FLAG_EXT) /* F4 */ -#define F5 (0x15 + FLAG_EXT) /* F5 */ -#define F6 (0x16 + FLAG_EXT) /* F6 */ -#define F7 (0x17 + FLAG_EXT) /* F7 */ -#define F8 (0x18 + FLAG_EXT) /* F8 */ -#define F9 (0x19 + FLAG_EXT) /* F9 */ -#define F10 (0x1A + FLAG_EXT) /* F10 */ -#define F11 (0x1B + FLAG_EXT) /* F11 */ -#define F12 (0x1C + FLAG_EXT) /* F12 */ +#define F1 (0x11 + FLAG_EXT) /* F1 */ +#define F2 (0x12 + FLAG_EXT) /* F2 */ +#define F3 (0x13 + FLAG_EXT) /* F3 */ +#define F4 (0x14 + FLAG_EXT) /* F4 */ +#define F5 (0x15 + FLAG_EXT) /* F5 */ +#define F6 (0x16 + FLAG_EXT) /* F6 */ +#define F7 (0x17 + FLAG_EXT) /* F7 */ +#define F8 (0x18 + FLAG_EXT) /* F8 */ +#define F9 (0x19 + FLAG_EXT) /* F9 */ +#define F10 (0x1A + FLAG_EXT) /* F10 */ +#define F11 (0x1B + FLAG_EXT) /* F11 */ +#define F12 (0x1C + FLAG_EXT) /* F12 */ /* Control Pad */ -#define PRINTSCREEN (0x1D + FLAG_EXT) /* Print Screen */ -#define PAUSEBREAK (0x1E + FLAG_EXT) /* Pause/Break */ -#define INSERT (0x1F + FLAG_EXT) /* Insert */ -#define DELETE (0x20 + FLAG_EXT) /* Delete */ -#define HOME (0x21 + FLAG_EXT) /* Home */ -#define END (0x22 + FLAG_EXT) /* End */ -#define PAGEUP (0x23 + FLAG_EXT) /* Page Up */ -#define PAGEDOWN (0x24 + FLAG_EXT) /* Page Down */ -#define UP (0x25 + FLAG_EXT) /* Up */ -#define DOWN (0x26 + FLAG_EXT) /* Down */ -#define LEFT (0x27 + FLAG_EXT) /* Left */ -#define RIGHT (0x28 + FLAG_EXT) /* Right */ +#define PRINTSCREEN (0x1D + FLAG_EXT) /* Print Screen */ +#define PAUSEBREAK (0x1E + FLAG_EXT) /* Pause/Break */ +#define INSERT (0x1F + FLAG_EXT) /* Insert */ +#define DELETE (0x20 + FLAG_EXT) /* Delete */ +#define HOME (0x21 + FLAG_EXT) /* Home */ +#define END (0x22 + FLAG_EXT) /* End */ +#define PAGEUP (0x23 + FLAG_EXT) /* Page Up */ +#define PAGEDOWN (0x24 + FLAG_EXT) /* Page Down */ +#define UP (0x25 + FLAG_EXT) /* Up */ +#define DOWN (0x26 + FLAG_EXT) /* Down */ +#define LEFT (0x27 + FLAG_EXT) /* Left */ +#define RIGHT (0x28 + FLAG_EXT) /* Right */ /* ACPI keys */ -#define POWER (0x29 + FLAG_EXT) /* Power */ -#define SLEEP (0x2A + FLAG_EXT) /* Sleep */ -#define WAKE (0x2B + FLAG_EXT) /* Wake Up */ +#define POWER (0x29 + FLAG_EXT) /* Power */ +#define SLEEP (0x2A + FLAG_EXT) /* Sleep */ +#define WAKE (0x2B + FLAG_EXT) /* Wake Up */ /* Num Pad */ -#define PAD_SLASH (0x2C + FLAG_EXT) /* / */ -#define PAD_STAR (0x2D + FLAG_EXT) /* * */ -#define PAD_MINUS (0x2E + FLAG_EXT) /* - */ -#define PAD_PLUS (0x2F + FLAG_EXT) /* + */ -#define PAD_ENTER (0x30 + FLAG_EXT) /* Enter */ -#define PAD_DOT (0x31 + FLAG_EXT) /* . */ -#define PAD_0 (0x32 + FLAG_EXT) /* 0 */ -#define PAD_1 (0x33 + FLAG_EXT) /* 1 */ -#define PAD_2 (0x34 + FLAG_EXT) /* 2 */ -#define PAD_3 (0x35 + FLAG_EXT) /* 3 */ -#define PAD_4 (0x36 + FLAG_EXT) /* 4 */ -#define PAD_5 (0x37 + FLAG_EXT) /* 5 */ -#define PAD_6 (0x38 + FLAG_EXT) /* 6 */ -#define PAD_7 (0x39 + FLAG_EXT) /* 7 */ -#define PAD_8 (0x3A + FLAG_EXT) /* 8 */ -#define PAD_9 (0x3B + FLAG_EXT) /* 9 */ -#define PAD_UP PAD_8 /* Up */ -#define PAD_DOWN PAD_2 /* Down */ -#define PAD_LEFT PAD_4 /* Left */ -#define PAD_RIGHT PAD_6 /* Right */ -#define PAD_HOME PAD_7 /* Home */ -#define PAD_END PAD_1 /* End */ -#define PAD_PAGEUP PAD_9 /* Page Up */ -#define PAD_PAGEDOWN PAD_3 /* Page Down */ -#define PAD_INS PAD_0 /* Ins */ -#define PAD_MID PAD_5 /* Middle key */ -#define PAD_DEL PAD_DOT /* Del */ +#define PAD_SLASH (0x2C + FLAG_EXT) /* / */ +#define PAD_STAR (0x2D + FLAG_EXT) /* * */ +#define PAD_MINUS (0x2E + FLAG_EXT) /* - */ +#define PAD_PLUS (0x2F + FLAG_EXT) /* + */ +#define PAD_ENTER (0x30 + FLAG_EXT) /* Enter */ +#define PAD_DOT (0x31 + FLAG_EXT) /* . */ +#define PAD_0 (0x32 + FLAG_EXT) /* 0 */ +#define PAD_1 (0x33 + FLAG_EXT) /* 1 */ +#define PAD_2 (0x34 + FLAG_EXT) /* 2 */ +#define PAD_3 (0x35 + FLAG_EXT) /* 3 */ +#define PAD_4 (0x36 + FLAG_EXT) /* 4 */ +#define PAD_5 (0x37 + FLAG_EXT) /* 5 */ +#define PAD_6 (0x38 + FLAG_EXT) /* 6 */ +#define PAD_7 (0x39 + FLAG_EXT) /* 7 */ +#define PAD_8 (0x3A + FLAG_EXT) /* 8 */ +#define PAD_9 (0x3B + FLAG_EXT) /* 9 */ +#define PAD_UP PAD_8 /* Up */ +#define PAD_DOWN PAD_2 /* Down */ +#define PAD_LEFT PAD_4 /* Left */ +#define PAD_RIGHT PAD_6 /* Right */ +#define PAD_HOME PAD_7 /* Home */ +#define PAD_END PAD_1 /* End */ +#define PAD_PAGEUP PAD_9 /* Page Up */ +#define PAD_PAGEDOWN PAD_3 /* Page Down */ +#define PAD_INS PAD_0 /* Ins */ +#define PAD_MID PAD_5 /* Middle key */ +#define PAD_DEL PAD_DOT /* Del */ /************************************************************************/ @@ -128,10 +128,10 @@ /************************************************************************/ /* Keyboard structure, 1 per console. */ typedef struct s_kb { - char* p_head; /* input cache pointer */ - char* p_tail; /* read cache pointer */ - int count; - char buf[KB_IN_BYTES]; + char* p_head; /* input cache pointer */ + char* p_tail; /* read cache pointer */ + int count; + char buf[KB_IN_BYTES]; }KB_INPUT; diff --git a/bsp/x86/drivers/keymap.h b/bsp/x86/drivers/keymap.h index aa9880e295..e141fa0d6e 100644 --- a/bsp/x86/drivers/keymap.h +++ b/bsp/x86/drivers/keymap.h @@ -17,227 +17,227 @@ /* It should be and can only be included by keyboard.c! */ /********************************************************************/ -#ifndef _TINIX_KEYMAP_H_ -#define _TINIX_KEYMAP_H_ +#ifndef _TINIX_KEYMAP_H_ +#define _TINIX_KEYMAP_H_ /* Keymap for US MF-2 keyboard. */ rt_uint32_t keymap[NR_SCAN_CODES * MAP_COLS] = { -/* scan-code !Shift Shift E0 XX */ +/* scan-code !Shift Shift E0 XX */ /* ==================================================================== */ -/* 0x00 - none */ 0, 0, 0, -/* 0x01 - ESC */ ESC, ESC, 0, -/* 0x02 - '1' */ '1', '!', 0, -/* 0x03 - '2' */ '2', '@', 0, -/* 0x04 - '3' */ '3', '#', 0, -/* 0x05 - '4' */ '4', '$', 0, -/* 0x06 - '5' */ '5', '%', 0, -/* 0x07 - '6' */ '6', '^', 0, -/* 0x08 - '7' */ '7', '&', 0, -/* 0x09 - '8' */ '8', '*', 0, -/* 0x0A - '9' */ '9', '(', 0, -/* 0x0B - '0' */ '0', ')', 0, -/* 0x0C - '-' */ '-', '_', 0, -/* 0x0D - '=' */ '=', '+', 0, -/* 0x0E - BS */ BACKSPACE, BACKSPACE, 0, -/* 0x0F - TAB */ TAB, TAB, 0, -/* 0x10 - 'q' */ 'q', 'Q', 0, -/* 0x11 - 'w' */ 'w', 'W', 0, -/* 0x12 - 'e' */ 'e', 'E', 0, -/* 0x13 - 'r' */ 'r', 'R', 0, -/* 0x14 - 't' */ 't', 'T', 0, -/* 0x15 - 'y' */ 'y', 'Y', 0, -/* 0x16 - 'u' */ 'u', 'U', 0, -/* 0x17 - 'i' */ 'i', 'I', 0, -/* 0x18 - 'o' */ 'o', 'O', 0, -/* 0x19 - 'p' */ 'p', 'P', 0, -/* 0x1A - '[' */ '[', '{', 0, -/* 0x1B - ']' */ ']', '}', 0, -/* 0x1C - CR/LF */ ENTER, ENTER, PAD_ENTER, -/* 0x1D - l. Ctrl */ CTRL_L, CTRL_L, CTRL_R, -/* 0x1E - 'a' */ 'a', 'A', 0, -/* 0x1F - 's' */ 's', 'S', 0, -/* 0x20 - 'd' */ 'd', 'D', 0, -/* 0x21 - 'f' */ 'f', 'F', 0, -/* 0x22 - 'g' */ 'g', 'G', 0, -/* 0x23 - 'h' */ 'h', 'H', 0, -/* 0x24 - 'j' */ 'j', 'J', 0, -/* 0x25 - 'k' */ 'k', 'K', 0, -/* 0x26 - 'l' */ 'l', 'L', 0, -/* 0x27 - ';' */ ';', ':', 0, -/* 0x28 - '\'' */ '\'', '"', 0, -/* 0x29 - '`' */ '`', '~', 0, -/* 0x2A - l. SHIFT */ SHIFT_L, SHIFT_L, 0, -/* 0x2B - '\' */ '\\', '|', 0, -/* 0x2C - 'z' */ 'z', 'Z', 0, -/* 0x2D - 'x' */ 'x', 'X', 0, -/* 0x2E - 'c' */ 'c', 'C', 0, -/* 0x2F - 'v' */ 'v', 'V', 0, -/* 0x30 - 'b' */ 'b', 'B', 0, -/* 0x31 - 'n' */ 'n', 'N', 0, -/* 0x32 - 'm' */ 'm', 'M', 0, -/* 0x33 - ',' */ ',', '<', 0, -/* 0x34 - '.' */ '.', '>', 0, -/* 0x35 - '/' */ '/', '?', PAD_SLASH, -/* 0x36 - r. SHIFT */ SHIFT_R, SHIFT_R, 0, -/* 0x37 - '*' */ '*', '*', 0, -/* 0x38 - ALT */ ALT_L, ALT_L, ALT_R, -/* 0x39 - ' ' */ ' ', ' ', 0, -/* 0x3A - CapsLock */ CAPS_LOCK, CAPS_LOCK, 0, -/* 0x3B - F1 */ F1, F1, 0, -/* 0x3C - F2 */ F2, F2, 0, -/* 0x3D - F3 */ F3, F3, 0, -/* 0x3E - F4 */ F4, F4, 0, -/* 0x3F - F5 */ F5, F5, 0, -/* 0x40 - F6 */ F6, F6, 0, -/* 0x41 - F7 */ F7, F7, 0, -/* 0x42 - F8 */ F8, F8, 0, -/* 0x43 - F9 */ F9, F9, 0, -/* 0x44 - F10 */ F10, F10, 0, -/* 0x45 - NumLock */ NUM_LOCK, NUM_LOCK, 0, -/* 0x46 - ScrLock */ SCROLL_LOCK, SCROLL_LOCK, 0, -/* 0x47 - Home */ PAD_HOME, '7', HOME, -/* 0x48 - CurUp */ PAD_UP, '8', UP, -/* 0x49 - PgUp */ PAD_PAGEUP, '9', PAGEUP, -/* 0x4A - '-' */ PAD_MINUS, '-', 0, -/* 0x4B - Left */ PAD_LEFT, '4', LEFT, -/* 0x4C - MID */ PAD_MID, '5', 0, -/* 0x4D - Right */ PAD_RIGHT, '6', RIGHT, -/* 0x4E - '+' */ PAD_PLUS, '+', 0, -/* 0x4F - End */ PAD_END, '1', END, -/* 0x50 - Down */ PAD_DOWN, '2', DOWN, -/* 0x51 - PgDown */ PAD_PAGEDOWN, '3', PAGEDOWN, -/* 0x52 - Insert */ PAD_INS, '0', INSERT, -/* 0x53 - Delete */ PAD_DOT, '.', DELETE, -/* 0x54 - Enter */ 0, 0, 0, -/* 0x55 - ??? */ 0, 0, 0, -/* 0x56 - ??? */ 0, 0, 0, -/* 0x57 - F11 */ F11, F11, 0, -/* 0x58 - F12 */ F12, F12, 0, -/* 0x59 - ??? */ 0, 0, 0, -/* 0x5A - ??? */ 0, 0, 0, -/* 0x5B - ??? */ 0, 0, GUI_L, -/* 0x5C - ??? */ 0, 0, GUI_R, -/* 0x5D - ??? */ 0, 0, APPS, -/* 0x5E - ??? */ 0, 0, 0, -/* 0x5F - ??? */ 0, 0, 0, -/* 0x60 - ??? */ 0, 0, 0, -/* 0x61 - ??? */ 0, 0, 0, -/* 0x62 - ??? */ 0, 0, 0, -/* 0x63 - ??? */ 0, 0, 0, -/* 0x64 - ??? */ 0, 0, 0, -/* 0x65 - ??? */ 0, 0, 0, -/* 0x66 - ??? */ 0, 0, 0, -/* 0x67 - ??? */ 0, 0, 0, -/* 0x68 - ??? */ 0, 0, 0, -/* 0x69 - ??? */ 0, 0, 0, -/* 0x6A - ??? */ 0, 0, 0, -/* 0x6B - ??? */ 0, 0, 0, -/* 0x6C - ??? */ 0, 0, 0, -/* 0x6D - ??? */ 0, 0, 0, -/* 0x6E - ??? */ 0, 0, 0, -/* 0x6F - ??? */ 0, 0, 0, -/* 0x70 - ??? */ 0, 0, 0, -/* 0x71 - ??? */ 0, 0, 0, -/* 0x72 - ??? */ 0, 0, 0, -/* 0x73 - ??? */ 0, 0, 0, -/* 0x74 - ??? */ 0, 0, 0, -/* 0x75 - ??? */ 0, 0, 0, -/* 0x76 - ??? */ 0, 0, 0, -/* 0x77 - ??? */ 0, 0, 0, -/* 0x78 - ??? */ 0, 0, 0, -/* 0x78 - ??? */ 0, 0, 0, -/* 0x7A - ??? */ 0, 0, 0, -/* 0x7B - ??? */ 0, 0, 0, -/* 0x7C - ??? */ 0, 0, 0, -/* 0x7D - ??? */ 0, 0, 0, -/* 0x7E - ??? */ 0, 0, 0, -/* 0x7F - ??? */ 0, 0, 0 +/* 0x00 - none */ 0, 0, 0, +/* 0x01 - ESC */ ESC, ESC, 0, +/* 0x02 - '1' */ '1', '!', 0, +/* 0x03 - '2' */ '2', '@', 0, +/* 0x04 - '3' */ '3', '#', 0, +/* 0x05 - '4' */ '4', '$', 0, +/* 0x06 - '5' */ '5', '%', 0, +/* 0x07 - '6' */ '6', '^', 0, +/* 0x08 - '7' */ '7', '&', 0, +/* 0x09 - '8' */ '8', '*', 0, +/* 0x0A - '9' */ '9', '(', 0, +/* 0x0B - '0' */ '0', ')', 0, +/* 0x0C - '-' */ '-', '_', 0, +/* 0x0D - '=' */ '=', '+', 0, +/* 0x0E - BS */ BACKSPACE, BACKSPACE, 0, +/* 0x0F - TAB */ TAB, TAB, 0, +/* 0x10 - 'q' */ 'q', 'Q', 0, +/* 0x11 - 'w' */ 'w', 'W', 0, +/* 0x12 - 'e' */ 'e', 'E', 0, +/* 0x13 - 'r' */ 'r', 'R', 0, +/* 0x14 - 't' */ 't', 'T', 0, +/* 0x15 - 'y' */ 'y', 'Y', 0, +/* 0x16 - 'u' */ 'u', 'U', 0, +/* 0x17 - 'i' */ 'i', 'I', 0, +/* 0x18 - 'o' */ 'o', 'O', 0, +/* 0x19 - 'p' */ 'p', 'P', 0, +/* 0x1A - '[' */ '[', '{', 0, +/* 0x1B - ']' */ ']', '}', 0, +/* 0x1C - CR/LF */ ENTER, ENTER, PAD_ENTER, +/* 0x1D - l. Ctrl */ CTRL_L, CTRL_L, CTRL_R, +/* 0x1E - 'a' */ 'a', 'A', 0, +/* 0x1F - 's' */ 's', 'S', 0, +/* 0x20 - 'd' */ 'd', 'D', 0, +/* 0x21 - 'f' */ 'f', 'F', 0, +/* 0x22 - 'g' */ 'g', 'G', 0, +/* 0x23 - 'h' */ 'h', 'H', 0, +/* 0x24 - 'j' */ 'j', 'J', 0, +/* 0x25 - 'k' */ 'k', 'K', 0, +/* 0x26 - 'l' */ 'l', 'L', 0, +/* 0x27 - ';' */ ';', ':', 0, +/* 0x28 - '\'' */ '\'', '"', 0, +/* 0x29 - '`' */ '`', '~', 0, +/* 0x2A - l. SHIFT */ SHIFT_L, SHIFT_L, 0, +/* 0x2B - '\' */ '\\', '|', 0, +/* 0x2C - 'z' */ 'z', 'Z', 0, +/* 0x2D - 'x' */ 'x', 'X', 0, +/* 0x2E - 'c' */ 'c', 'C', 0, +/* 0x2F - 'v' */ 'v', 'V', 0, +/* 0x30 - 'b' */ 'b', 'B', 0, +/* 0x31 - 'n' */ 'n', 'N', 0, +/* 0x32 - 'm' */ 'm', 'M', 0, +/* 0x33 - ',' */ ',', '<', 0, +/* 0x34 - '.' */ '.', '>', 0, +/* 0x35 - '/' */ '/', '?', PAD_SLASH, +/* 0x36 - r. SHIFT */ SHIFT_R, SHIFT_R, 0, +/* 0x37 - '*' */ '*', '*', 0, +/* 0x38 - ALT */ ALT_L, ALT_L, ALT_R, +/* 0x39 - ' ' */ ' ', ' ', 0, +/* 0x3A - CapsLock */ CAPS_LOCK, CAPS_LOCK, 0, +/* 0x3B - F1 */ F1, F1, 0, +/* 0x3C - F2 */ F2, F2, 0, +/* 0x3D - F3 */ F3, F3, 0, +/* 0x3E - F4 */ F4, F4, 0, +/* 0x3F - F5 */ F5, F5, 0, +/* 0x40 - F6 */ F6, F6, 0, +/* 0x41 - F7 */ F7, F7, 0, +/* 0x42 - F8 */ F8, F8, 0, +/* 0x43 - F9 */ F9, F9, 0, +/* 0x44 - F10 */ F10, F10, 0, +/* 0x45 - NumLock */ NUM_LOCK, NUM_LOCK, 0, +/* 0x46 - ScrLock */ SCROLL_LOCK, SCROLL_LOCK, 0, +/* 0x47 - Home */ PAD_HOME, '7', HOME, +/* 0x48 - CurUp */ PAD_UP, '8', UP, +/* 0x49 - PgUp */ PAD_PAGEUP, '9', PAGEUP, +/* 0x4A - '-' */ PAD_MINUS, '-', 0, +/* 0x4B - Left */ PAD_LEFT, '4', LEFT, +/* 0x4C - MID */ PAD_MID, '5', 0, +/* 0x4D - Right */ PAD_RIGHT, '6', RIGHT, +/* 0x4E - '+' */ PAD_PLUS, '+', 0, +/* 0x4F - End */ PAD_END, '1', END, +/* 0x50 - Down */ PAD_DOWN, '2', DOWN, +/* 0x51 - PgDown */ PAD_PAGEDOWN, '3', PAGEDOWN, +/* 0x52 - Insert */ PAD_INS, '0', INSERT, +/* 0x53 - Delete */ PAD_DOT, '.', DELETE, +/* 0x54 - Enter */ 0, 0, 0, +/* 0x55 - ??? */ 0, 0, 0, +/* 0x56 - ??? */ 0, 0, 0, +/* 0x57 - F11 */ F11, F11, 0, +/* 0x58 - F12 */ F12, F12, 0, +/* 0x59 - ??? */ 0, 0, 0, +/* 0x5A - ??? */ 0, 0, 0, +/* 0x5B - ??? */ 0, 0, GUI_L, +/* 0x5C - ??? */ 0, 0, GUI_R, +/* 0x5D - ??? */ 0, 0, APPS, +/* 0x5E - ??? */ 0, 0, 0, +/* 0x5F - ??? */ 0, 0, 0, +/* 0x60 - ??? */ 0, 0, 0, +/* 0x61 - ??? */ 0, 0, 0, +/* 0x62 - ??? */ 0, 0, 0, +/* 0x63 - ??? */ 0, 0, 0, +/* 0x64 - ??? */ 0, 0, 0, +/* 0x65 - ??? */ 0, 0, 0, +/* 0x66 - ??? */ 0, 0, 0, +/* 0x67 - ??? */ 0, 0, 0, +/* 0x68 - ??? */ 0, 0, 0, +/* 0x69 - ??? */ 0, 0, 0, +/* 0x6A - ??? */ 0, 0, 0, +/* 0x6B - ??? */ 0, 0, 0, +/* 0x6C - ??? */ 0, 0, 0, +/* 0x6D - ??? */ 0, 0, 0, +/* 0x6E - ??? */ 0, 0, 0, +/* 0x6F - ??? */ 0, 0, 0, +/* 0x70 - ??? */ 0, 0, 0, +/* 0x71 - ??? */ 0, 0, 0, +/* 0x72 - ??? */ 0, 0, 0, +/* 0x73 - ??? */ 0, 0, 0, +/* 0x74 - ??? */ 0, 0, 0, +/* 0x75 - ??? */ 0, 0, 0, +/* 0x76 - ??? */ 0, 0, 0, +/* 0x77 - ??? */ 0, 0, 0, +/* 0x78 - ??? */ 0, 0, 0, +/* 0x78 - ??? */ 0, 0, 0, +/* 0x7A - ??? */ 0, 0, 0, +/* 0x7B - ??? */ 0, 0, 0, +/* 0x7C - ??? */ 0, 0, 0, +/* 0x7D - ??? */ 0, 0, 0, +/* 0x7E - ??? */ 0, 0, 0, +/* 0x7F - ??? */ 0, 0, 0 }; /*====================================================================================* - Appendix: Scan code set 1 + Appendix: Scan code set 1 *====================================================================================* -KEY MAKE BREAK ----- KEY MAKE BREAK ----- KEY MAKE BREAK +KEY MAKE BREAK ----- KEY MAKE BREAK ----- KEY MAKE BREAK -------------------------------------------------------------------------------------- -A 1E 9E 9 0A 8A [ 1A 9A -B 30 B0 ` 29 89 INSERT E0,52 E0,D2 -C 2E AE - 0C 8C HOME E0,47 E0,C7 -D 20 A0 = 0D 8D PG UP E0,49 E0,C9 -E 12 92 \ 2B AB DELETE E0,53 E0,D3 -F 21 A1 BKSP 0E 8E END E0,4F E0,CF -G 22 A2 SPACE 39 B9 PG DN E0,51 E0,D1 -H 23 A3 TAB 0F 8F U ARROW E0,48 E0,C8 -I 17 97 CAPS 3A BA L ARROW E0,4B E0,CB -J 24 A4 L SHFT 2A AA D ARROW E0,50 E0,D0 -K 25 A5 L CTRL 1D 9D R ARROW E0,4D E0,CD -L 26 A6 L GUI E0,5B E0,DB NUM 45 C5 -M 32 B2 L ALT 38 B8 KP / E0,35 E0,B5 -N 31 B1 R SHFT 36 B6 KP * 37 B7 -O 18 98 R CTRL E0,1D E0,9D KP - 4A CA -P 19 99 R GUI E0,5C E0,DC KP + 4E CE -Q 10 19 R ALT E0,38 E0,B8 KP EN E0,1C E0,9C -R 13 93 APPS E0,5D E0,DD KP . 53 D3 -S 1F 9F ENTER 1C 9C KP 0 52 D2 -T 14 94 ESC 01 81 KP 1 4F CF -U 16 96 F1 3B BB KP 2 50 D0 -V 2F AF F2 3C BC KP 3 51 D1 -W 11 91 F3 3D BD KP 4 4B CB -X 2D AD F4 3E BE KP 5 4C CC -Y 15 95 F5 3F BF KP 6 4D CD -Z 2C AC F6 40 C0 KP 7 47 C7 -0 0B 8B F7 41 C1 KP 8 48 C8 -1 02 82 F8 42 C2 KP 9 49 C9 -2 03 83 F9 43 C3 ] 1B 9B -3 04 84 F10 44 C4 ; 27 A7 -4 05 85 F11 57 D7 ' 28 A8 -5 06 86 F12 58 D8 , 33 B3 +A 1E 9E 9 0A 8A [ 1A 9A +B 30 B0 ` 29 89 INSERT E0,52 E0,D2 +C 2E AE - 0C 8C HOME E0,47 E0,C7 +D 20 A0 = 0D 8D PG UP E0,49 E0,C9 +E 12 92 \ 2B AB DELETE E0,53 E0,D3 +F 21 A1 BKSP 0E 8E END E0,4F E0,CF +G 22 A2 SPACE 39 B9 PG DN E0,51 E0,D1 +H 23 A3 TAB 0F 8F U ARROW E0,48 E0,C8 +I 17 97 CAPS 3A BA L ARROW E0,4B E0,CB +J 24 A4 L SHFT 2A AA D ARROW E0,50 E0,D0 +K 25 A5 L CTRL 1D 9D R ARROW E0,4D E0,CD +L 26 A6 L GUI E0,5B E0,DB NUM 45 C5 +M 32 B2 L ALT 38 B8 KP / E0,35 E0,B5 +N 31 B1 R SHFT 36 B6 KP * 37 B7 +O 18 98 R CTRL E0,1D E0,9D KP - 4A CA +P 19 99 R GUI E0,5C E0,DC KP + 4E CE +Q 10 19 R ALT E0,38 E0,B8 KP EN E0,1C E0,9C +R 13 93 APPS E0,5D E0,DD KP . 53 D3 +S 1F 9F ENTER 1C 9C KP 0 52 D2 +T 14 94 ESC 01 81 KP 1 4F CF +U 16 96 F1 3B BB KP 2 50 D0 +V 2F AF F2 3C BC KP 3 51 D1 +W 11 91 F3 3D BD KP 4 4B CB +X 2D AD F4 3E BE KP 5 4C CC +Y 15 95 F5 3F BF KP 6 4D CD +Z 2C AC F6 40 C0 KP 7 47 C7 +0 0B 8B F7 41 C1 KP 8 48 C8 +1 02 82 F8 42 C2 KP 9 49 C9 +2 03 83 F9 43 C3 ] 1B 9B +3 04 84 F10 44 C4 ; 27 A7 +4 05 85 F11 57 D7 ' 28 A8 +5 06 86 F12 58 D8 , 33 B3 -6 07 87 PRTSCRN E0,2A E0,B7 . 34 B4 - E0,37 E0,AA +6 07 87 PRTSCRN E0,2A E0,B7 . 34 B4 + E0,37 E0,AA -7 08 88 SCROLL 46 C6 / 35 B5 +7 08 88 SCROLL 46 C6 / 35 B5 -8 09 89 PAUSE E1,1D,45 -NONE- - E1,9D,C5 +8 09 89 PAUSE E1,1D,45 -NONE- + E1,9D,C5 ----------------- ACPI Scan Codes: ------------------------------------------- -Key Make Code Break Code +Key Make Code Break Code ------------------------------------------- -Power E0, 5E E0, DE -Sleep E0, 5F E0, DF -Wake E0, 63 E0, E3 +Power E0, 5E E0, DE +Sleep E0, 5F E0, DF +Wake E0, 63 E0, E3 ------------------------------- Windows Multimedia Scan Codes: ------------------------------------------- -Key Make Code Break Code +Key Make Code Break Code ------------------------------------------- -Next Track E0, 19 E0, 99 -Previous Track E0, 10 E0, 90 -Stop E0, 24 E0, A4 -Play/Pause E0, 22 E0, A2 -Mute E0, 20 E0, A0 -Volume Up E0, 30 E0, B0 -Volume Down E0, 2E E0, AE -Media Select E0, 6D E0, ED -E-Mail E0, 6C E0, EC -Calculator E0, 21 E0, A1 -My Computer E0, 6B E0, EB -WWW Search E0, 65 E0, E5 -WWW Home E0, 32 E0, B2 -WWW Back E0, 6A E0, EA -WWW Forward E0, 69 E0, E9 -WWW Stop E0, 68 E0, E8 -WWW Refresh E0, 67 E0, E7 -WWW Favorites E0, 66 E0, E6 +Next Track E0, 19 E0, 99 +Previous Track E0, 10 E0, 90 +Stop E0, 24 E0, A4 +Play/Pause E0, 22 E0, A2 +Mute E0, 20 E0, A0 +Volume Up E0, 30 E0, B0 +Volume Down E0, 2E E0, AE +Media Select E0, 6D E0, ED +E-Mail E0, 6C E0, EC +Calculator E0, 21 E0, A1 +My Computer E0, 6B E0, EB +WWW Search E0, 65 E0, E5 +WWW Home E0, 32 E0, B2 +WWW Back E0, 6A E0, EA +WWW Forward E0, 69 E0, E9 +WWW Stop E0, 68 E0, E8 +WWW Refresh E0, 67 E0, E7 +WWW Favorites E0, 66 E0, E6 *=====================================================================================*/ diff --git a/bsp/x86/drivers/serial.c b/bsp/x86/drivers/serial.c index 64830135fc..58cc9dee90 100644 --- a/bsp/x86/drivers/serial.c +++ b/bsp/x86/drivers/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,17 +24,17 @@ */ void rt_serial_init(void) { - outb(COM1+3,0x80); /* set DLAB of line control reg */ - outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */ - outb(COM1+1,0x00); /* MS of divisor */ - outb(COM1+3,0x03); /* reset DLAB */ - outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */ - outb(COM1+1,0x0d); /* enable all intrs but writes */ - inb(COM1); /* read data port to reset things (?) */ + outb(COM1+3,0x80); /* set DLAB of line control reg */ + outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */ + outb(COM1+1,0x00); /* MS of divisor */ + outb(COM1+3,0x03); /* reset DLAB */ + outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */ + outb(COM1+1,0x0d); /* enable all intrs but writes */ + inb(COM1); /* read data port to reset things (?) */ } /** - * This function read a character from serial without interrupt enable mode + * This function read a character from serial without interrupt enable mode * * @return the read char */ @@ -53,13 +53,13 @@ char rt_serial_getc(void) void rt_serial_putc(const char c) { int val; - + while(1) { - if ((val = inb(COM1+COMSTATUS)) & THRE) + if ((val = inb(COM1+COMSTATUS)) & THRE) break; } - + outb(COM1+COMWRITE, c&0xff); } diff --git a/bsp/x86/src/hello.c b/bsp/x86/src/hello.c index a075f18ef1..b4018617b5 100644 --- a/bsp/x86/src/hello.c +++ b/bsp/x86/src/hello.c @@ -9,28 +9,28 @@ extern void rt_kprintf(const char* fmt,...); int add(int a, int b) { - return a+b; + return a+b; } int main(int argc, char* argv[]) { - int i; - char str[32] = "Hello World\n"; + int i; + char str[32] = "Hello World\n"; - for(i=0; i<argc; i++) - { - printf("argv[%d]='%s'\n", i, argv[i]); - } + for(i=0; i<argc; i++) + { + printf("argv[%d]='%s'\n", i, argv[i]); + } - printf(str); + printf(str); - printf("g_str address is %ph\n",g_str); - puts(g_str); + printf("g_str address is %ph\n",g_str); + puts(g_str); - rt_kprintf("\nnative rt_kprintf a(%ph)=%d, b(%ph)=%d\n", &a, a, &b, b); + rt_kprintf("\nnative rt_kprintf a(%ph)=%d, b(%ph)=%d\n", &a, a, &b, b); - printf("%d+%d=%d\n", 4, 5, add(4, 5)); + printf("%d+%d=%d\n", 4, 5, add(4, 5)); - return 0xdeadbeef; + return 0xdeadbeef; } |