diff options
| author | bernard.xiong <[email protected]> | 2009-07-02 23:19:19 +0000 |
|---|---|---|
| committer | bernard.xiong <[email protected]> | 2009-07-02 23:19:19 +0000 |
| commit | c462da5dd02f77e4440958cdfb12173cb3cc8cf3 (patch) | |
| tree | b20fe8ab9aa22f6bc08a7deced7a3240ebe3b815 /bsp | |
| parent | 99922cdf19851bf89989d997ae4a0c02f6eed523 (diff) | |
import lm3s, lpc2148/lpc2478, x86/qemu, AT91SAM7S/7X, s3c44b0, STM32F103ZE bsp
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@5 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'bsp')
57 files changed, 6202 insertions, 0 deletions
diff --git a/bsp/lpc2148/application.c b/bsp/lpc2148/application.c new file mode 100644 index 0000000000..6c1f0113cc --- /dev/null +++ b/bsp/lpc2148/application.c @@ -0,0 +1,140 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-06-05 Bernard the first version + */
+ +#include <rtthread.h>
+#include <finsh.h>
+ +/** + * @addtogroup LPC2148 + */ +/*@{*/
+
+#ifdef RT_USING_DFS
+/* dfs init */
+#include <dfs_init.h>
+/* dfs filesystem:FAT filesystem init */
+#include <dfs_fat.h>
+/* dfs filesystem:EFS filesystem init */
+#include <dfs_efs.h>
+/* dfs Filesystem APIs */
+#include <dfs_fs.h>
+#endif
+
+#ifdef RT_USING_LWIP
+#include <lwip/sys.h>
+#endif
+
+#ifdef RT_USING_RTGUI
+#include <rtgui/rtgui.h>
+#endif
+
+/* thread phase init */
+void rt_init_thread_entry(void *parameter)
+{
+/* Filesystem Initialization */
+#ifdef RT_USING_DFS
+ {
+ /* init the device filesystem */
+ dfs_init();
+ /* init the efsl filesystam*/
+ efsl_init();
+
+ /* mount sd card fat partition 1 as root directory */
+ if (dfs_mount("sd0", "/", "efs", 0, 0) == 0)
+ rt_kprintf("File System initialized!\n");
+ else
+ rt_kprintf("File System init failed!\n");
+ }
+#endif
+
+/* LwIP Initialization */
+#ifdef RT_USING_LWIP
+ {
+ extern void lwip_sys_init(void);
+
+ /* init lwip system */
+ lwip_sys_init();
+ rt_kprintf("TCP/IP initialized!\n");
+ }
+#endif
+}
+ +/************** LED BLINK *******************/
+#include "lpc214x.h"
+#define LED1 ( 1<<16) //P1
+#define LED2 ( 1<<17) //P1
+#define LED3 ( 1<<18) //P1
+#define LED4 ( 1<<19) //P1
+char thread3_stack[512];
+struct rt_thread thread3;
+void thread3_entry(void* parameter)
+{
+ volatile unsigned int i;
+ IO1DIR |= LED1;
+ while(1)
+ {
+ IO1CLR = LED1;
+ rt_thread_delay(20);
+ IO1SET = LED1;
+ rt_thread_delay(20);
+ }
+}
+
+char thread4_stack[512];
+struct rt_thread thread4;
+void thread4_entry(void* parameter)
+{
+ volatile unsigned int i;
+ IO1DIR |= LED2;
+ while(1)
+ {
+ IO1CLR = LED2;
+ rt_thread_delay(30);
+ IO1SET = LED2;
+ rt_thread_delay(30);
+ }
+}
+/************** LED BLINK *******************/
+ +int rt_application_init() +{
+ rt_thread_init(&thread3, + "led1", + thread3_entry, RT_NULL, + &thread3_stack[0], sizeof(thread3_stack), + 20, 10);
+ + rt_thread_init(&thread4, + "led2", + thread4_entry, RT_NULL, + &thread4_stack[0], sizeof(thread4_stack), + 25, 8); + rt_thread_startup(&thread3); + rt_thread_startup(&thread4);
+
+ {
+ rt_thread_t init_thread;
+
+ init_thread = rt_thread_create("init",
+ rt_init_thread_entry, RT_NULL,
+ 1024, 8, 5);
+ rt_thread_startup(init_thread);
+ }
+
+ rt_kprintf("enter list() to get function list!\n");
+ + return 0; +}
+ +/*@}*/ diff --git a/bsp/lpc2148/board.c b/bsp/lpc2148/board.c new file mode 100644 index 0000000000..6d029a4a80 --- /dev/null +++ b/bsp/lpc2148/board.c @@ -0,0 +1,106 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard first implementation + */ + +#include <rthw.h> +#include <rtthread.h>
+ +#include "lpc214x.h"
+#include "board.h"
+ +/** + * @addtogroup LPC2148 + */ +/*@{*/ + +/** + * This is the timer interrupt service routine. + * @param vector the irq number for timer + */ +void rt_hw_timer_handler(int vector) +{
+ rt_tick_increase();
+
+ /* clear interrupt flag */
+ T0IR |= 0x01;
+
+ /* acknowledge Interrupt */
+ VICVectAddr = 0;
+} + +/** + * This function is used to display a string on console, normally, it's + * invoked by rt_kprintf + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{
+ while (*str) + { + if (*str=='\n')
+ {
+ while (!(U0LSR & 0x20));
+ U0THR = '\r';
+ }
+ + while (!(U0LSR & 0x20));
+ U0THR = *str;
+
+ str ++;
+ }
+}
+
+#define BAUD_RATE 115200
+#define U0PINS 0x05
+void rt_hw_console_init()
+{
+ /* Enable RxD and TxD pins */
+ PINSEL0 = U0PINS;
+
+ /* 8 bits, no Parity, 1 Stop bit */
+ U0LCR = 0x83;
+
+ /* Setup Baudrate */
+ U0DLL = (PCLK/16/BAUD_RATE) & 0xFF;
+ U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF;
+
+ /* DLAB = 0 */
+ U0LCR = 0x03;
+}
+
+/** + * This function will initial sam7x256 board. + */ +void rt_hw_board_init() +{
+ /* console init */
+ rt_hw_console_init();
+
+ /* prescaler = 0*/
+ T0PR = 0;
+ T0PC = 0;
+
+ /* reset and enable MR0 interrupt */
+ T0MCR = 0x3;
+ T0MR0 = PCLK / RT_TICK_PER_SECOND;
+
+ /* enable timer 0 */
+ T0TCR = 1;
+
+ /* install timer handler */ + rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL); + rt_hw_interrupt_umask(TIMER0_INT); +}
+ +/*@}*/ diff --git a/bsp/lpc2148/board.h b/bsp/lpc2148/board.h new file mode 100644 index 0000000000..beec781a62 --- /dev/null +++ b/bsp/lpc2148/board.h @@ -0,0 +1,28 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-02-16 Bernard add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__
+#include <rtthread.h>
+
+#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ +#define PCLK 15000000 /* CCLK/4, use default */
+ +void rt_hw_board_init(void);
+
+#ifdef RT_USING_FINSH +void rt_hw_finsh_init(void);
+#endif
+ +#endif diff --git a/bsp/lpc2148/dm9000.c b/bsp/lpc2148/dm9000.c new file mode 100644 index 0000000000..f64dbde160 --- /dev/null +++ b/bsp/lpc2148/dm9000.c @@ -0,0 +1,157 @@ +#include <rtthread.h>
+#include "dm9000.h"
+
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+
+#define MAX_ADDR_LEN 6
+struct rt_dm9000_eth
+{
+ /* inherit from ethernet device */
+ struct eth_device parent;
+
+ /* interface address info. */
+ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
+};
+static struct rt_dm9000_eth dm9000_device;
+
+/* interrupt service routine */
+void rt_dm9000_isr(int irqno)
+{
+ rt_uint32_t status;
+
+ if (status) // if receive packet
+ {
+ rt_err_t result;
+
+ /* a frame has been received */
+ result = eth_device_ready(&(dm9000_device.parent));
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ if (status) // if finished packet transmission
+ {
+ }
+}
+
+/* RT-Thread Device Interface */
+/* initialize the interface */
+
+static rt_err_t rt_dm9000_init(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_dm9000_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_err_t rt_dm9000_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+ switch(cmd)
+ {
+ case NIOCTL_GADDR:
+ /* get mac address */
+ if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
+ else return -RT_ERROR;
+ break;
+
+ default :
+ break;
+ }
+
+ return RT_EOK;
+}
+
+/* ethernet device interface */
+/* transmit packet. */
+rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
+{
+ struct pbuf* q;
+ rt_uint32_t len;
+ rt_uint8_t* ptr;
+
+ for (q = p; q != NULL; q = q->next)
+ {
+ len = q->len;
+ ptr = q->payload;
+
+ /* write data to device */
+ }
+
+ return RT_EOK;
+}
+
+/* reception packet. */
+struct pbuf *rt_dm9000_rx(rt_device_t dev)
+{
+ struct pbuf* p;
+ rt_uint32_t len;
+
+ /* init p pointer */
+ p = RT_NULL;
+
+ if (1) // if there is packet in device
+ {
+ /* get one packet length */
+ len = 0; // packet length
+
+ /* allocate buffer */
+ p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
+
+ if (p != RT_NULL)
+ {
+ rt_uint8_t* data;
+ struct pbuf* q;
+
+ for (q = p; q != RT_NULL; q= q->next)
+ {
+ data = q->payload;
+ len = q->len;
+
+ /* read data from device */
+ }
+ }
+ }
+ else
+ {
+ /* restore interrupt */
+ }
+
+ return p;
+}
+
+void rt_hw_dm9000_init()
+{
+ dm9000_device.parent.parent.init = rt_dm9000_init;
+ dm9000_device.parent.parent.open = rt_dm9000_open;
+ dm9000_device.parent.parent.close = rt_dm9000_close;
+ dm9000_device.parent.parent.read = rt_dm9000_read;
+ dm9000_device.parent.parent.write = rt_dm9000_write;
+ dm9000_device.parent.parent.control = rt_dm9000_control;
+ dm9000_device.parent.parent.private = RT_NULL;
+
+ dm9000_device.parent.eth_rx = rt_dm9000_rx;
+ dm9000_device.parent.eth_tx = rt_dm9000_tx;
+
+ rt_device_register((rt_device_t)&dm9000_device,
+ "E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX);
+}
diff --git a/bsp/lpc2148/dm9000.h b/bsp/lpc2148/dm9000.h new file mode 100644 index 0000000000..402a2fe7ff --- /dev/null +++ b/bsp/lpc2148/dm9000.h @@ -0,0 +1,6 @@ +#ifndef __DM9000_H__
+#define __DM9000_H__
+
+void rt_hw_dm9000_init(void);
+
+#endif
diff --git a/bsp/lpc2148/project.Opt b/bsp/lpc2148/project.Opt new file mode 100644 index 0000000000..55b3f79ea0 --- /dev/null +++ b/bsp/lpc2148/project.Opt @@ -0,0 +1,130 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+ cExt (*.c)
+ aExt (*.s*; *.src; *.a*)
+ oExt (*.obj)
+ lExt (*.lib)
+ tExt (*.txt; *.h; *.inc)
+ pExt (*.plm)
+ CppX (*.cpp)
+ DaveTm { 0,0,0,0,0,0,0,0 }
+
+Target (RT-Thread/LPC2148), 0x0004 // Tools: 'ARM-ADS'
+GRPOPT 1,(Startup),1,0,0
+GRPOPT 2,(Kernel),0,0,0
+GRPOPT 3,(LPC214x),0,0,0
+GRPOPT 4,(finsh),0,0,0
+GRPOPT 5,(Filesystem),0,0,0
+GRPOPT 6,(LwIP),0,0,0
+
+OPTFFF 1,1,1,150994944,0,0,0,0,<.\application.c><application.c>
+OPTFFF 1,2,1,0,0,0,0,0,<.\board.c><board.c>
+OPTFFF 1,3,1,0,0,0,0,0,<.\startup.c><startup.c>
+OPTFFF 1,4,1,0,0,0,0,0,<.\dm9000.c><dm9000.c>
+OPTFFF 1,5,1,0,0,0,0,0,<.\sd.c><sd.c>
+OPTFFF 1,6,5,0,0,0,0,0,<.\rtconfig.h><rtconfig.h>
+OPTFFF 2,7,1,0,0,0,0,0,<..\..\src\clock.c><clock.c>
+OPTFFF 2,8,1,150994944,0,0,0,0,<..\..\src\device.c><device.c>
+OPTFFF 2,9,1,0,0,0,0,0,<..\..\src\ipc.c><ipc.c>
+OPTFFF 2,10,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c>
+OPTFFF 2,11,1,0,0,0,0,0,<..\..\src\object.c><object.c>
+OPTFFF 2,12,1,0,0,0,0,0,<..\..\src\timer.c><timer.c>
+OPTFFF 2,13,1,0,0,0,0,0,<..\..\src\idle.c><idle.c>
+OPTFFF 2,14,1,0,0,0,0,0,<..\..\src\irq.c><irq.c>
+OPTFFF 2,15,1,0,0,0,0,0,<..\..\src\mem.c><mem.c>
+OPTFFF 2,16,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c>
+OPTFFF 2,17,1,0,0,0,0,0,<..\..\src\slab.c><slab.c>
+OPTFFF 2,18,1,0,0,0,0,0,<..\..\src\thread.c><thread.c>
+OPTFFF 2,19,1,0,0,0,0,0,<..\..\src\kservice.c><kservice.c>
+OPTFFF 3,20,1,0,0,0,0,0,<..\..\libcpu\arm\lpc214x\serial.c><serial.c>
+OPTFFF 3,21,1,0,0,0,0,0,<..\..\libcpu\arm\lpc214x\interrupt.c><interrupt.c>
+OPTFFF 3,22,1,0,0,0,0,0,<..\..\libcpu\arm\lpc214x\cpu.c><cpu.c>
+OPTFFF 3,23,1,0,0,0,0,0,<..\..\libcpu\arm\lpc214x\trap.c><trap.c>
+OPTFFF 3,24,1,0,0,0,0,0,<..\..\libcpu\arm\lpc214x\stack.c><stack.c>
+OPTFFF 3,25,2,0,0,0,0,0,<..\..\libcpu\arm\lpc214x\start_rvds.s><start_rvds.s>
+OPTFFF 3,26,2,0,0,0,0,0,<..\..\libcpu\arm\lpc214x\context_rvds.s><context_rvds.s>
+OPTFFF 4,27,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+OPTFFF 4,28,1,0,0,0,0,0,<..\..\finsh\finsh_error.c><finsh_error.c>
+OPTFFF 4,29,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+OPTFFF 4,30,1,0,0,0,0,0,<..\..\finsh\finsh_init.c><finsh_init.c>
+OPTFFF 4,31,1,0,0,0,0,0,<..\..\finsh\finsh_node.c><finsh_node.c>
+OPTFFF 4,32,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+OPTFFF 4,33,1,0,0,0,0,0,<..\..\finsh\finsh_token.c><finsh_token.c>
+OPTFFF 4,34,1,0,0,0,0,0,<..\..\finsh\finsh_var.c><finsh_var.c>
+OPTFFF 4,35,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+OPTFFF 4,36,1,0,0,0,0,0,<..\..\finsh\shell.c><shell.c>
+OPTFFF 4,37,1,0,0,0,0,0,<..\..\finsh\symbol.c><symbol.c>
+OPTFFF 4,38,1,0,0,0,0,0,<..\..\finsh\cmd.c><cmd.c>
+OPTFFF 4,39,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+OPTFFF 5,40,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c>
+OPTFFF 5,41,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c>
+OPTFFF 5,42,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c>
+OPTFFF 5,43,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c>
+OPTFFF 5,44,1,301989888,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c>
+OPTFFF 5,45,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c>
+OPTFFF 5,46,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c>
+OPTFFF 5,47,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c>
+OPTFFF 5,48,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c>
+OPTFFF 5,49,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c>
+OPTFFF 5,50,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c>
+OPTFFF 5,51,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c>
+OPTFFF 5,52,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c>
+OPTFFF 5,53,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c>
+OPTFFF 5,54,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c>
+OPTFFF 5,55,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c>
+OPTFFF 5,56,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c>
+OPTFFF 6,57,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c><etharp.c>
+OPTFFF 6,58,1,150994944,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c>
+OPTFFF 6,59,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c><udp.c>
+OPTFFF 6,60,1,0,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c><dhcp.c>
+OPTFFF 6,61,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c><dns.c>
+OPTFFF 6,62,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c><init.c>
+OPTFFF 6,63,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c>
+OPTFFF 6,64,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c><netif.c>
+OPTFFF 6,65,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c><pbuf.c>
+OPTFFF 6,66,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c><raw.c>
+OPTFFF 6,67,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c><stats.c>
+OPTFFF 6,68,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c><sys.c>
+OPTFFF 6,69,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp.c><tcp.c>
+OPTFFF 6,70,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c>
+OPTFFF 6,71,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c>
+OPTFFF 6,72,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
+OPTFFF 6,73,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c>
+OPTFFF 6,74,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c>
+OPTFFF 6,75,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c>
+OPTFFF 6,76,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c>
+OPTFFF 6,77,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
+OPTFFF 6,78,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c>
+OPTFFF 6,79,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
+OPTFFF 6,80,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c><tcpip.c>
+OPTFFF 6,81,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c><api_lib.c>
+OPTFFF 6,82,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c><api_msg.c>
+OPTFFF 6,83,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c><err.c>
+OPTFFF 6,84,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c><netbuf.c>
+OPTFFF 6,85,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c><netdb.c>
+OPTFFF 6,86,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c><netifapi.c>
+OPTFFF 6,87,1,0,0,0,0,0,<..\..\net\lwip\src\api\sockets.c><sockets.c>
+OPTFFF 6,88,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c>
+OPTFFF 6,89,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c>
+
+
+TARGOPT 1, (RT-Thread/LPC2148)
+ ADSCLK=12000000
+ OPTTT 1,1,1,0
+ OPTHX 1,65535,0,0,0
+ OPTLX 79,66,8,<.\objs\>
+ OPTOX 16
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+ OPTXL 1,1,1,1,1,1,1,0,0
+ OPTFL 1,0,1
+ OPTAX 0
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC2148)(SARM.DLL)()(TARMP.DLL)(-pLPC2148)
+ OPTDBG 48125,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
+ OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(153=-1,-1,-1,-1,0)(154=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(145=-1,-1,-1,-1,0)(147=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(113=556,103,931,655,0)(112=-1,-1,-1,-1,0)(137=-1,-1,-1,-1,0)(138=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(146=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(143=-1,-1,-1,-1,0)(144=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
+ OPTKEY 0,(ARMDBGFLAGS)(-T5F)
+ OPTDF 0xB0
+ OPTLE <>
+ OPTLC <>
+EndOpt
+
diff --git a/bsp/lpc2148/project.Uv2 b/bsp/lpc2148/project.Uv2 new file mode 100644 index 0000000000..f1f82c90c8 --- /dev/null +++ b/bsp/lpc2148/project.Uv2 @@ -0,0 +1,193 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (RT-Thread/LPC2148), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Startup)
+Group (Kernel)
+Group (LPC214x)
+Group (finsh)
+Group (Filesystem)
+Group (LwIP)
+
+File 1,1,<.\application.c><application.c>
+File 1,1,<.\board.c><board.c>
+File 1,1,<.\startup.c><startup.c>
+File 1,1,<.\dm9000.c><dm9000.c>
+File 1,1,<.\sd.c><sd.c>
+File 1,5,<.\rtconfig.h><rtconfig.h>
+File 2,1,<..\..\src\clock.c><clock.c>
+File 2,1,<..\..\src\device.c><device.c>
+File 2,1,<..\..\src\ipc.c><ipc.c>
+File 2,1,<..\..\src\mempool.c><mempool.c>
+File 2,1,<..\..\src\object.c><object.c>
+File 2,1,<..\..\src\timer.c><timer.c>
+File 2,1,<..\..\src\idle.c><idle.c>
+File 2,1,<..\..\src\irq.c><irq.c>
+File 2,1,<..\..\src\mem.c><mem.c>
+File 2,1,<..\..\src\scheduler.c><scheduler.c>
+File 2,1,<..\..\src\slab.c><slab.c>
+File 2,1,<..\..\src\thread.c><thread.c>
+File 2,1,<..\..\src\kservice.c><kservice.c>
+File 3,1,<..\..\libcpu\arm\lpc214x\serial.c><serial.c>
+File 3,1,<..\..\libcpu\arm\lpc214x\interrupt.c><interrupt.c>
+File 3,1,<..\..\libcpu\arm\lpc214x\cpu.c><cpu.c>
+File 3,1,<..\..\libcpu\arm\lpc214x\trap.c><trap.c>
+File 3,1,<..\..\libcpu\arm\lpc214x\stack.c><stack.c>
+File 3,2,<..\..\libcpu\arm\lpc214x\start_rvds.s><start_rvds.s>
+File 3,2,<..\..\libcpu\arm\lpc214x\context_rvds.s><context_rvds.s>
+File 4,1,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+File 4,1,<..\..\finsh\finsh_error.c><finsh_error.c>
+File 4,1,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+File 4,1,<..\..\finsh\finsh_init.c><finsh_init.c>
+File 4,1,<..\..\finsh\finsh_node.c><finsh_node.c>
+File 4,1,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+File 4,1,<..\..\finsh\finsh_token.c><finsh_token.c>
+File 4,1,<..\..\finsh\finsh_var.c><finsh_var.c>
+File 4,1,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+File 4,1,<..\..\finsh\shell.c><shell.c>
+File 4,1,<..\..\finsh\symbol.c><symbol.c>
+File 4,1,<..\..\finsh\cmd.c><cmd.c>
+File 4,1,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+File 5,1,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c>
+File 5,1,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c>
+File 5,1,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c>
+File 5,1,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c>
+File 5,1,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c>
+File 5,1,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c>
+File 5,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c>
+File 6,1,<..\..\net\lwip\src\netif\etharp.c><etharp.c>
+File 6,1,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c>
+File 6,1,<..\..\net\lwip\src\core\udp.c><udp.c>
+File 6,1,<..\..\net\lwip\src\core\dhcp.c><dhcp.c>
+File 6,1,<..\..\net\lwip\src\core\dns.c><dns.c>
+File 6,1,<..\..\net\lwip\src\core\init.c><init.c>
+File 6,1,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c>
+File 6,1,<..\..\net\lwip\src\core\netif.c><netif.c>
+File 6,1,<..\..\net\lwip\src\core\pbuf.c><pbuf.c>
+File 6,1,<..\..\net\lwip\src\core\raw.c><raw.c>
+File 6,1,<..\..\net\lwip\src\core\stats.c><stats.c>
+File 6,1,<..\..\net\lwip\src\core\sys.c><sys.c>
+File 6,1,<..\..\net\lwip\src\core\tcp.c><tcp.c>
+File 6,1,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c>
+File 6,1,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c>
+File 6,1,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
+File 6,1,<..\..\net\lwip\src\api\tcpip.c><tcpip.c>
+File 6,1,<..\..\net\lwip\src\api\api_lib.c><api_lib.c>
+File 6,1,<..\..\net\lwip\src\api\api_msg.c><api_msg.c>
+File 6,1,<..\..\net\lwip\src\api\err.c><err.c>
+File 6,1,<..\..\net\lwip\src\api\netbuf.c><netbuf.c>
+File 6,1,<..\..\net\lwip\src\api\netdb.c><netdb.c>
+File 6,1,<..\..\net\lwip\src\api\netifapi.c><netifapi.c>
+File 6,1,<..\..\net\lwip\src\api\sockets.c><sockets.c>
+File 6,1,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c>
+File 6,1,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c>
+
+
+Options 1,0,0 // Target 'RT-Thread/LPC2148'
+ Device (LPC2148)
+ Vendor (NXP (founded by Philips))
+ Cpu (IRAM(0x40000000-0x40007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
+ FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 38400 1))
+ StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))
+ FlashDR (UL2ARM(-U268761108 -O7 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000))
+ DevID (3880)
+ Rgf (LPC214X.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (�Philips\)
+ OrgReg (�Philips\)
+ TgStat=16
+ OutDir (.\objs\)
+ OutName (rtthread-lpc2148)
+ GenApp=1
+ GenLib=0
+ GenHex=0
+ Debug=1
+ Browse=1
+ LstDir (.\objs\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP (ARM7TDMI)
+ RVDEV ()
+ ADSTFLGA { 0,12,0,2,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,64,0,128,0,0 }
+ OCMADSIROM { 1,0,0,0,0,0,0,8,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,128,0,0,0,0,0,0,0,0,0,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD (.;..\..\include;..\..\libcpu\arm\lpc214x;..\..\finsh;..\..\net\lwip\src;..\..\net\lwip\src\include;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00000000)
+ ADSLDDA (0x40000000)
+ ADSLDSC (.\rtthread-lpc2148.sct)
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC (--keep __fsym_* --keep __vsym_*)
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC2148)(SARM.DLL)()(TARMP.DLL)(-pLPC2148)
+ OPTDBG 48125,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
+ FLASH1 { 2,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (BIN\UL2ARM.DLL)
+ FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1))
+ FLASH4 ()
+EndOpt
+
diff --git a/bsp/lpc2148/rtconfig.h b/bsp/lpc2148/rtconfig.h new file mode 100644 index 0000000000..14d1ef4e1a --- /dev/null +++ b/bsp/lpc2148/rtconfig.h @@ -0,0 +1,138 @@ +/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX 32
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using Faset Event*/
+/* #define RT_USING_FASTEVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+
+/* Using SLAB Allocator*/
+/* #define RT_USING_SLAB */
+
+/* SECTION: Device System */
+/* Using Device System*/
+#define RT_USING_DEVICE
+#define RT_USING_UART1
+#define RT_USING_UART2
+#define RT_UART_RX_BUFFER_SIZE 64
+
+/* SECTION: Console options */
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: emulator options */
+/* Using QEMU or SkyEye*/
+/* #define RT_USING_EMULATOR */
+
+/* SECTION: a mini libc */
+/* Using mini libc library*/
+/* #define RT_USING_MINILIBC */
+
+/* SECTION: C++ support */
+/* Using C++ support*/
+/* #define RT_USING_CPLUSPLUS */
+
+/* SECTION: DFS options */ +#define RT_USING_DFS +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 8
+ +/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* Using lighweight TCP/IP protocol stack*/
+#define RT_USING_LWIP
+
+/* Trace LwIP protocol*/
+/* #define RT_LWIP_DEBUG */
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+
+/* Enable IGMP protocol*/
+#define RT_LWIP_IGMP
+
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+
+/* Enable SNMP protocol*/
+/* #define RT_LWIP_SNMP */
+
+/* Using DHCP*/
+/* #define RT_LWIP_DHCP */
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 0
+#define RT_LWIP_IPADDR3 30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 0
+#define RT_LWIP_GWADDR3 1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+
+#endif
diff --git a/bsp/lpc2148/sd.c b/bsp/lpc2148/sd.c new file mode 100644 index 0000000000..9961cee5ec --- /dev/null +++ b/bsp/lpc2148/sd.c @@ -0,0 +1,93 @@ +#include <rtthread.h>
+#include <dfs_fs.h>
+#include <lpc214x.h>
+
+#include "sd.h"
+
+static struct rt_device sd;
+static struct dfs_partition part;
+
+static rt_err_t rt_sdcard_init(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_sdcard_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ /* append partition offset */
+ pos += part.offset * 512;
+
+ return 0;
+}
+
+static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ /* append partition offset */
+ pos += part.offset * 512;
+
+ return 0;
+}
+
+static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+ return RT_EOK;
+}
+
+void rt_hw_sdcard_init()
+{
+ rt_size_t length;
+ rt_uint8_t* sector;
+
+ /* sdcard hardware init */
+
+ sd.type = RT_Device_Class_Block;
+ sd.init = rt_sdcard_init;
+ sd.open = rt_sdcard_open;
+ sd.close = rt_sdcard_close;
+ sd.read = rt_sdcard_read;
+ sd.write = rt_sdcard_write;
+ sd.control = rt_sdcard_control;
+ sd.private = RT_NULL;
+
+ /* get the first sector to read partition table */
+ sector = (rt_uint8_t*) rt_malloc (512);
+ if (sector == RT_NULL)
+ {
+ rt_kprintf("allocate partition sector buffer failed\n");
+ return;
+ }
+
+ length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
+ if (length == 512)
+ {
+ rt_err_t status;
+
+ /* get the first partition */
+ status = dfs_filesystem_get_partition(&part, sector, 0);
+ if (status != RT_EOK)
+ {
+ /* there is no partition table */
+ part.offset = 0;
+ part.size = 0;
+ }
+ }
+ else
+ {
+ /* there is no partition table */
+ part.offset = 0;
+ part.size = 0;
+ }
+
+ rt_device_register(&sd,
+ "sd", RT_DEVICE_FLAG_RDWR);
+}
diff --git a/bsp/lpc2148/sd.h b/bsp/lpc2148/sd.h new file mode 100644 index 0000000000..0f38e06dfb --- /dev/null +++ b/bsp/lpc2148/sd.h @@ -0,0 +1,6 @@ +#ifndef __SPI_SD_H__
+#define __SPI_SD_H__
+
+void rt_hw_sdcard_init(void);
+
+#endif
diff --git a/bsp/lpc2148/startup.c b/bsp/lpc2148/startup.c new file mode 100644 index 0000000000..eb9b5d065b --- /dev/null +++ b/bsp/lpc2148/startup.c @@ -0,0 +1,140 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-02-16 Bernard first implementation + */ + +#include <rthw.h> +#include <rtthread.h> +#ifdef RT_USING_FINSH
+#include <finsh.h>
+#endif
+ +#include "board.h" +#ifdef RT_USING_LWIP
+#include <netif/ethernetif.h>
+#include "dm9000.h"
+#endif
+#ifdef RT_USING_DFS
+#include "sd.h"
+#endif
+ +/** + * @addtogroup lpc2148 + */ + +/*@{*/ + +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +#endif + +extern int rt_application_init(void); +extern void rt_show_version(void);
+#ifdef RT_USING_DEVICE
+extern rt_err_t rt_hw_serial_init(void);
+#endif
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+#endif
+
+#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit;
+#else
+extern int __bss_end;
+#endif
+
+/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init hardware interrupt */ + rt_hw_interrupt_init();
+ + /* init board */ + rt_hw_board_init(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + rt_show_version(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+ rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x40008000);
+#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)0x40008000);
+#endif +#endif
+ + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_HOOK /* if the hook is used */ + /* set idle thread hook */ + rt_thread_idle_sethook(0); +#endif
+
+#ifdef RT_USING_DEVICE
+#ifdef RT_USING_DFS
+ /* init sd card */
+ rt_hw_sdcard_init();
+#endif
+
+#ifdef RT_USING_LWIP
+ eth_system_device_init();
+ /* init ethernetif device */
+ rt_hw_dm9000_init();
+#endif
+
+ /* init hardware serial device */
+ rt_hw_serial_init();
+
+ /*init all registed devices*/
+ rt_device_init_all();
+#endif
+ + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +}
+ +int main (void)
+{
+ /* invoke rtthread_startup */
+ rtthread_startup();
+
+ return 0;
+}
+ +/*@}*/ diff --git a/bsp/lpc2478/application.c b/bsp/lpc2478/application.c new file mode 100644 index 0000000000..89515b43d3 --- /dev/null +++ b/bsp/lpc2478/application.c @@ -0,0 +1,72 @@ +/*
+ * File : app.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2008-12-11 xuxinming the first version
+ */
+
+#include <rtthread.h>
+
+/**
+ * @addtogroup LPC2478
+ */
+/*@{*/
+ +char thread1_stack[512]; +char thread2_stack[512]; + +struct rt_thread thread1; +struct rt_thread thread2;
+ +void thread1_entry(void* parameter) +{ + int i; + + while (1) + { + for (i = 0; i < 10; i ++) + { + rt_kprintf("%d\n", i); + rt_thread_delay(100); + } + } +}
+
+void thread2_entry(void* parameter) +{ + int count = 0; + while (1) + { + rt_kprintf("Thread2 count:%d\n", count++);
+ rt_thread_delay(50); + } +} + +int rt_application_init() +{
+ rt_thread_init(&thread1, + "thread1", + thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), + 20, 10);
+ + rt_thread_init(&thread2, + "thread2", + thread2_entry, RT_NULL, + &thread2_stack[0], sizeof(thread2_stack), + 25, 8); + + rt_thread_startup(&thread1); + rt_thread_startup(&thread2); + + return 0; +}
+ +/*@}*/ diff --git a/bsp/lpc2478/board.c b/bsp/lpc2478/board.c new file mode 100644 index 0000000000..c68b8c1300 --- /dev/null +++ b/bsp/lpc2478/board.c @@ -0,0 +1,243 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-12-11 xuxinming first version + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <LPC24xx.h> +#include "board.h" + +/* #define BOARD_DEBUG */ + +#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */ + +/** + * @addtogroup LPC2478 + */ +/*@{*/ + +void rt_timer_handler(int vector) +{ +#ifdef BOARD_DEBUG + rt_kprintf("timer handler, increase a tick\n"); +#endif + + T0IR |= 0x01; /* clear interrupt flag */ + rt_tick_increase(); + VICVectAddr = 0; /* Acknowledge Interrupt */ +} + +/** + * This function will init LPC2478 board + */ +void rt_hw_board_init() +{
+ extern void rt_serial_init(void); + /* init hardware serial */ + rt_serial_init();
+ + T0IR = 0xff; + T0TC = 0; + T0MCR = 0x03; + T0MR0 = (DATA_COUNT);
+ + rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL);
+ rt_hw_interrupt_umask(TIMER0_INT);
+ + T0TCR = 0x01; //enable timer0 counter +} + +#ifdef RT_USING_FINSH +extern void finsh_notify(void); +void rt_serial_isr(int vector) +{ + rt_uint32_t iir;
+
+ if (U0LSR & 0x01)
+ {
+ rt_uint8_t ch;
+
+ while (U0LSR & 0x01)
+ {
+ ch = U0RBR;
+ rt_serial_savechar(ch);
+ }
+
+ /* notify finsh shell thread */
+ finsh_notify();
+ }
+
+ /* clear interrupt source */
+ iir = U0IIR;
+
+ /* acknowledge Interrupt */
+ VICVectAddr = 0;
+} + +void rt_hw_finsh_init() +{
+ /* init UART rx interrupt */
+ U0IER = 0x01;
+ + /* install UART isr */ + rt_hw_interrupt_install(UART0_INT, rt_serial_isr, RT_NULL); + rt_hw_interrupt_umask(UART0_INT); +} +#endif + +/****************************************************************************** +** Function name: TargetInit +** +** Descriptions: Initialize the target board; it is called in a necessary +** place, change it as needed +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void TargetInit(void) +{ + /* Add your codes here */ + return; +} + +/****************************************************************************** +** Function name: GPIOResetInit +** +** Descriptions: Initialize the target board before running the main() +** function; User may change it as needed, but may not +** deleted it. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void GPIOResetInit( void ) +{ + return; +} + +/****************************************************************************** +** Function name: ConfigurePLL +** +** Descriptions: Configure PLL switching to main OSC instead of IRC +** at power up and wake up from power down. +** This routine is used in TargetResetInit() and those +** examples using power down and wake up such as +** USB suspend to resume, ethernet WOL, and power management +** example +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ConfigurePLL ( void ) +{ + unsigned long MValue, NValue; + + if ( PLLSTAT & (1 << 25) ) + { + PLLCON = 1; /* Enable PLL, disconnected */ + PLLFEED = 0xaa; + PLLFEED = 0x55; + } + + PLLCON = 0; /* Disable PLL, disconnected */ + PLLFEED = 0xaa; + PLLFEED = 0x55; + + SCS |= 0x20; /* Enable main OSC */ + while( !(SCS & 0x40) ); /* Wait until main OSC is usable */ + + CLKSRCSEL = 0x1; /* select main OSC, 12MHz, as the PLL clock source */ + + PLLCFG = PLL_MValue | (PLL_NValue << 16); + PLLFEED = 0xaa; + PLLFEED = 0x55; + + PLLCON = 1; /* Enable PLL, disconnected */ + PLLFEED = 0xaa; + PLLFEED = 0x55; + + CCLKCFG = CCLKDivValue; /* Set clock divider */ +#if USE_USB + USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */ +#endif + + while ( ((PLLSTAT & (1 << 26)) == 0) ); /* Check lock bit status */ + + MValue = PLLSTAT & 0x00007FFF; + NValue = (PLLSTAT & 0x00FF0000) >> 16; + while ((MValue != PLL_MValue) && ( NValue != PLL_NValue) ); + + PLLCON = 3; /* enable and connect */ + PLLFEED = 0xaa; + PLLFEED = 0x55; + while ( ((PLLSTAT & (1 << 25)) == 0) ); /* Check connect bit status */ + return; +} + +/****************************************************************************** +** Function name: TargetResetInit +** +** Descriptions: Initialize the target board before running the main() +** function; User may change it as needed, but may not +** deleted it. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void TargetResetInit(void) +{
+ MEMMAP = 0x1; /* remap to internal flash */ + +#if USE_USB + PCONP |= 0x80000000; /* Turn On USB PCLK */ +#endif + /* Configure PLL, switch from IRC to Main OSC */ + ConfigurePLL(); + + /* Set system timers for each component */ +#if (Fpclk / (Fcclk / 4)) == 1 + PCLKSEL0 = 0x00000000; /* PCLK is 1/4 CCLK */ + PCLKSEL1 = 0x00000000; +#endif +#if (Fpclk / (Fcclk / 4)) == 2 + PCLKSEL0 = 0xAAAAAAAA; /* PCLK is 1/2 CCLK */ + PCLKSEL1 = 0xAAAAAAAA; +#endif +#if (Fpclk / (Fcclk / 4)) == 4 + PCLKSEL0 = 0x55555555; /* PCLK is the same as CCLK */ + PCLKSEL1 = 0x55555555; +#endif + + /* Set memory accelerater module*/ + MAMCR = 0; +#if Fcclk < 20000000 + MAMTIM = 1; +#else +#if Fcclk < 40000000 + MAMTIM = 2; +#else + MAMTIM = 3; +#endif +#endif + MAMCR = 2; + + GPIOResetInit(); + + return; +} + +/*@}*/ diff --git a/bsp/lpc2478/board.h b/bsp/lpc2478/board.h new file mode 100644 index 0000000000..8aa9ee1aa8 --- /dev/null +++ b/bsp/lpc2478/board.h @@ -0,0 +1,116 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-12-11 xuxinming first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +void rt_hw_board_init(void); +void rt_hw_led_set(rt_uint32_t led); +void rt_hw_led_flash(void); + +#ifdef RT_USING_FINSH +void rt_hw_finsh_init(void); +#endif + +#define USE_USB 0 + +#if USE_USB /* 1 is USB, 0 is non-USB related */ +#define PLL_MValue 11 +#define PLL_NValue 0 +#define CCLKDivValue 4 +#define USBCLKDivValue 5 + +#define Fosc 12000000 +#define Fcclk 57600000 +#define Fcco 288000000 +#else + +#define PLL_MValue 12 +#define PLL_NValue 1 +#define CCLKDivValue 5 + +#define Fosc 12000000 +#define Fcclk 72000000 +#define Fcco 360000000 + +#endif + +#if USE_USB +#define Fpclk (Fcclk / 2) +#else +#define Fpclk (Fcclk / 4) +#endif + +/* IRQ define */ +#define SYS32Mode 0x1F +#define IRQ32Mode 0x12 +#define FIQ32Mode 0x11 + +#define HIGHEST_PRIORITY 0x01 +#define LOWEST_PRIORITY 0x0F + +#define WDT_INT 0 +#define SWI_INT 1 +#define ARM_CORE0_INT 2 +#define ARM_CORE1_INT 3 +#define TIMER0_INT 4 +#define TIMER1_INT 5 +#define UART0_INT 6 +#define UART1_INT 7 +#define PWM0_1_INT 8 +#define I2C0_INT 9 +#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ +#define SSP0_INT 10 +#define SSP1_INT 11 +#define PLL_INT 12 +#define RTC_INT 13 +#define EINT0_INT 14 +#define EINT1_INT 15 +#define EINT2_INT 16 +#define EINT3_INT 17 +#define ADC0_INT 18 +#define I2C1_INT 19 +#define BOD_INT 20 +#define EMAC_INT 21 +#define USB_INT 22 +#define CAN_INT 23 +#define MCI_INT 24 +#define GPDMA_INT 25 +#define TIMER2_INT 26 +#define TIMER3_INT 27 +#define UART2_INT 28 +#define UART3_INT 29 +#define I2C2_INT 30 +#define I2S_INT 31 + +#define VIC_SIZE 32 + +#define VECT_ADDR_INDEX 0x100 +#define VECT_CNTL_INDEX 0x200 + +/****************************************************************************** +** Function name: TargetInit +** +** Descriptions: Initialize the target board; it is called in a +** necessary place, change it as needed +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +extern void TargetInit(void); +extern void ConfigurePLL( void ); +extern void TargetResetInit(void); + +#endif diff --git a/bsp/lpc2478/lowlevel.S b/bsp/lpc2478/lowlevel.S new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/bsp/lpc2478/lowlevel.S diff --git a/bsp/lpc2478/lpc2478_ram.lds b/bsp/lpc2478/lpc2478_ram.lds new file mode 100644 index 0000000000..ffdada7a2a --- /dev/null +++ b/bsp/lpc2478/lpc2478_ram.lds @@ -0,0 +1,89 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0xa0000000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + } =0 + __text_end = .; + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = 0xa0100000; + __data_start = .; + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(4); + __bss_start = __data_end; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + . = ALIGN(4); + __UndStack_start = __bss_end; + .UndStack : { *(.UndStack) } + __UndStack_end = ( __UndStack_start + 0x00000100 ); + + . = ALIGN(4); + __IRQStack_start = __UndStack_end; + .IRQStack : { *(.IRQStack) } + __IRQStack_end = ( __IRQStack_start + 0x00000100 ); + + . = ALIGN(4); + __FIQStack_start = __IRQStack_end; + .FIQStack : { *(.FIQStack) } + __FIQStack_end = ( __FIQStack_start + 0x00000100 ); + + . = ALIGN(4); + __SVCStack_start = __FIQStack_end; + .SVCStack : { *(.SVCStack) } + __SVCStack_end = ( __SVCStack_start + 0x00000100 ); + + . = ALIGN(4); + __ABTStack_start = __SVCStack_end; + .ABTStack : { *(.ABTStack) } + __ABTStack_end = ( __ABTStack_start + 0x00000100 ); + + . = ALIGN(4); + __USRStack_start = __ABTStack_end; + .USRStack : { *(.USRStack) } + __USRStack_end = ( __USRStack_start + 0x00003B00 ); + + . = ALIGN(4); + __Heap_start = __USRStack_end; + .Heap : { *(.Heap) } + __Heap_end = (__Heap_start + 0x00008000); + + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/lpc2478/lpc2478_rom.lds b/bsp/lpc2478/lpc2478_rom.lds new file mode 100644 index 0000000000..d710277d10 --- /dev/null +++ b/bsp/lpc2478/lpc2478_rom.lds @@ -0,0 +1,91 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + } =0 + + __text_end = .; + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*)} + __rodata_end = .; + + . = 0x40000000; /*Data in SRAM*/ + + __data_start = .; + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(4); + __bss_start = __data_end; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + . = ALIGN(4); + __UndStack_start = __bss_end; + .UndStack : { *(.UndStack) } + __UndStack_end = ( __UndStack_start + 0x00000100 ); + + . = ALIGN(4); + __IRQStack_start = __UndStack_end; + .IRQStack : { *(.IRQStack) } + __IRQStack_end = ( __IRQStack_start + 0x00000400 ); + + . = ALIGN(4); + __FIQStack_start = __IRQStack_end; + .FIQStack : { *(.FIQStack) } + __FIQStack_end = ( __FIQStack_start + 0x00000400 ); + + . = ALIGN(4); + __SVCStack_start = __FIQStack_end; + .SVCStack : { *(.SVCStack) } + __SVCStack_end = ( __SVCStack_start + 0x00000400 ); + + . = ALIGN(4); + __ABTStack_start = __SVCStack_end; + .ABTStack : { *(.ABTStack) } + __ABTStack_end = ( __ABTStack_start + 0x00000400 ); + + . = ALIGN(4); + __USRStack_start = __ABTStack_end; + .USRStack : { *(.USRStack) } + __USRStack_end = ( __USRStack_start + 0x00000400 ); + + . = ALIGN(4); + __Heap_start = __USRStack_end; + .Heap : { *(.Heap) } + __Heap_end = (__Heap_start + 0x00004000); + + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/lpc2478/project.Uv2 b/bsp/lpc2478/project.Uv2 new file mode 100644 index 0000000000..1af58b8373 --- /dev/null +++ b/bsp/lpc2478/project.Uv2 @@ -0,0 +1,138 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (RT-Thread/LPC2478), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Startup)
+Group (Kernel)
+Group (LPC2478)
+Group (finsh)
+
+File 1,1,<.\application.c><application.c>
+File 1,1,<.\board.c><board.c>
+File 1,1,<.\startup.c><startup.c>
+File 2,1,<..\..\src\clock.c><clock.c>
+File 2,1,<..\..\src\device.c><device.c>
+File 2,1,<..\..\src\ipc.c><ipc.c>
+File 2,1,<..\..\src\mempool.c><mempool.c>
+File 2,1,<..\..\src\object.c><object.c>
+File 2,1,<..\..\src\timer.c><timer.c>
+File 2,1,<..\..\src\idle.c><idle.c>
+File 2,1,<..\..\src\irq.c><irq.c>
+File 2,1,<..\..\src\mem.c><mem.c>
+File 2,1,<..\..\src\scheduler.c><scheduler.c>
+File 2,1,<..\..\src\slab.c><slab.c>
+File 2,1,<..\..\src\kservice.c><kservice.c>
+File 2,1,<..\..\src\thread.c><thread.c>
+File 3,1,<..\..\libcpu\arm\lpc24xx\cpu.c><cpu.c>
+File 3,1,<..\..\libcpu\arm\lpc24xx\interrupt.c><interrupt.c>
+File 3,1,<..\..\libcpu\arm\lpc24xx\serial.c><serial.c>
+File 3,1,<..\..\libcpu\arm\lpc24xx\stack.c><stack.c>
+File 3,1,<..\..\libcpu\arm\lpc24xx\trap.c><trap.c>
+File 3,2,<..\..\libcpu\arm\lpc24xx\context_rvds.s><context_rvds.s>
+File 3,2,<..\..\libcpu\arm\lpc24xx\start_rvds.s><start_rvds.s>
+File 4,1,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+File 4,1,<..\..\finsh\finsh_error.c><finsh_error.c>
+File 4,1,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+File 4,1,<..\..\finsh\finsh_init.c><finsh_init.c>
+File 4,1,<..\..\finsh\finsh_node.c><finsh_node.c>
+File 4,1,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+File 4,1,<..\..\finsh\finsh_token.c><finsh_token.c>
+File 4,1,<..\..\finsh\finsh_var.c><finsh_var.c>
+File 4,1,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+File 4,1,<..\..\finsh\shell.c><shell.c>
+File 4,1,<..\..\finsh\symbol.c><symbol.c>
+File 4,1,<..\..\finsh\cmd.c><cmd.c>
+File 4,1,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+
+
+Options 1,0,0 // Target 'RT-Thread/LPC2478'
+ Device (LPC2478)
+ Vendor (NXP (founded by Philips))
+ Cpu (IRAM(0x40000000-0x4000FFFF) IRAM2(0x7FE00000-0x7FE03FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
+ FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 38400 1))
+ StupF ("STARTUP\Philips\LPC2400.s" ("Philips LPC2400 Startup Code"))
+ FlashDR (UL2ARM(-U268761108 -O7 -S0 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07E000))
+ DevID (4307)
+ Rgf (LPC23xx.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (�Philips\)
+ OrgReg (�Philips\)
+ TgStat=16
+ OutDir (.\objs\)
+ OutName (rtthread-lpc2478)
+ GenApp=1
+ GenLib=0
+ GenHex=0
+ Debug=1
+ Browse=1
+ LstDir (.\objs\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP (ARM7TDMI)
+ RVDEV ()
+ ADSTFLGA { 0,12,16,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,64,0,0,1,0 }
+ OCMADSIROM { 1,0,0,0,0,0,0,8,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,1,0,0,0,0,224,127,0,64,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD (.;..\..\include;..\..\libcpu\arm\lpc24xx;..\..\finsh)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00000000)
+ ADSLDDA (0x40000000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC (--keep __fsym_* --keep __vsym_*)
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARM.DLL)(-cLPC24xx)(DARMP.DLL)(-pLPC2478)(SARM.DLL)()(TARMP.DLL)(-pLPC2478)
+ OPTDBG 48125,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
+ FLASH1 { 2,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (BIN\UL2ARM.DLL)
+ FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1))
+ FLASH4 ()
+EndOpt
+
diff --git a/bsp/lpc2478/rtconfig.h b/bsp/lpc2478/rtconfig.h new file mode 100644 index 0000000000..700d6a4ec1 --- /dev/null +++ b/bsp/lpc2478/rtconfig.h @@ -0,0 +1,126 @@ +/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX 32
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using Faset Event*/
+/* #define RT_USING_FASTEVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+
+/* Using SLAB Allocator*/
+/* #define RT_USING_SLAB */
+
+/* SECTION: Device System */
+/* Using Device System*/
+/* #define RT_USING_DEVICE */
+
+/* SECTION: Console options */
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: emulator options */
+/* Using QEMU or SkyEye*/
+/* #define RT_USING_EMULATOR */
+
+/* SECTION: a mini libc */
+/* Using mini libc library*/
+/* #define RT_USING_MINILIBC */
+
+/* SECTION: C++ support */
+/* Using C++ support*/
+/* #define RT_USING_CPLUSPLUS */
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* Using lighweight TCP/IP protocol stack*/
+/* #define RT_USING_LWIP */
+
+/* Trace LwIP protocol*/
+/* #define RT_LWIP_DEBUG */
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+
+/* Enable IGMP protocol*/
+#define RT_LWIP_IGMP
+
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+
+/* Enable SNMP protocol*/
+/* #define RT_LWIP_SNMP */
+
+/* Using DHCP*/
+/* #define RT_LWIP_DHCP */
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 0
+#define RT_LWIP_IPADDR3 30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 0
+#define RT_LWIP_GWADDR3 1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+
+#endif
diff --git a/bsp/lpc2478/startup.c b/bsp/lpc2478/startup.c new file mode 100644 index 0000000000..289d97b7b9 --- /dev/null +++ b/bsp/lpc2478/startup.c @@ -0,0 +1,111 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-12-11 xuxinming first version + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <LPC24xx.h> +#include <board.h> + +/** + * @addtogroup LPC2478 + */ +/*@{*/ + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit;
+#else +extern char __rodata_start[]; +extern char __rodata_end[]; +extern char __data_start[]; +extern char __bss_start[]; +extern char __data_end[]; +extern char __bss_end[]; +extern char __Heap_start[]; +extern char __Heap_end[]; +#endif + +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +#endif +extern int rt_application_init(void); + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init hardware Target */ + // TargetResetInit(); +
+ /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* init board */ + rt_hw_board_init(); + + rt_show_version(); +
+ /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + + /* init memory system */ +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x40010000); +#else + rt_system_heap_init((void*)__Heap_start, 0x40010000); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init the finsh input */ + rt_hw_finsh_init(); + + /* init finsh */ + finsh_system_init(); +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +}
+
+#ifdef __CC_ARM +int main(void)
+{
+ rtthread_startup();
+
+ return 0;
+}
+#endif
+ +/*@}*/ diff --git a/bsp/qemu/application.c b/bsp/qemu/application.c new file mode 100644 index 0000000000..cad1e64d97 --- /dev/null +++ b/bsp/qemu/application.c @@ -0,0 +1,28 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-15 QiuYi the first version + */ + +/** + * @addtogroup QEMU + */ +/*@{*/ + +/** + * This function will be invoked to initalize user application when system startup. + */ +int rt_application_init() +{ + return 0; /* empty */ +} + +/*@}*/ diff --git a/bsp/qemu/board.c b/bsp/qemu/board.c new file mode 100644 index 0000000000..c537b507be --- /dev/null +++ b/bsp/qemu/board.c @@ -0,0 +1,69 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.fayfayspace.org/license/LICENSE. + * + * Change Logs: + * Date Author Notes + * 2006-09-15 QiuYi the first version + * 2006-10-10 Bernard add hardware related of finsh + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <bsp.h> + +/** + * @addtogroup QEMU + */ +/*@{*/ + +static void rt_timer_handler(int vector) +{ + rt_tick_increase(); +} + +/** + * This function will init QEMU + * + */ +void rt_hw_board_init(void) +{ + /* initialize 8253 clock to interrupt 100 times/sec */ + outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); + outb(IO_TIMER1, TIMER_DIV(100) % 256); + outb(IO_TIMER1, TIMER_DIV(100) / 256); + + /* install interrupt handler */ + rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL); + rt_hw_interrupt_umask(INTTIMER0); +} + +#ifdef RT_USING_FINSH +extern void finsh_notify(void); +static void rt_serial_isr(int vector) +{ + finsh_notify(); +} + +/** + * This function will init hardware related in finsh shell + */ +void rt_hw_finsh_init() +{ + /* install UART isr */ + rt_hw_interrupt_install(INTUART0_RX, rt_serial_isr, RT_NULL); + rt_hw_interrupt_umask(INTUART0_RX); + + /* install keyboard isr */ + rt_hw_interrupt_install(INTKEYBOARD, rt_serial_isr, RT_NULL); + rt_hw_interrupt_umask(INTKEYBOARD); +} +#endif + +/*@}*/ diff --git a/bsp/qemu/board.h b/bsp/qemu/board.h new file mode 100644 index 0000000000..c7f4583157 --- /dev/null +++ b/bsp/qemu/board.h @@ -0,0 +1,24 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-09 Bernard first version + */
+ +#ifndef __BOARD_H__
+#define __BOARD_H__
+
+void rt_hw_board_init(void); + +#ifdef RT_USING_FINSH +void rt_hw_finsh_init(void); +#endif + +#endif
diff --git a/bsp/qemu/console.c b/bsp/qemu/console.c new file mode 100644 index 0000000000..bf42ebbfa8 --- /dev/null +++ b/bsp/qemu/console.c @@ -0,0 +1,200 @@ +/* + * File : console.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-15 QiuYi the first version + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <bsp.h> + +static unsigned addr_6845; +static rt_uint16_t *crt_buf; +static rt_int16 crt_pos; + +extern void rt_serial_init(void); +extern char rt_keyboard_getc(void); + +static void rt_console_putc(int c); + +/** + * @addtogroup QEMU + */ +/*@{*/ + +/** + * This function initializes cga + * + */ +void rt_cga_init(void) +{ + rt_uint16_t volatile *cp; + rt_uint16_t was; + rt_uint32_t pos; + + cp = (short *) (CGA_BUF); + was = *cp; + *cp = (rt_uint16_t) 0xA55A; + if (*cp != 0xA55A) + { + cp = (rt_int16 *) (MONO_BUF); + addr_6845 = MONO_BASE; + } + else + { + *cp = was; + addr_6845 = CGA_BASE; + } + + /* Extract cursor location */ + outb(addr_6845, 14); + pos = inb(addr_6845+1) << 8; + outb(addr_6845, 15); + pos |= inb(addr_6845+1); + + crt_buf = (rt_uint16_t *)cp; + crt_pos = pos; +} + +/** + * This function will write a character to cga + * + * @param c the char to write + */ +static void rt_cga_putc(int c) +{ + /* if no attribute given, then use black on white */ + if (!(c & ~0xff)) c |= 0x0700; + + switch (c & 0xff) + { + case '\b': + if (crt_pos > 0) + { + crt_pos--; + crt_buf[crt_pos] = (c&~0xff) | ' '; + } + break; + case '\n': + crt_pos += CRT_COLS; + /* cascade */ + case '\r': + crt_pos -= (crt_pos % CRT_COLS); + break; + case '\t': + rt_console_putc(' '); + rt_console_putc(' '); + rt_console_putc(' '); + rt_console_putc(' '); + rt_console_putc(' '); + break; + default: + crt_buf[crt_pos++] = c; /* write the character */ + break; + } + + if (crt_pos >= CRT_SIZE) + { + rt_int32 i; + rt_memcpy(crt_buf, crt_buf + CRT_COLS, (CRT_SIZE - CRT_COLS) << 1); + for (i = CRT_SIZE - CRT_COLS; i < CRT_SIZE; i++) + crt_buf[i] = 0x0700 | ' '; + crt_pos -= CRT_COLS; + } + + outb(addr_6845, 14); + outb(addr_6845+1, crt_pos >> 8); + outb(addr_6845, 15); + outb(addr_6845+1, crt_pos); +} + +/** + * This function will write a character to serial an cga + * + * @param c the char to write + */ +static void rt_console_putc(int c) +{ + rt_cga_putc(c); + rt_serial_putc(c); +} + +/** + * This function initializes console + * + */ +void rt_console_init(void) +{ + rt_cga_init(); + rt_serial_init(); +} + +/** + * This function is used to display a string on console, normally, it's + * invoked by rt_kprintf + * + * @param str the displayed string + */ +void rt_console_puts(const char* str) +{ + while (*str) + { + rt_console_putc (*str++); + } +} + +#define BY2CONS 512 + +static struct +{ + rt_uint8_t buf[BY2CONS]; + rt_uint32_t rpos; + rt_uint32_t wpos; +}cons; + +static void rt_console_intr(char (*proc)(void)) +{ + int c; + + while ((c = (*proc)()) != -1) + { + if (c == 0) + continue; + cons.buf[cons.wpos++] = c; + if (cons.wpos == BY2CONS) + cons.wpos = 0; + } +} + +/** + * return the next input character from the console,either from serial, + * or keyboard + * + */ +int rt_console_getc(void) +{ + int c; + + rt_console_intr(rt_serial_getc); + rt_console_intr(rt_keyboard_getc); + + if (cons.rpos != cons.wpos) + { + c = cons.buf[cons.rpos++]; + if (cons.rpos == BY2CONS) + cons.rpos = 0; + return c; + } + return 0; +} + +/*@}*/ diff --git a/bsp/qemu/keyboard.c b/bsp/qemu/keyboard.c new file mode 100644 index 0000000000..5bf3de3906 --- /dev/null +++ b/bsp/qemu/keyboard.c @@ -0,0 +1,138 @@ +/*
+ * File : keyboard.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-09-15 QiuYi the first version + */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include <bsp.h>
+
+#define NO 0
+
+#define SHIFT (1 << 0)
+#define CTL (1 << 1)
+#define ALT (1 << 2)
+
+#define CAPSLOCK (1<<3)
+#define NUMLOCK (1<<4)
+#define SCROLLOCK (1<<5)
+
+static int shiftcode[256] =
+{
+ [29] CTL,
+ [42] SHIFT,
+ [54] SHIFT,
+ [56] ALT,
+};
+
+static int togglecode[256] =
+{
+ [58] CAPSLOCK,
+ [69] NUMLOCK,
+ [70] SCROLLOCK,
+};
+
+static char normalmap[256] =
+{
+ NO, 033, '1', '2', '3', '4', '5', '6',
+ '7', '8', '9', '0', '-', '=', '\b', '\t',
+ 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i',
+ 'o', 'p', '[', ']', '\n', NO, 'a', 's',
+ 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';',
+ '\'', '`', NO, '\\', 'z', 'x', 'c', 'v',
+ 'b', 'n', 'm', ',', '.', '/', NO, '*',
+ NO, ' ', NO, NO, NO, NO, NO, NO,
+ NO, NO, NO, NO, NO, NO, NO, '7',
+ '8', '9', '-', '4', '5', '6', '+', '1',
+ '2', '3', '0', '.',
+};
+
+static char shiftmap[256] =
+{
+ NO, 033, '!', '@', '#', '$', '%', '^',
+ '&', '*', '(', ')', '_', '+', '\b', '\t',
+ 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I',
+ 'O', 'P', '{', '}', '\n', NO, 'A', 'S',
+ 'D', 'F', 'G', 'H', 'J', 'K', 'L', ';',
+ '"', '~', NO, '|', 'Z', 'X', 'C', 'V',
+ 'B', 'N', 'M', '<', '>', '?', NO, '*',
+ NO, ' ', NO, NO, NO, NO, NO, NO,
+ NO, NO, NO, NO, NO, NO, NO, '7',
+ '8', '9', '-', '4', '5', '6', '+', '1',
+ '2', '3', '0', '.',
+};
+
+#define C(x) (x-'@')
+
+static char ctlmap[256] =
+{
+ NO, NO, NO, NO, NO, NO, NO, NO,
+ NO, NO, NO, NO, NO, NO, NO, NO,
+ C('Q'), C('W'), C('E'), C('R'), C('T'), C('Y'), C('U'), C('I'),
+ C('O'), C('P'), NO, NO, '\r', NO, C('A'), C('S'),
+ C('D'), C('F'), C('G'), C('H'), C('J'), C('K'), C('L'), NO,
+ NO, NO, NO, C('\\'), C('Z'), C('X'), C('C'), C('V'),
+ C('B'), C('N'), C('M'), NO, NO, C('/'), NO, NO,
+};
+
+static char *charcode[4] =
+{
+ normalmap,
+ shiftmap,
+ ctlmap,
+ ctlmap,
+};
+
+/**
+ * @addtogroup QEMU
+ */
+/*@{*/
+
+/**
+ * This function get a char from the keyboard
+ */
+char rt_keyboard_getc(void)
+{
+ int c;
+ rt_uint8_t data;
+ static rt_uint32_t shift;
+
+ if ((inb(KBSTATP) & KBS_DIB) == 0)
+ return -1;
+
+ data = inb(KBDATAP);
+
+ if (data & 0x80)
+ {
+ /* key up */
+ shift &= ~shiftcode[data&~0x80];
+ return 0;
+ }
+
+ /* key down */
+ shift |= shiftcode[data];
+ shift ^= togglecode[data];
+ c = charcode[shift&(CTL|SHIFT)][data];
+
+ if (shift&CAPSLOCK)
+ {
+ if ('a' <= c && c <= 'z')
+ c += 'A' - 'a';
+ else if ('A' <= c && c <= 'Z')
+ c += 'a' - 'A';
+ }
+
+ return c;
+}
+
+/*@}*/
diff --git a/bsp/qemu/qemu_ram.lds b/bsp/qemu/qemu_ram.lds new file mode 100644 index 0000000000..8964405875 --- /dev/null +++ b/bsp/qemu/qemu_ram.lds @@ -0,0 +1,41 @@ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) +SECTIONS +{ + . = 0x00100000; + + . = ALIGN(4); + .text : + { + *(.init) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + /* stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _end = .; +} diff --git a/bsp/qemu/serial.c b/bsp/qemu/serial.c new file mode 100644 index 0000000000..9807c7b16e --- /dev/null +++ b/bsp/qemu/serial.c @@ -0,0 +1,74 @@ +/*
+ * File : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-09-15 QiuYi the first version
+ * 2006-10-10 Bernard use keyboard instead of serial + */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include <bsp.h>
+
+/**
+ * @addtogroup QEMU
+ */
+/*@{*/
+
+/**
+ * This function initializes serial
+ */
+void rt_serial_init(void)
+{
+ outb(COM1+3,0x80); /* set DLAB of line control reg */
+ outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */
+ outb(COM1+1,0x00); /* MS of divisor */
+ outb(COM1+3,0x03); /* reset DLAB */
+ outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */
+ outb(COM1+1,0x0d); /* enable all intrs but writes */
+ inb(COM1); /* read data port to reset things (?) */
+}
+
+/**
+ * This function read a character from serial without interrupt enable mode
+ *
+ * @return the read char
+ */
+char rt_serial_getc(void)
+{
+ return rt_keyboard_getc();
+
+#if 0
+ while(!(inb(COM1+COMSTATUS) & COMDATA));
+
+ return inb(COM1+COMREAD);
+#endif
+}
+
+/**
+ * This function will write a character to serial without interrupt enable mode
+ *
+ * @param c the char to write
+ */
+void rt_serial_putc(const char c)
+{
+ int val;
+
+ while(1)
+ {
+ if ((val = inb(COM1+COMSTATUS)) & THRE)
+ break;
+ }
+
+ outb(COM1+COMWRITE, c&0xff);
+}
+
+/*@}*/
diff --git a/bsp/qemu/startup.c b/bsp/qemu/startup.c new file mode 100644 index 0000000000..4841da83f1 --- /dev/null +++ b/bsp/qemu/startup.c @@ -0,0 +1,108 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.fayfayspace.org/license/LICENSE. + * + * Change Logs: + * Date Author Notes + * 2006-09-15 QiuYi the first version + * 2006-10-10 Bernard update to 0.2.2 version + */ + +#include <rtthread.h> +#include <rthw.h> + +#include "board.h" + +extern void rt_console_init(void); +extern void rt_hw_interrupt_init(void); +extern void rt_hw_board_init(void); +extern void rt_system_timer_init(void); +extern void rt_system_scheduler_init(void); +extern void rt_thread_idle_init(void); + +extern unsigned char __bss_start[]; +extern unsigned char __bss_end[]; + +/** + * @addtogroup QEMU + */ + /*@{*/ + +/* clear .bss */ +void rt_hw_clear_bss() +{ + unsigned char *dst; + dst = __bss_start; + while(dst < __bss_end) *dst++ = 0; +} + +extern void finsh_system_init(void); +extern int rt_application_init(void); + +/** + * This function will startup RT-Thread RTOS + */ +void rtthread_startup() +{ + /* clear .bss */ + rt_hw_clear_bss(); + + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* init the console */ + rt_console_init(); + + /* init board */ + rt_hw_board_init(); + + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + + /* init memory system */ +#ifdef RT_USING_HEAP + //rt_system_heap_init(); +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init application */ + rt_application_init(); + + /* init the finsh input */ + rt_hw_finsh_init(); + + /* init finsh */ + finsh_system_init(); + +#ifdef RT_USING_HOOK + /* set idle thread hook */ + rt_thread_idle_sethook(RT_NULL); +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; + +} + +/*@}*/ diff --git a/bsp/sam7s/application.c b/bsp/sam7s/application.c new file mode 100644 index 0000000000..46e5ef6232 --- /dev/null +++ b/bsp/sam7s/application.c @@ -0,0 +1,26 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-06-05 Bernard the first version + */ + +/** + * @addtogroup sam7s + */ +/*@{*/
+#include <rtthread.h>
+ +int rt_application_init() +{ + return 0; +} + +/*@}*/ diff --git a/bsp/sam7s/board.c b/bsp/sam7s/board.c new file mode 100644 index 0000000000..b7f92495ca --- /dev/null +++ b/bsp/sam7s/board.c @@ -0,0 +1,172 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard first implementation + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <AT91SAM7S.h> +#include "board.h" + +static void rt_hw_board_led_init(void); + +/** + * @addtogroup sam7s + */ +/*@{*/ + +/* Periodic Interval Value */ +#define PIV (((MCK/16)/1000)*(1000/RT_TICK_PER_SECOND)) + +/** + * This is the timer interrupt service routine. + * @param vector the irq number for timer + */ +void rt_hw_timer_handler(int vector) +{ + if (AT91C_PITC_PISR & 0x01) + { + /* increase a tick */ + rt_tick_increase(); + + /* ack interrupt */ + AT91C_AIC_EOICR = AT91C_PITC_PIVR; + } + else + { + /* end of interrupt */ + AT91C_AIC_EOICR = 0; + } +} + + /* PIO Flash PA PB PIN */ +#define LED (1 << 8)/* PA8 & TWD NPCS3 43 */ + +/** + * This function will init led on the board + */ +static void rt_hw_board_led_init() +{ + /* Enable Clock for PIO */ + AT91C_PMC_PCER = 1 << AT91C_ID_PIOA; + + /* configure PIO as output for led */ + AT91C_PIO_PER = LED; + AT91C_PIO_OER = LED; +} + +/** + * This function will take the led on board on. + * + * @param n the number nth led + */ +void rt_hw_board_led_on() +{ + AT91C_PIO_CODR = LED; +} + +/** + * This function will take the led on board off. + * + * @param n the number nth led + */ +void rt_hw_board_led_off() +{ + AT91C_PIO_SODR = LED; +} + +void rt_hw_led_flash() +{ + int i; + + rt_hw_board_led_off(); + for (i = 0; i < 2000000; i ++); + + rt_hw_board_led_on(); + for (i = 0; i < 2000000; i ++); +} + +/* + * RT-Thread Console Interface, used by rt_kprintf + */ +/** + * This function is used to display a string on console, normally, it's + * invoked by rt_kprintf + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + if (*str == '\n') + { + while (!(AT91C_US0_CSR & AT91C_US_TXRDY)); + AT91C_US0_THR = '\r'; + } + + /* Wait for Empty Tx Buffer */ + while (!(AT91C_US0_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + AT91C_US0_THR = *str; + + str ++; + } +} + +static void rt_hw_console_init() +{ + /* Enable Clock for USART0 */ + AT91C_PMC_PCER = 1 << AT91C_ID_US0; + /* Enable RxD0 and TxDO Pin */ + AT91C_PIO_PDR = (1 << 5) | (1 << 6); + + AT91C_US0_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ + + AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + + /* set baud rate divisor */ + AT91C_US0_BRGR = BRD; + + AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ +} + +/** + * This function will initial sam7s64 board. + */ +void rt_hw_board_init() +{ + extern void rt_serial_init(void); + + /* init hardware console */ + rt_hw_console_init(); + + /* init led */ + rt_hw_board_led_init(); + + /* init PITC */ + AT91C_PITC_PIMR = (1 << 25) | (1 << 24) | PIV; + /* install timer handler */ + rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL); + AT91C_AIC_SMR(AT91C_ID_SYS) = 0; + rt_hw_interrupt_umask(AT91C_ID_SYS); +} +/*@}*/ diff --git a/bsp/sam7s/board.h b/bsp/sam7s/board.h new file mode 100644 index 0000000000..2df27acc3a --- /dev/null +++ b/bsp/sam7s/board.h @@ -0,0 +1,69 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-08 Bernard add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include <AT91SAM7S.h> + +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ + +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ + +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ + +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ + +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ + +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ + +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ + +void rt_hw_board_led_on(void); +void rt_hw_board_led_off(void); +void rt_hw_board_init(void); +void rt_hw_led_flash(void); + +#endif diff --git a/bsp/sam7s/project.Opt b/bsp/sam7s/project.Opt new file mode 100644 index 0000000000..56495d7951 --- /dev/null +++ b/bsp/sam7s/project.Opt @@ -0,0 +1,76 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+ cExt (*.c)
+ aExt (*.s*; *.src; *.a*)
+ oExt (*.obj)
+ lExt (*.lib)
+ tExt (*.txt; *.h; *.inc)
+ pExt (*.plm)
+ CppX (*.cpp)
+ DaveTm { 0,0,0,0,0,0,0,0 }
+
+Target (RT-Thread/AT91SAM7S), 0x0004 // Tools: 'ARM-ADS'
+GRPOPT 1,(Startup),1,0,0
+GRPOPT 2,(Kernel),0,0,0
+GRPOPT 3,(AT91SAM7S),1,0,0
+GRPOPT 4,(finsh),1,0,0
+
+OPTFFF 1,1,1,352321536,0,0,0,0,<.\application.c><application.c>
+OPTFFF 1,2,1,402653184,0,0,0,0,<.\board.c><board.c>
+OPTFFF 1,3,1,0,0,0,0,0,<.\startup.c><startup.c>
+OPTFFF 1,4,5,0,0,0,0,0,<.\rtconfig.h><rtconfig.h>
+OPTFFF 2,5,1,0,0,0,0,0,<..\..\src\clock.c><clock.c>
+OPTFFF 2,6,1,0,0,0,0,0,<..\..\src\idle.c><idle.c>
+OPTFFF 2,7,1,0,0,0,0,0,<..\..\src\ipc.c><ipc.c>
+OPTFFF 2,8,1,0,0,0,0,0,<..\..\src\irq.c><irq.c>
+OPTFFF 2,9,1,0,0,0,0,0,<..\..\src\kservice.c><kservice.c>
+OPTFFF 2,10,1,0,0,0,0,0,<..\..\src\mem.c><mem.c>
+OPTFFF 2,11,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c>
+OPTFFF 2,12,1,0,0,0,0,0,<..\..\src\object.c><object.c>
+OPTFFF 2,13,1,0,0,0,0,0,<..\..\src\timer.c><timer.c>
+OPTFFF 2,14,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c>
+OPTFFF 2,15,1,0,0,0,0,0,<..\..\src\slab.c><slab.c>
+OPTFFF 2,16,1,0,0,0,0,0,<..\..\src\thread.c><thread.c>
+OPTFFF 2,17,1,0,0,0,0,0,<..\..\src\device.c><device.c>
+OPTFFF 3,18,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\cpu.c><cpu.c>
+OPTFFF 3,19,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\interrupt.c><interrupt.c>
+OPTFFF 3,20,1,100663296,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\serial.c><serial.c>
+OPTFFF 3,21,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\stack.c><stack.c>
+OPTFFF 3,22,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\trap.c><trap.c>
+OPTFFF 3,23,2,385875968,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\context_rvds.S><context_rvds.S>
+OPTFFF 3,24,2,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7S\start_rvds.S><start_rvds.S>
+OPTFFF 4,25,1,0,0,0,0,0,<..\..\finsh\cmd.c><cmd.c>
+OPTFFF 4,26,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+OPTFFF 4,27,1,0,0,0,0,0,<..\..\finsh\finsh_error.c><finsh_error.c>
+OPTFFF 4,28,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+OPTFFF 4,29,1,0,0,0,0,0,<..\..\finsh\finsh_init.c><finsh_init.c>
+OPTFFF 4,30,1,0,0,0,0,0,<..\..\finsh\finsh_node.c><finsh_node.c>
+OPTFFF 4,31,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+OPTFFF 4,32,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+OPTFFF 4,33,1,0,0,0,0,0,<..\..\finsh\finsh_token.c><finsh_token.c>
+OPTFFF 4,34,1,0,0,0,0,0,<..\..\finsh\finsh_var.c><finsh_var.c>
+OPTFFF 4,35,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+OPTFFF 4,36,1,0,0,0,0,0,<..\..\finsh\shell.c><shell.c>
+OPTFFF 4,37,1,0,0,0,0,0,<..\..\finsh\symbol.c><symbol.c>
+
+
+TARGOPT 1, (RT-Thread/AT91SAM7S)
+ ADSCLK=20000000
+ OPTTT 0,1,1,0
+ OPTHX 1,65535,0,0,0
+ OPTLX 79,66,8,<.\objs\>
+ OPTOX 16
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+ OPTXL 1,1,1,1,1,1,1,0,0
+ OPTFL 1,0,1
+ OPTAX 0
+ OPTDL (SARM.DLL)(-cAT91SAM7S)(DARMATS.DLL)(-p91SAM7S64)(SARM.DLL)()(TARMATS.DLL)(-p91SAM7S64)
+ OPTDBG 8189,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
+ OPTKEY 0,(DLGDARM)((117=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(130=150,119,741,704,0)(131=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(3010=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(3006=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0))
+ OPTKEY 0,(ARMDBGFLAGS)(-T5F)
+ OPTDF 0x90
+ OPTLE <>
+ OPTLC <>
+EndOpt
+
diff --git a/bsp/sam7s/project.Uv2 b/bsp/sam7s/project.Uv2 new file mode 100644 index 0000000000..27333279da --- /dev/null +++ b/bsp/sam7s/project.Uv2 @@ -0,0 +1,139 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (RT-Thread/AT91SAM7S), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Startup)
+Group (Kernel)
+Group (AT91SAM7S)
+Group (finsh)
+
+File 1,1,<.\application.c><application.c>
+File 1,1,<.\board.c><board.c>
+File 1,1,<.\startup.c><startup.c>
+File 1,5,<.\rtconfig.h><rtconfig.h>
+File 2,1,<..\..\src\clock.c><clock.c>
+File 2,1,<..\..\src\idle.c><idle.c>
+File 2,1,<..\..\src\ipc.c><ipc.c>
+File 2,1,<..\..\src\irq.c><irq.c>
+File 2,1,<..\..\src\kservice.c><kservice.c>
+File 2,1,<..\..\src\mem.c><mem.c>
+File 2,1,<..\..\src\mempool.c><mempool.c>
+File 2,1,<..\..\src\object.c><object.c>
+File 2,1,<..\..\src\timer.c><timer.c>
+File 2,1,<..\..\src\scheduler.c><scheduler.c>
+File 2,1,<..\..\src\slab.c><slab.c>
+File 2,1,<..\..\src\thread.c><thread.c>
+File 2,1,<..\..\src\device.c><device.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7S\cpu.c><cpu.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7S\interrupt.c><interrupt.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7S\serial.c><serial.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7S\stack.c><stack.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7S\trap.c><trap.c>
+File 3,2,<..\..\libcpu\arm\AT91SAM7S\context_rvds.S><context_rvds.S>
+File 3,2,<..\..\libcpu\arm\AT91SAM7S\start_rvds.S><start_rvds.S>
+File 4,1,<..\..\finsh\cmd.c><cmd.c>
+File 4,1,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+File 4,1,<..\..\finsh\finsh_error.c><finsh_error.c>
+File 4,1,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+File 4,1,<..\..\finsh\finsh_init.c><finsh_init.c>
+File 4,1,<..\..\finsh\finsh_node.c><finsh_node.c>
+File 4,1,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+File 4,1,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+File 4,1,<..\..\finsh\finsh_token.c><finsh_token.c>
+File 4,1,<..\..\finsh\finsh_var.c><finsh_var.c>
+File 4,1,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+File 4,1,<..\..\finsh\shell.c><shell.c>
+File 4,1,<..\..\finsh\symbol.c><symbol.c>
+
+
+Options 1,0,0 // Target 'RT-Thread/AT91SAM7S'
+ Device (AT91SAM7S64)
+ Vendor (Atmel)
+ Cpu (IRAM(0x200000-0x203FFF) IROM(0x100000-0x10FFFF) CLOCK(20000000) CPUTYPE(ARM7TDMI))
+ FlashUt ()
+ StupF ("STARTUP\Atmel\SAM7.s" ("Atmel AT91SAM7 Startup Code"))
+ FlashDR (UL2ARM(-U44045500 -O15 -S0 -C0 -D00(3F0F0F0F) -L00(4) -FO6 -FD200000 -FC800 -FN1 -FF0AT91SAM7_64 -FS0100000 -FL010000))
+ DevID (3815)
+ Rgf (AT91SAM7S64.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (�Atmel\SAM7S\)
+ OrgReg (�Atmel\SAM7S\)
+ TgStat=16
+ OutDir (.\objs\)
+ OutName (rtthread-sam7s)
+ GenApp=1
+ GenLib=0
+ GenHex=1
+ Debug=1
+ Browse=1
+ LstDir (.\objs\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 242,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP (ARM7TDMI)
+ RVDEV ()
+ ADSTFLGA { 0,12,0,18,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,32,0,0,64,0,0 }
+ OCMADSIROM { 1,0,0,16,0,0,0,1,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,16,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,64,0,0,0,0,0,0,0,0,0,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD (.;..\..\include;..\..\libcpu\arm\AT91SAM7S;..\..\finsh)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00100000)
+ ADSLDDA (0x00200000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC (--keep __fsym_* --keep __vsym_*)
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARM.DLL)(-cAT91SAM7S)(DARMATS.DLL)(-p91SAM7S64)(SARM.DLL)()(TARMATS.DLL)(-p91SAM7S64)
+ OPTDBG 8189,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
+ FLASH1 { 9,0,0,0,1,0,0,0,4,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (Segger\JLTAgdi.dll)
+ FLASH3 ("" ())
+ FLASH4 ()
+EndOpt
+
diff --git a/bsp/sam7s/rtconfig.h b/bsp/sam7s/rtconfig.h new file mode 100644 index 0000000000..da90650479 --- /dev/null +++ b/bsp/sam7s/rtconfig.h @@ -0,0 +1,183 @@ +/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 4
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX 32
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using Faset Event*/
+/* #define RT_USING_FASTEVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+
+/* Using SLAB Allocator*/
+/* #define RT_USING_SLAB */
+
+/* SECTION: Device System */
+/* Using Device System*/
+#define RT_USING_DEVICE
+
+/* buffer size for UART reception*/
+#define RT_UART_RX_BUFFER_SIZE 64
+
+/* buffer size for UART transmission*/
+#define RT_UART_TX_BUFFER_SIZE 64
+
+/* Using UART1*/
+#define RT_USING_UART1
+
+/* Using UART1*/
+/* #define RT_USING_UART2 */
+
+/* Using UART1*/
+/* #define RT_USING_UART3 */
+
+/* SECTION: Console options */
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+
+/* SECTION: a runtime libc library */
+/* a runtime libc library*/
+/* #define RT_USING_NEWLIB */
+
+/* SECTION: a mini libc */
+/* Using mini libc library*/
+#define RT_USING_MINILIBC
+
+/* SECTION: C++ support */
+/* Using C++ support*/
+/* #define RT_USING_CPLUSPLUS */
+
+/* SECTION: RTGUI support */
+/* using RTGUI support*/
+/* #define RT_USING_RTGUI */
+
+/* SECTION: Device filesystem support */
+/* using DFS support*/
+/* #define RT_USING_DFS */
+
+/* SECTION: EFSL filesystem support */
+/* using EFSL filesystem support*/
+/* #define RT_USING_EFSL */
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* Using lighweight TCP/IP protocol stack*/
+/* #define RT_USING_LWIP */
+
+/* Using webserver goahead support*/
+/* #define RT_USING_WEBSERVER */
+
+/* Using ftpserver support*/
+/* #define RT_USING_FTPSERVER */
+
+/* Trace LwIP protocol*/
+/* #define RT_LWIP_DEBUG */
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+
+/* Enable IGMP protocol*/
+#define RT_LWIP_IGMP
+
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM 5
+
+/* TCP sender buffer space*/
+#define RT_LWIP_TCP_SND_BUF 10240
+
+/* Enable SNMP protocol*/
+/* #define RT_LWIP_SNMP */
+
+/* Using DHCP*/
+/* #define RT_LWIP_DHCP */
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 0
+#define RT_LWIP_IPADDR3 30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 0
+#define RT_LWIP_GWADDR3 1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+
+/* the number of blocks for pbuf*/
+#define RT_LWIP_PBUF_NUM 16
+
+/* thread priority of tcpip thread*/
+#define RT_LWIP_TCPTHREAD_PRIORITY 128
+
+/* mail box size of tcpip thread to wait for*/
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+
+/* thread stack size of tcpip thread*/
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+
+/* thread priority of ethnetif thread*/
+#define RT_LWIP_ETHTHREAD_PRIORITY 144
+
+/* mail box size of ethnetif thread to wait for*/
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32
+
+/* thread stack size of ethnetif thread*/
+#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
+
+#endif
diff --git a/bsp/sam7s/sam7s_rom.lds b/bsp/sam7s/sam7s_rom.lds new file mode 100644 index 0000000000..c5d8cc1e4c --- /dev/null +++ b/bsp/sam7s/sam7s_rom.lds @@ -0,0 +1,48 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DATA (rw) : ORIGIN = 0x00200000, LENGTH = 0x00004000 +} +ENTRY(_start) +SECTIONS +{ + .text : + { + *(.init) + *(.text) + } > CODE = 0 + + . = ALIGN(4); + .rodata : + { + *(.rodata .rodata.*) + } > CODE + + _etext = . ; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + _data = . ; + *(.data) + SORT(CONSTRUCTORS) + } >DATA + . = ALIGN(4); + + _edata = . ; + PROVIDE (edata = .); + + . = ALIGN(4); + __bss_start = .; + .bss : + { + *(.bss) + } > DATA + __bss_end = .; + + _end = .; +} diff --git a/bsp/sam7s/startup.c b/bsp/sam7s/startup.c new file mode 100644 index 0000000000..9c7eb80037 --- /dev/null +++ b/bsp/sam7s/startup.c @@ -0,0 +1,120 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include <rthw.h> +#include <rtthread.h> + +#include <AT91SAM7S.h> +#include "board.h"
+ +#ifdef RT_USING_FINSH
+#include <finsh.h>
+extern void finsh_system_init(void);
+#endif
+ +/** + * @addtogroup sam7s + */ + +/*@{*/ +#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#endif
+
+#ifdef __GNUC__ +extern unsigned char __bss_start; +extern unsigned char __bss_end; +#endif
+ +extern void rt_hw_interrupt_init(void); +extern int rt_application_init(void); +#ifdef RT_USING_DEVICE
+extern rt_err_t rt_hw_serial_init(void);
+#endif
+ +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init hardware interrupt */ + rt_hw_interrupt_init();
+ + /* init board */ + rt_hw_board_init(); + + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+ rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
+#elif __ICCARM__
+ rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
+#else
+ rt_system_heap_init((void*)&__bss_end, (void*)0x204000);
+#endif
+#endif
+ + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_HOOK /* if the hook is used */ + /* set idle thread hook */ + rt_thread_idle_sethook(rt_hw_led_flash); +#endif
+ +#ifdef RT_USING_DEVICE
+ /* init hardware serial device */
+ rt_hw_serial_init();
+ /* init all device */
+ rt_device_init_all();
+#endif
+ + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +}
+ +int main (void)
+{
+ /* invoke rtthread_startup */
+ rtthread_startup();
+
+ return 0;
+}
+ +/*@}*/ diff --git a/bsp/sam7x/application.c b/bsp/sam7x/application.c new file mode 100644 index 0000000000..c6cb353dcc --- /dev/null +++ b/bsp/sam7x/application.c @@ -0,0 +1,85 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-06-05 Bernard the first version + */ + +/** + * @addtogroup sam7x + */ +/*@{*/
+#include <rtthread.h>
+
+#ifdef RT_USING_DFS
+/* dfs init */
+#include <dfs_init.h>
+/* dfs filesystem:FAT filesystem init */
+#include <dfs_fat.h>
+/* dfs filesystem:EFS filesystem init */
+#include <dfs_efs.h>
+/* dfs Filesystem APIs */
+#include <dfs_fs.h>
+#endif
+
+#ifdef RT_USING_LWIP
+#include <lwip/sys.h>
+#endif
+
+#ifdef RT_USING_RTGUI
+#include <rtgui/rtgui.h>
+#endif
+
+/* thread phase init */
+void rt_init_thread_entry(void *parameter)
+{
+/* Filesystem Initialization */
+#ifdef RT_USING_DFS
+ {
+ /* init the device filesystem */
+ dfs_init();
+ /* init the efsl filesystam*/
+ efsl_init();
+
+ /* mount sd card fat partition 1 as root directory */
+ if (dfs_mount("sd0", "/", "efs", 0, 0) == 0)
+ rt_kprintf("File System initialized!\n");
+ else
+ rt_kprintf("File System init failed!\n");
+ }
+#endif
+
+/* LwIP Initialization */
+#ifdef RT_USING_LWIP
+ {
+ extern void lwip_sys_init(void);
+
+ /* init lwip system */
+ lwip_sys_init();
+ rt_kprintf("TCP/IP initialized!\n");
+ }
+#endif
+}
+
+int rt_application_init() +{
+ rt_thread_t init_thread;
+
+ init_thread = rt_thread_create("init",
+ rt_init_thread_entry, RT_NULL,
+ 1024, 8, 5);
+ rt_thread_startup(init_thread);
+
+ rt_kprintf("enter list() to get function list!\n");
+
+ return 0; +} + +/*@}*/ diff --git a/bsp/sam7x/board.c b/bsp/sam7x/board.c new file mode 100644 index 0000000000..d3f97c4112 --- /dev/null +++ b/bsp/sam7x/board.c @@ -0,0 +1,173 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard first implementation + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <AT91SAM7X.h> +#include "board.h" + +static void rt_hw_board_led_init(void); + +/** + * @addtogroup sam7s + */ +/*@{*/ + +/* Periodic Interval Value */ +#define PIV (((MCK/16)/1000)*(1000/RT_TICK_PER_SECOND)) + +/** + * This is the timer interrupt service routine. + * @param vector the irq number for timer + */ +void rt_hw_timer_handler(int vector) +{ + if (AT91C_PITC_PISR & 0x01) + { + /* increase a tick */ + rt_tick_increase(); + + /* ack interrupt */ + AT91C_AIC_EOICR = AT91C_PITC_PIVR; + } + else + { + /* end of interrupt */ + AT91C_AIC_EOICR = 0; + } +} + /* PIO Flash PA PB PIN */ +#define LED1 (1 << 19) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ +#define LED2 (1 << 20) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ +#define LED3 (1 << 21) /* PA2 & PWM2 SCK0 44 */ +#define LED4 (1 << 22) /* PA3 & TWD NPCS3 43 */ +#define LED_MASK (LED1|LED2|LED3|LED4) + +int leds[] = {LED1, LED2, LED3, LED4}; + +/** + * This function will init led on the board + */ +static void rt_hw_board_led_init() +{ + /* enable the clock of the PIO A, PIO B */ + AT91C_PMC_PCER = 1 << AT91C_ID_PIOA | 1 << AT91C_ID_PIOB; + + /* configure PIO as output for led */ + AT91C_PIOB_PER = LED_MASK; + AT91C_PIOB_OER = LED_MASK; +} + +/** + * This function will take the led on board on. + * + * @param n the number nth led + */ +void rt_hw_board_led_on(int n) +{ + if (n >= 0 && n < 4) + { + AT91C_PIOB_CODR = leds[n]; + } +} + +/** + * This function will take the led on board off. + * + * @param n the number nth led + */ +void rt_hw_board_led_off(int n) +{ + if (n >= 0 && n < 4) + { + AT91C_PIOB_SODR = leds[n]; + } +} + +/* + * RT-Thread Console Interface, used by rt_kprintf + */ +/** + * This function is used to display a string on console, normally, it's + * invoked by rt_kprintf + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + if (*str == '\n') + { + while (!(AT91C_US0_CSR & AT91C_US_TXRDY)); + AT91C_US0_THR = '\r'; + } + + /* Wait for Empty Tx Buffer */ + while (!(AT91C_US0_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + AT91C_US0_THR = *str; + + str ++; + } +} + +static void rt_hw_console_init() +{ + /* Enable Clock for USART0 */ + AT91C_PMC_PCER = 1 << AT91C_ID_US0; + /* Enable RxD0 and TxDO Pin */ + AT91C_PIO_PDR = (1 << 5) | (1 << 6); + + AT91C_US0_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ + + AT91C_US0_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + + /* set baud rate divisor */ + AT91C_US0_BRGR = BRD; + + AT91C_US0_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ +} + +/** + * This function will initial sam7x board. + */ +void rt_hw_board_init() +{ + extern void rt_serial_init(void); + + /* init hardware console */ + rt_hw_console_init(); + + /* init led */ + rt_hw_board_led_init(); + + /* init PITC */ + AT91C_PITC_PIMR = (1 << 25) | (1 << 24) | PIV; + + /* install timer handler */ + rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL); + AT91C_AIC_SMR(AT91C_ID_SYS) = 0; + rt_hw_interrupt_umask(AT91C_ID_SYS); +} +/*@}*/ diff --git a/bsp/sam7x/board.h b/bsp/sam7x/board.h new file mode 100644 index 0000000000..acaad92449 --- /dev/null +++ b/bsp/sam7x/board.h @@ -0,0 +1,69 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-08 Bernard add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include <rthw.h> +#include <rtthread.h> + +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ + +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ + +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ + +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ + +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ + +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ + +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ + +void rt_hw_board_led_on(int n); +void rt_hw_board_led_off(int n); +void rt_hw_board_init(void); + +#endif diff --git a/bsp/sam7x/project.Opt b/bsp/sam7x/project.Opt new file mode 100644 index 0000000000..b064f924b2 --- /dev/null +++ b/bsp/sam7x/project.Opt @@ -0,0 +1,143 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+ cExt (*.c)
+ aExt (*.s*; *.src; *.a*)
+ oExt (*.obj)
+ lExt (*.lib)
+ tExt (*.txt; *.h; *.inc)
+ pExt (*.plm)
+ CppX (*.cpp)
+ DaveTm { 0,0,0,0,0,0,0,0 }
+
+Target (RT-Thread/AT91SAM7X), 0x0004 // Tools: 'ARM-ADS'
+GRPOPT 1,(Startup),1,0,0
+GRPOPT 2,(Kernel),0,0,0
+GRPOPT 3,(AT91SAM7X),1,0,0
+GRPOPT 4,(finsh),0,0,0
+GRPOPT 5,(LwIP),0,0,0
+GRPOPT 6,(Filesystem),0,0,0
+
+OPTFFF 1,1,1,0,0,0,0,0,<.\application.c><application.c>
+OPTFFF 1,2,1,0,0,0,0,0,<.\board.c><board.c>
+OPTFFF 1,3,1,0,0,145,151,0,<.\startup.c><startup.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,186,2,0,0,198,0,0,0 }
+OPTFFF 1,4,5,0,0,0,0,0,<.\rtconfig.h><rtconfig.h>
+OPTFFF 1,5,1,2,0,478,490,0,<.\sd.c><sd.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,66,0,0,0,87,0,0,0,218,2,0,0,74,1,0,0 }
+OPTFFF 2,6,1,0,0,0,0,0,<..\..\src\clock.c><clock.c>
+OPTFFF 2,7,1,0,0,0,0,0,<..\..\src\idle.c><idle.c>
+OPTFFF 2,8,1,0,0,0,0,0,<..\..\src\ipc.c><ipc.c>
+OPTFFF 2,9,1,0,0,0,0,0,<..\..\src\irq.c><irq.c>
+OPTFFF 2,10,1,402653184,0,0,0,0,<..\..\src\kservice.c><kservice.c>
+OPTFFF 2,11,1,0,0,0,0,0,<..\..\src\mem.c><mem.c>
+OPTFFF 2,12,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c>
+OPTFFF 2,13,1,0,0,0,0,0,<..\..\src\object.c><object.c>
+OPTFFF 2,14,1,0,0,0,0,0,<..\..\src\timer.c><timer.c>
+OPTFFF 2,15,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c>
+OPTFFF 2,16,1,0,0,0,0,0,<..\..\src\slab.c><slab.c>
+OPTFFF 2,17,1,0,0,0,0,0,<..\..\src\thread.c><thread.c>
+OPTFFF 2,18,1,0,0,0,0,0,<..\..\src\device.c><device.c>
+OPTFFF 3,19,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\interrupt.c><interrupt.c>
+OPTFFF 3,20,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\serial.c><serial.c>
+OPTFFF 3,21,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\stack.c><stack.c>
+OPTFFF 3,22,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\trap.c><trap.c>
+OPTFFF 3,23,1,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\cpu.c><cpu.c>
+OPTFFF 3,24,2,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\start_rvds.S><start_rvds.S>
+OPTFFF 3,25,2,0,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\context_rvds.S><context_rvds.S>
+OPTFFF 3,26,1,150994945,0,0,0,0,<..\..\libcpu\arm\AT91SAM7X\sam7x_emac.c><sam7x_emac.c>
+OPTFFF 4,27,1,0,0,0,0,0,<..\..\finsh\cmd.c><cmd.c>
+OPTFFF 4,28,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+OPTFFF 4,29,1,0,0,0,0,0,<..\..\finsh\finsh_error.c><finsh_error.c>
+OPTFFF 4,30,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+OPTFFF 4,31,1,0,0,0,0,0,<..\..\finsh\finsh_init.c><finsh_init.c>
+OPTFFF 4,32,1,0,0,0,0,0,<..\..\finsh\finsh_node.c><finsh_node.c>
+OPTFFF 4,33,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+OPTFFF 4,34,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+OPTFFF 4,35,1,0,0,0,0,0,<..\..\finsh\finsh_token.c><finsh_token.c>
+OPTFFF 4,36,1,0,0,0,0,0,<..\..\finsh\finsh_var.c><finsh_var.c>
+OPTFFF 4,37,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+OPTFFF 4,38,1,0,0,0,0,0,<..\..\finsh\shell.c><shell.c>
+OPTFFF 4,39,1,0,0,0,0,0,<..\..\finsh\symbol.c><symbol.c>
+OPTFFF 5,40,1,0,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c><dhcp.c>
+OPTFFF 5,41,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c><dns.c>
+OPTFFF 5,42,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c><init.c>
+OPTFFF 5,43,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c><netif.c>
+OPTFFF 5,44,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c><pbuf.c>
+OPTFFF 5,45,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c><raw.c>
+OPTFFF 5,46,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c><stats.c>
+OPTFFF 5,47,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c><sys.c>
+OPTFFF 5,48,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp.c><tcp.c>
+OPTFFF 5,49,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c>
+OPTFFF 5,50,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c>
+OPTFFF 5,51,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c><udp.c>
+OPTFFF 5,52,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c>
+OPTFFF 5,53,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c>
+OPTFFF 5,54,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c>
+OPTFFF 5,55,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c>
+OPTFFF 5,56,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
+OPTFFF 5,57,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c>
+OPTFFF 5,58,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
+OPTFFF 5,59,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
+OPTFFF 5,60,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\asn1_dec.c><asn1_dec.c>
+OPTFFF 5,61,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\asn1_enc.c><asn1_enc.c>
+OPTFFF 5,62,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\mib2.c><mib2.c>
+OPTFFF 5,63,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\mib_structs.c><mib_structs.c>
+OPTFFF 5,64,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_in.c><msg_in.c>
+OPTFFF 5,65,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_out.c><msg_out.c>
+OPTFFF 5,66,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c><api_lib.c>
+OPTFFF 5,67,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c><api_msg.c>
+OPTFFF 5,68,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c><err.c>
+OPTFFF 5,69,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c><netbuf.c>
+OPTFFF 5,70,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c><netdb.c>
+OPTFFF 5,71,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c><netifapi.c>
+OPTFFF 5,72,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c><tcpip.c>
+OPTFFF 5,73,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c><etharp.c>
+OPTFFF 5,74,1,0,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c>
+OPTFFF 5,75,1,0,0,0,0,0,<..\..\net\lwip\src\netif\loopif.c><loopif.c>
+OPTFFF 5,76,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c>
+OPTFFF 5,77,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c>
+OPTFFF 5,78,1,0,0,0,0,0,<..\..\net\lwip\src\api\sockets.c><sockets.c>
+OPTFFF 5,79,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c>
+OPTFFF 6,80,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c>
+OPTFFF 6,81,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c>
+OPTFFF 6,82,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c>
+OPTFFF 6,83,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c>
+OPTFFF 6,84,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c>
+OPTFFF 6,85,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c>
+OPTFFF 6,86,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c>
+OPTFFF 6,87,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c>
+OPTFFF 6,88,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c>
+OPTFFF 6,89,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c>
+OPTFFF 6,90,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c>
+OPTFFF 6,91,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c>
+OPTFFF 6,92,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c>
+OPTFFF 6,93,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c>
+OPTFFF 6,94,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c>
+OPTFFF 6,95,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c>
+OPTFFF 6,96,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c>
+
+ExtF <E:\Keil\ARM\INC\Atmel\SAM7X\AT91SAM7X256.h> 2725,2729,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,44,0,0,0,58,0,0,0,230,2,0,0,0,1,0,0 }
+ExtF <E:\Projects\opensvn\rt-thread\branches\0_3_0\kernel\libcpu\arm\AT91SAM7X\sam7x_emac.h> 48,48,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,66,0,0,0,87,0,0,0,252,2,0,0,29,1,0,0 }
+
+TARGOPT 1, (RT-Thread/AT91SAM7X)
+ ADSCLK=18432000
+ OPTTT 1,1,1,0
+ OPTHX 1,65535,0,0,0
+ OPTLX 79,66,8,<.\objs\>
+ OPTOX 16
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+ OPTXL 1,1,1,1,1,1,1,0,0
+ OPTFL 1,0,1
+ OPTAX 0
+ OPTDL (SARM.DLL)(-cAT91SAM7X)(DARMATS.DLL)(-p91SAM7X256)(SARM.DLL)()(TARMATS.DLL)(-p91SAM7X256)
+ OPTDBG 49150,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
+ OPTKEY 0,(DLGTARM)((117=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(3010=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(3006=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0))
+ OPTKEY 0,(ARMDBGFLAGS)()
+ OPTKEY 0,(JLTAgdi)(-O1070 -J1 -Y1000 -Z1 -FO7 -FD200000 -FC800 -FN0)
+ OPTKEY 0,(JLTDLG)()
+ OPTBB 0,0,551,1,1051508,0,0,0,0,1,<sd.c>()()
+ OPTMM 1,2,(sector)
+ OPTDF 0x80
+ OPTLE <>
+ OPTLC <>
+EndOpt
+
diff --git a/bsp/sam7x/project.Uv2 b/bsp/sam7x/project.Uv2 new file mode 100644 index 0000000000..3ccc487035 --- /dev/null +++ b/bsp/sam7x/project.Uv2 @@ -0,0 +1,200 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (RT-Thread/AT91SAM7X), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Startup)
+Group (Kernel)
+Group (AT91SAM7X)
+Group (finsh)
+Group (LwIP)
+Group (Filesystem)
+
+File 1,1,<.\application.c><application.c>
+File 1,1,<.\board.c><board.c>
+File 1,1,<.\startup.c><startup.c>
+File 1,5,<.\rtconfig.h><rtconfig.h>
+File 1,1,<.\sd.c><sd.c>
+File 2,1,<..\..\src\clock.c><clock.c>
+File 2,1,<..\..\src\idle.c><idle.c>
+File 2,1,<..\..\src\ipc.c><ipc.c>
+File 2,1,<..\..\src\irq.c><irq.c>
+File 2,1,<..\..\src\kservice.c><kservice.c>
+File 2,1,<..\..\src\mem.c><mem.c>
+File 2,1,<..\..\src\mempool.c><mempool.c>
+File 2,1,<..\..\src\object.c><object.c>
+File 2,1,<..\..\src\timer.c><timer.c>
+File 2,1,<..\..\src\scheduler.c><scheduler.c>
+File 2,1,<..\..\src\slab.c><slab.c>
+File 2,1,<..\..\src\thread.c><thread.c>
+File 2,1,<..\..\src\device.c><device.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7X\interrupt.c><interrupt.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7X\serial.c><serial.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7X\stack.c><stack.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7X\trap.c><trap.c>
+File 3,1,<..\..\libcpu\arm\AT91SAM7X\cpu.c><cpu.c>
+File 3,2,<..\..\libcpu\arm\AT91SAM7X\start_rvds.S><start_rvds.S>
+File 3,2,<..\..\libcpu\arm\AT91SAM7X\context_rvds.S><context_rvds.S>
+File 3,1,<..\..\libcpu\arm\AT91SAM7X\sam7x_emac.c><sam7x_emac.c>
+File 4,1,<..\..\finsh\cmd.c><cmd.c>
+File 4,1,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+File 4,1,<..\..\finsh\finsh_error.c><finsh_error.c>
+File 4,1,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+File 4,1,<..\..\finsh\finsh_init.c><finsh_init.c>
+File 4,1,<..\..\finsh\finsh_node.c><finsh_node.c>
+File 4,1,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+File 4,1,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+File 4,1,<..\..\finsh\finsh_token.c><finsh_token.c>
+File 4,1,<..\..\finsh\finsh_var.c><finsh_var.c>
+File 4,1,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+File 4,1,<..\..\finsh\shell.c><shell.c>
+File 4,1,<..\..\finsh\symbol.c><symbol.c>
+File 5,1,<..\..\net\lwip\src\core\dhcp.c><dhcp.c>
+File 5,1,<..\..\net\lwip\src\core\dns.c><dns.c>
+File 5,1,<..\..\net\lwip\src\core\init.c><init.c>
+File 5,1,<..\..\net\lwip\src\core\netif.c><netif.c>
+File 5,1,<..\..\net\lwip\src\core\pbuf.c><pbuf.c>
+File 5,1,<..\..\net\lwip\src\core\raw.c><raw.c>
+File 5,1,<..\..\net\lwip\src\core\stats.c><stats.c>
+File 5,1,<..\..\net\lwip\src\core\sys.c><sys.c>
+File 5,1,<..\..\net\lwip\src\core\tcp.c><tcp.c>
+File 5,1,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c>
+File 5,1,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c>
+File 5,1,<..\..\net\lwip\src\core\udp.c><udp.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
+File 5,1,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
+File 5,1,<..\..\net\lwip\src\core\snmp\asn1_dec.c><asn1_dec.c>
+File 5,1,<..\..\net\lwip\src\core\snmp\asn1_enc.c><asn1_enc.c>
+File 5,1,<..\..\net\lwip\src\core\snmp\mib2.c><mib2.c>
+File 5,1,<..\..\net\lwip\src\core\snmp\mib_structs.c><mib_structs.c>
+File 5,1,<..\..\net\lwip\src\core\snmp\msg_in.c><msg_in.c>
+File 5,1,<..\..\net\lwip\src\core\snmp\msg_out.c><msg_out.c>
+File 5,1,<..\..\net\lwip\src\api\api_lib.c><api_lib.c>
+File 5,1,<..\..\net\lwip\src\api\api_msg.c><api_msg.c>
+File 5,1,<..\..\net\lwip\src\api\err.c><err.c>
+File 5,1,<..\..\net\lwip\src\api\netbuf.c><netbuf.c>
+File 5,1,<..\..\net\lwip\src\api\netdb.c><netdb.c>
+File 5,1,<..\..\net\lwip\src\api\netifapi.c><netifapi.c>
+File 5,1,<..\..\net\lwip\src\api\tcpip.c><tcpip.c>
+File 5,1,<..\..\net\lwip\src\netif\etharp.c><etharp.c>
+File 5,1,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c>
+File 5,1,<..\..\net\lwip\src\netif\loopif.c><loopif.c>
+File 5,1,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c>
+File 5,1,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c>
+File 5,1,<..\..\net\lwip\src\api\sockets.c><sockets.c>
+File 5,1,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c>
+File 6,1,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c>
+File 6,1,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c>
+File 6,1,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c>
+File 6,1,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c>
+File 6,1,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c>
+File 6,1,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c>
+File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c>
+
+
+Options 1,0,0 // Target 'RT-Thread/AT91SAM7X'
+ Device (AT91SAM7X256)
+ Vendor (Atmel)
+ Cpu (IRAM(0x200000-0x20FFFF) IROM(0x100000-0x13FFFF) CLOCK(18432000) CPUTYPE(ARM7TDMI))
+ FlashUt ()
+ StupF ("STARTUP\Atmel\SAM7.s" ("Atmel AT91SAM7 Startup Code"))
+ FlashDR (UL2ARM(-U56240812 -O15 -S0 -C0 -FO7 -FD200000 -FC800 -FN1 -FF0AT91SAM7_256 -FS0100000 -FL040000))
+ DevID (4081)
+ Rgf (AT91SAM7X256.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (�Atmel\SAM7X\)
+ OrgReg (�Atmel\SAM7X\)
+ TgStat=16
+ OutDir (.\objs\)
+ OutName (rtthread-sam7x)
+ GenApp=1
+ GenLib=0
+ GenHex=0
+ Debug=1
+ Browse=1
+ LstDir (.\objs\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 242,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP (ARM7TDMI)
+ RVDEV ()
+ ADSTFLGA { 0,12,0,2,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,32,0,0,0,1,0 }
+ OCMADSIROM { 1,0,0,16,0,0,0,4,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,16,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD (.;..\..\include;..\..\libcpu\arm\AT91SAM7X;..\..\finsh;..\..\net\lwip\src\include;..\..\net\lwip\src;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00100000)
+ ADSLDDA (0x00200000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC (--keep __fsym_* --keep __vsym_*)
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARM.DLL)(-cAT91SAM7X)(DARMATS.DLL)(-p91SAM7X256)(SARM.DLL)()(TARMATS.DLL)(-p91SAM7X256)
+ OPTDBG 49150,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
+ FLASH1 { 1,0,0,0,1,0,0,0,4,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (Segger\JLTAgdi.dll)
+ FLASH3 ("" ())
+ FLASH4 ()
+EndOpt
+
diff --git a/bsp/sam7x/rtconfig.h b/bsp/sam7x/rtconfig.h new file mode 100644 index 0000000000..4d41525990 --- /dev/null +++ b/bsp/sam7x/rtconfig.h @@ -0,0 +1,150 @@ +/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX 32
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using Faset Event*/
+/* #define RT_USING_FASTEVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+#define RT_MEM_STATS
+
+/* Using SLAB Allocator*/
+/* #define RT_USING_SLAB */
+
+/* SECTION: Device System */
+/* Using Device System*/
+#define RT_USING_DEVICE
+#define RT_USING_UART1
+#define RT_UART_RX_BUFFER_SIZE 128
+
+/* SECTION: Console options */
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* use symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: a mini libc */
+/* Using mini libc library*/
+/* #define RT_USING_MINILIBC */
+
+/* SECTION: C++ support */
+/* Using C++ support*/
+/* #define RT_USING_CPLUSPLUS */
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* Using lighweight TCP/IP protocol stack*/
+#define RT_USING_LWIP
+
+/* Trace LwIP protocol*/
+/* #define RT_LWIP_DEBUG */
+
+/* LwIP tcp thread option */
+#define RT_LWIP_TCPTHREAD_PRIORITY 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
+
+/* LwIP eth thread option */
+#define RT_LWIP_ETHTHREAD_PRIORITY 15
+#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+
+/* Enable IGMP protocol*/
+#define RT_LWIP_IGMP
+
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM 5
+
+/* TCP sender buffer space*/
+#define RT_LWIP_TCP_SND_BUF 1500
+
+/* Enable SNMP protocol*/
+/* #define RT_LWIP_SNMP */
+
+/* Using DHCP*/
+/* #define RT_LWIP_DHCP */
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+
+/* SECTION: DFS options */
+#define RT_USING_DFS +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 1 +/* the max number of opened files */ +#define DFS_FD_MAX 2 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 +
+#endif
diff --git a/bsp/sam7x/sam7x_ram.lds b/bsp/sam7x/sam7x_ram.lds new file mode 100644 index 0000000000..43a56de7b5 --- /dev/null +++ b/bsp/sam7x/sam7x_ram.lds @@ -0,0 +1,37 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +MEMORY +{ + DATA (rw) : ORIGIN = 0x00200000, LENGTH = 0x00010000 +} +ENTRY(_start) +SECTIONS +{ + .text : + { + *(.init) + *(.text) + } > DATA = 0 + + . = ALIGN(4); + .rodata : + { + *(.rodata) + } > DATA + + . = ALIGN(4); + .data : + { + *(.data) + } > DATA + + . = ALIGN(4); + __bss_start = .; + .bss : + { + *(.bss) + } > DATA + __bss_end = .; + + _end = .; +} diff --git a/bsp/sam7x/sam7x_rom.lds b/bsp/sam7x/sam7x_rom.lds new file mode 100644 index 0000000000..ae8fa91399 --- /dev/null +++ b/bsp/sam7x/sam7x_rom.lds @@ -0,0 +1,38 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +MEMORY +{ + CODE (rx) : ORIGIN = 0x00100000, LENGTH = 0x00040000 + DATA (rw) : ORIGIN = 0x00200000, LENGTH = 0x00010000 +} +ENTRY(_start) +SECTIONS +{ + .text : + { + *(.init) + *(.text) + } > CODE = 0 + + . = ALIGN(4); + .rodata : + { + *(.rodata) + } > CODE + + . = ALIGN(4); + .data : + { + *(.data) + } > DATA + + . = ALIGN(4); + __bss_start = .; + .bss : + { + *(.bss) + } > DATA + __bss_end = .; + + _end = .; +} diff --git a/bsp/sam7x/sd.c b/bsp/sam7x/sd.c new file mode 100644 index 0000000000..da66b00c63 --- /dev/null +++ b/bsp/sam7x/sd.c @@ -0,0 +1,662 @@ +#include <rtthread.h>
+#include <dfs_fs.h>
+
+#include "sd.h"
+
+#include <AT91SAM7X.h>
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
+
+#define CARD_WP_PIN AT91C_PIO_PA16
+#define CARD_INS_PIN AT91C_PIO_PA15
+#define CARD_PWR_PIN AT91C_PIO_PA12
+
+typedef volatile unsigned int AT91S_REG;// Hardware register definition
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91S_REG SPI_CR; // Control Register
+ AT91S_REG SPI_MR; // Mode Register
+ AT91S_REG SPI_RDR; // Receive Data Register
+ AT91S_REG SPI_TDR; // Transmit Data Register
+ AT91S_REG SPI_SR; // Status Register
+ AT91S_REG SPI_IER; // Interrupt Enable Register
+ AT91S_REG SPI_IDR; // Interrupt Disable Register
+ AT91S_REG SPI_IMR; // Interrupt Mask Register
+ AT91S_REG Reserved0[4]; //
+ AT91S_REG SPI_CSR[4]; // Chip Select Register
+ AT91S_REG Reserved1[48]; //
+ AT91S_REG SPI_RPR; // Receive Pointer Register
+ AT91S_REG SPI_RCR; // Receive Counter Register
+ AT91S_REG SPI_TPR; // Transmit Pointer Register
+ AT91S_REG SPI_TCR; // Transmit Counter Register
+ AT91S_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91S_REG SPI_RNCR; // Receive Next Counter Register
+ AT91S_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91S_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91S_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91S_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+static AT91PS_SPI pSPI = ((AT91PS_SPI) 0xFFFE0000);
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+#define CARD_SELECT_PIN AT91C_PA13_SPI0_NPCS1
+#define SPI_CSR_NUM 0
+
+#define SPI_SCBR_MIN 2
+
+/* MMC/SD command (in SPI) */
+#define CMD0 (0x40+0) /* GO_IDLE_STATE */
+#define CMD1 (0x40+1) /* SEND_OP_COND */
+#define CMD9 (0x40+9) /* SEND_CSD */
+#define CMD10 (0x40+10) /* SEND_CID */
+#define CMD12 (0x40+12) /* STOP_TRANSMISSION */
+#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */
+#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */
+#define CMD24 (0x40+24) /* WRITE_BLOCK */
+#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */
+#define CMD58 (0x40+58) /* READ_OCR */
+
+/* Control signals (Platform dependent) */
+#define SELECT() (AT91C_PIOA_CODR = CARD_SELECT_PIN) /* MMC CS = L */
+#define DESELECT() (AT91C_PIOA_SODR = CARD_SELECT_PIN) /* MMC CS = H */
+
+#define SOCKWP CARD_WP_PIN /* Write protect switch (PB5) */
+#define SOCKINS CARD_INS_PIN /* Card detect switch (PB4) */
+
+#define POWER_ON() (AT91C_PIOA_CODR = CARD_PWR_PIN)
+#define POWER_OFF() (AT91C_PIOA_SODR = CARD_PWR_PIN)
+
+static struct rt_device sd;
+static struct dfs_partition part;
+
+static void AT91_spiSetSpeed(rt_uint8_t speed)
+{
+ rt_uint32_t reg;
+
+ if ( speed < SPI_SCBR_MIN ) speed = SPI_SCBR_MIN;
+ if ( speed > 1 ) speed &= 0xFE;
+
+ reg = pSPI->SPI_CSR[SPI_CSR_NUM];
+ reg = ( reg & ~(AT91C_SPI_SCBR) ) | ( (rt_uint32_t)speed << 8 );
+ pSPI->SPI_CSR[SPI_CSR_NUM] = reg;
+}
+
+static rt_uint8_t AT91_spi(rt_uint8_t outgoing)
+{
+ rt_uint8_t incoming;
+
+ while( !( pSPI->SPI_SR & AT91C_SPI_TDRE ) ); // transfer compl. wait
+ pSPI->SPI_TDR = (rt_uint16_t)( outgoing );
+
+ while( !( pSPI->SPI_SR & AT91C_SPI_RDRF ) ); // wait for char
+ incoming = (rt_uint8_t)( pSPI->SPI_RDR );
+
+ return incoming;
+}
+
+/*--------------------------------*/
+/* Transmit a rt_uint8_t to MMC via SPI */
+/* (Platform dependent) */
+rt_inline void xmit_spi(rt_uint8_t dat)
+{
+ AT91_spi(dat);
+}
+
+/*---------------------------------*/
+/* Receive a rt_uint8_t from MMC via SPI */
+/* (Platform dependent) */
+rt_inline rt_uint8_t rcvr_spi(void)
+{
+ return AT91_spi(0xff);
+}
+
+/* Alternative "macro" (not at AT91 so far) to receive data fast */
+static void rcvr_spi_m(rt_uint8_t *dst)
+{
+ *dst = rcvr_spi();
+}
+
+/*---------------------*/
+/* Wait for card ready */
+static rt_uint8_t wait_ready ()
+{
+ rt_uint8_t res;
+
+ rcvr_spi();
+ do
+ {
+ res = rcvr_spi();
+ } while ((res != 0xFF));
+
+ return res;
+}
+
+/*--------------------------------*/
+/* Receive a data packet from MMC */
+
+rt_bool_t rcvr_datablock (rt_uint8_t *buff, rt_uint8_t wc)
+{
+ rt_uint8_t token;
+
+ {
+ /* Wait for data packet in timeout of 100ms */
+ token = rcvr_spi();
+ }while ((token == 0xFF));
+
+ if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */
+
+ do
+ {
+ /* Receive the data block into buffer */
+ rcvr_spi_m(buff++);
+ rcvr_spi_m(buff++);
+ } while (--wc);
+
+ rcvr_spi(); /* Discard CRC */
+ rcvr_spi();
+
+ return RT_TRUE; /* Return with success */
+}
+
+/*---------------------------*/
+/* Send a data packet to MMC */
+static rt_bool_t xmit_datablock(const rt_uint8_t *buff, rt_uint8_t token)
+{
+ rt_uint8_t resp, wc = 0;
+
+ if (wait_ready() != 0xFF) return RT_FALSE;
+
+ xmit_spi(token); /* Xmit data token */
+ if (token != 0xFD)
+ { /* Is data token */
+ do
+ {
+ /* Xmit the 512 rt_uint8_t data block to MMC */
+ xmit_spi(*buff++);
+ xmit_spi(*buff++);
+ } while (--wc);
+
+ xmit_spi(0xFF); /* CRC (Dummy) */
+ xmit_spi(0xFF);
+ resp = rcvr_spi(); /* Reveive data response */
+
+ if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */
+ return RT_FALSE;
+ }
+
+ return RT_TRUE;
+}
+
+/*------------------------------*/
+/* Send a command packet to MMC */
+rt_uint8_t send_cmd (rt_uint8_t cmd, rt_uint32_t arg)
+{
+ rt_uint8_t n, res;
+
+ if (wait_ready() != 0xFF) return 0xFF;
+
+ /* Send command packet */
+ xmit_spi(cmd); /* Command */
+ xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */
+ xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */
+ xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */
+ xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */
+ xmit_spi(0x95); /* CRC (valid for only CMD0) */
+
+ /* Receive command response */
+ if (cmd == CMD12) rcvr_spi(); /* Skip a stuff rt_uint8_t when stop reading */
+ n = 10; /* Wait for a valid response in timeout of 10 attempts */
+ do
+ {
+ res = rcvr_spi();
+ }
+ while ((res & 0x80) && --n);
+
+ return res; /* Return with the response value */
+}
+
+static rt_err_t rt_sdcard_init(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_sdcard_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ rt_uint8_t count;
+
+ count = size / 512;
+
+ /* CS = L */
+ SELECT();
+
+ /* append partition offset */
+ pos += part.offset * 512;
+
+ if (count == 1)
+ { /* Single block read */
+ if ((send_cmd(CMD17, pos) == 0) /* READ_SINGLE_BLOCK */
+ && rcvr_datablock(buffer, (rt_uint8_t)(512/2)))
+ count = 0;
+ else
+ count = 1;
+ }
+ else
+ { /* Multiple block read */
+ if (send_cmd(CMD18, pos) == 0)
+ {
+ rt_uint8_t* ptr;
+
+ ptr = buffer;
+ do
+ {
+ if (!rcvr_datablock(ptr, (rt_uint8_t)(512/2))) break;
+ ptr += 512;
+ } while (--count);
+
+ send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
+ }
+ }
+
+ DESELECT(); /* CS = H */
+ rcvr_spi(); /* Idle (Release DO) */
+
+ if (count)
+ {
+ // rt_set_errno(-RT_ERROR);
+ return 0;
+ }
+
+ return size / 512;
+}
+
+static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ rt_uint8_t count;
+
+ count = size / 512;
+
+ /* CS = L */
+ SELECT();
+
+ /* append partition offset */
+ pos += part.offset * 512;
+
+ if (count == 1)
+ {
+ /* Single block write */
+ if ((send_cmd(CMD24, pos) == 0) /* WRITE_BLOCK */
+ && xmit_datablock(buffer, 0xFE))
+ count = 0;
+ else
+ count = 1;
+ }
+ else
+ {
+ /* Multiple block write */
+ if (send_cmd(CMD25, pos) == 0)
+ {
+ rt_uint8_t *ptr;
+
+ ptr = (rt_uint8_t *)buffer;
+ do
+ {
+ if (!xmit_datablock(ptr, 0xFC)) break;
+ ptr += 512;
+ } while (--count);
+
+ if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */
+ count = 1;
+ }
+ }
+
+ DESELECT(); /* CS = H */
+ rcvr_spi(); /* Idle (Release DO) */
+
+ if (count)
+ {
+ // rt_set_errno(-RT_ERROR);
+ return 0;
+ }
+
+ return size / 512;
+}
+
+static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+ return RT_EOK;
+}
+
+void rt_hw_sdcard_init()
+{
+ rt_uint32_t n;
+ rt_uint8_t* sector;
+
+ sd.type = RT_Device_Class_Block;
+ sd.init = rt_sdcard_init;
+ sd.open = rt_sdcard_open;
+ sd.close = rt_sdcard_close;
+ sd.read = rt_sdcard_read;
+ sd.write = rt_sdcard_write;
+ sd.control = rt_sdcard_control;
+ sd.private = RT_NULL;
+
+ AT91C_PIOA_PER = CARD_PWR_PIN; // enable GPIO of CS-pin
+ AT91C_PIOA_CODR = CARD_PWR_PIN; // set high
+ AT91C_PIOA_OER = CARD_PWR_PIN; // output enable
+
+ for (n = 0; n < 3000; n ++) ;
+
+ // disable PIO from controlling MOSI, MISO, SCK (=hand over to SPI)
+ // keep CS untouched - used as GPIO pin during init
+ AT91C_PIOA_PDR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; // | NCPS_PDR_BIT;
+ // set pin-functions in PIO Controller
+ AT91C_PIOA_ASR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; /// not here: | NCPS_ASR_BIT;
+
+ // set chip-select as output high (unselect card)
+ AT91C_PIOA_PER = CARD_SELECT_PIN; // enable GPIO of CS-pin
+ AT91C_PIOA_SODR = CARD_SELECT_PIN; // set high
+ AT91C_PIOA_OER = CARD_SELECT_PIN; // output enable
+
+ // enable peripheral clock for SPI ( PID Bit 5 )
+ AT91C_PMC_PCER = ( (rt_uint32_t) 1 << AT91C_ID_SPI0 ); // n.b. IDs are just bit-numbers
+
+ // SPI enable and reset
+ pSPI->SPI_CR = AT91C_SPI_SPIEN | AT91C_SPI_SWRST;
+
+ // SPI mode: master, FDIV=0, fault detection disabled
+ pSPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS;
+
+ // set chip-select-register
+ // 8 bits per transfer, CPOL=1, ClockPhase=0, DLYBCT = 0
+ pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_CPOL | AT91C_SPI_BITS_8;
+
+ // slow during init
+ AT91_spiSetSpeed(0xFE);
+
+ // enable
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;
+
+ n = 10; /* Dummy clock */
+ do
+ {
+ rcvr_spi();
+ } while (--n);
+
+ SELECT(); /* CS = L */
+ if (send_cmd(CMD0, 0) == 1)
+ {
+ /* Enter Idle state */
+ while (send_cmd(CMD1, 0));
+ }
+
+ DESELECT(); /* CS = H */
+ rcvr_spi(); /* Idle (Release DO) */
+
+ AT91_spiSetSpeed(SPI_SCBR_MIN);
+
+ /* get the first sector to read partition table */
+ sector = (rt_uint8_t*) rt_malloc (512);
+ if (sector == RT_NULL)
+ {
+ rt_kprintf("allocate partition sector buffer failed\n");
+ return;
+ }
+
+ n = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
+ if (n == 512)
+ {
+ rt_err_t status;
+
+ /* get the first partition */
+ status = dfs_filesystem_get_partition(&part, sector, 0);
+ if (status != RT_EOK)
+ {
+ /* there is no partition table */
+ part.offset = 0;
+ part.size = 0;
+ }
+ }
+ else
+ {
+ /* there is no partition table */
+ part.offset = 0;
+ part.size = 0;
+ }
+
+ /* release sector buffer */
+ rt_free(sector);
+
+ /* register sd device */
+ rt_device_register(&sd, "sd", RT_DEVICE_FLAG_RDWR);
+}
diff --git a/bsp/sam7x/sd.h b/bsp/sam7x/sd.h new file mode 100644 index 0000000000..0f38e06dfb --- /dev/null +++ b/bsp/sam7x/sd.h @@ -0,0 +1,6 @@ +#ifndef __SPI_SD_H__
+#define __SPI_SD_H__
+
+void rt_hw_sdcard_init(void);
+
+#endif
diff --git a/bsp/sam7x/startup.c b/bsp/sam7x/startup.c new file mode 100644 index 0000000000..c2ba230687 --- /dev/null +++ b/bsp/sam7x/startup.c @@ -0,0 +1,158 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include <rthw.h> +#include <rtthread.h> + +#include <AT91SAM7X.h> +#include "board.h"
+ +#ifdef RT_USING_DFS
+#include "sd.h"
+#endif
+
+#ifdef RT_USING_LWIP
+#include "sam7x_emac.h"
+#endif
+ +#ifdef RT_USING_FINSH +#include <finsh.h> +extern void finsh_system_init(void); +#endif + +/** + * @addtogroup sam7x256 + */ + +/*@{*/ +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#endif + +#ifdef __GNUCC__ +extern unsigned char __bss_start; +extern unsigned char __bss_end; +#endif + +extern void rt_hw_interrupt_init(void); +extern int rt_application_init(void); +#ifdef RT_USING_DEVICE +extern rt_err_t rt_hw_serial_init(void); +#endif +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +#endif + +void led_flash() +{ + int i; + static int j = 0; + + rt_hw_board_led_off(j); + for (i = 0; i < 2000000; i ++); + + j ++; + if (j >= 4) j = 0; + + rt_hw_board_led_on(j); + for (i = 0; i < 2000000; i ++); +} + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* init board */ + rt_hw_board_init(); + + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x00210000); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)0x00210000); +#else + rt_system_heap_init(&__bss_end, 0x00210000); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_HOOK /* if the hook is used */ + /* set idle thread hook */ + rt_thread_idle_sethook(led_flash); +#endif + +#ifdef RT_USING_DEVICE + /* init hardware serial device */ + rt_hw_serial_init(); + +#ifdef RT_USING_LWIP + eth_system_device_init(); + + /* register AT91 EMAC device */ + sam7xether_register("E0"); +#endif
+ +#ifdef RT_USING_DFS
+ rt_hw_sdcard_init();
+#endif
+ + /*init all registed devices*/ + rt_device_init_all(); +#endif + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main (void) +{ + /* invoke rtthread_startup */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/wh44b0/application.c b/bsp/wh44b0/application.c new file mode 100644 index 0000000000..8e653127f5 --- /dev/null +++ b/bsp/wh44b0/application.c @@ -0,0 +1,26 @@ +/*
+ * File : app.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-10-08 Bernard the first version
+ */
+
+/**
+ * @addtogroup wh44b0
+ */
+/** @{ */
+
+/* application start function */
+int rt_application_init()
+{
+ return 0; /* empty */
+}
+
+/** @} */
diff --git a/bsp/wh44b0/board.c b/bsp/wh44b0/board.c new file mode 100644 index 0000000000..8728785c0a --- /dev/null +++ b/bsp/wh44b0/board.c @@ -0,0 +1,204 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-23 Bernard first version + * 2006-09-24 Bernard add rt_hw_finsh_init implementation + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <s3c44b0.h> +#include "board.h" + +/* #define BOARD_DEBUG */ +extern void rt_serial_putc(const char ch);
+ +#define DATA_COUNT 0xfff + +/** + * @addtogroup wh44b0 + */ +/*@{*/ + +void rt_timer_handler(int vector) +{ +#ifdef BOARD_DEBUG + rt_kprintf("timer handler, increase a tick\n"); +#endif + + rt_tick_increase(); +} + +void rt_hw_port_init(void) +{ + /* PORT A GROUP */ + /* BIT 9 8 7 6 5 4 3 2 1 0 */ + /* A24 A23 A22 A21 A20 A19 A18 A17 A16 A0 */ + /* 1 1 1 1 1 1 1 1 1 1 */ + PCONA = 0x1ff; + PDATA = 0x2db; + + /* PORT B GROUP */ + /* BIT 10 9 8 7 6 5 4 3 2 1 0 */ + /* /CS5 /CS4 /CS3 /CS2 /CS1 nWBE3 nWBE2 /SRAS /SCAS SCLS SCKE */ + /* NC NC RTL8019 USBD12 NV_Flash NC NC Sdram Sdram Sdram Sdram*/ + /* 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1 */ + PDATB = 0x4f; + PCONB = 0x7cf; + + /* PORT C GROUP */ + /* BUSWIDTH=16 */ + /* PC15 14 13 12 11 10 9 8 */ + /* o o RXD1 TXD1 o o o o */ + /* NC NC Uart1 Uart1 NC NC NC NC */ + /* 01 01 11 11 01 01 01 00 */ + + /* PC7 6 5 4 3 2 1 0 */ + /* o o o o o o o o */ + /* NC NC NC NC NFALE NFCLE NFCE NFRB*/ + /* 01 01 01 01 01 01 01 00 */ + PDATC = 0x3001; /* All IO is low */ + PCONC = 0x5f555555; + PUPC = 0x3000; /* PULL UP RESISTOR should be enabled to I/O */ + + /* PORT D GROUP */ + /* PORT D GROUP(I/O OR LCD) */ + /* BIT7 6 5 4 3 2 1 0 */ + /* VF VM VLINE VCLK VD3 VD2 VD1 VD0 */ + /* 01 01 01 01 01 01 01 01 */ + PDATD= 0x0; + PCOND= 0xaaaa; + PUPD = 0x00; /* These pins must be set only after CPU's internal LCD controller is enable */ + + /* PORT E GROUP */ + /* Bit 8 7 6 5 4 3 2 1 0 */ + /* ENDLAN LED3 LED2 LED1 LED0 BEEP RXD0 TXD0 CLKOUT */ + /* 00 01 01 01 01 01 10 10 11 */ + PCONE = 0x556b; /*0->input, 1 2->TXD0 RXD0, 3 4->input, 5->led, 6->buzzer, 7->led, 8->CODECLK */ + PDATE = 0x57; + PUPE = 0x006; /* disable all pull-up */ + + /* PORT F GROUP */ + /* Bit8 7 6 5 4 3 2 1 0 */ + /* IISCLK IISDI IISDO IISLRCK Input Input Input IICSDA IICSCL */ + /* 100 010 010 001 00 01 01 10 10 */ + PDATF = 0x2f; + PCONF = 0x24900a; + PUPF = 0x1d3; + + /* PORT G GROUP */ + /* BIT7 6 5 4 3 2 1 0 */ + /* INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 */ + /* S3 S4 S5 S6 NIC EXT IDE USB */ + /* 11 11 11 11 11 11 11 11 */ + PDATG = 0xfc; + PCONG = 0x000f; /* eint1 is eth interrupt in WH44B0 */ + PUPG = 0x00; /* should be enabled */ + + SPUCR=0x7; /* D15-D0 pull-up disable */ + + /* all external interrupts are triggered by low level */ + EXTINT=0x0; +} + +/** + * This function will init lumit4510 board + */ +void rt_hw_board_init() +{ + /* init port setting */ + rt_hw_port_init(); + + /* set timer0 register */ + /* stop timer */ + TCON &= ~(0x00000001); + + /* dead zone = 0, pre = 150 */ + TCFG0 = 0x00000095; + /* all are interrupt mode */ + TCFG1 = 0x00000003; + + TCNTB0 = DATA_COUNT; + TCMPB0 = 0; + + /* manual update */ + TCON |= 0x00000002; + + /* auto reload on,output inverter off */ + TCON &= ~(0x0000000f); + TCON |= (0x00000008); + + /* install timer handler */ + rt_hw_interrupt_install(INT_TIMER0, rt_timer_handler, RT_NULL); + rt_hw_interrupt_umask(INT_TIMER0); + + /* start timer */ + TCON |=(0x00000001); +} + +void rt_hw_led_set(rt_uint32_t led) +{ + if((led & 0x01)==0x01) /* D1 */ + PDATC = PDATC | (1<<1) ; + else + PDATC = PDATC & (~(1<<1)) ; + + if((led & 0x02)==0x02) /* D2 */ + PDATC = PDATC | (1<<2) ; + else + PDATC = PDATC & (~(1<<2)) ; + + if((led & 0x04)==0x04) /* D3 */ + PDATC = PDATC | (1<<3) ; + else + PDATC = PDATC & (~(1<<3)) ; +} + +/* led loop */ +void rt_hw_led_flash(void) +{ + register int i; + + rt_hw_led_set(0x01); + for ( i = 0; i < 2000000; i++); + + rt_hw_led_set(0x02); + for ( i = 0; i < 2000000; i++); + + rt_hw_led_set(0x04); + for ( i = 0; i < 2000000; i++); +} + +#ifdef RT_USING_FINSH +extern void finsh_notify(void); +void rt_serial_isr(int vector) +{ + finsh_notify(); +} + +void rt_hw_finsh_init() +{ + /* install UART isr */ + rt_hw_interrupt_install(INT_URXD0, rt_serial_isr, RT_NULL); + rt_hw_interrupt_umask(INT_URXD0); +} +#endif +
+void rt_hw_console_output(const char* string)
+{
+ while (*string)
+ {
+ rt_serial_putc(*string++);
+ }
+}
+ +/*@}*/ diff --git a/bsp/wh44b0/board.h b/bsp/wh44b0/board.h new file mode 100644 index 0000000000..180a088498 --- /dev/null +++ b/bsp/wh44b0/board.h @@ -0,0 +1,27 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-23 Bernard first version + * 2006-09-24 Bernard add rt_hw_finsh_init declaration + */
+ +#ifndef __BOARD_H__
+#define __BOARD_H__
+
+void rt_hw_board_init(void); +void rt_hw_led_set(rt_uint32_t led); +void rt_hw_led_flash(void);
+ +#ifdef RT_USING_FINSH +void rt_hw_finsh_init(void); +#endif + +#endif
diff --git a/bsp/wh44b0/lowlevel.S b/bsp/wh44b0/lowlevel.S new file mode 100644 index 0000000000..8c5e3a2135 --- /dev/null +++ b/bsp/wh44b0/lowlevel.S @@ -0,0 +1,131 @@ +.equ B0_Tacs, 0x0 /* 0clk */ +.equ B0_Tcos, 0x0 /* 0clk */ +.equ B0_Tacc, 0x4 /* 6clk */ +.equ B0_Tcoh, 0x0 /* 0clk */ +.equ B0_Tah, 0x0 /* 0clk */ +.equ B0_Tacp, 0x0 /* 0clk */ +.equ B0_PMC, 0x0 /* normal(1data) */ + +/* Bank 1 parameter */ +.equ B1_Tacs, 0x3 /* 4clk */ +.equ B1_Tcos, 0x3 /* 4clk */ +.equ B1_Tacc, 0x7 /* 14clkv */ +.equ B1_Tcoh, 0x3 /* 4clk */ +.equ B1_Tah, 0x3 /* 4clk */ +.equ B1_Tacp, 0x3 /* 6clk */ +.equ B1_PMC, 0x0 /* normal(1data) */ + +/* Bank 2 parameter - LAN91C96 */ +.equ B2_Tacs, 0x3 /* 4clk */ +.equ B2_Tcos, 0x3 /* 4clk */ +.equ B2_Tacc, 0x7 /* 14clk */ +.equ B2_Tcoh, 0x3 /* 4clk */ +.equ B2_Tah, 0x3 /* 4clk */ +.equ B2_Tacp, 0x3 /* 6clk */ +.equ B2_PMC, 0x0 /* normal(1data) */ + +/* Bank 3 parameter */ +.equ B3_Tacs, 0x3 /* 4clk */ +.equ B3_Tcos, 0x3 /* 4clk */ +.equ B3_Tacc, 0x7 /* 14clk */ +.equ B3_Tcoh, 0x3 /* 4clk */ +.equ B3_Tah, 0x3 /* 4clk */ +.equ B3_Tacp, 0x3 /* 6clk */ +.equ B3_PMC, 0x0 /* normal(1data) */ + +/* Bank 4 parameter */ +.equ B4_Tacs, 0x3 /* 4clk */ +.equ B4_Tcos, 0x3 /* 4clk */ +.equ B4_Tacc, 0x7 /* 14clk */ +.equ B4_Tcoh, 0x3 /* 4clk */ +.equ B4_Tah, 0x3 /* 4clk */ +.equ B4_Tacp, 0x3 /* 6clk */ +.equ B4_PMC, 0x0 /* normal(1data) */ + +/* Bank 5 parameter */ +.equ B5_Tacs, 0x3 /* 4clk */ +.equ B5_Tcos, 0x3 /* 4clk */ +.equ B5_Tacc, 0x7 /* 14clk */ +.equ B5_Tcoh, 0x3 /* 4clk */ +.equ B5_Tah, 0x3 /* 4clk */ +.equ B5_Tacp, 0x3 /* 6clk */ +.equ B5_PMC, 0x0 /* normal(1data) */ + +/* Bank 6(if SROM) parameter */ +.equ B6_Tacs, 0x3 /* 4clk */ +.equ B6_Tcos, 0x3 /* 4clk */ +.equ B6_Tacc, 0x7 /* 14clk */ +.equ B6_Tcoh, 0x3 /* 4clk */ +.equ B6_Tah, 0x3 /* 4clk */ +.equ B6_Tacp, 0x3 /* 6clk */ +.equ B6_PMC, 0x0 /* normal(1data) */ + +/* Bank 7(if SROM) parameter */ +.equ B7_Tacs, 0x3 /* 4clk */ +.equ B7_Tcos, 0x3 /* 4clk */ +.equ B7_Tacc, 0x7 /* 14clk */ +.equ B7_Tcoh, 0x3 /* 4clk */ +.equ B7_Tah, 0x3 /* 4clk */ +.equ B7_Tacp, 0x3 /* 6clk */ +.equ B7_PMC, 0x0 /* normal(1data) */ + +/* Bank 6 parameter */ +.equ B6_MT, 0x3 /* SDRAM */ +.equ B6_Trcd, 0x0 /* 2clk */ +.equ B6_SCAN, 0x0 /* 8bit */ + +.equ B7_MT, 0x3 /* SDRAM */ +.equ B7_Trcd, 0x0 /* 2clk */ +.equ B7_SCAN, 0x0 /* 8bit */ + +/* REFRESH parameter */ +.equ REFEN, 0x1 /* Refresh enable */ +.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */ +.equ Trp, 0x0 /* 2clk */ +.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/ +.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */ +.equ REFCNT, 879 + +MEMORY_CONFIG: + .long 0x11111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/ + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/ + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/ + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/ + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/ + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/ + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/ + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/ + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/ + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/ + .word 0x16 /*SCLK power down mode, BANKSIZE 8M/8M*/ + .word 0x20 /*MRSR6 CL=2clk*/ + .word 0x20 /*MRSR7*/ + + .equ PLLCON, 0x01d80000 + .equ CLKCON, 0x01d80004 + .equ LOCKTIME, 0x01d8000c + +.globl lowlevel_init +lowlevel_init: + /* set clock control register */
+ ldr r1, =LOCKTIME
+ ldrb r0, =0x7d0
+ strb r0, [r1]
+
+ ldr r1, =PLLCON
+ ldr r0, =0x58061
+ str r0, [r1]
+
+ ldr r1, =CLKCON
+ ldr r0, =0x7ff8
+ str r0, [r1]
+ + /* + * memory configuration + */ + adr r0, MEMORY_CONFIG + + ldmia r0, {r1-r13} + ldr r0, =0x01c80000 + stmia r0, {r1-r13} + mov pc, lr diff --git a/bsp/wh44b0/project.Uv2 b/bsp/wh44b0/project.Uv2 new file mode 100644 index 0000000000..82d5daa6c3 --- /dev/null +++ b/bsp/wh44b0/project.Uv2 @@ -0,0 +1,124 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (RT-Thread/44B0), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Startup)
+Group (Kernel)
+Group (44B0)
+
+File 1,1,<.\application.c><application.c>
+File 1,1,<.\board.c><board.c>
+File 1,1,<.\startup.c><startup.c>
+File 2,1,<..\..\src\clock.c><clock.c>
+File 2,1,<..\..\src\device.c><device.c>
+File 2,1,<..\..\src\idle.c><idle.c>
+File 2,1,<..\..\src\ipc.c><ipc.c>
+File 2,1,<..\..\src\irq.c><irq.c>
+File 2,1,<..\..\src\kservice.c><kservice.c>
+File 2,1,<..\..\src\mem.c><mem.c>
+File 2,1,<..\..\src\mempool.c><mempool.c>
+File 2,1,<..\..\src\object.c><object.c>
+File 2,1,<..\..\src\scheduler.c><scheduler.c>
+File 2,1,<..\..\src\slab.c><slab.c>
+File 2,1,<..\..\src\thread.c><thread.c>
+File 2,1,<..\..\src\timer.c><timer.c>
+File 3,1,<..\..\libcpu\arm\s3c44b0\cpu.c><cpu.c>
+File 3,1,<..\..\libcpu\arm\s3c44b0\interrupt.c><interrupt.c>
+File 3,1,<..\..\libcpu\arm\s3c44b0\serial.c><serial.c>
+File 3,1,<..\..\libcpu\arm\s3c44b0\stack.c><stack.c>
+File 3,1,<..\..\libcpu\arm\s3c44b0\trap.c><trap.c>
+File 3,2,<..\..\libcpu\arm\s3c44b0\start_rvds.s><start_rvds.s>
+File 3,2,<..\..\libcpu\arm\s3c44b0\context_rvds.s><context_rvds.s>
+
+
+Options 1,0,0 // Target 'RT-Thread/44B0'
+ Device (S3C44B0X)
+ Vendor (Samsung)
+ Cpu (IRAM(0x10000000-0x10001FFF) CLOCK(66000000) CPUTYPE(ARM7TDMI))
+ FlashUt ()
+ StupF ("STARTUP\Samsung\S3C44B0X.s" ("Samsung S3C44B0x Startup Code"))
+ FlashDR ()
+ DevID (3835)
+ Rgf (S3C44B0X.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (�Samsung\)
+ OrgReg (�Samsung\)
+ TgStat=16
+ OutDir (.\obj\)
+ OutName (rtthread-44b0)
+ GenApp=1
+ GenLib=0
+ GenHex=0
+ Debug=1
+ Browse=1
+ LstDir (.\obj\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP (ARM7TDMI)
+ RVDEV ()
+ ADSTFLGA { 0,8,64,0,96,0,64,72,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,16,0,32,0,0 }
+ OCMADSIROM { 0,0,0,0,0,0,0,0,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,12,0,0,16,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,16,12,0,0,240,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,16,0,32,0,0,0,0,0,0,0,0,0,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD (..\..\include;..\..\libcpu\arm\s3c44b0;..\wh44b0)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00000000)
+ ADSLDDA (0x10000000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC ()
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARM.DLL)()(DARMS.DLL)(-pS3C44B0X)(SARM.DLL)()(TARMS.DLL)(-pS3C44B0X)
+ OPTDBG 48125,-1,()()()()()()()()()() ()()()()
+ FLASH1 { 1,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }
+ FLASH2 ()
+ FLASH3 ("" ())
+ FLASH4 ()
+EndOpt
+
diff --git a/bsp/wh44b0/rtconfig.h b/bsp/wh44b0/rtconfig.h new file mode 100644 index 0000000000..11d663b5e9 --- /dev/null +++ b/bsp/wh44b0/rtconfig.h @@ -0,0 +1,119 @@ +/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX 256
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using Faset Event*/
+/* #define RT_USING_FASTEVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+/* #define RT_USING_SMALL_MEM */
+
+/* Using SLAB Allocator*/
+#define RT_USING_SLAB
+
+/* SECTION: Device System */
+/* Using Device System*/
+#define RT_USING_DEVICE
+
+/* SECTION: Console options */
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+/* #define RT_USING_FINSH */
+
+/* SECTION: a mini libc */
+/* Using mini libc library*/
+/* #define RT_USING_MINILIBC */
+
+/* SECTION: C++ support */
+/* Using C++ support*/
+/* #define RT_USING_CPLUSPLUS */
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* Using lighweight TCP/IP protocol stack*/
+/* #define RT_USING_LWIP */
+
+/* Trace LwIP protocol*/
+/* #define RT_LWIP_DEBUG */
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+
+/* Enable IGMP protocol*/
+#define RT_LWIP_IGMP
+
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+
+/* Enable SNMP protocol*/
+/* #define RT_LWIP_SNMP */
+
+/* Using DHCP*/
+/* #define RT_LWIP_DHCP */
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 0
+#define RT_LWIP_IPADDR3 30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 0
+#define RT_LWIP_GWADDR3 1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+
+#endif
diff --git a/bsp/wh44b0/skyeye.conf b/bsp/wh44b0/skyeye.conf new file mode 100644 index 0000000000..817bc4f5ef --- /dev/null +++ b/bsp/wh44b0/skyeye.conf @@ -0,0 +1,5 @@ +cpu: arm7tdmi +mach: s3c44b0 +mem_bank: map=M, type=R, addr=0x00000000, size=0x00200000, file=./rtthread-wh44b0.bin +mem_bank: map=I, type=RW, addr=0x01c00000, size=0x00400000 +mem_bank: map=M, type=RW, addr=0x0C000000, size=0x00800000 diff --git a/bsp/wh44b0/startup.c b/bsp/wh44b0/startup.c new file mode 100644 index 0000000000..2eba637d71 --- /dev/null +++ b/bsp/wh44b0/startup.c @@ -0,0 +1,121 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-23 Bernard first version + * 2006-10-05 Bernard add .nobbs attribute for _svc_stack_start + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <s3c44b0.h> +#include <board.h> + +extern void rt_hw_interrupt_init(void); +extern void rt_serial_init(void); +extern void rt_hw_cpu_icache_enable(void); + +/** + * @addtogroup wh44b0 + */ +/*@{*/ + +#ifdef __CC_ARM
+extern int Image$$RW_RAM1$$ZI$$Limit;
+#else
+extern int __bss_end;
+#endif
+ +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +#endif +extern int rt_application_init(void); + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* enable cpu cache */ + rt_hw_cpu_icache_enable(); + + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* init board */ + rt_hw_board_init(); + + /* init hardware serial */ + rt_serial_init(); + + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + + /* init memory system */ +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)0xD000000); +#else + rt_system_heap_init((void*)&__bss_end, (void*)0xD000000); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_HOOK + /* set idle thread hook */ + rt_thread_idle_sethook(rt_hw_led_flash); +#endif + +#ifdef RT_USING_DEVICE + rt_device_init_all(); +#endif + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init the finsh input */ + rt_hw_finsh_init(); + + /* init finsh */ + finsh_system_init(); +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* unmask interrupt */ + rt_hw_interrupt_umask(INT_GLOBAL); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +}
+ +int main(void)
+{
+ /* invoke rtthread startup */
+ rtthread_startup();
+}
+ +/*@}*/ diff --git a/bsp/wh44b0/wh44b0_ram.lds b/bsp/wh44b0/wh44b0_ram.lds new file mode 100644 index 0000000000..e40eaa3b28 --- /dev/null +++ b/bsp/wh44b0/wh44b0_ram.lds @@ -0,0 +1,43 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x0c000000; + + . = ALIGN(4); + .text : { + *(.init) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .nobss : { *(.nobss) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + /* stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _end = .; +} diff --git a/bsp/wh44b0/wh44b0_rom.lds b/bsp/wh44b0/wh44b0_rom.lds new file mode 100644 index 0000000000..85e0c57027 --- /dev/null +++ b/bsp/wh44b0/wh44b0_rom.lds @@ -0,0 +1,43 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x0c000000; + + . = ALIGN(4); + .text : { + *(.init) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .nobss : { *(.nobss) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + /* stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _end = .; +} |