diff options
| author | bernard.xiong <[email protected]> | 2009-12-26 07:12:39 +0000 |
|---|---|---|
| committer | bernard.xiong <[email protected]> | 2009-12-26 07:12:39 +0000 |
| commit | d65e9dd6109a62e65ce24130dd9781bea3c48cd4 (patch) | |
| tree | 52d41411062dec201fd94847bf4ca9c76b0d6775 /bsp | |
| parent | 0dc84a480af07e93c20d097e3978d0e1b3cb3ae8 (diff) | |
add EXT_SRAM configuration.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@232 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/stm3210/board.c | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/bsp/stm3210/board.c b/bsp/stm3210/board.c index 17f1439288..9581d7668e 100644 --- a/bsp/stm3210/board.c +++ b/bsp/stm3210/board.c @@ -16,6 +16,7 @@ #include <rtthread.h>
#include "stm32f10x.h"
+#include "stm32f10x_fsmc.h"
#include "board.h"
static void rt_hw_console_init(void);
@@ -64,6 +65,88 @@ void SysTick_Configuration(void) SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
}
+#if STM32_EXT_SRAM
+#define Bank1_SRAM3_ADDR ((u32)0x68000000)
+void EXT_SRAM_Configuration(void)
+{
+ FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
+ FSMC_NORSRAMTimingInitTypeDef p;
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
+ RCC_APB2Periph_GPIOF, ENABLE);
+
+ /*-- GPIO Configuration ------------------------------------------------------*/
+ /* SRAM Data lines configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+ GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+ GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
+ GPIO_Pin_15;
+ GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+ /* SRAM Address lines configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
+ GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
+ GPIO_Pin_14 | GPIO_Pin_15;
+ GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
+ GPIO_Pin_4 | GPIO_Pin_5;
+ GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ /* NOE and NWE configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ /* NE3 NE4 configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_12;
+ GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+ /* NBL0, NBL1 configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
+ GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+ /*-- FSMC Configuration ------------------------------------------------------*/
+ p.FSMC_AddressSetupTime = 0;
+ p.FSMC_AddressHoldTime = 0;
+ p.FSMC_DataSetupTime = 2;
+ p.FSMC_BusTurnAroundDuration = 0;
+ p.FSMC_CLKDivision = 0;
+ p.FSMC_DataLatency = 0;
+ p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+ /* Enable FSMC Bank1_SRAM Bank */
+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+}
+#endif
+
/**
* This is the timer interrupt service routine.
*
@@ -90,6 +173,10 @@ void rt_hw_board_init() /* Configure the SysTick */
SysTick_Configuration();
+#if STM32_EXT_SRAM
+ EXT_SRAM_Configuration();
+#endif
+
rt_hw_console_init();
}
|