diff options
| author | qiuyiuestc <[email protected]> | 2009-12-25 14:39:36 +0000 |
|---|---|---|
| committer | qiuyiuestc <[email protected]> | 2009-12-25 14:39:36 +0000 |
| commit | 6774f3d1b011ff365174e8ff797dc4b31cc9b5eb (patch) | |
| tree | 3c92e8ef4199e59ac427e2e11f73211b469de747 /bsp | |
| parent | ad17cb7691720ca587b02c3fbaa403503b045bad (diff) | |
Add Libraries directory for lm3s
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@229 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'bsp')
56 files changed, 57890 insertions, 0 deletions
diff --git a/bsp/lm3s/Libraries/driverlib/adc.c b/bsp/lm3s/Libraries/driverlib/adc.c new file mode 100644 index 0000000000..792fdbc697 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/adc.c @@ -0,0 +1,979 @@ +//*****************************************************************************
+//
+// adc.c - Driver for the ADC.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup adc_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_adc.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/adc.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// These defines are used by the ADC driver to simplify access to the ADC
+// sequencer's registers.
+//
+//*****************************************************************************
+#define ADC_SEQ (ADC_O_SSMUX0)
+#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
+#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
+#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
+#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
+#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
+
+//*****************************************************************************
+//
+// The currently configured software oversampling factor for each of the ADC
+// sequencers.
+//
+//*****************************************************************************
+static unsigned char g_pucOversampleFactor[3];
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an ADC interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! ADC sample sequence interrupt occurs.
+//!
+//! This function sets the handler to be called when a sample sequence
+//! interrupt occurs. This will enable the global interrupt in the interrupt
+//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
+//! is the interrupt handler's responsibility to clear the interrupt source via
+//! ADCIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
+ void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine the interrupt to register based on the sequence number.
+ //
+ ulInt = INT_ADC0 + ulSequenceNum;
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the timer interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for an ADC interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function unregisters the interrupt handler. This will disable the
+//! global interrupt in the interrupt controller; the sequence interrupt must
+//! be disabled via ADCIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine the interrupt to unregister based on the sequence number.
+ //
+ ulInt = INT_ADC0 + ulSequenceNum;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence interrupt. Any
+//! outstanding interrupts are cleared before enabling the sample sequence
+//! interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear any outstanding interrupts on this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
+
+ //
+ // Enable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the specified sample sequence.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current raw or masked interrupt status.
+//
+//*****************************************************************************
+unsigned long
+ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
+ tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));
+ }
+ else
+ {
+ return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence interrupt source.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! The specified sample sequence interrupt is cleared, so that it no longer
+//! asserts. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the interrupt.
+ //
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! Allows the specified sample sequence to be captured when its trigger is
+//! detected. A sample sequence must be configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Enable the specified sequence.
+ //
+ HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! Prevents the specified sample sequence from being captured when its trigger
+//! is detected. A sample sequence should be disabled before it is configured.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable the specified sequences.
+ //
+ HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Configures the trigger source and priority of a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulTrigger is the trigger source that initiates the sample sequence;
+//! must be one of the \b ADC_TRIGGER_* values.
+//! \param ulPriority is the relative priority of the sample sequence with
+//! respect to the other sample sequences.
+//!
+//! This function configures the initiation criteria for a sample sequence.
+//! Valid sample sequences range from zero to three; sequence zero will capture
+//! up to eight samples, sequences one and two will capture up to four samples,
+//! and sequence three will capture a single sample. The trigger condition and
+//! priority (with respect to other sample sequence execution) is set.
+//!
+//! The \e ulTrigger parameter can take on the following values:
+//!
+//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
+//! ADCProcessorTrigger() function.
+//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
+//! B4 pin.
+//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
+//! TimerControlTrigger().
+//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
+//! sample sequence to capture repeatedly (so long as
+//! there is not a higher priority source active).
+//!
+//! Note that not all trigger sources are available on all Stellaris family
+//! members; consult the data sheet for the device in question to determine the
+//! availability of triggers.
+//!
+//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents
+//! the highest priority and 3 the lowest. Note that when programming the
+//! priority among a set of sample sequences, each must have unique priority;
+//! it is up to the caller to guarantee the uniqueness of the priorities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long ulTrigger, unsigned long ulPriority)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+ ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
+ (ulTrigger == ADC_TRIGGER_COMP0) ||
+ (ulTrigger == ADC_TRIGGER_COMP1) ||
+ (ulTrigger == ADC_TRIGGER_COMP2) ||
+ (ulTrigger == ADC_TRIGGER_EXTERNAL) ||
+ (ulTrigger == ADC_TRIGGER_TIMER) ||
+ (ulTrigger == ADC_TRIGGER_PWM0) ||
+ (ulTrigger == ADC_TRIGGER_PWM1) ||
+ (ulTrigger == ADC_TRIGGER_PWM2) ||
+ (ulTrigger == ADC_TRIGGER_ALWAYS));
+ ASSERT(ulPriority < 4);
+
+ //
+ // Compute the shift for the bits that control this sample sequence.
+ //
+ ulSequenceNum *= 4;
+
+ //
+ // Set the trigger event for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
+ ~(0xf << ulSequenceNum)) |
+ ((ulTrigger & 0xf) << ulSequenceNum));
+
+ //
+ // Set the priority for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
+ ~(0xf << ulSequenceNum)) |
+ ((ulPriority & 0x3) << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Configure a step of the sample sequencer.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulStep is the step to be configured.
+//! \param ulConfig is the configuration of this step; must be a logical OR of
+//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
+//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).
+//!
+//! This function will set the configuration of the ADC for one step of a
+//! sample sequence. The ADC can be configured for single-ended or
+//! differential operation (the \b ADC_CTL_D bit selects differential
+//! operation when set), the channel to be sampled can be chosen (the
+//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature
+//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step
+//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it
+//! can be configured to cause an interrupt when the step is complete (the
+//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the
+//! appropriate time when the trigger for this sequence occurs.
+//!
+//! The \e ulStep parameter determines the order in which the samples are
+//! captured by the ADC when the trigger occurs. It can range from zero to
+//! seven for the first sample sequence, from zero to three for the second and
+//! third sample sequence, and can only be zero for the fourth sample sequence.
+//!
+//! Differential mode only works with adjacent channel pairs (for example, 0
+//! and 1). The channel select must be the number of the channel pair to
+//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
+//! and 3) or undefined results will be returned by the ADC. Additionally, if
+//! differential mode is selected when the temperature sensor is being sampled,
+//! undefined results will be returned by the ADC.
+//!
+//! It is the responsibility of the caller to ensure that a valid configuration
+//! is specified; this function does not check the validity of the specified
+//! configuration.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long ulStep, unsigned long ulConfig)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+ ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
+ ((ulSequenceNum == 1) && (ulStep < 4)) ||
+ ((ulSequenceNum == 2) && (ulStep < 4)) ||
+ ((ulSequenceNum == 3) && (ulStep < 1)));
+
+ //
+ // Get the offset of the sequence to be configured.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Compute the shift for the bits that control this step.
+ //
+ ulStep *= 4;
+
+ //
+ // Set the analog mux value for this step.
+ //
+ HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
+ ~(0x0000000f << ulStep)) |
+ ((ulConfig & 0x0f) << ulStep));
+
+ //
+ // Set the control value for this step.
+ //
+ HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
+ ~(0x0000000f << ulStep)) |
+ (((ulConfig & 0xf0) >> 4) << ulStep));
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence overflow occurred.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This determines if a sample sequence overflow has occurred. This will
+//! happen if the captured samples are not read from the FIFO before the next
+//! trigger occurs.
+//!
+//! \return Returns zero if there was not an overflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+long
+ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine if there was an overflow on this sequence.
+ //
+ return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the overflow condition on a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This will clear an overflow condition on one of the sample sequences. The
+//! overflow condition must be cleared in order to detect a subsequent overflow
+//! condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the overflow condition for this sequence.
+ //
+ HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence underflow occurred.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This determines if a sample sequence underflow has occurred. This will
+//! happen if too many samples are read from the FIFO.
+//!
+//! \return Returns zero if there was not an underflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+long
+ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine if there was an underflow on this sequence.
+ //
+ return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the underflow condition on a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This will clear an underflow condition on one of the sample sequences. The
+//! underflow condition must be cleared in order to detect a subsequent
+//! underflow condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the underflow condition for this sequence.
+ //
+ HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pulBuffer is the address where the data is stored.
+//!
+//! This function copies data from the specified sample sequence output FIFO to
+//! a memory resident buffer. The number of samples available in the hardware
+//! FIFO are copied into the buffer, which is assumed to be large enough to
+//! hold that many samples. This will only return the samples that are
+//! presently available, which may not be the entire sample sequence if it is
+//! in the process of being executed.
+//!
+//! \return Returns the number of samples copied to the buffer.
+//
+//*****************************************************************************
+long
+ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long *pulBuffer)
+{
+ unsigned long ulCount;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Get the offset of the sequence to be read.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Read samples from the FIFO until it is empty.
+ //
+ ulCount = 0;
+ while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8))
+ {
+ //
+ // Read the FIFO and copy it to the destination.
+ //
+ *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO);
+
+ //
+ // Increment the count of samples read.
+ //
+ ulCount++;
+ }
+
+ //
+ // Return the number of samples read.
+ //
+ return(ulCount);
+}
+
+//*****************************************************************************
+//
+//! Causes a processor trigger for a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function triggers a processor-initiated sample sequence if the sample
+//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Generate a processor trigger for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Configures the software oversampling factor of the ADC.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulFactor is the number of samples to be averaged.
+//!
+//! This function configures the software oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data. Oversampling is
+//! accomplished by averaging multiple samples from the same analog input.
+//! Three different oversampling rates are supported; 2x, 4x, and 8x.
+//!
+//! Oversampling is only supported on the sample sequencers that are more than
+//! one sample in depth (that is, the fourth sample sequencer is not
+//! supported). Oversampling by 2x (for example) divides the depth of the
+//! sample sequencer by two; so 2x oversampling on the first sample sequencer
+//! can only provide four samples per trigger. This also means that 8x
+//! oversampling is only available on the first sample sequencer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulFactor)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
+ ((ulSequenceNum == 0) || (ulFactor != 8)));
+
+ //
+ // Convert the oversampling factor to a shift factor.
+ //
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
+ {
+ }
+
+ //
+ // Save the sfiht factor.
+ //
+ g_pucOversampleFactor[ulSequenceNum] = ulValue;
+}
+
+//*****************************************************************************
+//
+//! Configures a step of the software oversampled sequencer.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulStep is the step to be configured.
+//! \param ulConfig is the configuration of this step.
+//!
+//! This function configures a step of the sample sequencer when using the
+//! software oversampling feature. The number of steps available depends on
+//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
+//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulSequenceNum == 0) &&
+ (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
+ (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
+
+ //
+ // Get the offset of the sequence to be configured.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Compute the shift for the bits that control this step.
+ //
+ ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
+
+ //
+ // Loop through the hardware steps that make up this step of the software
+ // oversampled sequence.
+ //
+ for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
+ ulSequenceNum; ulSequenceNum--)
+ {
+ //
+ // Set the analog mux value for this step.
+ //
+ HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
+ ~(0x0000000f << ulStep)) |
+ ((ulConfig & 0x0f) << ulStep));
+
+ //
+ // Set the control value for this step.
+ //
+ HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
+ ~(0x0000000f << ulStep)) |
+ (((ulConfig & 0xf0) >> 4) << ulStep));
+ if(ulSequenceNum != 1)
+ {
+ HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
+ ADC_SSCTL0_END0) << ulStep);
+ }
+
+ //
+ // Go to the next hardware step.
+ //
+ ulStep += 4;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence using software oversampling.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pulBuffer is the address where the data is stored.
+//! \param ulCount is the number of samples to be read.
+//!
+//! This function copies data from the specified sample sequence output FIFO to
+//! a memory resident buffer with software oversampling applied. The requested
+//! number of samples are copied into the data buffer; if there are not enough
+//! samples in the hardware FIFO to satisfy this many oversampled data items
+//! then incorrect results will be returned. It is the caller's responsibility
+//! to read only the samples that are available and wait until enough data is
+//! available, for example as a result of receiving an interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long *pulBuffer, unsigned long ulCount)
+{
+ unsigned long ulIdx, ulAccum;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulSequenceNum == 0) &&
+ (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
+ (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
+
+ //
+ // Get the offset of the sequence to be read.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Read the samples from the FIFO until it is empty.
+ //
+ while(ulCount--)
+ {
+ //
+ // Compute the sum of the samples.
+ //
+ ulAccum = 0;
+ for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
+ {
+ //
+ // Read the FIFO and add it to the accumulator.
+ //
+ ulAccum += HWREG(ulBase + ADC_SSFIFO);
+ }
+
+ //
+ // Write the averaged sample to the output buffer.
+ //
+ *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the hardware oversampling factor of the ADC.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulFactor is the number of samples to be averaged.
+//!
+//! This function configures the hardware oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data. Oversampling is
+//! accomplished by averaging multiple samples from the same analog input. Six
+//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
+//! Specifying an oversampling factor of zero will disable hardware
+//! oversampling.
+//!
+//! Hardware oversampling applies uniformly to all sample sequencers. It does
+//! not reduce the depth of the sample sequencers like the software
+//! oversampling APIs; each sample written into the sample sequence FIFO is a
+//! fully oversampled analog input reading.
+//!
+//! Enabling hardware averaging increases the precision of the ADC at the cost
+//! of throughput. For example, enabling 4x oversampling reduces the
+//! throughput of a 250 Ksps ADC to 62.5 Ksps.
+//!
+//! \note Hardware oversampling is available beginning with Rev C0 of the
+//! Stellaris microcontroller.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
+ (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
+ (ulFactor == 64)));
+
+ //
+ // Convert the oversampling factor to a shift factor.
+ //
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
+ {
+ }
+
+ //
+ // Write the shift factor to the ADC to configure the hardware oversampler.
+ //
+ HWREG(ulBase + ADC_O_SAC) = ulValue;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/adc.h b/bsp/lm3s/Libraries/driverlib/adc.h new file mode 100644 index 0000000000..6a008ce7ce --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/adc.h @@ -0,0 +1,149 @@ +//*****************************************************************************
+//
+// adc.h - ADC headers for using the ADC driver functions.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger
+// parameter.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
+// parameter.
+//
+//*****************************************************************************
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select
+#define ADC_CTL_IE 0x00000040 // Interrupt enable
+#define ADC_CTL_END 0x00000020 // Sequence end select
+#define ADC_CTL_D 0x00000010 // Differential select
+#define ADC_CTL_CH0 0x00000000 // Input channel 0
+#define ADC_CTL_CH1 0x00000001 // Input channel 1
+#define ADC_CTL_CH2 0x00000002 // Input channel 2
+#define ADC_CTL_CH3 0x00000003 // Input channel 3
+#define ADC_CTL_CH4 0x00000004 // Input channel 4
+#define ADC_CTL_CH5 0x00000005 // Input channel 5
+#define ADC_CTL_CH6 0x00000006 // Input channel 6
+#define ADC_CTL_CH7 0x00000007 // Input channel 7
+#define ADC_CTL_CH8 0x00000008 // Input channel 8
+#define ADC_CTL_CH9 0x00000009 // Input channel 9
+#define ADC_CTL_CH10 0x0000000A // Input channel 10
+#define ADC_CTL_CH11 0x0000000B // Input channel 11
+#define ADC_CTL_CH12 0x0000000C // Input channel 12
+#define ADC_CTL_CH13 0x0000000D // Input channel 13
+#define ADC_CTL_CH14 0x0000000E // Input channel 14
+#define ADC_CTL_CH15 0x0000000F // Input channel 15
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
+ void (*pfnHandler)(void));
+extern void ADCIntUnregister(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern unsigned long ADCIntStatus(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ tBoolean bMasked);
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCSequenceEnable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceDisable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulTrigger,
+ unsigned long ulPriority);
+extern void ADCSequenceStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig);
+extern long ADCSequenceOverflow(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceOverflowClear(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern long ADCSequenceUnderflow(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern long ADCSequenceDataGet(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long *pulBuffer);
+extern void ADCProcessorTrigger(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulFactor);
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig);
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long *pulBuffer,
+ unsigned long ulCount);
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulFactor);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ADC_H__
diff --git a/bsp/lm3s/Libraries/driverlib/can.c b/bsp/lm3s/Libraries/driverlib/can.c new file mode 100644 index 0000000000..4bd4c0e105 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/can.c @@ -0,0 +1,2203 @@ +//*****************************************************************************
+//
+// can.c - Driver for the CAN module.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup can_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_can.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/can.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// This is the maximum number that can be stored as an 11bit Message
+// identifier.
+//
+//*****************************************************************************
+#define CAN_MAX_11BIT_MSG_ID (0x7ff)
+
+//*****************************************************************************
+//
+// This is used as the loop delay for accessing the CAN controller registers.
+//
+//*****************************************************************************
+#define CAN_RW_DELAY (5)
+
+//
+// The maximum CAN bit timing divisor is 13.
+//
+#define CAN_MAX_BIT_DIVISOR (13)
+
+//
+// The minimum CAN bit timing divisor is 5.
+//
+#define CAN_MIN_BIT_DIVISOR (5)
+
+//
+// The maximum CAN pre-divisor is 1024.
+//
+#define CAN_MAX_PRE_DIVISOR (1024)
+
+//
+// The minimum CAN pre-divisor is 1024.
+//
+#define CAN_MIN_PRE_DIVISOR (1024)
+
+//*****************************************************************************
+//
+// This table is used by the CANBitRateSet() API as the register defaults for
+// the bit timing values.
+//
+//*****************************************************************************
+static const unsigned short g_usCANBitValues[] =
+{
+ 0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5
+ 0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6
+ 0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7
+ 0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8
+ 0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9
+ 0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10
+ 0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11
+ 0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12
+ 0x3740 // TSEG2 4, TSEG1 8, SJW 2, Divide 13
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a CAN base address.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//!
+//! This function determines if a CAN controller base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+CANBaseValid(unsigned long ulBase)
+{
+ return((ulBase == CAN0_BASE) || (ulBase == CAN1_BASE) ||
+ (ulBase == CAN2_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Returns the CAN controller interrupt number.
+//!
+//! \param ulBase is the base address of the selected CAN controller
+//!
+//! Given a CAN controller base address, returns the corresponding interrupt
+//! number.
+//!
+//! This function replaces the original CANGetIntNumber() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return Returns a CAN interrupt number, or -1 if \e ulPort is invalid.
+//
+//*****************************************************************************
+static long
+CANIntNumberGet(unsigned long ulBase)
+{
+ long lIntNumber;
+
+ //
+ // Return the interrupt number for the given CAN controller.
+ //
+ switch(ulBase)
+ {
+ //
+ // Return the interrupt number for CAN 0
+ //
+ case CAN0_BASE:
+ {
+ lIntNumber = INT_CAN0;
+ break;
+ }
+
+ //
+ // Return the interrupt number for CAN 1
+ //
+ case CAN1_BASE:
+ {
+ lIntNumber = INT_CAN1;
+ break;
+ }
+
+ //
+ // Return the interrupt number for CAN 2
+ //
+ case CAN2_BASE:
+ {
+ lIntNumber = INT_CAN2;
+ break;
+ }
+
+ //
+ // Return -1 to indicate a bad address was passed in.
+ //
+ default:
+ {
+ lIntNumber = -1;
+ }
+ }
+ return(lIntNumber);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Reads a CAN controller register.
+//!
+//! \param ulRegAddress is the full address of the CAN register to be read.
+//!
+//! This function performs the necessary synchronization to read from a CAN
+//! controller register.
+//!
+//! This function replaces the original CANReadReg() API and performs the same
+//! actions. A macro is provided in <tt>can.h</tt> to map the original API to
+//! this API.
+//!
+//! \note This function provides the delay required to access CAN registers.
+//! This delay is required when accessing CAN registers directly.
+//!
+//! \return Returns the value read from the register.
+//
+//*****************************************************************************
+static unsigned long
+CANRegRead(unsigned long ulRegAddress)
+{
+ volatile int iDelay;
+ unsigned long ulRetVal;
+ unsigned long ulIntNumber;
+ unsigned long ulReenableInts;
+
+ //
+ // Get the CAN interrupt number from the register base address.
+ //
+ ulIntNumber = CANIntNumberGet(ulRegAddress & 0xfffff000);
+
+ //
+ // Make sure that the CAN base address was valid.
+ //
+ ASSERT(ulIntNumber != (unsigned long)-1);
+
+ //
+ // Remember current state so that CAN interrupts are only re-enabled if
+ // they were already enabled.
+ //
+ ulReenableInts = HWREG(NVIC_EN1) & (1 << (ulIntNumber - 48));
+
+ //
+ // If the CAN interrupt was enabled then disable it.
+ //
+ if(ulReenableInts)
+ {
+ IntDisable(ulIntNumber);
+ }
+
+ //
+ // Trigger the inital read to the CAN controller. The value returned at
+ // this point is not valid.
+ //
+ HWREG(ulRegAddress);
+
+ //
+ // This delay is necessary for the CAN have the correct data on the bus.
+ //
+ for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
+ {
+ }
+
+ //
+ // Do the final read that has the valid value of the register.
+ //
+ ulRetVal = HWREG(ulRegAddress);
+
+ //
+ // Reenable CAN interrupts if they were enabled before this call.
+ //
+ if(ulReenableInts)
+ {
+ IntEnable(ulIntNumber);
+ }
+
+ return(ulRetVal);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Writes a CAN controller register.
+//!
+//! \param ulRegAddress is the full address of the CAN register to be written.
+//! \param ulRegValue is the value to write into the register specified by
+//! \e ulRegAddress.
+//!
+//! This function takes care of the synchronization necessary to write to a
+//! CAN controller register.
+//!
+//! This function replaces the original CANWriteReg() API and performs the same
+//! actions. A macro is provided in <tt>can.h</tt> to map the original API to
+//! this API.
+//!
+//! \note The delays in this function are required when accessing CAN registers
+//! directly.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
+{
+ volatile int iDelay;
+
+ //
+ // Trigger the inital write to the CAN controller. The value will not make
+ // it out to the CAN controller for CAN_RW_DELAY cycles.
+ //
+ HWREG(ulRegAddress) = ulRegValue;
+
+ //
+ // Delay to allow the CAN controller to receive the new data.
+ //
+ for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Copies data from a buffer to the CAN Data registers.
+//!
+//! \param pucData is a pointer to the data to be written out to the CAN
+//! controller's data registers.
+//! \param pulRegister is an unsigned long pointer to the first register of the
+//! CAN controller's data registers. For example, in order to use the IF1
+//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b +
+//! \b CAN_O_IF1DA1.
+//! \param iSize is the number of bytes to copy into the CAN controller.
+//!
+//! This function takes the steps necessary to copy data from a contiguous
+//! buffer in memory into the non-contiguous data registers used by the CAN
+//! controller. This function is rarely used outside of the CANMessageSet()
+//! function.
+//!
+//! This function replaces the original CANWriteDataReg() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize)
+{
+ int iIdx;
+ unsigned long ulValue;
+
+ //
+ // Loop always copies 1 or 2 bytes per iteration.
+ //
+ for(iIdx = 0; iIdx < iSize; )
+ {
+
+ //
+ // Write out the data 16 bits at a time since this is how the registers
+ // are aligned in memory.
+ //
+ ulValue = pucData[iIdx++];
+
+ //
+ // Only write the second byte if needed otherwise it will be zero.
+ //
+ if(iIdx < iSize)
+ {
+ ulValue |= (pucData[iIdx++] << 8);
+ }
+ CANRegWrite((unsigned long)(pulRegister++), ulValue);
+ }
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Copies data from a buffer to the CAN Data registers.
+//!
+//! \param pucData is a pointer to the location to store the data read from the
+//! CAN controller's data registers.
+//! \param pulRegister is an unsigned long pointer to the first register of the
+//! CAN controller's data registers. For example, in order to use the IF1
+//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b +
+//! \b CAN_O_IF1DA1.
+//! \param iSize is the number of bytes to copy from the CAN controller.
+//!
+//! This function takes the steps necessary to copy data to a contiguous buffer
+//! in memory from the non-contiguous data registers used by the CAN
+//! controller. This function is rarely used outside of the CANMessageGet()
+//! function.
+//!
+//! This function replaces the original CANReadDataReg() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
+{
+ int iIdx;
+ unsigned long ulValue;
+
+ //
+ // Loop always copies 1 or 2 bytes per iteration.
+ //
+ for(iIdx = 0; iIdx < iSize; )
+ {
+ //
+ // Read out the data 16 bits at a time since this is how the registers
+ // are aligned in memory.
+ //
+ ulValue = CANRegRead((unsigned long)(pulRegister++));
+
+ //
+ // Store the first byte.
+ //
+ pucData[iIdx++] = (unsigned char)ulValue;
+
+ //
+ // Only read the second byte if needed.
+ //
+ if(iIdx < iSize)
+ {
+ pucData[iIdx++] = (unsigned char)(ulValue >> 8);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Initializes the CAN controller after reset.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//!
+//! After reset, the CAN controller is left in the disabled state. However,
+//! the memory used for message objects contains undefined values and must be
+//! cleared prior to enabling the CAN controller the first time. This prevents
+//! unwanted transmission or reception of data before the message objects are
+//! configured. This function must be called before enabling the controller
+//! the first time.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANInit(unsigned long ulBase)
+{
+ int iMsg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Place CAN controller in init state, regardless of previous state. This
+ // will put controller in idle, and allow the message object RAM to be
+ // programmed.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL, CAN_CTL_INIT);
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Clear the message value bit in the arbitration register. This indicates
+ // the message is not valid and is a "safe" condition to leave the message
+ // object. The same arb reg is used to program all the message objects.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB |
+ CAN_IF1CMSK_CONTROL);
+ CANRegWrite(ulBase + CAN_O_IF1ARB2, 0);
+ CANRegWrite(ulBase + CAN_O_IF1MCTL, 0);
+
+ //
+ // Loop through to program all 32 message objects
+ //
+ for(iMsg = 1; iMsg <= 32; iMsg++)
+ {
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Initiate programming the message object
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
+ }
+
+ //
+ // Make sure that the interrupt and new data flags are updated for the
+ // message objects.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_NEWDAT |
+ CAN_IF1CMSK_CLRINTPND);
+
+ //
+ // Loop through to program all 32 message objects
+ //
+ for(iMsg = 1; iMsg <= 32; iMsg++)
+ {
+ //
+ // Wait for busy bit to clear.
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Initiate programming the message object
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
+ }
+
+ //
+ // Acknowledge any pending status interrupts.
+ //
+ CANRegRead(ulBase + CAN_O_STS);
+}
+
+//*****************************************************************************
+//
+//! Enables the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller to enable.
+//!
+//! Enables the CAN controller for message processing. Once enabled, the
+//! controller will automatically transmit any pending frames, and process any
+//! received frames. The controller can be stopped by calling CANDisable().
+//! Prior to calling CANEnable(), CANInit() should have been called to
+//! initialize the controller and the CAN bus clock should be configured by
+//! calling CANBitTimingSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Clear the init bit in the control register.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) & ~CAN_CTL_INIT);
+}
+
+//*****************************************************************************
+//
+//! Disables the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller to disable.
+//!
+//! Disables the CAN controller for message processing. When disabled, the
+//! controller will no longer automatically process data on the CAN bus. The
+//! controller can be restarted by calling CANEnable(). The state of the CAN
+//! controller and the message objects in the controller are left as they were
+//! before this call was made.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Set the init bit in the control register.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) | CAN_CTL_INIT);
+}
+
+//*****************************************************************************
+//
+//! Reads the current settings for the CAN controller bit timing.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pClkParms is a pointer to a structure to hold the timing parameters.
+//!
+//! This function reads the current configuration of the CAN controller bit
+//! clock timing, and stores the resulting information in the structure
+//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the
+//! values that are returned in the structure pointed to by \e pClkParms.
+//!
+//! This function replaces the original CANGetBitTiming() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
+{
+ unsigned int uBitReg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT(pClkParms != 0);
+
+ //
+ // Read out all the bit timing values from the CAN controller registers.
+ //
+ uBitReg = CANRegRead(ulBase + CAN_O_BIT);
+
+ //
+ // Set the phase 2 segment.
+ //
+ pClkParms->uPhase2Seg = ((uBitReg & CAN_BIT_TSEG2_M) >> 12) + 1;
+
+ //
+ // Set the phase 1 segment.
+ //
+ pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BIT_TSEG1_M) >> 8) + 1;
+
+ //
+ // Set the sychronous jump width.
+ //
+ pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> 6) + 1;
+
+ //
+ // Set the pre-divider for the CAN bus bit clock.
+ //
+ pClkParms->uQuantumPrescaler =
+ ((uBitReg & CAN_BIT_BRP_M) |
+ ((CANRegRead(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1;
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the CAN bit timing values to a nominal setting
+//! based on a desired bit rate.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulSourceClock is the system clock for the device in Hz.
+//! \param ulBitRate is the desired bit rate.
+//!
+//! This function will set the CAN bit timing for the bit rate passed in the
+//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Since the
+//! CAN clock is based off of the system clock the calling function should pass
+//! in the source clock rate either by retrieving it from SysCtlClockGet() or
+//! using a specific value in Hz. The CAN bit clock is calculated to be an
+//! average timing value that should work for most systems. If tighter timing
+//! requirements are needed, then the CANBitTimingSet() function is available
+//! for full customization of all of the CAN bit timing values. Since not all
+//! bit rates can be matched exactly, the bit rate is set to the value closest
+//! to the desired bit rate without being higher than the \e ulBitRate value.
+//!
+//! \note On some devices the source clock is fixed at 8MHz so the
+//! \e ulSourceClock should be set to 8000000.
+//!
+//! \return This function returns the bit rate that the CAN controller was
+//! configured to use or it returns 0 to indicate that the bit rate was not
+//! changed because the requested bit rate was not valid.
+//!
+//*****************************************************************************
+unsigned long
+CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
+ unsigned long ulBitRate)
+{
+ unsigned long ulDesiredRatio;
+ unsigned long ulCANBits;
+ unsigned long ulPreDivide;
+ unsigned long ulRegValue;
+ unsigned short usCANCTL;
+
+ ASSERT(ulBitRate != 0);
+
+ //
+ // Caclulate the desired clock rate.
+ //
+ ulDesiredRatio = ulSourceClock / ulBitRate;
+
+ //
+ // If the ratio of CAN bit rate to processor clock is too small or too
+ // large then return 0 indicating that no bit rate was set.
+ //
+ if((ulDesiredRatio > (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)) ||
+ (ulDesiredRatio < CAN_MIN_BIT_DIVISOR))
+ {
+ return(0);
+ }
+
+ //
+ // Make sure that the Desired Ratio is not too large. This enforces the
+ // requirement that the bit rate is larger than requested.
+ //
+ if((ulSourceClock / ulDesiredRatio) > ulBitRate)
+ {
+ ulDesiredRatio += 1;
+ }
+
+ //
+ // Check all possible values to find a matching value.
+ //
+ while(ulDesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)
+ {
+ //
+ // Loop through all possible CAN bit divisors.
+ //
+ for(ulCANBits = CAN_MAX_BIT_DIVISOR; ulCANBits >= CAN_MIN_BIT_DIVISOR;
+ ulCANBits--)
+ {
+ //
+ // For a given CAN bit divisor save the pre divisor.
+ //
+ ulPreDivide = ulDesiredRatio / ulCANBits;
+
+ //
+ // If the caculated divisors match the desired clock ratio then
+ // return these bit rate and set the CAN bit timing.
+ //
+ if((ulPreDivide * ulCANBits) == ulDesiredRatio)
+ {
+ //
+ // Start building the bit timing value by adding the bit timing
+ // in time quanta.
+ //
+ ulRegValue = g_usCANBitValues[ulCANBits - CAN_MIN_BIT_DIVISOR];
+
+ //
+ // To set the bit timing register, the controller must be placed
+ // in init mode (if not already), and also configuration change
+ // bit enabled. The stat of the register should be saved
+ // so it can be restored.
+ //
+ usCANCTL = CANRegRead(ulBase + CAN_O_CTL);
+ CANRegWrite(ulBase + CAN_O_CTL, usCANCTL | CAN_CTL_INIT |
+ CAN_CTL_CCE);
+
+ //
+ // Now add in the pre-scalar on the bit rate.
+ //
+ ulRegValue |= ((ulPreDivide - 1)& CAN_BIT_BRP_M);
+
+ //
+ // Set the clock bits in the and the lower bits of the
+ // pre-scalar.
+ //
+ CANRegWrite(ulBase + CAN_O_BIT, ulRegValue);
+
+ //
+ // Set the divider upper bits in the extension register.
+ //
+ CANRegWrite(ulBase + CAN_O_BRPE,
+ ((ulPreDivide - 1) >> 6) & CAN_BRPE_BRPE_M);
+
+ //
+ // Restore the saved CAN Control register.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL, usCANCTL);
+
+ //
+ // Return the computed bit rate.
+ //
+ return(ulSourceClock / ( ulPreDivide * ulCANBits));
+ }
+ }
+
+ //
+ // Move the divisor up one and look again. Only in rare cases are
+ // more than 2 loops required to find the value.
+ //
+ ulDesiredRatio++;
+ }
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Configures the CAN controller bit timing.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pClkParms points to the structure with the clock parameters.
+//!
+//! Configures the various timing parameters for the CAN bus bit timing:
+//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
+//! the Synchronization Jump Width. The values for Propagation and Phase
+//! Buffer 1 segments are derived from the combination
+//! \e pClkParms->uSyncPropPhase1Seg parameter. Phase Buffer 2 is determined
+//! from the \e pClkParms->uPhase2Seg parameter. These two parameters, along
+//! with \e pClkParms->uSJW are based in units of bit time quanta. The actual
+//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value,
+//! which specifies the divisor for the CAN module clock.
+//!
+//! The total bit time, in quanta, will be the sum of the two Seg parameters,
+//! as follows:
+//!
+//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1
+//!
+//! Note that the Sync_Seg is always one quantum in duration, and will be added
+//! to derive the correct duration of Prop_Seg and Phase1_Seg.
+//!
+//! The equation to determine the actual bit rate is as follows:
+//!
+//! CAN Clock /
+//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler))
+//!
+//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1,
+//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be
+//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec.
+//!
+//! This function replaces the original CANSetBitTiming() API and performs the
+//! same actions. A macro is provided in <tt>can.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
+{
+ unsigned int uBitReg;
+ unsigned int uSavedInit;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT(pClkParms != 0);
+
+ //
+ // The phase 1 segment must be in the range from 2 to 16.
+ //
+ ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) &&
+ (pClkParms->uSyncPropPhase1Seg <= 16));
+
+ //
+ // The phase 2 segment must be in the range from 1 to 8.
+ //
+ ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8));
+
+ //
+ // The synchronous jump windows must be in the range from 1 to 4.
+ //
+ ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4));
+
+ //
+ // The CAN clock pre-divider must be in the range from 1 to 1024.
+ //
+ ASSERT((pClkParms->uQuantumPrescaler <= 1024) &&
+ (pClkParms->uQuantumPrescaler >= 1));
+
+ //
+ // To set the bit timing register, the controller must be placed in init
+ // mode (if not already), and also configuration change bit enabled. State
+ // of the init bit should be saved so it can be restored at the end.
+ //
+ uSavedInit = CANRegRead(ulBase + CAN_O_CTL);
+ CANRegWrite(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);
+
+ //
+ // Set the bit fields of the bit timing register according to the parms.
+ //
+ uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BIT_TSEG2_M;
+ uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BIT_TSEG1_M;
+ uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BIT_SJW_M;
+ uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP_M;
+ CANRegWrite(ulBase + CAN_O_BIT, uBitReg);
+
+ //
+ // Set the divider upper bits in the extension register.
+ //
+ CANRegWrite(ulBase + CAN_O_BRPE,
+ ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M);
+ //
+ // Clear the config change bit, and restore the init bit.
+ //
+ uSavedInit &= ~CAN_CTL_CCE;
+
+ //
+ // If Init was not set before, then clear it.
+ //
+ if(uSavedInit & CAN_CTL_INIT)
+ {
+ uSavedInit &= ~CAN_CTL_INIT;
+ }
+ CANRegWrite(ulBase + CAN_O_CTL, uSavedInit);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled CAN interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables CAN interrupts on the interrupt controller; specific CAN
+//! interrupt sources must be enabled using CANIntEnable(). The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! CANIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() should be used to enable CAN interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulIntNumber;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Get the actual interrupt number for this CAN controller.
+ //
+ ulIntNumber = CANIntNumberGet(ulBase);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulIntNumber, pfnHandler);
+
+ //
+ // Enable the Ethernet interrupt.
+ //
+ IntEnable(ulIntNumber);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the CAN controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt on the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulIntNumber;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Get the actual interrupt number for this CAN controller.
+ //
+ ulIntNumber = CANIntNumberGet(ulBase);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntUnregister(ulIntNumber);
+
+ //
+ // Disable the CAN interrupt.
+ //
+ IntDisable(ulIntNumber);
+}
+
+//*****************************************************************************
+//
+//! Enables individual CAN controller interrupt sources.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables specific interrupt sources of the CAN controller. Only enabled
+//! sources will cause a processor interrupt.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b CAN_INT_ERROR - a controller error condition has occurred
+//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has
+//! been detected
+//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts
+//!
+//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled.
+//! Further, for any particular transaction from a message object to generate
+//! an interrupt, that message object must have interrupts enabled (see
+//! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the
+//! controller enters the ``bus off'' condition, or if the error counters reach
+//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few
+//! status conditions and may provide more interrupts than the application
+//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine
+//! the cause.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);
+
+ //
+ // Enable the specified interrupts.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) | ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Disables individual CAN controller interrupt sources.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the specified CAN controller interrupt sources. Only enabled
+//! interrupt sources can cause a processor interrupt.
+//!
+//! The \e ulIntFlags parameter has the same definition as in the
+//! CANIntEnable() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);
+
+ //
+ // Disable the specified interrupts.
+ //
+ CANRegWrite(ulBase + CAN_O_CTL,
+ CANRegRead(ulBase + CAN_O_CTL) & ~(ulIntFlags));
+}
+
+//*****************************************************************************
+//
+//! Returns the current CAN controller interrupt status.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param eIntStsReg indicates which interrupt status register to read
+//!
+//! Returns the value of one of two interrupt status registers. The interrupt
+//! status register read is determined by the \e eIntStsReg parameter, which
+//! can have one of the following values:
+//!
+//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt
+//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message
+//! objects
+//!
+//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register
+//! and indicates the cause of the interrupt. It will be a value of
+//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case,
+//! the status register should be read with the CANStatusGet() function.
+//! Calling this function to read the status will also clear the status
+//! interrupt. If the value of the interrupt register is in the range 1-32,
+//! then this indicates the number of the highest priority message object that
+//! has an interrupt pending. The message object interrupt can be cleared by
+//! using the CANIntClear() function, or by reading the message using
+//! CANMessageGet() in the case of a received message. The interrupt handler
+//! can read the interrupt status again to make sure all pending interrupts are
+//! cleared before returning from the interrupt.
+//!
+//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects
+//! have pending interrupts. This can be used to discover all of the pending
+//! interrupts at once, as opposed to repeatedly reading the interrupt register
+//! by using \b CAN_INT_STS_CAUSE.
+//!
+//! \return Returns the value of one of the interrupt status registers.
+//
+//*****************************************************************************
+unsigned long
+CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // See which status the caller is looking for.
+ //
+ switch(eIntStsReg)
+ {
+ //
+ // The caller wants the global interrupt status for the CAN controller
+ // specified by ulBase.
+ //
+ case CAN_INT_STS_CAUSE:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_INT);
+ break;
+ }
+
+ //
+ // The caller wants the current message status interrupt for all
+ // messages.
+ //
+ case CAN_INT_STS_OBJECT:
+ {
+ //
+ // Read and combine both 16 bit values into one 32bit status.
+ //
+ ulStatus = (CANRegRead(ulBase + CAN_O_MSG1INT) &
+ CAN_MSG1INT_INTPND_M);
+ ulStatus |= (CANRegRead(ulBase + CAN_O_MSG2INT) << 16);
+ break;
+ }
+
+ //
+ // Request was for unknown status so just return 0.
+ //
+ default:
+ {
+ ulStatus = 0;
+ break;
+ }
+ }
+ //
+ // Return the interrupt status value
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears a CAN interrupt source.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulIntClr is a value indicating which interrupt source to clear.
+//!
+//! This function can be used to clear a specific interrupt source. The
+//! \e ulIntClr parameter should be one of the following values:
+//!
+//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt.
+//! - 1-32 - Clears the specified message object interrupt
+//!
+//! It is not necessary to use this function to clear an interrupt. This
+//! should only be used if the application wants to clear an interrupt source
+//! without taking the normal interrupt action.
+//!
+//! Normally, the status interrupt is cleared by reading the controller status
+//! using CANStatusGet(). A specific message object interrupt is normally
+//! cleared by reading the message object using CANMessageGet().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANIntClear(unsigned long ulBase, unsigned long ulIntClr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulIntClr == CAN_INT_INTID_STATUS) ||
+ ((ulIntClr>=1) && (ulIntClr <=32)));
+
+ if(ulIntClr == CAN_INT_INTID_STATUS)
+ {
+ //
+ // Simply read and discard the status to clear the interrupt.
+ //
+ CANRegRead(ulBase + CAN_O_STS);
+ }
+ else
+ {
+ //
+ // Wait to be sure that this interface is not busy.
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Only change the interrupt pending state by setting only the
+ // CAN_IF1CMSK_CLRINTPND bit.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_CLRINTPND);
+
+ //
+ // Send the clear pending interrupt command to the CAN controller.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, ulIntClr & CAN_IF1CRQ_MNUM_M);
+
+ //
+ // Wait to be sure that this interface is not busy.
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the CAN controller automatic retransmission behavior.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param bAutoRetry enables automatic retransmission.
+//!
+//! Enables or disables automatic retransmission of messages with detected
+//! errors. If \e bAutoRetry is \b true, then automatic retransmission is
+//! enabled, otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry)
+{
+ unsigned long ulCtlReg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ ulCtlReg = CANRegRead(ulBase + CAN_O_CTL);
+
+ //
+ // Conditionally set the DAR bit to enable/disable auto-retry.
+ //
+ if(bAutoRetry)
+ {
+ //
+ // Clearing the DAR bit tells the controller to not disable the
+ // auto-retry of messages which were not transmitted or received
+ // correctly.
+ //
+ ulCtlReg &= ~CAN_CTL_DAR;
+ }
+ else
+ {
+ //
+ // Setting the DAR bit tells the controller to disable the auto-retry
+ // of messages which were not transmitted or received correctly.
+ //
+ ulCtlReg |= CAN_CTL_DAR;
+ }
+
+ CANRegWrite(ulBase + CAN_O_CTL, ulCtlReg);
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting for automatic retransmission.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//!
+//! Reads the current setting for the automatic retransmission in the CAN
+//! controller and returns it to the caller.
+//!
+//! \return Returns \b true if automatic retransmission is enabled, \b false
+//! otherwise.
+//
+//*****************************************************************************
+tBoolean
+CANRetryGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Read the disable automatic retry setting from the CAN controller.
+ //
+ if(CANRegRead(ulBase + CAN_O_CTL) & CAN_CTL_DAR)
+ {
+ //
+ // Automatic data retransmission is not enabled.
+ //
+ return(false);
+ }
+
+ //
+ // Automatic data retransmission is enabled.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Reads one of the controller status registers.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param eStatusReg is the status register to read.
+//!
+//! Reads a status register of the CAN controller and returns it to the caller.
+//! The different status registers are:
+//!
+//! - \b CAN_STS_CONTROL - the main controller status
+//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission
+//! - \b CAN_STS_NEWDAT - bit mask of objects with new data
+//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration
+//!
+//! When reading the main controller status register, a pending status
+//! interrupt will be cleared. This should be used in the interrupt handler
+//! for the CAN controller if the cause is a status interrupt. The controller
+//! status register fields are as follows:
+//!
+//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition
+//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96
+//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state
+//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of
+//! any message filtering).
+//! - \b CAN_STATUS_TXOK - a message was successfully transmitted
+//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits)
+//! - \b CAN_STATUS_LEC_NONE - no error
+//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected
+//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part
+//! of a message
+//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged
+//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in
+//! recessive mode
+//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in
+//! dominant mode
+//! - \b CAN_STATUS_LEC_CRC - CRC error in received message
+//!
+//! The remaining status registers are 32-bit bit maps to the message objects.
+//! They can be used to quickly obtain information about the status of all the
+//! message objects without needing to query each one. They contain the
+//! following information:
+//!
+//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that
+//! means that a transmission is pending on that object. The application can
+//! use this to determine which objects are still waiting to send a message.
+//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means
+//! that a new message has been received in that object, and has not yet been
+//! picked up by the host application
+//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means
+//! it has a valid configuration programmed. The host application can use this
+//! to determine which message objects are empty/unused.
+//!
+//! \return Returns the value of the status register.
+//
+//*****************************************************************************
+unsigned long
+CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ switch(eStatusReg)
+ {
+ //
+ // Just return the global CAN status register since that is what was
+ // requested.
+ //
+ case CAN_STS_CONTROL:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_STS);
+ CANRegWrite(ulBase + CAN_O_STS,
+ ~(CAN_STS_RXOK | CAN_STS_TXOK | CAN_STS_LEC_M));
+ break;
+ }
+
+ //
+ // Combine the Transmit status bits into one 32bit value.
+ //
+ case CAN_STS_TXREQUEST:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_TXRQ1);
+ ulStatus |= CANRegRead(ulBase + CAN_O_TXRQ2) << 16;
+ break;
+ }
+
+ //
+ // Combine the New Data status bits into one 32bit value.
+ //
+ case CAN_STS_NEWDAT:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_NWDA1);
+ ulStatus |= CANRegRead(ulBase + CAN_O_NWDA2) << 16;
+ break;
+ }
+
+ //
+ // Combine the Message valid status bits into one 32bit value.
+ //
+ case CAN_STS_MSGVAL:
+ {
+ ulStatus = CANRegRead(ulBase + CAN_O_MSG1VAL);
+ ulStatus |= CANRegRead(ulBase + CAN_O_MSG2VAL) << 16;
+ break;
+ }
+
+ //
+ // Unknown CAN status requested so return 0.
+ //
+ default:
+ {
+ ulStatus = 0;
+ break;
+ }
+ }
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Reads the CAN controller error counter register.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param pulRxCount is a pointer to storage for the receive error counter.
+//! \param pulTxCount is a pointer to storage for the transmit error counter.
+//!
+//! Reads the error counter register and returns the transmit and receive error
+//! counts to the caller along with a flag indicating if the controller receive
+//! counter has reached the error passive limit. The values of the receive and
+//! transmit error counters are returned through the pointers provided as
+//! parameters.
+//!
+//! After this call, \e *pulRxCount will hold the current receive error count
+//! and \e *pulTxCount will hold the current transmit error count.
+//!
+//! \return Returns \b true if the receive error count has reached the error
+//! passive limit, and \b false if the error count is below the error passive
+//! limit.
+//
+//*****************************************************************************
+tBoolean
+CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
+ unsigned long *pulTxCount)
+{
+ unsigned long ulCANError;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+
+ //
+ // Read the current count of transmit/receive errors.
+ //
+ ulCANError = CANRegRead(ulBase + CAN_O_ERR);
+
+ //
+ // Extract the error numbers from the register value.
+ //
+ *pulRxCount = (ulCANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S;
+ *pulTxCount = (ulCANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S;
+
+ if(ulCANError & CAN_ERR_RP)
+ {
+ return(true);
+ }
+ return(false);
+}
+
+//*****************************************************************************
+//
+//! Configures a message object in the CAN controller.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulObjID is the object number to configure (1-32).
+//! \param pMsgObject is a pointer to a structure containing message object
+//! settings.
+//! \param eMsgType indicates the type of message for this object.
+//!
+//! This function is used to configure any one of the 32 message objects in the
+//! CAN controller. A message object can be configured as any type of CAN
+//! message object as well as several options for automatic transmission and
+//! reception. This call also allows the message object to be configured to
+//! generate interrupts on completion of message receipt or transmission. The
+//! message object can also be configured with a filter/mask so that actions
+//! are only taken when a message that meets certain parameters is seen on the
+//! CAN bus.
+//!
+//! The \e eMsgType parameter must be one of the following values:
+//!
+//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object.
+//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object.
+//! - \b MSG_OBJ_TYPE_RX - CAN receive message object.
+//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object.
+//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then
+//! transmit message object.
+//!
+//! The message object pointed to by \e pMsgObject must be populated by the
+//! caller, as follows:
+//!
+//! - \e ulMsgID - contains the message ID, either 11 or 29 bits.
+//! - \e ulMsgIDMask - mask of bits from \e ulMsgID that must match if
+//! identifier filtering is enabled.
+//! - \e ulFlags
+//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission.
+//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt.
+//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the
+//! identifier mask specified by \e ulMsgIDMask.
+//! - \e ulMsgLen - the number of bytes in the message data. This should be
+//! non-zero even for a remote frame; it should match the expected bytes of the
+//! data responding data frame.
+//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a
+//! data frame.
+//!
+//! \b Example: To send a data frame or remote frame(in response to a remote
+//! request), take the following steps:
+//!
+//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX.
+//! -# Set \e pMsgObject->ulMsgID to the message ID.
+//! -# Set \e pMsgObject->ulFlags. Make sure to set \b MSG_OBJ_TX_INT_ENABLE to
+//! allow an interrupt to be generated when the message is sent.
+//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the data frame.
+//! -# Set \e pMsgObject->pucMsgData to point to an array containing the bytes
+//! to send in the message.
+//! -# Call this function with \e ulObjID set to one of the 32 object buffers.
+//!
+//! \b Example: To receive a specific data frame, take the following steps:
+//!
+//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX.
+//! -# Set \e pMsgObject->ulMsgID to the full message ID, or a partial mask to
+//! use partial ID matching.
+//! -# Set \e pMsgObject->ulMsgIDMask bits that should be used for masking
+//! during comparison.
+//! -# Set \e pMsgObject->ulFlags as follows:
+//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame
+//! is received.
+//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering.
+//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data
+//! frame.
+//! -# The buffer pointed to by \e pMsgObject->pucMsgData and
+//! \e pMsgObject->ulMsgLen are not used by this call as no data is present at
+//! the time of the call.
+//! -# Call this function with \e ulObjID set to one of the 32 object buffers.
+//!
+//! If you specify a message object buffer that already contains a message
+//! definition, it will be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType)
+{
+ unsigned short usCmdMaskReg;
+ unsigned short usMaskReg[2];
+ unsigned short usArbReg[2];
+ unsigned short usMsgCtrl;
+ tBoolean bTransferData;
+ tBoolean bUseExtendedID;
+
+ bTransferData = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulObjID <= 32) && (ulObjID != 0));
+ ASSERT((eMsgType == MSG_OBJ_TYPE_TX) ||
+ (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
+ (eMsgType == MSG_OBJ_TYPE_RX) ||
+ (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) ||
+ (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
+ (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE));
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // See if we need to use an extended identifier or not.
+ //
+ if((pMsgObject->ulMsgID > CAN_MAX_11BIT_MSG_ID) ||
+ (pMsgObject->ulFlags & MSG_OBJ_EXTENDED_ID))
+ {
+ bUseExtendedID = 1;
+ }
+ else
+ {
+ bUseExtendedID = 0;
+ }
+
+ //
+ // This is always a write to the Message object as this call is setting a
+ // message object. This call will also always set all size bits so it sets
+ // both data bits. The call will use the CONTROL register to set control
+ // bits so this bit needs to be set as well.
+ //
+ usCmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB |
+ CAN_IF1CMSK_CONTROL);
+
+ //
+ // Initialize the values to a known state before filling them in based on
+ // the type of message object that is being configured.
+ //
+ usArbReg[0] = 0;
+ usMsgCtrl = 0;
+ usMaskReg[0] = 0;
+ usMaskReg[1] = 0;
+
+ switch(eMsgType)
+ {
+ //
+ // Transmit message object.
+ //
+ case MSG_OBJ_TYPE_TX:
+ {
+ //
+ // Set the TXRQST bit and the reset the rest of the register.
+ //
+ usMsgCtrl |= CAN_IF1MCTL_TXRQST;
+ usArbReg[1] = CAN_IF1ARB2_DIR;
+ bTransferData = 1;
+ break;
+ }
+
+ //
+ // Transmit remote request message object
+ //
+ case MSG_OBJ_TYPE_TX_REMOTE:
+ {
+ //
+ // Set the TXRQST bit and the reset the rest of the register.
+ //
+ usMsgCtrl |= CAN_IF1MCTL_TXRQST;
+ usArbReg[1] = 0;
+ break;
+ }
+
+ //
+ // Receive message object.
+ //
+ case MSG_OBJ_TYPE_RX:
+ {
+ //
+ // This clears the DIR bit along with everthing else. The TXRQST
+ // bit was cleard by defaulting usMsgCtrl to 0.
+ //
+ usArbReg[1] = 0;
+ break;
+ }
+
+ //
+ // Receive remote request message object.
+ //
+ case MSG_OBJ_TYPE_RX_REMOTE:
+ {
+ //
+ // The DIR bit is set to one for remote receivers. The TXRQST bit
+ // was cleard by defaulting usMsgCtrl to 0.
+ //
+ usArbReg[1] = CAN_IF1ARB2_DIR;
+
+ //
+ // Set this object so that it only indicates that a remote frame
+ // was received and allow for software to handle it by sending back
+ // a data frame.
+ //
+ usMsgCtrl = CAN_IF1MCTL_UMASK;
+
+ //
+ // Use the full Identifier by default.
+ //
+ usMaskReg[0] = 0xffff;
+ usMaskReg[1] = 0x1fff;
+
+ //
+ // Make sure to send the mask to the message object.
+ //
+ usCmdMaskReg |= CAN_IF1CMSK_MASK;
+ break;
+ }
+
+ //
+ // Remote frame receive remote, with auto-transmit message object.
+ //
+ case MSG_OBJ_TYPE_RXTX_REMOTE:
+ {
+ //
+ // Oddly the DIR bit is set to one for remote receivers.
+ //
+ usArbReg[1] = CAN_IF1ARB2_DIR;
+
+ //
+ // Set this object to auto answer if a matching identifier is seen.
+ //
+ usMsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK;
+
+ //
+ // The data to be returned needs to be filled in.
+ //
+ bTransferData = 1;
+ break;
+ }
+
+ //
+ // This case should never happen due to the ASSERT statement at the
+ // beginning of this function.
+ //
+ default:
+ {
+ return;
+ }
+ }
+
+ //
+ // Configure the Mask Registers.
+ //
+ if(pMsgObject->ulFlags & MSG_OBJ_USE_ID_FILTER)
+ {
+ if(bUseExtendedID)
+ {
+ //
+ // Set the 29 bits of Identifier mask that were requested.
+ //
+ usMaskReg[0] = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M;
+ usMaskReg[1] = ((pMsgObject->ulMsgIDMask >> 16) &
+ CAN_IF1MSK2_IDMSK_M);
+ }
+ else
+ {
+ //
+ // Lower 16 bit are unused so set them to zero.
+ //
+ usMaskReg[0] = 0;
+
+ //
+ // Put the 11 bit Mask Identifier into the upper bits of the field
+ // in the register.
+ //
+ usMaskReg[1] = ((pMsgObject->ulMsgIDMask << 2) &
+ CAN_IF1MSK2_IDMSK_M);
+ }
+ }
+
+ //
+ // If the caller wants to filter on the extended ID bit then set it.
+ //
+ if((pMsgObject->ulFlags & MSG_OBJ_USE_EXT_FILTER) ==
+ MSG_OBJ_USE_EXT_FILTER)
+ {
+ usMaskReg[1] |= CAN_IF1MSK2_MXTD;
+ }
+
+ //
+ // The caller wants to filter on the message direction field.
+ //
+ if((pMsgObject->ulFlags & MSG_OBJ_USE_DIR_FILTER) ==
+ MSG_OBJ_USE_DIR_FILTER)
+ {
+ usMaskReg[1] |= CAN_IF1MSK2_MDIR;
+ }
+
+ if(pMsgObject->ulFlags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER |
+ MSG_OBJ_USE_EXT_FILTER))
+ {
+ //
+ // Set the UMASK bit to enable using the mask register.
+ //
+ usMsgCtrl |= CAN_IF1MCTL_UMASK;
+
+ //
+ // Set the MASK bit so that this gets trasferred to the Message Object.
+ //
+ usCmdMaskReg |= CAN_IF1CMSK_MASK;
+ }
+
+ //
+ // Set the Arb bit so that this gets transferred to the Message object.
+ //
+ usCmdMaskReg |= CAN_IF1CMSK_ARB;
+
+ //
+ // Configure the Arbitration registers.
+ //
+ if(bUseExtendedID)
+ {
+ //
+ // Set the 29 bit version of the Identifier for this message object.
+ //
+ usArbReg[0] |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M;
+ usArbReg[1] |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M;
+
+ //
+ // Mark the message as valid and set the extended ID bit.
+ //
+ usArbReg[1] |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD;
+ }
+ else
+ {
+ //
+ // Set the 11 bit version of the Identifier for this message object.
+ // The lower 18 bits are set to zero.
+ //
+ usArbReg[1] |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M;
+
+ //
+ // Mark the message as valid.
+ //
+ usArbReg[1] |= CAN_IF1ARB2_MSGVAL;
+ }
+
+ //
+ // Set the data length since this is set for all transfers. This is also a
+ // single transfer and not a FIFO transfer so set EOB bit.
+ //
+ usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M) | CAN_IF1MCTL_EOB;
+
+ //
+ // Enable transmit interrupts if they should be enabled.
+ //
+ if(pMsgObject->ulFlags & MSG_OBJ_TX_INT_ENABLE)
+ {
+ usMsgCtrl |= CAN_IF1MCTL_TXIE;
+ }
+
+ //
+ // Enable receive interrupts if they should be enabled.
+ //
+ if(pMsgObject->ulFlags & MSG_OBJ_RX_INT_ENABLE)
+ {
+ usMsgCtrl |= CAN_IF1MCTL_RXIE;
+ }
+
+ //
+ // Write the data out to the CAN Data registers if needed.
+ //
+ if(bTransferData)
+ {
+ CANDataRegWrite(pMsgObject->pucMsgData,
+ (unsigned long *)(ulBase + CAN_O_IF1DA1),
+ pMsgObject->ulMsgLen);
+ }
+
+ //
+ // Write out the registers to program the message object.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, usCmdMaskReg);
+ CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg[0]);
+ CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg[1]);
+ CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg[0]);
+ CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg[1]);
+ CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl);
+
+ //
+ // Transfer the message object to the message object specifiec by ulObjID.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Reads a CAN message from one of the message object buffers.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulObjID is the object number to read (1-32).
+//! \param pMsgObject points to a structure containing message object fields.
+//! \param bClrPendingInt indicates whether an associated interrupt should be
+//! cleared.
+//!
+//! This function is used to read the contents of one of the 32 message objects
+//! in the CAN controller, and return it to the caller. The data returned is
+//! stored in the fields of the caller-supplied structure pointed to by
+//! \e pMsgObject. The data consists of all of the parts of a CAN message,
+//! plus some control and status information.
+//!
+//! Normally this is used to read a message object that has received and stored
+//! a CAN message with a certain identifier. However, this could also be used
+//! to read the contents of a message object in order to load the fields of the
+//! structure in case only part of the structure needs to be changed from a
+//! previous setting.
+//!
+//! When using CANMessageGet, all of the same fields of the structure are
+//! populated in the same way as when the CANMessageSet() function is used,
+//! with the following exceptions:
+//!
+//! \e pMsgObject->ulFlags:
+//!
+//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it
+//! was read
+//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on
+//! this message object, and not read by the host before being overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt)
+{
+ unsigned short usCmdMaskReg;
+ unsigned short usMaskReg[2];
+ unsigned short usArbReg[2];
+ unsigned short usMsgCtrl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulObjID <= 32) && (ulObjID != 0));
+
+ //
+ // This is always a read to the Message object as this call is setting a
+ // message object.
+ //
+ usCmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB |
+ CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK | CAN_IF1CMSK_ARB);
+
+ //
+ // Clear a pending interrupt and new data in a message object.
+ //
+ if(bClrPendingInt)
+ {
+ usCmdMaskReg |= CAN_IF1CMSK_CLRINTPND;
+ }
+
+ //
+ // Set up the request for data from the message object.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CMSK, usCmdMaskReg);
+
+ //
+ // Transfer the message object to the message object specifiec by ulObjID.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Read out the IF Registers.
+ //
+ usMaskReg[0] = CANRegRead(ulBase + CAN_O_IF2MSK1);
+ usMaskReg[1] = CANRegRead(ulBase + CAN_O_IF2MSK2);
+ usArbReg[0] = CANRegRead(ulBase + CAN_O_IF2ARB1);
+ usArbReg[1] = CANRegRead(ulBase + CAN_O_IF2ARB2);
+ usMsgCtrl = CANRegRead(ulBase + CAN_O_IF2MCTL);
+
+ pMsgObject->ulFlags = MSG_OBJ_NO_FLAGS;
+
+ //
+ // Determine if this is a remote frame by checking the TXRQST and DIR bits.
+ //
+ if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
+ (usArbReg[1] & CAN_IF1ARB2_DIR)) ||
+ ((usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
+ (!(usArbReg[1] & CAN_IF1ARB2_DIR))))
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_REMOTE_FRAME;
+ }
+
+ //
+ // Get the identifier out of the register, the format depends on size of
+ // the mask.
+ //
+ if(usArbReg[1] & CAN_IF1ARB2_XTD)
+ {
+ //
+ // Set the 29 bit version of the Identifier for this message object.
+ //
+ pMsgObject->ulMsgID = ((usArbReg[1] & CAN_IF1ARB2_ID_M) << 16) |
+ usArbReg[0];
+
+ pMsgObject->ulFlags |= MSG_OBJ_EXTENDED_ID;
+ }
+ else
+ {
+ //
+ // The Identifier is an 11 bit value.
+ //
+ pMsgObject->ulMsgID = (usArbReg[1] & CAN_IF1ARB2_ID_M) >> 2;
+ }
+
+ //
+ // Indicate that we lost some data.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_MSGLST)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_DATA_LOST;
+ }
+
+ //
+ // Set the flag to indicate if ID masking was used.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_UMASK)
+ {
+ if(usArbReg[1] & CAN_IF1ARB2_XTD)
+ {
+ //
+ // The Identifier Mask is assumed to also be a 29 bit value.
+ //
+ pMsgObject->ulMsgIDMask =
+ ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg[0];
+ //
+ // If this is a fully specified Mask and a remote frame then don't
+ // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
+ // filtered.
+ //
+ if((pMsgObject->ulMsgIDMask != 0x1fffffff) ||
+ ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0))
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER;
+ }
+ }
+ else
+ {
+ //
+ // The Identifier Mask is assumed to also be an 11 bit value.
+ //
+ pMsgObject->ulMsgIDMask = ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) >>
+ 2);
+
+ //
+ // If this is a fully specified Mask and a remote frame then don't
+ // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
+ // filtered.
+ //
+ if((pMsgObject->ulMsgIDMask != 0x7ff) ||
+ ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0))
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER;
+ }
+ }
+
+ //
+ // Indicate if the extended bit was used in filtering.
+ //
+ if(usMaskReg[1] & CAN_IF1MSK2_MXTD)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_EXT_FILTER;
+ }
+
+ //
+ // Indicate if direction filtering was enabled.
+ //
+ if(usMaskReg[1] & CAN_IF1MSK2_MDIR)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_USE_DIR_FILTER;
+ }
+ }
+
+ //
+ // Set the interupt flags.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_TXIE)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_TX_INT_ENABLE;
+ }
+ if(usMsgCtrl & CAN_IF1MCTL_RXIE)
+ {
+ pMsgObject->ulFlags |= MSG_OBJ_RX_INT_ENABLE;
+ }
+
+ //
+ // See if there is new data available.
+ //
+ if(usMsgCtrl & CAN_IF1MCTL_NEWDAT)
+ {
+ //
+ // Get the amount of data needed to be read.
+ //
+ pMsgObject->ulMsgLen = (usMsgCtrl & CAN_IF1MCTL_DLC_M);
+
+ //
+ // Don't read any data for a remote frame, there is nothing valid in
+ // that buffer anyway.
+ //
+ if((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0)
+ {
+ //
+ // Read out the data from the CAN registers.
+ //
+ CANDataRegRead(pMsgObject->pucMsgData,
+ (unsigned long *)(ulBase + CAN_O_IF2DA1),
+ pMsgObject->ulMsgLen);
+ }
+
+ //
+ // Now clear out the new data flag.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CMSK, CAN_IF1CMSK_NEWDAT);
+
+ //
+ // Transfer the message object to the message object specifiec by
+ // ulObjID.
+ //
+ CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Indicate that there is new data in this message.
+ //
+ pMsgObject->ulFlags |= MSG_OBJ_NEW_DATA;
+ }
+ else
+ {
+ //
+ // Along with the MSG_OBJ_NEW_DATA not being set the amount of data
+ // needs to be set to zero if none was available.
+ //
+ pMsgObject->ulMsgLen = 0;
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears a message object so that it is no longer used.
+//!
+//! \param ulBase is the base address of the CAN controller.
+//! \param ulObjID is the message object number to disable (1-32).
+//!
+//! This function frees the specified message object from use. Once a message
+//! object has been ``cleared,'' it will no longer automatically send or
+//! receive messages, or generate interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CANMessageClear(unsigned long ulBase, unsigned long ulObjID)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(CANBaseValid(ulBase));
+ ASSERT((ulObjID >= 1) && (ulObjID <= 32));
+
+ //
+ // Wait for busy bit to clear
+ //
+ while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
+ {
+ }
+
+ //
+ // Clear the message value bit in the arbitration register. This indicates
+ // the message is not valid.
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB);
+ CANRegWrite(ulBase + CAN_O_IF1ARB1, 0);
+ CANRegWrite(ulBase + CAN_O_IF1ARB2, 0);
+
+ //
+ // Initiate programming the message object
+ //
+ CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/can.h b/bsp/lm3s/Libraries/driverlib/can.h new file mode 100644 index 0000000000..51df810346 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/can.h @@ -0,0 +1,458 @@ +//*****************************************************************************
+//
+// can.h - Defines and Macros for the CAN controller.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CAN_H__
+#define __CAN_H__
+
+//*****************************************************************************
+//
+//! \addtogroup can_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Miscellaneous defines for Message ID Types
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! These are the flags used by the tCANMsgObject variable when calling the
+//! CANMessageSet() and CANMessageGet() functions.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! This indicates that transmit interrupts should be enabled, or are
+ //! enabled.
+ //
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,
+
+ //
+ //! This indicates that receive interrupts should be enabled, or are
+ //! enabled.
+ //
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,
+
+ //
+ //! This indicates that a message object will use or is using an extended
+ //! identifier.
+ //
+ MSG_OBJ_EXTENDED_ID = 0x00000004,
+
+ //
+ //! This indicates that a message object will use or is using filtering
+ //! based on the object's message identifier.
+ //
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,
+
+ //
+ //! This indicates that new data was available in the message object.
+ //
+ MSG_OBJ_NEW_DATA = 0x00000080,
+
+ //
+ //! This indicates that data was lost since this message object was last
+ //! read.
+ //
+ MSG_OBJ_DATA_LOST = 0x00000100,
+
+ //
+ //! This indicates that a message object will use or is using filtering
+ //! based on the direction of the transfer. If the direction filtering is
+ //! used, then ID filtering must also be enabled.
+ //
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),
+
+ //
+ //! This indicates that a message object will use or is using message
+ //! identifier filtering based on the extended identifier. If the extended
+ //! identifier filtering is used, then ID filtering must also be enabled.
+ //
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),
+
+ //
+ //! This indicates that a message object is a remote frame.
+ //
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,
+
+ //
+ //! This indicates that a message object has no flags set.
+ //
+ MSG_OBJ_NO_FLAGS = 0x00000000
+}
+tCANObjFlags;
+
+//*****************************************************************************
+//
+//! This define is used with the #tCANObjFlags enumerated values to allow
+//! checking only status flags and not configuration flags.
+//
+//*****************************************************************************
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
+
+//*****************************************************************************
+//
+//! The structure used for encapsulating all the items associated with a CAN
+//! message object in the CAN controller.
+//
+//*****************************************************************************
+typedef struct
+{
+ //
+ //! The CAN message identifier used for 11 or 29 bit identifiers.
+ //
+ unsigned long ulMsgID;
+
+ //
+ //! The message identifier mask used when identifier filtering is enabled.
+ //
+ unsigned long ulMsgIDMask;
+
+ //
+ //! This value holds various status flags and settings specified by
+ //! tCANObjFlags.
+ //
+ unsigned long ulFlags;
+
+ //
+ //! This value is the number of bytes of data in the message object.
+ //
+ unsigned long ulMsgLen;
+
+ //
+ //! This is a pointer to the message object's data.
+ //
+ unsigned char *pucMsgData;
+}
+tCANMsgObject;
+
+//*****************************************************************************
+//
+//! This structure is used for encapsulating the values associated with setting
+//! up the bit timing for a CAN controller. The structure is used when calling
+//! the CANGetBitTiming and CANSetBitTiming functions.
+//
+//*****************************************************************************
+typedef struct
+{
+ //
+ //! This value holds the sum of the Synchronization, Propagation, and Phase
+ //! Buffer 1 segments, measured in time quanta. The valid values for this
+ //! setting range from 2 to 16.
+ //
+ unsigned int uSyncPropPhase1Seg;
+
+ //
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid
+ //! values for this setting range from 1 to 8.
+ //
+ unsigned int uPhase2Seg;
+
+ //
+ //! This value holds the Resynchronization Jump Width in time quanta. The
+ //! valid values for this setting range from 1 to 4.
+ //
+ unsigned int uSJW;
+
+ //
+ //! This value holds the CAN_CLK divider used to determine time quanta.
+ //! The valid values for this setting range from 1 to 1023.
+ //
+ unsigned int uQuantumPrescaler;
+}
+tCANBitClkParms;
+
+//*****************************************************************************
+//
+//! This data type is used to identify the interrupt status register. This is
+//! used when calling the CANIntStatus() function.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! Read the CAN interrupt status information.
+ //
+ CAN_INT_STS_CAUSE,
+
+ //
+ //! Read a message object's interrupt status.
+ //
+ CAN_INT_STS_OBJECT
+}
+tCANIntStsReg;
+
+//*****************************************************************************
+//
+//! This data type is used to identify which of several status registers to
+//! read when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! Read the full CAN controller status.
+ //
+ CAN_STS_CONTROL,
+
+ //
+ //! Read the full 32-bit mask of message objects with a transmit request
+ //! set.
+ //
+ CAN_STS_TXREQUEST,
+
+ //
+ //! Read the full 32-bit mask of message objects with new data available.
+ //
+ CAN_STS_NEWDAT,
+
+ //
+ //! Read the full 32-bit mask of message objects that are enabled.
+ //
+ CAN_STS_MSGVAL
+}
+tCANStsReg;
+
+//*****************************************************************************
+//
+//! These definitions are used to specify interrupt sources to CANIntEnable()
+//! and CANIntDisable().
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! This flag is used to allow a CAN controller to generate error
+ //! interrupts.
+ //
+ CAN_INT_ERROR = 0x00000008,
+
+ //
+ //! This flag is used to allow a CAN controller to generate status
+ //! interrupts.
+ //
+ CAN_INT_STATUS = 0x00000004,
+
+ //
+ //! This flag is used to allow a CAN controller to generate any CAN
+ //! interrupts. If this is not set, then no interrupts will be generated
+ //! by the CAN controller.
+ //
+ CAN_INT_MASTER = 0x00000002
+}
+tCANIntFlags;
+
+//*****************************************************************************
+//
+//! This definition is used to determine the type of message object that will
+//! be set up via a call to the CANMessageSet() API.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! Transmit message object.
+ //
+ MSG_OBJ_TYPE_TX,
+
+ //
+ //! Transmit remote request message object
+ //
+ MSG_OBJ_TYPE_TX_REMOTE,
+
+ //
+ //! Receive message object.
+ //
+ MSG_OBJ_TYPE_RX,
+
+ //
+ //! Receive remote request message object.
+ //
+ MSG_OBJ_TYPE_RX_REMOTE,
+
+ //
+ //! Remote frame receive remote, with auto-transmit message object.
+ //
+ MSG_OBJ_TYPE_RXTX_REMOTE
+}
+tMsgObjType;
+
+//*****************************************************************************
+//
+//! The following enumeration contains all error or status indicators that can
+//! be returned when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+typedef enum
+{
+ //
+ //! CAN controller has entered a Bus Off state.
+ //
+ CAN_STATUS_BUS_OFF = 0x00000080,
+
+ //
+ //! CAN controller error level has reached warning level.
+ //
+ CAN_STATUS_EWARN = 0x00000040,
+
+ //
+ //! CAN controller error level has reached error passive level.
+ //
+ CAN_STATUS_EPASS = 0x00000020,
+
+ //
+ //! A message was received successfully since the last read of this status.
+ //
+ CAN_STATUS_RXOK = 0x00000010,
+
+ //
+ //! A message was transmitted successfully since the last read of this
+ //! status.
+ //
+ CAN_STATUS_TXOK = 0x00000008,
+
+ //
+ //! This is the mask for the last error code field.
+ //
+ CAN_STATUS_LEC_MSK = 0x00000007,
+
+ //
+ //! There was no error.
+ //
+ CAN_STATUS_LEC_NONE = 0x00000000,
+
+ //
+ //! A bit stuffing error has occurred.
+ //
+ CAN_STATUS_LEC_STUFF = 0x00000001,
+
+ //
+ //! A formatting error has occurred.
+ //
+ CAN_STATUS_LEC_FORM = 0x00000002,
+
+ //
+ //! An acknowledge error has occurred.
+ //
+ CAN_STATUS_LEC_ACK = 0x00000003,
+
+ //
+ //! The bus remained a bit level of 1 for longer than is allowed.
+ //
+ CAN_STATUS_LEC_BIT1 = 0x00000004,
+
+ //
+ //! The bus remained a bit level of 0 for longer than is allowed.
+ //
+ CAN_STATUS_LEC_BIT0 = 0x00000005,
+
+ //
+ //! A CRC error has occurred.
+ //
+ CAN_STATUS_LEC_CRC = 0x00000006,
+
+ //
+ //! This is the mask for the CAN Last Error Code (LEC).
+ //
+ CAN_STATUS_LEC_MASK = 0x00000007
+}
+tCANStatusCtrl;
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms);
+extern void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms);
+extern unsigned long CANBitRateSet(unsigned long ulBase,
+ unsigned long ulSourceClock,
+ unsigned long ulBitRate);
+extern void CANDisable(unsigned long ulBase);
+extern void CANEnable(unsigned long ulBase);
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
+ unsigned long *pulTxCount);
+extern void CANInit(unsigned long ulBase);
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern unsigned long CANIntStatus(unsigned long ulBase,
+ tCANIntStsReg eIntStsReg);
+extern void CANIntUnregister(unsigned long ulBase);
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
+extern tBoolean CANRetryGet(unsigned long ulBase);
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
+
+//*****************************************************************************
+//
+// Several CAN APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define CANSetBitTiming(a, b) CANBitTimingSet(a, b)
+#define CANGetBitTiming(a, b) CANBitTimingGet(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __CAN_H__
diff --git a/bsp/lm3s/Libraries/driverlib/comp.c b/bsp/lm3s/Libraries/driverlib/comp.c new file mode 100644 index 0000000000..b7cba55413 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/comp.c @@ -0,0 +1,439 @@ +//*****************************************************************************
+//
+// comp.c - Driver for the analog comparator.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup comp_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_comp.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/comp.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Configures a comparator.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulConfig is the configuration of the comparator.
+//!
+//! This function will configure a comparator. The \e ulConfig parameter is
+//! the result of a logical OR operation between the \b COMP_TRIG_xxx,
+//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
+//!
+//! The \b COMP_TRIG_xxx term can take on the following values:
+//!
+//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
+//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
+//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
+//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
+//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
+//! high.
+//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
+//! or high.
+//!
+//! The \b COMP_INT_xxx term can take on the following values:
+//!
+//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
+//! high.
+//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
+//! low.
+//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
+//! low.
+//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
+//! high.
+//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
+//! low or high.
+//!
+//! The \b COMP_ASRCP_xxx term can take on the following values:
+//!
+//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
+//! voltage.
+//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
+//! the same as \b COMP_ASRCP_PIN for the comparator 0).
+//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
+//! reference voltage.
+//!
+//! The \b COMP_OUTPUT_xxx term can take on the following values:
+//!
+//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
+//! to a device pin.
+//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
+//! a device pin.
+//! - \b COMP_OUTPUT_NONE is deprecated and behaves the same as
+//! \b COMP_OUTPUT_NORMAL.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Configure this comparator.
+ //
+ HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Sets the internal reference voltage.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulRef is the desired reference voltage.
+//!
+//! This function will set the internal reference voltage value. The voltage
+//! is specified as one of the following values:
+//!
+//! - \b COMP_REF_OFF to turn off the reference voltage
+//! - \b COMP_REF_0V to set the reference voltage to 0 V
+//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
+//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
+//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
+//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
+//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
+//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
+//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
+//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
+//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
+//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
+//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
+//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
+//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
+//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
+//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
+//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
+//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
+//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
+//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
+//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
+//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
+//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
+//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
+//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
+//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
+//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
+//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorRefSet(unsigned long ulBase, unsigned long ulRef)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+
+ //
+ // Set the voltage reference voltage as requested.
+ //
+ HWREG(ulBase + COMP_O_ACREFCTL) = ulRef;
+}
+
+//*****************************************************************************
+//
+//! Gets the current comparator output value.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function retrieves the current value of the comparator output.
+//!
+//! \return Returns \b true if the comparator output is high and \b false if
+//! the comparator output is low.
+//
+//*****************************************************************************
+tBoolean
+ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Return the appropriate value based on the comparator's present output
+ // value.
+ //
+ if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT0_OVAL)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! comparator interrupt occurs.
+//!
+//! This sets the handler to be called when the comparator interrupt occurs.
+//! This will enable the interrupt in the interrupt controller; it is the
+//! interrupt-handler's responsibility to clear the interrupt source via
+//! ComparatorIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
+ void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_COMP0 + ulComp, pfnHandler);
+
+ //
+ // Enable the interrupt in the interrupt controller.
+ //
+ IntEnable(INT_COMP0 + ulComp);
+
+ //
+ // Enable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function will clear the handler to be called when a comparator
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Disable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
+
+ //
+ // Disable the interrupt in the interrupt controller.
+ //
+ IntDisable(INT_COMP0 + ulComp);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_COMP0 + ulComp);
+}
+
+//*****************************************************************************
+//
+//! Enables the comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function enables generation of an interrupt from the specified
+//! comparator. Only comparators whose interrupts are enabled can be reflected
+//! to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Enable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
+}
+
+//*****************************************************************************
+//
+//! Disables the comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function disables generation of an interrupt from the specified
+//! comparator. Only comparators whose interrupts are enabled can be reflected
+//! to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Disable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the comparator. Either the raw or
+//! the masked interrupt status can be returned.
+//!
+//! \return \b true if the interrupt is asserted and \b false if it is not
+//! asserted.
+//
+//*****************************************************************************
+tBoolean
+ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(((HWREG(ulBase + COMP_O_ACMIS) >> ulComp) & 1) ? true : false);
+ }
+ else
+ {
+ return(((HWREG(ulBase + COMP_O_ACRIS) >> ulComp) & 1) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears a comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! The comparator interrupt is cleared, so that it no longer asserts. This
+//! must be done in the interrupt handler to keep it from being called again
+//! immediately upon exit. Note that for a level triggered interrupt, the
+//! interrupt cannot be cleared until it stops asserting.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntClear(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Clear the interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACMIS) = 1 << ulComp;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/comp.h b/bsp/lm3s/Libraries/driverlib/comp.h new file mode 100644 index 0000000000..6c6bf8fcc1 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/comp.h @@ -0,0 +1,133 @@ +//*****************************************************************************
+//
+// comp.h - Prototypes for the analog comparator driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __COMP_H__
+#define __COMP_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorConfigure() as the ulConfig
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
+// the values may be selected and combined together with values from the other
+// groups via a logical OR.
+//
+//*****************************************************************************
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high
+#define COMP_INT_LOW 0x00000000 // Interrupt when low
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
+#ifndef DEPRECATED
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
+#endif
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
+//
+//*****************************************************************************
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig);
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
+ void (*pfnHandler)(void));
+extern void ComparatorIntUnregister(unsigned long ulBase,
+ unsigned long ulComp);
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bMasked);
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __COMP_H__
diff --git a/bsp/lm3s/Libraries/driverlib/cpu.c b/bsp/lm3s/Libraries/driverlib/cpu.c new file mode 100644 index 0000000000..fbe243647f --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/cpu.c @@ -0,0 +1,189 @@ +//*****************************************************************************
+//
+// cpu.c - Instruction wrappers for special CPU instructions needed by the
+// drivers.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include "driverlib/cpu.h"
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsid(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs %0, PRIMASK\n"
+ " cpsid i\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ mrs r0, PRIMASK;
+ cpsid i;
+ bx lr
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsie(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs %0, PRIMASK\n"
+ " cpsie i\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ mrs r0, PRIMASK;
+ cpsie i;
+ bx lr
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the WFI instruction.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" wfi\n"
+ " bx lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" wfi\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ wfi;
+ bx lr
+}
+#endif
diff --git a/bsp/lm3s/Libraries/driverlib/cpu.h b/bsp/lm3s/Libraries/driverlib/cpu.h new file mode 100644 index 0000000000..8939ecd45a --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/cpu.h @@ -0,0 +1,60 @@ +//*****************************************************************************
+//
+// cpu.h - Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern void CPUwfi(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
diff --git a/bsp/lm3s/Libraries/driverlib/cr_project.xml b/bsp/lm3s/Libraries/driverlib/cr_project.xml new file mode 100644 index 0000000000..835b3c172f --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/cr_project.xml @@ -0,0 +1,66 @@ +<!--
+Configuration file for Code Red project libdriver
+
+Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+Software License Agreement
+
+Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+exclusively on LMI's microcontroller products.
+
+The software is owned by LMI and/or its suppliers, and is protected under
+applicable copyright laws. All rights are reserved. You may not combine
+this software with "viral" open-source software in order to form a larger
+program. Any use in violation of the foregoing restrictions may subject
+the user to criminal sanctions under applicable laws, as well as to civil
+liability for the breach of the terms and conditions of this license.
+
+THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
+This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+-->
+
+<project chip="LM3S101"
+ target="driver"
+ type="Static library"
+ vendor="LMI">
+ <import src=".">
+ <exclude>{(Makefile|codered|ewarm|gcc|rvmdk|sourcerygxx)}</exclude>
+ <exclude>{.*\.(ewd|ewp|eww|icf|Opt|sct|Uv2|xml|ld)}</exclude>
+ </import>
+ <requires>
+ <value>inc</value>
+ </requires>
+ <setting id="assembler.def">
+ <value>codered</value>
+ </setting>
+ <setting id="compiler.def"
+ buildType="Debug"
+ mode="replace">
+ <value>DEBUG</value>
+ </setting>
+ <setting id="compiler.def"
+ buildType="Release"
+ mode="replace">
+ <value>NDEBUG</value>
+ </setting>
+ <setting id="compiler.def">
+ <value>__CODE_RED</value>
+ <value>codered</value>
+ <value>PART_LM3S101</value>
+ </setting>
+ <setting id="compiler.opt"
+ buildType="Debug">
+ <value>-O2</value>
+ </setting>
+ <setting id="compiler.opt"
+ buildType="Release">
+ <value>-O2</value>
+ </setting>
+ <setting id="compiler.inc">
+ <value>${workspace_loc:/}</value>
+ </setting>
+</project>
diff --git a/bsp/lm3s/Libraries/driverlib/debug.h b/bsp/lm3s/Libraries/driverlib/debug.h new file mode 100644 index 0000000000..ed8c8aa05e --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/debug.h @@ -0,0 +1,56 @@ +//*****************************************************************************
+//
+// debug.h - Macros for assisting debug of the driver library.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API. This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long ulLine);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking. Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) { \
+ if(!(expr)) \
+ { \
+ __error__(__FILE__, __LINE__); \
+ } \
+ }
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DEBUG_H__
diff --git a/bsp/lm3s/Libraries/driverlib/driverlib.Opt b/bsp/lm3s/Libraries/driverlib/driverlib.Opt new file mode 100644 index 0000000000..25476e97fc --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/driverlib.Opt @@ -0,0 +1,59 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+ cExt (*.c)
+ aExt (*.s*; *.src; *.a*)
+ oExt (*.obj)
+ lExt (*.lib)
+ tExt (*.txt; *.h; *.inc)
+ pExt (*.plm)
+ CppX (*.cpp)
+ DaveTm { 0,0,0,0,0,0,0,0 }
+
+Target (driverlib), 0x0004 // Tools: 'ARM-ADS'
+GRPOPT 1,(Source),1,0,0
+GRPOPT 2,(Documentation),0,0,0
+
+OPTFFF 1,1,1,0,0,0,0,0,<.\adc.c><adc.c>
+OPTFFF 1,2,1,0,0,0,0,0,<.\can.c><can.c>
+OPTFFF 1,3,1,0,0,0,0,0,<.\comp.c><comp.c>
+OPTFFF 1,4,1,0,0,0,0,0,<.\cpu.c><cpu.c>
+OPTFFF 1,5,1,0,0,0,0,0,<.\epi.c><epi.c>
+OPTFFF 1,6,1,0,0,0,0,0,<.\ethernet.c><ethernet.c>
+OPTFFF 1,7,1,0,0,0,0,0,<.\flash.c><flash.c>
+OPTFFF 1,8,1,0,0,0,0,0,<.\gpio.c><gpio.c>
+OPTFFF 1,9,1,0,0,0,0,0,<.\hibernate.c><hibernate.c>
+OPTFFF 1,10,1,0,0,0,0,0,<.\i2c.c><i2c.c>
+OPTFFF 1,11,1,0,0,0,0,0,<.\i2s.c><i2s.c>
+OPTFFF 1,12,1,0,0,0,0,0,<.\interrupt.c><interrupt.c>
+OPTFFF 1,13,1,0,0,0,0,0,<.\mpu.c><mpu.c>
+OPTFFF 1,14,1,0,0,0,0,0,<.\pwm.c><pwm.c>
+OPTFFF 1,15,1,0,0,0,0,0,<.\qei.c><qei.c>
+OPTFFF 1,16,1,0,0,0,0,0,<.\ssi.c><ssi.c>
+OPTFFF 1,17,1,0,0,0,0,0,<.\sysctl.c><sysctl.c>
+OPTFFF 1,18,1,0,0,0,0,0,<.\systick.c><systick.c>
+OPTFFF 1,19,1,0,0,0,0,0,<.\timer.c><timer.c>
+OPTFFF 1,20,1,738197506,0,707,707,0,<.\uart.c><uart.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,182,2,0,0,196,0,0,0 }
+OPTFFF 1,21,1,0,0,0,0,0,<.\udma.c><udma.c>
+OPTFFF 1,22,1,0,0,0,0,0,<.\usb.c><usb.c>
+OPTFFF 1,23,1,0,0,0,0,0,<.\watchdog.c><watchdog.c>
+OPTFFF 2,24,5,0,0,0,0,0,<.\readme.txt><readme.txt>
+
+
+TARGOPT 1, (driverlib)
+ ADSCLK=6000000
+ OPTTT 0,1,1,0
+ OPTHX 1,65535,0,0,0
+ OPTLX 79,66,8,<.\rvmdk\>
+ OPTOX 16
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+ OPTXL 1,1,1,1,1,1,1,0,0
+ OPTFL 1,0,1
+ OPTAX 0
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)
+ OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
+ OPTDF 0x0
+ OPTLE <>
+ OPTLC <>
+EndOpt
+
diff --git a/bsp/lm3s/Libraries/driverlib/driverlib.Uv2 b/bsp/lm3s/Libraries/driverlib/driverlib.Uv2 new file mode 100644 index 0000000000..c81ec86ede --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/driverlib.Uv2 @@ -0,0 +1,124 @@ +### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (driverlib), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Source)
+Group (Documentation)
+
+File 1,1,<.\adc.c><adc.c>
+File 1,1,<.\can.c><can.c>
+File 1,1,<.\comp.c><comp.c>
+File 1,1,<.\cpu.c><cpu.c>
+File 1,1,<.\epi.c><epi.c>
+File 1,1,<.\ethernet.c><ethernet.c>
+File 1,1,<.\flash.c><flash.c>
+File 1,1,<.\gpio.c><gpio.c>
+File 1,1,<.\hibernate.c><hibernate.c>
+File 1,1,<.\i2c.c><i2c.c>
+File 1,1,<.\i2s.c><i2s.c>
+File 1,1,<.\interrupt.c><interrupt.c>
+File 1,1,<.\mpu.c><mpu.c>
+File 1,1,<.\pwm.c><pwm.c>
+File 1,1,<.\qei.c><qei.c>
+File 1,1,<.\ssi.c><ssi.c>
+File 1,1,<.\sysctl.c><sysctl.c>
+File 1,1,<.\systick.c><systick.c>
+File 1,1,<.\timer.c><timer.c>
+File 1,1,<.\uart.c><uart.c>
+File 1,1,<.\udma.c><udma.c>
+File 1,1,<.\usb.c><usb.c>
+File 1,1,<.\watchdog.c><watchdog.c>
+File 2,5,<.\readme.txt><readme.txt>
+
+
+Options 1,0,0 // Target 'driverlib'
+ Device (LM3S6965)
+ Vendor (Luminary Micro)
+ Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3"))
+ FlashUt ()
+ StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))
+ FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000))
+ DevID (4337)
+ Rgf (LM3Sxxxx.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (�Luminary\)
+ OrgReg (�Luminary\)
+ TgStat=16
+ OutDir (.\rvmdk\)
+ OutName (driverlib)
+ GenApp=0
+ GenLib=1
+ GenHex=0
+ Debug=1
+ Browse=1
+ LstDir (.\rvmdk\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP ("Cortex-M3")
+ RVDEV ()
+ ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }
+ OCMADSIROM { 1,0,0,0,0,0,0,4,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 12,34,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN (rvmdk)
+ ADSCUDEF ()
+ ADSCINCD (..;)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00000000)
+ ADSLDDA (0x20000000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC ()
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)
+ OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
+ FLASH1 { 1,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (BIN\UL2CM3.DLL)
+ FLASH3 ("" ())
+ FLASH4 ()
+EndOpt
+
diff --git a/bsp/lm3s/Libraries/driverlib/driverlib.ewp b/bsp/lm3s/Libraries/driverlib/driverlib.ewp new file mode 100644 index 0000000000..fbce106a60 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/driverlib.ewp @@ -0,0 +1,839 @@ +<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>1</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>14</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>ewarm\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>ewarm\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>ewarm\List</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>7</version>
+ <state>31</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Full formatting.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Full formatting.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>RTConfigPath</name>
+ <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>5.11.0.50579</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>5.11.0.50579</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>LM3S101 Luminary LM3S101</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>19</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCDefines</name>
+ <state>ewarm</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state>Pa050</state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLangSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>$PROJ_DIR$\..</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCStdIncludePath</name>
+ <state>$TOOLKIT_DIR$\INC\</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>3</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>7</version>
+ <wantNonLocal>1</wantNonLocal>
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diff --git a/bsp/lm3s/Libraries/driverlib/driverlib.sgxx b/bsp/lm3s/Libraries/driverlib/driverlib.sgxx Binary files differnew file mode 100644 index 0000000000..2f10fd87cd --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/driverlib.sgxx diff --git a/bsp/lm3s/Libraries/driverlib/epi.c b/bsp/lm3s/Libraries/driverlib/epi.c new file mode 100644 index 0000000000..61a2c7718c --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/epi.c @@ -0,0 +1,1039 @@ +//*****************************************************************************
+//
+// epi.c - Driver for the EPI module.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_epi.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/epi.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! \addtogroup epi_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Sets the usage mode of the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulMode is the usage mode of the EPI module.
+//!
+//! This functions sets the operating mode of the EPI module. The parameter
+//! \e ulMode must be one of the following:
+//!
+//! - \b EPI_MODE_NONE - non-moded operation
+//! - \b EPI_MODE_SDRAM - use with SDRAM device
+//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface
+//! - \b EPI_MODE_DISABLE - disable the EPI module
+//!
+//! Selection of any of the above modes will enable the EPI module, except
+//! for \b EPI_MODE_DISABLE which should be used to disable the module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIModeSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT((ulMode == EPI_MODE_NONE) ||
+ (ulMode == EPI_MODE_SDRAM) ||
+ (ulMode == EPI_MODE_HB8) ||
+ (ulMode == EPI_MODE_DISABLE));
+
+ //
+ // Write the mode word to the register.
+ //
+ HWREG(ulBase + EPI_O_CFG) = ulMode;
+}
+
+//*****************************************************************************
+//
+//! Sets the clock divider for the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulDivider is the value of the clock divider to be applied to
+//! the external interface (0-65535).
+//!
+//! This functions sets the clock divider that will be used to determine the
+//! clock rate of the external interface. The value is the number of high
+//! and low ticks of the system clock per external bus clock. A value of 0
+//! means that the system clock is used without any reduction. The system
+//! clock will be divided by the value of \e ulDivider multiplied by 2. A
+//! value of 1 gives a divider of 2, and value of 2 gives a divider of 4, a
+//! value of 3 gives a divider of 6, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIDividerSet(unsigned long ulBase, unsigned long ulDivider)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Write the divider value to the register.
+ //
+ HWREG(ulBase + EPI_O_BAUD) = ulDivider;
+}
+
+//*****************************************************************************
+//
+//! Configures the SDRAM mode of operation.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the SDRAM interface configuration.
+//! \param ulRefresh is the refresh count in core clocks (0-2047).
+//!
+//! This function is used to configure the SDRAM interface, when the SDRAM
+//! mode is chosen with the function EPIModeSet(). The parameter \e ulConfig
+//! is the logical OR of several sets of choices:
+//!
+//! The processor core frequency must be specified with one of the following:
+//!
+//! - \b EPI_SDRAM_CORE_FREQ_0_15 - core clock is 0 MHz < clk <= 15 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_15_30 - core clock is 15 MHz < clk <= 30 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_30_50 - core clock is 30 MHz < clk <= 50 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_50_100 - core clock is 50 MHz < clk <= 100 MHz
+//!
+//! The low power mode is specified with one of the following:
+//!
+//! - \b EPI_SDRAM_LOW_POWER - enter low power, self-refresh state
+//! - \b EPI_SDRAM_FULL_POWER - normal operating state
+//!
+//! The SDRAM device size is specified with one of the following:
+//!
+//! - \b EPI_SDRAM_SIZE_64MBIT - 64 Mbit device (8 MB)
+//! - \b EPI_SDRAM_SIZE_128MBIT - 128 Mbit device (16 MB)
+//! - \b EPI_SDRAM_SIZE_256MBIT - 256 Mbit device (32 MB)
+//! - \b EPI_SDRAM_SIZE_512MBIT - 512 Mbit device (64 MB)
+//!
+//! The parameter \e ulRefresh sets the refresh counter in units of core
+//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulRefresh)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulRefresh < 2048);
+
+ //
+ // Fill in the refresh count field of the configuration word.
+ //
+ ulConfig &= ~EPI_SDRAMCFG_RFSH_M;
+ ulConfig |= ulRefresh << EPI_SDRAMCFG_RFSH_S;
+
+ //
+ // Write the SDRAM configuration register.
+ //
+ HWREG(ulBase + EPI_O_SDRAMCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for Host-bus 8 operation.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the interface configuration.
+//! \param ulMaxWait is the maximum number of external clocks to wait
+//! if a FIFO ready signal is holding off the transaction.
+//!
+//! This function is used to configure the interface when used in Host-bus 8
+//! operation as chosen with the function EPIModeSet(). The parameter
+//! \e ulConfig is the logical OR of any of the following:
+//!
+//! - one of \b EPI_HB8_MODE_ADMUX, \b EPI_HB8_MODE_ADDEMUX,
+//! \b EPI_HB8_MODE_SRAM, or \b EPI_HB8_MODE_FIFO to select the HB8 mode
+//! - \b EPI_HB8_USE_TXEMPTY - enable TXEMPTY signal with FIFO
+//! - \b EPI_HB8_USE_RXFULL - enable RXFULL signal with FIFO
+//! - \b EPI_HB8_WRHIGH - use active high write strobe, otherwise it is
+//! active low
+//! - \b EPI_HB8_RDHIGH - use active high read strobe, otherwise it is
+//! active low
+//! - one of \b EPI_HB8_WRWAIT_0, \b EPI_HB8_WRWAIT_1, \b EPI_HB8_WRWAIT_2,
+//! or \b EPI_HB8_WRWAIT_3 to select the number of write wait states (default
+//! is 0 wait states)
+//! - one of \b EPI_HB8_RDWAIT_0, \b EPI_HB8_RDWAIT_1, \b EPI_HB8_RDWAIT_2,
+//! or \b EPI_HB8_RDWAIT_3 to select the number of read wait states (default
+//! is 0 wait states)
+//!
+//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
+//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
+//! parameter determines the maximum number of clocks to wait when the
+//! transaction is being held off by by the FIFO using one of these ready
+//! signals. A value of 0 means to wait forever.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxWait)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulMaxWait < 256);
+
+ //
+ // Fill in the max wait field of the configuration word.
+ //
+ ulConfig &= ~EPI_HB8CFG_MAXWAIT_M;
+ ulConfig |= ulMaxWait << EPI_HB8CFG_MAXWAIT_S;
+
+ //
+ // Write the non-moded configuration register.
+ //
+ HWREG(ulBase + EPI_O_HB8CFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for non-moded operation.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the interface configuration.
+//! \param ulFrameCount is the frame size in clocks, if the frame signal
+//! is used (0-15).
+//! \param ulMaxWait is the maximum number of external clocks to wait
+//! when the external clock enable is holding off the transaction (0-255).
+//!
+//! This function is used to configure the interface when used in non-moded
+//! operation as chosen with the function EPIModeSet(). The parameter
+//! \e ulConfig is the logical OR of any of the following:
+//!
+//! - \b EPI_NONMODE_CLKPIN - interface clock is output on a pin
+//! - \b EPI_NONMODE_CLKSTOP - clock is stopped when there is no transaction,
+//! otherwise it is free-running
+//! - \b EPI_NONMODE_CLKENA - enable the clock enable input from the device
+//! - \b EPI_NONMODE_FRAMEPIN - framing signal is emitted on a pin
+//! - \b EPI_NONMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it
+//! is a pulse
+//! - \b EPI_NONMODE_READWRITE - read and write strobes are emitted on pins
+//! - \b EPI_NONMODE_WRITE2CYCLE - a two cycle write is used, otherwise a
+//! single-cycle write is used
+//! - \b EPI_NONMODE_READ2CYCLE - a two cycle read is used, otherwise a
+//! single-cycle read is used
+//! - \b EPI_NONMODE_ASIZE_NONE, \b EPI_NONMODE_ASIZE_4,
+//! \b EPI_NONMODE_ASIZE_12, or \b EPI_NONMODE_ASIZE_20 to choose no address
+//! bus, or and address bus size of 4, 12, or 20 bits
+//! - \b EPI_NONMODE_DSIZE_8, \b EPI_NONMODE_DSIZE_16,
+//! \b EPI_NONMODE_DSIZE_24, or \b EPI_NONMODE_DSIZE_32 to select a data bus
+//! size of 8, 16, 24, or 32 bits
+//!
+//! The parameter \e ulFrameCount is the number of clocks used to form the
+//! framing signal, if the framing signal is used. The behavior depends on
+//! whether the frame signal is a pulse or a 50/50 duty cycle. This value
+//! is not used if the framing signal is not enabled with the option
+//! \b EPI_NONMMODE_FRAMEPIN.
+//!
+//! The parameter \e ulMaxWait is used if the external clock enable is turned
+//! on with the \b EPI_NONMODE_CLKENA option is used. In the case that
+//! external clock enable is used, this parameter determines the maximum
+//! number of clocks to wait when the external clock enable signal is holding
+//! off a transaction. A value of 0 means to wait forever. If a non-zero
+//! value is used and exceeded, an interrupt will occur and the transaction
+//! aborted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulFrameCount, unsigned long ulMaxWait)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulFrameCount < 16);
+ ASSERT(ulMaxWait < 256);
+
+ //
+ // Fill in the frame count field of the configuration word.
+ //
+ ulConfig &= ~EPI_GPCFG_FRMCNT_M;
+ ulConfig |= ulFrameCount << EPI_GPCFG_FRMCNT_S;
+
+ //
+ // Fill in the max wait field of the configuration word.
+ //
+ ulConfig &= ~EPI_GPCFG_MAXWAIT_M;
+ ulConfig |= ulMaxWait << EPI_GPCFG_MAXWAIT_S;
+
+ //
+ // Write the non-moded configuration register.
+ //
+ HWREG(ulBase + EPI_O_GPCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the address map for the external interface.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulMap is the address mapping configuration.
+//!
+//! This function is used to configure the address mapping for the external
+//! interface. This determines the base address of the external memory or
+//! device within the processor peripheral and/or memory space.
+//!
+//! The parameter \e ulMap is the logical OR of the following:
+//!
+//! - \b EPI_ADDR_PER_SIZE_256B, \b EPI_ADDR_PER_SIZE_64KB,
+//! \b EPI_ADDR_PER_SIZE_16MB, or \b EPI_ADDR_PER_SIZE_512MB to choose a
+//! peripheral address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes
+//! - \b EPI_ADDR_PER_BASE_NONE, \b EPI_ADDR_PER_BASE_A, or
+//! \b EPI_ADDR_PER_BASE_C to choose the base address of the peripheral
+//! space as none, 0xA0000000, or 0xC0000000
+//! - \b EPI_ADDR_RAM_SIZE_256B, \b EPI_ADDR_RAM_SIZE_64KB,
+//! \b EPI_ADDR_RAM_SIZE_16MB, or \b EPI_ADDR_RAM_SIZE_512MB to choose a
+//! RAM address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes
+//! - \b EPI_ADDR_RAM_BASE_NONE, \b EPI_ADDR_RAM_BASE_6, or
+//! \b EPI_ADDR_RAM_BASE_8 to choose the base address of the RAM space
+//! as none, 0x60000000, or 0x80000000
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulMap < 0x100);
+
+ //
+ // Set the value of the address mapping register.
+ //
+ HWREG(ulBase + EPI_O_ADDRMAP) = ulMap;
+}
+
+//*****************************************************************************
+//
+//! Configures a non-blocking read transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//! \param ulDataSize is the size of the data items to read.
+//! \param ulAddress is the starting address to read.
+//!
+//! This function is used to configure a non-blocking read channel for a
+//! transaction. Two channels are available which can be used in a ping-pong
+//! method for continuous reading. It is not necessary to use both channels
+//! to perform a non-blocking read.
+//!
+//! The parameter \e ulDataSize is one of \b EPI_NBCONFIG_SIZE_8,
+//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit,
+//! or 32-bit sized data transfers.
+//!
+//! The parameter \e ulAddress is the starting address for the read, relative
+//! to the external device. The start of the device is address 0.
+//!
+//! Once configured, the non-blocking read is started by calling
+//! EPINonBlockingReadStart(). If the addresses to be read from the device
+//! are in a sequence, it is not necessary to call this function multiple
+//! times. Until it is changed, the EPI module will remember the last address
+//! that was used for a non-blocking read (per channel).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulDataSize, unsigned long ulAddress)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+ ASSERT(ulDataSize < 4);
+ ASSERT(ulAddress < 0x20000000);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RSIZE1 - EPI_O_RSIZE0);
+
+ //
+ // Write the data size register for the channel.
+ //
+ HWREG(ulBase + EPI_O_RSIZE0 + ulOffset) = ulDataSize;
+
+ //
+ // Write the starting address register for the channel.
+ //
+ HWREG(ulBase + EPI_O_RADDR0 + ulOffset) = ulAddress;
+}
+
+//*****************************************************************************
+//
+//! Starts a non-blocking read transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//! \param ulCount is the number of items to read (1-4095).
+//!
+//! This function starts a non-blocking read that was previously configured
+//! with the function EPINonBlockingReadConfigure(). Once this function is
+//! called, the EPI module will begin reading data from the external device
+//! into the read FIFO. The EPI will stop reading when the FIFO fills up
+//! and resume reading when the application drains the FIFO, until the
+//! total specified count of data items has been read.
+//!
+//! Once a read transaction is completed and the FIFO drained, another
+//! transaction can be started from the next address by calling this
+//! function again.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulCount)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+ ASSERT(ulCount < 4096);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+ //
+ // Write to the read count register.
+ //
+ HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = ulCount;
+}
+
+//*****************************************************************************
+//
+//! Stops a non-blocking read transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//!
+//! This function cancels a non-blocking read transaction that is already
+//! in progress.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+ //
+ // Write a 0 to the read count register, which will cancel the transaction.
+ //
+ HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0;
+}
+
+//*****************************************************************************
+//
+//! Get the count remaining for a non-blocking transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//!
+//! This function gets the remaining count of items for a non-blocking read
+//! transaction.
+//!
+//! \return The number of items remaining in the non-blocking read transaction.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadCount(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+ //
+ // Read the count remaining and return the value to the caller.
+ //
+ return(HWREG(ulBase + EPI_O_RPSTD0 + ulOffset));
+}
+
+//*****************************************************************************
+//
+//! Get the count of items available in the read FIFO.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function gets the number of items that are available to read in
+//! the read FIFO. The read FIFO is filled by a non-blocking read transaction
+//! which is configured by the functions EPINonBlockingReadConfigure() and
+//! EPINonBlockingReadStart().
+//!
+//! \return The number of items available to read in the read FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Read the FIFO count and return it to the caller.
+ //
+ return(HWREG(ulBase + EPI_O_RFIFOCNT));
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 32-bit data items.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulCount is the maximum count of items to read.
+//! \param pulBuf is the caller supplied buffer where the read data should
+//! be stored.
+//!
+//! This function reads 32-bit data items from the read FIFO and stores
+//! the values in a caller supplied buffer. The function will read and store
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ulCount. The actual
+//! count of items will be returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount,
+ unsigned long *pulBuf)
+{
+ unsigned long ulCountRead = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulCount < 4096);
+ ASSERT(pulBuf);
+
+ //
+ // Read from the FIFO while there are any items to read, and
+ // the callers specified count is not exceeded.
+ //
+ while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
+ {
+ //
+ // Read from the FIFO and store in the caller supplied buffer.
+ //
+ *pulBuf = HWREG(ulBase + EPI_O_READFIFO);
+
+ //
+ // Update the caller's buffer pointer and the count of items read.
+ //
+ pulBuf++;
+ ulCountRead++;
+ }
+
+ //
+ // Return the count of items read to the caller.
+ //
+ return(ulCountRead);
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 16-bit data items.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulCount is the maximum count of items to read.
+//! \param pusBuf is the caller supplied buffer where the read data should
+//! be stored.
+//!
+//! This function reads 16-bit data items from the read FIFO and stores
+//! the values in a caller supplied buffer. The function will read and store
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ulCount. The actual
+//! count of items will be returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount,
+ unsigned short *pusBuf)
+{
+ unsigned long ulCountRead = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulCount < 4096);
+ ASSERT(pusBuf);
+
+ //
+ // Read from the FIFO while there are any items to read, and
+ // the callers specified count is not exceeded.
+ //
+ while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
+ {
+ //
+ // Read from the FIFO and store in the caller supplied buffer.
+ //
+ *pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO);
+
+ //
+ // Update the caller's buffer pointer and the count of items read.
+ //
+ pusBuf++;
+ ulCountRead++;
+ }
+
+ //
+ // Return the count of items read to the caller.
+ //
+ return(ulCountRead);
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 8-bit data items.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulCount is the maximum count of items to read.
+//! \param pucBuf is the caller supplied buffer where the read data should
+//! be stored.
+//!
+//! This function reads 8-bit data items from the read FIFO and stores
+//! the values in a caller supplied buffer. The function will read and store
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ulCount. The actual
+//! count of items will be returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount,
+ unsigned char *pucBuf)
+{
+ unsigned long ulCountRead = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulCount < 4096);
+ ASSERT(pucBuf);
+
+ //
+ // Read from the FIFO while there are any items to read, and
+ // the callers specified count is not exceeded.
+ //
+ while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
+ {
+ //
+ // Read from the FIFO and store in the caller supplied buffer.
+ //
+ *pucBuf = (unsigned char)HWREG(ulBase + EPI_O_READFIFO);
+
+ //
+ // Update the caller's buffer pointer and the count of items read.
+ //
+ pucBuf++;
+ ulCountRead++;
+ }
+
+ //
+ // Return the count of items read to the caller.
+ //
+ return(ulCountRead);
+}
+
+//*****************************************************************************
+//
+//! Configures the read FIFO.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the FIFO configuration.
+//!
+//! This function configures the FIFO trigger levels and error
+//! generation. The parameter \e ulConfig is the logical OR of the
+//! following:
+//!
+//! - \b EPI_FIFO_CONFIG_WTFULLERR - enables an error interrupt when a write is
+//! attempted and the write FIFO is full
+//! - \b EPI_FIFO_CONFIG_RSTALLERR - enables an error interrupt when a read is
+//! stalled due to an interleaved write or other reason
+//! - \b EPI_FIFO_CONFIG_TX_EMPTY, \b EPI_FIFO_CONFIG_TX_1_4,
+//! \b EPI_FIFO_CONFIG_TX_1_2, or \b EPI_FIFO_CONFIG_TX_3_4 to set the
+//! TX FIFO trigger level to empty, 1/4, 1/2, or 3/4 level
+//! - \b EPI_FIFO_CONFIG_RX_1_8, \b EPI_FIFO_CONFIG_RX_1_4,
+//! \b EPI_FIFO_CONFIG_RX_1_2, \b EPI_FIFO_CONFIG_RX_3_4,
+//! \b EPI_FIFO_CONFIG_RX_7_8, or \b EPI_FIFO_CONFIG_RX_FULL to set the
+//! RX FIFO trigger level to 1/8, 1/4, 1/2, 3/4, 7/8 or full level
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulConfig == (ulConfig & 0x00030077));
+
+ //
+ // Load the configuration into the FIFO config reg.
+ //
+ HWREG(ulBase + EPI_O_FIFOLVL) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Reads the number of empty slots in the write transaction FIFO.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function returns the number of slots available in the transaction
+//! FIFO. It can be used in a polling method to avoid attempting a write
+//! that would stall.
+//!
+//! \return The number of empty slots in the transaction FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingWriteCount(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Read the FIFO count and return it to the caller.
+ //
+ return(HWREG(ulBase + EPI_O_WFIFOCNT));
+}
+
+//*****************************************************************************
+//
+//! Enables EPI interrupt sources.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the specified EPI sources to generate interrupts.
+//! The \e ulIntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b EPI_INT_TXREQ - transmit FIFO is below the trigger level
+//! - \b EPI_INT_RXREQ - read FIFO is above the trigger level
+//! - \b EPI_INT_ERR - an error condition occurred
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulIntFlags < 16);
+
+ //
+ // Write the interrupt flags mask to the mask register.
+ //
+ HWREG(ulBase + EPI_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables EPI interrupt sources.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the specified EPI sources for interrupt
+//! generation. The \e ulIntFlags parameter can be the logical OR
+//! of any of the following values: \b EPI_INT_RXREQ, \b EPI_INT_TXREQ, or
+//! \b I2S_INT_ERR.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulIntFlags < 16);
+
+ //
+ // Write the interrupt flags mask to the mask register.
+ //
+ HWREG(ulBase + EPI_O_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the EPI interrupt status.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param bMasked is set \b true to get the masked interrupt status, or
+//! \b false to get the raw interrupt status.
+//!
+//! This function returns the EPI interrupt status. It can return either
+//! the raw or masked interrupt status.
+//!
+//! \return Returns the masked or raw EPI interrupt status, as a bit field
+//! of any of the following values: \b EPI_INT_TXREQ, \b EPI_INT_RXREQ,
+//! or \b EPI_INT_ERR
+//
+//*****************************************************************************
+unsigned long
+EPIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + EPI_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + EPI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the EPI error interrupt status.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function returns the error status of the EPI. If the return value of
+//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this
+//! function can be used to determine the cause of the error.
+//!
+//! This function returns a bit mask of error flags, which can be the logical
+//! OR of any of the following:
+//!
+//! - \b EPI_INT_ERR_WTFULL - occurs when a write stalled when the transaction
+//! FIFO was full
+//! - \b EPI_INT_ERR_RSTALL - occurs when a read stalled
+//! - \b EPI_INT_ERR_TIMEOUT - occurs when the external clock enable held
+//! off a transaction longer than the configured maximum wait time
+//!
+//! \return Returns the interrupt error flags as the logical OR of any of
+//! the following: \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or
+//! \b EPI_INT_ERR_TIMEOUT.
+//
+//*****************************************************************************
+unsigned long
+EPIIntErrorStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Read the error status and return to caller.
+ //
+ return(HWREG(ulBase + EPI_O_EISC));
+}
+
+//*****************************************************************************
+//
+//! Clears pending EPI error sources.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulErrFlags is a bit mask of the error sources to be cleared.
+//!
+//! This function clears the specified pending EPI errors. The \e ulErrFlags
+//! parameter can be the logical OR of any of the following values:
+//! \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or \b EPI_INT_ERR_TIMEOUT.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulErrFlags < 16);
+
+ //
+ // Write the error flags to the register to clear the pending errors.
+ //
+ HWREG(ulBase + EPI_O_EISC) = ulErrFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the EPI module
+//! generates an interrupt. Specific EPI interrupts must still be enabled
+//! with the EPIIntEnable() function.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(pfnHandler);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_EPI0, pfnHandler);
+
+ //
+ // Enable the EPI interface interrupt.
+ //
+ IntEnable(INT_EPI0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function will disable and clear the handler to be called when the
+//! EPI interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Disable the EPI interface interrupt.
+ //
+ IntDisable(INT_EPI0);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_EPI0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/epi.h b/bsp/lm3s/Libraries/driverlib/epi.h new file mode 100644 index 0000000000..4cd478e39f --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/epi.h @@ -0,0 +1,229 @@ +//*****************************************************************************
+//
+// epi.h - Prototypes and macros for the EPI module.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __EPI_H__
+#define __EPI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIModeSet()
+//
+//*****************************************************************************
+#define EPI_MODE_NONE 0x00000010
+#define EPI_MODE_SDRAM 0x00000011
+#define EPI_MODE_HB8 0x00000012
+#define EPI_MODE_DISABLE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigSDRAMSet()
+//
+//*****************************************************************************
+#define EPI_SDRAM_CORE_FREQ_0_15 0x00000000
+#define EPI_SDRAM_CORE_FREQ_15_30 0x40000000
+#define EPI_SDRAM_CORE_FREQ_30_50 0x80000000
+#define EPI_SDRAM_CORE_FREQ_50_100 0xC0000000
+#define EPI_SDRAM_LOW_POWER 0x00000200
+#define EPI_SDRAM_FULL_POWER 0x00000000
+#define EPI_SDRAM_SIZE_64MBIT 0x00000000
+#define EPI_SDRAM_SIZE_128MBIT 0x00000001
+#define EPI_SDRAM_SIZE_256MBIT 0x00000002
+#define EPI_SDRAM_SIZE_512MBIT 0x00000003
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigNoModeSet()
+//
+//*****************************************************************************
+#define EPI_NONMODE_CLKPIN 0x80000000
+#define EPI_NONMODE_CLKSTOP 0x40000000
+#define EPI_NONMODE_CLKENA 0x10000000
+#define EPI_NONMODE_FRAMEPIN 0x08000000
+#define EPI_NONMODE_FRAME50 0x04000000
+#define EPI_NONMODE_READWRITE 0x00200000
+#define EPI_NONMODE_WRITE2CYCLE 0x00080000
+#define EPI_NONMODE_READ2CYCLE 0x00040000
+#define EPI_NONMODE_ASIZE_NONE 0x00000000
+#define EPI_NONMODE_ASIZE_4 0x00000010
+#define EPI_NONMODE_ASIZE_12 0x00000020
+#define EPI_NONMODE_ASIZE_20 0x00000030
+#define EPI_NONMODE_DSIZE_8 0x00000000
+#define EPI_NONMODE_DSIZE_16 0x00000001
+#define EPI_NONMODE_DSIZE_24 0x00000002
+#define EPI_NONMODE_DSIZE_32 0x00000003
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigHB8ModeSet()
+//
+//*****************************************************************************
+#define EPI_HB8_USE_TXEMPTY 0x00800000
+#define EPI_HB8_USE_RXFULL 0x00400000
+#define EPI_HB8_WRHIGH 0x00200000
+#define EPI_HB8_RDHIGH 0x00100000
+#define EPI_HB8_WRWAIT_0 0x00000000
+#define EPI_HB8_WRWAIT_1 0x00000040
+#define EPI_HB8_WRWAIT_2 0x00000080
+#define EPI_HB8_WRWAIT_3 0x000000C0
+#define EPI_HB8_RDWAIT_0 0x00000000
+#define EPI_HB8_RDWAIT_1 0x00000010
+#define EPI_HB8_RDWAIT_2 0x00000020
+#define EPI_HB8_RDWAIT_3 0x00000030
+#define EPI_HB8_MODE_ADMUX 0x00000000
+#define EPI_HB8_MODE_ADDEMUX 0x00000001
+#define EPI_HB8_MODE_SRAM 0x00000002
+#define EPI_HB8_MODE_FIFO 0x00000003
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigSDRAMSet()
+//
+//*****************************************************************************
+#define EPI_ADDR_PER_SIZE_256B 0x00000000
+#define EPI_ADDR_PER_SIZE_64KB 0x00000040
+#define EPI_ADDR_PER_SIZE_16MB 0x00000080
+#define EPI_ADDR_PER_SIZE_512MB 0x000000C0
+#define EPI_ADDR_PER_BASE_NONE 0x00000000
+#define EPI_ADDR_PER_BASE_A 0x00000010
+#define EPI_ADDR_PER_BASE_C 0x00000020
+#define EPI_ADDR_RAM_SIZE_256B 0x00000000
+#define EPI_ADDR_RAM_SIZE_64KB 0x00000004
+#define EPI_ADDR_RAM_SIZE_16MB 0x00000008
+#define EPI_ADDR_RAM_SIZE_512MB 0x0000000C
+#define EPI_ADDR_RAM_BASE_NONE 0x00000000
+#define EPI_ADDR_RAM_BASE_6 0x00000001
+#define EPI_ADDR_RAM_BASE_8 0x00000002
+
+//*****************************************************************************
+//
+// Values that can be passed to EPINonBlockingReadConfigure()
+//
+//*****************************************************************************
+#define EPI_NBCONFIG_SIZE_8 1
+#define EPI_NBCONFIG_SIZE_16 2
+#define EPI_NBCONFIG_SIZE_32 3
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIFIFOConfig()
+//
+//*****************************************************************************
+#define EPI_FIFO_CONFIG_WTFULLERR 0x00020000
+#define EPI_FIFO_CONFIG_RSTALLERR 0x00010000
+#define EPI_FIFO_CONFIG_TX_EMPTY 0x00000000
+#define EPI_FIFO_CONFIG_TX_1_4 0x00000020
+#define EPI_FIFO_CONFIG_TX_1_2 0x00000030
+#define EPI_FIFO_CONFIG_TX_3_4 0x00000040
+#define EPI_FIFO_CONFIG_RX_1_8 0x00000001
+#define EPI_FIFO_CONFIG_RX_1_4 0x00000002
+#define EPI_FIFO_CONFIG_RX_1_2 0x00000003
+#define EPI_FIFO_CONFIG_RX_3_4 0x00000004
+#define EPI_FIFO_CONFIG_RX_7_8 0x00000005
+#define EPI_FIFO_CONFIG_RX_FULL 0x00000006
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned
+// as flags from EPIIntStatus()
+//
+//*****************************************************************************
+#define EPI_INT_TXREQ 0x00000004
+#define EPI_INT_RXREQ 0x00000002
+#define EPI_INT_ERR 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIIntErrorClear(), or returned as flags from
+// EPIIntErrorStatus()
+//
+//*****************************************************************************
+#define EPI_INT_ERR_WTFULL 0x00000004
+#define EPI_INT_ERR_RSTALL 0x00000002
+#define EPI_INT_ERR_TIMEOUT 0x00000001
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+void EPIModeSet(unsigned long ulBase, unsigned long ulMode);
+void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider);
+void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulRefresh);
+void EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulFrameCount, unsigned long ulMaxWait);
+void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxWait);
+void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
+void EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulDataSize, unsigned long ulAddress);
+void EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulCount);
+void EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel);
+unsigned long EPINonBlockingReadCount(unsigned long ulBase,
+ unsigned long ulChannel);
+unsigned long EPINonBlockingReadAvail(unsigned long ulBase);
+unsigned long EPINonBlockingReadGet32(unsigned long ulBase,
+ unsigned long ulCount,
+ unsigned long *pulBuf);
+unsigned long EPINonBlockingReadGet16(unsigned long ulBase,
+ unsigned long ulCount,
+ unsigned short *pusBuf);
+unsigned long EPINonBlockingReadGet8(unsigned long ulBase,
+ unsigned long ulCount,
+ unsigned char *pucBuf);
+void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig);
+unsigned long EPINonBlockingWriteCount(unsigned long ulBase);
+void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked);
+unsigned long EPIIntErrorStatus(unsigned long ulBase);
+void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags);
+void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+void EPIIntUnregister(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __EPI_H__
diff --git a/bsp/lm3s/Libraries/driverlib/ethernet.c b/bsp/lm3s/Libraries/driverlib/ethernet.c new file mode 100644 index 0000000000..df65dee309 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/ethernet.c @@ -0,0 +1,1280 @@ +//*****************************************************************************
+//
+// ethernet.c - Driver for the Integrated Ethernet Controller
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ethernet_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ethernet.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/ethernet.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Initializes the Ethernet controller for operation.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
+//!
+//! This function will prepare the Ethernet controller for first time use in
+//! a given hardware/software configuration. This function should be called
+//! before any other Ethernet API functions are called.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original EthernetInit() API and performs the
+//! same actions. A macro is provided in <tt>ethernet.h</tt> to map the
+//! original API to this API.
+//!
+//! \note If the device configuration is changed (for example, the system clock
+//! is reprogrammed to a different speed), then the Ethernet controller must be
+//! disabled by calling the EthernetDisable() function and the controller must
+//! be reinitialized by calling the EthernetInitExpClk() function again. After
+//! the controller has been reinitialized, the controller should be
+//! reconfigured using the appropriate Ethernet API calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
+{
+ unsigned long ulDiv;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Set the Management Clock Divider register for access to the PHY
+ // register set (via EthernetPHYRead/Write).
+ //
+ // The MDC clock divided down from the system clock using the following
+ // formula. A maximum of 2.5MHz is allowed for F(mdc).
+ //
+ // F(mdc) = F(sys) / (2 * (div + 1))
+ // div = (F(sys) / (2 * F(mdc))) - 1
+ // div = (F(sys) / 2 / F(mdc)) - 1
+ //
+ // Note: Because we should round up, to ensure we don't violate the
+ // maximum clock speed, we can simplify this as follows:
+ //
+ // div = F(sys) / 2 / F(mdc)
+ //
+ // For example, given a system clock of 6.0MHz, and a div value of 1,
+ // the mdc clock would be programmed as 1.5 MHz.
+ //
+ ulDiv = (ulEthClk / 2) / 2500000;
+ HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M);
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulConfig is the configuration for the controller.
+//!
+//! After the EthernetInitExpClk() function has been called, this API function
+//! can be used to configure the various features of the Ethernet controller.
+//!
+//! The Ethernet controller provides three control registers that are used
+//! to configure the controller's operation. The transmit control register
+//! provides settings to enable full duplex operation, to auto-generate the
+//! frame check sequence, and to pad the transmit packets to the minimum
+//! length as required by the IEEE standard. The receive control register
+//! provides settings to enable reception of packets with bad frame check
+//! sequence values and to enable multi-cast or promiscuous modes. The
+//! timestamp control register provides settings that enable support logic in
+//! the controller that allow the use of the General Purpose Timer 3 to capture
+//! timestamps for the transmitted and received packets.
+//!
+//! The \e ulConfig parameter is the logical OR of the following values:
+//!
+//! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer
+//! inputs
+//! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC
+//! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets)
+//! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets
+//! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode
+//! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation
+//! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size
+//!
+//! These bit-mapped values are programmed into the transmit, receive, and/or
+//! timestamp control register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
+ ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS |
+ ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN |
+ ETH_CFG_TS_TSEN)) == 0);
+
+ //
+ // Setup the Transmit Control Register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_TCTL);
+ ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN);
+ ulTemp |= ulConfig & 0x0FF;
+ HWREG(ulBase + MAC_O_TCTL) = ulTemp;
+
+ //
+ // Setup the Receive Control Register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_RCTL);
+ ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
+ ulTemp |= (ulConfig >> 8) & 0x0FF;
+ HWREG(ulBase + MAC_O_RCTL) = ulTemp;
+
+ //
+ // Setup the Time Stamp Configuration register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_TS);
+ ulTemp &= ~(MAC_TS_TSEN);
+ ulTemp |= (ulConfig >> 16) & 0x0FF;
+ HWREG(ulBase + MAC_O_TS) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function will query the control registers of the Ethernet controller
+//! and return a bit-mapped configuration value.
+//!
+//! \sa The description of the EthernetConfigSet() function provides detailed
+//! information for the bit-mapped configuration values that will be returned.
+//!
+//! \return Returns the bit-mapped Ethernet controller configuration value.
+//
+//*****************************************************************************
+unsigned long
+EthernetConfigGet(unsigned long ulBase)
+{
+ unsigned long ulConfig;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Read and return the Ethernet controller configuration parameters,
+ // properly shifted into the appropriate bit field positions.
+ //
+ ulConfig = HWREG(ulBase + MAC_O_TS) << 16;
+ ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8;
+ ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN);
+ return(ulConfig);
+}
+
+//*****************************************************************************
+//
+//! Sets the MAC address of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
+//!
+//! This function will program the IEEE-defined MAC-48 address specified in
+//! \e pucMACAddr into the Ethernet controller. This address is used by the
+//! Ethernet controller for hardware-level filtering of incoming Ethernet
+//! packets (when promiscuous mode is not enabled).
+//!
+//! The MAC-48 address is defined as 6 octets, illustrated by the following
+//! example address. The numbers are shown in hexadecimal format.
+//!
+//! AC-DE-48-00-00-80
+//!
+//! In this representation, the first three octets (AC-DE-48) are the
+//! Organizationally Unique Identifier (OUI). This is a number assigned by
+//! the IEEE to an organization that requests a block of MAC addresses. The
+//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner
+//! to uniquely identify a piece of hardware within that organization that is
+//! to be connected to the Ethernet.
+//!
+//! In this representation, the octets are transmitted from left to right,
+//! with the ``AC'' octet being transmitted first and the ``80'' octet being
+//! transmitted last. Within an octet, the bits are transmitted LSB to MSB.
+//! For this address, the first bit to be transmitted would be ``0'', the LSB
+//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of
+//! ``80''.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
+{
+ unsigned long ulTemp;
+ unsigned char *pucTemp = (unsigned char *)&ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucMACAddr != 0);
+
+ //
+ // Program the MAC Address into the device. The first four bytes of the
+ // MAC Address are placed into the IA0 register. The remaining two bytes
+ // of the MAC address are placed into the IA1 register.
+ //
+ pucTemp[0] = pucMACAddr[0];
+ pucTemp[1] = pucMACAddr[1];
+ pucTemp[2] = pucMACAddr[2];
+ pucTemp[3] = pucMACAddr[3];
+ HWREG(ulBase + MAC_O_IA0) = ulTemp;
+ ulTemp = 0;
+ pucTemp[0] = pucMACAddr[4];
+ pucTemp[1] = pucMACAddr[5];
+ HWREG(ulBase + MAC_O_IA1) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the MAC address of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucMACAddr is the pointer to the location in which to store the
+//! array of MAC-48 address octets.
+//!
+//! This function will read the currently programmed MAC address into the
+//! \e pucMACAddr buffer.
+//!
+//! \sa Refer to EthernetMACAddrSet() API description for more details about
+//! the MAC address format.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
+{
+ unsigned long ulTemp;
+ unsigned char *pucTemp = (unsigned char *)&ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucMACAddr != 0);
+
+ //
+ // Read the MAC address from the device. The first four bytes of the
+ // MAC address are read from the IA0 register. The remaining two bytes
+ // of the MAC addres
+ //
+ ulTemp = HWREG(ulBase + MAC_O_IA0);
+ pucMACAddr[0] = pucTemp[0];
+ pucMACAddr[1] = pucTemp[1];
+ pucMACAddr[2] = pucTemp[2];
+ pucMACAddr[3] = pucTemp[3];
+ ulTemp = HWREG(ulBase + MAC_O_IA1);
+ pucMACAddr[4] = pucTemp[0];
+ pucMACAddr[5] = pucTemp[1];
+}
+
+//*****************************************************************************
+//
+//! Enables the Ethernet controller for normal operation.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! Once the Ethernet controller has been configured using the
+//! EthernetConfigSet() function and the MAC address has been programmed using
+//! the EthernetMACAddrSet() function, this API function can be called to
+//! enable the controller for normal operation.
+//!
+//! This function will enable the controller's transmitter and receiver, and
+//! will reset the receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Reset the receive FIFO.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+
+ //
+ // Enable the Ethernet receiver.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN;
+
+ //
+ // Enable Ethernet transmitter.
+ //
+ HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN;
+
+ //
+ // Reset the receive FIFO again, after the receiver has been enabled.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+}
+
+//*****************************************************************************
+//
+//! Disables the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! When terminating operations on the Ethernet interface, this function should
+//! be called. This function will disable the transmitter and receiver, and
+//! will clear out the receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Reset the receive FIFO.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+
+ //
+ // Disable the Ethernet transmitter.
+ //
+ HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN);
+
+ //
+ // Disable the Ethernet receiver.
+ //
+ HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN);
+
+ //
+ // Reset the receive FIFO again, after the receiver has been disabled.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+}
+
+//*****************************************************************************
+//
+//! Check for packet available from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! The Ethernet controller provides a register that contains the number of
+//! packets available in the receive FIFO. When the last bytes of a packet are
+//! successfully received (that is, the frame check sequence bytes), the packet
+//! count is incremented. Once the packet has been fully read (including the
+//! frame check sequence bytes) from the FIFO, the packet count will be
+//! decremented.
+//!
+//! \return Returns \b true if there are one or more packets available in the
+//! receive FIFO, including the current packet being read, and \b false
+//! otherwise.
+//
+//*****************************************************************************
+tBoolean
+EthernetPacketAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Return the availability of packets.
+ //
+ return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Checks for packet space available in the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! The Ethernet controller's transmit FIFO is designed to support a single
+//! packet at a time. After the packet has been written into the FIFO, the
+//! transmit request bit must be set to enable the transmission of the packet.
+//! Only after the packet has been transmitted can a new packet be written
+//! into the FIFO. This function will simply check to see if a packet is
+//! in progress. If so, there is no space available in the transmit FIFO.
+//!
+//! \return Returns \b true if a space is available in the transmit FIFO, and
+//! \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+EthernetSpaceAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Internal function for reading a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! Based on the following table of how the receive frame is stored in the
+//! receive FIFO, this function will extract a packet from the FIFO and store
+//! it in the packet buffer that was passed in.
+//!
+//! Format of the data in the RX FIFO is as follows:
+//!
+//! \verbatim
+//! +---------+----------+----------+----------+----------+
+//! | | 31:24 | 23:16 | 15:8 | 7:0 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 0 | DA 2 | DA 1 | FL MSB | FL LSB |
+//! +---------+----------+----------+----------+----------+
+//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
+//! +---------+----------+----------+----------+----------+
+//! | ... | | | | |
+//! +---------+----------+----------+----------+----------+
+//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word Y | FCS 4 | FCS 3 | FCS 2 | FCS 1 |
+//! +---------+----------+----------+----------+----------+
+//! \endverbatim
+//!
+//! Where FL is Frame Length, (FL + DA + SA + FT + DATA + FCS) Bytes.
+//! Where DA is Destination (MAC) Address.
+//! Where SA is Source (MAC) Address.
+//! Where FT is Frame Type (or Frame Length for Ethernet).
+//! Where DATA is Payload Data for the Ethernet Frame.
+//! Where FCS is the Frame Check Sequence.
+//!
+//! \return Returns the negated packet length \b -n if the packet is too large
+//! for \e pucBuf, and returns the packet length \b n otherwise.
+//
+//*****************************************************************************
+static long
+EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ unsigned long ulTemp;
+ long lFrameLen, lTempLen;
+ long i = 0;
+
+ //
+ // Read WORD 0 (see format above) from the FIFO, set the receive
+ // Frame Length and store the first two bytes of the destination
+ // address in the receive buffer.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ lFrameLen = (long)(ulTemp & 0xFFFF);
+ pucBuf[i++] = (unsigned char) ((ulTemp >> 16) & 0xff);
+ pucBuf[i++] = (unsigned char) ((ulTemp >> 24) & 0xff);
+
+ //
+ // Read all but the last WORD into the receive buffer.
+ //
+ lTempLen = (lBufLen < (lFrameLen - 6)) ? lBufLen : (lFrameLen - 6);
+ while(i <= (lTempLen - 4))
+ {
+ *(unsigned long *)&pucBuf[i] = HWREG(ulBase + MAC_O_DATA);
+ i += 4;
+ }
+
+ //
+ // Read the last 1, 2, or 3 BYTES into the buffer
+ //
+ if(i < lTempLen)
+ {
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ if(i == lTempLen - 3)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 8) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 16) & 0xff);
+ i += 1;
+ }
+ else if(i == lTempLen - 2)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 8) & 0xff);
+ i += 2;
+ }
+ else if(i == lTempLen - 1)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ i += 3;
+ }
+ }
+
+ //
+ // Read any remaining WORDS (that did not fit into the buffer).
+ //
+ while(i < (lFrameLen - 2))
+ {
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ i += 4;
+ }
+
+ //
+ // If frame was larger than the buffer, return the "negative" frame length
+ //
+ lFrameLen -= 6;
+ if(lFrameLen > lBufLen)
+ {
+ return(-lFrameLen);
+ }
+
+ //
+ // Return the Frame Length
+ //
+ return(lFrameLen);
+}
+
+//*****************************************************************************
+//
+//! Receives a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! This function reads a packet from the receive FIFO of the controller and
+//! places it into \e pucBuf. If no packet is available the function will
+//! return immediately. Otherwise, the function will read the entire packet
+//! from the receive FIFO. If there are more bytes in the packet than will fit
+//! into \e pucBuf (as specified by \e lBufLen), the function will return the
+//! negated length of the packet and the buffer will contain \e lBufLen bytes
+//! of the packet. Otherwise, the function will return the length of the
+//! packet that was read and \e pucBuf will contain the entire packet
+//! (excluding the frame check sequence bytes).
+//!
+//! This function replaces the original EthernetPacketNonBlockingGet() API and
+//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
+//! map the original API to this API.
+//!
+//! \note This function will return immediately if no packet is available.
+//!
+//! \return Returns \b 0 if no packet is available, the negated packet length
+//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n
+//! otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Check to see if any packets are available.
+ //
+ if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Read the packet, and return.
+ //
+ return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Waits for a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! This function reads a packet from the receive FIFO of the controller and
+//! places it into \e pucBuf. The function will wait until a packet is
+//! available in the FIFO. Then the function will read the entire packet
+//! from the receive FIFO. If there are more bytes in the packet than will
+//! fit into \e pucBuf (as specified by \e lBufLen), the function will return
+//! the negated length of the packet and the buffer will contain \e lBufLen
+//! bytes of the packet. Otherwise, the function will return the length of
+//! the packet that was read and \e pucBuf will contain the entire packet
+//! (excluding the frame check sequence bytes).
+//!
+//! \note This function is blocking and will not return until a packet arrives.
+//!
+//! \return Returns the negated packet length \b -n if the packet is too large
+//! for \e pucBuf, and returns the packet length \b n otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Wait for a packet to become available
+ //
+ while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
+ {
+ }
+
+ //
+ // Read the packet
+ //
+ return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Internal function for sending a packet to the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! Puts a packet into the transmit FIFO of the controller.
+//!
+//! Format of the data in the TX FIFO is as follows:
+//!
+//! \verbatim
+//! +---------+----------+----------+----------+----------+
+//! | | 31:24 | 23:16 | 15:8 | 7:0 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 0 | DA 2 | DA 1 | PL MSB | PL LSB |
+//! +---------+----------+----------+----------+----------+
+//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
+//! +---------+----------+----------+----------+----------+
+//! | ... | | | | |
+//! +---------+----------+----------+----------+----------+
+//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
+//! +---------+----------+----------+----------+----------+
+//! \endverbatim
+//!
+//! Where PL is Payload Length, (DATA) only
+//! Where DA is Destination (MAC) Address
+//! Where SA is Source (MAC) Address
+//! Where FT is Frame Type (or Frame Length for Ethernet)
+//! Where DATA is Payload Data for the Ethernet Frame
+//!
+//! \return Returns the negated packet length \b -lBufLen if the packet is too
+//! large for FIFO, and the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+static long
+EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ unsigned long ulTemp;
+ long i = 0;
+
+ //
+ // If the packet is too large, return the negative packet length as
+ // an error code.
+ //
+ if(lBufLen > (2048 - 2))
+ {
+ return(-lBufLen);
+ }
+
+ //
+ // Build and write WORD 0 (see format above) to the transmit FIFO.
+ //
+ ulTemp = (unsigned long)(lBufLen - 14);
+ ulTemp |= (pucBuf[i++] << 16);
+ ulTemp |= (pucBuf[i++] << 24);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+
+ //
+ // Write each subsequent WORD n to the transmit FIFO, except for the last
+ // WORD (if the word does not contain 4 bytes).
+ //
+ while(i <= (lBufLen - 4))
+ {
+ HWREG(ulBase + MAC_O_DATA) = *(unsigned long *)&pucBuf[i];
+ i += 4;
+ }
+
+ //
+ // Build the last word of the remaining 1, 2, or 3 bytes, and store
+ // the WORD into the transmit FIFO.
+ //
+ if(i != lBufLen)
+ {
+ if(i == (lBufLen - 3))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ ulTemp |= (pucBuf[i++] << 8);
+ ulTemp |= (pucBuf[i++] << 16);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ else if(i == (lBufLen - 2))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ ulTemp |= (pucBuf[i++] << 8);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ else if(i == (lBufLen - 1))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ }
+
+ //
+ // Activate the transmitter
+ //
+ HWREG(ulBase + MAC_O_TR) = MAC_TR_NEWTX;
+
+ //
+ // Return the Buffer Length transmitted.
+ //
+ return(lBufLen);
+}
+
+//*****************************************************************************
+//
+//! Sends a packet to the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
+//! into the transmit FIFO of the controller and then activates the
+//! transmitter for this packet. If no space is available in the FIFO, the
+//! function will return immediately. If space is available, the
+//! function will return once \e lBufLen bytes of the packet have been placed
+//! into the FIFO and the transmitter has been started. The function will not
+//! wait for the transmission to complete. The function will return the
+//! negated \e lBufLen if the length is larger than the space available in
+//! the transmit FIFO.
+//!
+//! This function replaces the original EthernetPacketNonBlockingPut() API and
+//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
+//! map the original API to this API.
+//!
+//! \note This function does not block and will return immediately if no space
+//! is available for the transmit packet.
+//!
+//! \return Returns \b 0 if no space is available in the transmit FIFO, the
+//! negated packet length \b -lBufLen if the packet is too large for FIFO, and
+//! the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Check if the transmit FIFO is in use and return the appropriate code.
+ //
+ if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
+ {
+ return(0);
+ }
+
+ //
+ // Send the packet and return.
+ //
+ return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Waits to send a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
+//! into the transmit FIFO of the controller and then activates the transmitter
+//! for this packet. This function will wait until the transmit FIFO is empty.
+//! Once space is available, the function will return once \e lBufLen bytes of
+//! the packet have been placed into the FIFO and the transmitter has been
+//! started. The function will not wait for the transmission to complete. The
+//! function will return the negated \e lBufLen if the length is larger than
+//! the space available in the transmit FIFO.
+//!
+//! \note This function blocks and will wait until space is available for the
+//! transmit packet before returning.
+//!
+//! \return Returns the negated packet length \b -lBufLen if the packet is too
+//! large for FIFO, and the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Wait for current packet (if any) to complete.
+ //
+ while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
+ {
+ }
+
+ //
+ // Send the packet and return.
+ //
+ return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled Ethernet interrupts occur.
+//!
+//! This function sets the handler to be called when the Ethernet interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It
+//! is the interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pfnHandler != 0);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_ETH, pfnHandler);
+
+ //
+ // Enable the Ethernet interrupt.
+ //
+ IntEnable(INT_ETH);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function unregisters the interrupt handler. This will disable the
+//! global interrupt in the interrupt controller so that the interrupt handler
+//! no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_ETH);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_ETH);
+}
+
+//*****************************************************************************
+//
+//! Enables individual Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated Ethernet interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated
+//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17,
+//! must be read to determine which PHY interrupt has occurred. This register
+//! can be read using the EthernetPHYRead() API function.
+//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the
+//! management interface has completed successfully.
+//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred
+//! during reception of a frame. This error can indicate a length mismatch, a
+//! CRC failure, or an error indication from the PHY.
+//! - \b ETH_INT_RXOF - This interrupt indicates that a frame has been received
+//! that exceeds the available space in the RX FIFO.
+//! - \b ETH_INT_TX - This interrupt indicates that the packet stored in the TX
+//! FIFO has been successfully transmitted.
+//! - \b ETH_INT_TXER - This interrupt indicates that an error has occurred
+//! during the transmission of a packet. This error can be either a retry
+//! failure during the back-off process, or an invalid length stored in the TX
+//! FIFO.
+//! - \b ETH_INT_RX - This interrupt indicates that one (or more) packets are
+//! available in the RX FIFO for processing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + MAC_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated Ethernet interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to EthernetIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + MAC_O_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current Ethernet interrupt status.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param bMasked is false if the raw interrupt status is required and true
+//! if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the Ethernet controller. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in EthernetIntEnable().
+//
+//*****************************************************************************
+unsigned long
+EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Read the unmasked status.
+ //
+ ulStatus = HWREG(ulBase + MAC_O_RIS);
+
+ //
+ // If masked status is requested, mask it off.
+ //
+ if(bMasked)
+ {
+ ulStatus &= HWREG(ulBase + MAC_O_IM);
+ }
+
+ //
+ // Return the interrupt status value.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified Ethernet interrupt sources are cleared so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to EthernetIntEnable().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Writes to the PHY register.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ucRegAddr is the address of the PHY register to be accessed.
+//! \param ulData is the data to be written to the PHY register.
+//!
+//! This function will write the \e ulData to the PHY register specified by
+//! \e ucRegAddr.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
+ unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Wait for any pending transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Program the DATA to be written.
+ //
+ HWREG(ulBase + MAC_O_MTXD) = ulData & MAC_MTXD_MDTX_M;
+
+ //
+ // Program the PHY register address and initiate the transaction.
+ //
+ HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
+ MAC_MCTL_WRITE | MAC_MCTL_START);
+
+ //
+ // Wait for the write transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Reads from a PHY register.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ucRegAddr is the address of the PHY register to be accessed.
+//!
+//! This function will return the contents of the PHY register specified by
+//! \e ucRegAddr.
+//!
+//! \return Returns the 16-bit value read from the PHY.
+//
+//*****************************************************************************
+unsigned long
+EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Wait for any pending transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Program the PHY register address and initiate the transaction.
+ //
+ HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
+ MAC_MCTL_START);
+
+ //
+ // Wait for the transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Return the PHY data that was read.
+ //
+ return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/ethernet.h b/bsp/lm3s/Libraries/driverlib/ethernet.h new file mode 100644 index 0000000000..16db1fe03f --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/ethernet.h @@ -0,0 +1,172 @@ +//*****************************************************************************
+//
+// ethernet.h - Defines and Macros for the ethernet module.
+//
+// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ETHERNET_H__
+#define __ETHERNET_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and
+// returned from EthernetConfigGet.
+//
+//*****************************************************************************
+#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
+// EthernetIntClear as the ulIntFlags parameter, and returned from
+// EthernetIntStatus.
+//
+//*****************************************************************************
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
+#define ETH_INT_MDIO 0x020 // Management Transaction
+#define ETH_INT_RXER 0x010 // RX Error
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
+#define ETH_INT_TX 0x004 // TX Complete
+#define ETH_INT_TXER 0x002 // TX Error
+#define ETH_INT_RX 0x001 // RX Complete
+
+//*****************************************************************************
+//
+// Helper Macros for Ethernet Processing
+//
+//*****************************************************************************
+//
+// htonl/ntohl - big endian/little endian byte swapping macros for
+// 32-bit (long) values
+//
+//*****************************************************************************
+#ifndef htonl
+ #define htonl(a) \
+ ((((a) >> 24) & 0x000000ff) | \
+ (((a) >> 8) & 0x0000ff00) | \
+ (((a) << 8) & 0x00ff0000) | \
+ (((a) << 24) & 0xff000000))
+#endif
+
+#ifndef ntohl
+ #define ntohl(a) htonl((a))
+#endif
+
+//*****************************************************************************
+//
+// htons/ntohs - big endian/little endian byte swapping macros for
+// 16-bit (short) values
+//
+//*****************************************************************************
+#ifndef htons
+ #define htons(a) \
+ ((((a) >> 8) & 0x00ff) | \
+ (((a) << 8) & 0xff00))
+#endif
+
+#ifndef ntohs
+ #define ntohs(a) htons((a))
+#endif
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern unsigned long EthernetConfigGet(unsigned long ulBase);
+extern void EthernetMACAddrSet(unsigned long ulBase,
+ unsigned char *pucMACAddr);
+extern void EthernetMACAddrGet(unsigned long ulBase,
+ unsigned char *pucMACAddr);
+extern void EthernetEnable(unsigned long ulBase);
+extern void EthernetDisable(unsigned long ulBase);
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
+extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
+ unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
+ unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen);
+extern void EthernetIntRegister(unsigned long ulBase,
+ void (*pfnHandler)(void));
+extern void EthernetIntUnregister(unsigned long ulBase);
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
+ unsigned long ulData);
+extern unsigned long EthernetPHYRead(unsigned long ulBase,
+ unsigned char ucRegAddr);
+
+//*****************************************************************************
+//
+// Several Ethernet APIs have been renamed, with the original function name
+// being deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define EthernetInit(a) \
+ EthernetInitExpClk(a, SysCtlClockGet())
+#define EthernetPacketNonBlockingGet(a, b, c) \
+ EthernetPacketGetNonBlocking(a, b, c)
+#define EthernetPacketNonBlockingPut(a, b, c) \
+ EthernetPacketPutNonBlocking(a, b, c)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ETHERNET_H__
diff --git a/bsp/lm3s/Libraries/driverlib/flash.c b/bsp/lm3s/Libraries/driverlib/flash.c new file mode 100644 index 0000000000..56eaa9ade2 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/flash.c @@ -0,0 +1,915 @@ +//*****************************************************************************
+//
+// flash.c - Driver for programming the on-chip flash.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_flash.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Program Enable (FMPPE) register.
+//
+//*****************************************************************************
+static const unsigned long g_pulFMPPERegs[] =
+{
+ FLASH_FMPPE,
+ FLASH_FMPPE1,
+ FLASH_FMPPE2,
+ FLASH_FMPPE3
+};
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Read Enable (FMPRE) register.
+//
+//*****************************************************************************
+static const unsigned long g_pulFMPRERegs[] =
+{
+ FLASH_FMPRE,
+ FLASH_FMPRE1,
+ FLASH_FMPRE2,
+ FLASH_FMPRE3
+};
+
+//*****************************************************************************
+//
+//! Gets the number of processor clocks per micro-second.
+//!
+//! This function returns the number of clocks per micro-second, as presently
+//! known by the flash controller.
+//!
+//! \return Returns the number of processor clocks per micro-second.
+//
+//*****************************************************************************
+unsigned long
+FlashUsecGet(void)
+{
+ //
+ // Return the number of clocks per micro-second.
+ //
+ return(HWREG(FLASH_USECRL) + 1);
+}
+
+//*****************************************************************************
+//
+//! Sets the number of processor clocks per micro-second.
+//!
+//! \param ulClocks is the number of processor clocks per micro-second.
+//!
+//! This function is used to tell the flash controller the number of processor
+//! clocks per micro-second. This value must be programmed correctly or the
+//! flash most likely will not program correctly; it has no affect on reading
+//! flash.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashUsecSet(unsigned long ulClocks)
+{
+ //
+ // Set the number of clocks per micro-second.
+ //
+ HWREG(FLASH_USECRL) = ulClocks - 1;
+}
+
+//*****************************************************************************
+//
+//! Erases a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be erased.
+//!
+//! This function will erase a 1 kB block of the on-chip flash. After erasing,
+//! the block will be filled with 0xFF bytes. Read-only and execute-only
+//! blocks cannot be erased.
+//!
+//! This function will not return until the block has been erased.
+//!
+//! \return Returns 0 on success, or -1 if an invalid block address was
+//! specified or the block is write-protected.
+//
+//*****************************************************************************
+long
+FlashErase(unsigned long ulAddress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
+
+ //
+ // Clear the flash access interrupt.
+ //
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
+
+ //
+ // Erase the block.
+ //
+ HWREG(FLASH_FMA) = ulAddress;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
+
+ //
+ // Wait until the block has been erased.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
+ {
+ }
+
+ //
+ // Return an error if an access violation occurred.
+ //
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
+ {
+ return(-1);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Programs flash.
+//!
+//! \param pulData is a pointer to the data to be programmed.
+//! \param ulAddress is the starting address in flash to be programmed. Must
+//! be a multiple of four.
+//! \param ulCount is the number of bytes to be programmed. Must be a multiple
+//! of four.
+//!
+//! This function will program a sequence of words into the on-chip flash.
+//! Programming each location consists of the result of an AND operation
+//! of the new data and the existing data; in other words bits that contain
+//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
+//! to 1. Therefore, a word can be programmed multiple times as long as these
+//! rules are followed; if a program operation attempts to change a 0 bit to
+//! a 1 bit, that bit will not have its value changed.
+//!
+//! Since the flash is programmed one word at a time, the starting address and
+//! byte count must both be multiples of four. It is up to the caller to
+//! verify the programmed contents, if such verification is required.
+//!
+//! This function will not return until the data has been programmed.
+//!
+//! \return Returns 0 on success, or -1 if a programming error is encountered.
+//
+//*****************************************************************************
+long
+FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+ unsigned long ulCount)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulAddress & 3));
+ ASSERT(!(ulCount & 3));
+
+ //
+ // Clear the flash access interrupt.
+ //
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
+
+ //
+ // See if this device has a write buffer.
+ //
+ if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB)
+ {
+ //
+ // Loop over the words to be programmed.
+ //
+ while(ulCount)
+ {
+ //
+ // Set the address of this block of words.
+ //
+ HWREG(FLASH_FMA) = ulAddress & ~(0x7f);
+
+ //
+ // Loop over the words in this 32-word block.
+ //
+ while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
+ (ulCount != 0))
+ {
+ //
+ // Write this word into the write buffer.
+ //
+ HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++;
+ ulAddress += 4;
+ ulCount -= 4;
+ }
+
+ //
+ // Program the contents of the write buffer into flash.
+ //
+ HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
+
+ //
+ // Wait until the write buffer has been programmed.
+ //
+ while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
+ {
+ }
+ }
+ }
+ else
+ {
+ //
+ // Loop over the words to be programmed.
+ //
+ while(ulCount)
+ {
+ //
+ // Program the next word.
+ //
+ HWREG(FLASH_FMA) = ulAddress;
+ HWREG(FLASH_FMD) = *pulData;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
+
+ //
+ // Wait until the word has been programmed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
+ {
+ }
+
+ //
+ // Increment to the next word.
+ //
+ pulData++;
+ ulAddress += 4;
+ ulCount -= 4;
+ }
+ }
+
+ //
+ // Return an error if an access violation occurred.
+ //
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
+ {
+ return(-1);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the protection setting for a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be queried.
+//!
+//! This function will get the current protection for the specified 2 kB block
+//! of flash. Each block can be read/write, read-only, or execute-only.
+//! Read/write blocks can be read, executed, erased, and programmed. Read-only
+//! blocks can be read and executed. Execute-only blocks can only be executed;
+//! processor and debugger data reads are not allowed.
+//!
+//! \return Returns the protection setting for this block. See
+//! FlashProtectSet() for possible values.
+//
+//*****************************************************************************
+tFlashProtection
+FlashProtectGet(unsigned long ulAddress)
+{
+ unsigned long ulFMPRE, ulFMPPE;
+ unsigned long ulBank;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
+
+ //
+ // Calculate the Flash Bank from Base Address, and mask off the Bank
+ // from ulAddress for subsequent reference.
+ //
+ ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4);
+ ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
+
+ //
+ // Read the appropriate flash protection registers for the specified
+ // flash bank.
+ //
+ ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
+ ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG protect options, and are
+ // not available for the FLASH protection scheme. When Querying Block
+ // Protection, assume these bits are 1.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
+ }
+
+ //
+ // Check the appropriate protection bits for the block of memory that
+ // is specified by the address.
+ //
+ switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
+ FLASH_FMP_BLOCK_0) << 1) |
+ ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
+ {
+ //
+ // This block is marked as execute only (that is, it can not be erased
+ // or programmed, and the only reads allowed are via the instruction
+ // fetch interface).
+ //
+ case 0:
+ case 1:
+ {
+ return(FlashExecuteOnly);
+ }
+
+ //
+ // This block is marked as read only (that is, it can not be erased or
+ // programmed).
+ //
+ case 2:
+ {
+ return(FlashReadOnly);
+ }
+
+ //
+ // This block is read/write; it can be read, erased, and programmed.
+ //
+ case 3:
+ default:
+ {
+ return(FlashReadWrite);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the protection setting for a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be protected.
+//! \param eProtect is the protection to be applied to the block. Can be one
+//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
+//!
+//! This function will set the protection for the specified 2 kB block of
+//! flash. Blocks which are read/write can be made read-only or execute-only.
+//! Blocks which are read-only can be made execute-only. Blocks which are
+//! execute-only cannot have their protection modified. Attempts to make the
+//! block protection less stringent (that is, read-only to read/write) will
+//! result in a failure (and be prevented by the hardware).
+//!
+//! Changes to the flash protection are maintained only until the next reset.
+//! This allows the application to be executed in the desired flash protection
+//! environment to check for inappropriate flash access (via the flash
+//! interrupt). To make the flash protection permanent, use the
+//! FlashProtectSave() function.
+//!
+//! \return Returns 0 on success, or -1 if an invalid address or an invalid
+//! protection was specified.
+//
+//*****************************************************************************
+long
+FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
+{
+ unsigned long ulProtectRE, ulProtectPE;
+ unsigned long ulBank;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
+ ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
+ (eProtect == FlashExecuteOnly));
+
+ //
+ // Convert the address into a block number.
+ //
+ ulAddress /= FLASH_PROTECT_SIZE;
+
+ //
+ // ulAddress contains a "raw" block number. Derive the Flash Bank from
+ // the "raw" block number, and convert ulAddress to a "relative"
+ // block number.
+ //
+ ulBank = ((ulAddress / 32) % 4);
+ ulAddress %= 32;
+
+ //
+ // Get the current protection for the specified flash bank.
+ //
+ ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]);
+ ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]);
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG protect options, and are
+ // not available for the FLASH protection scheme. When setting protection,
+ // check to see if block 30 or 31 and protection is FlashExecuteOnly. If
+ // so, return an error condition.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ if((ulAddress >= 30) && (eProtect == FlashExecuteOnly))
+ {
+ return(-1);
+ }
+ }
+
+ //
+ // Set the protection based on the requested proection.
+ //
+ switch(eProtect)
+ {
+ //
+ // Make this block execute only.
+ //
+ case FlashExecuteOnly:
+ {
+ //
+ // Turn off the read and program bits for this block.
+ //
+ ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+
+ //
+ // We're done handling this protection.
+ //
+ break;
+ }
+
+ //
+ // Make this block read only.
+ //
+ case FlashReadOnly:
+ {
+ //
+ // The block can not be made read only if it is execute only.
+ //
+ if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0)
+ {
+ return(-1);
+ }
+
+ //
+ // Make this block read only.
+ //
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+
+ //
+ // We're done handling this protection.
+ //
+ break;
+ }
+
+ //
+ // Make this block read/write.
+ //
+ case FlashReadWrite:
+ default:
+ {
+ //
+ // The block can not be made read/write if it is not already
+ // read/write.
+ //
+ if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0) ||
+ (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0))
+ {
+ return(-1);
+ }
+
+ //
+ // The block is already read/write, so there is nothing to do.
+ //
+ return(0);
+ }
+ }
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG options, and are not
+ // available for the FLASH protection scheme. When setting block
+ // protection, ensure that these bits are not altered.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
+ ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
+ (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
+ }
+
+ //
+ // Set the new protection for the specified flash bank.
+ //
+ HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE;
+ HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the flash protection settings.
+//!
+//! This function will make the currently programmed flash protection settings
+//! permanent. This is a non-reversible operation; a chip reset or power cycle
+//! will not change the flash protection.
+//!
+//! This function will not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashProtectSave(void)
+{
+ int ulTemp, ulLimit;
+
+ //
+ // If running on a Sandstorm-class device, only trigger a save of the first
+ // two protection registers (FMPRE and FMPPE). Otherwise, save the
+ // entire bank of flash protection registers.
+ //
+ ulLimit = CLASS_IS_SANDSTORM ? 2 : 8;
+ for(ulTemp = 0; ulTemp < ulLimit; ulTemp++)
+ {
+ //
+ // Tell the flash controller to write the flash protection register.
+ //
+ HWREG(FLASH_FMA) = ulTemp;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the user registers.
+//!
+//! \param pulUser0 is a pointer to the location to store USER Register 0.
+//! \param pulUser1 is a pointer to the location to store USER Register 1.
+//!
+//! This function will read the contents of user registers (0 and 1), and
+//! store them in the specified locations.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
+{
+ //
+ // Verify that the pointers are valid.
+ //
+ ASSERT(pulUser0 != 0);
+ ASSERT(pulUser1 != 0);
+
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Get and store the current value of the user registers.
+ //
+ *pulUser0 = HWREG(FLASH_USERREG0);
+ *pulUser1 = HWREG(FLASH_USERREG1);
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the user registers.
+//!
+//! \param ulUser0 is the value to store in USER Register 0.
+//! \param ulUser1 is the value to store in USER Register 1.
+//!
+//! This function will set the contents of the user registers (0 and 1) to
+//! the specified values.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
+{
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Save the new values into the user registers.
+ //
+ HWREG(FLASH_USERREG0) = ulUser0;
+ HWREG(FLASH_USERREG1) = ulUser1;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the user registers.
+//!
+//! This function will make the currently programmed user register settings
+//! permanent. This is a non-reversible operation; a chip reset or power cycle
+//! will not change this setting.
+//!
+//! This function will not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserSave(void)
+{
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Setting the MSB of FMA will trigger a permanent save of a USER
+ // register. Bit 0 will indicate User 0 (0) or User 1 (1).
+ //
+ HWREG(FLASH_FMA) = 0x80000000;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+
+ //
+ // Tell the flash controller to write the USER1 Register.
+ //
+ HWREG(FLASH_FMA) = 0x80000001;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the flash interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the flash
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when the flash interrupt occurs. The
+//! flash controller can generate an interrupt when an invalid flash access
+//! occurs, such as trying to program or erase a read-only block, or trying to
+//! read from an execute-only block. It can also generate an interrupt when a
+//! program or erase operation has completed. The interrupt will be
+//! automatically enabled when the handler is registered.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_FLASH, pfnHandler);
+
+ //
+ // Enable the flash interrupt.
+ //
+ IntEnable(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the flash interrupt.
+//!
+//! This function will clear the handler to be called when the flash interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_FLASH);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! Enables individual flash controller interrupt sources.
+//!
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//!
+//! Enables the indicated flash controller interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntEnable(unsigned long ulIntFlags)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(FLASH_FCIM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual flash controller interrupt sources.
+//!
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//!
+//! Disables the indicated flash controller interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntDisable(unsigned long ulIntFlags)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(FLASH_FCIM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the flash controller. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_AMISC.
+//
+//*****************************************************************************
+unsigned long
+FlashIntGetStatus(tBoolean bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(FLASH_FCMISC));
+ }
+ else
+ {
+ return(HWREG(FLASH_FCRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears flash controller interrupt sources.
+//!
+//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
+//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_AMISC values.
+//!
+//! The specified flash controller interrupt sources are cleared, so that they
+//! no longer assert. This must be done in the interrupt handler to keep it
+//! from being called again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntClear(unsigned long ulIntFlags)
+{
+ //
+ // Clear the flash interrupt.
+ //
+ HWREG(FLASH_FCMISC) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/flash.h b/bsp/lm3s/Libraries/driverlib/flash.h new file mode 100644 index 0000000000..0d1f7d4fd5 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/flash.h @@ -0,0 +1,89 @@ +//*****************************************************************************
+//
+// flash.h - Prototypes for the flash driver.
+//
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FlashProtectSet(), and returned by
+// FlashProtectGet().
+//
+//*****************************************************************************
+typedef enum
+{
+ FlashReadWrite, // Flash can be read and written
+ FlashReadOnly, // Flash can only be read
+ FlashExecuteOnly // Flash can only be executed
+}
+tFlashProtection;
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long FlashUsecGet(void);
+extern void FlashUsecSet(unsigned long ulClocks);
+extern long FlashErase(unsigned long ulAddress);
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+ unsigned long ulCount);
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
+extern long FlashProtectSet(unsigned long ulAddress,
+ tFlashProtection eProtect);
+extern long FlashProtectSave(void);
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
+extern long FlashUserSave(void);
+extern void FlashIntRegister(void (*pfnHandler)(void));
+extern void FlashIntUnregister(void);
+extern void FlashIntEnable(unsigned long ulIntFlags);
+extern void FlashIntDisable(unsigned long ulIntFlags);
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);
+extern void FlashIntClear(unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLASH_H__
diff --git a/bsp/lm3s/Libraries/driverlib/gpio.c b/bsp/lm3s/Libraries/driverlib/gpio.c new file mode 100644 index 0000000000..9936d44373 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/gpio.c @@ -0,0 +1,1512 @@ +//*****************************************************************************
+//
+// gpio.c - API for GPIO ports
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup gpio_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/gpio.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// The base addresses of all the GPIO modules. Both the APB and AHB apertures
+// are provided.
+//
+//*****************************************************************************
+static const unsigned long g_pulGPIOBaseAddrs[] =
+{
+ GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE,
+ GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE,
+ GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE,
+ GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE,
+ GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE,
+ GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE,
+ GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE,
+ GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE,
+ GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE,
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a GPIO base address.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function determines if a GPIO port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+GPIOBaseValid(unsigned long ulPort)
+{
+ return((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTA_AHB_BASE) ||
+ (ulPort == GPIO_PORTB_BASE) || (ulPort == GPIO_PORTB_AHB_BASE) ||
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTC_AHB_BASE) ||
+ (ulPort == GPIO_PORTD_BASE) || (ulPort == GPIO_PORTD_AHB_BASE) ||
+ (ulPort == GPIO_PORTE_BASE) || (ulPort == GPIO_PORTE_AHB_BASE) ||
+ (ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) ||
+ (ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) ||
+ (ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE) ||
+ (ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the GPIO interrupt number.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! Given a GPIO base address, returns the corresponding interrupt number.
+//!
+//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
+//
+//*****************************************************************************
+static long
+GPIOGetIntNumber(unsigned long ulPort)
+{
+ unsigned int ulInt;
+
+ //
+ // Determine the GPIO interrupt number for the given module.
+ //
+ switch(ulPort)
+ {
+ case GPIO_PORTA_BASE:
+ case GPIO_PORTA_AHB_BASE:
+ {
+ ulInt = INT_GPIOA;
+ break;
+ }
+
+ case GPIO_PORTB_BASE:
+ case GPIO_PORTB_AHB_BASE:
+ {
+ ulInt = INT_GPIOB;
+ break;
+ }
+
+ case GPIO_PORTC_BASE:
+ case GPIO_PORTC_AHB_BASE:
+ {
+ ulInt = INT_GPIOC;
+ break;
+ }
+
+ case GPIO_PORTD_BASE:
+ case GPIO_PORTD_AHB_BASE:
+ {
+ ulInt = INT_GPIOD;
+ break;
+ }
+
+ case GPIO_PORTE_BASE:
+ case GPIO_PORTE_AHB_BASE:
+ {
+ ulInt = INT_GPIOE;
+ break;
+ }
+
+ case GPIO_PORTF_BASE:
+ case GPIO_PORTF_AHB_BASE:
+ {
+ ulInt = INT_GPIOF;
+ break;
+ }
+
+ case GPIO_PORTG_BASE:
+ case GPIO_PORTG_AHB_BASE:
+ {
+ ulInt = INT_GPIOG;
+ break;
+ }
+
+ case GPIO_PORTH_BASE:
+ case GPIO_PORTH_AHB_BASE:
+ {
+ ulInt = INT_GPIOH;
+ break;
+ }
+
+ case GPIO_PORTJ_BASE:
+ case GPIO_PORTJ_AHB_BASE:
+ {
+ ulInt = INT_GPIOJ;
+ break;
+ }
+
+ default:
+ {
+ return(-1);
+ }
+ }
+
+ //
+ // Return GPIO interrupt number.
+ //
+ return(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Sets the direction and mode of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulPinIO is the pin direction and/or mode.
+//!
+//! This function will set the specified pin(s) on the selected GPIO port
+//! as either an input or output under software control, or it will set the
+//! pin to be under hardware control.
+//!
+//! The parameter \e ulPinIO is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_DIR_MODE_IN
+//! - \b GPIO_DIR_MODE_OUT
+//! - \b GPIO_DIR_MODE_HW
+//!
+//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
+//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
+//! will be programmed as a software controlled output, and
+//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under
+//! hardware control.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) ||
+ (ulPinIO == GPIO_DIR_MODE_HW));
+
+ //
+ // Set the pin direction and mode.
+ //
+ HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ?
+ (HWREG(ulPort + GPIO_O_DIR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ?
+ (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) :
+ (HWREG(ulPort + GPIO_O_AFSEL) &
+ ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the direction and mode of a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the direction and control mode for a specified pin on
+//! the selected GPIO port. The pin can be configured as either an input or
+//! output under software control, or it can be under hardware control. The
+//! type of control and direction are returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIODirModeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulDir, ulAFSEL;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = 1 << ucPin;
+
+ //
+ // Return the pin direction and mode.
+ //
+ ulDir = HWREG(ulPort + GPIO_O_DIR);
+ ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL);
+ return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the interrupt type for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulIntType specifies the type of interrupt trigger mechanism.
+//!
+//! This function sets up the various interrupt trigger mechanisms for the
+//! specified pin(s) on the selected GPIO port.
+//!
+//! The parameter \e ulIntType is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_FALLING_EDGE
+//! - \b GPIO_RISING_EDGE
+//! - \b GPIO_BOTH_EDGES
+//! - \b GPIO_LOW_LEVEL
+//! - \b GPIO_HIGH_LEVEL
+//!
+//! where the different values describe the interrupt detection mechanism
+//! (edge or level) and the particular triggering event (falling, rising,
+//! or both edges for edge detect, low or high for level detect).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note In order to avoid any spurious interrupts, the user must
+//! ensure that the GPIO inputs remain stable for the duration of
+//! this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
+ (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
+ (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
+
+ //
+ // Set the pin interrupt type.
+ //
+ HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ?
+ (HWREG(ulPort + GPIO_O_IBE) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ?
+ (HWREG(ulPort + GPIO_O_IS) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IS) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ?
+ (HWREG(ulPort + GPIO_O_IEV) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt type for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the interrupt type for a specified pin on the selected
+//! GPIO port. The pin can be configured as a falling edge, rising edge, or
+//! both edge detected interrupt, or it can be configured as a low level or
+//! high level detected interrupt. The type of interrupt detection mechanism
+//! is returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIOIntTypeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulIBE, ulIS, ulIEV;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = 1 << ucPin;
+
+ //
+ // Return the pin interrupt type.
+ //
+ ulIBE = HWREG(ulPort + GPIO_O_IBE);
+ ulIS = HWREG(ulPort + GPIO_O_IS);
+ ulIEV = HWREG(ulPort + GPIO_O_IEV);
+ return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
+ ((ulIEV & ucPin) ? 4 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the pad configuration for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulStrength specifies the output drive strength.
+//! \param ulPinType specifies the pin type.
+//!
+//! This function sets the drive strength and type for the specified pin(s)
+//! on the selected GPIO port. For pin(s) configured as input ports, the
+//! pad is configured as requested, but the only real effect on the input
+//! is the configuration of the pull-up or pull-down termination.
+//!
+//! The parameter \e ulStrength can be one of the following values:
+//!
+//! - \b GPIO_STRENGTH_2MA
+//! - \b GPIO_STRENGTH_4MA
+//! - \b GPIO_STRENGTH_8MA
+//! - \b GPIO_STRENGTH_8MA_SC
+//!
+//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive
+//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with
+//! slew control.
+//!
+//! The parameter \e ulPinType can be one of the following values:
+//!
+//! - \b GPIO_PIN_TYPE_STD
+//! - \b GPIO_PIN_TYPE_STD_WPU
+//! - \b GPIO_PIN_TYPE_STD_WPD
+//! - \b GPIO_PIN_TYPE_OD
+//! - \b GPIO_PIN_TYPE_OD_WPU
+//! - \b GPIO_PIN_TYPE_OD_WPD
+//! - \b GPIO_PIN_TYPE_ANALOG
+//!
+//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*
+//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD
+//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an
+//! analog input (for the comparators).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulStrength, unsigned long ulPinType)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulStrength == GPIO_STRENGTH_2MA) ||
+ (ulStrength == GPIO_STRENGTH_4MA) ||
+ (ulStrength == GPIO_STRENGTH_8MA) ||
+ (ulStrength == GPIO_STRENGTH_8MA_SC));
+ ASSERT((ulPinType == GPIO_PIN_TYPE_STD) ||
+ (ulPinType == GPIO_PIN_TYPE_STD_WPU) ||
+ (ulPinType == GPIO_PIN_TYPE_STD_WPD) ||
+ (ulPinType == GPIO_PIN_TYPE_OD) ||
+ (ulPinType == GPIO_PIN_TYPE_OD_WPU) ||
+ (ulPinType == GPIO_PIN_TYPE_OD_WPD) ||
+ (ulPinType == GPIO_PIN_TYPE_ANALOG))
+
+ //
+ // Set the output drive strength.
+ //
+ HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ?
+ (HWREG(ulPort + GPIO_O_DR2R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ?
+ (HWREG(ulPort + GPIO_O_DR4R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ?
+ (HWREG(ulPort + GPIO_O_DR8R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ?
+ (HWREG(ulPort + GPIO_O_SLR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins)));
+
+ //
+ // Set the pin type.
+ //
+ HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ?
+ (HWREG(ulPort + GPIO_O_ODR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ?
+ (HWREG(ulPort + GPIO_O_PUR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ?
+ (HWREG(ulPort + GPIO_O_PDR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ?
+ (HWREG(ulPort + GPIO_O_DEN) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins)));
+
+ //
+ // Set the analog mode select register. This register only appears in
+ // DustDevil-class (and later) devices, but is a harmless write on
+ // Sandstorm- and Fury-class devices.
+ //
+ HWREG(ulPort + GPIO_O_AMSEL) =
+ ((ulPinType == GPIO_PIN_TYPE_ANALOG) ?
+ (HWREG(ulPort + GPIO_O_AMSEL) | ucPins) :
+ (HWREG(ulPort + GPIO_O_AMSEL) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the pad configuration for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//! \param pulStrength is a pointer to storage for the output drive strength.
+//! \param pulPinType is a pointer to storage for the output drive type.
+//!
+//! This function gets the pad configuration for a specified pin on the
+//! selected GPIO port. The values returned in \e pulStrength and
+//! \e pulPinType correspond to the values used in GPIOPadConfigSet(). This
+//! function also works for pin(s) configured as input pin(s); however, the
+//! only meaningful data returned is whether the pin is terminated with a
+//! pull-up or down resistor.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
+ unsigned long *pulStrength, unsigned long *pulPinType)
+{
+ unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = (1 << ucPin);
+
+ //
+ // Get the drive strength for this pin.
+ //
+ ulTemp1 = HWREG(ulPort + GPIO_O_DR2R);
+ ulTemp2 = HWREG(ulPort + GPIO_O_DR4R);
+ ulTemp3 = HWREG(ulPort + GPIO_O_DR8R);
+ ulTemp4 = HWREG(ulPort + GPIO_O_SLR);
+ *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
+
+ //
+ // Get the pin type.
+ //
+ ulTemp1 = HWREG(ulPort + GPIO_O_ODR);
+ ulTemp2 = HWREG(ulPort + GPIO_O_PUR);
+ ulTemp3 = HWREG(ulPort + GPIO_O_PDR);
+ ulTemp4 = HWREG(ulPort + GPIO_O_DEN);
+ *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Unmasks the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Enable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_IM) |= ucPins;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Masks the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Disable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_IM) &= ~(ucPins);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns a bit-packed byte, where each bit that is set identifies
+//! an active masked or raw interrupt, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//! Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the interrupt status.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulPort + GPIO_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulPort + GPIO_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the interrupt for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Clears the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Clear the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_ICR) = ucPins;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
+//! function.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected from the selected
+//! GPIO port. This function will also enable the corresponding GPIO interrupt
+//! in the interrupt controller; individual pin interrupts and interrupt
+//! sources must be enabled with GPIOPinIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulPort, pfnIntHandler);
+
+ //
+ // Enable the GPIO interrupt.
+ //
+ IntEnable(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! GPIO port. This function will also disable the corresponding
+//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
+//! and interrupt sources must be disabled with GPIOPinIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPortIntUnregister(unsigned long ulPort)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Disable the GPIO interrupt.
+ //
+ IntDisable(ulPort);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Reads the values present of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The values at the specified pin(s) are read, as specified by \e ucPins.
+//! Values are returned for both input and output pin(s), and the value
+//! for pin(s) that are not specified by \e ucPins are set to 0.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return Returns a bit-packed byte providing the state of the specified
+//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
+//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
+//! is returned as a 0. Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the pin value(s).
+ //
+ return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ucVal is the value to write to the pin(s).
+//!
+//! Writes the corresponding bit values to the output pin(s) specified by
+//! \e ucPins. Writing to a pin configured as an input pin has no effect.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Write the pins.
+ //
+ HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal;
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as analog-to-digital converter inputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The analog-to-digital converter input pins must be properly configured
+//! to function correctly on DustDevil-class devices. This function provides
+//! the proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an ADC input; it only
+//! configures an ADC input pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as a CAN device.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The CAN pins must be properly configured for the CAN peripherals to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a CAN pin; it only
+//! configures a CAN pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an analog comparator input.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The analog comparator input pins must be properly configured for the analog
+//! comparator to function correctly. This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an analog comparator input;
+//! it only configures an analog comparator pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO inputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO inputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO outputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be outputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO open drain outputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be outputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the I2C peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The I2C pins must be properly configured for the I2C peripheral to function
+//! correctly. This function provides the proper configuration for those
+//! pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an I2C pin; it only
+//! configures an I2C pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for open-drain operation with a weak pull-up.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the PWM peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The PWM pins must be properly configured for the PWM peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a PWM pin; it only
+//! configures a PWM pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the QEI peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The QEI pins must be properly configured for the QEI peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, not using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a QEI pin; it only
+//! configures a QEI pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation with a weak pull-up.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the SSI peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The SSI pins must be properly configured for the SSI peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a SSI pin; it only
+//! configures a SSI pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Timer peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The CCP pins must be properly configured for the timer peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a timer pin; it only
+//! configures a timer pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the UART peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The UART pins must be properly configured for the UART peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a UART pin; it only
+//! configures a UART pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some USB digital pins must be properly configured for the USB peripheral to
+//! function correctly. This function provides a typical configuration for
+//! the digital USB pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some USB analog pins must be properly configured for the USB peripheral to
+//! function correctly. This function provides the proper configuration for
+//! those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the I2S peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some I2S pins must be properly configured for the I2S peripheral to
+//! function correctly. This function provides a typical configuration for
+//! the digital I2S pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a I2S pin; it only
+//! configures a I2S pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures the alternate function of a GPIO pin.
+//!
+//! \param ulPinConfig is the pin configuration value, specified as one of the
+//! \b GPIO_P??_??? values.
+//!
+//! This function configures the pin mux that selects the peripheral function
+//! associated with a particular GPIO pin. Only one peripheral function at a
+//! time can be associated with a GPIO pin, and each peripheral function should
+//! only be associated with a single GPIO pin at a time (despite the fact that
+//! many of them can be associated with more than one GPIO pin).
+//!
+//! \note This function is only valid on Tempest-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinConfigure(unsigned long ulPinConfig)
+{
+ unsigned long ulBase, ulShift;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(((ulPinConfig >> 16) & 0xff) < 9);
+ ASSERT(((ulPinConfig >> 8) & 0xe3) == 0);
+
+ //
+ // Extract the base address index from the input value.
+ //
+ ulBase = (ulPinConfig >> 16) & 0xff;
+
+ //
+ // Get the base address of the GPIO module, selecting either the APB or the
+ // AHB aperture as appropriate.
+ //
+ if(HWREG(SYSCTL_GPIOHSCTL) & (1 << ulBase))
+ {
+ ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1];
+ }
+ else
+ {
+ ulBase = g_pulGPIOBaseAddrs[ulBase << 1];
+ }
+
+ //
+ // Extract the shift from the input value.
+ //
+ ulShift = (ulPinConfig >> 8) & 0xff;
+
+ //
+ // Write the requested pin muxing value for this GPIO pin.
+ //
+ HWREG(ulBase + GPIO_O_PCTL) = ((HWREG(ulBase + GPIO_O_PCTL) &
+ ~(0xf << ulShift)) |
+ ((ulPinConfig & 0xf) << ulShift));
+
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/gpio.h b/bsp/lm3s/Libraries/driverlib/gpio.h new file mode 100644 index 0000000000..08b594ff55 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/gpio.h @@ -0,0 +1,768 @@ +//*****************************************************************************
+//
+// gpio.h - Defines and Macros for GPIO API.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ucPins argument to several
+// of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
+// returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.
+//
+//*****************************************************************************
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.
+//
+//*****************************************************************************
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter.
+//
+//*****************************************************************************
+//
+// GPIO pin A0
+//
+#define GPIO_PA0_U0RX 0x00000001
+#define GPIO_PA0_I2C1SCL 0x00000008
+#define GPIO_PA0_U1RX 0x00000009
+
+//
+// GPIO pin A1
+//
+#define GPIO_PA1_U0TX 0x00000401
+#define GPIO_PA1_I2C1SDA 0x00000408
+#define GPIO_PA1_U1TX 0x00000409
+
+//
+// GPIO pin A2
+//
+#define GPIO_PA2_SSI0CLK 0x00000801
+#define GPIO_PA2_PWM4 0x00000804
+#define GPIO_PA2_I2S0RXSD 0x00000809
+
+//
+// GPIO pin A3
+//
+#define GPIO_PA3_SSI0FSS 0x00000c01
+#define GPIO_PA3_PWM5 0x00000c04
+#define GPIO_PA3_I2S0RXMCLK 0x00000c09
+
+//
+// GPIO pin A4
+//
+#define GPIO_PA4_SSI0RX 0x00001001
+#define GPIO_PA4_PWM6 0x00001004
+#define GPIO_PA4_CAN0RX 0x00001005
+#define GPIO_PA4_I2S0TXSCK 0x00001009
+
+//
+// GPIO pin A5
+//
+#define GPIO_PA5_SSI0TX 0x00001401
+#define GPIO_PA5_PWM7 0x00001404
+#define GPIO_PA5_CAN0TX 0x00001405
+#define GPIO_PA5_I2S0TXWS 0x00001409
+
+//
+// GPIO pin A6
+//
+#define GPIO_PA6_I2C1SCL 0x00001801
+#define GPIO_PA6_CCP1 0x00001802
+#define GPIO_PA6_PWM0 0x00001804
+#define GPIO_PA6_PWM4 0x00001805
+#define GPIO_PA6_CAN0RX 0x00001806
+#define GPIO_PA6_USB0EPEN 0x00001808
+#define GPIO_PA6_U1CTS 0x00001809
+
+//
+// GPIO pin A7
+//
+#define GPIO_PA7_I2C1SDA 0x00001c01
+#define GPIO_PA7_CCP4 0x00001c02
+#define GPIO_PA7_PWM1 0x00001c04
+#define GPIO_PA7_PWM5 0x00001c05
+#define GPIO_PA7_CAN0TX 0x00001c06
+#define GPIO_PA7_CCP3 0x00001c07
+#define GPIO_PA7_USB0PFLT 0x00001c08
+#define GPIO_PA7_U1DCD 0x00001c09
+
+//
+// GPIO pin B0
+//
+#define GPIO_PB0_CCP0 0x00010001
+#define GPIO_PB0_PWM2 0x00010002
+#define GPIO_PB0_U1RX 0x00010005
+
+//
+// GPIO pin B1
+//
+#define GPIO_PB1_CCP2 0x00010401
+#define GPIO_PB1_PWM3 0x00010402
+#define GPIO_PB1_CCP1 0x00010404
+#define GPIO_PB1_U1TX 0x00010405
+
+//
+// GPIO pin B2
+//
+#define GPIO_PB2_I2C0SCL 0x00010801
+#define GPIO_PB2_IDX0 0x00010802
+#define GPIO_PB2_CCP3 0x00010804
+#define GPIO_PB2_CCP0 0x00010805
+#define GPIO_PB2_USB0EPEN 0x00010808
+
+//
+// GPIO pin B3
+//
+#define GPIO_PB3_I2C0SDA 0x00010c01
+#define GPIO_PB3_FAULT0 0x00010c02
+#define GPIO_PB3_FAULT3 0x00010c04
+#define GPIO_PB3_USB0PFLT 0x00010c08
+
+//
+// GPIO pin B4
+//
+#define GPIO_PB4_U2RX 0x00011004
+#define GPIO_PB4_CAN0RX 0x00011005
+#define GPIO_PB4_IDX0 0x00011006
+#define GPIO_PB4_U1RX 0x00011007
+#define GPIO_PB4_EPI0S23 0x00011008
+
+//
+// GPIO pin B5
+//
+#define GPIO_PB5_C0O 0x00011401
+#define GPIO_PB5_CCP5 0x00011402
+#define GPIO_PB5_CCP6 0x00011403
+#define GPIO_PB5_CCP0 0x00011404
+#define GPIO_PB5_CAN0TX 0x00011405
+#define GPIO_PB5_CCP2 0x00011406
+#define GPIO_PB5_U1TX 0x00011407
+#define GPIO_PB5_EPI0S22 0x00011408
+
+//
+// GPIO pin B6
+//
+#define GPIO_PB6_CCP1 0x00011801
+#define GPIO_PB6_CCP7 0x00011802
+#define GPIO_PB6_C0O 0x00011803
+#define GPIO_PB6_FAULT1 0x00011804
+#define GPIO_PB6_IDX0 0x00011805
+#define GPIO_PB6_CCP5 0x00011806
+#define GPIO_PB6_I2S0TXSCK 0x00011809
+
+//
+// GPIO pin B7
+//
+#define GPIO_PB7_NMI 0x00011c04
+
+//
+// GPIO pin C0
+//
+#define GPIO_PC0_TCK 0x00020003
+
+//
+// GPIO pin C1
+//
+#define GPIO_PC1_TMS 0x00020403
+
+//
+// GPIO pin C2
+//
+#define GPIO_PC2_TDI 0x00020803
+
+//
+// GPIO pin C3
+//
+#define GPIO_PC3_TDO 0x00020c03
+
+//
+// GPIO pin C4
+//
+#define GPIO_PC4_CCP5 0x00021001
+#define GPIO_PC4_PHA0 0x00021002
+#define GPIO_PC4_PWM6 0x00021004
+#define GPIO_PC4_CCP2 0x00021005
+#define GPIO_PC4_CCP4 0x00021006
+#define GPIO_PC4_EPI0S2 0x00021008
+#define GPIO_PC4_CCP1 0x00021009
+
+//
+// GPIO pin C5
+//
+#define GPIO_PC5_CCP1 0x00021401
+#define GPIO_PC5_C1O 0x00021402
+#define GPIO_PC5_C0O 0x00021403
+#define GPIO_PC5_FAULT2 0x00021404
+#define GPIO_PC5_CCP3 0x00021405
+#define GPIO_PC5_USB0EPEN 0x00021406
+#define GPIO_PC5_EPI0S3 0x00021408
+
+//
+// GPIO pin C6
+//
+#define GPIO_PC6_CCP3 0x00021801
+#define GPIO_PC6_PHB0 0x00021802
+#define GPIO_PC6_C2O 0x00021803
+#define GPIO_PC6_PWM7 0x00021804
+#define GPIO_PC6_U1RX 0x00021805
+#define GPIO_PC6_CCP0 0x00021806
+#define GPIO_PC6_USB0PFLT 0x00021807
+#define GPIO_PC6_EPI0S4 0x00021808
+
+//
+// GPIO pin C7
+//
+#define GPIO_PC7_CCP4 0x00021c01
+#define GPIO_PC7_PHB0 0x00021c02
+#define GPIO_PC7_CCP0 0x00021c04
+#define GPIO_PC7_U1TX 0x00021c05
+#define GPIO_PC7_USB0PFLT 0x00021c06
+#define GPIO_PC7_C1O 0x00021c07
+#define GPIO_PC7_EPI0S5 0x00021c08
+
+//
+// GPIO pin D0
+//
+#define GPIO_PD0_PWM0 0x00030001
+#define GPIO_PD0_CAN0RX 0x00030002
+#define GPIO_PD0_IDX0 0x00030003
+#define GPIO_PD0_U2RX 0x00030004
+#define GPIO_PD0_U1RX 0x00030005
+#define GPIO_PD0_CCP6 0x00030006
+#define GPIO_PD0_I2S0RXSCK 0x00030008
+#define GPIO_PD0_U1CTS 0x00030009
+
+//
+// GPIO pin D1
+//
+#define GPIO_PD1_PWM1 0x00030401
+#define GPIO_PD1_CAN0TX 0x00030402
+#define GPIO_PD1_PHA0 0x00030403
+#define GPIO_PD1_U2TX 0x00030404
+#define GPIO_PD1_U1TX 0x00030405
+#define GPIO_PD1_CCP7 0x00030406
+#define GPIO_PD1_I2S0RXWS 0x00030408
+#define GPIO_PD1_U1DCD 0x00030409
+#define GPIO_PD1_CCP2 0x0003040a
+#define GPIO_PD1_PHB1 0x0003040b
+
+//
+// GPIO pin D2
+//
+#define GPIO_PD2_U1RX 0x00030801
+#define GPIO_PD2_CCP6 0x00030802
+#define GPIO_PD2_PWM2 0x00030803
+#define GPIO_PD2_CCP5 0x00030804
+#define GPIO_PD2_EPI0S20 0x00030808
+
+//
+// GPIO pin D3
+//
+#define GPIO_PD3_U1TX 0x00030c01
+#define GPIO_PD3_CCP7 0x00030c02
+#define GPIO_PD3_PWM3 0x00030c03
+#define GPIO_PD3_CCP0 0x00030c04
+#define GPIO_PD3_EPI0S21 0x00030c08
+
+//
+// GPIO pin D4
+//
+#define GPIO_PD4_CCP0 0x00031001
+#define GPIO_PD4_CCP3 0x00031002
+#define GPIO_PD4_I2S0RXSD 0x00031008
+#define GPIO_PD4_U1RI 0x00031009
+#define GPIO_PD4_EPI0S19 0x0003100a
+
+//
+// GPIO pin D5
+//
+#define GPIO_PD5_CCP2 0x00031401
+#define GPIO_PD5_CCP4 0x00031402
+#define GPIO_PD5_I2S0RXMCLK 0x00031408
+#define GPIO_PD5_U2RX 0x00031409
+#define GPIO_PD5_EPI0S28 0x0003140a
+
+//
+// GPIO pin D6
+//
+#define GPIO_PD6_FAULT0 0x00031801
+#define GPIO_PD6_I2S0TXSCK 0x00031808
+#define GPIO_PD6_U2TX 0x00031809
+#define GPIO_PD6_EPI0S29 0x0003180a
+
+//
+// GPIO pin D7
+//
+#define GPIO_PD7_IDX0 0x00031c01
+#define GPIO_PD7_C0O 0x00031c02
+#define GPIO_PD7_CCP1 0x00031c03
+#define GPIO_PD7_I2S0TXWS 0x00031c08
+#define GPIO_PD7_U1DTR 0x00031c09
+#define GPIO_PD7_EPI0S30 0x00031c0a
+
+//
+// GPIO pin E0
+//
+#define GPIO_PE0_PWM4 0x00040001
+#define GPIO_PE0_SSI1CLK 0x00040002
+#define GPIO_PE0_CCP3 0x00040003
+#define GPIO_PE0_EPI0S8 0x00040008
+#define GPIO_PE0_USB0PFLT 0x00040009
+
+//
+// GPIO pin E1
+//
+#define GPIO_PE1_PWM5 0x00040401
+#define GPIO_PE1_SSI1FSS 0x00040402
+#define GPIO_PE1_FAULT0 0x00040403
+#define GPIO_PE1_CCP2 0x00040404
+#define GPIO_PE1_CCP6 0x00040405
+#define GPIO_PE1_EPI0S9 0x00040408
+
+//
+// GPIO pin E2
+//
+#define GPIO_PE2_CCP4 0x00040801
+#define GPIO_PE2_SSI1RX 0x00040802
+#define GPIO_PE2_PHB1 0x00040803
+#define GPIO_PE2_PHA0 0x00040804
+#define GPIO_PE2_CCP2 0x00040805
+#define GPIO_PE2_EPI0S24 0x00040808
+
+//
+// GPIO pin E3
+//
+#define GPIO_PE3_CCP1 0x00040c01
+#define GPIO_PE3_SSI1TX 0x00040c02
+#define GPIO_PE3_PHA1 0x00040c03
+#define GPIO_PE3_PHB0 0x00040c04
+#define GPIO_PE3_CCP7 0x00040c05
+#define GPIO_PE3_EPI0S25 0x00040c08
+
+//
+// GPIO pin E4
+//
+#define GPIO_PE4_CCP3 0x00041001
+#define GPIO_PE4_FAULT0 0x00041004
+#define GPIO_PE4_U2TX 0x00041005
+#define GPIO_PE4_CCP2 0x00041006
+#define GPIO_PE4_I2S0TXWS 0x00041009
+
+//
+// GPIO pin E5
+//
+#define GPIO_PE5_CCP5 0x00041401
+#define GPIO_PE5_I2S0TXSD 0x00041409
+
+//
+// GPIO pin E6
+//
+#define GPIO_PE6_PWM4 0x00041801
+#define GPIO_PE6_C1O 0x00041802
+#define GPIO_PE6_U1CTS 0x00041809
+
+//
+// GPIO pin E7
+//
+#define GPIO_PE7_PWM5 0x00041c01
+#define GPIO_PE7_C2O 0x00041c02
+#define GPIO_PE7_U1DCD 0x00041c09
+
+//
+// GPIO pin F0
+//
+#define GPIO_PF0_CAN1RX 0x00050001
+#define GPIO_PF0_PHB0 0x00050002
+#define GPIO_PF0_PWM0 0x00050003
+#define GPIO_PF0_I2S0TXSD 0x00050008
+#define GPIO_PF0_U1DSR 0x00050009
+
+//
+// GPIO pin F1
+//
+#define GPIO_PF1_CAN1TX 0x00050401
+#define GPIO_PF1_IDX1 0x00050402
+#define GPIO_PF1_PWM1 0x00050403
+#define GPIO_PF1_I2S0TXMCLK 0x00050408
+#define GPIO_PF1_U1RTS 0x00050409
+#define GPIO_PF1_CCP3 0x0005040a
+
+//
+// GPIO pin F2
+//
+#define GPIO_PF2_LED1 0x00050801
+#define GPIO_PF2_PWM4 0x00050802
+#define GPIO_PF2_PWM2 0x00050804
+#define GPIO_PF2_SSI1CLK 0x00050809
+
+//
+// GPIO pin F3
+//
+#define GPIO_PF3_LED0 0x00050c01
+#define GPIO_PF3_PWM5 0x00050c02
+#define GPIO_PF3_PWM3 0x00050c04
+#define GPIO_PF3_SSI1FSS 0x00050c09
+
+//
+// GPIO pin F4
+//
+#define GPIO_PF4_CCP0 0x00051001
+#define GPIO_PF4_C0O 0x00051002
+#define GPIO_PF4_FAULT0 0x00051004
+#define GPIO_PF4_EPI0S12 0x00051008
+#define GPIO_PF4_SSI1RX 0x00051009
+
+//
+// GPIO pin F5
+//
+#define GPIO_PF5_CCP2 0x00051401
+#define GPIO_PF5_C1O 0x00051402
+#define GPIO_PF5_EPI0S15 0x00051408
+#define GPIO_PF5_SSI1TX 0x00051409
+
+//
+// GPIO pin F6
+//
+#define GPIO_PF6_CCP1 0x00051801
+#define GPIO_PF6_C2O 0x00051802
+#define GPIO_PF6_PHA0 0x00051804
+#define GPIO_PF6_I2S0TXMCLK 0x00051809
+#define GPIO_PF6_U1RTS 0x0005180a
+
+//
+// GPIO pin F7
+//
+#define GPIO_PF7_CCP4 0x00051c01
+#define GPIO_PF7_PHB0 0x00051c04
+#define GPIO_PF7_EPI0S12 0x00051c08
+#define GPIO_PF7_FAULT1 0x00051c09
+
+//
+// GPIO pin G0
+//
+#define GPIO_PG0_U2RX 0x00060001
+#define GPIO_PG0_PWM0 0x00060002
+#define GPIO_PG0_I2C1SCL 0x00060003
+#define GPIO_PG0_PWM4 0x00060004
+#define GPIO_PG0_USB0EPEN 0x00060007
+#define GPIO_PG0_EPI0S13 0x00060008
+
+//
+// GPIO pin G1
+//
+#define GPIO_PG1_U2TX 0x00060401
+#define GPIO_PG1_PWM1 0x00060402
+#define GPIO_PG1_I2C1SDA 0x00060403
+#define GPIO_PG1_PWM5 0x00060404
+#define GPIO_PG1_EPI0S14 0x00060408
+
+//
+// GPIO pin G2
+//
+#define GPIO_PG2_PWM0 0x00060801
+#define GPIO_PG2_FAULT0 0x00060804
+#define GPIO_PG2_IDX1 0x00060808
+#define GPIO_PG2_I2S0RXSD 0x00060809
+
+//
+// GPIO pin G3
+//
+#define GPIO_PG3_PWM1 0x00060c01
+#define GPIO_PG3_FAULT2 0x00060c04
+#define GPIO_PG3_FAULT0 0x00060c08
+#define GPIO_PG3_I2S0RXMCLK 0x00060c09
+
+//
+// GPIO pin G4
+//
+#define GPIO_PG4_CCP3 0x00061001
+#define GPIO_PG4_FAULT1 0x00061004
+#define GPIO_PG4_EPI0S15 0x00061008
+#define GPIO_PG4_PWM6 0x00061009
+#define GPIO_PG4_U1RI 0x0006100a
+
+//
+// GPIO pin G5
+//
+#define GPIO_PG5_CCP5 0x00061401
+#define GPIO_PG5_IDX0 0x00061404
+#define GPIO_PG5_FAULT1 0x00061405
+#define GPIO_PG5_PWM7 0x00061408
+#define GPIO_PG5_I2S0RXSCK 0x00061409
+#define GPIO_PG5_U1DTR 0x0006140a
+
+//
+// GPIO pin G6
+//
+#define GPIO_PG6_PHA1 0x00061801
+#define GPIO_PG6_PWM6 0x00061804
+#define GPIO_PG6_FAULT1 0x00061808
+#define GPIO_PG6_I2S0RXWS 0x00061809
+#define GPIO_PG6_U1RI 0x0006180a
+
+//
+// GPIO pin G7
+//
+#define GPIO_PG7_PHB1 0x00061c01
+#define GPIO_PG7_PWM7 0x00061c04
+#define GPIO_PG7_CCP5 0x00061c08
+#define GPIO_PG7_EPI0S31 0x00061c09
+
+//
+// GPIO pin H0
+//
+#define GPIO_PH0_CCP6 0x00070001
+#define GPIO_PH0_PWM2 0x00070002
+#define GPIO_PH0_EPI0S6 0x00070008
+#define GPIO_PH0_PWM4 0x00070009
+
+//
+// GPIO pin H1
+//
+#define GPIO_PH1_CCP7 0x00070401
+#define GPIO_PH1_PWM3 0x00070402
+#define GPIO_PH1_EPI0S7 0x00070408
+#define GPIO_PH1_PWM5 0x00070409
+
+//
+// GPIO pin H2
+//
+#define GPIO_PH2_IDX1 0x00070801
+#define GPIO_PH2_C1O 0x00070802
+#define GPIO_PH2_FAULT3 0x00070804
+#define GPIO_PH2_EPI0S1 0x00070808
+
+//
+// GPIO pin H3
+//
+#define GPIO_PH3_PHB0 0x00070c01
+#define GPIO_PH3_FAULT0 0x00070c02
+#define GPIO_PH3_USB0EPEN 0x00070c04
+#define GPIO_PH3_EPI0S0 0x00070c08
+
+//
+// GPIO pin H4
+//
+#define GPIO_PH4_USB0PFLT 0x00071004
+#define GPIO_PH4_EPI0S10 0x00071008
+#define GPIO_PH4_SSI1CLK 0x0007100b
+
+//
+// GPIO pin H5
+//
+#define GPIO_PH5_EPI0S11 0x00071408
+#define GPIO_PH5_FAULT2 0x0007140a
+#define GPIO_PH5_SSI1FSS 0x0007140b
+
+//
+// GPIO pin H6
+//
+#define GPIO_PH6_EPI0S26 0x00071808
+#define GPIO_PH6_PWM4 0x0007180a
+#define GPIO_PH6_SSI1RX 0x0007180b
+
+//
+// GPIO pin H7
+//
+#define GPIO_PH7_EPI0S27 0x00071c08
+#define GPIO_PH7_PWM5 0x00071c0a
+#define GPIO_PH7_SSI1TX 0x00071c0b
+
+//
+// GPIO pin J0
+//
+#define GPIO_PJ0_EPI0S16 0x00080008
+#define GPIO_PJ0_PWM0 0x0008000a
+#define GPIO_PJ0_I2C1SCL 0x0008000b
+
+//
+// GPIO pin J1
+//
+#define GPIO_PJ1_EPI0S17 0x00080408
+#define GPIO_PJ1_USB0PFLT 0x00080409
+#define GPIO_PJ1_PWM1 0x0008040a
+#define GPIO_PJ1_I2C1SDA 0x0008040b
+
+//
+// GPIO pin J2
+//
+#define GPIO_PJ2_EPI0S18 0x00080808
+#define GPIO_PJ2_CCP0 0x00080809
+#define GPIO_PJ2_FAULT0 0x0008080a
+
+//
+// GPIO pin J3
+//
+#define GPIO_PJ3_EPI0S19 0x00080c08
+#define GPIO_PJ3_U1CTS 0x00080c09
+#define GPIO_PJ3_CCP6 0x00080c0a
+
+//
+// GPIO pin J4
+//
+#define GPIO_PJ4_EPI0S28 0x00081008
+#define GPIO_PJ4_U1DCD 0x00081009
+#define GPIO_PJ4_CCP4 0x0008100a
+
+//
+// GPIO pin J5
+//
+#define GPIO_PJ5_EPI0S29 0x00081408
+#define GPIO_PJ5_U1DSR 0x00081409
+#define GPIO_PJ5_CCP2 0x0008140a
+
+//
+// GPIO pin J6
+//
+#define GPIO_PJ6_EPI0S30 0x00081808
+#define GPIO_PJ6_U1RTS 0x00081809
+#define GPIO_PJ6_CCP1 0x0008180a
+
+//
+// GPIO pin J7
+//
+#define GPIO_PJ7_U1DTR 0x00081c09
+#define GPIO_PJ7_CCP0 0x00081c0a
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO);
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType);
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulStrength,
+ unsigned long ulPadType);
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
+ unsigned long *pulStrength,
+ unsigned long *pulPadType);
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPortIntRegister(unsigned long ulPort,
+ void (*pfnIntHandler)(void));
+extern void GPIOPortIntUnregister(unsigned long ulPort);
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
+ unsigned char ucVal);
+extern void GPIOPinConfigure(unsigned long ulPinConfig);
+extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
+ unsigned char ucPins);
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPIO_H__
diff --git a/bsp/lm3s/Libraries/driverlib/hibernate.c b/bsp/lm3s/Libraries/driverlib/hibernate.c new file mode 100644 index 0000000000..b2ff21b82e --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/hibernate.c @@ -0,0 +1,965 @@ +//*****************************************************************************
+//
+// hibernate.c - Driver for the Hibernation module
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup hibernate_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_hibernate.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/hibernate.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// The delay in microseconds for writing to the Hibernation module registers.
+//
+//*****************************************************************************
+#define DELAY_USECS 95
+
+//*****************************************************************************
+//
+// The number of processor cycles to execute one pass of the delay loop.
+//
+//*****************************************************************************
+#define LOOP_CYCLES 3
+
+//*****************************************************************************
+//
+// The calculated number of delay loops to achieve the write delay.
+//
+//*****************************************************************************
+static unsigned long g_ulWriteDelay;
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Polls until the write complete (WRC) bit in the hibernate control register
+//! is set.
+//!
+//! \param None.
+//!
+//! On non-Fury-class devices, the hibernate module provides an indication when
+//! any write is completed. This is used to pace writes to the module. This
+//! function merely polls this bit and returns as soon as it is set. At this
+//! point, it is safe to perform another write to the module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateWriteComplete(void)
+{
+ //
+ // Spin until the write complete bit is set.
+ //
+ while(!(HWREG(HIB_CTL) & HIB_CTL_WRC))
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the Hibernation module for operation.
+//!
+//! \param ulHibClk is the rate of the clock supplied to the Hibernation
+//! module.
+//!
+//! Enables the Hibernation module for operation. This function should be
+//! called before any of the Hibernation module features are used.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original HibernateEnable() API and performs the
+//! same actions. A macro is provided in <tt>hibernate.h</tt> to map the
+//! original API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateEnableExpClk(unsigned long ulHibClk)
+{
+ //
+ // Turn on the clock enable bit.
+ //
+ HWREG(HIB_CTL) |= HIB_CTL_CLK32EN;
+
+ //
+ // For Fury-class devices, compute the number of delay loops that must be
+ // used to achieve the desired delay for writes to the hibernation
+ // registers. This value will be used in calls to SysCtlDelay().
+ //
+ if(CLASS_IS_FURY)
+ {
+ g_ulWriteDelay = (((ulHibClk / 1000) * DELAY_USECS) /
+ (1000L * LOOP_CYCLES));
+ g_ulWriteDelay++;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables the Hibernation module for operation.
+//!
+//! Disables the Hibernation module for operation. After this function is
+//! called, none of the Hibernation module features are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDisable(void)
+{
+ //
+ // Turn off the clock enable bit.
+ //
+ HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN;
+}
+
+//*****************************************************************************
+//
+//! Selects the clock input for the Hibernation module.
+//!
+//! \param ulClockInput specifies the clock input.
+//!
+//! Configures the clock input for the Hibernation module. The configuration
+//! option chosen depends entirely on hardware design. The clock input for the
+//! module will either be a 32.768 kHz oscillator or a 4.194304 MHz crystal.
+//! The \e ulClockFlags parameter must be one of the following:
+//!
+//! - \b HIBERNATE_CLOCK_SEL_RAW - use the raw signal from a 32.768 kHz
+//! oscillator.
+//! - \b HIBERNATE_CLOCK_SEL_DIV128 - use the crystal input, divided by 128.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateClockSelect(unsigned long ulClockInput)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulClockInput == HIBERNATE_CLOCK_SEL_RAW) ||
+ (ulClockInput == HIBERNATE_CLOCK_SEL_DIV128));
+
+ //
+ // Set the clock selection bit according to the parameter.
+ //
+ HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL);
+}
+
+//*****************************************************************************
+//
+//! Enables the RTC feature of the Hibernation module.
+//!
+//! Enables the RTC in the Hibernation module. The RTC can be used to wake the
+//! processor from hibernation at a certain time, or to generate interrupts at
+//! certain times. This function must be called before using any of the RTC
+//! features of the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCEnable(void)
+{
+ //
+ // Turn on the RTC enable bit.
+ //
+ HWREG(HIB_CTL) |= HIB_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the RTC feature of the Hibernation module.
+//!
+//! Disables the RTC in the Hibernation module. After calling this function
+//! the RTC features of the Hibernation module will not be available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCDisable(void)
+{
+ //
+ // Turn off the RTC enable bit.
+ //
+ HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Configures the wake conditions for the Hibernation module.
+//!
+//! \param ulWakeFlags specifies which conditions should be used for waking.
+//!
+//! Enables the conditions under which the Hibernation module will wake. The
+//! \e ulWakeFlags parameter is the logical OR of any combination of the
+//! following:
+//!
+//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted.
+//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateWakeSet(unsigned long ulWakeFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulWakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)));
+
+ //
+ // Set the specified wake flags in the control register.
+ //
+ HWREG(HIB_CTL) = (ulWakeFlags |
+ (HWREG(HIB_CTL) &
+ ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)));
+}
+
+//*****************************************************************************
+//
+//! Gets the currently configured wake conditions for the Hibernation module.
+//!
+//! Returns the flags representing the wake configuration for the Hibernation
+//! module. The return value will be a combination of the following flags:
+//!
+//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted.
+//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs.
+//!
+//! \return Returns flags indicating the configured wake conditions.
+//
+//*****************************************************************************
+unsigned long
+HibernateWakeGet(void)
+{
+ //
+ // Read the wake bits from the control register and return
+ // those bits to the caller.
+ //
+ return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC));
+}
+
+//*****************************************************************************
+//
+//! Configures the low battery detection.
+//!
+//! \param ulLowBatFlags specifies behavior of low battery detection.
+//!
+//! Enables the low battery detection and whether hibernation is allowed if a
+//! low battery is detected. If low battery detection is enabled, then a low
+//! battery condition will be indicated in the raw interrupt status register,
+//! and can also trigger an interrupt. Optionally, hibernation can be aborted
+//! if a low battery is detected.
+//!
+//! The \e ulLowBatFlags parameter is one of the following values:
+//!
+//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition.
+//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort
+//! hibernation if low battery is detected.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateLowBatSet(unsigned long ulLowBatFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulLowBatFlags == HIBERNATE_LOW_BAT_DETECT) ||
+ (ulLowBatFlags == HIBERNATE_LOW_BAT_ABORT));
+
+ //
+ // Set the low battery detect and abort bits in the control register,
+ // according to the parameter.
+ //
+ HWREG(HIB_CTL) = (ulLowBatFlags |
+ (HWREG(HIB_CTL) & ~HIBERNATE_LOW_BAT_ABORT));
+}
+
+//*****************************************************************************
+//
+//! Gets the currently configured low battery detection behavior.
+//!
+//! Returns a value representing the currently configured low battery detection
+//! behavior. The return value will be one of the following:
+//!
+//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition.
+//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort
+//! hibernation if low battery is detected.
+//!
+//! \return Returns a value indicating the configured low battery detection.
+//
+//*****************************************************************************
+unsigned long
+HibernateLowBatGet(void)
+{
+ //
+ // Read the low bat bits from the control register and return those bits to
+ // the caller.
+ //
+ return(HWREG(HIB_CTL) & HIBERNATE_LOW_BAT_ABORT);
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the real time clock (RTC) counter.
+//!
+//! \param ulRTCValue is the new value for the RTC.
+//!
+//! Sets the value of the RTC. The RTC will count seconds if the hardware is
+//! configured correctly. The RTC must be enabled by calling
+//! HibernateRTCEnable() before calling this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCSet(unsigned long ulRTCValue)
+{
+ //
+ // Write the new RTC value to the RTC load register.
+ //
+ HWREG(HIB_RTCLD) = ulRTCValue;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the real time clock (RTC) counter.
+//!
+//! Gets the value of the RTC and returns it to the caller.
+//!
+//! \return Returns the value of the RTC.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCGet(void)
+{
+ //
+ // Return the value of the RTC counter register to the caller.
+ //
+ return(HWREG(HIB_RTCC));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC match 0 register.
+//!
+//! \param ulMatch is the value for the match register.
+//!
+//! Sets the match 0 register for the RTC. The Hibernation module can be
+//! configured to wake from hibernation, and/or generate an interrupt when the
+//! value of the RTC counter is the same as the match register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCMatch0Set(unsigned long ulMatch)
+{
+ //
+ // Write the new match value to the match register.
+ //
+ HWREG(HIB_RTCM0) = ulMatch;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the RTC match 0 register.
+//!
+//! Gets the value of the match 0 register for the RTC.
+//!
+//! \return Returns the value of the match register.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCMatch0Get(void)
+{
+ //
+ // Return the value of the match register to the caller.
+ //
+ return(HWREG(HIB_RTCM0));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC match 1 register.
+//!
+//! \param ulMatch is the value for the match register.
+//!
+//! Sets the match 1 register for the RTC. The Hibernation module can be
+//! configured to wake from hibernation, and/or generate an interrupt when the
+//! value of the RTC counter is the same as the match register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCMatch1Set(unsigned long ulMatch)
+{
+ //
+ // Write the new match value to the match register.
+ //
+ HWREG(HIB_RTCM1) = ulMatch;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the RTC match 1 register.
+//!
+//! Gets the value of the match 1 register for the RTC.
+//!
+//! \return Returns the value of the match register.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCMatch1Get(void)
+{
+ //
+ // Return the value of the match register to the caller.
+ //
+ return(HWREG(HIB_RTCM1));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC predivider trim register.
+//!
+//! \param ulTrim is the new value for the pre-divider trim register.
+//!
+//! Sets the value of the pre-divider trim register. The input time source is
+//! divided by the pre-divider to achieve a one-second clock rate. Once every
+//! 64 seconds, the value of the pre-divider trim register is applied to the
+//! predivider to allow fine-tuning of the RTC rate, in order to make
+//! corrections to the rate. The software application can make adjustments to
+//! the predivider trim register to account for variations in the accuracy of
+//! the input time source. The nominal value is 0x7FFF, and it can be adjusted
+//! up or down in order to fine-tune the RTC rate.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCTrimSet(unsigned long ulTrim)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulTrim < 0x10000);
+
+ //
+ // Write the new trim value to the trim register.
+ //
+ HWREG(HIB_RTCT) = ulTrim;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the RTC predivider trim register.
+//!
+//! Gets the value of the pre-divider trim register. This function can be used
+//! to get the current value of the trim register prior to making an adjustment
+//! by using the HibernateRTCTrimSet() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCTrimGet(void)
+{
+ //
+ // Return the value of the trim register to the caller.
+ //
+ return(HWREG(HIB_RTCT));
+}
+
+//*****************************************************************************
+//
+//! Stores data in the non-volatile memory of the Hibernation module.
+//!
+//! \param pulData points to the data that the caller wants to store in the
+//! memory of the Hibernation module.
+//! \param ulCount is the count of 32-bit words to store.
+//!
+//! Stores a set of data in the Hibernation module non-volatile memory. This
+//! memory will be preserved when the power to the processor is turned off, and
+//! can be used to store application state information which will be available
+//! when the processor wakes. Up to 64 32-bit words can be stored in the
+//! non-volatile memory. The data can be restored by calling the
+//! HibernateDataGet() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDataSet(unsigned long *pulData, unsigned long ulCount)
+{
+ unsigned int uIdx;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulCount <= 64);
+ ASSERT(pulData != 0);
+
+ //
+ // Loop through all the words to be stored, storing one at a time.
+ //
+ for(uIdx = 0; uIdx < ulCount; uIdx++)
+ {
+ //
+ // Write a word to the non-volatile storage area.
+ //
+ HWREG(HIB_DATA + (uIdx * 4)) = pulData[uIdx];
+
+ //
+ // Add a delay between writes to the data area.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Reads a set of data from the non-volatile memory of the Hibernation module.
+//!
+//! \param pulData points to a location where the data that is read from the
+//! Hibernation module will be stored.
+//! \param ulCount is the count of 32-bit words to read.
+//!
+//! Retrieves a set of data from the Hibernation module non-volatile memory
+//! that was previously stored with the HibernateDataSet() function. The
+//! caller must ensure that \e pulData points to a large enough memory block to
+//! hold all the data that is read from the non-volatile memory.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDataGet(unsigned long *pulData, unsigned long ulCount)
+{
+ unsigned int uIdx;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulCount <= 64);
+ ASSERT(pulData != 0);
+
+ //
+ // Loop through all the words to be restored, reading one at a time.
+ //
+ for(uIdx = 0; uIdx < ulCount; uIdx++)
+ {
+ //
+ // Read a word from the non-volatile storage area. No delay is
+ // required between reads.
+ //
+ pulData[uIdx] = HWREG(HIB_DATA + (uIdx * 4));
+ }
+}
+
+//*****************************************************************************
+//
+//! Requests hibernation mode.
+//!
+//! This function requests the Hibernation module to disable the external
+//! regulator, thus removing power from the processor and all peripherals. The
+//! Hibernation module will remain powered from the battery or auxiliary power
+//! supply.
+//!
+//! The Hibernation module will re-enable the external regulator when one of
+//! the configured wake conditions occurs (such as RTC match or external
+//! \b WAKE pin). When the power is restored the processor will go through a
+//! normal power-on reset. The processor can retrieve saved state information
+//! with the HibernateDataGet() function. Prior to calling the function to
+//! request hibernation mode, the conditions for waking must have already been
+//! set by using the HibernateWakeSet() function.
+//!
+//! Note that this function may return because some time may elapse before the
+//! power is actually removed, or it may not be removed at all. For this
+//! reason, the processor will continue to execute instructions for some time
+//! and the caller should be prepared for this function to return. There are
+//! various reasons why the power may not be removed. For example, if the
+//! HibernateLowBatSet() function was used to configure an abort if low
+//! battery is detected, then the power will not be removed if the battery
+//! voltage is too low. There may be other reasons, related to the external
+//! circuit design, that a request for hibernation may not actually occur.
+//!
+//! For all these reasons, the caller must be prepared for this function to
+//! return. The simplest way to handle it is to just enter an infinite loop
+//! and wait for the power to be removed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRequest(void)
+{
+ //
+ // Set the bit in the control register to cut main power to the processor.
+ //
+ HWREG(HIB_CTL) |= HIB_CTL_HIBREQ;
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts for the Hibernation module.
+//!
+//! \param ulIntFlags is the bit mask of the interrupts to be enabled.
+//!
+//! Enables the specified interrupt sources from the Hibernation module.
+//!
+//! The \e ulIntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt
+//! - \b HIBERNATE_INT_LOW_BAT - low battery interrupt
+//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt
+//! - \b HIBERNATE_INT_RTC_MATCH_1 - RTC match 1 interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntEnable(unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+ HIBERNATE_INT_RTC_MATCH_0 |
+ HIBERNATE_INT_RTC_MATCH_1)));
+
+ //
+ // Set the specified interrupt mask bits.
+ //
+ HWREG(HIB_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the Hibernation module.
+//!
+//! \param ulIntFlags is the bit mask of the interrupts to be disabled.
+//!
+//! Disables the specified interrupt sources from the Hibernation module.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to the HibernateIntEnable() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntDisable(unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+ HIBERNATE_INT_RTC_MATCH_0 |
+ HIBERNATE_INT_RTC_MATCH_1)));
+
+ //
+ // Clear the specified interrupt mask bits.
+ //
+ HWREG(HIB_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the Hibernation module interrupt.
+//!
+//! \param pfnHandler points to the function to be called when a hibernation
+//! interrupt occurs.
+//!
+//! Registers the interrupt handler in the system interrupt controller. The
+//! interrupt is enabled at the global level, but individual interrupt sources
+//! must still be enabled with a call to HibernateIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_HIBERNATE, pfnHandler);
+
+ //
+ // Enable the hibernate module interrupt.
+ //
+ IntEnable(INT_HIBERNATE);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the Hibernation module interrupt.
+//!
+//! Unregisters the interrupt handler in the system interrupt controller. The
+//! interrupt is disabled at the global level, and the interrupt handler will
+//! no longer be called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntUnregister(void)
+{
+ //
+ // Disable the hibernate interrupt.
+ //
+ IntDisable(INT_HIBERNATE);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_HIBERNATE);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status of the Hibernation module.
+//!
+//! \param bMasked is false to retrieve the raw interrupt status, and true to
+//! retrieve the masked interrupt status.
+//!
+//! Returns the interrupt status of the Hibernation module. The caller can use
+//! this to determine the cause of a hibernation interrupt. Either the masked
+//! or raw interrupt status can be returned.
+//!
+//! \return Returns the interrupt status as a bit field with the values as
+//! described in the HibernateIntEnable() function.
+//
+//*****************************************************************************
+unsigned long
+HibernateIntStatus(tBoolean bMasked)
+{
+ //
+ // Read and return the Hibernation module raw or masked interrupt status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(HIB_MIS) & 0xf);
+ }
+ else
+ {
+ return(HWREG(HIB_RIS) & 0xf);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears pending interrupts from the Hibernation module.
+//!
+//! \param ulIntFlags is the bit mask of the interrupts to be cleared.
+//!
+//! Clears the specified interrupt sources. This must be done from within the
+//! interrupt handler or else the handler will be called again upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to the HibernateIntEnable() function.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntClear(unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+ HIBERNATE_INT_RTC_MATCH_0 |
+ HIBERNATE_INT_RTC_MATCH_1)));
+
+ //
+ // Write the specified interrupt bits into the interrupt clear register.
+ //
+ HWREG(HIB_IC) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Checks to see if the Hibernation module is already powered up.
+//!
+//! This function queries the control register to determine if the module is
+//! already active. This function can be called at a power-on reset to help
+//! determine if the reset is due to a wake from hibernation or a cold start.
+//! If the Hibernation module is already active, then it does not need to be
+//! re-enabled and its status can be queried immediately.
+//!
+//! The software application should also use the HibernateIntStatus() function
+//! to read the raw interrupt status to determine the cause of the wake. The
+//! HibernateDataGet() function can be used to restore state. These
+//! combinations of functions can be used by the software to determine if the
+//! processor is waking from hibernation and the appropriate action to take as
+//! a result.
+//!
+//! \return Returns \b true if the module is already active, and \b false if
+//! not.
+//
+//*****************************************************************************
+unsigned int
+HibernateIsActive(void)
+{
+ //
+ // Read the control register, and return true if the module is enabled.
+ //
+ return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/hibernate.h b/bsp/lm3s/Libraries/driverlib/hibernate.h new file mode 100644 index 0000000000..4be5f81231 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/hibernate.h @@ -0,0 +1,130 @@ +//*****************************************************************************
+//
+// hibernate.h - API definition for the Hibernation module.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HIBERNATE_H__
+#define __HIBERNATE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macros needed for selecting the clock source for HibernateClockSelect()
+//
+//*****************************************************************************
+#define HIBERNATE_CLOCK_SEL_RAW 0x04
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00
+
+//*****************************************************************************
+//
+// Macros need to configure wake events for HibernateWakeSet()
+//
+//*****************************************************************************
+#define HIBERNATE_WAKE_PIN 0x10
+#define HIBERNATE_WAKE_RTC 0x08
+
+//*****************************************************************************
+//
+// Macros needed to configure low battery detect for HibernateLowBatSet()
+//
+//*****************************************************************************
+#define HIBERNATE_LOW_BAT_DETECT 0x20
+#define HIBERNATE_LOW_BAT_ABORT 0xA0
+
+//*****************************************************************************
+//
+// Macros defining interrupt source bits for the interrupt functions.
+//
+//*****************************************************************************
+#define HIBERNATE_INT_PIN_WAKE 0x08
+#define HIBERNATE_INT_LOW_BAT 0x04
+#define HIBERNATE_INT_RTC_MATCH_0 0x01
+#define HIBERNATE_INT_RTC_MATCH_1 0x02
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void HibernateEnableExpClk(unsigned long ulHibClk);
+extern void HibernateDisable(void);
+extern void HibernateClockSelect(unsigned long ulClockInput);
+extern void HibernateRTCEnable(void);
+extern void HibernateRTCDisable(void);
+extern void HibernateWakeSet(unsigned long ulWakeFlags);
+extern unsigned long HibernateWakeGet(void);
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
+extern unsigned long HibernateLowBatGet(void);
+extern void HibernateRTCSet(unsigned long ulRTCValue);
+extern unsigned long HibernateRTCGet(void);
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);
+extern unsigned long HibernateRTCMatch0Get(void);
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);
+extern unsigned long HibernateRTCMatch1Get(void);
+extern void HibernateRTCTrimSet(unsigned long ulTrim);
+extern unsigned long HibernateRTCTrimGet(void);
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
+extern void HibernateRequest(void);
+extern void HibernateIntEnable(unsigned long ulIntFlags);
+extern void HibernateIntDisable(unsigned long ulIntFlags);
+extern void HibernateIntRegister(void (*pfnHandler)(void));
+extern void HibernateIntUnregister(void);
+extern unsigned long HibernateIntStatus(tBoolean bMasked);
+extern void HibernateIntClear(unsigned long ulIntFlags);
+extern unsigned int HibernateIsActive(void);
+
+//*****************************************************************************
+//
+// Several Hibernate module APIs have been renamed, with the original function
+// name being deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define HibernateEnable(a) \
+ HibernateEnableExpClk(a, SysCtlClockGet())
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HIBERNATE_H__
diff --git a/bsp/lm3s/Libraries/driverlib/i2c.c b/bsp/lm3s/Libraries/driverlib/i2c.c new file mode 100644 index 0000000000..eadeec1c97 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/i2c.c @@ -0,0 +1,1109 @@ +//*****************************************************************************
+//
+// i2c.c - Driver for Inter-IC (I2C) bus block.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup i2c_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_i2c.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/i2c.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Initializes the I2C Master block.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ulI2CClk is the rate of the clock supplied to the I2C module.
+//! \param bFast set up for fast data transfers
+//!
+//! This function initializes operation of the I2C Master block. Upon
+//! successful initialization of the I2C block, this function will have set the
+//! bus speed for the master, and will have enabled the I2C Master block.
+//!
+//! If the parameter \e bFast is \b true, then the master block will be set up
+//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data
+//! at 100 kbps.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original I2CMasterInit() API and performs the
+//! same actions. A macro is provided in <tt>i2c.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
+ tBoolean bFast)
+{
+ unsigned long ulSCLFreq;
+ unsigned long ulTPR;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Must enable the device before doing anything else.
+ //
+ I2CMasterEnable(ulBase);
+
+ //
+ // Get the desired SCL speed.
+ //
+ if(bFast == true)
+ {
+ ulSCLFreq = 400000;
+ }
+ else
+ {
+ ulSCLFreq = 100000;
+ }
+
+ //
+ // Compute the clock divider that achieves the fastest speed less than or
+ // equal to the desired speed. The numerator is biased to favor a larger
+ // clock divider so that the resulting clock is always less than or equal
+ // to the desired clock, never greater.
+ //
+ ulTPR = ((ulI2CClk + (2 * 10 * ulSCLFreq) - 1) / (2 * 10 * ulSCLFreq)) - 1;
+ HWREG(ulBase + I2C_O_MTPR) = ulTPR;
+}
+
+//*****************************************************************************
+//
+//! Initializes the I2C Slave block.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ucSlaveAddr 7-bit slave address
+//!
+//! This function initializes operation of the I2C Slave block. Upon
+//! successful initialization of the I2C blocks, this function will have set
+//! the slave address and have enabled the I2C Slave block.
+//!
+//! The parameter \e ucSlaveAddr is the value that will be compared against the
+//! slave address sent by an I2C master.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+ ASSERT(!(ucSlaveAddr & 0x80));
+
+ //
+ // Must enable the device before doing anything else.
+ //
+ I2CSlaveEnable(ulBase);
+
+ //
+ // Set up the slave address.
+ //
+ HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master block.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This will enable operation of the I2C Master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Enable the master block.
+ //
+ HWREG(ulBase + I2C_O_MCR) |= I2C_MCR_MFE;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave block.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This will enable operation of the I2C Slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Enable the clock to the slave block.
+ //
+ HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) |=
+ I2C_MCR_SFE;
+
+ //
+ // Enable the slave.
+ //
+ HWREG(ulBase + I2C_O_SCSR) = I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C master block.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This will disable operation of the I2C master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Disable the master block.
+ //
+ HWREG(ulBase + I2C_O_MCR) &= ~(I2C_MCR_MFE);
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C slave block.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This will disable operation of the I2C slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Disable the slave.
+ //
+ HWREG(ulBase + I2C_O_SCSR) = 0;
+
+ //
+ // Disable the clock to the slave block.
+ //
+ HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) &=
+ ~(I2C_MCR_SFE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the I2C module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! I2C interrupt occurs.
+//!
+//! This sets the handler to be called when an I2C interrupt occurs. This will
+//! enable the global interrupt in the interrupt controller; specific I2C
+//! interrupts must be enabled via I2CMasterIntEnable() and
+//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
+//! responsibility to clear the interrupt source via I2CMasterIntClear() and
+//! I2CSlaveIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Determine the interrupt number based on the I2C port.
+ //
+ ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the I2C interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the I2C module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function will clear the handler to be called when an I2C interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Determine the interrupt number based on the I2C port.
+ //
+ ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master interrupt.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! Enables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Enable the master interrupt.
+ //
+ HWREG(ulBase + I2C_O_MIMR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave interrupt.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! Enables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Enable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Enables individual I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated I2C Slave interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt
+//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt
+//! - \b I2C_SLAVE_INT_DATA - Data interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Enable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Master interrupt.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! Disables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Disable the master interrupt.
+ //
+ HWREG(ulBase + I2C_O_MIMR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Slave interrupt.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! Disables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Disable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Disables individual I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated I2C Slave interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to I2CSlaveIntEnableEx().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Disable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Master interrupt status.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This returns the interrupt status for the I2C Master module. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+tBoolean
+I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return((HWREG(ulBase + I2C_O_MMIS)) ? true : false);
+ }
+ else
+ {
+ return((HWREG(ulBase + I2C_O_MRIS)) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This returns the interrupt status for the I2C Slave module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+tBoolean
+I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return((HWREG(ulBase + I2C_O_SMIS)) ? true : false);
+ }
+ else
+ {
+ return((HWREG(ulBase + I2C_O_SRIS)) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This returns the interrupt status for the I2C Slave module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in I2CSlaveIntEnableEx().
+//
+//*****************************************************************************
+unsigned long
+I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ //
+ // Workaround for I2C slave masked interrupt status register errata
+ // (7.1) for Dustdevil Rev A0 devices.
+ //
+ if(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)
+ {
+ ulValue = HWREG(ulBase + I2C_O_SRIS);
+ return(ulValue & HWREG(ulBase + I2C_O_SIMR));
+ }
+ else
+ {
+ return(HWREG(ulBase + I2C_O_SMIS));
+ }
+ }
+ else
+ {
+ return(HWREG(ulBase + I2C_O_SRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Master interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! The I2C Master interrupt source is cleared, so that it no longer asserts.
+//! This must be done in the interrupt handler to keep it from being called
+//! again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Clear the I2C master interrupt source.
+ //
+ HWREG(ulBase + I2C_O_MICR) = I2C_MICR_IC;
+
+ //
+ // Workaround for I2C master interrupt clear errata for rev B Stellaris
+ // devices. For later devices, this write is ignored and therefore
+ // harmless (other than the slight performance hit).
+ //
+ HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
+//! This must be done in the interrupt handler to keep it from being called
+//! again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Clear the I2C slave interrupt source.
+ //
+ HWREG(ulBase + I2C_O_SICR) = I2C_SICR_DATAIC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified I2C Slave interrupt sources are cleared, so that they no
+//! longer assert. This must be done in the interrupt handler to keep it from
+//! being called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to I2CSlaveIntEnableEx().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Clear the I2C slave interrupt source.
+ //
+ HWREG(ulBase + I2C_O_SICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Sets the address that the I2C Master will place on the bus.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ucSlaveAddr 7-bit slave address
+//! \param bReceive flag indicating the type of communication with the slave
+//!
+//! This function will set the address that the I2C Master will place on the
+//! bus when initiating a transaction. When the \e bReceive parameter is set
+//! to \b true, the address will indicate that the I2C Master is initiating a
+//! read from the slave; otherwise the address will indicate that the I2C
+//! Master is initiating a write to the slave.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
+ tBoolean bReceive)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+ ASSERT(!(ucSlaveAddr & 0x80));
+
+ //
+ // Set the address of the slave with which the master will communicate.
+ //
+ HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive;
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C Master is busy.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function returns an indication of whether or not the I2C Master is
+//! busy transmitting or receiving data.
+//!
+//! \return Returns \b true if the I2C Master is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+tBoolean
+I2CMasterBusy(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Return the busy status.
+ //
+ if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C bus is busy.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function returns an indication of whether or not the I2C bus is busy.
+//! This function can be used in a multi-master environment to determine if
+//! another master is currently using the bus.
+//!
+//! \return Returns \b true if the I2C bus is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+tBoolean
+I2CMasterBusBusy(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Return the bus busy status.
+ //
+ if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSBSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Controls the state of the I2C Master module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ulCmd command to be issued to the I2C Master module
+//!
+//! This function is used to control the state of the Master module send and
+//! receive operations. The \e ucCmd parameter can be one of the following
+//! values:
+//!
+//! - \b I2C_MASTER_CMD_SINGLE_SEND
+//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE
+//! - \b I2C_MASTER_CMD_BURST_SEND_START
+//! - \b I2C_MASTER_CMD_BURST_SEND_CONT
+//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH
+//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+ ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
+ (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
+
+ //
+ // Send the command.
+ //
+ HWREG(ulBase + I2C_O_MCS) = ulCmd;
+}
+
+//*****************************************************************************
+//
+//! Gets the error status of the I2C Master module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function is used to obtain the error status of the Master module send
+//! and receive operations.
+//!
+//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE,
+//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or
+//! \b I2C_MASTER_ERR_ARB_LOST.
+//
+//*****************************************************************************
+unsigned long
+I2CMasterErr(unsigned long ulBase)
+{
+ unsigned long ulErr;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Get the raw error state
+ //
+ ulErr = HWREG(ulBase + I2C_O_MCS);
+
+ //
+ // If the I2C master is busy, then all the other bit are invalid, and
+ // don't have an error to report.
+ //
+ if(ulErr & I2C_MCS_BUSY)
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+
+ //
+ // Check for errors.
+ //
+ if(ulErr & I2C_MCS_ERROR)
+ {
+ return(ulErr & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK));
+ }
+ else
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Master.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ucData data to be transmitted from the I2C Master
+//!
+//! This function will place the supplied data into I2C Master Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Write the byte.
+ //
+ HWREG(ulBase + I2C_O_MDR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Master.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function reads a byte of data from the I2C Master Data Register.
+//!
+//! \return Returns the byte received from by the I2C Master, cast as an
+//! unsigned long.
+//
+//*****************************************************************************
+unsigned long
+I2CMasterDataGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Read a byte.
+ //
+ return(HWREG(ulBase + I2C_O_MDR));
+}
+
+//*****************************************************************************
+//
+//! Gets the I2C Slave module status
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This function will return the action requested from a master, if any.
+//! Possible values are:
+//!
+//! - \b I2C_SLAVE_ACT_NONE
+//! - \b I2C_SLAVE_ACT_RREQ
+//! - \b I2C_SLAVE_ACT_TREQ
+//! - \b I2C_SLAVE_ACT_RREQ_FBR
+//!
+//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been
+//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that
+//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ
+//! to indicate that an I2C master has requested that the I2C Slave module send
+//! data, and \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent
+//! data to the I2C slave and the first byte following the slave's own address
+//! has been received.
+//
+//*****************************************************************************
+unsigned long
+I2CSlaveStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Return the slave status.
+ //
+ return(HWREG(ulBase + I2C_O_SCSR));
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Slave.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ucData data to be transmitted from the I2C Slave
+//!
+//! This function will place the supplied data into I2C Slave Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Write the byte.
+ //
+ HWREG(ulBase + I2C_O_SDR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Slave.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This function reads a byte of data from the I2C Slave Data Register.
+//!
+//! \return Returns the byte received from by the I2C Slave, cast as an
+//! unsigned long.
+//
+//*****************************************************************************
+unsigned long
+I2CSlaveDataGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Read a byte.
+ //
+ return(HWREG(ulBase + I2C_O_SDR));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/i2c.h b/bsp/lm3s/Libraries/driverlib/i2c.h new file mode 100644 index 0000000000..d31b190d56 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/i2c.h @@ -0,0 +1,170 @@ +//*****************************************************************************
+//
+// i2c.h - Prototypes for the I2C Driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Defines for the API.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Interrupt defines.
+//
+//*****************************************************************************
+#define I2C_INT_MASTER 0x00000001
+#define I2C_INT_SLAVE 0x00000002
+
+//*****************************************************************************
+//
+// I2C Master commands.
+//
+//*****************************************************************************
+#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005
+
+//*****************************************************************************
+//
+// I2C Master error status.
+//
+//*****************************************************************************
+#define I2C_MASTER_ERR_NONE 0
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010
+
+//*****************************************************************************
+//
+// I2C Slave action requests
+//
+//*****************************************************************************
+#define I2C_SLAVE_ACT_NONE 0
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
+#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
+
+//*****************************************************************************
+//
+// Miscellaneous I2C driver definitions.
+//
+//*****************************************************************************
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
+
+//*****************************************************************************
+//
+// I2C Slave interrupts.
+//
+//*****************************************************************************
+#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
+#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
+#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
+extern void I2CIntUnregister(unsigned long ulBase);
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
+extern tBoolean I2CMasterBusy(unsigned long ulBase);
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
+extern void I2CMasterDisable(unsigned long ulBase);
+extern void I2CMasterEnable(unsigned long ulBase);
+extern unsigned long I2CMasterErr(unsigned long ulBase);
+extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
+ tBoolean bFast);
+extern void I2CMasterIntClear(unsigned long ulBase);
+extern void I2CMasterIntDisable(unsigned long ulBase);
+extern void I2CMasterIntEnable(unsigned long ulBase);
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
+ unsigned char ucSlaveAddr,
+ tBoolean bReceive);
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
+extern void I2CSlaveDisable(unsigned long ulBase);
+extern void I2CSlaveEnable(unsigned long ulBase);
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
+extern void I2CSlaveIntClear(unsigned long ulBase);
+extern void I2CSlaveIntDisable(unsigned long ulBase);
+extern void I2CSlaveIntEnable(unsigned long ulBase);
+extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2CSlaveIntDisableEx(unsigned long ulBase,
+ unsigned long ulIntFlags);
+extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags);
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase,
+ tBoolean bMasked);
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several I2C APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define I2CMasterInit(a, b) \
+ I2CMasterInitExpClk(a, SysCtlClockGet(), b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2C_H__
diff --git a/bsp/lm3s/Libraries/driverlib/i2s.c b/bsp/lm3s/Libraries/driverlib/i2s.c new file mode 100644 index 0000000000..fd530b3651 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/i2s.c @@ -0,0 +1,1139 @@ +//*****************************************************************************
+//
+// i2s.c - Driver for the I2S controller.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup i2s_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_i2s.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/i2s.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Enables the I2S transmit module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function enables the transmit module for operation. The module
+//! should be enabled after configuration. When the module is disabled,
+//! no data or clocks will be generated on the I2S signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Enable the tx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM;
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2S transmit module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function disables the transmit module for operation. The module
+//! should be disabled before configuration. When the module is disabled,
+//! no data or clocks will be generated on the I2S signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_TXEN;
+}
+
+//*****************************************************************************
+//
+//! Writes data samples to the I2S transmit FIFO with blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulData is the single or dual channel I2S data.
+//!
+//! This function writes a single channel sample or combined left-right
+//! samples to the I2S transmit FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2STxConfigSet().
+//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter
+//! contains either the left or right sample. The left and right sample
+//! alternate with each write to the FIFO, left sample first. If the transmit
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! \e ulData parameter contains both the left and right samples. If the
+//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are written at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no room in the transmit FIFO, then this function will wait
+//! in a polling loop until the data can be written.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxDataPut(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Wait until there is space.
+ //
+ while(HWREG(ulBase + I2S_O_TXLEV) >= 16)
+ {
+ }
+
+ //
+ // Write the data to the I2S.
+ //
+ HWREG(ulBase + I2S_O_TXFIFO) = ulData;
+}
+
+//*****************************************************************************
+//
+//! Writes data samples to the I2S transmit FIFO without blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulData is the single or dual channel I2S data.
+//!
+//! This function writes a single channel sample or combined left-right
+//! samples to the I2S transmit FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2STxConfigSet().
+//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter
+//! contains either the left or right sample. The left and right sample
+//! alternate with each write to the FIFO, left sample first. If the transmit
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! \e ulData parameter contains both the left and right samples. If the
+//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are written at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no room in the transmit FIFO, then this function will return
+//! immediately without writing any data to the FIFO.
+//!
+//! \return The number of elements written to the I2S transmit FIFO (1 or 0).
+//
+//*****************************************************************************
+long
+I2STxDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Check for space to write.
+ //
+ if(HWREG(ulBase + I2S_O_TXLEV) < 16)
+ {
+ HWREG(ulBase + I2S_O_TXFIFO) = ulData;
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the I2S transmit module.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulConfig is the logical OR of the configuration options.
+//!
+//! This function is used to configure the options for the I2S transmit
+//! channel. The parameter \e ulConfig is the logical OR of the following
+//! options:
+//!
+//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
+//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
+//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
+//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
+//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
+//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
+//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
+//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
+//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
+//! the I2S transmitter is the clock master or slave.
+//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per sample.
+//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per word that are transferred on the data
+//! line.
+//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether
+//! the module transmits zeroes or repeats the last sample when the FIFO is
+//! empty.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
+ I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK |
+ I2S_CONFIG_SAMPLE_SIZE_MASK |
+ I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);
+
+ //
+ // Check to see if a compact mode is used.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
+ {
+ //
+ // If compact 8 mode is used, then need to adjust some bits
+ // before writing the config register. Also set the FIFO
+ // config register for 8 bit compact samples.
+ //
+ ulConfig &= ~I2S_CONFIG_MODE_MONO;
+ HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS;
+ }
+ else
+ {
+ //
+ // If compact 8 mode is not used, then set the FIFO config
+ // register for 16 bit. This is okay if a compact mode is
+ // not used.
+ //
+ HWREG(ulBase + I2S_O_TXFIFOCFG) = 0;
+ }
+
+ //
+ // Write the configuration register. Since all the fields are
+ // specified by the configuration parameter, it is not necessary
+ // to do a read-modify-write.
+ //
+ HWREG(ulBase + I2S_O_TXCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which a service request is generated.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulLevel is the FIFO service request limit.
+//!
+//! This function is used to set the transmit FIFO fullness level at which
+//! a service request will occur. The service request is used to generate
+//! an interrupt or a DMA transfer request. The transmit FIFO will
+//! generate a service request when the number of items in the FIFO is
+//! less than the level specified in the \e ulLevel parameter. For example,
+//! if \e ulLevel is 8, then a service request will be generated when
+//! there are less than 8 samples remaining in the transmit FIFO.
+//!
+//! For the purposes of counting the FIFO level, a left-right sample pair
+//! counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, the level must be an even number from 0 to 16. The
+//! maximum value is 16, which will cause a service request when there
+//! is any room in the FIFO. The minimum value is 0, which disables the
+//! service request.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT(ulLevel <= 16);
+
+ //
+ // Write the FIFO limit
+ //
+ HWREG(ulBase + I2S_O_TXLIMIT) = ulLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the current setting of the FIFO service request level.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the value of the transmit FIFO service
+//! request level. This value is set using the I2STxFIFOLimitSet()
+//! function.
+//!
+//! \return Returns the current value of the FIFO service request limit.
+//
+//*****************************************************************************
+unsigned long
+I2STxFIFOLimitGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the FIFO limit
+ //
+ return(HWREG(ulBase + I2S_O_TXLIMIT));
+}
+
+//*****************************************************************************
+//
+//! Gets the number of samples in the transmit FIFO.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the number of samples in the transmit
+//! FIFO. For the purposes of measuring the FIFO level, a left-right sample
+//! pair counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, normally the level will be an even number from 0 to
+//! 16. If dual stereo mode is used and only the left sample has been
+//! written without the matching right sample, then the FIFO level will be an
+//! odd value. If the FIFO level is odd, it indicates a left-right sample
+//! mismatch.
+//!
+//! \return Returns the number of samples in the transmit FIFO, which will
+//! normally be an even number.
+//
+//*****************************************************************************
+unsigned long
+I2STxFIFOLevelGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the transmit FIFO level.
+ //
+ return(HWREG(ulBase + I2S_O_TXLEV));
+}
+
+//*****************************************************************************
+//
+//! Enables the I2S receive module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function enables the receive module for operation. The module
+//! should be enabled after configuration. When the module is disabled,
+//! no data will be clocked in regardless of the signals on the I2S interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Enable the tx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM;
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2S receive module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function disables the receive module for operation. The module
+//! should be disabled before configuration. When the module is disabled,
+//! no data will be clocked in regardless of the signals on the I2S interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN;
+}
+
+//*****************************************************************************
+//
+//! Reads data samples from the I2S receive FIFO with blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param pulData points to storage for the returned I2S sample data.
+//!
+//! This function reads a single channel sample or combined left-right
+//! samples from the I2S receive FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2SRxConfigSet().
+//! If the receive mode is I2S_MODE_DUAL_STEREO then the returned value
+//! contains either the left or right sample. The left and right sample
+//! alternate with each read from the FIFO, left sample first. If the receive
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! returned data contains both the left and right samples. If the
+//! receive mode is I2S_MODE_SINGLE_MONO then the returned data
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are read at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no data in the receive FIFO, then this function will wait
+//! in a polling loop until data is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxDataGet(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Wait until there is data available.
+ //
+ while(HWREG(ulBase + I2S_O_RXLEV) == 0)
+ {
+ }
+
+ //
+ // Read data from the I2S receive FIFO.
+ //
+ *pulData = HWREG(ulBase + I2S_O_RXFIFO);
+}
+
+//*****************************************************************************
+//
+//! Reads data samples from the I2S receive FIFO without blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param pulData points to storage for the returned I2S sample data.
+//!
+//! This function reads a single channel sample or combined left-right
+//! samples from the I2S receive FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2SRxConfigSet().
+//! If the receive mode is I2S_MODE_DUAL_STEREO then the received data
+//! contains either the left or right sample. The left and right sample
+//! alternate with each read from the FIFO, left sample first. If the receive
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! received data contains both the left and right samples. If the
+//! receive mode is I2S_MODE_SINGLE_MONO then the received data
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are read at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no data in the receive FIFO, then this function will return
+//! immediately without reading any data from the FIFO.
+//!
+//! \return The number of elements read from the I2S receive FIFO (1 or 0).
+//
+//*****************************************************************************
+long
+I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Check for available samples.
+ //
+ if(HWREG(ulBase + I2S_O_RXLEV) != 0)
+ {
+ *pulData = HWREG(ulBase + I2S_O_RXFIFO);
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the I2S receive module.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulConfig is the logical OR of the configuration options.
+//!
+//! This function is used to configure the options for the I2S receive
+//! channel. The parameter \e ulConfig is the logical OR of the following
+//! options:
+//!
+//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
+//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
+//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
+//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
+//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
+//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
+//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
+//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
+//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
+//! the I2S receiver is the clock master or slave.
+//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per sample.
+//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per word that are transferred on the data
+//! line.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
+ I2S_CONFIG_CLK_MASK | I2S_CONFIG_SAMPLE_SIZE_MASK |
+ I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);
+
+ //
+ // Clear out any prior config of the RX FIFO config register.
+ //
+ HWREG(ulBase + I2S_O_RXFIFOCFG) = 0;
+
+ //
+ // If mono mode is used, then the FMM bit needs to be set.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO)
+ {
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM;
+ }
+
+ //
+ // If a compact mode is used, then the CSS bit needs to be set.
+ //
+ else if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
+ {
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS;
+ }
+
+ //
+ // The "mono" bits needs to be removed from the configuration word
+ // prior to writing to hardware, because the RX configuration register
+ // does not actually use these bits.
+ //
+ ulConfig &= ~I2S_CONFIG_MODE_MONO;
+
+ //
+ // Write the configuration register. Since all the fields are
+ // specified by the configuration parameter, it is not necessary
+ // to do a read-modify-write.
+ //
+ HWREG(ulBase + I2S_O_RXCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which a service request is generated.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulLevel is the FIFO service request limit.
+//!
+//! This function is used to set the receive FIFO fullness level at which
+//! a service request will occur. The service request is used to generate
+//! an interrupt or a DMA transfer request. The receive FIFO will
+//! generate a service request when the number of items in the FIFO is
+//! greater than the level specified in the \e ulLevel parameter. For example,
+//! if \e ulLevel is 4, then a service request will be generated when
+//! there are more than 4 samples available in the receive FIFO.
+//!
+//! For the purposes of counting the FIFO level, a left-right sample pair
+//! counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, the level must be an even number from 0 to 16. The
+//! minimum value is 0, which will cause a service request when there
+//! is any data available in the FIFO. The maximum value is 16, which
+//! disables the service request (because there cannot be more than 16
+//! items in the FIFO).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT(ulLevel <= 16);
+
+ //
+ // Write the FIFO limit
+ //
+ HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the current setting of the FIFO service request level.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the value of the receive FIFO service
+//! request level. This value is set using the I2SRxFIFOLimitSet()
+//! function.
+//!
+//! \return Returns the current value of the FIFO service request limit.
+//
+//*****************************************************************************
+unsigned long
+I2SRxFIFOLimitGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the FIFO limit. The lower bit is masked
+ // because it always reads as 1, and has no meaning.
+ //
+ return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE);
+}
+
+//*****************************************************************************
+//
+//! Gets the number of samples in the receive FIFO.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the number of samples in the receive
+//! FIFO. For the purposes of measuring the FIFO level, a left-right sample
+//! pair counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, normally the level will be an even number from 0 to
+//! 16. If dual stereo mode is used and only the left sample has been
+//! read without reading the matching right sample, then the FIFO level will
+//! be an odd value. If the FIFO level is odd, it indicates a left-right
+//! sample mismatch.
+//!
+//! \return Returns the number of samples in the transmit FIFO, which will
+//! normally be an even number.
+//
+//*****************************************************************************
+unsigned long
+I2SRxFIFOLevelGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the receive FIFO level.
+ //
+ return(HWREG(ulBase + I2S_O_RXLEV));
+}
+
+//*****************************************************************************
+//
+//! Enables the I2S transmit and receive modules for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function simultaneously enables the transmit and receive modules for
+//! operation, providing a synchronized SCLK and LRCLK. The module should be
+//! enabled after configuration. When the module is disabled, no data or
+//! clocks will be generated on the I2S signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxRxEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Enable the Tx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM;
+
+ //
+ // Enable the Rx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM;
+
+ //
+ // Enable the transmit and receive modules.
+ //
+ HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2S transmit and receive modules.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function simultaneously disables the transmit and receive modules.
+//! When the module is disabled, no data or clocks will be generated on the I2S
+//! signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxRxDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Disable the transmit and receive modules.
+ //
+ HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN);
+}
+
+//*****************************************************************************
+//
+//! Configures the I2S transmit and receive modules.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulConfig is the logical OR of the configuration options.
+//!
+//! This function is used to configure the options for the I2S transmit and
+//! receive channels with identical parameters. The parameter \e ulConfig is
+//! the logical OR of the following options:
+//!
+//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
+//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
+//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
+//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
+//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
+//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
+//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
+//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
+//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
+//! the I2S transmitter is the clock master or slave.
+//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per sample.
+//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per word that are transferred on the data
+//! line.
+//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether
+//! the module transmits zeroes or repeats the last sample when the FIFO is
+//! empty.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
+ I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK |
+ I2S_CONFIG_SAMPLE_SIZE_MASK |
+ I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);
+
+ //
+ // Clear out any prior configuration of the FIFO config registers.
+ //
+ HWREG(ulBase + I2S_O_TXFIFOCFG) = 0;
+ HWREG(ulBase + I2S_O_RXFIFOCFG) = 0;
+
+ //
+ // If mono mode is used, then the FMM bit needs to be set.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO)
+ {
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM;
+ ulConfig &= ~(I2S_CONFIG_MODE_MONO);
+ }
+
+ //
+ // If a compact mode is used, then the CSS bit needs to be set.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
+ {
+ HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS;
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS;
+ }
+
+ //
+ // Write the configuration register. Since all the fields are specified by
+ // the configuration parameter, it is not necessary to do a
+ // read-modify-write.
+ //
+ HWREG(ulBase + I2S_O_TXCFG) = ulConfig;
+ HWREG(ulBase + I2S_O_RXCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Selects the source of the master clock, internal or external.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulMClock is the logical OR of the master clock configuration
+//! choices.
+//!
+//! This function selects whether the master clock is sourced from the device
+//! internal PLL, or comes from an external pin. The I2S serial bit clock
+//! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master
+//! clock. The transmit and receive modules can be configured independently.
+//! The \e ulMClock parameter is chosen from the following:
+//!
+//! - one of \b I2S_TX_MCLK_EXT or \b I2S_TX_MCLK_INT
+//! - one of \b I2S_RX_MCLK_EXT or \b I2S_RX_MCLK_INT
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock)
+{
+ unsigned long ulConfig;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulMClock & (I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT)) == ulMClock);
+
+ //
+ // Set the clock selection bits in the configuation word.
+ //
+ ulConfig = HWREG(ulBase + I2S_O_CFG) &
+ ~(I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT);
+ HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock;
+}
+
+//*****************************************************************************
+//
+//! Enables I2S interrupt sources.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the specified I2S sources to generate interrupts.
+//! The \e ulIntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b I2S_INT_RXERR for receive errors
+//! - \b I2S_INT_RXREQ for receive FIFO service requests
+//! - \b I2S_INT_TXERR for transmit errors
+//! - \b I2S_INT_TXREQ for transmit FIFO service requests
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
+ I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + I2S_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables I2S interrupt sources.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the specified I2S sources for interrupt
+//! generation. The \e ulIntFlags parameter can be the logical OR
+//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ,
+//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
+ I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the I2S interrupt status.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param bMasked is set \b true to get the masked interrupt status, or
+//! \b false to get the raw interrupt status.
+//!
+//! This function returns the I2S interrupt status. It can return either
+//! the raw or masked interrupt status.
+//!
+//! \return Returns the masked or raw I2S interrupt status, as a bit field
+//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ,
+//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ
+//
+//*****************************************************************************
+unsigned long
+I2SIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + I2S_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + I2S_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears pending I2S interrupt sources.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears the specified pending I2S interrupts. This must
+//! be done in the interrupt handler to keep the handler from being called
+//! again immediately upon exit. The \e ulIntFlags parameter can be the
+//! logical OR of any of the following values: \b I2S_INT_RXERR,
+//! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
+ I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + I2S_O_IC) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the I2S controller.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the I2S controller
+//! generates an interrupt. Specific I2S interrupts must still be enabled
+//! with the I2SIntEnable() function. It is the responsibility of the
+//! interrupt handler to clear any pending interrupts with I2SIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT(pfnHandler);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_I2S0, pfnHandler);
+
+ //
+ // Enable the I2S interface interrupt.
+ //
+ IntEnable(INT_I2S0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the I2S controller.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function will disable and clear the handler to be called when the
+//! I2S interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Disable the I2S interface interrupt.
+ //
+ IntDisable(INT_I2S0);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_I2S0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/i2s.h b/bsp/lm3s/Libraries/driverlib/i2s.h new file mode 100644 index 0000000000..93cc2e6fe0 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/i2s.h @@ -0,0 +1,157 @@ +//*****************************************************************************
+//
+// i2s.h - Prototypes and macros for the I2S controller.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to I2STxConfigSet() and I2SRxConfigSet()
+//
+//*****************************************************************************
+#define I2S_CONFIG_FORMAT_MASK 0x3C000000 // JST, DLY, SCP, LRP
+#define I2S_CONFIG_FORMAT_I2S 0x14000000 // !JST, DLY, !SCP, LRP
+#define I2S_CONFIG_FORMAT_LEFT_JUST \
+ 0x00000000 // !JST, !DLY, !SCP, !LRP
+#define I2S_CONFIG_FORMAT_RIGHT_JUST \
+ 0x20000000 // JST, !DLY, !SCP, !LRP
+
+#define I2S_CONFIG_SCLK_INVERT 0x08000000
+
+#define I2S_CONFIG_MODE_MASK 0x03000000
+#define I2S_CONFIG_MODE_DUAL 0x00000000
+#define I2S_CONFIG_MODE_COMPACT_16 \
+ 0x01000000
+#define I2S_CONFIG_MODE_COMPACT_8 \
+ 0x03000000
+#define I2S_CONFIG_MODE_MONO 0x02000000
+
+#define I2S_CONFIG_EMPTY_MASK 0x00800000
+#define I2S_CONFIG_EMPTY_ZERO 0x00000000
+#define I2S_CONFIG_EMPTY_REPEAT 0x00800000
+
+#define I2S_CONFIG_CLK_MASK 0x00400000
+#define I2S_CONFIG_CLK_MASTER 0x00400000
+#define I2S_CONFIG_CLK_SLAVE 0x00000000
+
+#define I2S_CONFIG_SAMPLE_SIZE_MASK \
+ 0x0000FC00
+#define I2S_CONFIG_SAMPLE_SIZE_32 \
+ 0x00007C00
+#define I2S_CONFIG_SAMPLE_SIZE_24 \
+ 0x00005C00
+#define I2S_CONFIG_SAMPLE_SIZE_20 \
+ 0x00004C00
+#define I2S_CONFIG_SAMPLE_SIZE_16 \
+ 0x00003C00
+#define I2S_CONFIG_SAMPLE_SIZE_8 \
+ 0x00001C00
+
+#define I2S_CONFIG_WIRE_SIZE_MASK \
+ 0x000003F0
+#define I2S_CONFIG_WIRE_SIZE_32 0x000001F0
+#define I2S_CONFIG_WIRE_SIZE_24 0x00000170
+#define I2S_CONFIG_WIRE_SIZE_20 0x00000130
+#define I2S_CONFIG_WIRE_SIZE_16 0x000000F0
+#define I2S_CONFIG_WIRE_SIZE_8 0x00000070
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SMasterClockSelect()
+//
+//*****************************************************************************
+#define I2S_TX_MCLK_EXT 0x00000010
+#define I2S_TX_MCLK_INT 0x00000000
+#define I2S_RX_MCLK_EXT 0x00000020
+#define I2S_RX_MCLK_INT 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SIntEnable(), I2SIntDisable(), and
+// I2SIntClear()
+//
+//*****************************************************************************
+#define I2S_INT_RXERR 0x00000020
+#define I2S_INT_RXREQ 0x00000010
+#define I2S_INT_TXERR 0x00000002
+#define I2S_INT_TXREQ 0x00000001
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void I2STxEnable(unsigned long ulBase);
+extern void I2STxDisable(unsigned long ulBase);
+extern void I2STxDataPut(unsigned long ulBase, unsigned long ulData);
+extern long I2STxDataPutNonBlocking(unsigned long ulBase,
+ unsigned long ulData);
+extern void I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern void I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
+extern unsigned long I2STxFIFOLimitGet(unsigned long ulBase);
+extern unsigned long I2STxFIFOLevelGet(unsigned long ulBase);
+extern void I2SRxEnable(unsigned long ulBase);
+extern void I2SRxDisable(unsigned long ulBase);
+extern void I2SRxDataGet(unsigned long ulBase, unsigned long *pulData);
+extern long I2SRxDataGetNonBlocking(unsigned long ulBase,
+ unsigned long *pulData);
+extern void I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern void I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
+extern unsigned long I2SRxFIFOLimitGet(unsigned long ulBase);
+extern unsigned long I2SRxFIFOLevelGet(unsigned long ulBase);
+extern void I2STxRxEnable(unsigned long ulBase);
+extern void I2STxRxDisable(unsigned long ulBase);
+extern void I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern void I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock);
+extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long I2SIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void I2SIntUnregister(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2S_H__
diff --git a/bsp/lm3s/Libraries/driverlib/interrupt.c b/bsp/lm3s/Libraries/driverlib/interrupt.c new file mode 100644 index 0000000000..f1cd137535 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/interrupt.c @@ -0,0 +1,550 @@ +//*****************************************************************************
+//
+// interrupt.c - Driver for the NVIC Interrupt Controller.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// This is a mapping between priority grouping encodings and the number of
+// preemption priority bits.
+//
+//*****************************************************************************
+static const unsigned long g_pulPriority[] =
+{
+ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+ NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
+ NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number and the register that contains
+// the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulRegs[] =
+{
+ 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
+ NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
+ NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts. It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger. Since interrupts should be disabled before unregistering the
+//! corresponding handler, this should never be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+ //
+ // Go into an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// The processor vector table.
+//
+// This contains a list of the handlers for the various interrupt sources in
+// the system. The layout of this list is defined by the hardware; assertion
+// of an interrupt causes the processor to start executing directly at the
+// address given in the corresponding location in this list.
+//
+//*****************************************************************************
+#if defined(ewarm)
+static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
+#elif defined(sourcerygxx)
+static __attribute__((section(".cs3.region-head.ram")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#else
+static __attribute__((section("vtable")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#endif
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! Allows the processor to respond to interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include <tt>interrupt.h</tt> and call this function without
+//! having included <tt>hw_types.h</tt>. Now that the return is a
+//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
+//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterEnable(void)
+{
+ //
+ // Enable processor interrupts.
+ //
+ return(CPUcpsie());
+}
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! Prevents the processor from receiving interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include <tt>interrupt.h</tt> and call this function without
+//! having included <tt>hw_types.h</tt>. Now that the return is a
+//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
+//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterDisable(void)
+{
+ //
+ // Disable processor interrupts.
+ //
+ return(CPUcpsid());
+}
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param pfnHandler is a pointer to the function to be called.
+//!
+//! This function is used to specify the handler function to be called when the
+//! given interrupt is asserted to the processor. When the interrupt occurs,
+//! if it is enabled (via IntEnable()), the handler function will be called in
+//! interrupt context. Since the handler function can preempt other code, care
+//! must be taken to protect memory or peripherals that are accessed by the
+//! handler and other non-handler code.
+//!
+//! \note The use of this function (directly or indirectly via a peripheral
+//! driver interrupt register function) moves the interrupt vector table from
+//! flash to SRAM. Therefore, care must be taken when linking the application
+//! to ensure that the SRAM vector table is located at the beginning of SRAM;
+//! otherwise NVIC will not look in the correct portion of memory for the
+//! vector table (it requires the vector table be on a 1 kB memory alignment).
+//! Normally, the SRAM vector table is so placed via the use of linker scripts;
+//! some tool chains, such as the evaluation version of RV-MDK, do not support
+//! linker scripts and therefore will not produce a valid executable. See the
+//! discussion of compile-time versus run-time interrupt handler registration
+//! in the introduction to this chapter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
+{
+ unsigned long ulIdx, ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Make sure that the RAM vector table is correctly aligned.
+ //
+ ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
+
+ //
+ // See if the RAM vector table has been initialized.
+ //
+ if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
+ {
+ //
+ // Copy the vector table from the beginning of FLASH to the RAM vector
+ // table.
+ //
+ ulValue = HWREG(NVIC_VTABLE);
+ for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
+ {
+ g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
+ ulValue);
+ }
+
+ //
+ // Point NVIC at the RAM vector table.
+ //
+ HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
+ }
+
+ //
+ // Save the interrupt handler.
+ //
+ g_pfnRAMVectors[ulInterrupt] = pfnHandler;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler should be called when the
+//! given interrupt is asserted to the processor. The interrupt source will be
+//! automatically disabled (via IntDisable()) if necessary.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntUnregister(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Reset the interrupt handler.
+ //
+ g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
+}
+
+//*****************************************************************************
+//
+//! Sets the priority grouping of the interrupt controller.
+//!
+//! \param ulBits specifies the number of bits of preemptable priority.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification. The range of
+//! the grouping values are dependent upon the hardware implementation; on
+//! the Stellaris family, three bits are available for hardware interrupt
+//! prioritization and therefore priority grouping values of three through
+//! seven have the same effect.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityGroupingSet(unsigned long ulBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBits < NUM_PRIORITY);
+
+ //
+ // Set the priority grouping.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
+}
+
+//*****************************************************************************
+//
+//! Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification.
+//!
+//! \return The number of bits of preemptable priority.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityGroupingGet(void)
+{
+ unsigned long ulLoop, ulValue;
+
+ //
+ // Read the priority grouping.
+ //
+ ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
+
+ //
+ // Loop through the priority grouping values.
+ //
+ for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
+ {
+ //
+ // Stop looping if this value matches.
+ //
+ if(ulValue == g_pulPriority[ulLoop])
+ {
+ break;
+ }
+ }
+
+ //
+ // Return the number of priority bits.
+ //
+ return(ulLoop);
+}
+
+//*****************************************************************************
+//
+//! Sets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param ucPriority specifies the priority of the interrupt.
+//!
+//! This function is used to set the priority of an interrupt. When multiple
+//! interrupts are asserted simultaneously, the ones with the highest priority
+//! are processed before the lower priority interrupts. Smaller numbers
+//! correspond to higher interrupt priorities; priority 0 is the highest
+//! interrupt priority.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits. The remaining bits can be
+//! used to sub-prioritize the interrupt sources, and may be used by the
+//! hardware priority mechanism on a future part. This arrangement allows
+//! priorities to migrate to different NVIC implementations without changing
+//! the gross prioritization of the interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Set the interrupt priority.
+ //
+ ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
+ ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
+ ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
+ HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function gets the priority of an interrupt. See IntPrioritySet() for
+//! a definition of the priority value.
+//!
+//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
+//! specified.
+//
+//*****************************************************************************
+long
+IntPriorityGet(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Return the interrupt priority.
+ //
+ return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
+ 0xFF);
+}
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntEnable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to enable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Enable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Enable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Enable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Enable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Enable the general interrupt.
+ //
+ HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Enable the general interrupt.
+ //
+ HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntDisable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to disable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Disable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Disable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Disable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Disable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Disable the general interrupt.
+ //
+ HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Disable the general interrupt.
+ //
+ HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/interrupt.h b/bsp/lm3s/Libraries/driverlib/interrupt.h new file mode 100644 index 0000000000..53fdfb403c --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/interrupt.h @@ -0,0 +1,76 @@ +//*****************************************************************************
+//
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean IntMasterEnable(void);
+extern tBoolean IntMasterDisable(void);
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
+extern void IntUnregister(unsigned long ulInterrupt);
+extern void IntPriorityGroupingSet(unsigned long ulBits);
+extern unsigned long IntPriorityGroupingGet(void);
+extern void IntPrioritySet(unsigned long ulInterrupt,
+ unsigned char ucPriority);
+extern long IntPriorityGet(unsigned long ulInterrupt);
+extern void IntEnable(unsigned long ulInterrupt);
+extern void IntDisable(unsigned long ulInterrupt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
diff --git a/bsp/lm3s/Libraries/driverlib/mpu.c b/bsp/lm3s/Libraries/driverlib/mpu.c new file mode 100644 index 0000000000..0500c5eb20 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/mpu.c @@ -0,0 +1,449 @@ +//*****************************************************************************
+//
+// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup mpu_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/mpu.h"
+
+//*****************************************************************************
+//
+//! Enables and configures the MPU for use.
+//!
+//! \param ulMPUConfig is the logical OR of the possible configurations.
+//!
+//! This function enables the Cortex-M3 memory protection unit. It also
+//! configures the default behavior when in privileged mode and while
+//! handling a hard fault or NMI. Prior to enabling the MPU, at least one
+//! region must be set by calling MPURegionSet() or else by enabling the
+//! default region for privileged mode by passing the
+//! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable().
+//! Once the MPU is enabled, a memory management fault will be generated
+//! for any memory access violations.
+//!
+//! The \e ulMPUConfig parameter should be the logical OR of any of the
+//! following:
+//!
+//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
+//! privileged mode and when no other regions are defined. If this option
+//! is not enabled, then there must be at least one valid region already
+//! defined when the MPU is enabled.
+//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
+//! exception handler. If this option is not enabled, then the MPU is
+//! disabled while in one of these exception handlers and the default
+//! memory map is applied.
+//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
+//! no default memory map is provided in privileged mode, and the MPU will
+//! not be enabled in the fault handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUEnable(unsigned long ulMPUConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulMPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
+ MPU_CONFIG_HARDFLT_NMI)));
+
+ //
+ // Set the MPU control bits according to the flags passed by the user,
+ // and also set the enable bit.
+ //
+ HWREG(NVIC_MPU_CTRL) = ulMPUConfig | NVIC_MPU_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the MPU for use.
+//!
+//! This function disables the Cortex-M3 memory protection unit. When the
+//! MPU is disabled, the default memory map is used and memory management
+//! faults are not generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUDisable(void)
+{
+ //
+ // Turn off the MPU enable bit.
+ //
+ HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Gets the count of regions supported by the MPU.
+//!
+//! This function is used to get the number of regions that are supported by
+//! the MPU. This is the total number that are supported, including regions
+//! that are already programmed.
+//!
+//! \return The number of memory protection regions that are available
+//! for programming using MPURegionSet().
+//
+//*****************************************************************************
+unsigned long
+MPURegionCountGet(void)
+{
+ //
+ // Read the DREGION field of the MPU type register, and mask off
+ // the bits of interest to get the count of regions.
+ //
+ return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M)
+ >> NVIC_MPU_TYPE_DREGION_S);
+}
+
+//*****************************************************************************
+//
+//! Enables a specific region.
+//!
+//! \param ulRegion is the region number to enable.
+//!
+//! This function is used to enable a memory protection region. The region
+//! should already be set up with the MPURegionSet() function. Once enabled,
+//! the memory protection rules of the region will be applied and access
+//! violations will cause a memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionEnable(unsigned long ulRegion)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+
+ //
+ // Select the region to modify.
+ //
+ HWREG(NVIC_MPU_NUMBER) = ulRegion;
+
+ //
+ // Modify the enable bit in the region attributes.
+ //
+ HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables a specific region.
+//!
+//! \param ulRegion is the region number to disable.
+//!
+//! This function is used to disable a previously enabled memory protection
+//! region. The region will remain configured if it is not overwritten with
+//! another call to MPURegionSet(), and can be enabled again by calling
+//! MPURegionEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionDisable(unsigned long ulRegion)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+
+ //
+ // Select the region to modify.
+ //
+ HWREG(NVIC_MPU_NUMBER) = ulRegion;
+
+ //
+ // Modify the enable bit in the region attributes.
+ //
+ HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Sets up the access rules for a specific region.
+//!
+//! \param ulRegion is the region number to set up.
+//! \param ulAddr is the base address of the region. It must be aligned
+//! according to the size of the region specified in ulFlags.
+//! \param ulFlags is a set of flags to define the attributes of the region.
+//!
+//! This function sets up the protection rules for a region. The region has
+//! a base address and a set of attributes including the size, which must
+//! be a power of 2. The base address parameter, \e ulAddr, must be aligned
+//! according to the size.
+//!
+//! The \e ulFlags parameter is the logical OR of all of the attributes
+//! of the region. It is a combination of choices for region size,
+//! execute permission, read/write permissions, disabled sub-regions,
+//! and a flag to determine if the region is enabled.
+//!
+//! The size flag determines the size of a region, and must be one of the
+//! following:
+//!
+//! - \b MPU_RGN_SIZE_32B
+//! - \b MPU_RGN_SIZE_64B
+//! - \b MPU_RGN_SIZE_128B
+//! - \b MPU_RGN_SIZE_256B
+//! - \b MPU_RGN_SIZE_512B
+//! - \b MPU_RGN_SIZE_1K
+//! - \b MPU_RGN_SIZE_2K
+//! - \b MPU_RGN_SIZE_4K
+//! - \b MPU_RGN_SIZE_8K
+//! - \b MPU_RGN_SIZE_16K
+//! - \b MPU_RGN_SIZE_32K
+//! - \b MPU_RGN_SIZE_64K
+//! - \b MPU_RGN_SIZE_128K
+//! - \b MPU_RGN_SIZE_256K
+//! - \b MPU_RGN_SIZE_512K
+//! - \b MPU_RGN_SIZE_1M
+//! - \b MPU_RGN_SIZE_2M
+//! - \b MPU_RGN_SIZE_4M
+//! - \b MPU_RGN_SIZE_8M
+//! - \b MPU_RGN_SIZE_16M
+//! - \b MPU_RGN_SIZE_32M
+//! - \b MPU_RGN_SIZE_64M
+//! - \b MPU_RGN_SIZE_128M
+//! - \b MPU_RGN_SIZE_256M
+//! - \b MPU_RGN_SIZE_512M
+//! - \b MPU_RGN_SIZE_1G
+//! - \b MPU_RGN_SIZE_2G
+//! - \b MPU_RGN_SIZE_4G
+//!
+//! The execute permission flag must be one of the following:
+//!
+//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
+//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
+//!
+//! The read/write access permissions are applied separately for the
+//! privileged and user modes. The read/write access flags must be one
+//! of the following:
+//!
+//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
+//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
+//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
+//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
+//!
+//! The region is automatically divided into 8 equally-sized sub-regions by
+//! the MPU. Sub-regions can only be used in regions of size 256 bytes
+//! or larger. Any of these 8 sub-regions can be disabled. This allows
+//! for creation of ``holes'' in a region which can be left open, or overlaid
+//! by another region with different attributes. Any of the 8 sub-regions
+//! can be disabled with a logical OR of any of the following flags:
+//!
+//! - \b MPU_SUB_RGN_DISABLE_0
+//! - \b MPU_SUB_RGN_DISABLE_1
+//! - \b MPU_SUB_RGN_DISABLE_2
+//! - \b MPU_SUB_RGN_DISABLE_3
+//! - \b MPU_SUB_RGN_DISABLE_4
+//! - \b MPU_SUB_RGN_DISABLE_5
+//! - \b MPU_SUB_RGN_DISABLE_6
+//! - \b MPU_SUB_RGN_DISABLE_7
+//!
+//! Finally, the region can be initially enabled or disabled with one of
+//! the following flags:
+//!
+//! - \b MPU_RGN_ENABLE
+//! - \b MPU_RGN_DISABLE
+//!
+//! As an example, to set a region with the following attributes: size of
+//! 32 KB, execution enabled, read-only for both privileged and user, one
+//! sub-region disabled, and initially enabled; the \e ulFlags parameter would
+//! have the following value:
+//!
+//! <code>
+//! (MPU_RG_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
+//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
+//! </code>
+//!
+//! \note This function will write to multiple registers and is not protected
+//! from interrupts. It is possible that an interrupt which accesses a
+//! region may occur while that region is in the process of being changed.
+//! The safest way to handle this is to disable a region before changing it.
+//! Refer to the discussion of this in the API Detailed Description section.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+ ASSERT((ulAddr & ~0 << (((ulFlags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))
+ == ulAddr);
+
+ //
+ // Program the base address, use the region field to select the
+ // region at the same time.
+ //
+ HWREG(NVIC_MPU_BASE) = ulAddr | ulRegion | NVIC_MPU_BASE_VALID;
+
+ //
+ // Program the region attributes. Set the TEX field and the S, C,
+ // and B bits to fixed values that are suitable for all Stellaris
+ // memory.
+ //
+ HWREG(NVIC_MPU_ATTR) = (ulFlags & ~(NVIC_MPU_ATTR_TEX_M |
+ NVIC_MPU_ATTR_CACHEABLE)) |
+ NVIC_MPU_ATTR_SHAREABLE |
+ NVIC_MPU_ATTR_BUFFRABLE;
+}
+
+//*****************************************************************************
+//
+//! Gets the current settings for a specific region.
+//!
+//! \param ulRegion is the region number to get.
+//! \param pulAddr points to storage for the base address of the region.
+//! \param pulFlags points to the attribute flags for the region.
+//!
+//! This function retrieves the configuration of a specific region. The
+//! meanings and format of the parameters is the same as that of the
+//! MPURegionSet() function.
+//!
+//! This function can be used to save the configuration of a region for
+//! later use with the MPURegionSet() function. The region's enable state
+//! will be preserved in the attributes that are saved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
+ unsigned long *pulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+ ASSERT(pulAddr);
+ ASSERT(pulFlags);
+
+ //
+ // Select the region to get.
+ //
+ HWREG(NVIC_MPU_NUMBER) = ulRegion;
+
+ //
+ // Read and store the base address for the region.
+ //
+ *pulAddr = HWREG(NVIC_MPU_BASE);
+
+ //
+ // Read and store the region attributes.
+ //
+ *pulFlags = HWREG(NVIC_MPU_ATTR);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the memory management fault.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! memory management fault occurs.
+//!
+//! This sets and enables the handler to be called when the MPU generates
+//! a memory management fault due to a protection region access violation.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(pfnHandler);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(FAULT_MPU, pfnHandler);
+
+ //
+ // Enable the memory management fault.
+ //
+ IntEnable(FAULT_MPU);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the memory management fault.
+//!
+//! This function will disable and clear the handler to be called when a
+//! memory management fault occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(FAULT_MPU);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(FAULT_MPU);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/mpu.h b/bsp/lm3s/Libraries/driverlib/mpu.h new file mode 100644 index 0000000000..8111942726 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/mpu.h @@ -0,0 +1,150 @@ +//*****************************************************************************
+//
+// mpu.h - Defines and Macros for the memory protection unit.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __MPU_H__
+#define __MPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Flags that can be passed to MPUEnable.
+//
+//*****************************************************************************
+#define MPU_CONFIG_PRIV_DEFAULT 4
+#define MPU_CONFIG_HARDFLT_NMI 2
+#define MPU_CONFIG_NONE 0
+
+//*****************************************************************************
+//
+// Flags for the region size to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_SIZE_32B (4 << 1)
+#define MPU_RGN_SIZE_64B (5 << 1)
+#define MPU_RGN_SIZE_128B (6 << 1)
+#define MPU_RGN_SIZE_256B (7 << 1)
+#define MPU_RGN_SIZE_512B (8 << 1)
+
+#define MPU_RGN_SIZE_1K (9 << 1)
+#define MPU_RGN_SIZE_2K (10 << 1)
+#define MPU_RGN_SIZE_4K (11 << 1)
+#define MPU_RGN_SIZE_8K (12 << 1)
+#define MPU_RGN_SIZE_16K (13 << 1)
+#define MPU_RGN_SIZE_32K (14 << 1)
+#define MPU_RGN_SIZE_64K (15 << 1)
+#define MPU_RGN_SIZE_128K (16 << 1)
+#define MPU_RGN_SIZE_256K (17 << 1)
+#define MPU_RGN_SIZE_512K (18 << 1)
+
+#define MPU_RGN_SIZE_1M (19 << 1)
+#define MPU_RGN_SIZE_2M (20 << 1)
+#define MPU_RGN_SIZE_4M (21 << 1)
+#define MPU_RGN_SIZE_8M (22 << 1)
+#define MPU_RGN_SIZE_16M (23 << 1)
+#define MPU_RGN_SIZE_32M (24 << 1)
+#define MPU_RGN_SIZE_64M (25 << 1)
+#define MPU_RGN_SIZE_128M (26 << 1)
+#define MPU_RGN_SIZE_256M (27 << 1)
+#define MPU_RGN_SIZE_512M (28 << 1)
+
+#define MPU_RGN_SIZE_1G (29 << 1)
+#define MPU_RGN_SIZE_2G (30 << 1)
+#define MPU_RGN_SIZE_4G (31 << 1)
+
+//*****************************************************************************
+//
+// Flags for the permissions to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_PERM_EXEC 0x00000000
+#define MPU_RGN_PERM_NOEXEC 0x10000000
+#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
+#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
+#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
+#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
+#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
+#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
+
+//*****************************************************************************
+//
+// Flags for the sub-region to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_SUB_RGN_DISABLE_0 0x00000100
+#define MPU_SUB_RGN_DISABLE_1 0x00000200
+#define MPU_SUB_RGN_DISABLE_2 0x00000400
+#define MPU_SUB_RGN_DISABLE_3 0x00000800
+#define MPU_SUB_RGN_DISABLE_4 0x00001000
+#define MPU_SUB_RGN_DISABLE_5 0x00002000
+#define MPU_SUB_RGN_DISABLE_6 0x00004000
+#define MPU_SUB_RGN_DISABLE_7 0x00008000
+
+//*****************************************************************************
+//
+// Flags to enable or disable a region, to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_ENABLE 1
+#define MPU_RGN_DISABLE 0
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void MPUEnable(unsigned long ulMPUConfig);
+extern void MPUDisable(void);
+extern unsigned long MPURegionCountGet(void);
+extern void MPURegionEnable(unsigned long ulRegion);
+extern void MPURegionDisable(unsigned long ulRegion);
+extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
+ unsigned long ulFlags);
+extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
+ unsigned long *pulFlags);
+extern void MPUIntRegister(void (*pfnHandler)(void));
+extern void MPUIntUnregister(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __MPU_H__
diff --git a/bsp/lm3s/Libraries/driverlib/pin_map.h b/bsp/lm3s/Libraries/driverlib/pin_map.h new file mode 100644 index 0000000000..3a226d4ef1 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/pin_map.h @@ -0,0 +1,20416 @@ +//*****************************************************************************
+//
+// pin_map.h - Mapping of peripherals to pins for all parts.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __PIN_MAP_H__
+#define __PIN_MAP_H__
+
+//*****************************************************************************
+//
+// LM3S101 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S101
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define 32KHZ_PORT (GPIO_PORTB_BASE)
+#define 32KHZ_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S101
+
+//*****************************************************************************
+//
+// LM3S102 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S102
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define 32KHZ_PORT (GPIO_PORTB_BASE)
+#define 32KHZ_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S102
+
+//*****************************************************************************
+//
+// LM3S300 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S300
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S300
+
+//*****************************************************************************
+//
+// LM3S301 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S301
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S301
+
+//*****************************************************************************
+//
+// LM3S308 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S308
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S308
+
+//*****************************************************************************
+//
+// LM3S310 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S310
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S310
+
+//*****************************************************************************
+//
+// LM3S315 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S315
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S315
+
+//*****************************************************************************
+//
+// LM3S316 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S316
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S316
+
+//*****************************************************************************
+//
+// LM3S317 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S317
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S317
+
+//*****************************************************************************
+//
+// LM3S328 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S328
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S328
+
+//*****************************************************************************
+//
+// LM3S600 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S600
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S600
+
+//*****************************************************************************
+//
+// LM3S601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S601
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX_PORT (GPIO_PORTD_BASE)
+#define IDX_PIN (GPIO_PIN_7)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S601
+
+//*****************************************************************************
+//
+// LM3S608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S608
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S608
+
+//*****************************************************************************
+//
+// LM3S610 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S610
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S610
+
+//*****************************************************************************
+//
+// LM3S611 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S611
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S611
+
+//*****************************************************************************
+//
+// LM3S612 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S612
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S612
+
+//*****************************************************************************
+//
+// LM3S613 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S613
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S613
+
+//*****************************************************************************
+//
+// LM3S615 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S615
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S615
+
+//*****************************************************************************
+//
+// LM3S617 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S617
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S617
+
+//*****************************************************************************
+//
+// LM3S618 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S618
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX_PORT (GPIO_PORTB_BASE)
+#define IDX_PIN (GPIO_PIN_2)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S618
+
+//*****************************************************************************
+//
+// LM3S628 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S628
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S628
+
+//*****************************************************************************
+//
+// LM3S800 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S800
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S800
+
+//*****************************************************************************
+//
+// LM3S801 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S801
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX_PORT (GPIO_PORTD_BASE)
+#define IDX_PIN (GPIO_PIN_7)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S801
+
+//*****************************************************************************
+//
+// LM3S808 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S808
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S808
+
+//*****************************************************************************
+//
+// LM3S811 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S811
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S811
+
+//*****************************************************************************
+//
+// LM3S812 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S812
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S812
+
+//*****************************************************************************
+//
+// LM3S815 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S815
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S815
+
+//*****************************************************************************
+//
+// LM3S817 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S817
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S817
+
+//*****************************************************************************
+//
+// LM3S818 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S818
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX_PORT (GPIO_PORTB_BASE)
+#define IDX_PIN (GPIO_PIN_2)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S818
+
+//*****************************************************************************
+//
+// LM3S828 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S828
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S828
+
+//*****************************************************************************
+//
+// LM3S1110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1110
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1110
+
+//*****************************************************************************
+//
+// LM3S1133 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1133
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1133
+
+//*****************************************************************************
+//
+// LM3S1138 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1138
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP4_PORT (GPIO_PORTF_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1138
+
+//*****************************************************************************
+//
+// LM3S1150 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1150
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1150
+
+//*****************************************************************************
+//
+// LM3S1162 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1162
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1162
+
+//*****************************************************************************
+//
+// LM3S1165 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1165
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP6_PORT (GPIO_PORTB_BASE)
+#define CCP6_PIN (GPIO_PIN_5)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1165
+
+//*****************************************************************************
+//
+// LM3S1332 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1332
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1332
+
+//*****************************************************************************
+//
+// LM3S1435 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1435
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1435
+
+//*****************************************************************************
+//
+// LM3S1439 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1439
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1439
+
+//*****************************************************************************
+//
+// LM3S1512 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1512
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C2O_PORT (GPIO_PORTF_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP4_PORT (GPIO_PORTD_BASE)
+#define CCP4_PIN (GPIO_PIN_5)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1512
+
+//*****************************************************************************
+//
+// LM3S1538 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1538
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1538
+
+//*****************************************************************************
+//
+// LM3S1601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1601
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1601
+
+//*****************************************************************************
+//
+// LM3S1608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1608
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1608
+
+//*****************************************************************************
+//
+// LM3S1620 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1620
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1620
+
+//*****************************************************************************
+//
+// LM3S1635 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1635
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1635
+
+//*****************************************************************************
+//
+// LM3S1637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1637
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1637
+
+//*****************************************************************************
+//
+// LM3S1751 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1751
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1751
+
+//*****************************************************************************
+//
+// LM3S1850 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1850
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1850
+
+//*****************************************************************************
+//
+// LM3S1911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1911
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1911
+
+//*****************************************************************************
+//
+// LM3S1918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1918
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1918
+
+//*****************************************************************************
+//
+// LM3S1937 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1937
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1937
+
+//*****************************************************************************
+//
+// LM3S1958 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1958
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1958
+
+//*****************************************************************************
+//
+// LM3S1960 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1960
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C2O_PORT (GPIO_PORTF_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP4_PORT (GPIO_PORTF_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define IDX1_PORT (GPIO_PORTH_BASE)
+#define IDX1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHA1_PORT (GPIO_PORTG_BASE)
+#define PHA1_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHB1_PORT (GPIO_PORTG_BASE)
+#define PHB1_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1960
+
+//*****************************************************************************
+//
+// LM3S1968 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1968
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT_PORT (GPIO_PORTH_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define IDX1_PORT (GPIO_PORTF_BASE)
+#define IDX1_PIN (GPIO_PIN_1)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHA1_PORT (GPIO_PORTG_BASE)
+#define PHA1_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHB1_PORT (GPIO_PORTG_BASE)
+#define PHB1_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_2)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1968
+
+//*****************************************************************************
+//
+// LM3S2016 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2016
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2016
+
+//*****************************************************************************
+//
+// LM3S2110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2110
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2110
+
+//*****************************************************************************
+//
+// LM3S2139 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2139
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2139
+
+//*****************************************************************************
+//
+// LM3S2410 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2410
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2410
+
+//*****************************************************************************
+//
+// LM3S2412 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2412
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2412
+
+//*****************************************************************************
+//
+// LM3S2432 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2432
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2432
+
+//*****************************************************************************
+//
+// LM3S2533 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2533
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2533
+
+//*****************************************************************************
+//
+// LM3S2601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2601
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2601
+
+//*****************************************************************************
+//
+// LM3S2608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2608
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2608
+
+//*****************************************************************************
+//
+// LM3S2620 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2620
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C2O_PORT (GPIO_PORTE_BASE)
+#define C2O_PIN (GPIO_PIN_7)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2620
+
+//*****************************************************************************
+//
+// LM3S2637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2637
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2637
+
+//*****************************************************************************
+//
+// LM3S2651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2651
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2651
+
+//*****************************************************************************
+//
+// LM3S2730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2730
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2730
+
+//*****************************************************************************
+//
+// LM3S2739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2739
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2739
+
+//*****************************************************************************
+//
+// LM3S2911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2911
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2911
+
+//*****************************************************************************
+//
+// LM3S2918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2918
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2918
+
+//*****************************************************************************
+//
+// LM3S2939 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2939
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2939
+
+//*****************************************************************************
+//
+// LM3S2948 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2948
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2948
+
+//*****************************************************************************
+//
+// LM3S2950 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2950
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C2O_PORT (GPIO_PORTF_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_2)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_3)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2950
+
+//*****************************************************************************
+//
+// LM3S2965 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2965
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP4_PORT (GPIO_PORTD_BASE)
+#define CCP4_PIN (GPIO_PIN_5)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP5_PORT (GPIO_PORTG_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define IDX1_PORT (GPIO_PORTH_BASE)
+#define IDX1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHA1_PORT (GPIO_PORTG_BASE)
+#define PHA1_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHB1_PORT (GPIO_PORTG_BASE)
+#define PHB1_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_2)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_3)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2965
+
+//*****************************************************************************
+//
+// LM3S6100 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6100
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6100
+
+//*****************************************************************************
+//
+// LM3S6110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6110
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6110
+
+//*****************************************************************************
+//
+// LM3S6420 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6420
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6420
+
+//*****************************************************************************
+//
+// LM3S6422 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6422
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6422
+
+//*****************************************************************************
+//
+// LM3S6432 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6432
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6432
+
+//*****************************************************************************
+//
+// LM3S6537 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6537
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6537
+
+//*****************************************************************************
+//
+// LM3S6610 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6610
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C2O_PORT (GPIO_PORTE_BASE)
+#define C2O_PIN (GPIO_PIN_7)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6610
+
+//*****************************************************************************
+//
+// LM3S6611 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6611
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6611
+
+//*****************************************************************************
+//
+// LM3S6618 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6618
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6618
+
+//*****************************************************************************
+//
+// LM3S6633 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6633
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6633
+
+//*****************************************************************************
+//
+// LM3S6637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6637
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6637
+
+//*****************************************************************************
+//
+// LM3S6730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6730
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6730
+
+//*****************************************************************************
+//
+// LM3S6753 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6753
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6753
+
+//*****************************************************************************
+//
+// LM3S6816 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6816
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT_PORT (GPIO_PORTE_BASE)
+#define FAULT_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6816
+
+//*****************************************************************************
+//
+// LM3S6911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6911
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6911
+
+//*****************************************************************************
+//
+// LM3S6916 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6916
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT_PORT (GPIO_PORTE_BASE)
+#define FAULT_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6916
+
+//*****************************************************************************
+//
+// LM3S6918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6918
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6918
+
+//*****************************************************************************
+//
+// LM3S6938 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6938
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6938
+
+//*****************************************************************************
+//
+// LM3S6950 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6950
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6950
+
+//*****************************************************************************
+//
+// LM3S6952 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6952
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6952
+
+//*****************************************************************************
+//
+// LM3S6965 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6965
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define IDX1_PORT (GPIO_PORTF_BASE)
+#define IDX1_PIN (GPIO_PIN_1)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHA1_PORT (GPIO_PORTE_BASE)
+#define PHA1_PIN (GPIO_PIN_3)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHB1_PORT (GPIO_PORTE_BASE)
+#define PHB1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6965
+
+//*****************************************************************************
+//
+// LM3S8530 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8530
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2RX_PORT (GPIO_PORTE_BASE)
+#define CAN2RX_PIN (GPIO_PIN_4)
+
+#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2TX_PORT (GPIO_PORTE_BASE)
+#define CAN2TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8530
+
+//*****************************************************************************
+//
+// LM3S8538 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8538
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8538
+
+//*****************************************************************************
+//
+// LM3S8630 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8630
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8630
+
+//*****************************************************************************
+//
+// LM3S8730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8730
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8730
+
+//*****************************************************************************
+//
+// LM3S8733 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8733
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8733
+
+//*****************************************************************************
+//
+// LM3S8738 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8738
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8738
+
+//*****************************************************************************
+//
+// LM3S8930 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8930
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8930
+
+//*****************************************************************************
+//
+// LM3S8933 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8933
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8933
+
+//*****************************************************************************
+//
+// LM3S8938 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8938
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8938
+
+//*****************************************************************************
+//
+// LM3S8962 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8962
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define IDX1_PORT (GPIO_PORTF_BASE)
+#define IDX1_PIN (GPIO_PIN_1)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHA1_PORT (GPIO_PORTE_BASE)
+#define PHA1_PIN (GPIO_PIN_3)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_6)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHB1_PORT (GPIO_PORTE_BASE)
+#define PHB1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8962
+
+//*****************************************************************************
+//
+// LM3S8970 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8970
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2RX_PORT (GPIO_PORTE_BASE)
+#define CAN2RX_PIN (GPIO_PIN_4)
+
+#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2TX_PORT (GPIO_PORTE_BASE)
+#define CAN2TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8970
+
+//*****************************************************************************
+//
+// LM3S8971 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8971
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX0_PORT (GPIO_PORTB_BASE)
+#define IDX0_PIN (GPIO_PIN_2)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8971
+
+//*****************************************************************************
+//
+// LM3S1607 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1607
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_1)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_0)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U2RX_PORT (GPIO_PORTB_BASE)
+#define U2RX_PIN (GPIO_PIN_4)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define U2TX_PORT (GPIO_PORTE_BASE)
+#define U2TX_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S1607
+
+//*****************************************************************************
+//
+// LM3S1625 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1625
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1625
+
+//*****************************************************************************
+//
+// LM3S1626 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1626
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_4)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_5)
+
+#endif // PART_LM3S1626
+
+//*****************************************************************************
+//
+// LM3S1627 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1627
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX0_PORT (GPIO_PORTB_BASE)
+#define IDX0_PIN (GPIO_PIN_4)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1627
+
+//*****************************************************************************
+//
+// LM3S1776 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1776
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define FAULT2_PORT (GPIO_PORTC_BASE)
+#define FAULT2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM6_PORT (GPIO_PORTC_BASE)
+#define PWM6_PIN (GPIO_PIN_4)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM7_PORT (GPIO_PORTC_BASE)
+#define PWM7_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1776
+
+//*****************************************************************************
+//
+// LM3S2276 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2276
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define FAULT2_PORT (GPIO_PORTC_BASE)
+#define FAULT2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM6_PORT (GPIO_PORTC_BASE)
+#define PWM6_PIN (GPIO_PIN_4)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM7_PORT (GPIO_PORTC_BASE)
+#define PWM7_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2276
+
+//*****************************************************************************
+//
+// LM3S2616 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2616
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_7)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_7)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0RX_PORT (GPIO_PORTA_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0TX_PORT (GPIO_PORTA_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2616
+
+//*****************************************************************************
+//
+// LM3S2671 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2671
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_7)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_7)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_5)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_1)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2671
+
+//*****************************************************************************
+//
+// LM3S2678 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2678
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_1)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_0)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT0_PORT (GPIO_PORTB_BASE)
+#define FAULT0_PIN (GPIO_PIN_3)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX0_PORT (GPIO_PORTB_BASE)
+#define IDX0_PIN (GPIO_PIN_2)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2678
+
+//*****************************************************************************
+//
+// LM3S2776 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2776
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define FAULT2_PORT (GPIO_PORTC_BASE)
+#define FAULT2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM6_PORT (GPIO_PORTC_BASE)
+#define PWM6_PIN (GPIO_PIN_4)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM7_PORT (GPIO_PORTC_BASE)
+#define PWM7_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2776
+
+//*****************************************************************************
+//
+// LM3S3651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3651
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_7)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_3)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP6_PORT (GPIO_PORTD_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP7_PORT (GPIO_PORTD_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S3651
+
+//*****************************************************************************
+//
+// LM3S3739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3739
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP7_PORT (GPIO_PORTD_BASE)
+#define CCP7_PIN (GPIO_PIN_3)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2RX_PORT (GPIO_PORTD_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2TX_PORT (GPIO_PORTD_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S3739
+
+//*****************************************************************************
+//
+// LM3S3748 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3748
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_3)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP2_PORT (GPIO_PORTF_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_4)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define FAULT0_PORT (GPIO_PORTF_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT1_PORT (GPIO_PORTG_BASE)
+#define FAULT1_PIN (GPIO_PIN_5)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT2_PORT (GPIO_PORTG_BASE)
+#define FAULT2_PIN (GPIO_PIN_3)
+
+#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT3_PORT (GPIO_PORTH_BASE)
+#define FAULT3_PIN (GPIO_PIN_2)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM2_PORT (GPIO_PORTF_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM3_PORT (GPIO_PORTF_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM4_PORT (GPIO_PORTG_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM5_PORT (GPIO_PORTG_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM6_PORT (GPIO_PORTG_BASE)
+#define PWM6_PIN (GPIO_PIN_6)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM7_PORT (GPIO_PORTG_BASE)
+#define PWM7_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define U1RX_PORT (GPIO_PORTC_BASE)
+#define U1RX_PIN (GPIO_PIN_6)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define U1TX_PORT (GPIO_PORTC_BASE)
+#define U1TX_PIN (GPIO_PIN_7)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S3748
+
+//*****************************************************************************
+//
+// LM3S3749 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3749
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_7)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_3)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP2_PORT (GPIO_PORTF_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP3_PORT (GPIO_PORTA_BASE)
+#define CCP3_PIN (GPIO_PIN_7)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP4_PORT (GPIO_PORTF_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP6_PORT (GPIO_PORTD_BASE)
+#define CCP6_PIN (GPIO_PIN_2)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT0_PORT (GPIO_PORTG_BASE)
+#define FAULT0_PIN (GPIO_PIN_2)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT1_PORT (GPIO_PORTG_BASE)
+#define FAULT1_PIN (GPIO_PIN_4)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT2_PORT (GPIO_PORTG_BASE)
+#define FAULT2_PIN (GPIO_PIN_3)
+
+#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT3_PORT (GPIO_PORTH_BASE)
+#define FAULT3_PIN (GPIO_PIN_2)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SDA_PORT (GPIO_PORTG_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_1)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define IDX0_PORT (GPIO_PORTG_BASE)
+#define IDX0_PIN (GPIO_PIN_5)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHA0_PORT (GPIO_PORTF_BASE)
+#define PHA0_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM6_PORT (GPIO_PORTG_BASE)
+#define PWM6_PIN (GPIO_PIN_6)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM7_PORT (GPIO_PORTG_BASE)
+#define PWM7_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2RX_PORT (GPIO_PORTD_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2TX_PORT (GPIO_PORTD_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S3749
+
+//*****************************************************************************
+//
+// LM3S5632 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5632
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5632
+
+//*****************************************************************************
+//
+// LM3S5652 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5652
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP2_PORT (GPIO_PORTE_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP3_PORT (GPIO_PORTA_BASE)
+#define CCP3_PIN (GPIO_PIN_7)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5652
+
+//*****************************************************************************
+//
+// LM3S5662 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5662
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_2)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT0_PORT (GPIO_PORTB_BASE)
+#define FAULT0_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5662
+
+//*****************************************************************************
+//
+// LM3S5732 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5732
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5732
+
+//*****************************************************************************
+//
+// LM3S5737 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5737
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_1)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5737
+
+//*****************************************************************************
+//
+// LM3S5739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5739
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0RX_PORT (GPIO_PORTA_BASE)
+#define CAN0RX_PIN (GPIO_PIN_6)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0TX_PORT (GPIO_PORTA_BASE)
+#define CAN0TX_PIN (GPIO_PIN_7)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP7_PORT (GPIO_PORTD_BASE)
+#define CCP7_PIN (GPIO_PIN_3)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SDA_PORT (GPIO_PORTG_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_1)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2RX_PORT (GPIO_PORTD_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2TX_PORT (GPIO_PORTD_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S5739
+
+//*****************************************************************************
+//
+// LM3S5747 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5747
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5747
+
+//*****************************************************************************
+//
+// LM3S5749 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5749
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_1)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT0_PORT (GPIO_PORTG_BASE)
+#define FAULT0_PIN (GPIO_PIN_2)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT1_PORT (GPIO_PORTG_BASE)
+#define FAULT1_PIN (GPIO_PIN_4)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT2_PORT (GPIO_PORTG_BASE)
+#define FAULT2_PIN (GPIO_PIN_3)
+
+#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT3_PORT (GPIO_PORTH_BASE)
+#define FAULT3_PIN (GPIO_PIN_2)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define IDX0_PORT (GPIO_PORTG_BASE)
+#define IDX0_PIN (GPIO_PIN_5)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHA0_PORT (GPIO_PORTF_BASE)
+#define PHA0_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM6_PORT (GPIO_PORTG_BASE)
+#define PWM6_PIN (GPIO_PIN_6)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM7_PORT (GPIO_PORTG_BASE)
+#define PWM7_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S5749
+
+//*****************************************************************************
+//
+// LM3S5752 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5752
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP2_PORT (GPIO_PORTE_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP3_PORT (GPIO_PORTA_BASE)
+#define CCP3_PIN (GPIO_PIN_7)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5752
+
+//*****************************************************************************
+//
+// LM3S5762 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5762
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_2)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT0_PORT (GPIO_PORTB_BASE)
+#define FAULT0_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5762
+
+//*****************************************************************************
+//
+// Pin Mapping Functions
+//
+// This section describes the code that is responsible for handling the
+// mapping of peripheral functions to their physical location on the pins of
+// a device.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Definitions to support mapping GPIO Ports and Pins to their function.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Configures the specified ADC pin to function as an ADC pin.
+//
+// \param ulName is one of the valid names for the ADC pins.
+//
+// This function takes on of the valid names for an ADC pin and configures
+// the pin for its ADC functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b ADC0, \b ADC1, \b ADC2,
+// \b ADC3, \b ADC4, \b ADC5, \b ADC6, or \b ADC7.
+//
+// \sa GPIOPinTypeADC() in order to configure multiple ADC pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeADC(ulName) GPIOPinTypeADC(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified CAN pin to function as a CAN pin.
+//
+// \param ulName is one of the valid names for the CAN pins.
+//
+// This function takes one of the valid names for a CAN pin and configures
+// the pin for its CAN functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b CAN0RX, \b CAN0TX,
+// \b CAN1RX, \b CAN1TX, \b CAN2RX, or \b CAN2TX.
+//
+// \sa GPIOPinTypeCAN() in order to configure multiple CAN pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeCAN(ulName) GPIOPinTypeCAN(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified comparator pin to function as a comparator pin.
+//
+// \param ulName is one of the valid names for the Comparator pins.
+//
+// This function takes one of the valid names for a comparator pin and
+// configures the pin for its comparator functionality depending on the part
+// that is defined.
+//
+// The valid names for the pins are as follows: \b C0_MINUS, \b C0_PLUS,
+// \b C1_MINUS, \b C1_PLUS, \b C2_MINUS, or \b C2_PLUS.
+//
+// \sa GPIOPinTypeComparator() in order to configure multiple comparator pins
+// at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeComparator(ulName) \
+ GPIOPinTypeComparator(ulName##_PORT, \
+ ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified I2C pin to function as an I2C pin.
+//
+// \param ulName is one of the valid names for the I2C pins.
+//
+// This function takes one of the valid names for an I2C pin and configures
+// the pin for its I2C functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b I2C0SCL, \b I2C0SDA,
+// \b I2C1SCL, or \b I2C1SDA.
+//
+// \sa GPIOPinTypeI2C() in order to configure multiple I2C pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeI2C(ulName) GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified PWM pin to function as a PWM pin.
+//
+// \param ulName is one of the valid names for the PWM pins.
+//
+// This function takes one of the valid names for a PWM pin and configures
+// the pin for its PWM functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b PWM0, \b PWM1, \b PWM2,
+// \b PWM3, \b PWM4, \b PWM5, or \b FAULT.
+//
+// \sa GPIOPinTypePWM() in order to configure multiple PWM pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypePWM(ulName) GPIOPinTypePWM(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified QEI pin to function as a QEI pin.
+//
+// \param ulName is one of the valid names for the QEI pins.
+//
+// This function takes one of the valid names for a QEI pin and configures
+// the pin for its QEI functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b PHA0, \b PHB0, \b IDX0,
+// \b PHA1, \b PHB1, or \b IDX1.
+//
+// \sa GPIOPinTypeQEI() in order to configure multiple QEI pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeQEI(ulName) GPIOPinTypeQEI(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified SSI pin to function as an SSI pin.
+//
+// \param ulName is one of the valid names for the SSI pins.
+//
+// This function takes one of the valid names for an SSI pin and configures
+// the pin for its SSI functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b SSI0CLK, \b SSI0FSS,
+// \b SSI0RX, \b SSI0TX, \b SSI1CLK, \b SSI1FSS, \b SSI1RX, or \b SSI1TX.
+//
+// \sa GPIOPinTypeSSI() in order to configure multiple SSI pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeSSI(ulName) GPIOPinTypeSSI(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified Timer pin to function as a Timer pin.
+//
+// \param ulName is one of the valid names for the Timer pins.
+//
+// This function takes one of the valid names for a Timer pin and configures
+// the pin for its Timer functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b CCP0, \b CCP1, \b CCP2,
+// \b CCP3, \b CCP4, \b CCP5, \b CCP6, or \b CCP7.
+//
+// \sa GPIOPinTypeTimer() in order to configure multiple CCP pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeTimer(ulName) GPIOPinTypeTimer(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified UART pin to function as a UART pin.
+//
+// \param ulName is one of the valid names for the UART pins.
+//
+// This function takes one of the valid names for a UART pin and configures
+// the pin for its UART functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b U0RX, \b U0TX, \b U1RX,
+// \b U1TX, \b U2RX, or \b U2TX.
+//
+// \sa GPIOPinTypeUART() in order to configure multiple UART pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeUART(ulName) GPIOPinTypeUART(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+//! Configures the specified USB digital pin to function as a USB pin.
+//!
+//! \param ulName is one of the valid names for a USB digital pin.
+//!
+//! This function takes one of the valid names for a USB digital pin and
+//! configures the pin for its USB functionality depending on the part that is
+//! defined.
+//!
+//! The valid names for the pins are as follows: \b EPEN or \b PFAULT.
+//!
+//! \sa GPIOPinTypeUSBDigital() in order to configure multiple USB pins at
+//! once.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define PinTypeUSBDigital(ulName) \
+ GPIOPinTypeUSBDigital(ulName##_PORT, \
+ ulName##_PIN)
+
+//*****************************************************************************
+//
+//! Enables the peripheral port used by the given pin.
+//!
+//! \param ulName is one of the valid names for a pin.
+//!
+//! This function takes one of the valid names for a pin function and
+//! enables the peripheral port for that pin depending on the part that is
+//! defined.
+//!
+//! Any valid pin name can be used.
+//!
+//! \sa SysCtlPeripheralEnable() in order to enable a single port when
+//! multiple pins are on the same port.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define PeripheralEnable(ulName) \
+ SysCtlPeripheralEnable(ulName##_PERIPH)
+
+#endif // __PIN_MAP_H__
diff --git a/bsp/lm3s/Libraries/driverlib/pwm.c b/bsp/lm3s/Libraries/driverlib/pwm.c new file mode 100644 index 0000000000..1bbc52620d --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/pwm.c @@ -0,0 +1,1728 @@ +//*****************************************************************************
+//
+// pwm.c - API for the PWM modules
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup pwm_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_pwm.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/pwm.h"
+
+//*****************************************************************************
+//
+// Misc macros for manipulating the encoded generator and output defines used
+// by the API.
+//
+//*****************************************************************************
+#define PWM_GEN_BADDR(_mod_, _gen_) \
+ ((_mod_) + (_gen_))
+#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \
+ ((_mod_) + PWM_GEN_EXT_0 + \
+ ((_gen_) - PWM_GEN_0) * 2)
+#define PWM_OUT_BADDR(_mod_, _out_) \
+ ((_mod_) + ((_out_) & 0xFFFFFFC0))
+#define PWM_IS_OUTPUT_ODD(_out_) \
+ ((_out_) & 0x00000001)
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM generator number.
+//!
+//! \param ulGen is the generator number.
+//!
+//! This function determines if a PWM generator number is valid.
+//!
+//! \return Returnes \b true if the generator number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+PWMGenValid(unsigned long ulGen)
+{
+ return((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
+ (ulGen == PWM_GEN_2) || (ulGen == PWM_GEN_3));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM output number.
+//!
+//! \param ulPWMOut is the output number.
+//!
+//! This function determines if a PWM output number is valid.
+//!
+//! \return Returns \b true if the output number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+PWMOutValid(unsigned long ulPWMOut)
+{
+ return((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
+ (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
+ (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5) ||
+ (ulPWMOut == PWM_OUT_6) || (ulPWMOut == PWM_OUT_7));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Configures a PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to configure. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulConfig is the configuration for the PWM generator.
+//!
+//! This function is used to set the mode of operation for a PWM generator.
+//! The counting mode, synchronization mode, and debug behavior are all
+//! configured. After configuration, the generator is left in the disabled
+//! state.
+//!
+//! A PWM generator can count in two different modes: count down mode or count
+//! up/down mode. In count down mode, it will count from a value down to zero,
+//! and then reset to the preset value. This will produce left-aligned PWM
+//! signals (that is the rising edge of the two PWM signals produced by the
+//! generator will occur at the same time). In count up/down mode, it will
+//! count up from zero to the preset value, count back down to zero, and then
+//! repeat the process. This will produce center-aligned PWM signals (that is,
+//! the middle of the high/low period of the PWM signals produced by the
+//! generator will occur at the same time).
+//!
+//! When the PWM generator parameters (period and pulse width) are modified,
+//! their affect on the output PWM signals can be delayed. In synchronous
+//! mode, the parameter updates are not applied until a synchronization event
+//! occurs. This allows multiple parameters to be modified and take affect
+//! simultaneously, instead of one at a time. Additionally, parameters to
+//! multiple PWM generators in synchronous mode can be updated simultaneously,
+//! allowing them to be treated as if they were a unified generator. In
+//! non-synchronous mode, the parameter updates are not delayed until a
+//! synchronization event. In either mode, the parameter updates only occur
+//! when the counter is at zero to help prevent oddly formed PWM signals during
+//! the update (that is, a PWM pulse that is too short or too long).
+//!
+//! The PWM generator can either pause or continue running when the processor
+//! is stopped via the debugger. If configured to pause, it will continue to
+//! count until it reaches zero, at which point it will pause until the
+//! processor is restarted. If configured to continue running, it will keep
+//! counting as if nothing had happened.
+//!
+//! The \e ulConfig parameter contains the desired configuration. It is the
+//! logical OR of the following:
+//!
+//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting
+//! mode
+//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter
+//! load and comparator update synchronization mode
+//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug
+//! behavior
+//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or
+//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization
+//! mode for generator counting mode changes
+//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or
+//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter
+//! synchronization mode
+//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to
+//! specify whether fault conditions are latched or not
+//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to
+//! specify whether minimum fault period support is required
+//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify
+//! whether extended fault source selection support is enabled or not
+//!
+//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the
+//! minimum duration of a PWM fault signal. Fault will be signaled for at
+//! least this time even if the external fault pin deasserts earlier. Care
+//! should be taken when using this mode since during the fault signal period,
+//! the fault interrupt from the PWM generator will remain asserted. The fault
+//! interrupt handler may, therefore, reenter immediately if it exits prior to
+//! expiration of the fault timer.
+//!
+//! \note Changes to the counter mode will affect the period of the PWM signals
+//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after
+//! any changes to the counter mode of a generator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Change the global configuration of the generator.
+ //
+ HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) &
+ ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |
+ PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER |
+ PWM_X_CTL_FLTSRC | PWM_X_CTL_DBFALLUPD_M |
+ PWM_X_CTL_DBRISEUPD_M |
+ PWM_X_CTL_DBCTLUPD_M |
+ PWM_X_CTL_GENBUPD_M |
+ PWM_X_CTL_GENAUPD_M |
+ PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |
+ PWM_X_CTL_CMPBUPD)) | ulConfig);
+
+ //
+ // Set the individual PWM generator controls.
+ //
+ if(ulConfig & PWM_X_CTL_MODE)
+ {
+ //
+ // In up/down count mode, set the signal high on up count comparison
+ // and low on down count comparison (that is, center align the
+ // signals).
+ //
+ HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE |
+ PWM_X_GENA_ACTCMPAD_ZERO);
+ HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE |
+ PWM_X_GENB_ACTCMPBD_ZERO);
+ }
+ else
+ {
+ //
+ // In down count mode, set the signal high on load and low on count
+ // comparison (that is, left align the signals).
+ //
+ HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE |
+ PWM_X_GENA_ACTCMPAD_ZERO);
+ HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE |
+ PWM_X_GENB_ACTCMPBD_ZERO);
+ }
+}
+
+//*****************************************************************************
+//
+//! Set the period of a PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be modified. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulPeriod specifies the period of PWM generator output, measured
+//! in clock ticks.
+//!
+//! This function sets the period of the specified PWM generator block, where
+//! the period of the generator block is defined as the number of PWM clock
+//! ticks between pulses on the generator block zero signal.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! will cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Set the reload register based on the mode.
+ //
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ //
+ // In up/down count mode, set the reload register to half the requested
+ // period.
+ //
+ ASSERT((ulPeriod / 2) < 65536);
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2;
+ }
+ else
+ {
+ //
+ // In down count mode, set the reload register to the requested period
+ // minus one.
+ //
+ ASSERT((ulPeriod <= 65536) && (ulPeriod != 0));
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the period of a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function gets the period of the specified PWM generator block. The
+//! period of the generator block is defined as the number of PWM clock ticks
+//! between pulses on the generator block zero signal.
+//!
+//! If the update of the counter for the specified PWM generator has yet
+//! to be completed, the value returned may not be the active period. The
+//! value returned is the programmed period, measured in PWM clock ticks.
+//!
+//! \return Returns the programmed period of the specified generator block
+//! in PWM clock ticks.
+//
+//*****************************************************************************
+unsigned long
+PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Figure out the counter mode.
+ //
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ //
+ // The period is twice the reload register value.
+ //
+ return(HWREG(ulGen + PWM_O_X_LOAD) * 2);
+ }
+ else
+ {
+ //
+ // The period is the reload register value plus one.
+ //
+ return(HWREG(ulGen + PWM_O_X_LOAD) + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the timer/counter for a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be enabled. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function allows the PWM clock to drive the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenEnable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Enable the PWM generator.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the timer/counter for a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be disabled. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function blocks the PWM clock from driving the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenDisable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Disable the PWM generator.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Sets the pulse width for the specified PWM output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0,
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
+//! \b PWM_OUT_6, or \b PWM_OUT_7.
+//! \param ulWidth specifies the width of the positive portion of the pulse.
+//!
+//! This function sets the pulse width for the specified PWM output, where the
+//! pulse width is defined as the number of PWM clock ticks.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! will cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
+ unsigned long ulWidth)
+{
+ unsigned long ulGenBase, ulReg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMOutValid(ulPWMOut));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
+
+ //
+ // If the counter is in up/down count mode, divide the width by two.
+ //
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ ulWidth /= 2;
+ }
+
+ //
+ // Get the period.
+ //
+ ulReg = HWREG(ulGenBase + PWM_O_X_LOAD);
+
+ //
+ // Make sure the width is not too large.
+ //
+ ASSERT(ulWidth < ulReg);
+
+ //
+ // Compute the compare value.
+ //
+ ulReg = ulReg - ulWidth;
+
+ //
+ // Write to the appropriate registers.
+ //
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))
+ {
+ HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg;
+ }
+ else
+ {
+ HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the pulse width of a PWM output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0,
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
+//! \b PWM_OUT_6, or \b PWM_OUT_7.
+//!
+//! This function gets the currently programmed pulse width for the specified
+//! PWM output. If the update of the comparator for the specified output has
+//! yet to be completed, the value returned may not be the active pulse width.
+//! The value returned is the programmed pulse width, measured in PWM clock
+//! ticks.
+//!
+//! \return Returns the width of the pulse in PWM clock ticks.
+//
+//*****************************************************************************
+unsigned long
+PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut)
+{
+ unsigned long ulGenBase, ulReg, ulLoad;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMOutValid(ulPWMOut));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
+
+ //
+ // Then compute the pulse width. If mode is UpDown, set
+ // width = (load - compare) * 2. Otherwise, set width = load - compare.
+ //
+ ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD);
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))
+ {
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPB);
+ }
+ else
+ {
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPA);
+ }
+ ulReg = ulLoad - ulReg;
+
+ //
+ // If in up/down count mode, double the pulse width.
+ //
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ ulReg = ulReg * 2;
+ }
+
+ //
+ // Return the pulse width.
+ //
+ return(ulReg);
+}
+
+//*****************************************************************************
+//
+//! Enables the PWM dead band output, and sets the dead band delays.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to modify. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param usRise specifies the width of delay from the rising edge.
+//! \param usFall specifies the width of delay from the falling edge.
+//!
+//! This function sets the dead bands for the specified PWM generator,
+//! where the dead bands are defined as the number of \b PWM clock ticks
+//! from the rising or falling edge of the generator's \b OutA signal.
+//! Note that this function causes the coupling of \b OutB to \b OutA.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned short usRise, unsigned short usFall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT(usRise < 4096);
+ ASSERT(usFall < 4096);
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Write the dead band delay values.
+ //
+ HWREG(ulGen + PWM_O_X_DBRISE) = usRise;
+ HWREG(ulGen + PWM_O_X_DBFALL) = usFall;
+
+ //
+ // Enable the deadband functionality.
+ //
+ HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the PWM dead band output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to modify. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function disables the dead band mode for the specified PWM generator.
+//! Doing so decouples the \b OutA and \b OutB signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Disable the deadband functionality.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &=
+ ~(PWM_X_DBCTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Synchronizes all pending updates.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenBits are the PWM generator blocks to be updated. Must be the
+//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
+//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM generators, this function causes all queued updates to
+//! the period or pulse width to be applied the next time the corresponding
+//! counter becomes zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+ PWM_GEN_3_BIT)));
+
+ //
+ // Synchronize pending PWM register changes.
+ //
+ HWREG(ulBase + PWM_O_CTL) = ulGenBits;
+}
+
+//*****************************************************************************
+//
+//! Synchronizes the counters in one or multiple PWM generator blocks.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be
+//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
+//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM module, this function synchronizes the time base
+//! of the generator blocks by causing the specified generator counters to be
+//! reset to zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+ PWM_GEN_3_BIT)));
+
+ //
+ // Synchronize the counters in the specified generators by writing to the
+ // module's synchronization register.
+ //
+ HWREG(ulBase + PWM_O_SYNC) = ulGenBits;
+}
+
+//*****************************************************************************
+//
+//! Enables or disables PWM outputs.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT,
+//! or \b PWM_OUT_7_BIT.
+//! \param bEnable determines if the signal is enabled or disabled.
+//!
+//! This function is used to enable or disable the selected PWM outputs. The
+//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
+//! \e bEnable determines the state of the selected outputs. If \e bEnable is
+//! \b true, then the selected PWM outputs are enabled, or placed in the active
+//! state. If \e bEnable is \b false, then the selected outputs are disabled,
+//! or placed in the inactive state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's ENABLE output control register, and set or clear the
+ // requested bits.
+ //
+ if(bEnable == true)
+ {
+ HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Selects the inversion mode for PWM outputs.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bInvert determines if the signal is inverted or passed through.
+//!
+//! This function is used to select the inversion mode for the selected PWM
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
+//! The parameter \e bInvert determines the inversion mode for the selected
+//! outputs. If \e bInvert is \b true, this function will cause the specified
+//! PWM output signals to be inverted, or made active low. If \e bInvert is
+//! \b false, the specified output will be passed through as is, or be made
+//! active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's INVERT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bInvert == true)
+ {
+ HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Specifies the level of PWM outputs suppressed in response to a fault
+//! condition.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bDriveHigh determines if the signal is driven high or low during an
+//! active fault condition.
+//!
+//! This function determines whether a PWM output pin that is suppressed in
+//! response to a fault condition will be driven high or low. The affected
+//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
+//! \e bDriveHigh determines the output level for the pins identified by
+//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs
+//! will be driven high when a fault is detected. If it is \e false, the pins
+//! will be driven low.
+//!
+//! In a fault condition, pins which have not been configured to be suppressed
+//! via a call to PWMOutputFault() are unaffected by this function.
+//!
+//! \note This function is available only on devices which support extended
+//! PWM fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bDriveHigh)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's FAULT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bDriveHigh == true)
+ {
+ HWREG(ulBase + PWM_O_FAULTVAL) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_FAULTVAL) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Specifies the state of PWM outputs in response to a fault condition.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bFaultSuppress determines if the signal is suppressed or passed
+//! through during an active fault condition.
+//!
+//! This function sets the fault handling characteristics of the selected PWM
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
+//! The parameter \e bFaultSuppress determines the fault handling
+//! characteristics for the selected outputs. If \e bFaultSuppress is \b true,
+//! then the selected outputs will be made inactive. If \e bFaultSuppress is
+//! \b false, then the selected outputs are unaffected by the detected fault.
+//!
+//! On devices supporting extended PWM fault handling, the state the affected
+//! output pins are driven to can be configured with PWMOutputFaultLevel(). If
+//! not configured, or if the device does not support extended PWM fault
+//! handling, affected outputs will be driven low on a fault condition.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bFaultSuppress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's FAULT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bFaultSuppress == true)
+ {
+ HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator in question. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! generator interrupt occurs.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected for the specified
+//! PWM generator block. This function will also enable the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be enabled with PWMIntEnable() and
+//! PWMGenIntTrigEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
+ void (*pfnIntHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Get the interrupt number associated with the specified generator.
+ //
+ if(ulGen == PWM_GEN_3)
+ {
+ ulInt = INT_PWM3;
+ }
+ else
+ {
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;
+ }
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnIntHandler);
+
+ //
+ // Enable the PWMx interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator in question. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! PWM generator block. This function will also disable the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be disabled with PWMIntDisable() and
+//! PWMGenIntTrigDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Get the interrupt number associated with the specified generator.
+ //
+ if(ulGen == PWM_GEN_3)
+ {
+ ulInt = INT_PWM3;
+ }
+ else
+ {
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;
+ }
+
+ //
+ // Disable the PWMx interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a fault condition detected in a PWM
+//! module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! fault interrupt occurs.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when a fault interrupt is detected for the
+//! selected PWM module. This function will also enable the PWM fault
+//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the
+//! module level using PWMIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Register the interrupt handler, returning an error if one occurs.
+ //
+ IntRegister(INT_PWM_FAULT, pfnIntHandler);
+
+ //
+ // Enable the PWM fault interrupt.
+ //
+ IntEnable(INT_PWM_FAULT);
+}
+
+//*****************************************************************************
+//
+//! Removes the PWM fault condition interrupt handler.
+//!
+//! \param ulBase is the base address of the PWM module.
+//!
+//! This function will remove the interrupt handler for a PWM fault interrupt
+//! from the selected PWM module. This function will also disable the PWM
+//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled
+//! at the module level using PWMIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Disable the PWM fault interrupt.
+ //
+ IntDisable(INT_PWM_FAULT);
+
+ //
+ // Unregister the interrupt handler, returning an error if one occurs.
+ //
+ IntUnregister(INT_PWM_FAULT);
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts and triggers for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to have interrupts and triggers enabled.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulIntTrig specifies the interrupts and triggers to be enabled.
+//!
+//! Unmasks the specified interrupt(s) and trigger(s) by setting the
+//! specified bits of the interrupt/trigger enable register for the specified
+//! PWM generator. The \e ulIntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+ PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+ PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
+ PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
+ PWM_TR_CNT_BD)) == 0);
+
+ //
+ // Enable the specified interrupts/triggers.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to have interrupts and triggers disabled.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulIntTrig specifies the interrupts and triggers to be disabled.
+//!
+//! Masks the specified interrupt(s) and trigger(s) by clearing the
+//! specified bits of the interrupt/trigger enable register for the specified
+//! PWM generator. The \e ulIntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+ PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+ PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
+ PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
+ PWM_TR_CNT_BD)) == 0);
+
+ //
+ // Disable the specified interrupts/triggers.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
+//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns the contents of the interrupt status register, or the
+//! contents of the raw interrupt status register, for the specified
+//! PWM generator.
+//
+//*****************************************************************************
+unsigned long
+PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Read and return the specified generator's raw or enabled interrupt
+ // status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(ulGen + PWM_O_X_ISC));
+ }
+ else
+ {
+ return(HWREG(ulGen + PWM_O_X_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the specified interrupt(s) for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
+//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulInts specifies the interrupts to be cleared.
+//!
+//! Clears the specified interrupt(s) by writing a 1 to the specified bits
+//! of the interrupt status register for the specified PWM generator. The
+//! \e ulInts parameter is the logical OR of \b PWM_INT_CNT_ZERO,
+//! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD,
+//! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulInts & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU |
+ PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) ==
+ 0);
+
+ //
+ // Clear the requested interrupts by writing ones to the specified bit
+ // of the module's interrupt enable register.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts;
+}
+
+//*****************************************************************************
+//
+//! Enables generator and fault interrupts for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenFault contains the interrupts to be enabled. Must be a logical
+//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
+//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
+//! or \b PWM_INT_FAULT3.
+//!
+//! Unmasks the specified interrupt(s) by setting the specified bits of
+//! the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+ PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Read the module's interrupt enable register, and enable interrupts
+ // for the specified PWM generators.
+ //
+ HWREG(ulBase + PWM_O_INTEN) |= ulGenFault;
+}
+
+//*****************************************************************************
+//
+//! Disables generator and fault interrupts for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenFault contains the interrupts to be disabled. Must be a
+//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
+//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
+//! or \b PWM_INT_FAULT3.
+//!
+//! Masks the specified interrupt(s) by clearing the specified bits of
+//! the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+ PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Read the module's interrupt enable register, and disable interrupts
+ // for the specified PWM generators.
+ //
+ HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault);
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//!
+//! Clears the fault interrupt by writing to the appropriate bit of the
+//! interrupt status register for the selected PWM module.
+//!
+//! This function clears only the FAULT0 interrupt and is retained for
+//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be
+//! used instead since it supports all fault interrupts supported on devices
+//! with and without extended PWM fault handling support.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Write the only writeable bit in the module's interrupt register.
+ //
+ HWREG(ulBase + PWM_O_ISC) = PWM_ISC_INTFAULT0;
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt status for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3,
+//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and
+//! \b PWM_INT_FAULT3.
+//!
+//*****************************************************************************
+unsigned long
+PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Read and return either the module's raw or enabled interrupt status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(ulBase + PWM_O_ISC));
+ }
+ else
+ {
+ return(HWREG(ulBase + PWM_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulFaultInts specifies the fault interrupts to clear.
+//!
+//! Clears one or more fault interrupts by writing to the appropriate bit of
+//! the PWM interrupt status register. The parameter \e ulFaultInts must be
+//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1,
+//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
+//!
+//! When running on a device supporting extended PWM fault handling, the fault
+//! interrupts are derived by performing a logical OR of each of the configured
+//! fault trigger signals for a given generator. Therefore, these interrupts
+//! are not directly related to the four possible FAULTn inputs to the device
+//! but indicate that a fault has been signaled to one of the four possible PWM
+//! generators. On a device without extended PWM fault handling, the interrupt
+//! is directly related to the state of the single FAULT pin.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several cycles before the interrupt source is actually cleared. Therefore,
+//! it is recommended that the interrupt source be cleared early in the
+//! interrupt handler (as opposed to the very last action) to avoid returning
+//! from the interrupt handler before the interrupt source is actually cleared.
+//! Failure to do so may result in the interrupt handler being immediately
+//! reentered (since NVIC still sees the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Clear the supplied fault bits.
+ //
+ HWREG(ulBase + PWM_O_ISC) = ulFaultInts;
+}
+
+//*****************************************************************************
+//
+//! Configures the minimum fault period and fault pin senses for a given
+//! PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault configuration is being set.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulMinFaultPeriod is the minimum fault active period expressed in
+//! PWM clock cycles.
+//! \param ulFaultSenses indicates which sense of each FAULT input should be
+//! considered the ``asserted'' state. Valid values are logical OR
+//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW.
+//!
+//! This function sets the minimum fault period for a given generator along
+//! with the sense of each of the 4 possible fault inputs. The minimum fault
+//! period is expressed in PWM clock cycles and takes effect only if
+//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the
+//! \e ulConfig parameter. When a fault input is asserted, the minimum fault
+//! period timer ensures that it remains asserted for at least the number of
+//! clock cycles specified.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulMinFaultPeriod,
+ unsigned long ulFaultSenses)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M);
+ ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW |
+ PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW |
+ PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW |
+ PWM_FAULT3_SENSE_HIGH | PWM_FAULT3_SENSE_LOW)) ==
+ 0);
+
+ //
+ // Write the minimum fault period.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_MINFLTPER) = ulMinFaultPeriod;
+
+ //
+ // Write the fault senses.
+ //
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSEN) = ulFaultSenses;
+}
+
+//*****************************************************************************
+//
+//! Configures the set of fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault triggers are being set. Must
+//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of possible faults that are to be
+//! configured. This must be \b PWM_FAULT_GROUP_0.
+//! \param ulFaultTriggers defines the set of inputs that are to contribute
+//! towards generation of the fault signal to the given PWM generator. For
+//! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0,
+//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.
+//!
+//! This function allows selection of the set of fault inputs that will be
+//! combined to generate a fault condition to a given PWM generator. By
+//! default, all generators use only FAULT0 (for backwards compatibility) but
+//! if PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the
+//! \e ulConfig parameter, extended fault handling is enabled and this function
+//! must be called to configure the fault triggers.
+//!
+//! The fault signal to the PWM generator is generated by ORing together each
+//! of the signals whose inputs are specified in the \e ulFaultTriggers
+//! parameter after having adjusted the sense of each FAULTn input based on the
+//! configuration previously set using a call to PWMGenFaultConfigure().
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup, unsigned long ulFaultTriggers)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+ ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+ PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+
+ //
+ // Write the fault triggers to the appropriate register.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) =
+ ulFaultTriggers;
+ }
+ else
+ {
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1) =
+ ulFaultTriggers;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the set of fault triggers currently configured for a given PWM
+//! generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault triggers are being queried.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0.
+//!
+//! This function allows an application to query the current set of inputs that
+//! contribute towards the generation of a fault condition to a given PWM
+//! generator.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current fault triggers configured for the fault group
+//! provided. For \b PWM_FAULT_GROUP_0, the returned value will be a logical
+//! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3.
+//
+//*****************************************************************************
+unsigned long
+PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+
+ //
+ // Return the current fault triggers.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0));
+ }
+ else
+ {
+ return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1));
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the current state of the fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault trigger states are being
+//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
+//! \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0.
+//!
+//! This function allows an application to query the current state of each of
+//! the fault trigger inputs to a given PWM generator. The current state of
+//! each fault trigger input is returned unless PWMGenConfigure() has
+//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the
+//! \e ulConfig parameter in which case the returned status is the latched
+//! fault trigger status.
+//!
+//! If latched faults are configured, the application must call
+//! PWMGenFaultClear() to clear each trigger.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current state of the fault triggers for the given PWM
+//! generator. A set bit indicates that the associated trigger is active. For
+//! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of
+//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3.
+//
+//*****************************************************************************
+unsigned long
+PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+
+ //
+ // Return the current fault status.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0));
+ }
+ else
+ {
+ return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears one or more latched fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault trigger states are being
+//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
+//! \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0.
+//! \param ulFaultTriggers is the set of fault triggers which are to be
+//! cleared.
+//!
+//! This function allows an application to clear the fault triggers for a given
+//! PWM generator. This is only required if PWMGenConfigure() has previously
+//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup, unsigned long ulFaultTriggers)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+ ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+ PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+
+ //
+ // Clear the given faults.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) =
+ ulFaultTriggers;
+ }
+ else
+ {
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1) =
+ ulFaultTriggers;
+ }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/pwm.h b/bsp/lm3s/Libraries/driverlib/pwm.h new file mode 100644 index 0000000000..12cdc45b57 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/pwm.h @@ -0,0 +1,277 @@ +//*****************************************************************************
+//
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __PWM_H__
+#define __PWM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are passed to PWMGenConfigure() as the ulConfig
+// parameter and specify the configuration of the PWM generator.
+//
+//*****************************************************************************
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
+#define PWM_GEN_MODE_FAULT_LATCHED \
+ 0x00040000 // Fault is latched
+#define PWM_GEN_MODE_FAULT_UNLATCHED \
+ 0x00000000 // Fault is not latched
+#define PWM_GEN_MODE_FAULT_MINPER \
+ 0x00020000 // Enable min fault period
+#define PWM_GEN_MODE_FAULT_NO_MINPER \
+ 0x00000000 // Disable min fault period
+#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
+#define PWM_GEN_MODE_FAULT_LEGACY \
+ 0x00000000 // Disable extended fault support
+#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
+ // immediately
+#define PWM_GEN_MODE_DB_SYNC_LOCAL \
+ 0x0000A800 // Deadband updates locally
+ // synchronized
+#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
+ 0x0000FC00 // Deadband updates globally
+ // synchronized
+#define PWM_GEN_MODE_GEN_NO_SYNC \
+ 0x00000000 // Generator mode updates occur
+ // immediately
+#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
+ 0x00000280 // Generator mode updates locally
+ // synchronized
+#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
+ 0x000003C0 // Generator mode updates globally
+ // synchronized
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM generator interrupts and
+// triggers.
+//
+//*****************************************************************************
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM interrupts.
+//
+//*****************************************************************************
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
+#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
+#ifndef DEPRECATED
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt
+#endif
+#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
+#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
+#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
+#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
+#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
+
+//*****************************************************************************
+//
+// Defines to identify the generators within a module.
+//
+//*****************************************************************************
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
+#define PWM_GEN_3 0x00000100 // Offset address of Gen3
+
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
+#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
+
+#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
+#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
+#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
+#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
+
+//*****************************************************************************
+//
+// Defines to identify the outputs within a module.
+//
+//*****************************************************************************
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
+#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
+#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
+
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
+#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
+#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_0.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_0 0
+
+#define PWM_FAULT_FAULT0 0x00000001
+#define PWM_FAULT_FAULT1 0x00000002
+#define PWM_FAULT_FAULT2 0x00000004
+#define PWM_FAULT_FAULT3 0x00000008
+#define PWM_FAULT_ACMP0 0x00010000
+#define PWM_FAULT_ACMP1 0x00020000
+#define PWM_FAULT_ACMP2 0x00040000
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_1.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_1 1
+
+//*****************************************************************************
+//
+// Defines to identify the sense of each of the external FAULTn signals
+//
+//*****************************************************************************
+#define PWM_FAULT0_SENSE_HIGH 0x00000000
+#define PWM_FAULT0_SENSE_LOW 0x00000001
+#define PWM_FAULT1_SENSE_HIGH 0x00000000
+#define PWM_FAULT1_SENSE_LOW 0x00000002
+#define PWM_FAULT2_SENSE_HIGH 0x00000000
+#define PWM_FAULT2_SENSE_LOW 0x00000004
+#define PWM_FAULT3_SENSE_HIGH 0x00000000
+#define PWM_FAULT3_SENSE_LOW 0x00000008
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulConfig);
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulPeriod);
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
+ unsigned long ulGen);
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
+ unsigned long ulWidth);
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
+ unsigned long ulPWMOut);
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned short usRise, unsigned short usFall);
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bEnable);
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bInvert);
+extern void PWMOutputFaultLevel(unsigned long ulBase,
+ unsigned long ulPWMOutBits,
+ tBoolean bDriveHigh);
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bFaultSuppress);
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
+ void (*pfnIntHandler)(void));
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
+extern void PWMFaultIntRegister(unsigned long ulBase,
+ void (*pfnIntHandler)(void));
+extern void PWMFaultIntUnregister(unsigned long ulBase);
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig);
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig);
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
+ tBoolean bMasked);
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulInts);
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMFaultIntClear(unsigned long ulBase);
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void PWMFaultIntClearExt(unsigned long ulBase,
+ unsigned long ulFaultInts);
+extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulMinFaultPeriod,
+ unsigned long ulFaultSenses);
+extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup,
+ unsigned long ulFaultTriggers);
+extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
+ unsigned long ulGen,
+ unsigned long ulGroup);
+extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
+ unsigned long ulGen,
+ unsigned long ulGroup);
+extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup,
+ unsigned long ulFaultTriggers);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PWM_H__
diff --git a/bsp/lm3s/Libraries/driverlib/qei.c b/bsp/lm3s/Libraries/driverlib/qei.c new file mode 100644 index 0000000000..36207582c7 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/qei.c @@ -0,0 +1,619 @@ +//*****************************************************************************
+//
+// qei.c - Driver for the Quadrature Encoder with Index.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup qei_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_qei.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/qei.h"
+
+//*****************************************************************************
+//
+//! Enables the quadrature encoder.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will enable operation of the quadrature encoder module. It must be
+//! configured before it is enabled.
+//!
+//! \sa QEIConfigure()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Enable the QEI module.
+ //
+ HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the quadrature encoder.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will disable operation of the quadrature encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Disable the QEI module.
+ //
+ HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Configures the quadrature encoder.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulConfig is the configuration for the quadrature encoder. See below
+//! for a description of this parameter.
+//! \param ulMaxPosition specifies the maximum position value.
+//!
+//! This will configure the operation of the quadrature encoder. The
+//! \e ulConfig parameter provides the configuration of the encoder and is the
+//! logical OR of several values:
+//!
+//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges
+//! on channel A or on both channels A and B should be counted by the
+//! position integrator and velocity accumulator.
+//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the
+//! position integrator should be reset when the index pulse is detected.
+//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if
+//! quadrature signals are being provided on ChA and ChB, or if a direction
+//! signal and a clock are being provided instead.
+//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
+//! provided on ChA and ChB should be swapped before being processed.
+//!
+//! \e ulMaxPosition is the maximum value of the position integrator, and is
+//! the value used to reset the position capture when in index reset mode and
+//! moving in the reverse (negative) direction.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxPosition)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Write the new configuration to the hardware.
+ //
+ HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
+ ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |
+ QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |
+ ulConfig);
+
+ //
+ // Set the maximum position.
+ //
+ HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition;
+}
+
+//*****************************************************************************
+//
+//! Gets the current encoder position.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the current position of the encoder. Depending upon the
+//! configuration of the encoder, and the incident of an index pulse, this
+//! value may or may not contain the expected data (that is, if in reset on
+//! index mode, if an index pulse has not been encountered, the position
+//! counter will not be aligned with the index pulse yet).
+//!
+//! \return The current position of the encoder.
+//
+//*****************************************************************************
+unsigned long
+QEIPositionGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the current position counter.
+ //
+ return(HWREG(ulBase + QEI_O_POS));
+}
+
+//*****************************************************************************
+//
+//! Sets the current encoder position.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulPosition is the new position for the encoder.
+//!
+//! This sets the current position of the encoder; the encoder position will
+//! then be measured relative to this value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Set the position counter.
+ //
+ HWREG(ulBase + QEI_O_POS) = ulPosition;
+}
+
+//*****************************************************************************
+//
+//! Gets the current direction of rotation.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the current direction of rotation. In this case, current
+//! means the most recently detected direction of the encoder; it may not be
+//! presently moving but this is the direction it last moved before it stopped.
+//!
+//! \return Returns 1 if moving in the forward direction or -1 if moving in the
+//! reverse direction.
+//
+//*****************************************************************************
+long
+QEIDirectionGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the direction of rotation.
+ //
+ return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the encoder error indicator.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the error indicator for the quadrature encoder. It is an
+//! error for both of the signals of the quadrature input to change at the same
+//! time.
+//!
+//! \return Returns \b true if an error has occurred and \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+QEIErrorGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the error indicator.
+ //
+ return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Enables the velocity capture.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will enable operation of the velocity capture in the quadrature
+//! encoder module. It must be configured before it is enabled. Velocity
+//! capture will not occur if the quadrature encoder is not enabled.
+//!
+//! \sa QEIVelocityConfigure() and QEIEnable()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Enable the velocity capture.
+ //
+ HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the velocity capture.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will disable operation of the velocity capture in the quadrature
+//! encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Disable the velocity capture.
+ //
+ HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN);
+}
+
+//*****************************************************************************
+//
+//! Configures the velocity capture.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulPreDiv specifies the predivider applied to the input quadrature
+//! signal before it is counted; can be one of \b QEI_VELDIV_1,
+//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16,
+//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128.
+//! \param ulPeriod specifies the number of clock ticks over which to measure
+//! the velocity; must be non-zero.
+//!
+//! This will configure the operation of the velocity capture portion of the
+//! quadrature encoder. The position increment signal is predivided as
+//! specified by \e ulPreDiv before being accumulated by the velocity capture.
+//! The divided signal is accumulated over \e ulPeriod system clock before
+//! being saved and resetting the accumulator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
+ unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+ ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M)));
+ ASSERT(ulPeriod != 0);
+
+ //
+ // Set the velocity predivider.
+ //
+ HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
+ ~(QEI_CTL_VELDIV_M)) | ulPreDiv);
+
+ //
+ // Set the timer period.
+ //
+ HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the current encoder speed.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the current speed of the encoder. The value returned is the
+//! number of pulses detected in the specified time period; this number can be
+//! multiplied by the number of time periods per second and divided by the
+//! number of pulses per revolution to obtain the number of revolutions per
+//! second.
+//!
+//! \return Returns the number of pulses captured in the given time period.
+//
+//*****************************************************************************
+unsigned long
+QEIVelocityGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the speed capture value.
+ //
+ return(HWREG(ulBase + QEI_O_SPEED));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the quadrature encoder interrupt.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! quadrature encoder interrupt occurs.
+//!
+//! This sets the handler to be called when a quadrature encoder interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().
+//! It is the interrupt handler's responsibility to clear the interrupt source
+//! via QEIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Determine the interrupt number based on the QEI module.
+ //
+ ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the quadrature encoder interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the quadrature encoder interrupt.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This function will clear the handler to be called when a quadrature encoder
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Determine the interrupt number based on the QEI module.
+ //
+ ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual quadrature encoder interrupt sources.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
+//! \b QEI_INTINDEX values.
+//!
+//! Enables the indicated quadrature encoder interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual quadrature encoder interrupt sources.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
+//! \b QEI_INTINDEX values.
+//!
+//! Disables the indicated quadrature encoder interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the quadrature encoder module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
+//
+//*****************************************************************************
+unsigned long
+QEIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + QEI_O_ISC));
+ }
+ else
+ {
+ return(HWREG(ulBase + QEI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears quadrature encoder interrupt sources.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
+//! \b QEI_INTINDEX values.
+//!
+//! The specified quadrature encoder interrupt sources are cleared, so that
+//! they no longer assert. This must be done in the interrupt handler to keep
+//! it from being called again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + QEI_O_ISC) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/qei.h b/bsp/lm3s/Libraries/driverlib/qei.h new file mode 100644 index 0000000000..4749f02e59 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/qei.h @@ -0,0 +1,115 @@ +//*****************************************************************************
+//
+// qei.h - Prototypes for the Quadrature Encoder Driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __QEI_H__
+#define __QEI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIConfigure as the ulConfig paramater.
+//
+//*****************************************************************************
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
+//
+//*****************************************************************************
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
+//
+//*****************************************************************************
+#define QEI_INTERROR 0x00000008 // Phase error detected
+#define QEI_INTDIR 0x00000004 // Direction change
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired
+#define QEI_INTINDEX 0x00000001 // Index pulse detected
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void QEIEnable(unsigned long ulBase);
+extern void QEIDisable(unsigned long ulBase);
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxPosition);
+extern unsigned long QEIPositionGet(unsigned long ulBase);
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
+extern long QEIDirectionGet(unsigned long ulBase);
+extern tBoolean QEIErrorGet(unsigned long ulBase);
+extern void QEIVelocityEnable(unsigned long ulBase);
+extern void QEIVelocityDisable(unsigned long ulBase);
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
+ unsigned long ulPeriod);
+extern unsigned long QEIVelocityGet(unsigned long ulBase);
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void QEIIntUnregister(unsigned long ulBase);
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __QEI_H__
diff --git a/bsp/lm3s/Libraries/driverlib/readme.txt b/bsp/lm3s/Libraries/driverlib/readme.txt new file mode 100644 index 0000000000..505472b922 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/readme.txt @@ -0,0 +1,24 @@ +This project will build the Stellaris Peripheral Driver Library.
+
+-------------------------------------------------------------------------------
+
+Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
+Software License Agreement
+
+Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+exclusively on LMI's microcontroller products.
+
+The software is owned by LMI and/or its suppliers, and is protected under
+applicable copyright laws. All rights are reserved. You may not combine
+this software with "viral" open-source software in order to form a larger
+program. Any use in violation of the foregoing restrictions may subject
+the user to criminal sanctions under applicable laws, as well as to civil
+liability for the breach of the terms and conditions of this license.
+
+THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
+This is part of revision 4694 of the Stellaris Peripheral Driver Library.
diff --git a/bsp/lm3s/Libraries/driverlib/rom.h b/bsp/lm3s/Libraries/driverlib/rom.h new file mode 100644 index 0000000000..211743f3bd --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/rom.h @@ -0,0 +1,2252 @@ +//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE ((unsigned long *)0x01000010)
+#define ROM_VERSION (ROM_APITABLE[0])
+#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14]))
+#define ROM_ETHERNETTABLE ((unsigned long *)(ROM_APITABLE[15]))
+#define ROM_USBTABLE ((unsigned long *)(ROM_APITABLE[16]))
+#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[17]))
+#define ROM_CANTABLE ((unsigned long *)(ROM_APITABLE[18]))
+#define ROM_HIBERNATETABLE ((unsigned long *)(ROM_APITABLE[19]))
+#define ROM_MPUTABLE ((unsigned long *)(ROM_APITABLE[20]))
+#define ROM_SOFTWARETABLE ((unsigned long *)(ROM_APITABLE[21]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceDataGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long *pulBuffer))ROM_ADCTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ tBoolean bMasked))ROM_ADCTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long ulTrigger, \
+ unsigned long ulPriority))ROM_ADCTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceStepConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long ulStep, \
+ unsigned long ulConfig))ROM_ADCTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceOverflow \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceOverflowClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceUnderflow \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCSequenceUnderflowClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCProcessorTrigger \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ADCHardwareOversampleConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFactor))ROM_ADCTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CAN API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntClr))ROM_CANTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANInit \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANEnable \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANDisable \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANBitTimingSet \
+ ((void (*)(unsigned long ulBase, \
+ tCANBitClkParms *pClkParms))ROM_CANTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANBitTimingGet \
+ ((void (*)(unsigned long ulBase, \
+ tCANBitClkParms *pClkParms))ROM_CANTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANMessageSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID, \
+ tCANMsgObject *pMsgObject, \
+ tMsgObjType eMsgType))ROM_CANTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANMessageGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID, \
+ tCANMsgObject *pMsgObject, \
+ tBoolean bClrPendingInt))ROM_CANTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANStatusGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tCANStsReg eStatusReg))ROM_CANTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANMessageClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID))ROM_CANTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CANTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CANTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tCANIntStsReg eIntStsReg))ROM_CANTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANRetryGet \
+ ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANRetrySet \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bAutoRetry))ROM_CANTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_CANErrCntrGet \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long *pulRxCount, \
+ unsigned long *pulTxCount))ROM_CANTABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Comparator API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ unsigned long ulConfig))ROM_COMPARATORTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorRefSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRef))ROM_COMPARATORTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorValueGet \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_ComparatorIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ tBoolean bMasked))ROM_COMPARATORTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Ethernet API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetInitExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEthClk))ROM_ETHERNETTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_ETHERNETTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetConfigGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetMACAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetMACAddrGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetEnable \
+ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetDisable \
+ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPacketPut \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_ETHERNETTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPHYWrite \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucRegAddr, \
+ unsigned long ulData))ROM_ETHERNETTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_EthernetPHYRead \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned char ucRegAddr))ROM_ETHERNETTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateEthernet \
+ ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Flash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProgram \
+ ((long (*)(unsigned long *pulData, \
+ unsigned long ulAddress, \
+ unsigned long ulCount))ROM_FLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUsecGet \
+ ((unsigned long (*)(void))ROM_FLASHTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUsecSet \
+ ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashErase \
+ ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProtectGet \
+ ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProtectSet \
+ ((long (*)(unsigned long ulAddress, \
+ tFlashProtection eProtect))ROM_FLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashProtectSave \
+ ((long (*)(void))ROM_FLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUserGet \
+ ((long (*)(unsigned long *pulUser0, \
+ unsigned long *pulUser1))ROM_FLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUserSet \
+ ((long (*)(unsigned long ulUser0, \
+ unsigned long ulUser1))ROM_FLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashUserSave \
+ ((long (*)(void))ROM_FLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntGetStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_FlashIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinWrite \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned char ucVal))ROM_GPIOTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIODirModeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulPinIO))ROM_GPIOTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIODirModeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOIntTypeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulIntType))ROM_GPIOTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOIntTypeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPadConfigSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulStrength, \
+ unsigned long ulPadType))ROM_GPIOTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPadConfigGet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPin, \
+ unsigned long *pulStrength, \
+ unsigned long *pulPadType))ROM_GPIOTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntEnable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntDisable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntStatus \
+ ((long (*)(unsigned long ulPort, \
+ tBoolean bMasked))ROM_GPIOTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinIntClear \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinRead \
+ ((long (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeCAN \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeComparator \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeGPIOInput \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeGPIOOutput \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeI2C \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypePWM \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeQEI \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeSSI \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeTimer \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeUART \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeGPIOOutputOD \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeADC \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_GPIOPinTypeUSBDigital \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Hibernate API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateEnableExpClk \
+ ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateDisable \
+ ((void (*)(void))ROM_HIBERNATETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateClockSelect \
+ ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCEnable \
+ ((void (*)(void))ROM_HIBERNATETABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCDisable \
+ ((void (*)(void))ROM_HIBERNATETABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateWakeSet \
+ ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateWakeGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateLowBatSet \
+ ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateLowBatGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCSet \
+ ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch0Set \
+ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch0Get \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch1Set \
+ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCMatch1Get \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCTrimSet \
+ ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRTCTrimGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateDataSet \
+ ((void (*)(unsigned long *pulData, \
+ unsigned long ulCount))ROM_HIBERNATETABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateDataGet \
+ ((void (*)(unsigned long *pulData, \
+ unsigned long ulCount))ROM_HIBERNATETABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateRequest \
+ ((void (*)(void))ROM_HIBERNATETABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_HibernateIsActive \
+ ((unsigned int (*)(void))ROM_HIBERNATETABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterInitExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulI2CClk, \
+ tBoolean bFast))ROM_I2CTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveInit \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucSlaveAddr))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterIntClear \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveIntClear \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterSlaveAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucSlaveAddr, \
+ tBoolean bReceive))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterBusBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterControl \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulCmd))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterErr \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CMasterDataGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_I2CSlaveDataGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateI2C \
+ ((void (*)(void))ROM_I2CTABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntEnable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntMasterEnable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntMasterDisable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntDisable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPriorityGroupingSet \
+ ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPriorityGroupingGet \
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPrioritySet \
+ ((void (*)(unsigned long ulInterrupt, \
+ unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_IntPriorityGet \
+ ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the MPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPUEnable \
+ ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPUDisable \
+ ((void (*)(void))ROM_MPUTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionCountGet \
+ ((unsigned long (*)(void))ROM_MPUTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionEnable \
+ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionDisable \
+ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionSet \
+ ((void (*)(unsigned long ulRegion, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_MPUTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_MPURegionGet \
+ ((void (*)(unsigned long ulRegion, \
+ unsigned long *pulAddr, \
+ unsigned long *pulFlags))ROM_MPUTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PWM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMPulseWidthSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOut, \
+ unsigned long ulWidth))ROM_PWMTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulConfig))ROM_PWMTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenPeriodSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulPeriod))ROM_PWMTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenPeriodGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMPulseWidthGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulPWMOut))ROM_PWMTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMDeadBandEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned short usRise, \
+ unsigned short usFall))ROM_PWMTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMDeadBandDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMSyncUpdate \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenBits))ROM_PWMTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMSyncTimeBase \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenBits))ROM_PWMTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputState \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bEnable))ROM_PWMTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputInvert \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bInvert))ROM_PWMTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputFault \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bFaultSuppress))ROM_PWMTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntTrigEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulIntTrig))ROM_PWMTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntTrigDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulIntTrig))ROM_PWMTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ tBoolean bMasked))ROM_PWMTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulInts))ROM_PWMTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenFault))ROM_PWMTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenFault))ROM_PWMTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMFaultIntClear \
+ ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_PWMTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMOutputFaultLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bDriveHigh))ROM_PWMTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMFaultIntClearExt \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFaultInts))ROM_PWMTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulMinFaultPeriod, \
+ unsigned long ulFaultSenses))ROM_PWMTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultTriggerSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup, \
+ unsigned long ulFaultTriggers))ROM_PWMTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultTriggerGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup))ROM_PWMTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup))ROM_PWMTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_PWMGenFaultClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup, \
+ unsigned long ulFaultTriggers))ROM_PWMTABLE[28])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the QEI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIPositionGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIEnable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIDisable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig, \
+ unsigned long ulMaxPosition))ROM_QEITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIPositionSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPosition))ROM_QEITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIDirectionGet \
+ ((long (*)(unsigned long ulBase))ROM_QEITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIErrorGet \
+ ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityEnable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityDisable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPreDiv, \
+ unsigned long ulPeriod))ROM_QEITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIVelocityGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_QEITABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_QEIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SSI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SSITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSSIClk, \
+ unsigned long ulProtocol, \
+ unsigned long ulMode, \
+ unsigned long ulBitRate, \
+ unsigned long ulDataWidth))ROM_SSITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIEnable \
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDisable \
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_SSITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SSITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SSITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SSITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateSSI \
+ ((void (*)(void))ROM_SSITABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_SSITABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SSIDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_SSITABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlSleep \
+ ((void (*)(void))ROM_SYSCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlSRAMSizeGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlFlashSizeGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPinPresent \
+ ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralPresent \
+ ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralReset \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralSleepEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralSleepDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralDeepSleepEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralDeepSleepDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPeripheralClockGating \
+ ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntEnable \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntDisable \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntClear \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlLDOSet \
+ ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlLDOGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlReset \
+ ((void (*)(void))ROM_SYSCTLTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlDeepSleep \
+ ((void (*)(void))ROM_SYSCTLTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlResetCauseGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlResetCauseClear \
+ ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlClockSet \
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlClockGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[24])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPWMClockSet \
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlPWMClockGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[26])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlADCSpeedSet \
+ ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlADCSpeedGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[28])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlGPIOAHBEnable \
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlGPIOAHBDisable \
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlUSBPLLEnable \
+ ((void (*)(void))ROM_SYSCTLTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysCtlUSBPLLDisable \
+ ((void (*)(void))ROM_SYSCTLTABLE[32])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysTick API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickValueGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickIntEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickIntDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickPeriodSet \
+ ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_SysTickPeriodGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_TIMERTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bInvert))ROM_TIMERTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlTrigger \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bEnable))ROM_TIMERTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlEvent \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulEvent))ROM_TIMERTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerControlStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bStall))ROM_TIMERTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerRTCEnable \
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerRTCDisable \
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerPrescaleSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerPrescaleGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerLoadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerLoadGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerValueGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_TimerIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_TIMERTABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTParityModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulParity))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTParityModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTFIFOLevelSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulRxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTFIFOLevelGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulTxLevel, \
+ unsigned long *pulRxLevel))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long ulBaud, \
+ unsigned long ulConfig))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTConfigGetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long *pulBaud, \
+ unsigned long *pulConfig))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTEnableSIR \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bLowPower))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDisableSIR \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharsAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharGetNonBlocking \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharGet \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTCharPutNonBlocking \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTBreakCtl \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_UARTTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UpdateUART \
+ ((void (*)(void))ROM_UARTTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_UARTDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the uDMA API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelTransferSet \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulMode, \
+ void *pvSrcAddr, \
+ void *pvDstAddr, \
+ unsigned long ulTransferSize))ROM_UDMATABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAEnable \
+ ((void (*)(void))ROM_UDMATABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMADisable \
+ ((void (*)(void))ROM_UDMATABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAErrorStatusGet \
+ ((unsigned long (*)(void))ROM_UDMATABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAErrorStatusClear \
+ ((void (*)(void))ROM_UDMATABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelEnable \
+ ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelDisable \
+ ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelIsEnabled \
+ ((tBoolean (*)(unsigned long ulChannel))ROM_UDMATABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAControlBaseSet \
+ ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAControlBaseGet \
+ ((void * (*)(void))ROM_UDMATABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelRequest \
+ ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelAttributeEnable \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulAttr))ROM_UDMATABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelAttributeDisable \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulAttr))ROM_UDMATABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelAttributeGet \
+ ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelControlSet \
+ ((void (*)(unsigned long ulChannel, \
+ unsigned long ulControl))ROM_UDMATABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelSizeGet \
+ ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_uDMAChannelModeGet \
+ ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the USB API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevAddrGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulAddress))ROM_USBTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevConnect \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevDisconnect \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulMaxPacketSize, \
+ unsigned long ulFlags))ROM_USBTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointDataAck \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ tBoolean bIsLastPacket))ROM_USBTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointStallClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBDevEndpointStatusClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned char *pucData, \
+ unsigned long *pulSize))ROM_USBTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataPut \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned char *pucData, \
+ unsigned long ulSize))ROM_USBTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataSend \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulTransType))ROM_USBTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointDataToggleClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBEndpointStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOConfigGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long *pulFIFOAddress, \
+ unsigned long *pulFIFOSize, \
+ unsigned long ulFlags))ROM_USBTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFIFOAddress, \
+ unsigned long ulFIFOSize, \
+ unsigned long ulFlags))ROM_USBTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFIFOFlush \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBFrameNumberGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_USBTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulMaxPacketSize, \
+ unsigned long ulNAKPollInterval, \
+ unsigned long ulTargetEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointDataAck \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointDataToggle \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ tBoolean bDataToggle, \
+ unsigned long ulFlags))ROM_USBTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostEndpointStatusClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostHubAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostHubAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_USBTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrDisable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrEnable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrFaultConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_USBTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrFaultDisable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostPwrFaultEnable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[32])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostRequestIN \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[33])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostRequestStatus \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[34])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostReset \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bStart))ROM_USBTABLE[35])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostResume \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bStart))ROM_USBTABLE[36])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostSpeedGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBHostSuspend \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[38])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[39])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_USBIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[40])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogIntClear \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogRunning \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogResetEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogResetDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogLock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogUnlock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogLockState \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogReloadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogReloadGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogValueGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogStallEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_WatchdogStallDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Software API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_Crc16Array \
+ ((unsigned short (*)(unsigned long ulWordLen, \
+ unsigned long *pulData))ROM_SOFTWARETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_Crc16Array3 \
+ ((void (*)(unsigned long ulWordLen, \
+ unsigned long *pulData, \
+ unsigned short *pusCrc3))ROM_SOFTWARETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1)
+#define ROM_pvAESTable \
+ ((void *)&(ROM_SOFTWARETABLE[7]))
+#endif
+
+#endif // __ROM_H__
diff --git a/bsp/lm3s/Libraries/driverlib/rom_map.h b/bsp/lm3s/Libraries/driverlib/rom_map.h new file mode 100644 index 0000000000..2a9d296641 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/rom_map.h @@ -0,0 +1,2763 @@ +//*****************************************************************************
+//
+// rom_map.h - Macros to facilitate calling functions in the ROM when they are
+// available and in flash otherwise.
+//
+// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_MAP_H__
+#define __ROM_MAP_H__
+
+//*****************************************************************************
+//
+// Macros for the ADC API.
+//
+//*****************************************************************************
+#ifdef ROM_ADCSequenceDataGet
+#define MAP_ADCSequenceDataGet \
+ ROM_ADCSequenceDataGet
+#else
+#define MAP_ADCSequenceDataGet \
+ ADCSequenceDataGet
+#endif
+#ifdef ROM_ADCIntDisable
+#define MAP_ADCIntDisable \
+ ROM_ADCIntDisable
+#else
+#define MAP_ADCIntDisable \
+ ADCIntDisable
+#endif
+#ifdef ROM_ADCIntEnable
+#define MAP_ADCIntEnable \
+ ROM_ADCIntEnable
+#else
+#define MAP_ADCIntEnable \
+ ADCIntEnable
+#endif
+#ifdef ROM_ADCIntStatus
+#define MAP_ADCIntStatus \
+ ROM_ADCIntStatus
+#else
+#define MAP_ADCIntStatus \
+ ADCIntStatus
+#endif
+#ifdef ROM_ADCIntClear
+#define MAP_ADCIntClear \
+ ROM_ADCIntClear
+#else
+#define MAP_ADCIntClear \
+ ADCIntClear
+#endif
+#ifdef ROM_ADCSequenceEnable
+#define MAP_ADCSequenceEnable \
+ ROM_ADCSequenceEnable
+#else
+#define MAP_ADCSequenceEnable \
+ ADCSequenceEnable
+#endif
+#ifdef ROM_ADCSequenceDisable
+#define MAP_ADCSequenceDisable \
+ ROM_ADCSequenceDisable
+#else
+#define MAP_ADCSequenceDisable \
+ ADCSequenceDisable
+#endif
+#ifdef ROM_ADCSequenceConfigure
+#define MAP_ADCSequenceConfigure \
+ ROM_ADCSequenceConfigure
+#else
+#define MAP_ADCSequenceConfigure \
+ ADCSequenceConfigure
+#endif
+#ifdef ROM_ADCSequenceStepConfigure
+#define MAP_ADCSequenceStepConfigure \
+ ROM_ADCSequenceStepConfigure
+#else
+#define MAP_ADCSequenceStepConfigure \
+ ADCSequenceStepConfigure
+#endif
+#ifdef ROM_ADCSequenceOverflow
+#define MAP_ADCSequenceOverflow \
+ ROM_ADCSequenceOverflow
+#else
+#define MAP_ADCSequenceOverflow \
+ ADCSequenceOverflow
+#endif
+#ifdef ROM_ADCSequenceOverflowClear
+#define MAP_ADCSequenceOverflowClear \
+ ROM_ADCSequenceOverflowClear
+#else
+#define MAP_ADCSequenceOverflowClear \
+ ADCSequenceOverflowClear
+#endif
+#ifdef ROM_ADCSequenceUnderflow
+#define MAP_ADCSequenceUnderflow \
+ ROM_ADCSequenceUnderflow
+#else
+#define MAP_ADCSequenceUnderflow \
+ ADCSequenceUnderflow
+#endif
+#ifdef ROM_ADCSequenceUnderflowClear
+#define MAP_ADCSequenceUnderflowClear \
+ ROM_ADCSequenceUnderflowClear
+#else
+#define MAP_ADCSequenceUnderflowClear \
+ ADCSequenceUnderflowClear
+#endif
+#ifdef ROM_ADCProcessorTrigger
+#define MAP_ADCProcessorTrigger \
+ ROM_ADCProcessorTrigger
+#else
+#define MAP_ADCProcessorTrigger \
+ ADCProcessorTrigger
+#endif
+#ifdef ROM_ADCHardwareOversampleConfigure
+#define MAP_ADCHardwareOversampleConfigure \
+ ROM_ADCHardwareOversampleConfigure
+#else
+#define MAP_ADCHardwareOversampleConfigure \
+ ADCHardwareOversampleConfigure
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CAN API.
+//
+//*****************************************************************************
+#ifdef ROM_CANIntClear
+#define MAP_CANIntClear \
+ ROM_CANIntClear
+#else
+#define MAP_CANIntClear \
+ CANIntClear
+#endif
+#ifdef ROM_CANInit
+#define MAP_CANInit \
+ ROM_CANInit
+#else
+#define MAP_CANInit \
+ CANInit
+#endif
+#ifdef ROM_CANEnable
+#define MAP_CANEnable \
+ ROM_CANEnable
+#else
+#define MAP_CANEnable \
+ CANEnable
+#endif
+#ifdef ROM_CANDisable
+#define MAP_CANDisable \
+ ROM_CANDisable
+#else
+#define MAP_CANDisable \
+ CANDisable
+#endif
+#ifdef ROM_CANBitTimingSet
+#define MAP_CANBitTimingSet \
+ ROM_CANBitTimingSet
+#else
+#define MAP_CANBitTimingSet \
+ CANBitTimingSet
+#endif
+#ifdef ROM_CANBitTimingGet
+#define MAP_CANBitTimingGet \
+ ROM_CANBitTimingGet
+#else
+#define MAP_CANBitTimingGet \
+ CANBitTimingGet
+#endif
+#ifdef ROM_CANMessageSet
+#define MAP_CANMessageSet \
+ ROM_CANMessageSet
+#else
+#define MAP_CANMessageSet \
+ CANMessageSet
+#endif
+#ifdef ROM_CANMessageGet
+#define MAP_CANMessageGet \
+ ROM_CANMessageGet
+#else
+#define MAP_CANMessageGet \
+ CANMessageGet
+#endif
+#ifdef ROM_CANStatusGet
+#define MAP_CANStatusGet \
+ ROM_CANStatusGet
+#else
+#define MAP_CANStatusGet \
+ CANStatusGet
+#endif
+#ifdef ROM_CANMessageClear
+#define MAP_CANMessageClear \
+ ROM_CANMessageClear
+#else
+#define MAP_CANMessageClear \
+ CANMessageClear
+#endif
+#ifdef ROM_CANIntEnable
+#define MAP_CANIntEnable \
+ ROM_CANIntEnable
+#else
+#define MAP_CANIntEnable \
+ CANIntEnable
+#endif
+#ifdef ROM_CANIntDisable
+#define MAP_CANIntDisable \
+ ROM_CANIntDisable
+#else
+#define MAP_CANIntDisable \
+ CANIntDisable
+#endif
+#ifdef ROM_CANIntStatus
+#define MAP_CANIntStatus \
+ ROM_CANIntStatus
+#else
+#define MAP_CANIntStatus \
+ CANIntStatus
+#endif
+#ifdef ROM_CANRetryGet
+#define MAP_CANRetryGet \
+ ROM_CANRetryGet
+#else
+#define MAP_CANRetryGet \
+ CANRetryGet
+#endif
+#ifdef ROM_CANRetrySet
+#define MAP_CANRetrySet \
+ ROM_CANRetrySet
+#else
+#define MAP_CANRetrySet \
+ CANRetrySet
+#endif
+#ifdef ROM_CANErrCntrGet
+#define MAP_CANErrCntrGet \
+ ROM_CANErrCntrGet
+#else
+#define MAP_CANErrCntrGet \
+ CANErrCntrGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Comparator API.
+//
+//*****************************************************************************
+#ifdef ROM_ComparatorIntClear
+#define MAP_ComparatorIntClear \
+ ROM_ComparatorIntClear
+#else
+#define MAP_ComparatorIntClear \
+ ComparatorIntClear
+#endif
+#ifdef ROM_ComparatorConfigure
+#define MAP_ComparatorConfigure \
+ ROM_ComparatorConfigure
+#else
+#define MAP_ComparatorConfigure \
+ ComparatorConfigure
+#endif
+#ifdef ROM_ComparatorRefSet
+#define MAP_ComparatorRefSet \
+ ROM_ComparatorRefSet
+#else
+#define MAP_ComparatorRefSet \
+ ComparatorRefSet
+#endif
+#ifdef ROM_ComparatorValueGet
+#define MAP_ComparatorValueGet \
+ ROM_ComparatorValueGet
+#else
+#define MAP_ComparatorValueGet \
+ ComparatorValueGet
+#endif
+#ifdef ROM_ComparatorIntEnable
+#define MAP_ComparatorIntEnable \
+ ROM_ComparatorIntEnable
+#else
+#define MAP_ComparatorIntEnable \
+ ComparatorIntEnable
+#endif
+#ifdef ROM_ComparatorIntDisable
+#define MAP_ComparatorIntDisable \
+ ROM_ComparatorIntDisable
+#else
+#define MAP_ComparatorIntDisable \
+ ComparatorIntDisable
+#endif
+#ifdef ROM_ComparatorIntStatus
+#define MAP_ComparatorIntStatus \
+ ROM_ComparatorIntStatus
+#else
+#define MAP_ComparatorIntStatus \
+ ComparatorIntStatus
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Ethernet API.
+//
+//*****************************************************************************
+#ifdef ROM_EthernetIntClear
+#define MAP_EthernetIntClear \
+ ROM_EthernetIntClear
+#else
+#define MAP_EthernetIntClear \
+ EthernetIntClear
+#endif
+#ifdef ROM_EthernetInitExpClk
+#define MAP_EthernetInitExpClk \
+ ROM_EthernetInitExpClk
+#else
+#define MAP_EthernetInitExpClk \
+ EthernetInitExpClk
+#endif
+#ifdef ROM_EthernetConfigSet
+#define MAP_EthernetConfigSet \
+ ROM_EthernetConfigSet
+#else
+#define MAP_EthernetConfigSet \
+ EthernetConfigSet
+#endif
+#ifdef ROM_EthernetConfigGet
+#define MAP_EthernetConfigGet \
+ ROM_EthernetConfigGet
+#else
+#define MAP_EthernetConfigGet \
+ EthernetConfigGet
+#endif
+#ifdef ROM_EthernetMACAddrSet
+#define MAP_EthernetMACAddrSet \
+ ROM_EthernetMACAddrSet
+#else
+#define MAP_EthernetMACAddrSet \
+ EthernetMACAddrSet
+#endif
+#ifdef ROM_EthernetMACAddrGet
+#define MAP_EthernetMACAddrGet \
+ ROM_EthernetMACAddrGet
+#else
+#define MAP_EthernetMACAddrGet \
+ EthernetMACAddrGet
+#endif
+#ifdef ROM_EthernetEnable
+#define MAP_EthernetEnable \
+ ROM_EthernetEnable
+#else
+#define MAP_EthernetEnable \
+ EthernetEnable
+#endif
+#ifdef ROM_EthernetDisable
+#define MAP_EthernetDisable \
+ ROM_EthernetDisable
+#else
+#define MAP_EthernetDisable \
+ EthernetDisable
+#endif
+#ifdef ROM_EthernetPacketAvail
+#define MAP_EthernetPacketAvail \
+ ROM_EthernetPacketAvail
+#else
+#define MAP_EthernetPacketAvail \
+ EthernetPacketAvail
+#endif
+#ifdef ROM_EthernetSpaceAvail
+#define MAP_EthernetSpaceAvail \
+ ROM_EthernetSpaceAvail
+#else
+#define MAP_EthernetSpaceAvail \
+ EthernetSpaceAvail
+#endif
+#ifdef ROM_EthernetPacketGetNonBlocking
+#define MAP_EthernetPacketGetNonBlocking \
+ ROM_EthernetPacketGetNonBlocking
+#else
+#define MAP_EthernetPacketGetNonBlocking \
+ EthernetPacketGetNonBlocking
+#endif
+#ifdef ROM_EthernetPacketGet
+#define MAP_EthernetPacketGet \
+ ROM_EthernetPacketGet
+#else
+#define MAP_EthernetPacketGet \
+ EthernetPacketGet
+#endif
+#ifdef ROM_EthernetPacketPutNonBlocking
+#define MAP_EthernetPacketPutNonBlocking \
+ ROM_EthernetPacketPutNonBlocking
+#else
+#define MAP_EthernetPacketPutNonBlocking \
+ EthernetPacketPutNonBlocking
+#endif
+#ifdef ROM_EthernetPacketPut
+#define MAP_EthernetPacketPut \
+ ROM_EthernetPacketPut
+#else
+#define MAP_EthernetPacketPut \
+ EthernetPacketPut
+#endif
+#ifdef ROM_EthernetIntEnable
+#define MAP_EthernetIntEnable \
+ ROM_EthernetIntEnable
+#else
+#define MAP_EthernetIntEnable \
+ EthernetIntEnable
+#endif
+#ifdef ROM_EthernetIntDisable
+#define MAP_EthernetIntDisable \
+ ROM_EthernetIntDisable
+#else
+#define MAP_EthernetIntDisable \
+ EthernetIntDisable
+#endif
+#ifdef ROM_EthernetIntStatus
+#define MAP_EthernetIntStatus \
+ ROM_EthernetIntStatus
+#else
+#define MAP_EthernetIntStatus \
+ EthernetIntStatus
+#endif
+#ifdef ROM_EthernetPHYWrite
+#define MAP_EthernetPHYWrite \
+ ROM_EthernetPHYWrite
+#else
+#define MAP_EthernetPHYWrite \
+ EthernetPHYWrite
+#endif
+#ifdef ROM_EthernetPHYRead
+#define MAP_EthernetPHYRead \
+ ROM_EthernetPHYRead
+#else
+#define MAP_EthernetPHYRead \
+ EthernetPHYRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Flash API.
+//
+//*****************************************************************************
+#ifdef ROM_FlashProgram
+#define MAP_FlashProgram \
+ ROM_FlashProgram
+#else
+#define MAP_FlashProgram \
+ FlashProgram
+#endif
+#ifdef ROM_FlashUsecGet
+#define MAP_FlashUsecGet \
+ ROM_FlashUsecGet
+#else
+#define MAP_FlashUsecGet \
+ FlashUsecGet
+#endif
+#ifdef ROM_FlashUsecSet
+#define MAP_FlashUsecSet \
+ ROM_FlashUsecSet
+#else
+#define MAP_FlashUsecSet \
+ FlashUsecSet
+#endif
+#ifdef ROM_FlashErase
+#define MAP_FlashErase \
+ ROM_FlashErase
+#else
+#define MAP_FlashErase \
+ FlashErase
+#endif
+#ifdef ROM_FlashProtectGet
+#define MAP_FlashProtectGet \
+ ROM_FlashProtectGet
+#else
+#define MAP_FlashProtectGet \
+ FlashProtectGet
+#endif
+#ifdef ROM_FlashProtectSet
+#define MAP_FlashProtectSet \
+ ROM_FlashProtectSet
+#else
+#define MAP_FlashProtectSet \
+ FlashProtectSet
+#endif
+#ifdef ROM_FlashProtectSave
+#define MAP_FlashProtectSave \
+ ROM_FlashProtectSave
+#else
+#define MAP_FlashProtectSave \
+ FlashProtectSave
+#endif
+#ifdef ROM_FlashUserGet
+#define MAP_FlashUserGet \
+ ROM_FlashUserGet
+#else
+#define MAP_FlashUserGet \
+ FlashUserGet
+#endif
+#ifdef ROM_FlashUserSet
+#define MAP_FlashUserSet \
+ ROM_FlashUserSet
+#else
+#define MAP_FlashUserSet \
+ FlashUserSet
+#endif
+#ifdef ROM_FlashUserSave
+#define MAP_FlashUserSave \
+ ROM_FlashUserSave
+#else
+#define MAP_FlashUserSave \
+ FlashUserSave
+#endif
+#ifdef ROM_FlashIntEnable
+#define MAP_FlashIntEnable \
+ ROM_FlashIntEnable
+#else
+#define MAP_FlashIntEnable \
+ FlashIntEnable
+#endif
+#ifdef ROM_FlashIntDisable
+#define MAP_FlashIntDisable \
+ ROM_FlashIntDisable
+#else
+#define MAP_FlashIntDisable \
+ FlashIntDisable
+#endif
+#ifdef ROM_FlashIntGetStatus
+#define MAP_FlashIntGetStatus \
+ ROM_FlashIntGetStatus
+#else
+#define MAP_FlashIntGetStatus \
+ FlashIntGetStatus
+#endif
+#ifdef ROM_FlashIntClear
+#define MAP_FlashIntClear \
+ ROM_FlashIntClear
+#else
+#define MAP_FlashIntClear \
+ FlashIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the GPIO API.
+//
+//*****************************************************************************
+#ifdef ROM_GPIOPinWrite
+#define MAP_GPIOPinWrite \
+ ROM_GPIOPinWrite
+#else
+#define MAP_GPIOPinWrite \
+ GPIOPinWrite
+#endif
+#ifdef ROM_GPIODirModeSet
+#define MAP_GPIODirModeSet \
+ ROM_GPIODirModeSet
+#else
+#define MAP_GPIODirModeSet \
+ GPIODirModeSet
+#endif
+#ifdef ROM_GPIODirModeGet
+#define MAP_GPIODirModeGet \
+ ROM_GPIODirModeGet
+#else
+#define MAP_GPIODirModeGet \
+ GPIODirModeGet
+#endif
+#ifdef ROM_GPIOIntTypeSet
+#define MAP_GPIOIntTypeSet \
+ ROM_GPIOIntTypeSet
+#else
+#define MAP_GPIOIntTypeSet \
+ GPIOIntTypeSet
+#endif
+#ifdef ROM_GPIOIntTypeGet
+#define MAP_GPIOIntTypeGet \
+ ROM_GPIOIntTypeGet
+#else
+#define MAP_GPIOIntTypeGet \
+ GPIOIntTypeGet
+#endif
+#ifdef ROM_GPIOPadConfigSet
+#define MAP_GPIOPadConfigSet \
+ ROM_GPIOPadConfigSet
+#else
+#define MAP_GPIOPadConfigSet \
+ GPIOPadConfigSet
+#endif
+#ifdef ROM_GPIOPadConfigGet
+#define MAP_GPIOPadConfigGet \
+ ROM_GPIOPadConfigGet
+#else
+#define MAP_GPIOPadConfigGet \
+ GPIOPadConfigGet
+#endif
+#ifdef ROM_GPIOPinIntEnable
+#define MAP_GPIOPinIntEnable \
+ ROM_GPIOPinIntEnable
+#else
+#define MAP_GPIOPinIntEnable \
+ GPIOPinIntEnable
+#endif
+#ifdef ROM_GPIOPinIntDisable
+#define MAP_GPIOPinIntDisable \
+ ROM_GPIOPinIntDisable
+#else
+#define MAP_GPIOPinIntDisable \
+ GPIOPinIntDisable
+#endif
+#ifdef ROM_GPIOPinIntStatus
+#define MAP_GPIOPinIntStatus \
+ ROM_GPIOPinIntStatus
+#else
+#define MAP_GPIOPinIntStatus \
+ GPIOPinIntStatus
+#endif
+#ifdef ROM_GPIOPinIntClear
+#define MAP_GPIOPinIntClear \
+ ROM_GPIOPinIntClear
+#else
+#define MAP_GPIOPinIntClear \
+ GPIOPinIntClear
+#endif
+#ifdef ROM_GPIOPinRead
+#define MAP_GPIOPinRead \
+ ROM_GPIOPinRead
+#else
+#define MAP_GPIOPinRead \
+ GPIOPinRead
+#endif
+#ifdef ROM_GPIOPinTypeCAN
+#define MAP_GPIOPinTypeCAN \
+ ROM_GPIOPinTypeCAN
+#else
+#define MAP_GPIOPinTypeCAN \
+ GPIOPinTypeCAN
+#endif
+#ifdef ROM_GPIOPinTypeComparator
+#define MAP_GPIOPinTypeComparator \
+ ROM_GPIOPinTypeComparator
+#else
+#define MAP_GPIOPinTypeComparator \
+ GPIOPinTypeComparator
+#endif
+#ifdef ROM_GPIOPinTypeGPIOInput
+#define MAP_GPIOPinTypeGPIOInput \
+ ROM_GPIOPinTypeGPIOInput
+#else
+#define MAP_GPIOPinTypeGPIOInput \
+ GPIOPinTypeGPIOInput
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutput
+#define MAP_GPIOPinTypeGPIOOutput \
+ ROM_GPIOPinTypeGPIOOutput
+#else
+#define MAP_GPIOPinTypeGPIOOutput \
+ GPIOPinTypeGPIOOutput
+#endif
+#ifdef ROM_GPIOPinTypeI2C
+#define MAP_GPIOPinTypeI2C \
+ ROM_GPIOPinTypeI2C
+#else
+#define MAP_GPIOPinTypeI2C \
+ GPIOPinTypeI2C
+#endif
+#ifdef ROM_GPIOPinTypePWM
+#define MAP_GPIOPinTypePWM \
+ ROM_GPIOPinTypePWM
+#else
+#define MAP_GPIOPinTypePWM \
+ GPIOPinTypePWM
+#endif
+#ifdef ROM_GPIOPinTypeQEI
+#define MAP_GPIOPinTypeQEI \
+ ROM_GPIOPinTypeQEI
+#else
+#define MAP_GPIOPinTypeQEI \
+ GPIOPinTypeQEI
+#endif
+#ifdef ROM_GPIOPinTypeSSI
+#define MAP_GPIOPinTypeSSI \
+ ROM_GPIOPinTypeSSI
+#else
+#define MAP_GPIOPinTypeSSI \
+ GPIOPinTypeSSI
+#endif
+#ifdef ROM_GPIOPinTypeTimer
+#define MAP_GPIOPinTypeTimer \
+ ROM_GPIOPinTypeTimer
+#else
+#define MAP_GPIOPinTypeTimer \
+ GPIOPinTypeTimer
+#endif
+#ifdef ROM_GPIOPinTypeUART
+#define MAP_GPIOPinTypeUART \
+ ROM_GPIOPinTypeUART
+#else
+#define MAP_GPIOPinTypeUART \
+ GPIOPinTypeUART
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutputOD
+#define MAP_GPIOPinTypeGPIOOutputOD \
+ ROM_GPIOPinTypeGPIOOutputOD
+#else
+#define MAP_GPIOPinTypeGPIOOutputOD \
+ GPIOPinTypeGPIOOutputOD
+#endif
+#ifdef ROM_GPIOPinTypeADC
+#define MAP_GPIOPinTypeADC \
+ ROM_GPIOPinTypeADC
+#else
+#define MAP_GPIOPinTypeADC \
+ GPIOPinTypeADC
+#endif
+#ifdef ROM_GPIOPinTypeUSBDigital
+#define MAP_GPIOPinTypeUSBDigital \
+ ROM_GPIOPinTypeUSBDigital
+#else
+#define MAP_GPIOPinTypeUSBDigital \
+ GPIOPinTypeUSBDigital
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Hibernate API.
+//
+//*****************************************************************************
+#ifdef ROM_HibernateIntClear
+#define MAP_HibernateIntClear \
+ ROM_HibernateIntClear
+#else
+#define MAP_HibernateIntClear \
+ HibernateIntClear
+#endif
+#ifdef ROM_HibernateEnableExpClk
+#define MAP_HibernateEnableExpClk \
+ ROM_HibernateEnableExpClk
+#else
+#define MAP_HibernateEnableExpClk \
+ HibernateEnableExpClk
+#endif
+#ifdef ROM_HibernateDisable
+#define MAP_HibernateDisable \
+ ROM_HibernateDisable
+#else
+#define MAP_HibernateDisable \
+ HibernateDisable
+#endif
+#ifdef ROM_HibernateClockSelect
+#define MAP_HibernateClockSelect \
+ ROM_HibernateClockSelect
+#else
+#define MAP_HibernateClockSelect \
+ HibernateClockSelect
+#endif
+#ifdef ROM_HibernateRTCEnable
+#define MAP_HibernateRTCEnable \
+ ROM_HibernateRTCEnable
+#else
+#define MAP_HibernateRTCEnable \
+ HibernateRTCEnable
+#endif
+#ifdef ROM_HibernateRTCDisable
+#define MAP_HibernateRTCDisable \
+ ROM_HibernateRTCDisable
+#else
+#define MAP_HibernateRTCDisable \
+ HibernateRTCDisable
+#endif
+#ifdef ROM_HibernateWakeSet
+#define MAP_HibernateWakeSet \
+ ROM_HibernateWakeSet
+#else
+#define MAP_HibernateWakeSet \
+ HibernateWakeSet
+#endif
+#ifdef ROM_HibernateWakeGet
+#define MAP_HibernateWakeGet \
+ ROM_HibernateWakeGet
+#else
+#define MAP_HibernateWakeGet \
+ HibernateWakeGet
+#endif
+#ifdef ROM_HibernateLowBatSet
+#define MAP_HibernateLowBatSet \
+ ROM_HibernateLowBatSet
+#else
+#define MAP_HibernateLowBatSet \
+ HibernateLowBatSet
+#endif
+#ifdef ROM_HibernateLowBatGet
+#define MAP_HibernateLowBatGet \
+ ROM_HibernateLowBatGet
+#else
+#define MAP_HibernateLowBatGet \
+ HibernateLowBatGet
+#endif
+#ifdef ROM_HibernateRTCSet
+#define MAP_HibernateRTCSet \
+ ROM_HibernateRTCSet
+#else
+#define MAP_HibernateRTCSet \
+ HibernateRTCSet
+#endif
+#ifdef ROM_HibernateRTCGet
+#define MAP_HibernateRTCGet \
+ ROM_HibernateRTCGet
+#else
+#define MAP_HibernateRTCGet \
+ HibernateRTCGet
+#endif
+#ifdef ROM_HibernateRTCMatch0Set
+#define MAP_HibernateRTCMatch0Set \
+ ROM_HibernateRTCMatch0Set
+#else
+#define MAP_HibernateRTCMatch0Set \
+ HibernateRTCMatch0Set
+#endif
+#ifdef ROM_HibernateRTCMatch0Get
+#define MAP_HibernateRTCMatch0Get \
+ ROM_HibernateRTCMatch0Get
+#else
+#define MAP_HibernateRTCMatch0Get \
+ HibernateRTCMatch0Get
+#endif
+#ifdef ROM_HibernateRTCMatch1Set
+#define MAP_HibernateRTCMatch1Set \
+ ROM_HibernateRTCMatch1Set
+#else
+#define MAP_HibernateRTCMatch1Set \
+ HibernateRTCMatch1Set
+#endif
+#ifdef ROM_HibernateRTCMatch1Get
+#define MAP_HibernateRTCMatch1Get \
+ ROM_HibernateRTCMatch1Get
+#else
+#define MAP_HibernateRTCMatch1Get \
+ HibernateRTCMatch1Get
+#endif
+#ifdef ROM_HibernateRTCTrimSet
+#define MAP_HibernateRTCTrimSet \
+ ROM_HibernateRTCTrimSet
+#else
+#define MAP_HibernateRTCTrimSet \
+ HibernateRTCTrimSet
+#endif
+#ifdef ROM_HibernateRTCTrimGet
+#define MAP_HibernateRTCTrimGet \
+ ROM_HibernateRTCTrimGet
+#else
+#define MAP_HibernateRTCTrimGet \
+ HibernateRTCTrimGet
+#endif
+#ifdef ROM_HibernateDataSet
+#define MAP_HibernateDataSet \
+ ROM_HibernateDataSet
+#else
+#define MAP_HibernateDataSet \
+ HibernateDataSet
+#endif
+#ifdef ROM_HibernateDataGet
+#define MAP_HibernateDataGet \
+ ROM_HibernateDataGet
+#else
+#define MAP_HibernateDataGet \
+ HibernateDataGet
+#endif
+#ifdef ROM_HibernateRequest
+#define MAP_HibernateRequest \
+ ROM_HibernateRequest
+#else
+#define MAP_HibernateRequest \
+ HibernateRequest
+#endif
+#ifdef ROM_HibernateIntEnable
+#define MAP_HibernateIntEnable \
+ ROM_HibernateIntEnable
+#else
+#define MAP_HibernateIntEnable \
+ HibernateIntEnable
+#endif
+#ifdef ROM_HibernateIntDisable
+#define MAP_HibernateIntDisable \
+ ROM_HibernateIntDisable
+#else
+#define MAP_HibernateIntDisable \
+ HibernateIntDisable
+#endif
+#ifdef ROM_HibernateIntStatus
+#define MAP_HibernateIntStatus \
+ ROM_HibernateIntStatus
+#else
+#define MAP_HibernateIntStatus \
+ HibernateIntStatus
+#endif
+#ifdef ROM_HibernateIsActive
+#define MAP_HibernateIsActive \
+ ROM_HibernateIsActive
+#else
+#define MAP_HibernateIsActive \
+ HibernateIsActive
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2C API.
+//
+//*****************************************************************************
+#ifdef ROM_I2CMasterDataPut
+#define MAP_I2CMasterDataPut \
+ ROM_I2CMasterDataPut
+#else
+#define MAP_I2CMasterDataPut \
+ I2CMasterDataPut
+#endif
+#ifdef ROM_I2CMasterInitExpClk
+#define MAP_I2CMasterInitExpClk \
+ ROM_I2CMasterInitExpClk
+#else
+#define MAP_I2CMasterInitExpClk \
+ I2CMasterInitExpClk
+#endif
+#ifdef ROM_I2CSlaveInit
+#define MAP_I2CSlaveInit \
+ ROM_I2CSlaveInit
+#else
+#define MAP_I2CSlaveInit \
+ I2CSlaveInit
+#endif
+#ifdef ROM_I2CMasterEnable
+#define MAP_I2CMasterEnable \
+ ROM_I2CMasterEnable
+#else
+#define MAP_I2CMasterEnable \
+ I2CMasterEnable
+#endif
+#ifdef ROM_I2CSlaveEnable
+#define MAP_I2CSlaveEnable \
+ ROM_I2CSlaveEnable
+#else
+#define MAP_I2CSlaveEnable \
+ I2CSlaveEnable
+#endif
+#ifdef ROM_I2CMasterDisable
+#define MAP_I2CMasterDisable \
+ ROM_I2CMasterDisable
+#else
+#define MAP_I2CMasterDisable \
+ I2CMasterDisable
+#endif
+#ifdef ROM_I2CSlaveDisable
+#define MAP_I2CSlaveDisable \
+ ROM_I2CSlaveDisable
+#else
+#define MAP_I2CSlaveDisable \
+ I2CSlaveDisable
+#endif
+#ifdef ROM_I2CMasterIntEnable
+#define MAP_I2CMasterIntEnable \
+ ROM_I2CMasterIntEnable
+#else
+#define MAP_I2CMasterIntEnable \
+ I2CMasterIntEnable
+#endif
+#ifdef ROM_I2CSlaveIntEnable
+#define MAP_I2CSlaveIntEnable \
+ ROM_I2CSlaveIntEnable
+#else
+#define MAP_I2CSlaveIntEnable \
+ I2CSlaveIntEnable
+#endif
+#ifdef ROM_I2CMasterIntDisable
+#define MAP_I2CMasterIntDisable \
+ ROM_I2CMasterIntDisable
+#else
+#define MAP_I2CMasterIntDisable \
+ I2CMasterIntDisable
+#endif
+#ifdef ROM_I2CSlaveIntDisable
+#define MAP_I2CSlaveIntDisable \
+ ROM_I2CSlaveIntDisable
+#else
+#define MAP_I2CSlaveIntDisable \
+ I2CSlaveIntDisable
+#endif
+#ifdef ROM_I2CMasterIntStatus
+#define MAP_I2CMasterIntStatus \
+ ROM_I2CMasterIntStatus
+#else
+#define MAP_I2CMasterIntStatus \
+ I2CMasterIntStatus
+#endif
+#ifdef ROM_I2CSlaveIntStatus
+#define MAP_I2CSlaveIntStatus \
+ ROM_I2CSlaveIntStatus
+#else
+#define MAP_I2CSlaveIntStatus \
+ I2CSlaveIntStatus
+#endif
+#ifdef ROM_I2CMasterIntClear
+#define MAP_I2CMasterIntClear \
+ ROM_I2CMasterIntClear
+#else
+#define MAP_I2CMasterIntClear \
+ I2CMasterIntClear
+#endif
+#ifdef ROM_I2CSlaveIntClear
+#define MAP_I2CSlaveIntClear \
+ ROM_I2CSlaveIntClear
+#else
+#define MAP_I2CSlaveIntClear \
+ I2CSlaveIntClear
+#endif
+#ifdef ROM_I2CMasterSlaveAddrSet
+#define MAP_I2CMasterSlaveAddrSet \
+ ROM_I2CMasterSlaveAddrSet
+#else
+#define MAP_I2CMasterSlaveAddrSet \
+ I2CMasterSlaveAddrSet
+#endif
+#ifdef ROM_I2CMasterBusy
+#define MAP_I2CMasterBusy \
+ ROM_I2CMasterBusy
+#else
+#define MAP_I2CMasterBusy \
+ I2CMasterBusy
+#endif
+#ifdef ROM_I2CMasterBusBusy
+#define MAP_I2CMasterBusBusy \
+ ROM_I2CMasterBusBusy
+#else
+#define MAP_I2CMasterBusBusy \
+ I2CMasterBusBusy
+#endif
+#ifdef ROM_I2CMasterControl
+#define MAP_I2CMasterControl \
+ ROM_I2CMasterControl
+#else
+#define MAP_I2CMasterControl \
+ I2CMasterControl
+#endif
+#ifdef ROM_I2CMasterErr
+#define MAP_I2CMasterErr \
+ ROM_I2CMasterErr
+#else
+#define MAP_I2CMasterErr \
+ I2CMasterErr
+#endif
+#ifdef ROM_I2CMasterDataGet
+#define MAP_I2CMasterDataGet \
+ ROM_I2CMasterDataGet
+#else
+#define MAP_I2CMasterDataGet \
+ I2CMasterDataGet
+#endif
+#ifdef ROM_I2CSlaveStatus
+#define MAP_I2CSlaveStatus \
+ ROM_I2CSlaveStatus
+#else
+#define MAP_I2CSlaveStatus \
+ I2CSlaveStatus
+#endif
+#ifdef ROM_I2CSlaveDataPut
+#define MAP_I2CSlaveDataPut \
+ ROM_I2CSlaveDataPut
+#else
+#define MAP_I2CSlaveDataPut \
+ I2CSlaveDataPut
+#endif
+#ifdef ROM_I2CSlaveDataGet
+#define MAP_I2CSlaveDataGet \
+ ROM_I2CSlaveDataGet
+#else
+#define MAP_I2CSlaveDataGet \
+ I2CSlaveDataGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Interrupt API.
+//
+//*****************************************************************************
+#ifdef ROM_IntEnable
+#define MAP_IntEnable \
+ ROM_IntEnable
+#else
+#define MAP_IntEnable \
+ IntEnable
+#endif
+#ifdef ROM_IntMasterEnable
+#define MAP_IntMasterEnable \
+ ROM_IntMasterEnable
+#else
+#define MAP_IntMasterEnable \
+ IntMasterEnable
+#endif
+#ifdef ROM_IntMasterDisable
+#define MAP_IntMasterDisable \
+ ROM_IntMasterDisable
+#else
+#define MAP_IntMasterDisable \
+ IntMasterDisable
+#endif
+#ifdef ROM_IntDisable
+#define MAP_IntDisable \
+ ROM_IntDisable
+#else
+#define MAP_IntDisable \
+ IntDisable
+#endif
+#ifdef ROM_IntPriorityGroupingSet
+#define MAP_IntPriorityGroupingSet \
+ ROM_IntPriorityGroupingSet
+#else
+#define MAP_IntPriorityGroupingSet \
+ IntPriorityGroupingSet
+#endif
+#ifdef ROM_IntPriorityGroupingGet
+#define MAP_IntPriorityGroupingGet \
+ ROM_IntPriorityGroupingGet
+#else
+#define MAP_IntPriorityGroupingGet \
+ IntPriorityGroupingGet
+#endif
+#ifdef ROM_IntPrioritySet
+#define MAP_IntPrioritySet \
+ ROM_IntPrioritySet
+#else
+#define MAP_IntPrioritySet \
+ IntPrioritySet
+#endif
+#ifdef ROM_IntPriorityGet
+#define MAP_IntPriorityGet \
+ ROM_IntPriorityGet
+#else
+#define MAP_IntPriorityGet \
+ IntPriorityGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the MPU API.
+//
+//*****************************************************************************
+#ifdef ROM_MPUEnable
+#define MAP_MPUEnable \
+ ROM_MPUEnable
+#else
+#define MAP_MPUEnable \
+ MPUEnable
+#endif
+#ifdef ROM_MPUDisable
+#define MAP_MPUDisable \
+ ROM_MPUDisable
+#else
+#define MAP_MPUDisable \
+ MPUDisable
+#endif
+#ifdef ROM_MPURegionCountGet
+#define MAP_MPURegionCountGet \
+ ROM_MPURegionCountGet
+#else
+#define MAP_MPURegionCountGet \
+ MPURegionCountGet
+#endif
+#ifdef ROM_MPURegionEnable
+#define MAP_MPURegionEnable \
+ ROM_MPURegionEnable
+#else
+#define MAP_MPURegionEnable \
+ MPURegionEnable
+#endif
+#ifdef ROM_MPURegionDisable
+#define MAP_MPURegionDisable \
+ ROM_MPURegionDisable
+#else
+#define MAP_MPURegionDisable \
+ MPURegionDisable
+#endif
+#ifdef ROM_MPURegionSet
+#define MAP_MPURegionSet \
+ ROM_MPURegionSet
+#else
+#define MAP_MPURegionSet \
+ MPURegionSet
+#endif
+#ifdef ROM_MPURegionGet
+#define MAP_MPURegionGet \
+ ROM_MPURegionGet
+#else
+#define MAP_MPURegionGet \
+ MPURegionGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PWM API.
+//
+//*****************************************************************************
+#ifdef ROM_PWMPulseWidthSet
+#define MAP_PWMPulseWidthSet \
+ ROM_PWMPulseWidthSet
+#else
+#define MAP_PWMPulseWidthSet \
+ PWMPulseWidthSet
+#endif
+#ifdef ROM_PWMGenConfigure
+#define MAP_PWMGenConfigure \
+ ROM_PWMGenConfigure
+#else
+#define MAP_PWMGenConfigure \
+ PWMGenConfigure
+#endif
+#ifdef ROM_PWMGenPeriodSet
+#define MAP_PWMGenPeriodSet \
+ ROM_PWMGenPeriodSet
+#else
+#define MAP_PWMGenPeriodSet \
+ PWMGenPeriodSet
+#endif
+#ifdef ROM_PWMGenPeriodGet
+#define MAP_PWMGenPeriodGet \
+ ROM_PWMGenPeriodGet
+#else
+#define MAP_PWMGenPeriodGet \
+ PWMGenPeriodGet
+#endif
+#ifdef ROM_PWMGenEnable
+#define MAP_PWMGenEnable \
+ ROM_PWMGenEnable
+#else
+#define MAP_PWMGenEnable \
+ PWMGenEnable
+#endif
+#ifdef ROM_PWMGenDisable
+#define MAP_PWMGenDisable \
+ ROM_PWMGenDisable
+#else
+#define MAP_PWMGenDisable \
+ PWMGenDisable
+#endif
+#ifdef ROM_PWMPulseWidthGet
+#define MAP_PWMPulseWidthGet \
+ ROM_PWMPulseWidthGet
+#else
+#define MAP_PWMPulseWidthGet \
+ PWMPulseWidthGet
+#endif
+#ifdef ROM_PWMDeadBandEnable
+#define MAP_PWMDeadBandEnable \
+ ROM_PWMDeadBandEnable
+#else
+#define MAP_PWMDeadBandEnable \
+ PWMDeadBandEnable
+#endif
+#ifdef ROM_PWMDeadBandDisable
+#define MAP_PWMDeadBandDisable \
+ ROM_PWMDeadBandDisable
+#else
+#define MAP_PWMDeadBandDisable \
+ PWMDeadBandDisable
+#endif
+#ifdef ROM_PWMSyncUpdate
+#define MAP_PWMSyncUpdate \
+ ROM_PWMSyncUpdate
+#else
+#define MAP_PWMSyncUpdate \
+ PWMSyncUpdate
+#endif
+#ifdef ROM_PWMSyncTimeBase
+#define MAP_PWMSyncTimeBase \
+ ROM_PWMSyncTimeBase
+#else
+#define MAP_PWMSyncTimeBase \
+ PWMSyncTimeBase
+#endif
+#ifdef ROM_PWMOutputState
+#define MAP_PWMOutputState \
+ ROM_PWMOutputState
+#else
+#define MAP_PWMOutputState \
+ PWMOutputState
+#endif
+#ifdef ROM_PWMOutputInvert
+#define MAP_PWMOutputInvert \
+ ROM_PWMOutputInvert
+#else
+#define MAP_PWMOutputInvert \
+ PWMOutputInvert
+#endif
+#ifdef ROM_PWMOutputFault
+#define MAP_PWMOutputFault \
+ ROM_PWMOutputFault
+#else
+#define MAP_PWMOutputFault \
+ PWMOutputFault
+#endif
+#ifdef ROM_PWMGenIntTrigEnable
+#define MAP_PWMGenIntTrigEnable \
+ ROM_PWMGenIntTrigEnable
+#else
+#define MAP_PWMGenIntTrigEnable \
+ PWMGenIntTrigEnable
+#endif
+#ifdef ROM_PWMGenIntTrigDisable
+#define MAP_PWMGenIntTrigDisable \
+ ROM_PWMGenIntTrigDisable
+#else
+#define MAP_PWMGenIntTrigDisable \
+ PWMGenIntTrigDisable
+#endif
+#ifdef ROM_PWMGenIntStatus
+#define MAP_PWMGenIntStatus \
+ ROM_PWMGenIntStatus
+#else
+#define MAP_PWMGenIntStatus \
+ PWMGenIntStatus
+#endif
+#ifdef ROM_PWMGenIntClear
+#define MAP_PWMGenIntClear \
+ ROM_PWMGenIntClear
+#else
+#define MAP_PWMGenIntClear \
+ PWMGenIntClear
+#endif
+#ifdef ROM_PWMIntEnable
+#define MAP_PWMIntEnable \
+ ROM_PWMIntEnable
+#else
+#define MAP_PWMIntEnable \
+ PWMIntEnable
+#endif
+#ifdef ROM_PWMIntDisable
+#define MAP_PWMIntDisable \
+ ROM_PWMIntDisable
+#else
+#define MAP_PWMIntDisable \
+ PWMIntDisable
+#endif
+#ifdef ROM_PWMFaultIntClear
+#define MAP_PWMFaultIntClear \
+ ROM_PWMFaultIntClear
+#else
+#define MAP_PWMFaultIntClear \
+ PWMFaultIntClear
+#endif
+#ifdef ROM_PWMIntStatus
+#define MAP_PWMIntStatus \
+ ROM_PWMIntStatus
+#else
+#define MAP_PWMIntStatus \
+ PWMIntStatus
+#endif
+#ifdef ROM_PWMOutputFaultLevel
+#define MAP_PWMOutputFaultLevel \
+ ROM_PWMOutputFaultLevel
+#else
+#define MAP_PWMOutputFaultLevel \
+ PWMOutputFaultLevel
+#endif
+#ifdef ROM_PWMFaultIntClearExt
+#define MAP_PWMFaultIntClearExt \
+ ROM_PWMFaultIntClearExt
+#else
+#define MAP_PWMFaultIntClearExt \
+ PWMFaultIntClearExt
+#endif
+#ifdef ROM_PWMGenFaultConfigure
+#define MAP_PWMGenFaultConfigure \
+ ROM_PWMGenFaultConfigure
+#else
+#define MAP_PWMGenFaultConfigure \
+ PWMGenFaultConfigure
+#endif
+#ifdef ROM_PWMGenFaultTriggerSet
+#define MAP_PWMGenFaultTriggerSet \
+ ROM_PWMGenFaultTriggerSet
+#else
+#define MAP_PWMGenFaultTriggerSet \
+ PWMGenFaultTriggerSet
+#endif
+#ifdef ROM_PWMGenFaultTriggerGet
+#define MAP_PWMGenFaultTriggerGet \
+ ROM_PWMGenFaultTriggerGet
+#else
+#define MAP_PWMGenFaultTriggerGet \
+ PWMGenFaultTriggerGet
+#endif
+#ifdef ROM_PWMGenFaultStatus
+#define MAP_PWMGenFaultStatus \
+ ROM_PWMGenFaultStatus
+#else
+#define MAP_PWMGenFaultStatus \
+ PWMGenFaultStatus
+#endif
+#ifdef ROM_PWMGenFaultClear
+#define MAP_PWMGenFaultClear \
+ ROM_PWMGenFaultClear
+#else
+#define MAP_PWMGenFaultClear \
+ PWMGenFaultClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the QEI API.
+//
+//*****************************************************************************
+#ifdef ROM_QEIPositionGet
+#define MAP_QEIPositionGet \
+ ROM_QEIPositionGet
+#else
+#define MAP_QEIPositionGet \
+ QEIPositionGet
+#endif
+#ifdef ROM_QEIEnable
+#define MAP_QEIEnable \
+ ROM_QEIEnable
+#else
+#define MAP_QEIEnable \
+ QEIEnable
+#endif
+#ifdef ROM_QEIDisable
+#define MAP_QEIDisable \
+ ROM_QEIDisable
+#else
+#define MAP_QEIDisable \
+ QEIDisable
+#endif
+#ifdef ROM_QEIConfigure
+#define MAP_QEIConfigure \
+ ROM_QEIConfigure
+#else
+#define MAP_QEIConfigure \
+ QEIConfigure
+#endif
+#ifdef ROM_QEIPositionSet
+#define MAP_QEIPositionSet \
+ ROM_QEIPositionSet
+#else
+#define MAP_QEIPositionSet \
+ QEIPositionSet
+#endif
+#ifdef ROM_QEIDirectionGet
+#define MAP_QEIDirectionGet \
+ ROM_QEIDirectionGet
+#else
+#define MAP_QEIDirectionGet \
+ QEIDirectionGet
+#endif
+#ifdef ROM_QEIErrorGet
+#define MAP_QEIErrorGet \
+ ROM_QEIErrorGet
+#else
+#define MAP_QEIErrorGet \
+ QEIErrorGet
+#endif
+#ifdef ROM_QEIVelocityEnable
+#define MAP_QEIVelocityEnable \
+ ROM_QEIVelocityEnable
+#else
+#define MAP_QEIVelocityEnable \
+ QEIVelocityEnable
+#endif
+#ifdef ROM_QEIVelocityDisable
+#define MAP_QEIVelocityDisable \
+ ROM_QEIVelocityDisable
+#else
+#define MAP_QEIVelocityDisable \
+ QEIVelocityDisable
+#endif
+#ifdef ROM_QEIVelocityConfigure
+#define MAP_QEIVelocityConfigure \
+ ROM_QEIVelocityConfigure
+#else
+#define MAP_QEIVelocityConfigure \
+ QEIVelocityConfigure
+#endif
+#ifdef ROM_QEIVelocityGet
+#define MAP_QEIVelocityGet \
+ ROM_QEIVelocityGet
+#else
+#define MAP_QEIVelocityGet \
+ QEIVelocityGet
+#endif
+#ifdef ROM_QEIIntEnable
+#define MAP_QEIIntEnable \
+ ROM_QEIIntEnable
+#else
+#define MAP_QEIIntEnable \
+ QEIIntEnable
+#endif
+#ifdef ROM_QEIIntDisable
+#define MAP_QEIIntDisable \
+ ROM_QEIIntDisable
+#else
+#define MAP_QEIIntDisable \
+ QEIIntDisable
+#endif
+#ifdef ROM_QEIIntStatus
+#define MAP_QEIIntStatus \
+ ROM_QEIIntStatus
+#else
+#define MAP_QEIIntStatus \
+ QEIIntStatus
+#endif
+#ifdef ROM_QEIIntClear
+#define MAP_QEIIntClear \
+ ROM_QEIIntClear
+#else
+#define MAP_QEIIntClear \
+ QEIIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SSI API.
+//
+//*****************************************************************************
+#ifdef ROM_SSIDataPut
+#define MAP_SSIDataPut \
+ ROM_SSIDataPut
+#else
+#define MAP_SSIDataPut \
+ SSIDataPut
+#endif
+#ifdef ROM_SSIConfigSetExpClk
+#define MAP_SSIConfigSetExpClk \
+ ROM_SSIConfigSetExpClk
+#else
+#define MAP_SSIConfigSetExpClk \
+ SSIConfigSetExpClk
+#endif
+#ifdef ROM_SSIEnable
+#define MAP_SSIEnable \
+ ROM_SSIEnable
+#else
+#define MAP_SSIEnable \
+ SSIEnable
+#endif
+#ifdef ROM_SSIDisable
+#define MAP_SSIDisable \
+ ROM_SSIDisable
+#else
+#define MAP_SSIDisable \
+ SSIDisable
+#endif
+#ifdef ROM_SSIIntEnable
+#define MAP_SSIIntEnable \
+ ROM_SSIIntEnable
+#else
+#define MAP_SSIIntEnable \
+ SSIIntEnable
+#endif
+#ifdef ROM_SSIIntDisable
+#define MAP_SSIIntDisable \
+ ROM_SSIIntDisable
+#else
+#define MAP_SSIIntDisable \
+ SSIIntDisable
+#endif
+#ifdef ROM_SSIIntStatus
+#define MAP_SSIIntStatus \
+ ROM_SSIIntStatus
+#else
+#define MAP_SSIIntStatus \
+ SSIIntStatus
+#endif
+#ifdef ROM_SSIIntClear
+#define MAP_SSIIntClear \
+ ROM_SSIIntClear
+#else
+#define MAP_SSIIntClear \
+ SSIIntClear
+#endif
+#ifdef ROM_SSIDataPutNonBlocking
+#define MAP_SSIDataPutNonBlocking \
+ ROM_SSIDataPutNonBlocking
+#else
+#define MAP_SSIDataPutNonBlocking \
+ SSIDataPutNonBlocking
+#endif
+#ifdef ROM_SSIDataGet
+#define MAP_SSIDataGet \
+ ROM_SSIDataGet
+#else
+#define MAP_SSIDataGet \
+ SSIDataGet
+#endif
+#ifdef ROM_SSIDataGetNonBlocking
+#define MAP_SSIDataGetNonBlocking \
+ ROM_SSIDataGetNonBlocking
+#else
+#define MAP_SSIDataGetNonBlocking \
+ SSIDataGetNonBlocking
+#endif
+#ifdef ROM_SSIDMAEnable
+#define MAP_SSIDMAEnable \
+ ROM_SSIDMAEnable
+#else
+#define MAP_SSIDMAEnable \
+ SSIDMAEnable
+#endif
+#ifdef ROM_SSIDMADisable
+#define MAP_SSIDMADisable \
+ ROM_SSIDMADisable
+#else
+#define MAP_SSIDMADisable \
+ SSIDMADisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysCtl API.
+//
+//*****************************************************************************
+#ifdef ROM_SysCtlSleep
+#define MAP_SysCtlSleep \
+ ROM_SysCtlSleep
+#else
+#define MAP_SysCtlSleep \
+ SysCtlSleep
+#endif
+#ifdef ROM_SysCtlSRAMSizeGet
+#define MAP_SysCtlSRAMSizeGet \
+ ROM_SysCtlSRAMSizeGet
+#else
+#define MAP_SysCtlSRAMSizeGet \
+ SysCtlSRAMSizeGet
+#endif
+#ifdef ROM_SysCtlFlashSizeGet
+#define MAP_SysCtlFlashSizeGet \
+ ROM_SysCtlFlashSizeGet
+#else
+#define MAP_SysCtlFlashSizeGet \
+ SysCtlFlashSizeGet
+#endif
+#ifdef ROM_SysCtlPinPresent
+#define MAP_SysCtlPinPresent \
+ ROM_SysCtlPinPresent
+#else
+#define MAP_SysCtlPinPresent \
+ SysCtlPinPresent
+#endif
+#ifdef ROM_SysCtlPeripheralPresent
+#define MAP_SysCtlPeripheralPresent \
+ ROM_SysCtlPeripheralPresent
+#else
+#define MAP_SysCtlPeripheralPresent \
+ SysCtlPeripheralPresent
+#endif
+#ifdef ROM_SysCtlPeripheralReset
+#define MAP_SysCtlPeripheralReset \
+ ROM_SysCtlPeripheralReset
+#else
+#define MAP_SysCtlPeripheralReset \
+ SysCtlPeripheralReset
+#endif
+#ifdef ROM_SysCtlPeripheralEnable
+#define MAP_SysCtlPeripheralEnable \
+ ROM_SysCtlPeripheralEnable
+#else
+#define MAP_SysCtlPeripheralEnable \
+ SysCtlPeripheralEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDisable
+#define MAP_SysCtlPeripheralDisable \
+ ROM_SysCtlPeripheralDisable
+#else
+#define MAP_SysCtlPeripheralDisable \
+ SysCtlPeripheralDisable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepEnable
+#define MAP_SysCtlPeripheralSleepEnable \
+ ROM_SysCtlPeripheralSleepEnable
+#else
+#define MAP_SysCtlPeripheralSleepEnable \
+ SysCtlPeripheralSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepDisable
+#define MAP_SysCtlPeripheralSleepDisable \
+ ROM_SysCtlPeripheralSleepDisable
+#else
+#define MAP_SysCtlPeripheralSleepDisable \
+ SysCtlPeripheralSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepEnable
+#define MAP_SysCtlPeripheralDeepSleepEnable \
+ ROM_SysCtlPeripheralDeepSleepEnable
+#else
+#define MAP_SysCtlPeripheralDeepSleepEnable \
+ SysCtlPeripheralDeepSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepDisable
+#define MAP_SysCtlPeripheralDeepSleepDisable \
+ ROM_SysCtlPeripheralDeepSleepDisable
+#else
+#define MAP_SysCtlPeripheralDeepSleepDisable \
+ SysCtlPeripheralDeepSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralClockGating
+#define MAP_SysCtlPeripheralClockGating \
+ ROM_SysCtlPeripheralClockGating
+#else
+#define MAP_SysCtlPeripheralClockGating \
+ SysCtlPeripheralClockGating
+#endif
+#ifdef ROM_SysCtlIntEnable
+#define MAP_SysCtlIntEnable \
+ ROM_SysCtlIntEnable
+#else
+#define MAP_SysCtlIntEnable \
+ SysCtlIntEnable
+#endif
+#ifdef ROM_SysCtlIntDisable
+#define MAP_SysCtlIntDisable \
+ ROM_SysCtlIntDisable
+#else
+#define MAP_SysCtlIntDisable \
+ SysCtlIntDisable
+#endif
+#ifdef ROM_SysCtlIntClear
+#define MAP_SysCtlIntClear \
+ ROM_SysCtlIntClear
+#else
+#define MAP_SysCtlIntClear \
+ SysCtlIntClear
+#endif
+#ifdef ROM_SysCtlIntStatus
+#define MAP_SysCtlIntStatus \
+ ROM_SysCtlIntStatus
+#else
+#define MAP_SysCtlIntStatus \
+ SysCtlIntStatus
+#endif
+#ifdef ROM_SysCtlLDOSet
+#define MAP_SysCtlLDOSet \
+ ROM_SysCtlLDOSet
+#else
+#define MAP_SysCtlLDOSet \
+ SysCtlLDOSet
+#endif
+#ifdef ROM_SysCtlLDOGet
+#define MAP_SysCtlLDOGet \
+ ROM_SysCtlLDOGet
+#else
+#define MAP_SysCtlLDOGet \
+ SysCtlLDOGet
+#endif
+#ifdef ROM_SysCtlReset
+#define MAP_SysCtlReset \
+ ROM_SysCtlReset
+#else
+#define MAP_SysCtlReset \
+ SysCtlReset
+#endif
+#ifdef ROM_SysCtlDeepSleep
+#define MAP_SysCtlDeepSleep \
+ ROM_SysCtlDeepSleep
+#else
+#define MAP_SysCtlDeepSleep \
+ SysCtlDeepSleep
+#endif
+#ifdef ROM_SysCtlResetCauseGet
+#define MAP_SysCtlResetCauseGet \
+ ROM_SysCtlResetCauseGet
+#else
+#define MAP_SysCtlResetCauseGet \
+ SysCtlResetCauseGet
+#endif
+#ifdef ROM_SysCtlResetCauseClear
+#define MAP_SysCtlResetCauseClear \
+ ROM_SysCtlResetCauseClear
+#else
+#define MAP_SysCtlResetCauseClear \
+ SysCtlResetCauseClear
+#endif
+#ifdef ROM_SysCtlClockSet
+#define MAP_SysCtlClockSet \
+ ROM_SysCtlClockSet
+#else
+#define MAP_SysCtlClockSet \
+ SysCtlClockSet
+#endif
+#ifdef ROM_SysCtlClockGet
+#define MAP_SysCtlClockGet \
+ ROM_SysCtlClockGet
+#else
+#define MAP_SysCtlClockGet \
+ SysCtlClockGet
+#endif
+#ifdef ROM_SysCtlPWMClockSet
+#define MAP_SysCtlPWMClockSet \
+ ROM_SysCtlPWMClockSet
+#else
+#define MAP_SysCtlPWMClockSet \
+ SysCtlPWMClockSet
+#endif
+#ifdef ROM_SysCtlPWMClockGet
+#define MAP_SysCtlPWMClockGet \
+ ROM_SysCtlPWMClockGet
+#else
+#define MAP_SysCtlPWMClockGet \
+ SysCtlPWMClockGet
+#endif
+#ifdef ROM_SysCtlADCSpeedSet
+#define MAP_SysCtlADCSpeedSet \
+ ROM_SysCtlADCSpeedSet
+#else
+#define MAP_SysCtlADCSpeedSet \
+ SysCtlADCSpeedSet
+#endif
+#ifdef ROM_SysCtlADCSpeedGet
+#define MAP_SysCtlADCSpeedGet \
+ ROM_SysCtlADCSpeedGet
+#else
+#define MAP_SysCtlADCSpeedGet \
+ SysCtlADCSpeedGet
+#endif
+#ifdef ROM_SysCtlGPIOAHBEnable
+#define MAP_SysCtlGPIOAHBEnable \
+ ROM_SysCtlGPIOAHBEnable
+#else
+#define MAP_SysCtlGPIOAHBEnable \
+ SysCtlGPIOAHBEnable
+#endif
+#ifdef ROM_SysCtlGPIOAHBDisable
+#define MAP_SysCtlGPIOAHBDisable \
+ ROM_SysCtlGPIOAHBDisable
+#else
+#define MAP_SysCtlGPIOAHBDisable \
+ SysCtlGPIOAHBDisable
+#endif
+#ifdef ROM_SysCtlUSBPLLEnable
+#define MAP_SysCtlUSBPLLEnable \
+ ROM_SysCtlUSBPLLEnable
+#else
+#define MAP_SysCtlUSBPLLEnable \
+ SysCtlUSBPLLEnable
+#endif
+#ifdef ROM_SysCtlUSBPLLDisable
+#define MAP_SysCtlUSBPLLDisable \
+ ROM_SysCtlUSBPLLDisable
+#else
+#define MAP_SysCtlUSBPLLDisable \
+ SysCtlUSBPLLDisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysTick API.
+//
+//*****************************************************************************
+#ifdef ROM_SysTickValueGet
+#define MAP_SysTickValueGet \
+ ROM_SysTickValueGet
+#else
+#define MAP_SysTickValueGet \
+ SysTickValueGet
+#endif
+#ifdef ROM_SysTickEnable
+#define MAP_SysTickEnable \
+ ROM_SysTickEnable
+#else
+#define MAP_SysTickEnable \
+ SysTickEnable
+#endif
+#ifdef ROM_SysTickDisable
+#define MAP_SysTickDisable \
+ ROM_SysTickDisable
+#else
+#define MAP_SysTickDisable \
+ SysTickDisable
+#endif
+#ifdef ROM_SysTickIntEnable
+#define MAP_SysTickIntEnable \
+ ROM_SysTickIntEnable
+#else
+#define MAP_SysTickIntEnable \
+ SysTickIntEnable
+#endif
+#ifdef ROM_SysTickIntDisable
+#define MAP_SysTickIntDisable \
+ ROM_SysTickIntDisable
+#else
+#define MAP_SysTickIntDisable \
+ SysTickIntDisable
+#endif
+#ifdef ROM_SysTickPeriodSet
+#define MAP_SysTickPeriodSet \
+ ROM_SysTickPeriodSet
+#else
+#define MAP_SysTickPeriodSet \
+ SysTickPeriodSet
+#endif
+#ifdef ROM_SysTickPeriodGet
+#define MAP_SysTickPeriodGet \
+ ROM_SysTickPeriodGet
+#else
+#define MAP_SysTickPeriodGet \
+ SysTickPeriodGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer API.
+//
+//*****************************************************************************
+#ifdef ROM_TimerIntClear
+#define MAP_TimerIntClear \
+ ROM_TimerIntClear
+#else
+#define MAP_TimerIntClear \
+ TimerIntClear
+#endif
+#ifdef ROM_TimerEnable
+#define MAP_TimerEnable \
+ ROM_TimerEnable
+#else
+#define MAP_TimerEnable \
+ TimerEnable
+#endif
+#ifdef ROM_TimerDisable
+#define MAP_TimerDisable \
+ ROM_TimerDisable
+#else
+#define MAP_TimerDisable \
+ TimerDisable
+#endif
+#ifdef ROM_TimerConfigure
+#define MAP_TimerConfigure \
+ ROM_TimerConfigure
+#else
+#define MAP_TimerConfigure \
+ TimerConfigure
+#endif
+#ifdef ROM_TimerControlLevel
+#define MAP_TimerControlLevel \
+ ROM_TimerControlLevel
+#else
+#define MAP_TimerControlLevel \
+ TimerControlLevel
+#endif
+#ifdef ROM_TimerControlTrigger
+#define MAP_TimerControlTrigger \
+ ROM_TimerControlTrigger
+#else
+#define MAP_TimerControlTrigger \
+ TimerControlTrigger
+#endif
+#ifdef ROM_TimerControlEvent
+#define MAP_TimerControlEvent \
+ ROM_TimerControlEvent
+#else
+#define MAP_TimerControlEvent \
+ TimerControlEvent
+#endif
+#ifdef ROM_TimerControlStall
+#define MAP_TimerControlStall \
+ ROM_TimerControlStall
+#else
+#define MAP_TimerControlStall \
+ TimerControlStall
+#endif
+#ifdef ROM_TimerRTCEnable
+#define MAP_TimerRTCEnable \
+ ROM_TimerRTCEnable
+#else
+#define MAP_TimerRTCEnable \
+ TimerRTCEnable
+#endif
+#ifdef ROM_TimerRTCDisable
+#define MAP_TimerRTCDisable \
+ ROM_TimerRTCDisable
+#else
+#define MAP_TimerRTCDisable \
+ TimerRTCDisable
+#endif
+#ifdef ROM_TimerPrescaleSet
+#define MAP_TimerPrescaleSet \
+ ROM_TimerPrescaleSet
+#else
+#define MAP_TimerPrescaleSet \
+ TimerPrescaleSet
+#endif
+#ifdef ROM_TimerPrescaleGet
+#define MAP_TimerPrescaleGet \
+ ROM_TimerPrescaleGet
+#else
+#define MAP_TimerPrescaleGet \
+ TimerPrescaleGet
+#endif
+#ifdef ROM_TimerLoadSet
+#define MAP_TimerLoadSet \
+ ROM_TimerLoadSet
+#else
+#define MAP_TimerLoadSet \
+ TimerLoadSet
+#endif
+#ifdef ROM_TimerLoadGet
+#define MAP_TimerLoadGet \
+ ROM_TimerLoadGet
+#else
+#define MAP_TimerLoadGet \
+ TimerLoadGet
+#endif
+#ifdef ROM_TimerValueGet
+#define MAP_TimerValueGet \
+ ROM_TimerValueGet
+#else
+#define MAP_TimerValueGet \
+ TimerValueGet
+#endif
+#ifdef ROM_TimerMatchSet
+#define MAP_TimerMatchSet \
+ ROM_TimerMatchSet
+#else
+#define MAP_TimerMatchSet \
+ TimerMatchSet
+#endif
+#ifdef ROM_TimerMatchGet
+#define MAP_TimerMatchGet \
+ ROM_TimerMatchGet
+#else
+#define MAP_TimerMatchGet \
+ TimerMatchGet
+#endif
+#ifdef ROM_TimerIntEnable
+#define MAP_TimerIntEnable \
+ ROM_TimerIntEnable
+#else
+#define MAP_TimerIntEnable \
+ TimerIntEnable
+#endif
+#ifdef ROM_TimerIntDisable
+#define MAP_TimerIntDisable \
+ ROM_TimerIntDisable
+#else
+#define MAP_TimerIntDisable \
+ TimerIntDisable
+#endif
+#ifdef ROM_TimerIntStatus
+#define MAP_TimerIntStatus \
+ ROM_TimerIntStatus
+#else
+#define MAP_TimerIntStatus \
+ TimerIntStatus
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UART API.
+//
+//*****************************************************************************
+#ifdef ROM_UARTCharPut
+#define MAP_UARTCharPut \
+ ROM_UARTCharPut
+#else
+#define MAP_UARTCharPut \
+ UARTCharPut
+#endif
+#ifdef ROM_UARTParityModeSet
+#define MAP_UARTParityModeSet \
+ ROM_UARTParityModeSet
+#else
+#define MAP_UARTParityModeSet \
+ UARTParityModeSet
+#endif
+#ifdef ROM_UARTParityModeGet
+#define MAP_UARTParityModeGet \
+ ROM_UARTParityModeGet
+#else
+#define MAP_UARTParityModeGet \
+ UARTParityModeGet
+#endif
+#ifdef ROM_UARTFIFOLevelSet
+#define MAP_UARTFIFOLevelSet \
+ ROM_UARTFIFOLevelSet
+#else
+#define MAP_UARTFIFOLevelSet \
+ UARTFIFOLevelSet
+#endif
+#ifdef ROM_UARTFIFOLevelGet
+#define MAP_UARTFIFOLevelGet \
+ ROM_UARTFIFOLevelGet
+#else
+#define MAP_UARTFIFOLevelGet \
+ UARTFIFOLevelGet
+#endif
+#ifdef ROM_UARTConfigSetExpClk
+#define MAP_UARTConfigSetExpClk \
+ ROM_UARTConfigSetExpClk
+#else
+#define MAP_UARTConfigSetExpClk \
+ UARTConfigSetExpClk
+#endif
+#ifdef ROM_UARTConfigGetExpClk
+#define MAP_UARTConfigGetExpClk \
+ ROM_UARTConfigGetExpClk
+#else
+#define MAP_UARTConfigGetExpClk \
+ UARTConfigGetExpClk
+#endif
+#ifdef ROM_UARTEnable
+#define MAP_UARTEnable \
+ ROM_UARTEnable
+#else
+#define MAP_UARTEnable \
+ UARTEnable
+#endif
+#ifdef ROM_UARTDisable
+#define MAP_UARTDisable \
+ ROM_UARTDisable
+#else
+#define MAP_UARTDisable \
+ UARTDisable
+#endif
+#ifdef ROM_UARTEnableSIR
+#define MAP_UARTEnableSIR \
+ ROM_UARTEnableSIR
+#else
+#define MAP_UARTEnableSIR \
+ UARTEnableSIR
+#endif
+#ifdef ROM_UARTDisableSIR
+#define MAP_UARTDisableSIR \
+ ROM_UARTDisableSIR
+#else
+#define MAP_UARTDisableSIR \
+ UARTDisableSIR
+#endif
+#ifdef ROM_UARTCharsAvail
+#define MAP_UARTCharsAvail \
+ ROM_UARTCharsAvail
+#else
+#define MAP_UARTCharsAvail \
+ UARTCharsAvail
+#endif
+#ifdef ROM_UARTSpaceAvail
+#define MAP_UARTSpaceAvail \
+ ROM_UARTSpaceAvail
+#else
+#define MAP_UARTSpaceAvail \
+ UARTSpaceAvail
+#endif
+#ifdef ROM_UARTCharGetNonBlocking
+#define MAP_UARTCharGetNonBlocking \
+ ROM_UARTCharGetNonBlocking
+#else
+#define MAP_UARTCharGetNonBlocking \
+ UARTCharGetNonBlocking
+#endif
+#ifdef ROM_UARTCharGet
+#define MAP_UARTCharGet \
+ ROM_UARTCharGet
+#else
+#define MAP_UARTCharGet \
+ UARTCharGet
+#endif
+#ifdef ROM_UARTCharPutNonBlocking
+#define MAP_UARTCharPutNonBlocking \
+ ROM_UARTCharPutNonBlocking
+#else
+#define MAP_UARTCharPutNonBlocking \
+ UARTCharPutNonBlocking
+#endif
+#ifdef ROM_UARTBreakCtl
+#define MAP_UARTBreakCtl \
+ ROM_UARTBreakCtl
+#else
+#define MAP_UARTBreakCtl \
+ UARTBreakCtl
+#endif
+#ifdef ROM_UARTIntEnable
+#define MAP_UARTIntEnable \
+ ROM_UARTIntEnable
+#else
+#define MAP_UARTIntEnable \
+ UARTIntEnable
+#endif
+#ifdef ROM_UARTIntDisable
+#define MAP_UARTIntDisable \
+ ROM_UARTIntDisable
+#else
+#define MAP_UARTIntDisable \
+ UARTIntDisable
+#endif
+#ifdef ROM_UARTIntStatus
+#define MAP_UARTIntStatus \
+ ROM_UARTIntStatus
+#else
+#define MAP_UARTIntStatus \
+ UARTIntStatus
+#endif
+#ifdef ROM_UARTIntClear
+#define MAP_UARTIntClear \
+ ROM_UARTIntClear
+#else
+#define MAP_UARTIntClear \
+ UARTIntClear
+#endif
+#ifdef ROM_UARTDMAEnable
+#define MAP_UARTDMAEnable \
+ ROM_UARTDMAEnable
+#else
+#define MAP_UARTDMAEnable \
+ UARTDMAEnable
+#endif
+#ifdef ROM_UARTDMADisable
+#define MAP_UARTDMADisable \
+ ROM_UARTDMADisable
+#else
+#define MAP_UARTDMADisable \
+ UARTDMADisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the uDMA API.
+//
+//*****************************************************************************
+#ifdef ROM_uDMAChannelTransferSet
+#define MAP_uDMAChannelTransferSet \
+ ROM_uDMAChannelTransferSet
+#else
+#define MAP_uDMAChannelTransferSet \
+ uDMAChannelTransferSet
+#endif
+#ifdef ROM_uDMAEnable
+#define MAP_uDMAEnable \
+ ROM_uDMAEnable
+#else
+#define MAP_uDMAEnable \
+ uDMAEnable
+#endif
+#ifdef ROM_uDMADisable
+#define MAP_uDMADisable \
+ ROM_uDMADisable
+#else
+#define MAP_uDMADisable \
+ uDMADisable
+#endif
+#ifdef ROM_uDMAErrorStatusGet
+#define MAP_uDMAErrorStatusGet \
+ ROM_uDMAErrorStatusGet
+#else
+#define MAP_uDMAErrorStatusGet \
+ uDMAErrorStatusGet
+#endif
+#ifdef ROM_uDMAErrorStatusClear
+#define MAP_uDMAErrorStatusClear \
+ ROM_uDMAErrorStatusClear
+#else
+#define MAP_uDMAErrorStatusClear \
+ uDMAErrorStatusClear
+#endif
+#ifdef ROM_uDMAChannelEnable
+#define MAP_uDMAChannelEnable \
+ ROM_uDMAChannelEnable
+#else
+#define MAP_uDMAChannelEnable \
+ uDMAChannelEnable
+#endif
+#ifdef ROM_uDMAChannelDisable
+#define MAP_uDMAChannelDisable \
+ ROM_uDMAChannelDisable
+#else
+#define MAP_uDMAChannelDisable \
+ uDMAChannelDisable
+#endif
+#ifdef ROM_uDMAChannelIsEnabled
+#define MAP_uDMAChannelIsEnabled \
+ ROM_uDMAChannelIsEnabled
+#else
+#define MAP_uDMAChannelIsEnabled \
+ uDMAChannelIsEnabled
+#endif
+#ifdef ROM_uDMAControlBaseSet
+#define MAP_uDMAControlBaseSet \
+ ROM_uDMAControlBaseSet
+#else
+#define MAP_uDMAControlBaseSet \
+ uDMAControlBaseSet
+#endif
+#ifdef ROM_uDMAControlBaseGet
+#define MAP_uDMAControlBaseGet \
+ ROM_uDMAControlBaseGet
+#else
+#define MAP_uDMAControlBaseGet \
+ uDMAControlBaseGet
+#endif
+#ifdef ROM_uDMAChannelRequest
+#define MAP_uDMAChannelRequest \
+ ROM_uDMAChannelRequest
+#else
+#define MAP_uDMAChannelRequest \
+ uDMAChannelRequest
+#endif
+#ifdef ROM_uDMAChannelAttributeEnable
+#define MAP_uDMAChannelAttributeEnable \
+ ROM_uDMAChannelAttributeEnable
+#else
+#define MAP_uDMAChannelAttributeEnable \
+ uDMAChannelAttributeEnable
+#endif
+#ifdef ROM_uDMAChannelAttributeDisable
+#define MAP_uDMAChannelAttributeDisable \
+ ROM_uDMAChannelAttributeDisable
+#else
+#define MAP_uDMAChannelAttributeDisable \
+ uDMAChannelAttributeDisable
+#endif
+#ifdef ROM_uDMAChannelAttributeGet
+#define MAP_uDMAChannelAttributeGet \
+ ROM_uDMAChannelAttributeGet
+#else
+#define MAP_uDMAChannelAttributeGet \
+ uDMAChannelAttributeGet
+#endif
+#ifdef ROM_uDMAChannelControlSet
+#define MAP_uDMAChannelControlSet \
+ ROM_uDMAChannelControlSet
+#else
+#define MAP_uDMAChannelControlSet \
+ uDMAChannelControlSet
+#endif
+#ifdef ROM_uDMAChannelSizeGet
+#define MAP_uDMAChannelSizeGet \
+ ROM_uDMAChannelSizeGet
+#else
+#define MAP_uDMAChannelSizeGet \
+ uDMAChannelSizeGet
+#endif
+#ifdef ROM_uDMAChannelModeGet
+#define MAP_uDMAChannelModeGet \
+ ROM_uDMAChannelModeGet
+#else
+#define MAP_uDMAChannelModeGet \
+ uDMAChannelModeGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the USB API.
+//
+//*****************************************************************************
+#ifdef ROM_USBIntStatus
+#define MAP_USBIntStatus \
+ ROM_USBIntStatus
+#else
+#define MAP_USBIntStatus \
+ USBIntStatus
+#endif
+#ifdef ROM_USBDevAddrGet
+#define MAP_USBDevAddrGet \
+ ROM_USBDevAddrGet
+#else
+#define MAP_USBDevAddrGet \
+ USBDevAddrGet
+#endif
+#ifdef ROM_USBDevAddrSet
+#define MAP_USBDevAddrSet \
+ ROM_USBDevAddrSet
+#else
+#define MAP_USBDevAddrSet \
+ USBDevAddrSet
+#endif
+#ifdef ROM_USBDevConnect
+#define MAP_USBDevConnect \
+ ROM_USBDevConnect
+#else
+#define MAP_USBDevConnect \
+ USBDevConnect
+#endif
+#ifdef ROM_USBDevDisconnect
+#define MAP_USBDevDisconnect \
+ ROM_USBDevDisconnect
+#else
+#define MAP_USBDevDisconnect \
+ USBDevDisconnect
+#endif
+#ifdef ROM_USBDevEndpointConfig
+#define MAP_USBDevEndpointConfig \
+ ROM_USBDevEndpointConfig
+#else
+#define MAP_USBDevEndpointConfig \
+ USBDevEndpointConfig
+#endif
+#ifdef ROM_USBDevEndpointDataAck
+#define MAP_USBDevEndpointDataAck \
+ ROM_USBDevEndpointDataAck
+#else
+#define MAP_USBDevEndpointDataAck \
+ USBDevEndpointDataAck
+#endif
+#ifdef ROM_USBDevEndpointStall
+#define MAP_USBDevEndpointStall \
+ ROM_USBDevEndpointStall
+#else
+#define MAP_USBDevEndpointStall \
+ USBDevEndpointStall
+#endif
+#ifdef ROM_USBDevEndpointStallClear
+#define MAP_USBDevEndpointStallClear \
+ ROM_USBDevEndpointStallClear
+#else
+#define MAP_USBDevEndpointStallClear \
+ USBDevEndpointStallClear
+#endif
+#ifdef ROM_USBDevEndpointStatusClear
+#define MAP_USBDevEndpointStatusClear \
+ ROM_USBDevEndpointStatusClear
+#else
+#define MAP_USBDevEndpointStatusClear \
+ USBDevEndpointStatusClear
+#endif
+#ifdef ROM_USBEndpointDataGet
+#define MAP_USBEndpointDataGet \
+ ROM_USBEndpointDataGet
+#else
+#define MAP_USBEndpointDataGet \
+ USBEndpointDataGet
+#endif
+#ifdef ROM_USBEndpointDataPut
+#define MAP_USBEndpointDataPut \
+ ROM_USBEndpointDataPut
+#else
+#define MAP_USBEndpointDataPut \
+ USBEndpointDataPut
+#endif
+#ifdef ROM_USBEndpointDataSend
+#define MAP_USBEndpointDataSend \
+ ROM_USBEndpointDataSend
+#else
+#define MAP_USBEndpointDataSend \
+ USBEndpointDataSend
+#endif
+#ifdef ROM_USBEndpointDataToggleClear
+#define MAP_USBEndpointDataToggleClear \
+ ROM_USBEndpointDataToggleClear
+#else
+#define MAP_USBEndpointDataToggleClear \
+ USBEndpointDataToggleClear
+#endif
+#ifdef ROM_USBEndpointStatus
+#define MAP_USBEndpointStatus \
+ ROM_USBEndpointStatus
+#else
+#define MAP_USBEndpointStatus \
+ USBEndpointStatus
+#endif
+#ifdef ROM_USBFIFOAddrGet
+#define MAP_USBFIFOAddrGet \
+ ROM_USBFIFOAddrGet
+#else
+#define MAP_USBFIFOAddrGet \
+ USBFIFOAddrGet
+#endif
+#ifdef ROM_USBFIFOConfigGet
+#define MAP_USBFIFOConfigGet \
+ ROM_USBFIFOConfigGet
+#else
+#define MAP_USBFIFOConfigGet \
+ USBFIFOConfigGet
+#endif
+#ifdef ROM_USBFIFOConfigSet
+#define MAP_USBFIFOConfigSet \
+ ROM_USBFIFOConfigSet
+#else
+#define MAP_USBFIFOConfigSet \
+ USBFIFOConfigSet
+#endif
+#ifdef ROM_USBFIFOFlush
+#define MAP_USBFIFOFlush \
+ ROM_USBFIFOFlush
+#else
+#define MAP_USBFIFOFlush \
+ USBFIFOFlush
+#endif
+#ifdef ROM_USBFrameNumberGet
+#define MAP_USBFrameNumberGet \
+ ROM_USBFrameNumberGet
+#else
+#define MAP_USBFrameNumberGet \
+ USBFrameNumberGet
+#endif
+#ifdef ROM_USBHostAddrGet
+#define MAP_USBHostAddrGet \
+ ROM_USBHostAddrGet
+#else
+#define MAP_USBHostAddrGet \
+ USBHostAddrGet
+#endif
+#ifdef ROM_USBHostAddrSet
+#define MAP_USBHostAddrSet \
+ ROM_USBHostAddrSet
+#else
+#define MAP_USBHostAddrSet \
+ USBHostAddrSet
+#endif
+#ifdef ROM_USBHostEndpointConfig
+#define MAP_USBHostEndpointConfig \
+ ROM_USBHostEndpointConfig
+#else
+#define MAP_USBHostEndpointConfig \
+ USBHostEndpointConfig
+#endif
+#ifdef ROM_USBHostEndpointDataAck
+#define MAP_USBHostEndpointDataAck \
+ ROM_USBHostEndpointDataAck
+#else
+#define MAP_USBHostEndpointDataAck \
+ USBHostEndpointDataAck
+#endif
+#ifdef ROM_USBHostEndpointDataToggle
+#define MAP_USBHostEndpointDataToggle \
+ ROM_USBHostEndpointDataToggle
+#else
+#define MAP_USBHostEndpointDataToggle \
+ USBHostEndpointDataToggle
+#endif
+#ifdef ROM_USBHostEndpointStatusClear
+#define MAP_USBHostEndpointStatusClear \
+ ROM_USBHostEndpointStatusClear
+#else
+#define MAP_USBHostEndpointStatusClear \
+ USBHostEndpointStatusClear
+#endif
+#ifdef ROM_USBHostHubAddrGet
+#define MAP_USBHostHubAddrGet \
+ ROM_USBHostHubAddrGet
+#else
+#define MAP_USBHostHubAddrGet \
+ USBHostHubAddrGet
+#endif
+#ifdef ROM_USBHostHubAddrSet
+#define MAP_USBHostHubAddrSet \
+ ROM_USBHostHubAddrSet
+#else
+#define MAP_USBHostHubAddrSet \
+ USBHostHubAddrSet
+#endif
+#ifdef ROM_USBHostPwrDisable
+#define MAP_USBHostPwrDisable \
+ ROM_USBHostPwrDisable
+#else
+#define MAP_USBHostPwrDisable \
+ USBHostPwrDisable
+#endif
+#ifdef ROM_USBHostPwrEnable
+#define MAP_USBHostPwrEnable \
+ ROM_USBHostPwrEnable
+#else
+#define MAP_USBHostPwrEnable \
+ USBHostPwrEnable
+#endif
+#ifdef ROM_USBHostPwrFaultConfig
+#define MAP_USBHostPwrFaultConfig \
+ ROM_USBHostPwrFaultConfig
+#else
+#define MAP_USBHostPwrFaultConfig \
+ USBHostPwrFaultConfig
+#endif
+#ifdef ROM_USBHostPwrFaultDisable
+#define MAP_USBHostPwrFaultDisable \
+ ROM_USBHostPwrFaultDisable
+#else
+#define MAP_USBHostPwrFaultDisable \
+ USBHostPwrFaultDisable
+#endif
+#ifdef ROM_USBHostPwrFaultEnable
+#define MAP_USBHostPwrFaultEnable \
+ ROM_USBHostPwrFaultEnable
+#else
+#define MAP_USBHostPwrFaultEnable \
+ USBHostPwrFaultEnable
+#endif
+#ifdef ROM_USBHostRequestIN
+#define MAP_USBHostRequestIN \
+ ROM_USBHostRequestIN
+#else
+#define MAP_USBHostRequestIN \
+ USBHostRequestIN
+#endif
+#ifdef ROM_USBHostRequestStatus
+#define MAP_USBHostRequestStatus \
+ ROM_USBHostRequestStatus
+#else
+#define MAP_USBHostRequestStatus \
+ USBHostRequestStatus
+#endif
+#ifdef ROM_USBHostReset
+#define MAP_USBHostReset \
+ ROM_USBHostReset
+#else
+#define MAP_USBHostReset \
+ USBHostReset
+#endif
+#ifdef ROM_USBHostResume
+#define MAP_USBHostResume \
+ ROM_USBHostResume
+#else
+#define MAP_USBHostResume \
+ USBHostResume
+#endif
+#ifdef ROM_USBHostSpeedGet
+#define MAP_USBHostSpeedGet \
+ ROM_USBHostSpeedGet
+#else
+#define MAP_USBHostSpeedGet \
+ USBHostSpeedGet
+#endif
+#ifdef ROM_USBHostSuspend
+#define MAP_USBHostSuspend \
+ ROM_USBHostSuspend
+#else
+#define MAP_USBHostSuspend \
+ USBHostSuspend
+#endif
+#ifdef ROM_USBIntDisable
+#define MAP_USBIntDisable \
+ ROM_USBIntDisable
+#else
+#define MAP_USBIntDisable \
+ USBIntDisable
+#endif
+#ifdef ROM_USBIntEnable
+#define MAP_USBIntEnable \
+ ROM_USBIntEnable
+#else
+#define MAP_USBIntEnable \
+ USBIntEnable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Watchdog API.
+//
+//*****************************************************************************
+#ifdef ROM_WatchdogIntClear
+#define MAP_WatchdogIntClear \
+ ROM_WatchdogIntClear
+#else
+#define MAP_WatchdogIntClear \
+ WatchdogIntClear
+#endif
+#ifdef ROM_WatchdogRunning
+#define MAP_WatchdogRunning \
+ ROM_WatchdogRunning
+#else
+#define MAP_WatchdogRunning \
+ WatchdogRunning
+#endif
+#ifdef ROM_WatchdogEnable
+#define MAP_WatchdogEnable \
+ ROM_WatchdogEnable
+#else
+#define MAP_WatchdogEnable \
+ WatchdogEnable
+#endif
+#ifdef ROM_WatchdogResetEnable
+#define MAP_WatchdogResetEnable \
+ ROM_WatchdogResetEnable
+#else
+#define MAP_WatchdogResetEnable \
+ WatchdogResetEnable
+#endif
+#ifdef ROM_WatchdogResetDisable
+#define MAP_WatchdogResetDisable \
+ ROM_WatchdogResetDisable
+#else
+#define MAP_WatchdogResetDisable \
+ WatchdogResetDisable
+#endif
+#ifdef ROM_WatchdogLock
+#define MAP_WatchdogLock \
+ ROM_WatchdogLock
+#else
+#define MAP_WatchdogLock \
+ WatchdogLock
+#endif
+#ifdef ROM_WatchdogUnlock
+#define MAP_WatchdogUnlock \
+ ROM_WatchdogUnlock
+#else
+#define MAP_WatchdogUnlock \
+ WatchdogUnlock
+#endif
+#ifdef ROM_WatchdogLockState
+#define MAP_WatchdogLockState \
+ ROM_WatchdogLockState
+#else
+#define MAP_WatchdogLockState \
+ WatchdogLockState
+#endif
+#ifdef ROM_WatchdogReloadSet
+#define MAP_WatchdogReloadSet \
+ ROM_WatchdogReloadSet
+#else
+#define MAP_WatchdogReloadSet \
+ WatchdogReloadSet
+#endif
+#ifdef ROM_WatchdogReloadGet
+#define MAP_WatchdogReloadGet \
+ ROM_WatchdogReloadGet
+#else
+#define MAP_WatchdogReloadGet \
+ WatchdogReloadGet
+#endif
+#ifdef ROM_WatchdogValueGet
+#define MAP_WatchdogValueGet \
+ ROM_WatchdogValueGet
+#else
+#define MAP_WatchdogValueGet \
+ WatchdogValueGet
+#endif
+#ifdef ROM_WatchdogIntEnable
+#define MAP_WatchdogIntEnable \
+ ROM_WatchdogIntEnable
+#else
+#define MAP_WatchdogIntEnable \
+ WatchdogIntEnable
+#endif
+#ifdef ROM_WatchdogIntStatus
+#define MAP_WatchdogIntStatus \
+ ROM_WatchdogIntStatus
+#else
+#define MAP_WatchdogIntStatus \
+ WatchdogIntStatus
+#endif
+#ifdef ROM_WatchdogStallEnable
+#define MAP_WatchdogStallEnable \
+ ROM_WatchdogStallEnable
+#else
+#define MAP_WatchdogStallEnable \
+ WatchdogStallEnable
+#endif
+#ifdef ROM_WatchdogStallDisable
+#define MAP_WatchdogStallDisable \
+ ROM_WatchdogStallDisable
+#else
+#define MAP_WatchdogStallDisable \
+ WatchdogStallDisable
+#endif
+
+#endif // __ROM_MAP_H__
diff --git a/bsp/lm3s/Libraries/driverlib/ssi.c b/bsp/lm3s/Libraries/driverlib/ssi.c new file mode 100644 index 0000000000..f9e84ad50c --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/ssi.c @@ -0,0 +1,680 @@ +//*****************************************************************************
+//
+// ssi.c - Driver for Synchronous Serial Interface.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ssi_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ssi.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/ssi.h"
+
+//*****************************************************************************
+//
+//! Configures the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
+//! \param ulProtocol specifies the data transfer protocol.
+//! \param ulMode specifies the mode of operation.
+//! \param ulBitRate specifies the clock rate.
+//! \param ulDataWidth specifies number of bits transferred per frame.
+//!
+//! This function configures the synchronous serial interface. It sets
+//! the SSI protocol, mode of operation, bit rate, and data width.
+//!
+//! The \e ulProtocol parameter defines the data frame format. The
+//! \e ulProtocol parameter can be one of the following values:
+//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
+//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
+//! frame formats imply the following polarity and phase configurations:
+//!
+//! <pre>
+//! Polarity Phase Mode
+//! 0 0 SSI_FRF_MOTO_MODE_0
+//! 0 1 SSI_FRF_MOTO_MODE_1
+//! 1 0 SSI_FRF_MOTO_MODE_2
+//! 1 1 SSI_FRF_MOTO_MODE_3
+//! </pre>
+//!
+//! The \e ulMode parameter defines the operating mode of the SSI module. The
+//! SSI module can operate as a master or slave; if a slave, the SSI can be
+//! configured to disable output on its serial output line. The \e ulMode
+//! parameter can be one of the following values: \b SSI_MODE_MASTER,
+//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
+//!
+//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
+//! must satisfy the following clock ratio criteria:
+//!
+//! - FSSI >= 2 * bit rate (master mode)
+//! - FSSI >= 12 * bit rate (slave modes)
+//!
+//! where FSSI is the frequency of the clock supplied to the SSI module.
+//!
+//! The \e ulDataWidth parameter defines the width of the data transfers, and
+//! can be a value between 4 and 16, inclusive.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original SSIConfig() API and performs the same
+//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
+//! this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
+ unsigned long ulProtocol, unsigned long ulMode,
+ unsigned long ulBitRate, unsigned long ulDataWidth)
+{
+ unsigned long ulMaxBitRate;
+ unsigned long ulRegVal;
+ unsigned long ulPreDiv;
+ unsigned long ulSCR;
+ unsigned long ulSPH_SPO;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_1) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_2) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_3) ||
+ (ulProtocol == SSI_FRF_TI) ||
+ (ulProtocol == SSI_FRF_NMW));
+ ASSERT((ulMode == SSI_MODE_MASTER) ||
+ (ulMode == SSI_MODE_SLAVE) ||
+ (ulMode == SSI_MODE_SLAVE_OD));
+ ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
+ ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
+ ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
+ ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
+
+ //
+ // Set the mode.
+ //
+ ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
+ ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
+ HWREG(ulBase + SSI_O_CR1) = ulRegVal;
+
+ //
+ // Set the clock predivider.
+ //
+ ulMaxBitRate = ulSSIClk / ulBitRate;
+ ulPreDiv = 0;
+ do
+ {
+ ulPreDiv += 2;
+ ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
+ }
+ while(ulSCR > 255);
+ HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
+
+ //
+ // Set protocol and clock rate.
+ //
+ ulSPH_SPO = ulProtocol << 6;
+ ulProtocol &= SSI_CR0_FRF_M;
+ ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
+ HWREG(ulBase + SSI_O_CR0) = ulRegVal;
+}
+
+//*****************************************************************************
+//
+//! Enables the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This will enable operation of the synchronous serial interface. It must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
+}
+
+//*****************************************************************************
+//
+//! Disables the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This will disable operation of the synchronous serial interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! synchronous serial interface interrupt occurs.
+//!
+//! This sets the handler to be called when an SSI interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
+//! it is the interrupt handler's responsibility to clear the interrupt source
+//! via SSIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the synchronous serial interface interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This function will clear the handler to be called when a SSI
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated SSI interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor. The \e ulIntFlags parameter can be any of the
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
+//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
+//! values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the SSI module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
+//
+//*****************************************************************************
+unsigned long
+SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + SSI_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + SSI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified SSI interrupt sources are cleared, so that
+//! they no longer assert. This must be done in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//! The \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO
+//! and \b SSI_RXOR values.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulData data to be transmitted over the SSI interface.
+//!
+//! This function will place the supplied data into the transmit FIFO of
+//! the specified SSI module.
+//!
+//! \note The upper 32 - N bits of the \e ulData will be discarded by the
+//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
+//! For example, if the interface is configured for 8-bit data width, the upper
+//! 24 bits of \e ulData will be discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataPut(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Wait until there is space.
+ //
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
+ {
+ }
+
+ //
+ // Write the data to the SSI.
+ //
+ HWREG(ulBase + SSI_O_DR) = ulData;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulData data to be transmitted over the SSI interface.
+//!
+//! This function will place the supplied data into the transmit FIFO of
+//! the specified SSI module. If there is no space in the FIFO, then this
+//! function will return a zero.
+//!
+//! This function replaces the original SSIDataNonBlockingPut() API and
+//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
+//! the original API to this API.
+//!
+//! \note The upper 32 - N bits of the \e ulData will be discarded by the
+//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
+//! For example, if the interface is configured for 8-bit data width, the upper
+//! 24 bits of \e ulData will be discarded.
+//!
+//! \return Returns the number of elements written to the SSI transmit FIFO.
+//
+//*****************************************************************************
+long
+SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Check for space to write.
+ //
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
+ {
+ HWREG(ulBase + SSI_O_DR) = ulData;
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pulData pointer to a storage location for data that was received
+//! over the SSI interface.
+//!
+//! This function will get received data from the receive FIFO of the specified
+//! SSI module, and place that data into the location specified by the
+//! \e pulData parameter.
+//!
+//! \note Only the lower N bits of the value written to \e pulData will contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
+//! will contain valid data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataGet(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Wait until there is data to be read.
+ //
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
+ {
+ }
+
+ //
+ // Read data from SSI.
+ //
+ *pulData = HWREG(ulBase + SSI_O_DR);
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pulData pointer to a storage location for data that was received
+//! over the SSI interface.
+//!
+//! This function will get received data from the receive FIFO of
+//! the specified SSI module, and place that data into the location specified
+//! by the \e ulData parameter. If there is no data in the FIFO, then this
+//! function will return a zero.
+//!
+//! This function replaces the original SSIDataNonBlockingGet() API and
+//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
+//! the original API to this API.
+//!
+//! \note Only the lower N bits of the value written to \e pulData will contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
+//! will contain valid data.
+//!
+//! \return Returns the number of elements read from the SSI receive FIFO.
+//
+//*****************************************************************************
+long
+SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Check for data to read.
+ //
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
+ {
+ *pulData = HWREG(ulBase + SSI_O_DR);
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable SSI DMA operation.
+//!
+//! \param ulBase is the base address of the SSI port.
+//! \param ulDMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified SSI DMA features are enabled. The SSI can be
+//! configured to use DMA for transmit and/or receive data transfers.
+//! The \e ulDMAFlags parameter is the logical OR of any of the following
+//! values:
+//!
+//! - SSI_DMA_RX - enable DMA for receive
+//! - SSI_DMA_TX - enable DMA for transmit
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the SSI.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable SSI DMA operation.
+//!
+//! \param ulBase is the base address of the SSI port.
+//! \param ulDMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable SSI DMA features that were enabled
+//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
+//! \e ulDMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - SSI_DMA_RX - disable DMA for receive
+//! - SSI_DMA_TX - disable DMA for transmit
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/ssi.h b/bsp/lm3s/Libraries/driverlib/ssi.h new file mode 100644 index 0000000000..4f7101b598 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/ssi.h @@ -0,0 +1,127 @@ +//*****************************************************************************
+//
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ulIntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less
+#define SSI_RXTO 0x00000002 // RX timeout
+#define SSI_RXOR 0x00000001 // RX overrun
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI 0x00000010 // TI frame format
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
+
+#define SSI_MODE_MASTER 0x00000000 // SSI master
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
+#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
+ unsigned long ulProtocol, unsigned long ulMode,
+ unsigned long ulBitRate,
+ unsigned long ulDataWidth);
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
+extern long SSIDataGetNonBlocking(unsigned long ulBase,
+ unsigned long *pulData);
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
+extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
+extern void SSIDisable(unsigned long ulBase);
+extern void SSIEnable(unsigned long ulBase);
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void SSIIntUnregister(unsigned long ulBase);
+extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+
+//*****************************************************************************
+//
+// Several SSI APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define SSIConfig(a, b, c, d, e) \
+ SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
+#define SSIDataNonBlockingGet(a, b) \
+ SSIDataGetNonBlocking(a, b)
+#define SSIDataNonBlockingPut(a, b) \
+ SSIDataPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SSI_H__
diff --git a/bsp/lm3s/Libraries/driverlib/sysctl.c b/bsp/lm3s/Libraries/driverlib/sysctl.c new file mode 100644 index 0000000000..0bc6ae7d51 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/sysctl.c @@ -0,0 +1,2319 @@ +//*****************************************************************************
+//
+// sysctl.c - Driver for the system controller.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// This macro extracts the array index out of the peripheral number.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_INDEX(a) (((a) >> 28) & 0xf)
+
+//*****************************************************************************
+//
+// This macro constructs the peripheral bit mask from the peripheral number.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_MASK(a) (((a) & 0xffff) << (((a) & 0x001f0000) >> 16))
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that
+// contains the peripheral present bit for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulDCRegs[] =
+{
+ SYSCTL_DC1,
+ SYSCTL_DC2,
+ SYSCTL_DC4,
+ SYSCTL_DC1
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that
+// controls the software reset for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulSRCRRegs[] =
+{
+ SYSCTL_SRCR0,
+ SYSCTL_SRCR1,
+ SYSCTL_SRCR2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that
+// controls the run-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulRCGCRegs[] =
+{
+ SYSCTL_RCGC0,
+ SYSCTL_RCGC1,
+ SYSCTL_RCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that
+// controls the sleep-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulSCGCRegs[] =
+{
+ SYSCTL_SCGC0,
+ SYSCTL_SCGC1,
+ SYSCTL_SCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that
+// controls the deep-sleep-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulDCGCRegs[] =
+{
+ SYSCTL_DCGC0,
+ SYSCTL_DCGC1,
+ SYSCTL_DCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the crystal number in RCC to a frequency.
+//
+//*****************************************************************************
+static const unsigned long g_pulXtals[] =
+{
+ 1000000,
+ 1843200,
+ 2000000,
+ 2457600,
+ 3579545,
+ 3686400,
+ 4000000,
+ 4096000,
+ 4915200,
+ 5000000,
+ 5120000,
+ 6000000,
+ 6144000,
+ 7372800,
+ 8000000,
+ 8192000,
+ 10000000,
+ 12000000,
+ 12288000,
+ 13560000,
+ 14318180,
+ 16000000,
+ 16384000
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a peripheral identifier.
+//!
+//! \param ulPeripheral is the peripheral identifier.
+//!
+//! This function determines if a peripheral identifier is valid.
+//!
+//! \return Returns \b true if the peripheral identifier is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+SysCtlPeripheralValid(unsigned long ulPeripheral)
+{
+ return((ulPeripheral == SYSCTL_PERIPH_ADC0) ||
+ (ulPeripheral == SYSCTL_PERIPH_ADC1) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN0) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN1) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN2) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
+ (ulPeripheral == SYSCTL_PERIPH_EPI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_ETH) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOJ) ||
+ (ulPeripheral == SYSCTL_PERIPH_HIBERNATE) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2C0) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2C1) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2S0) ||
+ (ulPeripheral == SYSCTL_PERIPH_IEEE1588) ||
+ (ulPeripheral == SYSCTL_PERIPH_MPU) ||
+ (ulPeripheral == SYSCTL_PERIPH_PLL) ||
+ (ulPeripheral == SYSCTL_PERIPH_PWM) ||
+ (ulPeripheral == SYSCTL_PERIPH_QEI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_QEI1) ||
+ (ulPeripheral == SYSCTL_PERIPH_SSI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_SSI1) ||
+ (ulPeripheral == SYSCTL_PERIPH_TEMP) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER3) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART2) ||
+ (ulPeripheral == SYSCTL_PERIPH_UDMA) ||
+ (ulPeripheral == SYSCTL_PERIPH_USB0) ||
+ (ulPeripheral == SYSCTL_PERIPH_WDOG0) ||
+ (ulPeripheral == SYSCTL_PERIPH_WDOG1));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! This function determines the size of the SRAM on the Stellaris device.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+unsigned long
+SysCtlSRAMSizeGet(void)
+{
+ //
+ // Compute the size of the SRAM.
+ //
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_M) >> 8) + 0x100);
+}
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! This function determines the size of the flash on the Stellaris device.
+//!
+//! \return The total number of bytes of flash.
+//
+//*****************************************************************************
+unsigned long
+SysCtlFlashSizeGet(void)
+{
+ //
+ // Compute the size of the flash.
+ //
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800);
+}
+
+//*****************************************************************************
+//
+//! Determines if a pin is present.
+//!
+//! \param ulPin is the pin in question.
+//!
+//! Determines if a particular pin is present in the device. The PWM, analog
+//! comparators, ADC, and timers have a varying number of pins across members
+//! of the Stellaris family; this will determine which are present on this
+//! device.
+//!
+//! The \e ulPin argument must be only one of the following values:
+//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2,
+//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5,
+//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O,
+//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O,
+//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O,
+//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2,
+//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5,
+//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0,
+//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3,
+//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, \b SYSCTL_PIN_CCP6,
+//! \b SYSCTL_PIN_CCP7, \b SYSCTL_PIN_32KHZ, or \b SYSCTL_PIN_MC_FAULT0.
+//!
+//! \return Returns \b true if the specified pin is present and \b false if it
+//! is not.
+//
+//*****************************************************************************
+tBoolean
+SysCtlPinPresent(unsigned long ulPin)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulPin == SYSCTL_PIN_PWM0) ||
+ (ulPin == SYSCTL_PIN_PWM1) ||
+ (ulPin == SYSCTL_PIN_PWM2) ||
+ (ulPin == SYSCTL_PIN_PWM3) ||
+ (ulPin == SYSCTL_PIN_PWM4) ||
+ (ulPin == SYSCTL_PIN_PWM5) ||
+ (ulPin == SYSCTL_PIN_C0MINUS) ||
+ (ulPin == SYSCTL_PIN_C0PLUS) ||
+ (ulPin == SYSCTL_PIN_C0O) ||
+ (ulPin == SYSCTL_PIN_C1MINUS) ||
+ (ulPin == SYSCTL_PIN_C1PLUS) ||
+ (ulPin == SYSCTL_PIN_C1O) ||
+ (ulPin == SYSCTL_PIN_C2MINUS) ||
+ (ulPin == SYSCTL_PIN_C2PLUS) ||
+ (ulPin == SYSCTL_PIN_C2O) ||
+ (ulPin == SYSCTL_PIN_MC_FAULT0) ||
+ (ulPin == SYSCTL_PIN_ADC0) ||
+ (ulPin == SYSCTL_PIN_ADC1) ||
+ (ulPin == SYSCTL_PIN_ADC2) ||
+ (ulPin == SYSCTL_PIN_ADC3) ||
+ (ulPin == SYSCTL_PIN_ADC4) ||
+ (ulPin == SYSCTL_PIN_ADC5) ||
+ (ulPin == SYSCTL_PIN_ADC6) ||
+ (ulPin == SYSCTL_PIN_ADC7) ||
+ (ulPin == SYSCTL_PIN_CCP0) ||
+ (ulPin == SYSCTL_PIN_CCP1) ||
+ (ulPin == SYSCTL_PIN_CCP2) ||
+ (ulPin == SYSCTL_PIN_CCP3) ||
+ (ulPin == SYSCTL_PIN_CCP4) ||
+ (ulPin == SYSCTL_PIN_CCP5) ||
+ (ulPin == SYSCTL_PIN_32KHZ));
+
+ //
+ // Determine if this pin is present.
+ //
+ if(HWREG(SYSCTL_DC3) & ulPin)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is present.
+//!
+//! \param ulPeripheral is the peripheral in question.
+//!
+//! Determines if a particular peripheral is present in the device. Each
+//! member of the Stellaris family has a different peripheral set; this will
+//! determine which are present on this device.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_MPU,
+//! \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TEMP, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0,
+//! \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, or \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return Returns \b true if the specified peripheral is present and \b false
+//! if it is not.
+//
+//*****************************************************************************
+tBoolean
+SysCtlPeripheralPresent(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Read the correct DC register and determine if this peripheral exists.
+ //
+ if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
+ SYSCTL_PERIPH_MASK(ulPeripheral))
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to reset.
+//!
+//! This function performs a software reset of the specified peripheral. An
+//! individual peripheral reset signal is asserted for a brief period and then
+//! deasserted, leaving the peripheral in a operating state but in its reset
+//! condition.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralReset(unsigned long ulPeripheral)
+{
+ volatile unsigned long ulDelay;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Put the peripheral into the reset state.
+ //
+ HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+
+ //
+ // Delay for a little bit.
+ //
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)
+ {
+ }
+
+ //
+ // Take the peripheral out of the reset state.
+ //
+ HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to enable.
+//!
+//! Peripherals are enabled with this function. At power-up, all peripherals
+//! are disabled; they must be enabled in order to operate or respond to
+//! register reads/writes.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \note It takes five clock cycles after the write to enable a peripheral
+//! before the the peripheral is actually enabled. During this time, attempts
+//! to access the peripheral will result in a bus fault. Care should be taken
+//! to ensure that the peripheral is not accessed during this brief time
+//! period.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral.
+ //
+ HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to disable.
+//!
+//! Peripherals are disabled with this function. Once disabled, they will not
+//! operate or respond to register reads/writes.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral.
+ //
+ HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to enable in sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into sleep mode. Since the clocking configuration of the device does
+//! not change, any peripheral can safely continue operating while the
+//! processor is in sleep mode, and can therefore wake the processor from sleep
+//! mode.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral in sleep mode.
+ //
+ HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to disable in sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into sleep mode. Disabling peripherals while in sleep mode helps to lower
+//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),
+//! the peripheral will automatically resume operation when the processor
+//! leaves sleep mode, maintaining its entire state from before sleep mode was
+//! entered.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral in sleep mode.
+ //
+ HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in deep-sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to enable in deep-sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into deep-sleep mode. Since the clocking configuration of the device
+//! may change, not all peripherals can safely continue operating while the
+//! processor is in sleep mode. Those that must run at a particular frequency
+//! (such as a UART) will not work as expected if the clock changes. It is the
+//! responsibility of the caller to make sensible choices.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ulPeripheral parameter must be one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral in deep-sleep mode.
+ //
+ HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in deep-sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to disable in deep-sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
+//! to lower the current draw of the device, and can keep peripherals that
+//! require a particular clock frequency from operating when the clock changes
+//! as a result of entering deep-sleep mode. If enabled (via
+//! SysCtlPeripheralEnable()), the peripheral will automatically resume
+//! operation when the processor leaves deep-sleep mode, maintaining its entire
+//! state from before deep-sleep mode was entered.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ulPeripheral parameter must be one of the following values:
+//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
+//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
+//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
+//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
+//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
+//! \b SYSCTL_PERIPH_WDOG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral in deep-sleep mode.
+ //
+ HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Controls peripheral clock gating in sleep and deep-sleep mode.
+//!
+//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
+//! peripheral configuration should be used and \b false if not.
+//!
+//! This function controls how peripherals are clocked when the processor goes
+//! into sleep or deep-sleep mode. By default, the peripherals are clocked the
+//! same as in run mode; if peripheral clock gating is enabled they are clocked
+//! according to the configuration set by SysCtlPeripheralSleepEnable(),
+//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and
+//! SysCtlPeripheralDeepSleepDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralClockGating(tBoolean bEnable)
+{
+ //
+ // Enable peripheral clock gating as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the system control interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the system
+//! control interrupt occurs.
+//!
+//! This sets the handler to be called when a system control interrupt occurs.
+//! This will enable the global interrupt in the interrupt controller; specific
+//! system control interrupts must be enabled via SysCtlIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! SysCtlIntClear().
+//!
+//! System control can generate interrupts when the PLL achieves lock, if the
+//! internal LDO current limit is exceeded, if the internal oscillator fails,
+//! if the main oscillator fails, if the internal LDO output voltage droops too
+//! much, if the external voltage droops too much, or if the PLL fails.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_SYSCTL, pfnHandler);
+
+ //
+ // Enable the system control interrupt.
+ //
+ IntEnable(INT_SYSCTL);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the system control interrupt.
+//!
+//! This function will clear the handler to be called when a system control
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_SYSCTL);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_SYSCTL);
+}
+
+//*****************************************************************************
+//
+//! Enables individual system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! Enables the indicated system control interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntEnable(unsigned long ulInts)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) |= ulInts;
+}
+
+//*****************************************************************************
+//
+//! Disables individual system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! Disables the indicated system control interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntDisable(unsigned long ulInts)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) &= ~(ulInts);
+}
+
+//*****************************************************************************
+//
+//! Clears system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! The specified system control interrupt sources are cleared, so that they no
+//! longer assert. This must be done in the interrupt handler to keep it from
+//! being called again immediately upon exit.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntClear(unsigned long ulInts)
+{
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(SYSCTL_MISC) = ulInts;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the system controller. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL,
+//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and
+//! \b SYSCTL_INT_PLL_FAIL.
+//
+//*****************************************************************************
+unsigned long
+SysCtlIntStatus(tBoolean bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(SYSCTL_MISC));
+ }
+ else
+ {
+ return(HWREG(SYSCTL_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the output voltage of the LDO.
+//!
+//! \param ulVoltage is the required output voltage from the LDO. Must be one
+//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
+//!
+//! This function sets the output voltage of the LDO. The default voltage is
+//! 2.5 V; it can be adjusted +/- 10%.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDOSet(unsigned long ulVoltage)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulVoltage == SYSCTL_LDO_2_25V) ||
+ (ulVoltage == SYSCTL_LDO_2_30V) ||
+ (ulVoltage == SYSCTL_LDO_2_35V) ||
+ (ulVoltage == SYSCTL_LDO_2_40V) ||
+ (ulVoltage == SYSCTL_LDO_2_45V) ||
+ (ulVoltage == SYSCTL_LDO_2_50V) ||
+ (ulVoltage == SYSCTL_LDO_2_55V) ||
+ (ulVoltage == SYSCTL_LDO_2_60V) ||
+ (ulVoltage == SYSCTL_LDO_2_65V) ||
+ (ulVoltage == SYSCTL_LDO_2_70V) ||
+ (ulVoltage == SYSCTL_LDO_2_75V));
+
+ //
+ // Set the LDO voltage to the requested value.
+ //
+ HWREG(SYSCTL_LDOPCTL) = ulVoltage;
+}
+
+//*****************************************************************************
+//
+//! Gets the output voltage of the LDO.
+//!
+//! This function determines the output voltage of the LDO, as specified by the
+//! control register.
+//!
+//! \return Returns the current voltage of the LDO; will be one of
+//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
+//
+//*****************************************************************************
+unsigned long
+SysCtlLDOGet(void)
+{
+ //
+ // Return the LDO voltage setting.
+ //
+ return(HWREG(SYSCTL_LDOPCTL));
+}
+
+//*****************************************************************************
+//
+//! Configures the LDO failure control.
+//!
+//! \param ulConfig is the required LDO failure control setting; can be either
+//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST.
+//!
+//! This function allows the LDO to be configured to cause a processor reset
+//! when the output voltage becomes unregulated.
+//!
+//! The LDO failure control is only available on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDOConfigSet(unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) ||
+ (ulConfig == SYSCTL_LDOCFG_NORST));
+
+ //
+ // Set the reset control as requested.
+ //
+ HWREG(SYSCTL_LDOARST) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Resets the device.
+//!
+//! This function will perform a software reset of the entire device. The
+//! processor and all peripherals will be reset and all device registers will
+//! return to their default values (with the exception of the reset cause
+//! register, which will maintain its current value but have the software reset
+//! bit set as well).
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+void
+SysCtlReset(void)
+{
+ //
+ // Perform a software reset request. This will cause the device to reset,
+ // no further code will be executed.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
+
+ //
+ // The device should have reset, so this should never be reached. Just in
+ // case, loop forever.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into sleep mode.
+//!
+//! This function places the processor into sleep mode; it will not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
+//! processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlSleep(void)
+{
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into deep-sleep mode.
+//!
+//! This function places the processor into deep-sleep mode; it will not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
+//! the processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleep(void)
+{
+ //
+ // Enable deep-sleep.
+ //
+ HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
+
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+
+ //
+ // Disable deep-sleep so that a future sleep will work correctly.
+ //
+ HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
+}
+
+//*****************************************************************************
+//
+//! Gets the reason for a reset.
+//!
+//! This function will return the reason(s) for a reset. Since the reset
+//! reasons are sticky until either cleared by software or an external reset,
+//! multiple reset reasons may be returned if multiple resets have occurred.
+//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO,
+//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR,
+//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! \return Returns the reason(s) for a reset.
+//
+//*****************************************************************************
+unsigned long
+SysCtlResetCauseGet(void)
+{
+ //
+ // Return the reset reasons.
+ //
+ return(HWREG(SYSCTL_RESC));
+}
+
+//*****************************************************************************
+//
+//! Clears reset reasons.
+//!
+//! \param ulCauses are the reset causes to be cleared; must be a logical OR of
+//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG,
+//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! This function clears the specified sticky reset reasons. Once cleared,
+//! another reset for the same reason can be detected, and a reset for a
+//! different reason can be distinguished (instead of having two reset causes
+//! set). If the reset reason is used by an application, all reset causes
+//! should be cleared after they are retrieved with SysCtlResetCauseGet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlResetCauseClear(unsigned long ulCauses)
+{
+ //
+ // Clear the given reset reasons.
+ //
+ HWREG(SYSCTL_RESC) &= ~(ulCauses);
+}
+
+//*****************************************************************************
+//
+//! Configures the brown-out control.
+//!
+//! \param ulConfig is the desired configuration of the brown-out control.
+//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or
+//! \b SYSCTL_BOR_RESAMPLE.
+//! \param ulDelay is the number of internal oscillator cycles to wait before
+//! resampling an asserted brown-out signal. This value only has meaning when
+//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192.
+//!
+//! This function configures how the brown-out control operates. It can detect
+//! a brown-out by looking at only the brown-out output, or it can wait for it
+//! to be active for two consecutive samples separated by a configurable time.
+//! When it detects a brown-out condition, it can either reset the device or
+//! generate a processor interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE)));
+ ASSERT(ulDelay < 8192);
+
+ //
+ // Configure the brown-out reset control.
+ //
+ HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BORTIM_S) | ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Provides a small delay.
+//!
+//! \param ulCount is the number of delay loop iterations to perform.
+//!
+//! This function provides a means of generating a constant length delay. It
+//! is written in assembly to keep the delay consistent across tool chains,
+//! avoiding the need to tune the delay based on the tool chain in use.
+//!
+//! The loop takes 3 cycles/loop.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(DOXYGEN)
+void
+SysCtlDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne.n SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+SysCtlDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+SysCtlDelay(unsigned long ulCount)
+{
+ subs r0, #1;
+ bne SysCtlDelay;
+ bx lr;
+}
+#endif
+
+//*****************************************************************************
+//
+//! Sets the clocking of the device.
+//!
+//! \param ulConfig is the required configuration of the device clocking.
+//!
+//! This function configures the clocking of the device. The input crystal
+//! frequency, oscillator to be used, use of the PLL, and the system clock
+//! divider are all configured with this function.
+//!
+//! The \e ulConfig parameter is the logical OR of several different values,
+//! many of which are grouped into sets where only one can be chosen.
+//!
+//! The system clock divider is chosen with one of the following values:
+//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ...
+//! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16
+//! are valid on Sandstorm-class devices.
+//!
+//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
+//! \b SYSCTL_USE_OSC.
+//!
+//! The external crystal frequency is chosen with one of the following values:
+//! \b SYSCTL_XTAL_1MHZ, \b SYSCTL_XTAL_1_84MHZ, \b SYSCTL_XTAL_2MHZ,
+//! \b SYSCTL_XTAL_2_45MHZ, \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ,
+//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
+//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
+//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
+//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
+//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
+//! \b SYSCTL_XTAL_16MHZ, or \b SYSCTL_XTAL_16_3MHZ. Values below
+//! \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. On
+//! Sandstorm- and Fury-class devices, values above \b SYSCTL_XTAL_8_19MHZ are
+//! not valid.
+//!
+//! The oscillator source is chosen with one of the following values:
+//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
+//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. On Sandstorm-class devices,
+//! \b SYSCTL_OSC_INT30 and \b SYSCTL_OSC_EXT32 are not valid.
+//! \b SYSCTL_OSC_EXT32 is only available on devices with the hibernate module,
+//! and then only when the hibernate module has been enabled.
+//!
+//! The internal and main oscillators are disabled with the
+//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
+//! The external oscillator must be enabled in order to use an external clock
+//! source. Note that attempts to disable the oscillator used to clock the
+//! device will be prevented by the hardware.
+//!
+//! To clock the system from an external source (such as an external crystal
+//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the
+//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
+//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use
+//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
+//! crystal with one of the \b SYSCTL_XTAL_xxx values.
+//!
+//! \note If selecting the PLL as the system clock source (that is, via
+//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to
+//! determine when the PLL has locked. If an interrupt handler for the
+//! system control interrupt is in place, and it responds to and clears the
+//! PLL lock interrupt, this function will delay until its timeout has occurred
+//! instead of completing as soon as PLL lock is achieved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClockSet(unsigned long ulConfig)
+{
+ unsigned long ulDelay, ulRCC, ulRCC2;
+
+ //
+ // See if this is a Sandstorm-class device and clocking features from newer
+ // devices were requested.
+ //
+ if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2))
+ {
+ //
+ // Return without changing the clocking since the requested
+ // configuration can not be achieved.
+ //
+ return;
+ }
+
+ //
+ // Get the current value of the RCC and RCC2 registers. If using a
+ // Sandstorm-class device, the RCC2 register will read back as zero and the
+ // writes to it from within this function will be ignored.
+ //
+ ulRCC = HWREG(SYSCTL_RCC);
+ ulRCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Bypass the PLL and system clock dividers for now.
+ //
+ ulRCC |= SYSCTL_RCC_BYPASS;
+ ulRCC &= ~(SYSCTL_RCC_USESYSDIV);
+ ulRCC2 |= SYSCTL_RCC2_BYPASS2;
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+
+ //
+ // See if either oscillator needs to be enabled.
+ //
+ if(((ulRCC & SYSCTL_RCC_IOSCDIS) && !(ulConfig & SYSCTL_RCC_IOSCDIS)) ||
+ ((ulRCC & SYSCTL_RCC_MOSCDIS) && !(ulConfig & SYSCTL_RCC_MOSCDIS)))
+ {
+ //
+ // Make sure that the required oscillators are enabled. For now, the
+ // previously enabled oscillators must be enabled along with the newly
+ // requested oscillators.
+ //
+ ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) |
+ (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS)));
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+
+ //
+ // Wait for a bit, giving the oscillator time to stabilize. The number
+ // of iterations is adjusted based on the current clock source; a
+ // smaller number of iterations is required for slower clock rates.
+ //
+ if(((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ (((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_30) ||
+ ((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_32))) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ ((ulRCC & SYSCTL_RCC_OSCSRC_M) == SYSCTL_RCC_OSCSRC_30)))
+ {
+ //
+ // Delay for 4096 iterations.
+ //
+ SysCtlDelay(4096);
+ }
+ else
+ {
+ //
+ // Delay for 524,288 iterations.
+ //
+ SysCtlDelay(524288);
+ }
+ }
+
+ //
+ // Set the new crystal value, oscillator source, and PLL configuration.
+ // Since the OSCSRC2 field in RCC2 overlaps the XTAL field in RCC, the
+ // OSCSRC field has a special encoding within ulConfig to avoid the
+ // overlap.
+ //
+ ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
+ ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
+ ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M |
+ SYSCTL_RCC2_PWRDN2);
+ ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC2_PWRDN2);
+ ulRCC2 |= (ulConfig & 0x00000008) << 3;
+
+ //
+ // Clear the PLL lock interrupt.
+ //
+ HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
+
+ //
+ // Write the new RCC value.
+ //
+ if(ulRCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+ HWREG(SYSCTL_RCC) = ulRCC;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+ }
+
+ //
+ // Wait for a bit so that new crystal value and oscillator source can take
+ // effect.
+ //
+ SysCtlDelay(16);
+
+ //
+ // Set the requested system divider and disable the appropriate
+ // oscillators. This will not get written immediately.
+ //
+ ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
+ ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
+ ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
+ ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M;
+ if(ulConfig & SYSCTL_RCC2_USEFRACT)
+ {
+ ulRCC |= SYSCTL_RCC_USESYSDIV;
+ ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV);
+ ulRCC2 |= ulConfig & (SYSCTL_RCC2_USEFRACT | SYSCTL_RCC2_FRACT);
+ }
+ else
+ {
+ ulRCC2 &= ~(SYSCTL_RCC2_USEFRACT);
+ }
+
+ //
+ // See if the PLL output is being used to clock the system.
+ //
+ if(!(ulConfig & SYSCTL_RCC_BYPASS))
+ {
+ //
+ // Wait until the PLL has locked.
+ //
+ for(ulDelay = 32768; ulDelay > 0; ulDelay--)
+ {
+ if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
+ {
+ break;
+ }
+ }
+
+ //
+ // Enable use of the PLL.
+ //
+ ulRCC &= ~(SYSCTL_RCC_BYPASS);
+ ulRCC2 &= ~(SYSCTL_RCC2_BYPASS2);
+ }
+
+ //
+ // Write the final RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+
+ //
+ // Delay for a little bit so that the system divider takes effect.
+ //
+ SysCtlDelay(16);
+}
+
+//*****************************************************************************
+//
+//! Gets the processor clock rate.
+//!
+//! This function determines the clock rate of the processor clock. This is
+//! also the clock rate of all the peripheral modules (with the exception of
+//! PWM, which has its own clock divider).
+//!
+//! \note This will not return accurate results if SysCtlClockSet() has not
+//! been called to configure the clocking of the device, or if the device is
+//! directly clocked from a crystal (or a clock source) that is not one of the
+//! supported crystal frequencies. In the later case, this function should be
+//! modified to directly return the correct system clock rate.
+//!
+//! \return The processor clock rate.
+//
+//*****************************************************************************
+unsigned long
+SysCtlClockGet(void)
+{
+ unsigned long ulRCC, ulRCC2, ulPLL, ulClk;
+
+ //
+ // Read RCC and RCC2. For Sandstorm-class devices (which do not have
+ // RCC2), the RCC2 read will return 0, which indicates that RCC2 is
+ // disabled (since the SYSCTL_RCC2_USERCC2 bit is clear).
+ //
+ ulRCC = HWREG(SYSCTL_RCC);
+ ulRCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Get the base clock rate.
+ //
+ switch((ulRCC2 & SYSCTL_RCC2_USERCC2) ?
+ (ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) :
+ (ulRCC & SYSCTL_RCC_OSCSRC_M))
+ {
+ //
+ // The main oscillator is the clock source. Determine its rate from
+ // the crystal setting field.
+ //
+ case SYSCTL_RCC_OSCSRC_MAIN:
+ {
+ ulClk = g_pulXtals[(ulRCC & SYSCTL_RCC_XTAL_M) >>
+ SYSCTL_RCC_XTAL_S];
+ break;
+ }
+
+ //
+ // The internal oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT:
+ {
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // The internal oscillator on a Sandstorm-class device is
+ // 15 MHz +/- 50%.
+ //
+ ulClk = 15000000;
+ }
+ else if((CLASS_IS_FURY && REVISION_IS_A2) ||
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
+ {
+ //
+ // The internal oscillator on a rev A2 Fury-class device and a
+ // rev A0 Dustdevil-class device is 12 MHz +/- 30%.
+ //
+ ulClk = 12000000;
+ }
+ else
+ {
+ //
+ // The internal oscillator on all other devices is 16 MHz.
+ //
+ ulClk = 16000000;
+ }
+ break;
+ }
+
+ //
+ // The internal oscillator divided by four is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT4:
+ {
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // The internal oscillator on a Sandstorm-class device is
+ // 15 MHz +/- 50%.
+ //
+ ulClk = 15000000 / 4;
+ }
+ else if((CLASS_IS_FURY && REVISION_IS_A2) ||
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
+ {
+ //
+ // The internal oscillator on a rev A2 Fury-class device and a
+ // rev A0 Dustdevil-class device is 12 MHz +/- 30%.
+ //
+ ulClk = 12000000 / 4;
+ }
+ else
+ {
+ //
+ // The internal oscillator on a Tempest-class device is 16 MHz.
+ //
+ ulClk = 16000000 / 4;
+ }
+ break;
+ }
+
+ //
+ // The internal 30 KHz oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_30:
+ {
+ //
+ // The internal 30 KHz oscillator has an accuracy of +/- 30%.
+ //
+ ulClk = 30000;
+ break;
+ }
+
+ //
+ // The 4.19 MHz clock from the hibernate module is the clock source.
+ //
+ case SYSCTL_RCC2_OSCSRC2_419:
+ {
+ ulClk = 4194304;
+ break;
+ }
+
+ //
+ // The 32 KHz clock from the hibernate module is the source clock.
+ //
+ case SYSCTL_RCC2_OSCSRC2_32:
+ {
+ ulClk = 32768;
+ break;
+ }
+
+ //
+ // An unknown setting, so return a zero clock (that is, an unknown
+ // clock rate).
+ //
+ default:
+ {
+ return(0);
+ }
+ }
+
+ //
+ // See if the PLL is being used.
+ //
+ if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC & SYSCTL_RCC_BYPASS)))
+ {
+ //
+ // Get the PLL configuration.
+ //
+ ulPLL = HWREG(SYSCTL_PLLCFG);
+
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // Compute the PLL output frequency based on its input frequency.
+ // The formula for a Sandstorm-class devices is
+ // "(xtal * (f + 2)) / (r + 2)".
+ //
+ ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S) + 2)) /
+ (((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 2));
+ }
+ else
+ {
+ //
+ // Compute the PLL output frequency based on its input frequency.
+ // The formula for a Fury-class device is
+ // "(xtal * f) / ((r + 1) * 2)".
+ //
+ ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S)) /
+ ((((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 1) * 2));
+ }
+
+ //
+ // See if the optional output divide by 2 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_2)
+ {
+ ulClk /= 2;
+ }
+
+ //
+ // See if the optional output divide by 4 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_4)
+ {
+ ulClk /= 4;
+ }
+ }
+
+ //
+ // See if the system divider is being used.
+ //
+ if(ulRCC & SYSCTL_RCC_USESYSDIV)
+ {
+ //
+ // Adjust the clock rate by the system clock divider.
+ //
+ if(ulRCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ if((ulRCC2 & SYSCTL_RCC2_USEFRACT) &&
+ (((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ulRCC & SYSCTL_RCC_BYPASS))))
+
+ {
+ ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M |
+ SYSCTL_RCC2_FRACT)) >>
+ (SYSCTL_RCC2_SYSDIV2_S - 1)) + 1));
+ }
+ else
+ {
+ ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
+ SYSCTL_RCC2_SYSDIV2_S) + 1);
+ }
+ }
+ else
+ {
+ ulClk /= (((ulRCC & SYSCTL_RCC_SYSDIV_M) >> SYSCTL_RCC_SYSDIV_S) +
+ 1);
+ }
+ }
+
+ //
+ // Return the computed clock rate.
+ //
+ return(ulClk);
+}
+
+//*****************************************************************************
+//
+//! Sets the PWM clock configuration.
+//!
+//! \param ulConfig is the configuration for the PWM clock; it must be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//!
+//! This function sets the rate of the clock provided to the PWM module as a
+//! ratio of the processor clock. This clock is used by the PWM module to
+//! generate PWM signals; its rate forms the basis for all PWM signals.
+//!
+//! \note The clocking of the PWM is dependent upon the system clock rate as
+//! configured by SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPWMClockSet(unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulConfig == SYSCTL_PWMDIV_1) ||
+ (ulConfig == SYSCTL_PWMDIV_2) ||
+ (ulConfig == SYSCTL_PWMDIV_4) ||
+ (ulConfig == SYSCTL_PWMDIV_8) ||
+ (ulConfig == SYSCTL_PWMDIV_16) ||
+ (ulConfig == SYSCTL_PWMDIV_32) ||
+ (ulConfig == SYSCTL_PWMDIV_64));
+
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
+
+ //
+ // Set the PWM clock configuration into the run-mode clock configuration
+ // register.
+ //
+ HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
+ ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) |
+ ulConfig);
+}
+
+//*****************************************************************************
+//
+//! Gets the current PWM clock configuration.
+//!
+//! This function returns the current PWM clock configuration.
+//!
+//! \return Returns the current PWM clock configuration; will be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//
+//*****************************************************************************
+unsigned long
+SysCtlPWMClockGet(void)
+{
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
+
+ //
+ // Return the current PWM clock configuration. Make sure that
+ // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled.
+ //
+ if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV))
+ {
+ //
+ // The divider is not active so reflect this in the value we return.
+ //
+ return(SYSCTL_PWMDIV_1);
+ }
+ else
+ {
+ //
+ // The divider is active so directly return the masked register value.
+ //
+ return(HWREG(SYSCTL_RCC) &
+ (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the sample rate of the ADC.
+//!
+//! \param ulSpeed is the desired sample rate of the ADC; must be one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//!
+//! This function sets the rate at which the ADC samples are captured by the
+//! ADC block. The sampling speed may be limited by the hardware, so the
+//! sample rate may end up being slower than requested. SysCtlADCSpeedGet()
+//! will return the actual speed in use.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlADCSpeedSet(unsigned long ulSpeed)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_500KSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_250KSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_125KSPS));
+
+ //
+ // Check that there is an ADC block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
+
+ //
+ // Set the ADC speed in run, sleep, and deep-sleep mode.
+ //
+ HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) |
+ ulSpeed);
+ HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) |
+ ulSpeed);
+ HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_DCGC0_ADCSPD_M)) |
+ ulSpeed);
+}
+
+//*****************************************************************************
+//
+//! Gets the sample rate of the ADC.
+//!
+//! This function gets the current sample rate of the ADC.
+//!
+//! \return Returns the current ADC sample rate; will be one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//
+//*****************************************************************************
+unsigned long
+SysCtlADCSpeedGet(void)
+{
+ //
+ // Check that there is an ADC block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
+
+ //
+ // Return the current ADC speed.
+ //
+ return(HWREG(SYSCTL_RCGC0) & SYSCTL_RCGC0_ADCSPD_M);
+}
+
+//*****************************************************************************
+//
+//! Configures the internal oscillator verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the internal oscillator
+//! verification timer should be enabled.
+//!
+//! This function allows the internal oscillator verification timer to be
+//! enabled or disabled. When enabled, an interrupt will be generated if the
+//! internal oscillator ceases to operate.
+//!
+//! The internal oscillator verification timer is only available on
+//! Sandstorm-class devices.
+//!
+//! \note Both oscillators (main and internal) must be enabled for this
+//! verification timer to operate as the main oscillator will verify the
+//! internal oscillator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIOSCVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the internal oscillator verification timer as
+ // requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the main oscillator verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the main oscillator
+//! verification timer should be enabled.
+//!
+//! This function allows the main oscillator verification timer to be enabled
+//! or disabled. When enabled, an interrupt will be generated if the main
+//! oscillator ceases to operate.
+//!
+//! The main oscillator verification timer is only available on
+//! Sandstorm-class devices.
+//!
+//! \note Both oscillators (main and internal) must be enabled for this
+//! verification timer to operate as the internal oscillator will verify the
+//! main oscillator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlMOSCVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the main oscillator verification timer as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the PLL verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the PLL verification timer
+//! should be enabled.
+//!
+//! This function allows the PLL verification timer to be enabled or disabled.
+//! When enabled, an interrupt will be generated if the PLL ceases to operate.
+//!
+//! The PLL verification timer is only available on Sandstorm-class devices.
+//!
+//! \note The main oscillator must be enabled for this verification timer to
+//! operate as it is used to check the PLL. Also, the verification timer
+//! should be disabled while the PLL is being reconfigured via
+//! SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPLLVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the PLL verification timer as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the clock verification status.
+//!
+//! This function clears the status of the clock verification timers, allowing
+//! them to assert another failure if detected.
+//!
+//! The clock verification timers are only available on Sandstorm-class
+//! devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClkVerificationClear(void)
+{
+ //
+ // Clear the clock verification.
+ //
+ HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_VERCLR;
+
+ //
+ // The bit does not self-reset, so clear it.
+ //
+ HWREG(SYSCTL_CLKVCLR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a GPIO peripheral for access from the AHB.
+//!
+//! \param ulGPIOPeripheral is the GPIO peripheral to enable.
+//!
+//! This function is used to enable the specified GPIO peripheral to be
+//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced
+//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access,
+//! the \b _AHB_BASE form of the base address should be used for GPIO
+//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base
+//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead.
+//!
+//! The \e ulGPIOPeripheral argument must be only one of the following values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Enable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHSCTL) |= ulGPIOPeripheral & 0xFFFF;
+}
+
+//*****************************************************************************
+//
+//! Disables a GPIO peripheral for access from the AHB.
+//!
+//! \param ulGPIOPeripheral is the GPIO peripheral to disable.
+//!
+//! This function disables the specified GPIO peripheral for access from the
+//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed
+//! from the legacy Advanced Peripheral Bus (AHB).
+//!
+//! The \b ulGPIOPeripheral argument must be only one of the following values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Disable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHSCTL) &= ~(ulGPIOPeripheral & 0xFFFF);
+}
+
+//*****************************************************************************
+//
+//! Powers up the USB PLL.
+//!
+//! This function will enable the USB controller's PLL which is used by it's
+//! physical layer. This call is necessary before connecting to any external
+//! devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLEnable(void)
+{
+ //
+ // Turn on the USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Powers down the USB PLL.
+//!
+//! This function will disable the USB controller's PLL which is used by it's
+//! physical layer. The USB registers are still accessible, but the physical
+//! layer will no longer function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLDisable(void)
+{
+ //
+ // Turn of USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Sets the MCLK frequency provided to the I2S module.
+//!
+//! \param ulInputClock is the input clock to the MCLK divider. If this is
+//! zero, the value is computed from the current PLL configuration.
+//! \param ulMClk is the desired MCLK frequency. If this is zero, MCLK output
+//! is disabled.
+//!
+//! This function sets the dividers to provide MCLK to the I2S module. A MCLK
+//! divider will be chosen that produces the MCLK frequency that is the closest
+//! possible to the requested frequency, which may be above or below the
+//! requested frequency.
+//!
+//! The actual MCLK frequency will be returned. It is the responsibility of
+//! the application to determine if the selected MCLK is acceptable; in general
+//! the human ear can not discern the frequency difference if it is within 0.3%
+//! of the desired frequency (though there is a very small percentage of the
+//! population that can discern lower frequency deviations).
+//!
+//! \return Returns the actual MCLK frequency.
+//
+//*****************************************************************************
+unsigned long
+SysCtlI2SMClkSet(unsigned long ulInputClock, unsigned long ulMClk)
+{
+ unsigned long ulDivInt, ulDivFrac, ulPLL;
+
+ //
+ // See if the I2S MCLK should be disabled.
+ //
+ if(ulMClk == 0)
+ {
+ //
+ // Disable the I2S MCLK and return.
+ //
+ HWREG(SYSCTL_I2SMCLKCFG) = 0;
+ return(0);
+ }
+
+ //
+ // See if the input clock was specified.
+ //
+ if(ulInputClock == 0)
+ {
+ //
+ // The input clock was not specified, so compute the output frequency
+ // of the PLL. Get the current PLL configuration.
+ //
+ ulPLL = HWREG(SYSCTL_PLLCFG);
+
+ //
+ // Get the frequency of the crystal in use.
+ //
+ ulInputClock = g_pulXtals[(HWREG(SYSCTL_RCC) & SYSCTL_RCC_XTAL_M) >>
+ SYSCTL_RCC_XTAL_S];
+
+ //
+ // Calculate the PLL output frequency.
+ //
+ ulInputClock = ((ulInputClock * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S)) /
+ ((((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 1)));
+
+ //
+ // See if the optional output divide by 2 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_2)
+ {
+ ulInputClock /= 2;
+ }
+
+ //
+ // See if the optional output divide by 4 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_4)
+ {
+ ulInputClock /= 4;
+ }
+ }
+
+ //
+ // Verify that the requested MCLK frequency is attainable.
+ //
+ ASSERT(ulMClk < ulInputClock);
+
+ //
+ // Add a rounding factor to the input clock, so that the MCLK frequency
+ // that is closest to the desire value is selected.
+ //
+ ulInputClock += (ulMClk / 32) - 1;
+
+ //
+ // Compute the integer portion of the MCLK divider.
+ //
+ ulDivInt = ulInputClock / ulMClk;
+
+ //
+ // If the divisor is too large, then simply use the maximum divisor.
+ //
+ if(CLASS_IS_TEMPEST && REVISION_IS_B1 && (ulDivInt > 255))
+ {
+ ulDivInt = 255;
+ ulDivFrac = 15;
+ }
+ else if(ulDivInt > 1023)
+ {
+ ulDivInt = 1023;
+ ulDivFrac = 15;
+ }
+ else
+ {
+ //
+ // Compute the fractional portion of the MCLK divider.
+ //
+ ulDivFrac = ((ulInputClock - (ulDivInt * ulMClk)) * 16) / ulMClk;
+ }
+
+ //
+ // Set the divisor for the Tx and Rx MCLK generators and enable the clocks.
+ //
+ HWREG(SYSCTL_I2SMCLKCFG) = (SYSCTL_I2SMCLKCFG_RXEN |
+ (ulDivInt << SYSCTL_I2SMCLKCFG_RXI_S) |
+ (ulDivFrac << SYSCTL_I2SMCLKCFG_RXF_S) |
+ SYSCTL_I2SMCLKCFG_TXEN |
+ (ulDivInt << SYSCTL_I2SMCLKCFG_TXI_S) |
+ (ulDivFrac << SYSCTL_I2SMCLKCFG_TXF_S));
+
+ //
+ // Return the actual MCLK frequency.
+ //
+ ulInputClock -= (ulMClk / 32) - 1;
+ ulDivInt = (ulDivInt * 16) + ulDivFrac;
+ ulMClk = (ulInputClock / ulDivInt) * 16;
+ ulMClk += ((ulInputClock - ((ulMClk / 16) * ulDivInt)) * 16) / ulDivInt;
+ return(ulMClk);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/sysctl.h b/bsp/lm3s/Libraries/driverlib/sysctl.h new file mode 100644 index 0000000000..3cef7f7621 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/sysctl.h @@ -0,0 +1,469 @@ +//*****************************************************************************
+//
+// sysctl.h - Prototypes for the system control driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSCTL_H__
+#define __SYSCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
+// is 3) can only be used with the SysCtlPeripheralPresent() API.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
+#endif
+#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
+#endif
+#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
+#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
+#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
+#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
+#endif
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
+#endif
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
+#endif
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
+#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
+#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
+#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
+#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
+#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
+#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPinPresent() API
+// as the ulPin parameter.
+//
+//*****************************************************************************
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
+#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
+#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOSet() API as
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlIntEnable(),
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
+// by the SysCtlIntStatus() API.
+//
+//*****************************************************************************
+#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
+#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlResetCauseClear()
+// API or returned by the SysCtlResetCauseGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()
+// API as the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPWMClockSet() API
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlADCSpeedSet() API
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlClockSet() API as
+// the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
+#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
+#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
+#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
+#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
+#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
+#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
+#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
+#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
+#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
+#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
+#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
+#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
+#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
+#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
+#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
+#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
+#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
+#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
+#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
+#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
+#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
+#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
+#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
+#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
+#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
+#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
+#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
+#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
+#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
+#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
+#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
+#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
+#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
+#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
+#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
+#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
+#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
+#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
+#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
+#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
+#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
+#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
+#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
+#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
+#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
+#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
+#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
+#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
+#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
+#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
+#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
+#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
+#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
+#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
+#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
+#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
+#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
+#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
+#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
+#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
+#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
+#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
+#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
+#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
+#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
+#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
+#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
+#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
+#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
+#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
+#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
+#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
+#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
+#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
+#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
+#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
+#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
+#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
+#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
+#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
+#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
+#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
+#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
+#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
+#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
+#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
+#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
+#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
+#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
+#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
+#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
+#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
+#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
+#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
+#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
+#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
+#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
+#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
+#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
+#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
+#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
+#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
+#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
+#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
+#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
+#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
+#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
+#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
+#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
+#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
+#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
+#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
+#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
+#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
+#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
+#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
+#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
+#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
+#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
+#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
+#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
+#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
+#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
+#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
+#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
+#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
+#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
+#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long SysCtlSRAMSizeGet(void);
+extern unsigned long SysCtlFlashSizeGet(void);
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);
+extern void SysCtlIntRegister(void (*pfnHandler)(void));
+extern void SysCtlIntUnregister(void);
+extern void SysCtlIntEnable(unsigned long ulInts);
+extern void SysCtlIntDisable(unsigned long ulInts);
+extern void SysCtlIntClear(unsigned long ulInts);
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);
+extern void SysCtlLDOSet(unsigned long ulVoltage);
+extern unsigned long SysCtlLDOGet(void);
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);
+extern void SysCtlReset(void);
+extern void SysCtlSleep(void);
+extern void SysCtlDeepSleep(void);
+extern unsigned long SysCtlResetCauseGet(void);
+extern void SysCtlResetCauseClear(unsigned long ulCauses);
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
+ unsigned long ulDelay);
+extern void SysCtlDelay(unsigned long ulCount);
+extern void SysCtlClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlClockGet(void);
+extern void SysCtlPWMClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlPWMClockGet(void);
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
+extern unsigned long SysCtlADCSpeedGet(void);
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);
+extern void SysCtlClkVerificationClear(void);
+extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
+extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
+extern void SysCtlUSBPLLEnable(void);
+extern void SysCtlUSBPLLDisable(void);
+extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
+ unsigned long ulMClk);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSCTL_H__
diff --git a/bsp/lm3s/Libraries/driverlib/systick.c b/bsp/lm3s/Libraries/driverlib/systick.c new file mode 100644 index 0000000000..4296851443 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/systick.c @@ -0,0 +1,262 @@ +//*****************************************************************************
+//
+// systick.c - Driver for the SysTick timer in NVIC.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/systick.h"
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This will start the SysTick counter. If an interrupt handler has been
+//! registered, it will be called when the SysTick counter rolls over.
+//!
+//! \note Calling this function will cause the SysTick counter to (re)commence
+//! counting from its current value. The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTickPeriodSet(). If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force this. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickEnable(void)
+{
+ //
+ // Enable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This will stop the SysTick counter. If an interrupt handler has been
+//! registered, it will no longer be called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickDisable(void)
+{
+ //
+ // Disable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This sets the handler to be called when a SysTick interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(FAULT_SYSTICK, pfnHandler);
+
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function will clear the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntUnregister(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(FAULT_SYSTICK);
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function will enable the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler does not need to clear the SysTick
+//! interrupt source as this is done automatically by NVIC when the interrupt
+//! handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntEnable(void)
+{
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function will disable the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntDisable(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param ulPeriod is the number of clock ticks in each period of the SysTick
+//! counter; must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on
+//! the next clock after the SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickPeriodSet(unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
+
+ //
+ // Set the period of the SysTick counter.
+ //
+ HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickPeriodGet(void)
+{
+ //
+ // Return the period of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_RELOAD) + 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter; this will
+//! be a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickValueGet(void)
+{
+ //
+ // Return the current value of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_CURRENT));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/systick.h b/bsp/lm3s/Libraries/driverlib/systick.h new file mode 100644 index 0000000000..e3d9d58759 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/systick.h @@ -0,0 +1,66 @@ +//*****************************************************************************
+//
+// systick.h - Prototypes for the SysTick driver.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SysTickEnable(void);
+extern void SysTickDisable(void);
+extern void SysTickIntRegister(void (*pfnHandler)(void));
+extern void SysTickIntUnregister(void);
+extern void SysTickIntEnable(void);
+extern void SysTickIntDisable(void);
+extern void SysTickPeriodSet(unsigned long ulPeriod);
+extern unsigned long SysTickPeriodGet(void);
+extern unsigned long SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSTICK_H__
diff --git a/bsp/lm3s/Libraries/driverlib/timer.c b/bsp/lm3s/Libraries/driverlib/timer.c new file mode 100644 index 0000000000..8065376d1b --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/timer.c @@ -0,0 +1,1007 @@ +//*****************************************************************************
+//
+// timer.c - Driver for the timer module.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup timer_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/timer.h"
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a timer base address.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function determines if a timer module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+TimerBaseValid(unsigned long ulBase)
+{
+ return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
+ (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Enables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This will enable operation of the timer module. The timer must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerEnable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Enable the timer(s) module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+}
+
+//*****************************************************************************
+//
+//! Disables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to disable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This will disable operation of the timer module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDisable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Disable the timer module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &
+ (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
+}
+
+//*****************************************************************************
+//
+//! Configures the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulConfig is the configuration for the timer.
+//!
+//! This function configures the operating mode of the timer(s). The timer
+//! module is disabled before being configured, and is left in the disabled
+//! state. The configuration is specified in \e ulConfig as one of the
+//! following values:
+//!
+//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer
+//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
+//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
+//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
+//!
+//! When configured for a pair of 16-bit timers, each timer is separately
+//! configured. The first timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the following values
+//! and \e ulConfig:
+//!
+//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer
+//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
+//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
+//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
+//! - \b TIMER_CFG_A_PWM - 16-bit PWM output
+//!
+//! Similarly, the second timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the corresponding
+//! \b TIMER_CFG_B_* values and \e ulConfig.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
+ (ulConfig == TIMER_CFG_32_BIT_PER) ||
+ (ulConfig == TIMER_CFG_32_RTC) ||
+ ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
+ ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
+ ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
+ (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
+
+ //
+ // Disable the timers.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+
+ //
+ // Set the global timer configuration.
+ //
+ HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;
+
+ //
+ // Set the configuration of the A and B timers. Note that the B timer
+ // configuration is ignored by the hardware in 32-bit modes.
+ //
+ HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
+ HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
+}
+
+//*****************************************************************************
+//
+//! Controls the output level.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bInvert specifies the output level.
+//!
+//! This function sets the PWM output level for the specified timer. If the
+//! \e bInvert parameter is \b true, then the timer's output will be made
+//! active low; otherwise, it will be made active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the output levels as requested.
+ //
+ ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
+ HWREG(ulBase + TIMER_O_CTL) = (bInvert ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Enables or disables the trigger output.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bEnable specifies the desired trigger state.
+//!
+//! This function controls the trigger output for the specified timer. If the
+//! \e bEnable parameter is \b true, then the timer's output trigger is
+//! enabled; otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the trigger output as requested.
+ //
+ ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
+ HWREG(ulBase + TIMER_O_CTL) = (bEnable ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the event type.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulEvent specifies the type of event; must be one of
+//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
+//! \b TIMER_EVENT_BOTH_EDGES.
+//!
+//! This function sets the signal edge(s) that will trigger the timer when in
+//! capture mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the event type.
+ //
+ ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
+ HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
+ ~(TIMER_CTL_TAEVENT_M |
+ TIMER_CTL_TBEVENT_M)) | ulEvent);
+}
+
+//*****************************************************************************
+//
+//! Controls the stall handling.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bStall specifies the response to a stall signal.
+//!
+//! This function controls the stall response for the specified timer. If the
+//! \e bStall parameter is \b true, then the timer will stop counting if the
+//! processor enters debug mode; otherwise the timer will keep running while in
+//! debug mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the stall mode.
+ //
+ ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
+ HWREG(ulBase + TIMER_O_CTL) = (bStall ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Enable RTC counting.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function causes the timer to start counting when in RTC mode. If not
+//! configured for RTC mode, this will do nothing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Enable RTC counting.
+ //
+ HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Disable RTC counting.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function causes the timer to stop counting when in RTC mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable RTC counting.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale value; must be between 0 and 255,
+//! inclusive.
+//!
+//! This function sets the value of the input clock prescaler. The prescaler
+//! is only operational when in 16-bit mode and is used to extend the range of
+//! the 16-bit timer modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+ ASSERT(ulValue < 256);
+
+ //
+ // Set the timer A prescaler if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAPR) = ulValue;
+ }
+
+ //
+ // Set the timer B prescaler if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBPR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler. The prescaler
+//! is only operational when in 16-bit mode and is used to extend the range of
+//! the 16-bit timer modes.
+//!
+//! \return The value of the timer prescaler.
+//
+//*****************************************************************************
+unsigned long
+TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :
+ HWREG(ulBase + TIMER_O_TBPR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for 32-bit operation.
+//! \param ulValue is the load value.
+//!
+//! This function sets the timer load value; if the timer is running then the
+//! value will be immediately loaded into the timer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A load value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAILR) = ulValue;
+ }
+
+ //
+ // Set the timer B load value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBILR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified timer.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate load value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :
+ HWREG(ulBase + TIMER_O_TBILR));
+}
+
+//*****************************************************************************
+//
+//! Gets the current timer value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate timer value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :
+ HWREG(ulBase + TIMER_O_TBR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for 32-bit operation.
+//! \param ulValue is the match value.
+//!
+//! This function sets the match value for a timer. This is used in capture
+//! count mode to determine when to interrupt the processor and in PWM mode to
+//! determine the duty cycle of the output signal.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A match value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;
+ }
+
+ //
+ // Set the timer B match value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \return Returns the match value for the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate match value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :
+ HWREG(ulBase + TIMER_O_TBMATCHR));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param pfnHandler is a pointer to the function to be called when the timer
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when a timer interrupt occurs. This
+//! will enable the global interrupt in the interrupt controller; specific
+//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source via TimerIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
+ ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
+
+ //
+ // Register an interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase);
+ }
+
+ //
+ // Register an interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase + 1, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function will clear the handler to be called when a timer interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
+ ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
+
+ //
+ // Unregister the interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase);
+ }
+
+ //
+ // Unregister the interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase + 1);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b TIMER_CAPB_EVENT - Capture B event interrupt
+//! - \b TIMER_CAPB_MATCH - Capture B match interrupt
+//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
+//! - \b TIMER_RTC_MATCH - RTC interrupt mask
+//! - \b TIMER_CAPA_EVENT - Capture A event interrupt
+//! - \b TIMER_CAPA_MATCH - Capture A match interrupt
+//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the timer module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! values described in TimerIntEnable().
+//
+//*****************************************************************************
+unsigned long
+TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :
+ HWREG(ulBase + TIMER_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! Clears timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified timer interrupt sources are cleared, so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Puts the timer into its reset state.
+//
+// \param ulBase is the base address of the timer module.
+//
+// The specified timer is disabled, and all its interrupts are disabled,
+// cleared, and unregistered. Then the timer registers are set to their reset
+// value.
+//
+// \return None.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+void
+TimerQuiesce(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable the timer.
+ //
+ HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL;
+
+ //
+ // Disable all the timer interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR;
+
+ //
+ // Clear all the timer interrupts.
+ //
+ HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF;
+
+ //
+ // Unregister the interrupt handler. This also disables interrupts to the
+ // core.
+ //
+ TimerIntUnregister(ulBase, TIMER_BOTH);
+
+ //
+ // Set all the registers to their reset value.
+ //
+ HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG;
+ HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR;
+ HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR;
+ HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS;
+ HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS;
+ HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR;
+ HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR;
+ HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR;
+ HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR;
+ HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR;
+ HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR;
+ HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR;
+ HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR;
+ HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR;
+ HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR;
+}
+#endif // DEPRECATED
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/timer.h b/bsp/lm3s/Libraries/driverlib/timer.h new file mode 100644 index 0000000000..978f5344db --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/timer.h @@ -0,0 +1,153 @@ +//*****************************************************************************
+//
+// timer.h - Prototypes for the timer module
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ulConfig parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ulTimer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A 0x000000ff // Timer A
+#define TIMER_B 0x0000ff00 // Timer B
+#define TIMER_BOTH 0x0000ffff // Timer Both
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert);
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bEnable);
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent);
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall);
+extern void TimerRTCEnable(unsigned long ulBase);
+extern void TimerRTCDisable(unsigned long ulBase);
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
+extern unsigned long TimerValueGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerMatchGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void));
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
+// instead to return the timer to its reset state.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void TimerQuiesce(unsigned long ulBase);
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __TIMER_H__
diff --git a/bsp/lm3s/Libraries/driverlib/uart.c b/bsp/lm3s/Libraries/driverlib/uart.c new file mode 100644 index 0000000000..648e6abead --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/uart.c @@ -0,0 +1,1621 @@ +//*****************************************************************************
+//
+// uart.c - Driver for the UART.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_uart.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/uart.h"
+
+//*****************************************************************************
+//
+// The system clock divider defining the maximum baud rate supported by the
+// UART.
+//
+//*****************************************************************************
+#define UART_CLK_DIVIDER ((CLASS_IS_SANDSTORM || \
+ (CLASS_IS_FURY && REVISION_IS_A2) || \
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \
+ 16 : 8)
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a UART base address.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function determines if a UART port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+UARTBaseValid(unsigned long ulBase)
+{
+ return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Sets the type of parity.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulParity specifies the type of parity to use.
+//!
+//! Sets the type of parity to use for transmitting and expect when receiving.
+//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
+//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
+//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
+//! parity bit; it will always be either be one or zero based on the mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
+ (ulParity == UART_CONFIG_PAR_EVEN) ||
+ (ulParity == UART_CONFIG_PAR_ODD) ||
+ (ulParity == UART_CONFIG_PAR_ONE) ||
+ (ulParity == UART_CONFIG_PAR_ZERO));
+
+ //
+ // Set the parity mode.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
+ ~(UART_LCRH_SPS | UART_LCRH_EPS |
+ UART_LCRH_PEN)) | ulParity);
+}
+
+//*****************************************************************************
+//
+//! Gets the type of parity currently being used.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function gets the type of parity used for transmitting data, and
+//! expected when receiving data.
+//!
+//! \return Returns the current parity settings, specified as one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
+//
+//*****************************************************************************
+unsigned long
+UARTParityModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current parity setting.
+ //
+ return(HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
+//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
+//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
+//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
+//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function sets the FIFO level at which transmit and receive interrupts
+//! will be generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
+ (ulTxLevel == UART_FIFO_TX2_8) ||
+ (ulTxLevel == UART_FIFO_TX4_8) ||
+ (ulTxLevel == UART_FIFO_TX6_8) ||
+ (ulTxLevel == UART_FIFO_TX7_8));
+ ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
+ (ulRxLevel == UART_FIFO_RX2_8) ||
+ (ulRxLevel == UART_FIFO_RX4_8) ||
+ (ulRxLevel == UART_FIFO_RX6_8) ||
+ (ulRxLevel == UART_FIFO_RX7_8));
+
+ //
+ // Set the FIFO interrupt levels.
+ //
+ HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
+//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or UART_FIFO_TX7_8.
+//! \param pulRxLevel is a pointer to storage for the receive FIFO level,
+//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
+//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function gets the FIFO level at which transmit and receive interrupts
+//! will be generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Read the FIFO level register.
+ //
+ ulTemp = HWREG(ulBase + UART_O_IFLS);
+
+ //
+ // Extract the transmit and receive FIFO levels.
+ //
+ *pulTxLevel = ulTemp & UART_IFLS_TX_M;
+ *pulRxLevel = ulTemp & UART_IFLS_RX_M;
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param ulBaud is the desired baud rate.
+//! \param ulConfig is the data format for the port (number of data bits,
+//! number of stop bits, and parity).
+//!
+//! This function will configure the UART for operation in the specified data
+//! format. The baud rate is provided in the \e ulBaud parameter and the data
+//! format in the \e ulConfig parameter.
+//!
+//! The \e ulConfig parameter is the logical OR of three values: the number of
+//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
+//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
+//! select from eight to five data bits per byte (respectively).
+//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
+//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
+//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
+//! select the parity mode (no parity bit, even parity bit, odd parity bit,
+//! parity bit always one, and parity bit always zero, respectively).
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original UARTConfigSet() API and performs the
+//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig)
+{
+ unsigned long ulDiv;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT(ulBaud != 0);
+ ASSERT(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER));
+
+ //
+ // Stop the UART.
+ //
+ UARTDisable(ulBase);
+
+ //
+ // Is the required baud rate greater than the maximum rate supported
+ // without the use of high speed mode?
+ //
+ if((ulBaud * 16) > ulUARTClk)
+ {
+ //
+ // Enable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE;
+
+ //
+ // Half the supplied baud rate to compensate for enabling high speed
+ // mode. This allows the following code to be common to both cases.
+ //
+ ulBaud /= 2;
+ }
+ else
+ {
+ //
+ // Disable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE);
+ }
+
+ //
+ // Compute the fractional baud rate divider.
+ //
+ ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
+
+ //
+ // Set the baud rate.
+ //
+ HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
+ HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
+
+ //
+ // Set parity, data length, and number of stop bits.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ulConfig;
+
+ //
+ // Clear the flags register.
+ //
+ HWREG(ulBase + UART_O_FR) = 0;
+
+ //
+ // Start the UART.
+ //
+ UARTEnable(ulBase);
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param pulBaud is a pointer to storage for the baud rate.
+//! \param pulConfig is a pointer to storage for the data format.
+//!
+//! The baud rate and data format for the UART is determined, given an
+//! explicitly provided peripheral clock (hence the ExpClk suffix). The
+//! returned baud rate is the actual baud rate; it may not be the exact baud
+//! rate requested or an ``official'' baud rate. The data format returned in
+//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
+//! UARTConfigSetExpClk().
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original UARTConfigGet() API and performs the
+//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud, unsigned long *pulConfig)
+{
+ unsigned long ulInt, ulFrac;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Compute the baud rate.
+ //
+ ulInt = HWREG(ulBase + UART_O_IBRD);
+ ulFrac = HWREG(ulBase + UART_O_FBRD);
+ *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
+
+ //
+ // See if high speed mode enabled.
+ //
+ if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE)
+ {
+ //
+ // High speed mode is enabled so the actual baud rate is actually
+ // double what was just calculated.
+ //
+ *pulBaud *= 2;
+ }
+
+ //
+ // Get the parity, data length, and number of stop bits.
+ //
+ *pulConfig = (HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
+ UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Enables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
+//! FIFOs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+
+ //
+ // Enable RX, TX, and the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Disables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
+//! transmission of the current character, and flushes the transmit FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait for end of TX.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
+ {
+ }
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+
+ //
+ // Disable the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions enables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions disables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFODisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+}
+
+//*****************************************************************************
+//
+//! Enables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bLowPower indicates if SIR Low Power Mode is to be used.
+//!
+//! Enables the SIREN control bit for IrDA mode on the UART. If the
+//! \e bLowPower flag is set, then SIRLP bit will also be set.
+//!
+//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable SIR and SIRLP (if appropriate).
+ //
+ if(bLowPower)
+ {
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
+ }
+ else
+ {
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
+//!
+//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisableSIR(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable SIR and SIRLP (if appropriate).
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
+}
+
+//*****************************************************************************
+//
+//! Enables ISO 7816 smart card mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
+//! This call also sets 8 bit word length and even parity as required by ISO
+//! 7816.
+//!
+//! \note The availability of ISO 7816 smart card mode varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardEnable(unsigned long ulBase)
+{
+ unsigned long ulVal;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ //
+ // Set 8 bit word length, even parity, 2 stop bits (even though the STP2
+ // bit is ignored when in smartcard mode, this lets the caller read back
+ // the actual setting in use).
+ //
+ ulVal = HWREG(ulBase + UART_O_LCRH);
+ ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
+ UART_LCRH_WLEN_M);
+ ulVal |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_STP2;
+ HWREG(ulBase + UART_O_LCRH) = ulVal;
+
+ //
+ // Enable SMART mode.
+ //
+ HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Disables ISO 7816 smart card mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
+//!
+//! \note The availability of ISO 7816 smart card mode varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ //
+ // Disable the SMART bit.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Sets the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! Sets the states of the DTR or RTS modem handshake outputs from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp |= (ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Clears the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! Clears the states of the DTR or RTS modem handshake outputs from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp &= ~(ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the DTR and RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current states of each of the two UART modem control signals,
+//! DTR and RTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This will be a
+//! logical logical OR combination of values \b UART_OUTPUT_RTS and
+//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
+//! associated signal is asserted.
+//
+//*****************************************************************************
+unsigned long
+UARTModemControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the RI, DCD, DSR and CTS modem status signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current states of each of the four UART modem status signals,
+//! RI, DCD, DSR and CTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This will be a
+//! logical logical OR combination of values \b UART_INPUT_RI, \b
+//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
+//! presence of each flag indicates that the associated signal is asserted.
+//
+//*****************************************************************************
+unsigned long
+UARTModemStatusGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+
+ return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD |
+ UART_INPUT_CTS | UART_INPUT_DSR));
+}
+
+//*****************************************************************************
+//
+//! Sets the UART hardware flow control mode to be used.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode indicates the flow control modes to be used. This is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
+//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
+//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
+//!
+//! Sets the required hardware flow control modes. If \e ulMode contains
+//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
+//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
+//! the RTS output is controlled by the hardware and is asserted only when
+//! there is space available in the receive FIFO. If no hardware flow control
+//! is required, UART_FLOWCONTROL_NONE should be passed.
+//!
+//! \note The availability of hardware flow control varies with the Stellaris
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+ ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
+
+ //
+ // Set the flow control mode as requested.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the UART hardware flow control mode currently in use.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current hardware flow control mode.
+//!
+//! \note The availability of hardware flow control varies with the Stellaris
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns the current flow control mode in use. This is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
+//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
+//! flow control is in use. If hardware flow control is disabled, \b
+//! UART_FLOWCONTROL_NONE will be returned.
+//
+//*****************************************************************************
+unsigned long
+UARTFlowControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX));
+}
+
+//*****************************************************************************
+//
+//! Sets the operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode is the operating mode for the transmit interrupt. It may be
+//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
+//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
+//! level.
+//!
+//! This function allows the mode of the UART transmit interrupt to be set. By
+//! default, the transmit interrupt is asserted when the FIFO level falls past
+//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
+//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
+//! transmit interrupt will only be asserted once the transmitter is completely
+//! idle - the transmit FIFO is empty and all bits, including any stop bits,
+//! have cleared the transmitter.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Stellaris part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+ ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
+ (ulMode == UART_TXINT_MODE_FIFO));
+
+ //
+ // Set or clear the EOT bit of the UART control register as appropriate.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current operating mode for the UART transmit
+//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the
+//! transmit interrupt is currently set to be asserted once the transmitter is
+//! completely idle - the transmit FIFO is empty and all bits, including any
+//! stop bits, have cleared the transmitter. The return value will be \b
+//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
+//! level of the transmit FIFO.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Stellaris part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
+//
+//*****************************************************************************
+unsigned long
+UARTTxIntModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+
+ //
+ // Return the current transmit interrupt mode.
+ //
+ return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO));
+}
+
+//*****************************************************************************
+//
+//! Determines if there are any characters in the receive FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is data
+//! available in the receive FIFO.
+//!
+//! \return Returns \b true if there is data in the receive FIFO, and \b false
+//! if there is no data in the receive FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharsAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of characters.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Determines if there is any space in the transmit FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is space
+//! available in the transmit FIFO.
+//!
+//! \return Returns \b true if there is space available in the transmit FIFO,
+//! and \b false if there is no space available in the transmit FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTSpaceAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Receives a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Gets a character from the receive FIFO for the specified port.
+//!
+//! This function replaces the original UARTCharNonBlockingGet() API and
+//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
+//! the original API to this API.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e long. A \b -1 will be returned if there are no characters present in
+//! the receive FIFO. The UARTCharsAvail() function should be called before
+//! attempting to call this function.
+//
+//*****************************************************************************
+long
+UARTCharGetNonBlocking(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there are any characters in the receive FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
+ {
+ //
+ // Read and return the next character.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+ }
+ else
+ {
+ //
+ // There are no characters, so return a failure.
+ //
+ return(-1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits for a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Gets a character from the receive FIFO for the specified port. If there
+//! are no characters available, this function will wait until a character is
+//! received before returning.
+//!
+//! \return Returns the character read from the specified port, cast as an
+//! \e long.
+//
+//*****************************************************************************
+long
+UARTCharGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until a char is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
+ {
+ }
+
+ //
+ // Now get the char.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+}
+
+//*****************************************************************************
+//
+//! Sends a character to the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! Writes the character \e ucData to the transmit FIFO for the specified port.
+//! This function does not block, so if there is no space available, then a
+//! \b false is returned, and the application will have to retry the function
+//! later.
+//!
+//! This function replaces the original UARTCharNonBlockingPut() API and
+//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
+//! the original API to this API.
+//!
+//! \return Returns \b true if the character was successfully placed in the
+//! transmit FIFO, and \b false if there was no space available in the transmit
+//! FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there is space in the transmit FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
+ {
+ //
+ // Write this character to the transmit FIFO.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+
+ //
+ // Success.
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // There is no space in the transmit FIFO, so return a failure.
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits to send a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! Sends the character \e ucData to the transmit FIFO for the specified port.
+//! If there is no space available in the transmit FIFO, this function will
+//! wait until there is space available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTCharPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until space is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
+ {
+ }
+
+ //
+ // Send the char.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Causes a BREAK to be sent.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bBreakState controls the output level.
+//!
+//! Calling this function with \e bBreakState set to \b true will assert a
+//! break condition on the UART. Calling this function with \e bBreakState set
+//! to \b false will remove the break condition. For proper transmission of a
+//! break command, the break must be asserted for at least two complete frames.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the break condition as requested.
+ //
+ HWREG(ulBase + UART_O_LCRH) =
+ (bBreakState ?
+ (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
+ (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
+}
+
+//*****************************************************************************
+//
+//! Determines whether the UART transmitter is busy or not.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware. If \b false is returned, the transmit FIFO is
+//! empty and all bits of the last transmitted character, including all stop
+//! bits, have left the hardware shift register.
+//!
+//! \return Returns \b true if the UART is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+tBoolean
+UARTBusy(unsigned long ulBase)
+{
+ //
+ // Check the argument.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine if the UART is busy.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! will enable the global interrupt in the interrupt controller; specific UART
+//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the UART interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! will clear the handler to be called when a UART interrupt occurs. This
+//! will also mask off the interrupt in the interrupt controller so that the
+//! interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated UART interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b UART_INT_OE - Overrun Error interrupt
+//! - \b UART_INT_BE - Break Error interrupt
+//! - \b UART_INT_PE - Parity Error interrupt
+//! - \b UART_INT_FE - Framing Error interrupt
+//! - \b UART_INT_RT - Receive Timeout interrupt
+//! - \b UART_INT_TX - Transmit interrupt
+//! - \b UART_INT_RX - Receive interrupt
+//! - \b UART_INT_DSR - DSR interrupt
+//! - \b UART_INT_DCD - DCD interrupt
+//! - \b UART_INT_CTS - CTS interrupt
+//! - \b UART_INT_RI - RI interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated UART interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bMasked is false if the raw interrupt status is required and true
+//! if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the specified UART. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in UARTIntEnable().
+//
+//*****************************************************************************
+unsigned long
+UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + UART_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + UART_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified UART interrupt sources are cleared, so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + UART_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified UART DMA features are enabled. The UART can be
+//! configured to use DMA for transmit or receive, and to disable
+//! receive if an error occurs. The \e ulDMAFlags parameter is the
+//! logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - enable DMA for receive
+//! - UART_DMA_TX - enable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable UART DMA features that were enabled
+//! by UARTDMAEnable(). The specified UART DMA features are disabled. The
+//! \e ulDMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - disable DMA for receive
+//! - UART_DMA_TX - disable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets current receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current state of each of the 4 receiver error
+//! sources. The returned errors are equivalent to the four error bits
+//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
+//! with the exception that the overrun error is set immediately the overrun
+//! occurs rather than when a character is next read.
+//!
+//! \return Returns a logical OR combination of the receiver error flags,
+//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
+//! and \b UART_RXERROR_OVERRUN.
+//
+//*****************************************************************************
+unsigned long
+UARTRxErrorGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current value of the receive status register.
+ //
+ return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! Clears all reported receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function is used to clear all receiver error conditions reported via
+//! UARTRxErrorGet(). If using the overrun, framing error, parity error or
+//! break interrupts, this function must be called after clearing the interrupt
+//! to ensure that later errors of the same type trigger another interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTRxErrorClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Any write to the Error Clear Register will clear all bits which are
+ // currently set.
+ //
+ HWREG(ulBase + UART_O_ECR) = 0;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/uart.h b/bsp/lm3s/Libraries/driverlib/uart.h new file mode 100644 index 0000000000..5c8416cc1b --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/uart.h @@ -0,0 +1,246 @@ +//*****************************************************************************
+//
+// uart.h - Defines and Macros for the UART.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __UART_H__
+#define __UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ulIntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask
+#define UART_INT_RX 0x010 // Receive Interrupt Mask
+#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
+#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
+#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
+#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
+// and returned by UARTConfigGetExpClk in the pulConfig parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ulParity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
+#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
+#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulTxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulRxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN 0x00000008
+#define UART_RXERROR_BREAK 0x00000004
+#define UART_RXERROR_PARITY 0x00000002
+#define UART_RXERROR_FRAMING 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTHandshakeOutputsSet() or returned from
+// UARTHandshakeOutputGet().
+//
+//*****************************************************************************
+#define UART_OUTPUT_RTS 0x00000800
+#define UART_OUTPUT_DTR 0x00000400
+
+//*****************************************************************************
+//
+// Values that can be returned from UARTHandshakeInputsGet().
+//
+//*****************************************************************************
+#define UART_INPUT_RI 0x00000100
+#define UART_INPUT_DCD 0x00000004
+#define UART_INPUT_DSR 0x00000002
+#define UART_INPUT_CTS 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFlowControl() or returned from
+// UARTFlowControlGet().
+//
+//*****************************************************************************
+#define UART_FLOWCONTROL_TX 0x00008000
+#define UART_FLOWCONTROL_RX 0x00004000
+#define UART_FLOWCONTROL_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTTxIntModeSet() or returned from
+// UARTTxIntModeGet().
+//
+//*****************************************************************************
+#define UART_TXINT_MODE_FIFO 0x00000000
+#define UART_TXINT_MODE_EOT 0x00000010
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
+extern unsigned long UARTParityModeGet(unsigned long ulBase);
+extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel);
+extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel);
+extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig);
+extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud,
+ unsigned long *pulConfig);
+extern void UARTEnable(unsigned long ulBase);
+extern void UARTDisable(unsigned long ulBase);
+extern void UARTFIFOEnable(unsigned long ulBase);
+extern void UARTFIFODisable(unsigned long ulBase);
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
+extern void UARTDisableSIR(unsigned long ulBase);
+extern tBoolean UARTCharsAvail(unsigned long ulBase);
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);
+extern long UARTCharGetNonBlocking(unsigned long ulBase);
+extern long UARTCharGet(unsigned long ulBase);
+extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
+ unsigned char ucData);
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
+extern tBoolean UARTBusy(unsigned long ulBase);
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void UARTIntUnregister(unsigned long ulBase);
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern unsigned long UARTRxErrorGet(unsigned long ulBase);
+extern void UARTRxErrorClear(unsigned long ulBase);
+extern void UARTSmartCardEnable(unsigned long ulBase);
+extern void UARTSmartCardDisable(unsigned long ulBase);
+extern void UARTModemControlSet(unsigned long ulBase,
+ unsigned long ulControl);
+extern void UARTModemControlClear(unsigned long ulBase,
+ unsigned long ulControl);
+extern unsigned long UARTModemControlGet(unsigned long ulBase);
+extern unsigned long UARTModemStatusGet(unsigned long ulBase);
+extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTFlowControlGet(unsigned long ulBase);
+extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several UART APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define UARTConfigSet(a, b, c) \
+ UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTConfigGet(a, b, c) \
+ UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTCharNonBlockingGet(a) \
+ UARTCharGetNonBlocking(a)
+#define UARTCharNonBlockingPut(a, b) \
+ UARTCharPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UART_H__
diff --git a/bsp/lm3s/Libraries/driverlib/udma.c b/bsp/lm3s/Libraries/driverlib/udma.c new file mode 100644 index 0000000000..3f4729ce45 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/udma.c @@ -0,0 +1,1247 @@ +//*****************************************************************************
+//
+// udma.c - Driver for the micro-DMA controller.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_udma.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+
+//*****************************************************************************
+//
+//! Enables the uDMA controller for use.
+//!
+//! This function enables the uDMA controller. The uDMA controller must be
+//! enabled before it can be configured and used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAEnable(void)
+{
+ //
+ // Set the master enable bit in the config register.
+ //
+ HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the uDMA controller for use.
+//!
+//! This function disables the uDMA controller. Once disabled, the uDMA
+//! controller will not operate until re-enabled with uDMAEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMADisable(void)
+{
+ //
+ // Clear the master enable bit in the config register.
+ //
+ HWREG(UDMA_CFG) = 0;
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA error status.
+//!
+//! This function returns the uDMA error status. It should be called from
+//! within the uDMA error interrupt handler to determine if a uDMA error
+//! occurred.
+//!
+//! \return Returns non-zero if a uDMA error is pending.
+//
+//*****************************************************************************
+unsigned long
+uDMAErrorStatusGet(void)
+{
+ //
+ // Return the uDMA error status.
+ //
+ return(HWREG(UDMA_ERRCLR));
+}
+
+//*****************************************************************************
+//
+//! Clears the uDMA error interrupt.
+//!
+//! This function clears a pending uDMA error interrupt. It should be called
+//! from within the uDMA error interrupt handler to clear the interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAErrorStatusClear(void)
+{
+ //
+ // Clear the uDMA error interrupt.
+ //
+ HWREG(UDMA_ERRCLR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables a uDMA channel for operation.
+//!
+//! \param ulChannel is the channel number to enable.
+//!
+//! This function enables a specific uDMA channel for use. This function must
+//! be used to enable a channel before it can be used to perform a uDMA
+//! transfer.
+//!
+//! When a uDMA transfer is completed, the channel will be automatically
+//! disabled by the uDMA controller. Therefore, this function should be called
+//! prior to starting up any new transfer.
+//!
+//! The \e ulChannel parameter must be one of the following:
+//!
+//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel
+//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel
+//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel
+//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel
+//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel
+//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel
+//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel
+//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel
+//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel
+//!
+//! And for microcontrollers that have a USB peripheral:
+//!
+//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive
+//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit
+//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive
+//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit
+//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive
+//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelEnable(unsigned long ulChannel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 32);
+
+ //
+ // Set the bit for this channel in the enable set register.
+ //
+ HWREG(UDMA_ENASET) = 1 << ulChannel;
+}
+
+//*****************************************************************************
+//
+//! Disables a uDMA channel for operation.
+//!
+//! \param ulChannel is the channel number to disable.
+//!
+//! This function disables a specific uDMA channel. Once disabled, a channel
+//! will not respond to uDMA transfer requests until re-enabled via
+//! uDMAChannelEnable().
+//!
+//! The \e ulChannel parameter must be one of the following:
+//!
+//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel
+//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel
+//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel
+//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel
+//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel
+//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel
+//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel
+//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel
+//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel
+//!
+//! And for microcontrollers that have a USB peripheral:
+//!
+//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive
+//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit
+//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive
+//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit
+//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive
+//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelDisable(unsigned long ulChannel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 32);
+
+ //
+ // Set the bit for this channel in the enable clear register.
+ //
+ HWREG(UDMA_ENACLR) = 1 << ulChannel;
+}
+
+//*****************************************************************************
+//
+//! Checks if a uDMA channel is enabled for operation.
+//!
+//! \param ulChannel is the channel number to check.
+//!
+//! This function checks to see if a specific uDMA channel is enabled. This
+//! can be used to check the status of a transfer, since the channel will
+//! be automatically disabled at the end of a transfer.
+//!
+//! The \e ulChannel parameter must be one of the following:
+//!
+//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel
+//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel
+//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel
+//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel
+//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel
+//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel
+//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel
+//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel
+//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel
+//!
+//! And for microcontrollers that have a USB peripheral:
+//!
+//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive
+//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit
+//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive
+//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit
+//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive
+//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit
+//!
+//! \return Returns \b true if the channel is enabled, \b false if disabled.
+//
+//*****************************************************************************
+tBoolean
+uDMAChannelIsEnabled(unsigned long ulChannel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 32);
+
+ //
+ // AND the specified channel bit with the enable register, and return the
+ // result.
+ //
+ return((HWREG(UDMA_ENASET) & (1 << ulChannel)) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the base address for the channel control table.
+//!
+//! \param pControlTable is a pointer to the 1024 byte aligned base address
+//! of the uDMA channel control table.
+//!
+//! This function sets the base address of the channel control table. This
+//! table resides in system memory and holds control information for each uDMA
+//! channel. The table must be aligned on a 1024 byte boundary. The base
+//! address must be set before any of the channel functions can be used.
+//!
+//! The size of the channel control table depends on the number of uDMA
+//! channels, and which transfer modes are used. Refer to the introductory
+//! text and the microcontroller datasheet for more information about the
+//! channel control table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAControlBaseSet(void *pControlTable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(((unsigned long)pControlTable & ~0x3FF) ==
+ (unsigned long)pControlTable);
+ ASSERT((unsigned long)pControlTable >= 0x20000000);
+
+ //
+ // Program the base address into the register.
+ //
+ HWREG(UDMA_CTLBASE) = (unsigned long)pControlTable;
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table.
+//!
+//! This function gets the base address of the channel control table. This
+//! table resides in system memory and holds control information for each uDMA
+//! channel.
+//!
+//! \return Returns a pointer to the base address of the channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlBaseGet(void)
+{
+ //
+ // Read the current value of the control base register, and return it to
+ // the caller.
+ //
+ return((void *)HWREG(UDMA_CTLBASE));
+}
+
+//*****************************************************************************
+//
+//! Requests a uDMA channel to start a transfer.
+//!
+//! \param ulChannel is the channel number on which to request a uDMA transfer.
+//!
+//! This function allows software to request a uDMA channel to begin a
+//! transfer. This could be used for performing a memory to memory transfer,
+//! or if for some reason a transfer needs to be initiated by software instead
+//! of the peripheral associated with that channel.
+//!
+//! The \e ulChannel parameter must be one of the following:
+//!
+//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel
+//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel
+//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel
+//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel
+//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel
+//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel
+//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel
+//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel
+//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel
+//!
+//! And for microcontrollers that have a USB peripheral:
+//!
+//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive
+//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit
+//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive
+//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit
+//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive
+//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit
+//!
+//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then
+//! the completion will be signaled on the uDMA dedicated interrupt. If a
+//! peripheral channel is used, then the completion will be signaled on the
+//! peripheral's interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelRequest(unsigned long ulChannel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 32);
+
+ //
+ // Set the bit for this channel in the software uDMA request register.
+ //
+ HWREG(UDMA_SWREQ) = 1 << ulChannel;
+}
+
+//*****************************************************************************
+//
+//! Enables attributes of a uDMA channel.
+//!
+//! \param ulChannel is the channel to configure.
+//! \param ulAttr is a combination of attributes for the channel.
+//!
+//! The \e ulChannel parameter must be one of the following:
+//!
+//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel
+//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel
+//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel
+//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel
+//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel
+//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel
+//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel
+//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel
+//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel
+//!
+//! And for microcontrollers that have a USB peripheral:
+//!
+//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive
+//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit
+//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive
+//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit
+//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive
+//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit
+//!
+//! The \e ulAttr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 32);
+ ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ //
+ // Set the useburst bit for this channel if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(UDMA_USEBURSTSET) = 1 << ulChannel;
+ }
+
+ //
+ // Set the alternate control select bit for this channel,
+ // if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(UDMA_ALTSET) = 1 << ulChannel;
+ }
+
+ //
+ // Set the high priority bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(UDMA_PRIOSET) = 1 << ulChannel;
+ }
+
+ //
+ // Set the request mask bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(UDMA_REQMASKSET) = 1 << ulChannel;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables attributes of a uDMA channel.
+//!
+//! \param ulChannel is the channel to configure.
+//! \param ulAttr is a combination of attributes for the channel.
+//!
+//! This function is used to disable attributes of a uDMA channel.
+//!
+//! The \e ulChannel parameter must be one of the following:
+//!
+//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel
+//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel
+//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel
+//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel
+//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel
+//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel
+//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel
+//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel
+//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel
+//!
+//! And for microcontrollers that have a USB peripheral:
+//!
+//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive
+//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit
+//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive
+//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit
+//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive
+//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit
+//!
+//! The \e ulAttr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 32);
+ ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ //
+ // Clear the useburst bit for this channel if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(UDMA_USEBURSTCLR) = 1 << ulChannel;
+ }
+
+ //
+ // Clear the alternate control select bit for this channel, if set in
+ // ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(UDMA_ALTCLR) = 1 << ulChannel;
+ }
+
+ //
+ // Clear the high priority bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(UDMA_PRIOCLR) = 1 << ulChannel;
+ }
+
+ //
+ // Clear the request mask bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(UDMA_REQMASKCLR) = 1 << ulChannel;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the enabled attributes of a uDMA channel.
+//!
+//! \param ulChannel is the channel to configure.
+//!
+//! This function returns a combination of flags representing the attributes of
+//! the uDMA channel.
+//!
+//! The \e ulChannel parameter must be one of the following:
+//!
+//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel
+//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel
+//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel
+//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel
+//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel
+//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel
+//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel
+//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel
+//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel
+//!
+//! And for microcontrollers that have a USB peripheral:
+//!
+//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive
+//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit
+//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive
+//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit
+//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive
+//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit
+//!
+//! \return Returns the logical OR of the attributes of the uDMA channel, which
+//! can be any of the following:
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelAttributeGet(unsigned long ulChannel)
+{
+ unsigned long ulAttr = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 32);
+
+ //
+ // Check to see if useburst bit is set for this channel.
+ //
+ if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannel))
+ {
+ ulAttr |= UDMA_ATTR_USEBURST;
+ }
+
+ //
+ // Check to see if the alternate control bit is set for this channel.
+ //
+ if(HWREG(UDMA_ALTSET) & (1 << ulChannel))
+ {
+ ulAttr |= UDMA_ATTR_ALTSELECT;
+ }
+
+ //
+ // Check to see if the high priority bit is set for this channel.
+ //
+ if(HWREG(UDMA_PRIOSET) & (1 << ulChannel))
+ {
+ ulAttr |= UDMA_ATTR_HIGH_PRIORITY;
+ }
+
+ //
+ // Check to see if the request mask bit is set for this channel.
+ //
+ if(HWREG(UDMA_REQMASKSET) & (1 << ulChannel))
+ {
+ ulAttr |= UDMA_ATTR_REQMASK;
+ }
+
+ //
+ // Return the configuration flags.
+ //
+ return(ulAttr);
+}
+
+//*****************************************************************************
+//
+//! Sets the control parameters for a uDMA channel.
+//!
+//! \param ulChannel is the logical OR of the uDMA channel number with
+//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ulControl is logical OR of several control values to set the control
+//! parameters for the channel.
+//!
+//! This function is used to set control parameters for a uDMA transfer. These
+//! are typically parameters that are not changed often.
+//!
+//! The \e ulChannel parameter is one of the choices documented in the
+//! uDMAChannelEnable() function. It should be the logical OR of the channel
+//! with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether
+//! the primary or alternate data structure is used.
+//!
+//! The \e ulControl parameter is the logical OR of five values: the data size,
+//! the source address increment, the destination address increment, the
+//! arbitration size, and the use burst flag. The choices available for each
+//! of these values is described below.
+//!
+//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or
+//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits.
+//!
+//! Choose the source address increment from one of \b UDMA_SRC_INC_8,
+//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! Choose the destination address increment from one of \b UDMA_DST_INC_8,
+//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! The arbitration size determines how many items are transferred before
+//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size
+//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8,
+//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024
+//! items, in powers of 2.
+//!
+//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only
+//! respond to burst requests at the tail end of a scatter-gather transfer.
+//!
+//! \note The address increment cannot be smaller than the data size.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelControlSet(unsigned long ulChannel, unsigned long ulControl)
+{
+ tDMAControlTable *pCtl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // Get the base address of the control table.
+ //
+ pCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off the fields to be
+ // changed, then OR in the new settings.
+ //
+ pCtl[ulChannel].ulControl = ((pCtl[ulChannel].ulControl &
+ ~(UDMA_CHCTL_DSTINC_M |
+ UDMA_CHCTL_DSTSIZE_M |
+ UDMA_CHCTL_SRCINC_M |
+ UDMA_CHCTL_SRCSIZE_M |
+ UDMA_CHCTL_ARBSIZE_M |
+ UDMA_CHCTL_NXTUSEBURST)) |
+ ulControl);
+}
+
+//*****************************************************************************
+//
+//! Sets the transfer parameters for a uDMA channel.
+//!
+//! \param ulChannel is the logical or of the uDMA channel number with either
+//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ulMode is the type of uDMA transfer.
+//! \param pvSrcAddr is the source address for the transfer.
+//! \param pvDstAddr is the destination address for the transfer.
+//! \param ulTransferSize is the number of data items to transfer.
+//!
+//! This function is used to set the parameters for a uDMA transfer. These are
+//! typically parameters that are changed often. The function
+//! uDMAChannelControlSet() MUST be called at least once for this channel prior
+//! to calling this function.
+//!
+//! The \e ulChannel parameter is one of the choices documented in the
+//! uDMAChannelEnable() function. It should be the logical OR of the channel
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether the
+//! primary or alternate data structure is used.
+//!
+//! The \e ulMode parameter should be one of the following values:
+//!
+//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode
+//! to this value at the end of a transfer.
+//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request.
+//! - \b UDMA_MODE_AUTO to perform a transfer that will always complete once
+//! started even if request is removed.
+//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the
+//! primary and alternate control structures for the channel. This allows
+//! use of ping-pong buffering for uDMA transfers.
+//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather
+//! transfer.
+//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather
+//! transfer.
+//!
+//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first
+//! location of the data to be transferred. These addresses should be aligned
+//! according to the item size. The compiler will take care of this if the
+//! pointers are pointing to storage of the appropriate data type.
+//!
+//! The \e ulTransferSize parameter is the number of data items, not the number
+//! of bytes.
+//!
+//! The two scatter/gather modes, memory and peripheral, are actually different
+//! depending on whether the primary or alternate control structure is
+//! selected. This function will look for the \b UDMA_PRI_SELECT and
+//! \b UDMA_ALT_SELECT flag along with the channel number and will set the
+//! scatter/gather mode as appropriate for the primary or alternate control
+//! structure.
+//!
+//! The channel must also be enabled using uDMAChannelEnable() after calling
+//! this function. The transfer will not begin until the channel has been set
+//! up and enabled. Note that the channel is automatically disabled after the
+//! transfer is completed, meaning that uDMAChannelEnable() must be called
+//! again after setting up the next transfer.
+//!
+//! \note Great care must be taken to not modify a channel control structure
+//! that is in use or else the results will be unpredictable, including the
+//! possibility of undesired data transfers to or from memory or peripherals.
+//! For BASIC and AUTO modes, it is safe to make changes when the channel is
+//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For
+//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
+//! primary or alternate control structure only when the other is being used.
+//! The uDMAChannelModeGet() function will return \b UDMA_MODE_STOP when a
+//! channel control structure is inactive and safe to modify.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode,
+ void *pvSrcAddr, void *pvDstAddr,
+ unsigned long ulTransferSize)
+{
+ tDMAControlTable *pControlTable;
+ unsigned long ulControl;
+ unsigned long ulSize;
+ unsigned long ulInc;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+ ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER);
+ ASSERT((unsigned long)pvSrcAddr >= 0x20000000);
+ ASSERT((unsigned long)pvDstAddr >= 0x20000000);
+ ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024));
+
+ //
+ // Get the base address of the control table.
+ //
+ pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off the mode and size
+ // fields.
+ //
+ ulControl = (pControlTable[ulChannel].ulControl &
+ ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+ //
+ // Adjust the mode if the alt control structure is selected.
+ //
+ if(ulChannel & UDMA_ALT_SELECT)
+ {
+ if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ (ulMode == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ulMode |= UDMA_MODE_ALT_SELECT;
+ }
+ }
+
+ //
+ // Set the transfer size and mode in the control word (but dont write the
+ // control word yet as it could kick off a transfer).
+ //
+ ulControl |= ulMode | ((ulTransferSize - 1) << 4);
+
+ //
+ // Get the data item size from the control word (set previously).
+ //
+ ulSize = (ulControl & UDMA_CHCTL_DSTSIZE_M) >> 28;
+
+ //
+ // Convert the transfer size to be in units of bytes. Shift (multiply) to
+ // get the value in bytes, based on the data item size.
+ //
+ ulTransferSize = ulTransferSize << ulSize;
+
+ //
+ // Get the address increment value for the source, from the control word.
+ //
+ ulInc = (ulControl & UDMA_CHCTL_SRCINC_M);
+
+ //
+ // Compute the ending source address of the transfer. If the source
+ // increment is set to none, then the ending address is the same as the
+ // beginning.
+ //
+ if(ulInc != UDMA_SRC_INC_NONE)
+ {
+ pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulTransferSize - 1);
+ }
+
+ //
+ // Load the source ending address into the control block.
+ //
+ pControlTable[ulChannel].pvSrcEndAddr = pvSrcAddr;
+
+ //
+ // Get the address increment value for the destination, from the control
+ // word.
+ //
+ ulInc = (ulControl & UDMA_CHCTL_DSTINC_M);
+
+ //
+ // Compute the ending destination address of the transfer. If the
+ // destination increment is set to none, then the ending address is the
+ // same as the beginning.
+ //
+ if(ulInc != UDMA_DST_INC_NONE)
+ {
+ pvDstAddr = (void *)((unsigned long)pvDstAddr + ulTransferSize - 1);
+ }
+
+ //
+ // Load the destination ending address into the control block.
+ //
+ pControlTable[ulChannel].pvDstEndAddr = pvDstAddr;
+
+ //
+ // Write the new control word value.
+ //
+ pControlTable[ulChannel].ulControl = ulControl;
+}
+
+//*****************************************************************************
+//
+//! Gets the current transfer size for a uDMA channel.
+//!
+//! \param ulChannel is the logical or of the uDMA channel number with either
+//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the uDMA transfer size for a channel. The
+//! transfer size is the number of items to transfer, where the size of an item
+//! might be 8, 16, or 32 bits. If a partial transfer has already occurred,
+//! then the number of remaining items will be returned. If the transfer is
+//! complete, then 0 will be returned.
+//!
+//! The \e ulChannel parameter is one of the choices documented in the
+//! uDMAChannelEnable() function. It should be the logical OR of the channel
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether
+//! the primary or alternate data structure is used.
+//!
+//! \return Returns the number of items remaining to transfer.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelSizeGet(unsigned long ulChannel)
+{
+ tDMAControlTable *pControlTable;
+ unsigned long ulControl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // Get the base address of the control table.
+ //
+ pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off all but the size field.
+ //
+ ulControl = pControlTable[ulChannel].ulControl & UDMA_CHCTL_XFERSIZE_M;
+
+ //
+ // Shift the size field and add one, then return to user.
+ //
+ return((ulControl >> 4) + 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the transfer mode for a uDMA channel.
+//!
+//! \param ulChannel is the logical or of the uDMA channel number with either
+//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the transfer mode for the uDMA channel. It
+//! can be used to query the status of a transfer on a channel. When the
+//! transfer is complete the mode will be \b UDMA_MODE_STOP.
+//!
+//! The \e ulChannel parameter is one of the choices documented in the
+//! uDMAChannelEnable() function. It should be the logical OR of the channel
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether the
+//! primary or alternate data structure is used.
+//!
+//! \return Returns the transfer mode of the specified channel and control
+//! structure, which will be one of the following values: \b UDMA_MODE_STOP,
+//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelModeGet(unsigned long ulChannel)
+{
+ tDMAControlTable *pControlTable;
+ unsigned long ulControl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannel < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // Get the base address of the control table.
+ //
+ pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off all but the mode field.
+ //
+ ulControl = pControlTable[ulChannel].ulControl & UDMA_CHCTL_XFERMODE_M;
+
+ //
+ // Check if scatter/gather mode, and if so, mask off the alt bit.
+ //
+ if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ulControl &= ~UDMA_MODE_ALT_SELECT;
+ }
+
+ //
+ // Return the mode to the caller.
+ //
+ return(ulControl);
+}
+
+//*****************************************************************************
+//
+//! Select the secondary peripheral for a set of uDMA channels.
+//!
+//! \param ulSecPeriphs is the logical or of the uDMA channels for which to
+//! use the secondary peripheral, instead of the default peripheral.
+//!
+//! This function is used to select the secondary peripheral assignment for
+//! a set of uDMA channels. By selecting the secondary peripheral assignment
+//! for a channel, the default peripheral assignment is no longer available
+//! for that channel.
+//!
+//! The parameter \e ulSecPeriphs can be the logical OR of any of the
+//! following macros. If one of the macros below is in the list passed
+//! to this function, then the secondary peripheral (marked as \b _SEC_)
+//! will be selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_GPIORX
+//! - \b UDMA_DEF_TMR1B_SEC_GPIOTX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectSecondary(unsigned long ulSecPeriphs)
+{
+ //
+ // Select the secondary peripheral for the specified channels.
+ //
+ HWREG(UDMA_CHALT) |= ulSecPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Select the default peripheral for a set of uDMA channels.
+//!
+//! \param ulDefPeriphs is the logical or of the uDMA channels for which to
+//! use the default peripheral, instead of the secondary peripheral.
+//!
+//! This function is used to select the default peripheral assignment for
+//! a set of uDMA channels.
+//!
+//! The parameter \e ulDefPeriphs can be the logical OR of any of the
+//! following macros. If one of the macros below is in the list passed
+//! to this function, then the default peripheral (marked as \b _DEF_)
+//! will be selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_GPIORX
+//! - \b UDMA_DEF_TMR1B_SEC_GPIOTX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectDefault(unsigned long ulDefPeriphs)
+{
+ //
+ // Select the default peripheral for the specified channels.
+ //
+ HWREG(UDMA_CHALT) &= ~ulDefPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA controller channel interrupt status.
+//!
+//! This function is used to get the interrupt status of the uDMA controller.
+//! The returned value is a 32-bit bit mask that indicates which channels are
+//! requesting an interrupt. This function can be used from within an
+//! interrupt handler to determine or confirm which uDMA channel has requested
+//! an interrupt.
+//!
+//! \return Returns a 32-bit mask which indicates requesting uDMA channels.
+//! There is a bit for each channel, and a 1 in a bit indicates that channel
+//! is requesting an interrupt. Multiple bits can be set.
+//
+//*****************************************************************************
+unsigned long
+uDMAIntStatus(void)
+{
+ return(HWREG(UDMA_CHIS));
+}
+
+//*****************************************************************************
+//
+//! Clears uDMA interrupt status.
+//!
+//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel.
+//!
+//! Clears bits in the uDMA interrupt status register according to which bits
+//! are set in \e ulChanMask. There is one bit for each channel. If a a bit
+//! is set in \e ulChanMask, then that corresponding channel's interrupt
+//! status will be cleared (if it was set).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntClear(unsigned long ulChanMask)
+{
+ HWREG(UDMA_CHIS) = ulChanMask;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the uDMA controller.
+//!
+//! \param ulIntChannel identifies which uDMA interrupt is to be registered.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the uDMA controller
+//! generates an interrupt. The \e ulIntChannel parameter should be one of the
+//! following:
+//!
+//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts
+//! from the uDMA software channel (UDMA_CHANNEL_SW)
+//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error
+//! interrupts
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note The interrupt handler for uDMA is for transfer completion when the
+//! channel UDMA_CHANNEL_SW is used, and for error interrupts. The
+//! interrupts for each peripheral channel are handled through the individual
+//! peripheral interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(pfnHandler);
+ ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulIntChannel, pfnHandler);
+
+ //
+ // Enable the memory management fault.
+ //
+ IntEnable(ulIntChannel);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the uDMA controller.
+//!
+//! \param ulIntChannel identifies which uDMA interrupt to unregister.
+//!
+//! This function will disable and clear the handler to be called for the
+//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of
+//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function
+//! uDMAIntRegister().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntUnregister(unsigned long ulIntChannel)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulIntChannel);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulIntChannel);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/udma.h b/bsp/lm3s/Libraries/driverlib/udma.h new file mode 100644 index 0000000000..d175947ee4 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/udma.h @@ -0,0 +1,338 @@ +//*****************************************************************************
+//
+// udma.h - Prototypes and macros for the uDMA controller.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __UDMA_H__
+#define __UDMA_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// A structure that defines an entry in the channel control table. These
+// fields are used by the uDMA controller and normally it is not necessary for
+// software to directly read or write fields in the table.
+//
+//*****************************************************************************
+typedef struct
+{
+ //
+ // The ending source address of the data transfer.
+ //
+ volatile void *pvSrcEndAddr;
+
+ //
+ // The ending destination address of the data transfer.
+ //
+ volatile void *pvDstEndAddr;
+
+ //
+ // The channel control mode.
+ //
+ volatile unsigned long ulControl;
+
+ //
+ // An unused location.
+ //
+ volatile unsigned long ulSpare;
+}
+tDMAControlTable;
+
+//*****************************************************************************
+//
+// Flags that can be passed to uDMAChannelAttributeEnable(),
+// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
+//
+//*****************************************************************************
+#define UDMA_ATTR_USEBURST 0x00000001
+#define UDMA_ATTR_ALTSELECT 0x00000002
+#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
+#define UDMA_ATTR_REQMASK 0x00000008
+#define UDMA_ATTR_ALL 0x0000000F
+
+//*****************************************************************************
+//
+// DMA control modes that can be passed to uDMAModeSet() and returned
+// uDMAModeGet().
+//
+//*****************************************************************************
+#define UDMA_MODE_STOP 0x00000000
+#define UDMA_MODE_BASIC 0x00000001
+#define UDMA_MODE_AUTO 0x00000002
+#define UDMA_MODE_PINGPONG 0x00000003
+#define UDMA_MODE_MEM_SCATTER_GATHER \
+ 0x00000004
+#define UDMA_MODE_PER_SCATTER_GATHER \
+ 0x00000006
+#define UDMA_MODE_ALT_SELECT 0x00000001
+
+//*****************************************************************************
+//
+// Channel configuration values that can be passed to uDMAControlSet().
+//
+//*****************************************************************************
+#define UDMA_DST_INC_8 0x00000000
+#define UDMA_DST_INC_16 0x40000000
+#define UDMA_DST_INC_32 0x80000000
+#define UDMA_DST_INC_NONE 0xc0000000
+#define UDMA_SRC_INC_8 0x00000000
+#define UDMA_SRC_INC_16 0x04000000
+#define UDMA_SRC_INC_32 0x08000000
+#define UDMA_SRC_INC_NONE 0x0c000000
+#define UDMA_SIZE_8 0x00000000
+#define UDMA_SIZE_16 0x11000000
+#define UDMA_SIZE_32 0x22000000
+#define UDMA_ARB_1 0x00000000
+#define UDMA_ARB_2 0x00004000
+#define UDMA_ARB_4 0x00008000
+#define UDMA_ARB_8 0x0000c000
+#define UDMA_ARB_16 0x00010000
+#define UDMA_ARB_32 0x00014000
+#define UDMA_ARB_64 0x00018000
+#define UDMA_ARB_128 0x0001c000
+#define UDMA_ARB_256 0x00020000
+#define UDMA_ARB_512 0x00024000
+#define UDMA_ARB_1024 0x00028000
+#define UDMA_NEXT_USEBURST 0x00000008
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.
+//
+//*****************************************************************************
+#define UDMA_CHANNEL_USBEP1RX 0
+#define UDMA_CHANNEL_USBEP1TX 1
+#define UDMA_CHANNEL_USBEP2RX 2
+#define UDMA_CHANNEL_USBEP2TX 3
+#define UDMA_CHANNEL_USBEP3RX 4
+#define UDMA_CHANNEL_USBEP3TX 5
+#define UDMA_CHANNEL_ETH0RX 6
+#define UDMA_CHANNEL_ETH0TX 7
+#define UDMA_CHANNEL_UART0RX 8
+#define UDMA_CHANNEL_UART0TX 9
+#define UDMA_CHANNEL_SSI0RX 10
+#define UDMA_CHANNEL_SSI0TX 11
+#define UDMA_CHANNEL_ADC0 14
+#define UDMA_CHANNEL_ADC1 15
+#define UDMA_CHANNEL_ADC2 16
+#define UDMA_CHANNEL_ADC3 17
+#define UDMA_CHANNEL_TMR0A 18
+#define UDMA_CHANNEL_TMR0B 19
+#define UDMA_CHANNEL_TMR1A 20
+#define UDMA_CHANNEL_TMR1B 21
+#define UDMA_CHANNEL_UART1RX 22
+#define UDMA_CHANNEL_UART1TX 23
+#define UDMA_CHANNEL_SSI1RX 24
+#define UDMA_CHANNEL_SSI1TX 25
+#define UDMA_CHANNEL_I2S0RX 28
+#define UDMA_CHANNEL_I2S0TX 29
+#define UDMA_CHANNEL_SW 30
+
+//*****************************************************************************
+//
+// Flags to be OR'd with the channel ID to indicate if the primary or alternate
+// control structure should be used.
+//
+//*****************************************************************************
+#define UDMA_PRI_SELECT 0x00000000
+#define UDMA_ALT_SELECT 0x00000020
+
+//*****************************************************************************
+//
+// uDMA interrupt sources, to be passed to uDMAIntRegister() and
+// uDMAIntUnregister().
+//
+//*****************************************************************************
+#define UDMA_INT_SW 62
+#define UDMA_INT_ERR 63
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID. These are for secondary peripheral assignments.
+//
+//*****************************************************************************
+#define UDMA_SEC_CHANNEL_UART2RX_0 \
+ 0
+#define UDMA_SEC_CHANNEL_UART2TX_1 \
+ 1
+#define UDMA_SEC_CHANNEL_TMR3A 2
+#define UDMA_SEC_CHANNEL_TMR3B 3
+#define UDMA_SEC_CHANNEL_TMR2A_4 \
+ 4
+#define UDMA_SEC_CHANNEL_TMR2B_5 \
+ 5
+#define UDMA_SEC_CHANNEL_TMR2A_6 \
+ 6
+#define UDMA_SEC_CHANNEL_TMR2B_7 \
+ 7
+#define UDMA_SEC_CHANNEL_UART1RX \
+ 8
+#define UDMA_SEC_CHANNEL_UART1TX \
+ 9
+#define UDMA_SEC_CHANNEL_SSI1RX 10
+#define UDMA_SEC_CHANNEL_SSI1TX 11
+#define UDMA_SEC_CHANNEL_UART2RX_12 \
+ 12
+#define UDMA_SEC_CHANNEL_UART2TX_13 \
+ 13
+#define UDMA_SEC_CHANNEL_TMR2A_14 \
+ 14
+#define UDMA_SEC_CHANNEL_TMR2B_15 \
+ 15
+#define UDMA_SEC_CHANNEL_TMR1A 18
+#define UDMA_SEC_CHANNEL_TMR1B 19
+#define UDMA_SEC_CHANNEL_EPI0RX 20
+#define UDMA_SEC_CHANNEL_EPI0TX 21
+#define UDMA_SEC_CHANNEL_ADC10 24
+#define UDMA_SEC_CHANNEL_ADC11 25
+#define UDMA_SEC_CHANNEL_ADC12 26
+#define UDMA_SEC_CHANNEL_ADC13 27
+#define UDMA_SEC_CHANNEL_SW 30
+
+//*****************************************************************************
+//
+// uDMA default/secondary peripheral selections, to be passed to
+// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
+//
+//*****************************************************************************
+#define UDMA_DEF_USBEP1RX_SEC_UART2RX \
+ 0x00000001
+#define UDMA_DEF_USBEP1TX_SEC_UART2TX \
+ 0x00000002
+#define UDMA_DEF_USBEP2RX_SEC_TMR3A \
+ 0x00000004
+#define UDMA_DEF_USBEP2TX_SEC_TMR3B \
+ 0x00000008
+#define UDMA_DEF_USBEP3RX_SEC_TMR2A \
+ 0x00000010
+#define UDMA_DEF_USBEP3TX_SEC_TMR2B \
+ 0x00000020
+#define UDMA_DEF_ETH0RX_SEC_TMR2A \
+ 0x00000040
+#define UDMA_DEF_ETH0TX_SEC_TMR2B \
+ 0x00000080
+#define UDMA_DEF_UART0RX_SEC_UART1RX \
+ 0x00000100
+#define UDMA_DEF_UART0TX_SEC_UART1TX \
+ 0x00000200
+#define UDMA_DEF_SSI0RX_SEC_SSI1RX \
+ 0x00000400
+#define UDMA_DEF_SSI0TX_SEC_SSI1TX \
+ 0x00000800
+#define UDMA_DEF_RESERVED_SEC_UART2RX \
+ 0x00001000
+#define UDMA_DEF_RESERVED_SEC_UART2TX \
+ 0x00002000
+#define UDMA_DEF_ADC00_SEC_TMR2A \
+ 0x00004000
+#define UDMA_DEF_ADC01_SEC_TMR2B \
+ 0x00008000
+#define UDMA_DEF_ADC02_SEC_RESERVED \
+ 0x00010000
+#define UDMA_DEF_ADC03_SEC_RESERVED \
+ 0x00020000
+#define UDMA_DEF_TMR0A_SEC_TMR1A \
+ 0x00040000
+#define UDMA_DEF_TMR0B_SEC_TMR1B \
+ 0x00080000
+#define UDMA_DEF_TMR1A_SEC_EPI0RX \
+ 0x00100000
+#define UDMA_DEF_TMR1B_SEC_EPI0TX \
+ 0x00200000
+#define UDMA_DEF_UART1RX_SEC_RESERVED \
+ 0x00400000
+#define UDMA_DEF_UART1TX_SEC_RESERVED \
+ 0x00800000
+#define UDMA_DEF_SSI1RX_SEC_ADC10 \
+ 0x01000000
+#define UDMA_DEF_SSI1TX_SEC_ADC11 \
+ 0x02000000
+#define UDMA_DEF_RESERVED_SEC_ADC12 \
+ 0x04000000
+#define UDMA_DEF_RESERVED_SEC_ADC13 \
+ 0x08000000
+#define UDMA_DEF_I2S0RX_SEC_RESERVED \
+ 0x10000000
+#define UDMA_DEF_I2S0TX_SEC_RESERVED \
+ 0x20000000
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void uDMAEnable(void);
+extern void uDMADisable(void);
+extern unsigned long uDMAErrorStatusGet(void);
+extern void uDMAErrorStatusClear(void);
+extern void uDMAChannelEnable(unsigned long ulChannel);
+extern void uDMAChannelDisable(unsigned long ulChannel);
+extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannel);
+extern void uDMAControlBaseSet(void *pControlTable);
+extern void *uDMAControlBaseGet(void);
+extern void uDMAChannelRequest(unsigned long ulChannel);
+extern void uDMAChannelAttributeEnable(unsigned long ulChannel,
+ unsigned long ulAttr);
+extern void uDMAChannelAttributeDisable(unsigned long ulChannel,
+ unsigned long ulAttr);
+extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannel);
+extern void uDMAChannelControlSet(unsigned long ulChannel,
+ unsigned long ulControl);
+extern void uDMAChannelTransferSet(unsigned long ulChannel,
+ unsigned long ulMode, void *pvSrcAddr,
+ void *pvDstAddr,
+ unsigned long ulTransferSize);
+extern unsigned long uDMAChannelSizeGet(unsigned long ulChannel);
+extern unsigned long uDMAChannelModeGet(unsigned long ulChannel);
+extern void uDMAIntRegister(unsigned long ulIntChannel,
+ void (*pfnHandler)(void));
+extern void uDMAIntUnregister(unsigned long ulIntChannel);
+extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
+extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
+extern unsigned long uDMAIntStatus(void);
+extern void uDMAIntClear(unsigned long ulChanMask);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UDMA_H__
diff --git a/bsp/lm3s/Libraries/driverlib/usb.c b/bsp/lm3s/Libraries/driverlib/usb.c new file mode 100644 index 0000000000..b59be5115f --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/usb.c @@ -0,0 +1,3434 @@ +//*****************************************************************************
+//
+// usb.c - Driver for the USB Interface.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup usb_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_usb.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+#include "driverlib/usb.h"
+
+//*****************************************************************************
+//
+// Amount to shift the RX interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#define USB_INT_RX_SHIFT 8
+
+//*****************************************************************************
+//
+// Amount to shift the status interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#define USB_INT_STATUS_SHIFT 24
+
+//*****************************************************************************
+//
+// Amount to shift the RX endpoint status sources by in the flags used in the
+// calls.
+//
+//*****************************************************************************
+#define USB_RX_EPSTATUS_SHIFT 16
+
+//*****************************************************************************
+//
+// Converts from an endpoint specifier to the offset of the endpoint's
+// control/status registers.
+//
+//*****************************************************************************
+#define EP_OFFSET(Endpoint) (Endpoint - 0x10)
+
+//*****************************************************************************
+//
+// Sets one of the indexed registers.
+//
+// \param ulBase specifies the USB module base address.
+// \param ulEndpoint is the endpoint index to target for this write.
+// \param ulIndexedReg is the indexed register to write to.
+// \param ucValue is the value to write to the register.
+//
+// This function is used to access the indexed registers for each endpoint.
+// The only registers that are indexed are the FIFO configuration registers
+// which are not used after configuration.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulIndexedReg, unsigned long ulValue,
+ unsigned long ulSize)
+{
+ unsigned long ulIndex;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) ||
+ (ulEndpoint == 3));
+ ASSERT((ulSize == 1) || (ulSize == 2));
+
+ //
+ // Save the old index in case it was in use.
+ //
+ ulIndex = HWREGB(ulBase + USB_O_EPIDX);
+
+ //
+ // Set the index.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint;
+
+ //
+ // Determine the size of the register value.
+ //
+ if(ulSize == 1)
+ {
+ //
+ // Set the value.
+ //
+ HWREGB(ulBase + ulIndexedReg) = ulValue;
+ }
+ else
+ {
+ //
+ // Set the value.
+ //
+ HWREGH(ulBase + ulIndexedReg) = ulValue;
+ }
+
+ //
+ // Restore the old index in case it was in use.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulIndex;
+}
+
+//*****************************************************************************
+//
+// Reads one of the indexed registers.
+//
+// \param ulBase specifies the USB module base address.
+// \param ulEndpoint is the endpoint index to target for this write.
+// \param ulIndexedReg is the indexed register to write to.
+//
+// This function is used interally to access the indexed registers for each
+// endpoint. The only registers that are indexed are the FIFO configuration
+// registers which are not used after configuration.
+//
+// \return The value in the register requested.
+//
+//*****************************************************************************
+static unsigned long
+USBIndexRead(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulIndexedReg, unsigned long ulSize)
+{
+ unsigned char ulIndex;
+ unsigned char ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) ||
+ (ulEndpoint == 3));
+ ASSERT((ulSize == 1) || (ulSize == 2));
+
+ //
+ // Save the old index in case it was in use.
+ //
+ ulIndex = HWREGB(ulBase + USB_O_EPIDX);
+
+ //
+ // Set the index.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint;
+
+ //
+ // Determine the size of the register value.
+ //
+ if(ulSize == 1)
+ {
+ //
+ // Get the value.
+ //
+ ulValue = HWREGB(ulBase + ulIndexedReg);
+ }
+ else
+ {
+ //
+ // Get the value.
+ //
+ ulValue = HWREGH(ulBase + ulIndexedReg);
+ }
+
+ //
+ // Restore the old index in case it was in use.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulIndex;
+
+ //
+ // Return the register's value.
+ //
+ return(ulValue);
+}
+
+//*****************************************************************************
+//
+//! Puts the USB bus in a suspended state.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! When used in host mode, this function will put the USB bus in the suspended
+//! state.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostSuspend(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Send the suspend signaling to the USB bus.
+ //
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SUSPEND;
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus reset condition.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies whether to start or stop signaling reset on the USB
+//! bus.
+//!
+//! When this function is called with the \e bStart parameter set to \b true,
+//! this function will cause the start of a reset condition on the USB bus.
+//! The caller should then delay at least 20ms before calling this function
+//! again with the \e bStart parameter set to \b false.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostReset(unsigned long ulBase, tBoolean bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Send a reset signal to the bus.
+ //
+ if(bStart)
+ {
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESET;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESET;
+ }
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus resume condition.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies if the USB controller is entering or leaving the
+//! resume signaling state.
+//!
+//! When in device mode this function will bring the USB controller out of the
+//! suspend state. This call should first be made with the \e bStart parameter
+//! set to \b true to start resume signaling. The device application should
+//! then delay at least 10ms but not more than 15ms before calling this
+//! function with the \e bStart parameter set to \b false.
+//!
+//! When in host mode this function will signal devices to leave the suspend
+//! state. This call should first be made with the \e bStart parameter set to
+//! \b true to start resume signaling. The host application should then delay
+//! at least 20ms before calling this function with the \e bStart parameter set
+//! to \b false. This will cause the controller to complete the resume
+//! signaling on the USB bus.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostResume(unsigned long ulBase, tBoolean bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Send a resume signal to the bus.
+ //
+ if(bStart)
+ {
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESUME;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESUME;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the current speed of the USB device connected.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will return the current speed of the USB bus.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return Returns either \b USB_LOW_SPEED, \b USB_FULL_SPEED, or
+//! \b USB_UNDEF_SPEED.
+//
+//*****************************************************************************
+unsigned long
+USBHostSpeedGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // If the Full Speed device bit is set, then this is a full speed device.
+ //
+ if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_FSDEV)
+ {
+ return(USB_FULL_SPEED);
+ }
+
+ //
+ // If the Low Speed device bit is set, then this is a low speed device.
+ //
+ if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_LSDEV)
+ {
+ return(USB_LOW_SPEED);
+ }
+
+ //
+ // The device speed is not known.
+ //
+ return(USB_UNDEF_SPEED);
+}
+
+//*****************************************************************************
+//
+//! Returns the status of the USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read the source of the interrupt for the USB controller.
+//! There are three groups of interrupt sources, IN Endpoints, OUT Endpoints,
+//! and general status changes. This call will return the current status for
+//! all of these interrupts. The bit values returned should be compared
+//! against the \b USB_HOST_IN, \b USB_HOST_OUT, \b USB_HOST_EP0,
+//! \b USB_DEV_IN, \b USB_DEV_OUT, and \b USB_DEV_EP0 values.
+//!
+//! \note This call will clear the source of all of the general status
+//! interrupts.
+//!
+//! \return Returns the status of the sources for the USB controller's
+//! interrupt.
+//
+//*****************************************************************************
+unsigned long
+USBIntStatus(unsigned long ulBase)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Get the transmit interrupt status.
+ //
+ ulStatus = (HWREGH(ulBase + USB_O_TXIS));
+
+ //
+ // Get the receive interrupt status, these bits go into the second byte of
+ // the returned value.
+ //
+ ulStatus |= (HWREGH(ulBase + USB_O_RXIS) << USB_INT_RX_SHIFT);
+
+ //
+ // Get the general interrupt status, these bits go into the upper 8 bits
+ // of the returned value.
+ //
+ ulStatus |= (HWREGB(ulBase + USB_O_IS) << USB_INT_STATUS_SHIFT);
+
+ //
+ // Add the power fault status.
+ //
+ if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF)
+ {
+ //
+ // Indicate a power fault was detected.
+ //
+ ulStatus |= USB_INT_POWER_FAULT;
+
+ //
+ // Clear the power fault interrupt.
+ //
+ HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF;
+ }
+
+ if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+ {
+ //
+ // Indicate a id detection was detected.
+ //
+ ulStatus |= USB_INT_MODE_DETECT;
+
+ //
+ // Clear the id detection interrupt.
+ //
+ HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+ }
+
+ //
+ // Return the combined interrupt status.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Disables the sources for USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which interrupts to disable.
+//!
+//! This function will disable the USB controller from generating the
+//! interrupts indicated by the \e ulFlags parameter. There are three groups
+//! of interrupt sources, IN Endpoints, OUT Endpoints, and general status
+//! changes, specified by \b USB_INT_HOST_IN, \b USB_INT_HOST_OUT,
+//! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS. If
+//! \b USB_INT_ALL is specified then all interrupts will be disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisable(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & ~(USB_INT_ALL)) == 0);
+
+ //
+ // If any transmit interrupts were disabled then write the transmit
+ // interrupt settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0))
+ {
+ HWREGH(ulBase + USB_O_TXIE) &=
+ ~(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0));
+ }
+
+ //
+ // If any receive interrupts were disabled then write the receive interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT))
+ {
+ HWREGH(ulBase + USB_O_RXIE) &=
+ ~((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >>
+ USB_INT_RX_SHIFT);
+ }
+
+ //
+ // If any general interrupts were disabled then write the general interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & USB_INT_STATUS)
+ {
+ HWREGB(ulBase + USB_O_IE) &=
+ ~((ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT);
+ }
+
+ //
+ // Disable the power fault interrupt.
+ //
+ if(ulFlags & USB_INT_POWER_FAULT)
+ {
+ HWREG(ulBase + USB_O_EPCIM) = 0;
+ }
+
+ //
+ // Disable the ID pin detect interrupt.
+ //
+ if(ulFlags & USB_INT_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the sources for USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which interrupts to enable.
+//!
+//! This function will enable the USB controller's ability to generate the
+//! interrupts indicated by the \e ulFlags parameter. There are three
+//! groups of interrupt sources, IN Endpoints, OUT Endpoints, and
+//! general status changes, specified by \b USB_INT_HOST_IN,
+//! \b USB_INT_HOST_OUT, \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and
+//! \b USB_STATUS. If \b USB_INT_ALL is specified then all interrupts will be
+//! enabled.
+//!
+//! \note A call must be made to enable the interrupt in the main interrupt
+//! controller to receive interrupts. The USBIntRegister() API performs this
+//! controller level interrupt enable. However if static interrupt handlers
+//! are used then then a call to IntEnable() must be made in order to allow any
+//! USB interrupts to occur.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnable(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & (~USB_INT_ALL)) == 0);
+
+ //
+ // If any transmit interrupts were enabled then write the transmit
+ // interrupt settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0))
+ {
+ HWREGH(ulBase + USB_O_TXIE) |=
+ ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0);
+ }
+
+ //
+ // If any receive interrupts were enabled then write the receive interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT))
+ {
+ HWREGH(ulBase + USB_O_RXIE) |=
+ ((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >>
+ USB_INT_RX_SHIFT);
+ }
+
+ //
+ // If any general interrupts were enabled then write the general interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & USB_INT_STATUS)
+ {
+ HWREGB(ulBase + USB_O_IE) |=
+ (ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT;
+ }
+
+ //
+ // Enable the power fault interrupt.
+ //
+ if(ulFlags & USB_INT_POWER_FAULT)
+ {
+ HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF;
+ }
+
+ //
+ // Enable the ID pin detect interrupt.
+ //
+ if(ulFlags & USB_INT_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param pfnHandler is a pointer to the function to be called when a USB
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when a USB interrupt occurs. This will
+//! also enable the global USB interrupt in the interrupt controller. The
+//! specific desired USB interrupts must be enabled via a separate call to
+//! USBIntEnable(). It is the interrupt handler's responsibility to clear the
+//! interrupt sources via a call to USBIntStatus().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_USB0, pfnHandler);
+
+ //
+ // Enable the USB interrupt.
+ //
+ IntEnable(INT_USB0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function unregister the interrupt handler. This function will also
+//! disable the USB interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering or
+//! unregistering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_USB0);
+
+ //
+ // Disable the CAN interrupt.
+ //
+ IntDisable(INT_USB0);
+}
+
+//*****************************************************************************
+//
+//! Returns the current status of an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will return the status of a given endpoint. If any of these
+//! status bits need to be cleared, then these these values must be cleared by
+//! calling the USBDevEndpointStatusClear() or USBHostEndpointStatusClear()
+//! functions.
+//!
+//! The following are the status flags for host mode:
+//!
+//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint.
+//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request.
+//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint.
+//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN
+//! endpoint in Isochronous mode.
+//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than
+//! the specified timeout period.
+//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN
+//! endpoint.
+//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full.
+//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint.
+//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than
+//! the specified timeout period.
+//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT
+//! request.
+//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint.
+//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this
+//! OUT endpoint.
+//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty.
+//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not
+//! completed.
+//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the
+//! specified timeout period.
+//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on
+//! endpoint zero.
+//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an
+//! IN transaction.
+//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN
+//! transaction.
+//!
+//! The following are the status flags for device mode:
+//!
+//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint.
+//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT
+//! endpoint.
+//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO.
+//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full.
+//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT
+//! endpoint's FIFO.
+//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come.
+//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint.
+//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no
+//! data was ready.
+//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty.
+//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not
+//! completed.
+//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End
+//! condition was sent.
+//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero.
+//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not
+//! completed.
+//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint
+//! zero's OUT FIFO.
+//!
+//! \return The current status flags for the endpoint depending on mode.
+//
+//*****************************************************************************
+unsigned long
+USBEndpointStatus(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the TX portion of the endpoint status.
+ //
+ ulStatus = HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1);
+
+ //
+ // Get the RX portion of the endpoint status.
+ //
+ ulStatus |= ((HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1)) <<
+ USB_RX_EPSTATUS_SHIFT);
+
+ //
+ // Return the endpoint status.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags are the status bits that will be cleared.
+//!
+//! This function will clear the status of any bits that are passed in the
+//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned
+//! from the USBEndpointStatus() call.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Clear the specified flags for the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) &= ~ulFlags;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= ~ulFlags;
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(ulFlags >> USB_RX_EPSTATUS_SHIFT);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags are the status bits that will be cleared.
+//!
+//! This function will clear the status of any bits that are passed in the
+//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned
+//! from the USBEndpointStatus() call.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // If this is endpoint 0 then the bits have different meaning and map into
+ // the TX memory location.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Set the Serviced RxPktRdy bit to clear the RxPktRdy.
+ //
+ if(ulFlags & USB_DEV_EP0_OUT_PKTRDY)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_RXRDYC;
+ }
+
+ //
+ // Set the serviced Setup End bit to clear the SetupEnd status.
+ //
+ if(ulFlags & USB_DEV_EP0_SETUP_END)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_SETENDC;
+ }
+
+ //
+ // Clear the Sent Stall status flag.
+ //
+ if(ulFlags & USB_DEV_EP0_SENT_STALL)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL);
+ }
+ }
+ else
+ {
+ //
+ // Clear out any TX flags that were passed in. Only
+ // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN should be cleared.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(ulFlags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));
+
+ //
+ // Clear out valid RX flags that were passed in. Only
+ // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN
+ // should be cleared.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~((ulFlags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR |
+ USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the value data toggle on an endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to reset the data toggle.
+//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1.
+//! \param ulFlags specifies whether to set the IN or OUT endpoint.
+//!
+//! This function is used to force the state of the data toggle in host mode.
+//! If the value passed in the \e bDataToggle parameter is \b false, then the
+//! data toggle will be set to the DATA0 state, and if it is \b true it will be
+//! set to the DATA1 state. The \e ulFlags parameter can be \b USB_EP_HOST_IN
+//! or \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The
+//! \e ulFlags parameter is ignored for endpoint zero.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint,
+ tBoolean bDataToggle, unsigned long ulFlags)
+{
+ unsigned long ulDataToggle;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // The data toggle defaults to DATA0.
+ //
+ ulDataToggle = 0;
+
+ //
+ // See if the data toggle should be set to DATA1.
+ //
+ if(bDataToggle)
+ {
+ //
+ // Select the data toggle bit based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulDataToggle = USB_CSRH0_DT;
+ }
+ else if(ulFlags == USB_EP_HOST_IN)
+ {
+ ulDataToggle = USB_RXCSRH1_DT;
+ }
+ else
+ {
+ ulDataToggle = USB_TXCSRH1_DT;
+ }
+ }
+
+ //
+ // Set the data toggle based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Set the write enable and the bit value for endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRH0) =
+ ((HWREGB(ulBase + USB_O_CSRH0) &
+ ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
+ (ulDataToggle | USB_CSRH0_DTWE));
+ }
+ else if(ulFlags == USB_EP_HOST_IN)
+ {
+ //
+ // Set the Write enable and the bit value for an IN endpoint.
+ //
+ HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) =
+ ((HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) &
+ ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
+ (ulDataToggle | USB_RXCSRH1_DTWE));
+ }
+ else
+ {
+ //
+ // Set the Write enable and the bit value for an OUT endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) =
+ ((HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) &
+ ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
+ (ulDataToggle | USB_TXCSRH1_DTWE));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the Data toggle on an endpoint to zero.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to reset the data toggle.
+//! \param ulFlags specifies whether to access the IN or OUT endpoint.
+//!
+//! This function will cause the controller to clear the data toggle for an
+//! endpoint. This call is not valid for endpoint zero and can be made with
+//! host or device controllers.
+//!
+//! The \e ulFlags parameter should be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive data toggle should be cleared.
+ //
+ if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Stalls the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to stall.
+//! \param ulFlags specifies whether to stall the IN or OUT endpoint.
+//!
+//! This function will cause to endpoint number passed in to go into a stall
+//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be issued on the IN portion of this endpoint. If the \e ulFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine how to stall this endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Perform a stall on endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) |=
+ (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
+ }
+ else if(ulFlags == USB_EP_DEV_IN)
+ {
+ //
+ // Perform a stall on an IN endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_STALL;
+ }
+ else
+ {
+ //
+ // Perform a stall on an OUT endpoint.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_RXCSRL1_STALL;
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the stall condition on the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint to remove the stall condition.
+//! \param ulFlags specifies whether to remove the stall condition from the IN
+//! or the OUT portion of this endpoint.
+//!
+//! This function will cause the endpoint number passed in to exit the stall
+//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be cleared on the IN portion of this endpoint. If the \e ulFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+ ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)
+
+ //
+ // Determine how to clear the stall on this endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Clear the stall on endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_STALLED;
+ }
+ else if(ulFlags == USB_EP_DEV_IN)
+ {
+ //
+ // Clear the stall on an IN endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
+
+ //
+ // Reset the data toggle.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ //
+ // Clear the stall on an OUT endpoint.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
+
+ //
+ // Reset the data toggle.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Connects the USB controller to the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft connect feature of the USB controller to
+//! be enabled. Call USBDisconnect() to remove the USB device from the bus.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevConnect(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable connection to the USB bus.
+ //
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SOFTCONN;
+}
+
+//*****************************************************************************
+//
+//! Removes the USB controller from the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft connect feature of the USB controller to
+//! remove the device from the USB bus. A call to USBDevConnect() is needed to
+//! reconnect to the bus.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevDisconnect(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Disable connection to the USB bus.
+ //
+ HWREGB(ulBase + USB_O_POWER) &= (~USB_POWER_SOFTCONN);
+}
+
+//*****************************************************************************
+//
+//! Sets the address in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulAddress is the address to use for a device.
+//!
+//! This function will set the device address on the USB bus. This address was
+//! likely received via a SET ADDRESS command from the host controller.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Set the function address in the correct location.
+ //
+ HWREGB(ulBase + USB_O_FADDR) = (unsigned char)ulAddress;
+}
+
+//*****************************************************************************
+//
+//! Returns the current device address in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will return the current device address. This address was set
+//! by a call to USBDevAddrSet().
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return The current device address.
+//
+//*****************************************************************************
+unsigned long
+USBDevAddrGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Return the function address.
+ //
+ return(HWREGB(ulBase + USB_O_FADDR));
+}
+
+//*****************************************************************************
+//
+//! Sets the base configuration for a host endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulMaxPayload is the maximum payload for this endpoint.
+//! \param ulNAKPollInterval is the either the NAK timeout limit or the polling
+//! interval depending on the type of endpoint.
+//! \param ulTargetEndpoint is the endpoint that the host endpoint is
+//! targeting.
+//! \param ulFlags are used to configure other endpoint settings.
+//!
+//! This function will set the basic configuration for the transmit or receive
+//! portion of an endpoint in host mode. The \e ulFlags parameter determines
+//! some of the configuration while the other parameters provide the rest. The
+//! \e ulFlags parameter determines whether this is an IN endpoint
+//! (USB_EP_HOST_IN or USB_EP_DEV_IN) or an OUT endpoint (USB_EP_HOST_OUT or
+//! USB_EP_DEV_OUT), whether this is a Full speed endpoint (USB_EP_SPEED_FULL)
+//! or a Low speed endpoint (USB_EP_SPEED_LOW).
+//!
+//! The \b USB_EP_MODE_ flags control the type of the endpoint.
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \e ulNAKPollInterval parameter has different meanings based on the
+//! \b USB_EP_MODE value and whether or not this call is being made for
+//! endpoint zero or another endpoint. For endpoint zero or any Bulk
+//! endpoints, this value always indicates the number of frames to allow a
+//! device to NAK before considering it a timeout. If this endpoint is an
+//! isochronous or interrupt endpoint, this value is the polling interval for
+//! this endpoint.
+//!
+//! For interrupt endpoints the polling interval is simply the number of
+//! frames between polling an interrupt endpoint. For isochronous endpoints
+//! this value represents a polling interval of 2 ^ (\e ulNAKPollInterval - 1)
+//! frames. When used as a NAK timeout, the \e ulNAKPollInterval value
+//! specifies 2 ^ (\e ulNAKPollInterval - 1) frames before issuing a time out.
+//! There are two special time out values that can be specified when setting
+//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT which is the
+//! maximum value that can be passed in this variable. The other is
+//! \b DISABLE_NAK_LIMIT which indicates that there should be no limit on the
+//! number of NAKs.
+//!
+//! The \b USB_EP_DMA_MODE_ flags enables the type of DMA used to access the
+//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used. See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit
+//! is specified to cause the transmission of data on the USB bus to start
+//! as soon as the number of bytes specified by \e ulMaxPayload have been
+//! written into the OUT FIFO for this endpoint.
+//!
+//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST
+//! bit can be specified to trigger the request for more data once the FIFO has
+//! been drained enough to fit \e ulMaxPayload bytes. The \b USB_EP_AUTO_CLEAR
+//! bit can be used to clear the data packet ready flag automatically once the
+//! data has been read from the FIFO. If this is not used, this flag must be
+//! manually cleared via a call to USBDevEndpointStatusClear() or
+//! USBHostEndpointStatusClear().
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulMaxPayload,
+ unsigned long ulNAKPollInterval,
+ unsigned long ulTargetEndpoint, unsigned long ulFlags)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+ ASSERT(ulNAKPollInterval <= MAX_NAK_LIMIT);
+
+ //
+ // Endpoint zero is configured differently than the other endpoints, so see
+ // if this is endpoint zero.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Set the NAK timeout.
+ //
+ HWREGB(ulBase + USB_O_NAKLMT) = ulNAKPollInterval;
+
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) =
+ ((ulFlags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL :
+ USB_TYPE0_SPEED_LOW);
+ }
+ else
+ {
+ //
+ // Start with the target endpoint.
+ //
+ ulRegister = ulTargetEndpoint;
+
+ //
+ // Set the speed for the device using this endpoint.
+ //
+ if(ulFlags & USB_EP_SPEED_FULL)
+ {
+ ulRegister |= USB_TXTYPE1_SPEED_FULL;
+ }
+ else
+ {
+ ulRegister |= USB_TXTYPE1_SPEED_LOW;
+ }
+
+ //
+ // Set the protocol for the device using this endpoint.
+ //
+ switch(ulFlags & USB_EP_MODE_MASK)
+ {
+ //
+ // The bulk protocol is being used.
+ //
+ case USB_EP_MODE_BULK:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_BULK;
+ break;
+ }
+
+ //
+ // The isochronous protocol is being used.
+ //
+ case USB_EP_MODE_ISOC:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_ISOC;
+ break;
+ }
+
+ //
+ // The interrupt protocol is being used.
+ //
+ case USB_EP_MODE_INT:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_INT;
+ break;
+ }
+
+ //
+ // The control protocol is being used.
+ //
+ case USB_EP_MODE_CTRL:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_CTRL;
+ break;
+ }
+ }
+
+ //
+ // See if the transmit or receive endpoint is being configured.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXTYPE1) =
+ ulRegister;
+
+ //
+ // Set the NAK timeout or polling interval.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXINTERVAL1) =
+ ulNAKPollInterval;
+
+ //
+ // Set the Maximum Payload per transaction.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) =
+ ulMaxPayload;
+
+ //
+ // Set the transmit control value to zero.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto setting of TxPktRdy when max packet size has been
+ // loaded into the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_SET)
+ {
+ ulRegister |= USB_TXCSRH1_AUTOSET;
+ }
+
+ //
+ // Configure the DMA Mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // Write out the transmit control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) =
+ (unsigned char)ulRegister;
+ }
+ else
+ {
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXTYPE1) =
+ ulRegister;
+
+ //
+ // Set the NAK timeout or polling interval.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXINTERVAL1) =
+ ulNAKPollInterval;
+
+ //
+ // Set the receive control value to zero.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto clearing of RxPktRdy when packet of size max packet
+ // has been unloaded from the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_CLEAR)
+ {
+ ulRegister |= USB_RXCSRH1_AUTOCL;
+ }
+
+ //
+ // Configure the DMA Mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN;
+ }
+
+ //
+ // Write out the receive control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) =
+ (unsigned char)ulRegister;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulMaxPacketSize is the maximum packet size for this endpoint.
+//! \param ulFlags are used to configure other endpoint settings.
+//!
+//! This function will set the basic configuration for an endpoint in device
+//! mode. Endpoint zero does not have a dynamic configuration, so this
+//! function should not be called for endpoint zero. The \e ulFlags parameter
+//! determines some of the configuration while the other parameters provide the
+//! rest.
+//!
+//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint.
+//!
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \b USB_EP_DMA_MODE_ flags determines the type of DMA access to the
+//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used. See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be
+//! specified to cause the automatic transmission of data on the USB bus as
+//! soon as \e ulMaxPacketSize bytes of data are written into the FIFO for
+//! this endpoint. This is commonly used with DMA as no interaction is
+//! required to start the transmission of data.
+//!
+//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is
+//! specified to trigger the request for more data once the FIFO has been
+//! drained enough to receive \e ulMaxPacketSize more bytes of data. Also for
+//! OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the data
+//! packet ready flag automatically once the data has been read from the FIFO.
+//! If this is not used, this flag must be manually cleared via a call to
+//! USBDevEndpointStatusClear(). Both of these settings can be used to remove
+//! the need for extra calls when using the controller in DMA mode.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulMaxPacketSize, unsigned long ulFlags)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine if a transmit or receive endpoint is being configured.
+ //
+ if(ulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Set the maximum packet size.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) =
+ ulMaxPacketSize;
+
+ //
+ // The transmit control value is zero unless options are enabled.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto setting of TxPktRdy when max packet size has been loaded
+ // into the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_SET)
+ {
+ ulRegister |= USB_TXCSRH1_AUTOSET;
+ }
+
+ //
+ // Configure the DMA mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // Enable isochronous mode if requested.
+ //
+ if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+ {
+ ulRegister |= USB_TXCSRH1_ISO;
+ }
+
+ //
+ // Write the transmit control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) =
+ (unsigned char)ulRegister;
+
+ //
+ // Reset the Data toggle to zero.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1) =
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ //
+ // Set the MaxPacketSize.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXMAXP1) =
+ ulMaxPacketSize;
+
+ //
+ // The receive control value is zero unless options are enabled.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto clearing of RxPktRdy when packet of size max packet
+ // has been unloaded from the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_CLEAR)
+ {
+ ulRegister = USB_RXCSRH1_AUTOCL;
+ }
+
+ //
+ // Configure the DMA mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN;
+ }
+
+ //
+ // Enable isochronous mode if requested.
+ //
+ if(USB_EP_MODE_ISOC & (ulFlags & USB_EP_MODE_MASK))
+ {
+ ulRegister |= USB_RXCSRH1_ISO;
+ }
+
+ //
+ // Write the receive control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) =
+ (unsigned char)ulRegister;
+
+ //
+ // Reset the Data toggle to zero.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1) =
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pulMaxPacketSize is a pointer which will be written with the
+//! maximum packet size for this endpoint.
+//! \param pulFlags is a pointer which will be written with the current
+//! endpoint settings. On entry to the function, this pointer must contain
+//! either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or
+//! OUT endpoint is to be queried.
+//!
+//! This function will return the basic configuration for an endpoint in device
+//! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are
+//! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to
+//! USBDevEndpointConfig for this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long *pulMaxPacketSize,
+ unsigned long *pulFlags)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT(pulMaxPacketSize && pulFlags);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine if a transmit or receive endpoint is being queried.
+ //
+ if(*pulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Clear the flags other than the direction bit.
+ //
+ *pulFlags = USB_EP_DEV_IN;
+
+ //
+ // Get the maximum packet size.
+ //
+ *pulMaxPacketSize = (unsigned long)HWREGB(ulBase +
+ EP_OFFSET(ulEndpoint) +
+ USB_O_TXMAXP1);
+
+ //
+ // Get the current transmit control register value.
+ //
+ ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) +
+ USB_O_TXCSRH1);
+
+ //
+ // Are we allowing auto setting of TxPktRdy when max packet size has
+ // been loaded into the FIFO?
+ //
+ if(ulRegister & USB_TXCSRH1_AUTOSET)
+ {
+ *pulFlags |= USB_EP_AUTO_SET;
+ }
+
+ //
+ // Get the DMA mode.
+ //
+ if(ulRegister & USB_TXCSRH1_DMAEN)
+ {
+ if(ulRegister & USB_TXCSRH1_DMAMOD)
+ {
+ *pulFlags |= USB_EP_DMA_MODE_1;
+ }
+ else
+ {
+ *pulFlags |= USB_EP_DMA_MODE_0;
+ }
+ }
+
+ //
+ // Are we in isochronous mode?
+ //
+ if(ulRegister & USB_TXCSRH1_ISO)
+ {
+ *pulFlags |= USB_EP_MODE_ISOC;
+ }
+ else
+ {
+ //
+ // The hardware doesn't differentiate between bulk, interrupt
+ // and control mode for the endpoint so we just set something
+ // that isn't isochronous. This ensures that anyone modifying
+ // the returned flags in preparation for a call to
+ // USBDevEndpointConfig will not see an unexpected mode change.
+ // If they decode the returned mode, however, they may be in for
+ // a surprise.
+ //
+ *pulFlags |= USB_EP_MODE_BULK;
+ }
+ }
+ else
+ {
+ //
+ // Clear the flags other than the direction bit.
+ //
+ *pulFlags = USB_EP_DEV_OUT;
+
+ //
+ // Get the MaxPacketSize.
+ //
+ *pulMaxPacketSize = (unsigned long)HWREGB(ulBase +
+ EP_OFFSET(ulEndpoint) +
+ USB_O_RXMAXP1);
+
+ //
+ // Get the current receive control register value.
+ //
+ ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) +
+ USB_O_RXCSRH1);
+
+ //
+ // Are we allowing auto clearing of RxPktRdy when packet of size max
+ // packet has been unloaded from the FIFO?
+ //
+ if(ulRegister & USB_RXCSRH1_AUTOCL)
+ {
+ *pulFlags |= USB_EP_AUTO_CLEAR;
+ }
+
+ //
+ // Get the DMA mode.
+ //
+ if(ulRegister & USB_RXCSRH1_DMAEN)
+ {
+ if(ulRegister & USB_RXCSRH1_DMAMOD)
+ {
+ *pulFlags |= USB_EP_DMA_MODE_1;
+ }
+ else
+ {
+ *pulFlags |= USB_EP_DMA_MODE_0;
+ }
+ }
+
+ //
+ // Are we in isochronous mode?
+ //
+ if(ulRegister & USB_RXCSRH1_ISO)
+ {
+ *pulFlags |= USB_EP_MODE_ISOC;
+ }
+ else
+ {
+ //
+ // The hardware doesn't differentiate between bulk, interrupt
+ // and control mode for the endpoint so we just set something
+ // that isn't isochronous. This ensures that anyone modifying
+ // the returned flags in preparation for a call to
+ // USBDevEndpointConfig will not see an unexpected mode change.
+ // If they decode the returned mode, however, they may be in for
+ // a surprise.
+ //
+ *pulFlags |= USB_EP_MODE_BULK;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFIFOAddress is the starting address for the FIFO.
+//! \param ulFIFOSize is the size of the FIFO in bytes.
+//! \param ulFlags specifies what information to set in the FIFO configuration.
+//!
+//! This function will set the starting FIFO RAM address and size of the FIFO
+//! for a given endpoint. Endpoint zero does not have a dynamically
+//! configurable FIFO so this function should not be called for endpoint zero.
+//! The \e ulFIFOSize parameter should be one of the values in the
+//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering
+//! it should use the values with the \b _DB at the end of the value. For
+//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16
+//! byte double buffered FIFO. If a double buffered FIFO is used, then the
+//! actual size of the FIFO will be twice the size indicated by the
+//! \e ulFIFOSize parameter. This means that the \b USB_FIFO_SZ_16_DB value
+//! will use 32 bytes of the USB controller's FIFO memory.
+//!
+//! The \e ulFIFOAddress value should be a multiple of 8 bytes and directly
+//! indicates the starting address in the USB controller's FIFO RAM. For
+//! example, a value of 64 indicates that the FIFO should start 64 bytes into
+//! the USB controller's FIFO memory. The \e ulFlags value specifies whether
+//! the endpoint's OUT or IN FIFO should be configured. If in host mode, use
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use
+//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFIFOAddress, unsigned long ulFIFOSize,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive FIFO is being configured.
+ //
+ if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Set the transmit FIFO location and size for this endpoint.
+ //
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOSZ, ulFIFOSize, 1);
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOADD,
+ ulFIFOAddress >> 3, 2);
+ }
+ else
+ {
+ //
+ // Set the receive FIFO location and size for this endpoint.
+ //
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOSZ, ulFIFOSize, 1);
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOADD,
+ ulFIFOAddress >> 3, 2);
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the FIFO configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pulFIFOAddress is the starting address for the FIFO.
+//! \param pulFIFOSize is the size of the FIFO in bytes.
+//! \param ulFlags specifies what information to retrieve from the FIFO
+//! configuration.
+//!
+//! This function will return the starting address and size of the FIFO for a
+//! given endpoint. Endpoint zero does not have a dynamically configurable
+//! FIFO so this function should not be called for endpoint zero. The
+//! \e ulFlags parameter specifies whether the endpoint's OUT or IN FIFO should
+//! be read. If in host mode, the \e ulFlags parameter should be
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode the
+//! \e ulFlags parameter should be either \b USB_EP_DEV_OUT or
+//! \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long *pulFIFOAddress, unsigned long *pulFIFOSize,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive FIFO is being configured.
+ //
+ if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Get the transmit FIFO location and size for this endpoint.
+ //
+ *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_TXFIFOADD,
+ 2)) << 3;
+ *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_TXFIFOSZ, 1);
+
+ }
+ else
+ {
+ //
+ // Get the receive FIFO location and size for this endpoint.
+ //
+ *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_RXFIFOADD,
+ 2)) << 3;
+ *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_RXFIFOSZ, 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable DMA on a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies which direction and what mode to use when enabling
+//! DMA.
+//!
+//! This function will enable DMA on a given endpoint and set the mode according
+//! to the values in the \e ulFlags parameter. The \e ulFlags parameter should
+//! have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // See if the transmit DMA is being enabled.
+ //
+ if(ulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Enable DMA on this end point.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |=
+ USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // See if the receive DMA is being enabled.
+ //
+ if(ulFlags & USB_EP_DEV_OUT)
+ {
+ //
+ // Enable DMA on this end point.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |=
+ USB_RXCSRH1_DMAEN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disable DMA on a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies which direction to disable.
+//!
+//! This function will disable DMA on a given end point to allow non-DMA
+//! USB transactions to generate interrupts normally. The ulFlags should be
+//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT all other bits are ignored.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // If this was a reques to disable DMA on the IN portion of the end point
+ // then handle it.
+ //
+ if(ulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Just disable DMA leave the mode setting.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) &=
+ ~USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // If this was a request to disable DMA on the OUT portion of the end point
+ // then handle it.
+ //
+ if(ulFlags & USB_EP_DEV_OUT)
+ {
+ //
+ // Just disable DMA leave the mode setting.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) &=
+ ~USB_RXCSRH1_DMAEN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Determine the number of bytes of data available in a given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will return the number of bytes of data currently available
+//! in the FIFO for the given receive (OUT) endpoint. It may be used prior to
+//! calling USBEndpointDataGet() to determine the size of buffer required to
+//! hold the newly-received packet.
+//!
+//! \return This call will return the number of bytes available in a given
+//! endpoint FIFO.
+//
+//*****************************************************************************
+unsigned long
+USBEndpointDataAvail(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the address of the receive status register to use, based on the
+ // endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulRegister = USB_O_CSRL0;
+ }
+ else
+ {
+ ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+ }
+
+ //
+ // Is there a packet ready in the FIFO?
+ //
+ if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Return the byte count in the FIFO.
+ //
+ return(HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint));
+}
+
+//*****************************************************************************
+//
+//! Retrieves data from the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used to return the data from
+//! the FIFO.
+//! \param pulSize is initially the size of the buffer passed into this call
+//! via the \e pucData parameter. It will be set to the amount of data
+//! returned in the buffer.
+//!
+//! This function will return the data from the FIFO for the given endpoint.
+//! The \e pulSize parameter should indicate the size of the buffer passed in
+//! the \e pulData parameter. The data in the \e pulSize parameter will be
+//! changed to match the amount of data returned in the \e pucData parameter.
+//! If a zero byte packet was received this call will not return a error but
+//! will instead just return a zero in the \e pulSize parameter. The only
+//! error case occurs when there is no data packet available.
+//!
+//! \return This call will return 0, or -1 if no packet was received.
+//
+//*****************************************************************************
+long
+USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long *pulSize)
+{
+ unsigned long ulRegister, ulByteCount, ulFIFO;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the address of the receive status register to use, based on the
+ // endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulRegister = USB_O_CSRL0;
+ }
+ else
+ {
+ ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+ }
+
+ //
+ // Don't allow reading of data if the RxPktRdy bit is not set.
+ //
+ if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0)
+ {
+ //
+ // Can't read the data because none is available.
+ //
+ *pulSize = 0;
+
+ //
+ // Return a failure since there is no data to read.
+ //
+ return(-1);
+ }
+
+ //
+ // Get the byte count in the FIFO.
+ //
+ ulByteCount = HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint);
+
+ //
+ // Determine how many bytes we will actually copy.
+ //
+ ulByteCount = (ulByteCount < *pulSize) ? ulByteCount : *pulSize;
+
+ //
+ // Return the number of bytes we are going to read.
+ //
+ *pulSize = ulByteCount;
+
+ //
+ // Calculate the FIFO address.
+ //
+ ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2);
+
+ //
+ // Read the data out of the FIFO.
+ //
+ for(; ulByteCount > 0; ulByteCount--)
+ {
+ //
+ // Read a byte at a time from the FIFO.
+ //
+ *pucData++ = HWREGB(ulFIFO);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in device
+//! mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param bIsLastPacket indicates if this is the last packet.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! The \e bIsLastPacket parameter is set to a \b true value if this is the
+//! last in a series of data packets on endpoint zero. The \e bIsLastPacket
+//! parameter is not used for endpoints other than endpoint zero. This call
+//! can be used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint,
+ tBoolean bIsLastPacket)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine which endpoint is being acked.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Clear RxPktRdy, and optionally DataEnd, on endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) =
+ USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0);
+ }
+ else
+ {
+ //
+ // Clear RxPktRdy on all other endpoints.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_RXCSRL1_RXRDY);
+ }
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in host
+//! mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! This call is used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Clear RxPktRdy.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_RXCSRL1_RXRDY);
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts data into the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used as the source for the
+//! data to put into the FIFO.
+//! \param ulSize is the amount of data to put into the FIFO.
+//!
+//! This function will put the data from the \e pucData parameter into the FIFO
+//! for this endpoint. If a packet is already pending for transmission then
+//! this call will not put any of the data into the FIFO and will return -1.
+//! Care should be taken to not write more data than can fit into the FIFO
+//! allocated by the call to USBFIFOConfig().
+//!
+//! \return This call will return 0 on success, or -1 to indicate that the FIFO
+//! is in use and cannot be written.
+//
+//*****************************************************************************
+long
+USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long ulSize)
+{
+ unsigned long ulFIFO;
+ unsigned char ucTxPktRdy;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the bit position of TxPktRdy based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ucTxPktRdy = USB_CSRL0_TXRDY;
+ }
+ else
+ {
+ ucTxPktRdy = USB_TXCSRL1_TXRDY;
+ }
+
+ //
+ // Don't allow transmit of data if the TxPktRdy bit is already set.
+ //
+ if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & ucTxPktRdy)
+ {
+ return(-1);
+ }
+
+ //
+ // Calculate the FIFO address.
+ //
+ ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2);
+
+ //
+ // Write the data to the FIFO.
+ //
+ for(; ulSize > 0; ulSize--)
+ {
+ HWREGB(ulFIFO) = *pucData++;
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Starts the transfer of data from an endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulTransType is set to indicate what type of data is being sent.
+//!
+//! This function will start the transfer of data from the FIFO for a given
+//! endpoint. This is necessary if the \b USB_EP_AUTO_SET bit was not enabled
+//! for the endpoint. Setting the \e ulTransType parameter will allow the
+//! appropriate signaling on the USB bus for the type of transaction being
+//! requested. The \e ulTransType parameter should be one of the following:
+//!
+//! - USB_TRANS_OUT for OUT transaction on any endpoint in host mode.
+//! - USB_TRANS_IN for IN transaction on any endpoint in device mode.
+//! - USB_TRANS_IN_LAST for the last IN transactions on endpoint zero in a
+//! sequence of IN transactions.
+//! - USB_TRANS_SETUP for setup transactions on endpoint zero.
+//! - USB_TRANS_STATUS for status results on endpoint zero.
+//!
+//! \return This call will return 0 on success, or -1 if a transmission is
+//! already in progress.
+//
+//*****************************************************************************
+long
+USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulTransType)
+{
+ unsigned long ulTxPktRdy;
+
+ //
+ // CHeck the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the bit position of TxPktRdy based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulTxPktRdy = ulTransType & 0xff;
+ }
+ else
+ {
+ ulTxPktRdy = (ulTransType >> 8) & 0xff;
+ }
+
+ //
+ // Don't allow transmit of data if the TxPktRdy bit is already set.
+ //
+ if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & USB_CSRL0_TXRDY)
+ {
+ return(-1);
+ }
+
+ //
+ // Set TxPktRdy in order to send the data.
+ //
+ HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) = ulTxPktRdy;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Forces a flush of an endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies if the IN or OUT endpoint should be accessed.
+//!
+//! This function will force the controller to flush out the data in the FIFO.
+//! The function can be called with either host or device controllers and
+//! requires the \e ulFlags parameter be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Endpoint zero has a different register set for FIFO flushing.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Nothing in the FIFO if neither of these bits are set.
+ //
+ if((HWREGB(ulBase + USB_O_CSRL0) &
+ (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ulBase + USB_O_CSRH0) = USB_CSRH0_FLUSH;
+ }
+ }
+ else
+ {
+ //
+ // Only reset the IN or OUT FIFO.
+ //
+ if(ulFlags & (USB_EP_HOST_IN | USB_EP_DEV_OUT))
+ {
+ //
+ // Nothing in the FIFO if neither of these bits are set.
+ //
+ if((HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &
+ USB_RXCSRL1_RXRDY) == 0)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_RXCSRL1_FLUSH;
+ }
+ }
+ else
+ {
+ if((HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &
+ USB_TXCSRL1_TXRDY) == 0)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_FLUSH;
+ }
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Schedules a request for an IN transaction on an endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will schedule a request for an IN transaction. When the USB
+//! device being communicated with responds the data, the data can be retrieved
+//! by calling USBEndpointDataGet() or via a DMA transfer.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Endpoint zero uses a different offset than the other endpoints.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulRegister = USB_O_CSRL0;
+ }
+ else
+ {
+ ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+ }
+
+ //
+ // Set the request for an IN transaction.
+ //
+ HWREGB(ulBase + ulRegister) = USB_RXCSRL1_REQPKT;
+}
+
+//*****************************************************************************
+//
+//! Issues a request for a status IN transaction on endpoint zero.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function is used to cause a request for an status IN transaction from
+//! a device on endpoint zero. This function can only be used with endpoint
+//! zero as that is the only control endpoint that supports this ability. This
+//! is used to complete the last phase of a control transaction to a device and
+//! an interrupt will be signaled when the status packet has been received.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Set the request for a status IN transaction.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
+}
+
+//*****************************************************************************
+//
+//! Sets the functional address for the device that is connected to an
+//! endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulAddr is the functional address for the controller to use for this
+//! endpoint.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will set the functional address for a device that is using
+//! this endpoint for communication. This \e ulAddr parameter is the address
+//! of the target device that this endpoint will be used to communicate with.
+//! The \e ulFlags parameter indicates if the IN or OUT endpoint should be set.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive address should be set.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the transmit address.
+ //
+ HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)) = ulAddr;
+ }
+ else
+ {
+ //
+ // Set the receive address.
+ //
+ HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current functional device address for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function returns the current functional address that an endpoint is
+//! using to communicate with a device. The \e ulFlags parameter determines if
+//! the IN or OUT endpoint's device address is returned.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return Returns the current function address being used by an endpoint.
+//
+//*****************************************************************************
+unsigned long
+USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive address should be returned.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Return this endpoint's transmit address.
+ //
+ return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)));
+ }
+ else
+ {
+ //
+ // Return this endpoint's receive address.
+ //
+ return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)));
+ }
+}
+
+//*****************************************************************************
+//
+//! Set the hub address for the device that is connected to an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulAddr is the hub address for the device using this endpoint.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will set the hub address for a device that is using this
+//! endpoint for communication. The \e ulFlags parameter determines if the
+//! device address for the IN or the OUT endpoint is set by this call.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the hub transmit or receive address is being set.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the hub transmit address for this endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)) = ulAddr;
+ }
+ else
+ {
+ //
+ // Set the hub receive address for this endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the current device hub address for this endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will return the current hub address that an endpoint is using
+//! to communicate with a device. The \e ulFlags parameter determines if the
+//! device address for the IN or OUT endpoint is returned.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return This function returns the current hub address being used by an
+//! endpoint.
+//
+//*****************************************************************************
+unsigned long
+USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the hub transmit or receive address should be returned.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Return the hub transmit address for this endpoint.
+ //
+ return(HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)));
+ }
+ else
+ {
+ //
+ // Return the hub receive address for this endpoint.
+ //
+ return(HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for USB power fault.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies the configuration of the power fault.
+//!
+//! This function will set the behavior of the USB controller during a power
+//! fault and the behavior of the USBPEN pin. The flags specify the power
+//! fault level sensitivity, the power fault action, and the power enable level
+//! and source. One of the following can be selected as the power fault level
+//! sensitivity:
+//!
+//! - \b USB_HOST_PWRFLT_LOW - Power fault is indicated by the pin being driven
+//! low.
+//! - \b USB_HOST_PWRFLT_HIGH - Power fault is indicated by the pin being
+//! driven! high.
+//!
+//! One of the following can be selected as the power fault action:
+//!
+//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault
+//! detected.
+//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBEPEN pin on a
+//! power fault.
+//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBEPEN pin low on a
+//! power fault.
+//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBEPEN pin high on a
+//! power fault.
+//!
+//! One of the following can be selected as the power enable level and source:
+//!
+//! - \b USB_HOST_PWREN_LOW - USBEPEN is driven low when power is enabled.
+//! - \b USB_HOST_PWREN_HIGH - USBEPEN is driven high when power is enabled.
+//! - \b USB_HOST_PWREN_VBLOW - USBEPEN is driven high when VBUS is low.
+//! - \b USB_HOST_PWREN_VBHIGH - USBEPEN is driven high when VBUS is high.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
+ USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)) == 0);
+
+ //
+ // Set the power fault configuration as specified. This will not change
+ // whether fault detection is enabled or not.
+ //
+ HWREGH(ulBase + USB_O_EPC) =
+ (ulFlags | (HWREGH(ulBase + USB_O_EPC) &
+ ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
+ USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)));
+}
+
+//*****************************************************************************
+//
+//! Enables power fault detection.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function enables power fault detection in the USB controller. If the
+//! USBPFLT pin is not in use this function should not be used.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable power fault input.
+ //
+ HWREGH(ulBase + USB_O_EPC) |= USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables power fault detection.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function disables power fault detection in the USB controller.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable power fault input.
+ //
+ HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the external power pin.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function enables the USBEPEN signal to enable an external power supply
+//! in host mode operation.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable the external power suppply enable signal.
+ //
+ HWREGH(ulBase + USB_O_EPC) |= USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Disables the external power pin.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function disables the USBEPEN signal to disable an external power
+//! supply in host mode operation.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Disable the external power supply enable signal.
+ //
+ HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Get the current frame number.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function returns the last frame number received.
+//!
+//! \return The last frame number received.
+//
+//*****************************************************************************
+unsigned long
+USBFrameNumberGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Return the most recent frame number.
+ //
+ return(HWREGH(ulBase + USB_O_FRAME));
+}
+
+//*****************************************************************************
+//
+//! Starts or ends a session.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies if this call starts or ends a session.
+//!
+//! This function is used in OTG mode to start a session request or end a
+//! session. If the \e bStart parameter is set to \b true, then this function
+//! start a session and if it is \b false it will end a session.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Start or end the session as directed.
+ //
+ if(bStart)
+ {
+ HWREGB(ulBase + USB_O_DEVCTL) |= USB_DEVCTL_SESSION;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the absolute FIFO address for a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint's FIFO address to return.
+//!
+//! This function returns the actual physical address of the FIFO. This is
+//! needed when the USB is going to be used with the uDMA controller and the
+//! source or destination address needs to be set to the physical FIFO address
+//! for a given endpoint.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ //
+ // Return the FIFO address for this endpoint.
+ //
+ return(ulBase + USB_O_FIFO0 + (ulEndpoint >> 2));
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode of the controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function returns the current operating mode on USB controllers with
+//! OTG or Dual mode functionality.
+//!
+//! For OTG controllers:
+//!
+//! The function will return on of the following values on OTG controllers:
+//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE.
+//!
+//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode
+//! on the B-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode
+//! on the B-side of the cable. If and OTG session request is started with no
+//! cable in place this is the default mode for the controller.
+//!
+//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to
+//! determine its role in the system.
+//!
+//! For Dual Mode controllers:
+//!
+//! The function will return on of the following values:
+//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//!
+//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host.
+//!
+//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device.
+//!
+//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as
+//! either a host or device.
+//!
+//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//
+//*****************************************************************************
+unsigned long
+USBModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Checks the current mode in the USB_O_DEVCTL and returns the current
+ // mode.
+ //
+ // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION
+ // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION
+ // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION |
+ // USB_DEVCTL_HOST
+ // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION
+ // USB_OTG_MODE_NONE: USB_DEVCTL_DEV
+ //
+ return(HWREGB(ulBase + USB_O_DEVCTL) &
+ (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION |
+ USB_DEVCTL_VBUS_M));
+}
+
+//*****************************************************************************
+//
+//! Sets the DMA channel to use for a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint's FIFO address to return.
+//! \param ulChannel specifies which DMA channel to use for which endpoint.
+//!
+//! This function is used to configure which DMA channel to use with a given
+//! endpoint. Receive DMA channels can only be used with receive endpoints
+//! and transmit DMA channels can only be used with transmit endpoints. This
+//! allows the 3 receive and 3 transmit DMA channels to be mapped to any
+//! endpoint other than 0. The values that should be passed into the \e
+//! ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h.
+//!
+//! \note This function only has an effect on microcontrollers that have the
+//! ability to change the DMA channel for an endpoint. Calling this function
+//! on other devices will have no effect.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulChannel)
+{
+ unsigned long ulMask;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+ ASSERT(ulChannel <= UDMA_CHANNEL_USBEP3TX);
+
+ //
+ // The input select mask needs to be shifted into the correct position
+ // based on the channel.
+ //
+ ulMask = 0xf << (ulChannel * 4);
+
+ //
+ // Clear out the current selection for the channel.
+ //
+ ulMask = HWREG(ulBase + USB_O_EPS) & (~ulMask);
+
+ //
+ // The input select is now shifted into the correct position based on the
+ // channel.
+ //
+ ulMask |= (USB_EP_TO_INDEX(ulEndpoint)) << (ulChannel * 4);
+
+ //
+ // Write the value out to the register.
+ //
+ HWREG(ulBase + USB_O_EPS) = ulMask;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to host.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to host mode. This
+//! is only valid on microcontrollers that have the host and device
+//! capabilities and not the OTG capabilities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostMode(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Set the USB controller mode to host.
+ //
+ HWREGB(ulBase + USB_O_GPCS) &= ~(USB_GPCS_DEVMOD);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/usb.h b/bsp/lm3s/Libraries/driverlib/usb.h new file mode 100644 index 0000000000..7cc8ec9924 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/usb.h @@ -0,0 +1,433 @@ +//*****************************************************************************
+//
+// usb.h - Prototypes for the USB Interface Driver.
+//
+// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __USB_H__
+#define __USB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnable(),
+// USBIntDisable(), and USBIntClear() as the ulIntFlags parameter, and which
+// are returned from USBIntStatus().
+//
+//*****************************************************************************
+#define USB_INT_ALL 0xFF030E0F // All Interrupt sources
+#define USB_INT_STATUS 0xFF000000 // Status Interrupts
+#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error
+#define USB_INT_SESSION_START 0x40000000 // Session Start Detected
+#define USB_INT_SESSION_END 0x20000000 // Session End Detected
+#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected
+#define USB_INT_CONNECT 0x10000000 // Device Connect Detected
+#define USB_INT_SOF 0x08000000 // Start of Frame Detected
+#define USB_INT_BABBLE 0x04000000 // Babble signaled
+#define USB_INT_RESET 0x04000000 // Reset signaled
+#define USB_INT_RESUME 0x02000000 // Resume detected
+#define USB_INT_SUSPEND 0x01000000 // Suspend detected
+#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid
+#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected
+#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts
+#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts
+#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt
+#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt
+#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt
+#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt
+#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts
+#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts
+#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt
+#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt
+#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBSpeedGet().
+//
+//*****************************************************************************
+#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined
+#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed
+#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBEndpointStatus(). The
+// USB_HOST_* values are used when the USB controller is in host mode and the
+// USB_DEV_* values are used when the USB controller is in device mode.
+//
+//*****************************************************************************
+#define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received
+#define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond
+#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
+#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error
+ // (ISOC Mode)
+#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a
+ // device
+#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
+#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
+#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
+ // (ISOC mode)
+#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received
+#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a
+ // device
+#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty
+#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted
+#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet
+#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a
+ // device
+#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received
+#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready
+#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint
+#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data
+#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to
+ // a full FIFO
+#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full
+#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready
+#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data
+ // to come
+#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint
+#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready
+#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty
+#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted
+#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before
+ // Data End seen
+#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint
+#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending
+#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostEndpointConfig() and
+// USBDevEndpointConfig() as the ulFlags parameter.
+//
+//*****************************************************************************
+#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled
+#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled
+#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled
+#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0
+#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1
+#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint
+#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint
+#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint
+#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint
+#define USB_EP_MODE_MASK 0x00000300 // Mode Mask
+#define USB_EP_SPEED_LOW 0x00000000 // Low Speed
+#define USB_EP_SPEED_FULL 0x00001000 // Full Speed
+#define USB_EP_HOST_EP0 0x00002000 // Host endpoint 0
+#define USB_EP_HOST_IN 0x00001000 // Host IN endpoint
+#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint
+#define USB_EP_DEV_EP0 0x00002000 // Device endpoint 0
+#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint
+#define USB_EP_DEV_OUT 0x00001000 // Device OUT endpoint
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostPwrFaultConfig() as
+// the ulFlags parameter.
+//
+//*****************************************************************************
+#define USB_HOST_PWRFLT_LOW 0x00000010
+#define USB_HOST_PWRFLT_HIGH 0x00000030
+#define USB_HOST_PWRFLT_EP_NONE 0x00000000
+#define USB_HOST_PWRFLT_EP_TRI 0x00000140
+#define USB_HOST_PWRFLT_EP_LOW 0x00000240
+#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
+#define USB_HOST_PWREN_LOW 0x00000000
+#define USB_HOST_PWREN_HIGH 0x00000001
+#define USB_HOST_PWREN_VBLOW 0x00000002
+#define USB_HOST_PWREN_VBHIGH 0x00000003
+
+//*****************************************************************************
+//
+// The following are special values that can be passed to
+// USBHostEndpointConfig() as the ulNAKPollInterval parameter.
+//
+//*****************************************************************************
+#define MAX_NAK_LIMIT 31 // Maximum NAK interval
+#define DISABLE_NAK_LIMIT 0 // No NAK timeouts
+
+//*****************************************************************************
+//
+// This value specifies the maximum size of transfers on endpoint 0 as 64
+// bytes. This value is fixed in hardware as the FIFO size for endpoint 0.
+//
+//*****************************************************************************
+#define MAX_PACKET_SIZE_EP0 64
+
+//*****************************************************************************
+//
+// These values are used to indicate which endpoint to access.
+//
+//*****************************************************************************
+#define USB_EP_0 0x00000000 // Endpoint 0
+#define USB_EP_1 0x00000010 // Endpoint 1
+#define USB_EP_2 0x00000020 // Endpoint 2
+#define USB_EP_3 0x00000030 // Endpoint 3
+#define USB_EP_4 0x00000040 // Endpoint 4
+#define USB_EP_5 0x00000050 // Endpoint 5
+#define USB_EP_6 0x00000060 // Endpoint 6
+#define USB_EP_7 0x00000070 // Endpoint 7
+#define USB_EP_8 0x00000080 // Endpoint 8
+#define USB_EP_9 0x00000090 // Endpoint 9
+#define USB_EP_10 0x000000A0 // Endpoint 10
+#define USB_EP_11 0x000000B0 // Endpoint 11
+#define USB_EP_12 0x000000C0 // Endpoint 12
+#define USB_EP_13 0x000000D0 // Endpoint 13
+#define USB_EP_14 0x000000E0 // Endpoint 14
+#define USB_EP_15 0x000000F0 // Endpoint 15
+#define NUM_USB_EP 16 // Number of supported endpoints
+
+//*****************************************************************************
+//
+// These macros allow conversion between 0-based endpoint indices and the
+// USB_EP_x values required when calling various USB APIs.
+//
+//*****************************************************************************
+#define INDEX_TO_USB_EP(x) ((x) << 4)
+#define USB_EP_TO_INDEX(x) ((x) >> 4)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBFIFOConfigSet() as the
+// ulFIFOSize parameter.
+//
+//*****************************************************************************
+#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO
+#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO
+#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO
+#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO
+#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO
+#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO
+#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO
+#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO
+#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO
+#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO
+#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO
+ // (occupying 16 bytes)
+#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO
+ // (occupying 32 bytes)
+#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO
+ // (occupying 64 bytes)
+#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO
+ // (occupying 128 bytes)
+#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO
+ // (occupying 256 bytes)
+#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO
+ // (occupying 512 bytes)
+#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO
+ // (occupying 1024 bytes)
+#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO
+ // (occupying 2048 bytes)
+#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO
+ // (occupying 4096 bytes)
+
+//*****************************************************************************
+//
+// This macro allow conversion from a FIFO size label as defined above to
+// a number of bytes
+//
+//*****************************************************************************
+#define USB_FIFO_SIZE_DB_FLAG 0x00000010
+#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \
+ (((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1))
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBEndpointDataSend() as the
+// ulTransType parameter.
+//
+//*****************************************************************************
+#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction
+#define USB_TRANS_IN 0x00000102 // Normal IN transaction
+#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for
+ // endpoint 0 in device mode)
+#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint
+ // 0)
+#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint
+ // 0)
+
+//*****************************************************************************
+//
+// The following are values are returned by the USBModeGet function.
+//
+//*****************************************************************************
+#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host
+ // mode.
+#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in
+ // Device mode.
+#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not
+ // set.
+#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set.
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long USBDevAddrGet(unsigned long ulBase);
+extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress);
+extern void USBDevConnect(unsigned long ulBase);
+extern void USBDevDisconnect(unsigned long ulBase);
+extern void USBDevEndpointConfig(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulMaxPacketSize,
+ unsigned long ulFlags);
+extern void USBDevEndpointConfigGet(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long *pulMaxPacketSize,
+ unsigned long *pulFlags);
+extern void USBDevEndpointDataAck(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ tBoolean bIsLastPacket);
+extern void USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBDevEndpointStallClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBDevEndpointStatusClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBEndpointDataAvail(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern void USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBEndpointDMADisable(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern long USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long *pulSize);
+extern long USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long ulSize);
+extern long USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulTransType);
+extern void USBEndpointDataToggleClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBEndpointStatus(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern unsigned long USBFIFOAddrGet(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern void USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long *pulFIFOAddress,
+ unsigned long *pulFIFOSize,
+ unsigned long ulFlags);
+extern void USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFIFOAddress,
+ unsigned long ulFIFOSize, unsigned long ulFlags);
+extern void USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBFrameNumberGet(unsigned long ulBase);
+extern unsigned long USBHostAddrGet(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags);
+extern void USBHostEndpointConfig(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulMaxPacketSize,
+ unsigned long ulNAKPollInterval,
+ unsigned long ulTargetEndpoint,
+ unsigned long ulFlags);
+extern void USBHostEndpointDataAck(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern void USBHostEndpointDataToggle(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ tBoolean bDataToggle,
+ unsigned long ulFlags);
+extern void USBHostEndpointStatusClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBHostHubAddrGet(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags);
+extern void USBHostPwrDisable(unsigned long ulBase);
+extern void USBHostPwrEnable(unsigned long ulBase);
+extern void USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags);
+extern void USBHostPwrFaultDisable(unsigned long ulBase);
+extern void USBHostPwrFaultEnable(unsigned long ulBase);
+extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint);
+extern void USBHostRequestStatus(unsigned long ulBase);
+extern void USBHostReset(unsigned long ulBase, tBoolean bStart);
+extern void USBHostResume(unsigned long ulBase, tBoolean bStart);
+extern unsigned long USBHostSpeedGet(unsigned long ulBase);
+extern void USBHostSuspend(unsigned long ulBase);
+extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern unsigned long USBIntStatus(unsigned long ulBase);
+extern void USBIntUnregister(unsigned long ulBase);
+extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart);
+extern unsigned long USBModeGet(unsigned long ulBase);
+extern void USBEndpointDMAChannel(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulChannel);
+extern void USBHostMode(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USB_H__
diff --git a/bsp/lm3s/Libraries/driverlib/watchdog.c b/bsp/lm3s/Libraries/driverlib/watchdog.c new file mode 100644 index 0000000000..fdfd5e821d --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/watchdog.c @@ -0,0 +1,567 @@ +//*****************************************************************************
+//
+// watchdog.c - Driver for the Watchdog Timer Module.
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup watchdog_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_watchdog.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/watchdog.h"
+
+//*****************************************************************************
+//
+//! Determines if the watchdog timer is enabled.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This will check to see if the watchdog timer is enabled.
+//!
+//! \return Returns \b true if the watchdog timer is enabled, and \b false
+//! if it is not.
+//
+//*****************************************************************************
+tBoolean
+WatchdogRunning(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // See if the watchdog timer module is enabled, and return.
+ //
+ return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This will enable the watchdog timer counter and interrupt.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog timer module.
+ //
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer reset.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Enables the capability of the watchdog timer to issue a reset to the
+//! processor upon a second timeout condition.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog reset.
+ //
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer reset.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Disables the capability of the watchdog timer to issue a reset to the
+//! processor upon a second timeout condition.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Disable the watchdog reset.
+ //
+ HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Locks out write access to the watchdog timer configuration registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogLock(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
+ // register causes the lock to go into effect.
+ //
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Enables write access to the watchdog timer configuration registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogUnlock(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Unlock watchdog register writes.
+ //
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
+}
+
+//*****************************************************************************
+//
+//! Gets the state of the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Returns the lock state of the watchdog timer registers.
+//!
+//! \return Returns \b true if the watchdog timer registers are locked, and
+//! \b false if they are not locked.
+//
+//*****************************************************************************
+tBoolean
+WatchdogLockState(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Get the lock state.
+ //
+ return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the watchdog timer reload value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param ulLoadVal is the load value for the watchdog timer.
+//!
+//! This function sets the value to load into the watchdog timer when the count
+//! reaches zero for the first time; if the watchdog timer is running when this
+//! function is called, then the value will be immediately loaded into the
+//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
+//! interrupt is immediately generated.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Set the load register.
+ //
+ HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
+}
+
+//*****************************************************************************
+//
+//! Gets the watchdog timer reload value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function gets the value that is loaded into the watchdog timer when
+//! the count reaches zero for the first time.
+//!
+//! \sa WatchdogReloadSet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+WatchdogReloadGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Get the load register.
+ //
+ return(HWREG(ulBase + WDT_O_LOAD));
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function reads the current value of the watchdog timer.
+//!
+//! \return Returns the current value of the watchdog timer.
+//
+//*****************************************************************************
+unsigned long
+WatchdogValueGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Get the current watchdog timer register value.
+ //
+ return(HWREG(ulBase + WDT_O_VALUE));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! watchdog timer interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! will enable the global interrupt in the interrupt controller; the watchdog
+//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source via
+//! WatchdogIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_WATCHDOG, pfnHandler);
+
+ //
+ // Enable the watchdog timer interrupt.
+ //
+ IntEnable(INT_WATCHDOG);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function does the actual unregistering of the interrupt handler. This
+//! function will clear the handler to be called when a watchdog timer
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_WATCHDOG);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_WATCHDOG);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Enables the watchdog timer interrupt.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog interrupt.
+ //
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer interrupt status.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the watchdog timer module. Either
+//! the raw interrupt status or the status of interrupt that is allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, where a 1 indicates that the
+//! watchdog interrupt is active, and a 0 indicates that it is not active.
+//
+//*****************************************************************************
+unsigned long
+WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + WDT_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + WDT_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! The watchdog timer interrupt source is cleared, so that it no longer
+//! asserts.
+//!
+//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
+//! several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (since NVIC still sees the interrupt source
+//! asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Clear the interrupt source.
+ //
+ HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
+}
+
+//*****************************************************************************
+//
+//! Enables stalling of the watchdog timer during debug events.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function allows the watchdog timer to stop counting when the processor
+//! is stopped by the debugger. By doing so, the watchdog is prevented from
+//! expiring (typically almost immediately from a human time perspective) and
+//! resetting the system (if reset is enabled). The watchdog will instead
+//! expired after the appropriate number of processor cycles have been executed
+//! while debugging (or at the appropriate time after the processor has been
+//! restarted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable timer stalling.
+ //
+ HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
+}
+
+//*****************************************************************************
+//
+//! Disables stalling of the watchdog timer during debug events.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function disables the debug mode stall of the watchdog timer. By
+//! doing so, the watchdog timer continues to count regardless of the processor
+//! debug state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Disable timer stalling.
+ //
+ HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/bsp/lm3s/Libraries/driverlib/watchdog.h b/bsp/lm3s/Libraries/driverlib/watchdog.h new file mode 100644 index 0000000000..50fde76e67 --- /dev/null +++ b/bsp/lm3s/Libraries/driverlib/watchdog.h @@ -0,0 +1,74 @@ +//*****************************************************************************
+//
+// watchdog.h - Prototypes for the Watchdog Timer API
+//
+// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean WatchdogRunning(unsigned long ulBase);
+extern void WatchdogEnable(unsigned long ulBase);
+extern void WatchdogResetEnable(unsigned long ulBase);
+extern void WatchdogResetDisable(unsigned long ulBase);
+extern void WatchdogLock(unsigned long ulBase);
+extern void WatchdogUnlock(unsigned long ulBase);
+extern tBoolean WatchdogLockState(unsigned long ulBase);
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);
+extern unsigned long WatchdogValueGet(unsigned long ulBase);
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void WatchdogIntUnregister(unsigned long ulBase);
+extern void WatchdogIntEnable(unsigned long ulBase);
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void WatchdogIntClear(unsigned long ulBase);
+extern void WatchdogStallEnable(unsigned long ulBase);
+extern void WatchdogStallDisable(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __WATCHDOG_H__
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