diff options
| author | [email protected] <[email protected]> | 2011-06-30 13:54:31 +0000 |
|---|---|---|
| committer | [email protected] <[email protected]> | 2011-06-30 13:54:31 +0000 |
| commit | 3d4e5e1fea2973cd462186a594da14b75c69e223 (patch) | |
| tree | bacbcd7e73260f23b8b27ce35bdadc09a624d0cc /bsp | |
| parent | 311e6695694c31dc0bd21453688f74ccfb76aaab (diff) | |
update library to 3.5.0; update project file to Keil4.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1557 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'bsp')
91 files changed, 6026 insertions, 6034 deletions
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s index 2ca88c2548..e34a520671 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s @@ -1,33 +1,34 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_cl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Connectivity line Devices vector table for Atollic
- * toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR
- * address.
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_cl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Connectivity line Devices vector table for Atollic
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR
+ * address.
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -469,4 +470,4 @@ g_pfnVectors: .weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler ,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s index dc976502eb..0aa91884f2 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s @@ -1,33 +1,34 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_hd.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x High Density Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address,
- * - Configure the clock system
- * - Configure external SRAM mounted on STM3210E-EVAL board
- * to be used as data memory (optional, to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_hd.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x High Density Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Configure external SRAM mounted on STM3210E-EVAL board
+ * to be used as data memory (optional, to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -465,4 +466,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s index 179299095e..55aa398616 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s @@ -1,33 +1,35 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_hd_vl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x High Density Value Line Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Configure external SRAM mounted on STM32100E-EVAL board
- * to be used as data memory (optional, to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_hd_vl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x High Density Value Line Devices vector table for Atollic
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Configure external SRAM mounted on STM32100E-EVAL board
+ * to be used as data memory (optional, to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -191,7 +193,7 @@ g_pfnVectors: .word TIM14_IRQHandler
.word 0
.word 0
- .word FSMC_IRQHandler
+ .word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
@@ -412,9 +414,6 @@ g_pfnVectors: .weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
@@ -448,5 +447,5 @@ g_pfnVectors: .weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s index 828fc8e18f..2c5aaa06be 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s @@ -1,31 +1,32 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_ld.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Low Density Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address.
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_ld.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Low Density Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address.
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -343,4 +344,4 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s index 6ac820acdd..9af6e8ba0b 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s @@ -1,31 +1,32 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_ld_vl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_ld_vl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -387,5 +388,5 @@ g_pfnVectors: .weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s index cc92a1e31a..c14ba21042 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s @@ -1,31 +1,32 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_md.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_md.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -358,5 +359,5 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s index abb71f65bb..4ac1230db3 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s @@ -1,31 +1,33 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_md_vl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_md_vl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -402,5 +404,5 @@ g_pfnVectors: .weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s index 46bdf874d7..19bdf5a8c9 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s @@ -1,33 +1,34 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_xl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system and the external SRAM mounted on
- * STM3210E-EVAL board to be used as data memory (optional,
- * to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_xl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM3210E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -463,4 +464,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s index 47da7d8acf..8196e697fd 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
@@ -365,4 +365,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s index 179921d875..adc9b94a93 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
@@ -355,4 +355,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s index 4465a1a6bb..d6082b0961 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
@@ -126,7 +126,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
- DCD FSMC_IRQHandler ; FSMC
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
@@ -244,7 +244,6 @@ Default_Handler PROC EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
- EXPORT FSMC_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
@@ -299,7 +298,6 @@ CEC_IRQHandler TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
-FSMC_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
@@ -345,4 +343,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s index 54c7187a50..3f3ac2ffd3 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
@@ -294,4 +294,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s index bcb7aaf307..fe22fc011b 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
@@ -301,4 +301,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s index bb65342ad3..3223fc95b3 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
@@ -304,4 +304,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s index 67109eed81..d3b8aa6c15 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
@@ -312,4 +312,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s index b3b6484c1f..7970052d7c 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
@@ -355,4 +355,4 @@ __user_initial_stackheap END
-;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s index b017eb811a..039ec06ca0 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s @@ -1,32 +1,33 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_cl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR
- * address.
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_cl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR
+ * address.
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -464,4 +465,4 @@ g_pfnVectors: .weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler ,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s index a1b1f93974..e4ba08c419 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s @@ -1,33 +1,34 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_hd.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system and the external SRAM mounted on
- * STM3210E-EVAL board to be used as data memory (optional,
- * to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_hd.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM3210E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -461,4 +462,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s index 9bfd877aba..daad5cc34b 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s @@ -1,34 +1,35 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_hd_vl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x High Density Value Line Devices vector table for RIDE7
- * toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system and the external SRAM mounted on
- * STM32100E-EVAL board to be used as data memory (optional,
- * to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_hd_vl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x High Density Value Line Devices vector table for RIDE7
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM32100E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -187,7 +188,7 @@ g_pfnVectors: .word TIM14_IRQHandler
.word 0
.word 0
- .word FSMC_IRQHandler
+ .word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
@@ -405,9 +406,6 @@ g_pfnVectors: .weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
@@ -441,4 +439,4 @@ g_pfnVectors: .weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s index c3dbf4147a..aaa09ecd4b 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s @@ -1,31 +1,32 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_ld.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_ld.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -339,4 +340,4 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s index c2e23536d1..d4401be2f5 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s @@ -1,32 +1,33 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_ld_vl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7
- * toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_ld_vl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -379,4 +380,4 @@ g_pfnVectors: .weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s index b91fbd7db4..4b4a0502be 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s @@ -1,31 +1,32 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_md.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_md.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -354,4 +355,4 @@ g_pfnVectors: .weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s index 368b91519f..8bce9979bc 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s @@ -1,32 +1,33 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_md_vl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7
- * toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_md_vl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -395,4 +396,4 @@ g_pfnVectors: .weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s index 4ae953823a..3d727a0d55 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s @@ -1,33 +1,34 @@ /**
- ******************************************************************************
- * @file startup_stm32f10x_xl.s
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system and the external SRAM mounted on
- * STM3210E-EVAL board to be used as data memory (optional,
- * to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- *******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ ******************************************************************************
+ * @file startup_stm32f10x_xl.s
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM3210E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
.syntax unified
.cpu cortex-m3
@@ -461,4 +462,4 @@ g_pfnVectors: .weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s index 8e317de20b..55a79320bd 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for
-;* EWARM5.x toolchain.
+;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
@@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -504,4 +504,4 @@ OTG_FS_IRQHandler B OTG_FS_IRQHandler
END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s index cb30e58d69..37ee7a203f 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s @@ -1,9 +1,9 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
-;* Description : STM32F10x High Density Devices vector table for EWARM5.x
+;* Version : V3.5.0
+;* Date : 11-March-2011
+;* Description : STM32F10x High Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
@@ -21,7 +21,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -493,4 +493,4 @@ DMA2_Channel4_5_IRQHandler END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s index 5d872cbfb9..33f592f1a5 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
-;* for EWARM5.x toolchain.
+;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
@@ -22,7 +22,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -119,7 +119,7 @@ __vector_table DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
- DCD FSMC_IRQHandler ; FSMC
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
@@ -402,11 +402,6 @@ TIM13_IRQHandler TIM14_IRQHandler
B TIM14_IRQHandler
- PUBWEAK FSMC_IRQHandler
- SECTION .text:CODE:REORDER(1)
-FSMC_IRQHandler
- B FSMC_IRQHandler
-
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
@@ -463,4 +458,4 @@ DMA2_Channel5_IRQHandler B DMA2_Channel5_IRQHandler
END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s index 8377fbba2e..e2b2b4df06 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s @@ -1,9 +1,9 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
-;* Description : STM32F10x Low Density Devices vector table for EWARM5.x
+;* Version : V3.5.0
+;* Date : 11-March-2011
+;* Description : STM32F10x Low Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
@@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -363,4 +363,4 @@ USBWakeUp_IRQHandler B USBWakeUp_IRQHandler
END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s index ec86189757..a4a49331c5 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
-;* for EWARM5.x toolchain.
+;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
@@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -366,4 +366,4 @@ TIM7_IRQHandler B TIM7_IRQHandler
END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s index f06c5435cd..5863eb90f4 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for
-;* EWARM5.x toolchain.
+;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
@@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -388,4 +388,4 @@ USBWakeUp_IRQHandler B USBWakeUp_IRQHandler
END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s index 5d3b7134c7..add509da6c 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s @@ -1,10 +1,10 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
+;* Version : V3.5.0
+;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
-;* for EWARM5.x toolchain.
+;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
@@ -20,7 +20,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -391,4 +391,4 @@ TIM7_IRQHandler B TIM7_IRQHandler
END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s index 9ed63d54a9..a7f49c56dd 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s @@ -1,9 +1,9 @@ -;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
-;* Version : V3.4.0
-;* Date : 10/15/2010
-;* Description : STM32F10x XL-Density Devices vector table for EWARM5.x
+;* Version : V3.5.0
+;* Date : 11-March-2011
+;* Description : STM32F10x XL-Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
@@ -21,7 +21,7 @@ ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
+;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
@@ -493,4 +493,4 @@ DMA2_Channel4_5_IRQHandler END
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h index fc6d74dc6e..af0c7c9af1 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h @@ -2,15 +2,31 @@ ******************************************************************************
* @file stm32f10x.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F10x Connectivity line,
* High density, High density value line, Medium density,
* Medium density Value line, Low density, Low density Value line
* and XL-density devices.
- ******************************************************************************
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripheral�s drivers in application code(i.e.
+ * code will be based on direct access to peripheral�s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral�s registers hardware
+ *
+ ******************************************************************************
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -19,7 +35,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -116,12 +132,14 @@ /**
* @brief STM32F10x Standard Peripheral Library version number
*/
-#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
-#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
- | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
- | __STM32F10X_STDPERIPH_VERSION_SUB2)
+#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F10X_STDPERIPH_VERSION_RC))
/**
* @}
@@ -346,7 +364,6 @@ typedef enum IRQn TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
@@ -358,7 +375,7 @@ typedef enum IRQn DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
- mapped at postion 60 only if the MISC_REMAP bit in
+ mapped at position 60 only if the MISC_REMAP bit in
the AFIO_MAPR2 register is set) */
#endif /* STM32F10X_HD_VL */
@@ -1005,7 +1022,7 @@ typedef struct __IO uint32_t MAPR2;
} AFIO_TypeDef;
/**
- * @brief Inter-integrated Circuit Interface
+ * @brief Inter Integrated Circuit Interface
*/
typedef struct
@@ -1953,7 +1970,7 @@ typedef struct #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
- #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
+ #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
@@ -2663,7 +2680,7 @@ typedef struct #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
/*!< PTP_PPS_REMAP configuration */
- #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+ #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
#endif
/***************** Bit definition for AFIO_EXTICR1 register *****************/
@@ -3210,7 +3227,7 @@ typedef struct #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
@@ -3218,7 +3235,7 @@ typedef struct #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
@@ -3413,7 +3430,7 @@ typedef struct #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
@@ -3468,7 +3485,7 @@ typedef struct /******************* Bit definition for DMA_CCR2 register *******************/
#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
-#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
@@ -3515,166 +3532,166 @@ typedef struct #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
/*!<****************** Bit definition for DMA_CCR4 register *******************/
-#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */
-#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
-#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
-#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
-#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
-#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */
-#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
-#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
/****************** Bit definition for DMA_CCR5 register *******************/
-#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */
-#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
-#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
-#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
-#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
-#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */
-#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
-#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
/******************* Bit definition for DMA_CCR6 register *******************/
-#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */
-#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
-#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
-#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
-#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
-#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */
-#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
-#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
/******************* Bit definition for DMA_CCR7 register *******************/
-#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */
-#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
-#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
-#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
-#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
-#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */
-#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
-#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
/****************** Bit definition for DMA_CNDTR1 register ******************/
-#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR2 register ******************/
-#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR3 register ******************/
-#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR4 register ******************/
-#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR5 register ******************/
-#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR6 register ******************/
-#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR7 register ******************/
-#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR1 register *******************/
-#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR2 register *******************/
-#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR3 register *******************/
-#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR4 register *******************/
-#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR5 register *******************/
-#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR6 register *******************/
-#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR7 register *******************/
-#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR1 register *******************/
-#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/****************** Bit definition for DMA_CMAR2 register *******************/
-#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/****************** Bit definition for DMA_CMAR3 register *******************/
-#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/****************** Bit definition for DMA_CMAR4 register *******************/
-#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/****************** Bit definition for DMA_CMAR5 register *******************/
-#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/****************** Bit definition for DMA_CMAR6 register *******************/
-#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/****************** Bit definition for DMA_CMAR7 register *******************/
-#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/******************************************************************************/
/* */
@@ -3683,348 +3700,348 @@ typedef struct /******************************************************************************/
/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
-#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
-#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
-#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
-#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
+#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */
/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */
-#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
-#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */
-#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
-#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
-#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */
-#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */
-#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */
-#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
-#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
-#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
+#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
+#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
+#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
+#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
+#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
+#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
-#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
-#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
-#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
-#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
-#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
-#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
-#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
-#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
-#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
-#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */
/******************************************************************************/
/* */
@@ -4033,90 +4050,90 @@ typedef struct /******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
-#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
-#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
-#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
-#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
-#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
@@ -4124,45 +4141,45 @@ typedef struct /* */
/******************************************************************************/
/******************** Bit definition for CEC_CFGR register ******************/
-#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
-#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
-#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
-#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
+#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
+#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
+#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
/******************** Bit definition for CEC_OAR register ******************/
-#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
-#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
+#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
/******************** Bit definition for CEC_PRES register ******************/
-#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
+#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
/******************** Bit definition for CEC_ESR register ******************/
-#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
-#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
-#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
-#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
-#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
-#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
-#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */
+#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
+#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
+#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
+#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
+#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
+#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
+#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */
/******************** Bit definition for CEC_CSR register ******************/
-#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
-#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
-#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
-#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
-#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
-#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
-#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
-#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
+#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
+#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
+#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
+#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
+#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
+#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
+#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
+#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
/******************** Bit definition for CEC_TXD register ******************/
-#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
+#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
/******************** Bit definition for CEC_RXD register ******************/
-#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
+#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
/******************************************************************************/
/* */
@@ -4171,290 +4188,290 @@ typedef struct /******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */
/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */
/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
+#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */
+#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */
-#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */
/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
/******************************************************************************/
/* */
@@ -4463,41 +4480,41 @@ typedef struct /******************************************************************************/
/******************* Bit definition for RTC_CRH register ********************/
-#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */
-#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */
-#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */
+#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */
/******************* Bit definition for RTC_CRL register ********************/
-#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */
-#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */
-#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */
-#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */
-#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */
-#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */
+#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */
+#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */
+#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */
+#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */
+#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */
/******************* Bit definition for RTC_PRLH register *******************/
-#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */
+#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */
/******************* Bit definition for RTC_PRLL register *******************/
-#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */
+#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */
/******************* Bit definition for RTC_DIVH register *******************/
-#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */
+#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */
/******************* Bit definition for RTC_DIVL register *******************/
-#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */
+#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */
/******************* Bit definition for RTC_CNTH register *******************/
-#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */
+#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */
/******************* Bit definition for RTC_CNTL register *******************/
-#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */
+#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */
/******************* Bit definition for RTC_ALRH register *******************/
-#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */
+#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */
/******************* Bit definition for RTC_ALRL register *******************/
-#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */
+#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */
/******************************************************************************/
/* */
@@ -4506,20 +4523,20 @@ typedef struct /******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
/******************************************************************************/
/* */
@@ -4528,35 +4545,35 @@ typedef struct /******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
@@ -4565,804 +4582,804 @@ typedef struct /******************************************************************************/
/****************** Bit definition for FSMC_BCR1 register *******************/
-#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
-#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
/****************** Bit definition for FSMC_BCR2 register *******************/
-#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
-#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
/****************** Bit definition for FSMC_BCR3 register *******************/
-#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
-#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
/****************** Bit definition for FSMC_BCR4 register *******************/
-#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
-#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
-#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
-#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
-#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
-#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
-#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
-#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
-#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
-#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
-#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
-#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
/****************** Bit definition for FSMC_BTR1 register ******************/
-#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/****************** Bit definition for FSMC_BTR2 register *******************/
-#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/******************* Bit definition for FSMC_BTR3 register *******************/
-#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/****************** Bit definition for FSMC_BTR4 register *******************/
-#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/****************** Bit definition for FSMC_BWTR1 register ******************/
-#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/****************** Bit definition for FSMC_BWTR2 register ******************/
-#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
-#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/****************** Bit definition for FSMC_BWTR3 register ******************/
-#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/****************** Bit definition for FSMC_BWTR4 register ******************/
-#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
-#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
/****************** Bit definition for FSMC_PCR2 register *******************/
-#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
-#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */
-#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
-#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
-#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
-#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
-#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
/****************** Bit definition for FSMC_PCR3 register *******************/
-#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
-#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */
-#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
-#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
-#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
-#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
/****************** Bit definition for FSMC_PCR4 register *******************/
-#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
-#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */
-#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
-#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
-#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
-#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
/******************* Bit definition for FSMC_SR2 register *******************/
-#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
-#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
-#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
-#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
-#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
+#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
/******************* Bit definition for FSMC_SR3 register *******************/
-#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
-#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
-#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
-#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
-#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
+#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
/******************* Bit definition for FSMC_SR4 register *******************/
-#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
-#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
-#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
-#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
-#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
+#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
/****************** Bit definition for FSMC_PMEM2 register ******************/
-#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
/****************** Bit definition for FSMC_PMEM3 register ******************/
-#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
/****************** Bit definition for FSMC_PMEM4 register ******************/
-#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
/****************** Bit definition for FSMC_PATT2 register ******************/
-#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
/****************** Bit definition for FSMC_PATT3 register ******************/
-#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
/****************** Bit definition for FSMC_PATT4 register ******************/
-#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
/****************** Bit definition for FSMC_PIO4 register *******************/
-#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
-#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
-#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
-#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
-#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
/****************** Bit definition for FSMC_ECCR2 register ******************/
-#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
/****************** Bit definition for FSMC_ECCR3 register ******************/
-#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
/******************************************************************************/
/* */
@@ -5371,157 +5388,157 @@ typedef struct /******************************************************************************/
/****************** Bit definition for SDIO_POWER register ******************/
-#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
-#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
/****************** Bit definition for SDIO_CLKCR register ******************/
-#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
-#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
-#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
-#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
-#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
-#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
/******************* Bit definition for SDIO_ARG register *******************/
-#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
/******************* Bit definition for SDIO_CMD register *******************/
-#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
-#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
-#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
-#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
-#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
/***************** Bit definition for SDIO_RESPCMD register *****************/
-#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
/****************** Bit definition for SDIO_RESP0 register ******************/
-#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
/****************** Bit definition for SDIO_RESP1 register ******************/
-#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
/****************** Bit definition for SDIO_RESP2 register ******************/
-#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
/****************** Bit definition for SDIO_RESP3 register ******************/
-#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
/****************** Bit definition for SDIO_RESP4 register ******************/
-#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
/****************** Bit definition for SDIO_DTIMER register *****************/
-#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
/****************** Bit definition for SDIO_DLEN register *******************/
-#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
/****************** Bit definition for SDIO_DCTRL register ******************/
-#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
-#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
-#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
-#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
-#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
-#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
/****************** Bit definition for SDIO_DCOUNT register *****************/
-#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
/****************** Bit definition for SDIO_STA register ********************/
-#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
-#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
-#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
-#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
-#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
-#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
-#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
-#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
-#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
-#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
-#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
-#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
-#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
/******************* Bit definition for SDIO_ICR register *******************/
-#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
/****************** Bit definition for SDIO_MASK register *******************/
-#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
/***************** Bit definition for SDIO_FIFOCNT register *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
/****************** Bit definition for SDIO_FIFO register *******************/
-#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
/******************************************************************************/
/* */
@@ -5529,667 +5546,667 @@ typedef struct /* */
/******************************************************************************/
-/*!<Endpoint-specific registers */
+/*!< Endpoint-specific registers */
/******************* Bit definition for USB_EP0R register *******************/
-#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
/******************* Bit definition for USB_EP1R register *******************/
-#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
/******************* Bit definition for USB_EP2R register *******************/
-#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
/******************* Bit definition for USB_EP3R register *******************/
-#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
/******************* Bit definition for USB_EP4R register *******************/
-#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
/******************* Bit definition for USB_EP5R register *******************/
-#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
/******************* Bit definition for USB_EP6R register *******************/
-#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
/******************* Bit definition for USB_EP7R register *******************/
-#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
-#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
-#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
-#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
-#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
-/*!<Common registers */
+/*!< Common registers */
/******************* Bit definition for USB_CNTR register *******************/
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
/******************* Bit definition for USB_ISTR register *******************/
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */
/******************* Bit definition for USB_FNR register ********************/
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */
/****************** Bit definition for USB_DADDR register *******************/
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
-#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
-#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
-#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
-#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
-#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
-#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */
-#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
-#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */
-/*!<Buffer descriptor table */
+/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
-#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
-#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
-#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
-#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
-#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
-#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
-#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
-#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
-#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
-#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
-#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
-#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
-#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
-#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
-#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
-#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
-#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
-#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
-#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
-#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
-#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
-#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
-#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
-#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
-#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
-#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
-#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
-#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
-#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
-#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
-#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
-#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
-#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
-#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
-#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
-#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
-#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
@@ -6197,1248 +6214,1248 @@ typedef struct /* */
/******************************************************************************/
-/*!<CAN control and status registers */
+/*!< CAN control and status registers */
/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
-#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
-#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
-#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
-#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
-#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
-#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
-#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
-#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */
/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
-#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
-#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
-#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
-#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
-#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
-#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
-#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */
/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
-#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
-#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
-#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
-#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
-#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */
/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
-#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */
/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
-#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
-#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
-#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
-#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
-#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
-#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
-#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */
-/*!<Mailbox registers */
+/*!< Mailbox registers */
/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
-/*!<CAN filter registers */
+/*!< CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */
/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */
/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
/******************************************************************************/
/* */
@@ -7447,82 +7464,82 @@ typedef struct /******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
-#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
-#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
-#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
-#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
-#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
-#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
-#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */
-#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */
/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */
/******************************************************************************/
/* */
@@ -7531,93 +7548,93 @@ typedef struct /******************************************************************************/
/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
-#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
-#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
-#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
-#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
-#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
-#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
-#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
-#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
-#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
-#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
-#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
-#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
-#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
-#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
-#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
-#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
-#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
-#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
-#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
-#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
-#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
-#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
-#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
-#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
-#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
-#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
-#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
-#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
-#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
-#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
-#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
-#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
/******************************************************************************/
/* */
@@ -7626,82 +7643,82 @@ typedef struct /******************************************************************************/
/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
-#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
-#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
-#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
-#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
-#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
-#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
-#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
-#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
-#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
-#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
-#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
-#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
-#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
-#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
-#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
-#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
-#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
-#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
-#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */
/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
-#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
-#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
-#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
-#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
-#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
-#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
-#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
-#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
-#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
-#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
-#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
-#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */
/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
/******************************************************************************/
/* */
@@ -7710,59 +7727,59 @@ typedef struct /******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */
/******************************************************************************/
/* */
@@ -7771,88 +7788,88 @@ typedef struct /******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */
-#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */
-#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */
-#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */
+#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */
-#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */
-#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */
+#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */
/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
/***************** Bit definition for FLASH_OPTKEYR register ****************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */
-#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */
-#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */
-#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */
+#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */
+#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */
/******************* Bit definition for FLASH_CR register *******************/
-#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */
-#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */
-#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */
-#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */
-#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */
-#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */
-#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */
-#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */
-#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */
-#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */
+#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */
+#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */
+#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */
/******************* Bit definition for FLASH_AR register *******************/
-#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */
-#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */
+#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */
-#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */
-#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
-#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
-#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
-#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */
+#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
+#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
+#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
+#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */
/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
/*----------------------------------------------------------------------------*/
/****************** Bit definition for FLASH_RDP register *******************/
-#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */
-#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
/****************** Bit definition for FLASH_USER register ******************/
-#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */
-#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
/****************** Bit definition for FLASH_Data0 register *****************/
-#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */
-#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
/****************** Bit definition for FLASH_Data1 register *****************/
-#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */
-#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
/****************** Bit definition for FLASH_WRP0 register ******************/
-#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
-#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP1 register ******************/
-#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
-#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP2 register ******************/
-#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
-#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP3 register ******************/
-#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
-#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
#ifdef STM32F10X_CL
/******************************************************************************/
@@ -8316,4 +8333,4 @@ typedef struct * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h index 22ce5a06fc..739f33283e 100644 --- a/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h +++ b/bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h @@ -2,10 +2,11 @@ ******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
- ******************************************************************************
+ ******************************************************************************
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -14,7 +15,7 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -94,4 +95,4 @@ extern void SystemCoreClockUpdate(void); /**
* @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/SConscript b/bsp/stm32f107/Libraries/SConscript index 7b86f60d1f..44b213e685 100644 --- a/bsp/stm32f107/Libraries/SConscript +++ b/bsp/stm32f107/Libraries/SConscript @@ -2,9 +2,13 @@ import rtconfig Import('RTT_ROOT')
from building import *
+# get current directory
+cwd = GetCurrentDir()
+
# The set of source files associated with this SConscript file.
src = Split("""
CMSIS/CM3/CoreSupport/core_cm3.c
+CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
@@ -30,11 +34,30 @@ STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c STM32F10x_StdPeriph_Driver/src/misc.c
""")
-path = [RTT_ROOT + '/bsp/stm3210/Libraries/STM32F10x_StdPeriph_Driver/inc',
- RTT_ROOT + '/bsp/stm3210/Libraries/CMSIS/CM3/CoreSupport',
- RTT_ROOT + '/bsp/stm3210/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x']
+# starupt scripts for each STM32 kind
+startup_scripts = {}
+startup_scripts['STM32F10X_CL'] = 'startup_stm32f10x_cl.s'
+startup_scripts['STM32F10X_HD'] = 'startup_stm32f10x_hd.s'
+startup_scripts['STM32F10X_HD_VL'] = 'startup_stm32f10x_hd_vl.s'
+startup_scripts['STM32F10X_LD'] = 'startup_stm32f10x_ld.s'
+startup_scripts['STM32F10X_LD_VL'] = 'startup_stm32f10x_ld_vl.s'
+startup_scripts['STM32F10X_MD'] = 'startup_stm32f10x_md.s'
+startup_scripts['STM32F10X_MD_VL'] = 'startup_stm32f10x_md_vl.s'
+startup_scripts['STM32F10X_XL'] = 'startup_stm32f10x_xl.s'
+
+# add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+ src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/' + startup_scripts[rtconfig.STM32_TYPE]]
+elif rtconfig.CROSS_TOOL == 'keil':
+ src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/' + startup_scripts[rtconfig.STM32_TYPE]]
+elif rtconfig.CROSS_TOOL == 'iar':
+ src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/' + startup_scripts[rtconfig.STM32_TYPE]]
+
+path = [cwd + '/STM32F10x_StdPeriph_Driver/inc',
+ cwd + '/CMSIS/CM3/CoreSupport',
+ cwd + '/CMSIS/CM3/DeviceSupport/ST/STM32F10x']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
-group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path)
+group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h index 7a93d5a1ad..7d401ca9be 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file misc.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
@@ -216,4 +217,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h index 26e725fa17..d1b2653a66 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_adc.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_ADC_H
@@ -479,4 +480,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h index dc40ec22ec..b620753eff 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_bkp.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the BKP firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_BKP_H
@@ -191,4 +192,4 @@ void BKP_ClearITPendingBit(void); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h index 544d779c0a..648f747cdc 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_can.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CAN_H
@@ -51,38 +52,51 @@ typedef struct
{
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
+ This parameter can be a value of
+ @ref CAN_operating_mode */
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware
- is allowed to lengthen or shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of
+ @ref CAN_synchronisation_jump_width */
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
+ Segment 2.
+ This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_2 */
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set either to ENABLE or DISABLE. */
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
+ communication mode. This parameter can be set
+ either to ENABLE or DISABLE. */
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set either to ENABLE or DISABLE. */
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
+ management. This parameter can be set either
+ to ENABLE or DISABLE. */
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set either to ENABLE or DISABLE. */
+ This parameter can be set either to ENABLE or
+ DISABLE. */
- FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.
- This parameter can be set either to ENABLE or DISABLE. */
+ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
+ retransmission mode. This parameter can be
+ set either to ENABLE or DISABLE. */
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set either to ENABLE or DISABLE. */
+ This parameter can be set either to ENABLE
+ or DISABLE. */
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set either to ENABLE or DISABLE. */
+ This parameter can be set either to ENABLE
+ or DISABLE. */
} CAN_InitTypeDef;
/**
@@ -91,36 +105,36 @@ typedef struct typedef struct
{
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
@@ -136,16 +150,20 @@ typedef struct uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
- uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
- uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter can be a value between 0 to 8 */
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
} CanTxMsg;
/**
@@ -160,19 +178,23 @@ typedef struct uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_identifier_type */
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter can be a value between 0 to 0xFF */
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
} CanRxMsg;
/**
@@ -187,14 +209,14 @@ typedef struct * @{
*/
-#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */
+#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
/**
* @}
*/
-/** @defgroup CAN_operating_mode
+/** @defgroup CAN_Mode
* @{
*/
@@ -203,8 +225,40 @@ typedef struct #define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
- ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+ ((MODE) == CAN_Mode_LoopBack)|| \
+ ((MODE) == CAN_Mode_Silent) || \
+ ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+ * @}
+ */
+
+
+/**
+ * @defgroup CAN_Operating_Mode
+ * @{
+ */
+#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+ ((MODE) == CAN_OperatingMode_Normal)|| \
+ ((MODE) == CAN_OperatingMode_Sleep))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
+
+
/**
* @}
*/
@@ -295,7 +349,7 @@ typedef struct * @{
*/
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
@@ -322,11 +376,10 @@ typedef struct * @{
*/
-#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
((FIFO) == CAN_FilterFIFO1))
-
/**
* @}
*/
@@ -356,10 +409,10 @@ typedef struct * @{
*/
-#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))
-
+#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+ ((IDTYPE) == CAN_Id_Extended))
/**
* @}
*/
@@ -368,9 +421,9 @@ typedef struct * @{
*/
-#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
/**
* @}
@@ -380,10 +433,10 @@ typedef struct * @{
*/
-#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */
-#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
/**
* @}
@@ -393,8 +446,8 @@ typedef struct * @{
*/
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
@@ -406,8 +459,8 @@ typedef struct * @{
*/
-#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
/**
* @}
@@ -417,8 +470,27 @@ typedef struct * @{
*/
-#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
+
/**
* @}
@@ -508,20 +580,44 @@ typedef struct #define CAN_IT_RQCP2 CAN_IT_TME
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Legacy
+ * @{
+ */
+#define CANINITFAILED CAN_InitStatus_Failed
+#define CANINITOK CAN_InitStatus_Success
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+#define CAN_ID_STD CAN_Id_Standard
+#define CAN_ID_EXT CAN_Id_Extended
+#define CAN_RTR_DATA CAN_RTR_Data
+#define CAN_RTR_REMOTE CAN_RTR_Remote
+#define CANTXFAILE CAN_TxStatus_Failed
+#define CANTXOK CAN_TxStatus_Ok
+#define CANTXPENDING CAN_TxStatus_Pending
+#define CAN_NO_MB CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED CAN_Sleep_Failed
+#define CANSLEEPOK CAN_Sleep_Ok
+#define CANWAKEUPFAILED CAN_WakeUp_Failed
+#define CANWAKEUPOK CAN_WakeUp_Ok
/**
* @}
@@ -542,22 +638,40 @@ typedef struct /** @defgroup CAN_Exported_Functions
* @{
*/
-
+/* Function used to set the CAN configuration to the default reset state *****/
void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* Transmit functions *********************************************************/
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
@@ -580,4 +694,4 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h index 10aaba7b1d..a3f8fc7853 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_cec.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the CEC firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CEC_H
@@ -101,7 +102,7 @@ typedef struct */
-/** @defgroup CEC_Own_Addres
+/** @defgroup CEC_Own_Address
* @{
*/
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
@@ -206,4 +207,4 @@ void CEC_ClearITPendingBit(uint16_t CEC_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h index 12acce09da..658a51cefd 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_crc.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CRC_H
@@ -90,4 +91,4 @@ uint8_t CRC_GetIDRegister(void); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h index 9abd63618a..710616412c 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_dac.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DAC_H
@@ -200,7 +201,7 @@ typedef struct * @}
*/
-/** @defgroup DAC_data_alignement
+/** @defgroup DAC_data_alignment
* @{
*/
@@ -313,4 +314,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h index 918e25fa7a..1e6a68acb4 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_dbgmcu.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the DBGMCU
* firmware library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DBGMCU_H
@@ -115,4 +116,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h index 2c5302b20c..b5dc6a80ab 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_dma.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DMA_H
@@ -413,10 +414,10 @@ void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
-void DMA_ClearFlag(uint32_t DMA_FLAG);
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);
-void DMA_ClearITPendingBit(uint32_t DMA_IT);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
@@ -435,4 +436,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h index 29bed11cf1..a1ab7d03e0 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_exti.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_EXTI_H
@@ -180,4 +181,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h index 5e2047d67e..f46d4e873b 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_flash.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FLASH_H
@@ -422,4 +423,4 @@ FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h index 9cf9847dad..ee707e7439 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_fsmc.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
@@ -76,7 +77,7 @@ typedef struct to the memory before getting the first data.
The value of this parameter depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- - It is don�t care in asynchronous NOR, SRAM or ROM accesses
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between 0 and 0xF in NOR Flash memories
with synchronous burst mode enable */
@@ -729,4 +730,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h index 1d99df02e0..b8aa49a2a8 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_gpio.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_GPIO_H
@@ -195,7 +196,7 @@ typedef enum #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
-#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
to TIM2 Internal Trigger 1 for calibration
(only for Connectivity line devices) */
@@ -381,4 +382,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h index 4726509505..2d42e5ce36 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_i2c.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_I2C_H
@@ -190,6 +191,18 @@ typedef struct * @}
*/
+/** @defgroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACKPosition_Next ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
+ ((POSITION) == I2C_NACKPosition_Current))
+/**
+ * @}
+ */
+
/** @defgroup I2C_interrupts_definition
* @{
*/
@@ -433,7 +446,7 @@ typedef struct * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
* used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of tranfer.
+ * current byte end of transfer.
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
* shall end (before sending the STOP condition). In this case slave has to stop sending
* data bytes and expect a Stop condition on the bus.
@@ -536,6 +549,7 @@ uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
@@ -577,10 +591,10 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); * @note
* For error management, it is advised to use the following functions:
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
- * in order to determine which error occured.
+ * in order to determine which error occurred.
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
* and/or I2C_GenerateStop() in order to clear the error flag and source,
* and return to correct communication status.
@@ -667,4 +681,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h index 4325ad4508..7f5ab7642c 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_iwdg.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IWDG_H
@@ -136,4 +137,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h index ad93abdca4..76e6ce91f9 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_pwr.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_PWR_H
@@ -152,4 +153,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h index 8f1473f921..b3b7d821d7 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_rcc.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the RCC firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RCC_H
@@ -723,4 +724,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h index ac34ca971b..214a5893a0 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_rtc.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RTC_H
@@ -131,4 +132,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h index d15556ce7d..40cfdedc30 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_sdio.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SDIO_H
@@ -189,7 +190,7 @@ typedef struct */
-/** @defgroup SDIO_Interrupt_soucres
+/** @defgroup SDIO_Interrupt_sources
* @{
*/
@@ -527,4 +528,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h index 30b558bee6..6056c4c6ba 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_spi.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SPI_H
@@ -339,7 +340,7 @@ typedef struct * @}
*/
-/** @defgroup SPI_NSS_internal_software_mangement
+/** @defgroup SPI_NSS_internal_software_management
* @{
*/
@@ -483,4 +484,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h index 6529c0b0a7..cd7ac3e9c7 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_tim.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TIM_H
@@ -44,7 +45,7 @@ /**
* @brief TIM Time Base Init structure definition
- * @note This sturcture is used with all TIMx except for TIM6 and TIM7.
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
*/
typedef struct
@@ -132,7 +133,7 @@ typedef struct /**
* @brief BDTR structure definition
- * @note This sturcture is used only with TIM1 and TIM8.
+ * @note This structure is used only with TIM1 and TIM8.
*/
typedef struct
@@ -669,42 +670,42 @@ typedef struct * @{
*/
-#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
- ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_18Bytes))
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
/**
* @}
*/
@@ -866,7 +867,7 @@ typedef struct * @}
*/
-/** @defgroup TIM_Ouput_Compare_Preload_State
+/** @defgroup TIM_Output_Compare_Preload_State
* @{
*/
@@ -878,7 +879,7 @@ typedef struct * @}
*/
-/** @defgroup TIM_Ouput_Compare_Fast_State
+/** @defgroup TIM_Output_Compare_Fast_State
* @{
*/
@@ -891,7 +892,7 @@ typedef struct * @}
*/
-/** @defgroup TIM_Ouput_Compare_Clear_State
+/** @defgroup TIM_Output_Compare_Clear_State
* @{
*/
@@ -1008,6 +1009,32 @@ typedef struct * @}
*/
+/** @defgroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -1134,4 +1161,4 @@ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h index 8d3c3818ab..61ae249a47 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_usart.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_USART_H
@@ -408,4 +409,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h index 859569841c..cd573da445 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h @@ -2,12 +2,12 @@ ******************************************************************************
* @file stm32f10x_wwdg.h
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_WWDG_H
@@ -111,4 +112,4 @@ void WWDG_ClearFlag(void); * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c index 6b72c99a23..ec9165f71f 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c @@ -2,12 +2,12 @@ ******************************************************************************
* @file misc.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -16,8 +16,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "misc.h"
@@ -103,9 +104,9 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) /**
* @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
+ * parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
+ * the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
@@ -148,7 +149,8 @@ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) * This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.
+ * @param Offset: Vector Table base offset field. This value must be a multiple
+ * of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
@@ -220,4 +222,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c index 663b9bb3ac..916a096d4b 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_adc.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the ADC firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_adc.h"
@@ -208,10 +209,10 @@ void ADC_DeInit(ADC_TypeDef* ADCx) /**
* @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
+ * in the ADC_InitStruct.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
+ * the configuration information for the specified ADC peripheral.
* @retval None
*/
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
@@ -379,7 +380,7 @@ void ADC_ResetCalibration(ADC_TypeDef* ADCx) {
/* Check the parameters */
assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Resets the selected ADC calibartion registers */
+ /* Resets the selected ADC calibration registers */
ADCx->CR2 |= CR2_RSTCAL_Set;
}
@@ -499,10 +500,10 @@ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) /**
* @brief Configures the discontinuous mode for the selected ADC regular
- * group channel.
+ * group channel.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param Number: specifies the discontinuous mode regular channel
- * count value. This number must be between 1 and 8.
+ * count value. This number must be between 1 and 8.
* @retval None
*/
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
@@ -525,11 +526,11 @@ void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) /**
* @brief Enables or disables the discontinuous mode on regular group
- * channel for the specified ADC
+ * channel for the specified ADC
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param NewState: new state of the selected ADC discontinuous mode
- * on regular group channel.
- * This parameter can be: ENABLE or DISABLE.
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
@@ -551,7 +552,7 @@ void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) /**
* @brief Configures for the selected ADC regular channel its corresponding
- * rank in the sequencer and its sample time.
+ * rank in the sequencer and its sample time.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_Channel: the ADC channel to configure.
* This parameter can be one of the following values:
@@ -724,7 +725,7 @@ uint32_t ADC_GetDualModeConversionValue(void) /**
* @brief Enables or disables the selected ADC automatic injected group
- * conversion after regular one.
+ * conversion after regular one.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param NewState: new state of the selected ADC auto injected conversion
* This parameter can be: ENABLE or DISABLE.
@@ -749,10 +750,10 @@ void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) /**
* @brief Enables or disables the discontinuous mode for injected group
- * channel for the specified ADC
+ * channel for the specified ADC
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param NewState: new state of the selected ADC discontinuous mode
- * on injected group channel.
+ * on injected group channel.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
@@ -813,10 +814,10 @@ void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_External /**
* @brief Enables or disables the ADCx injected channels conversion through
- * external trigger
+ * external trigger
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param NewState: new state of the selected ADC external trigger start of
- * injected conversion.
+ * injected conversion.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
@@ -839,7 +840,7 @@ void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState /**
* @brief Enables or disables the selected ADC start of the injected
- * channels conversion.
+ * channels conversion.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param NewState: new state of the selected ADC software start injected conversion.
* This parameter can be: ENABLE or DISABLE.
@@ -891,7 +892,7 @@ FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) /**
* @brief Configures for the selected ADC injected channel its corresponding
- * rank in the sequencer and its sample time.
+ * rank in the sequencer and its sample time.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_Channel: the ADC channel to configure.
* This parameter can be one of the following values:
@@ -1065,7 +1066,7 @@ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedC /**
* @brief Enables or disables the analog watchdog on single/all regular
- * or injected channels
+ * or injected channels
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
* This parameter can be one of the following values:
@@ -1270,7 +1271,7 @@ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) }
/**
- * @brief Clears the ADCx�s interrupt pending bits.
+ * @brief Clears the ADCx's interrupt pending bits.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_IT: specifies the ADC interrupt pending bit to clear.
* This parameter can be any combination of the following values:
@@ -1303,4 +1304,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c index 3ad63af35a..3004b9ef80 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_bkp.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the BKP firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_bkp.h"
@@ -304,4 +305,4 @@ void BKP_ClearITPendingBit(void) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c index 043819a6f3..607d6924f7 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_can.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the CAN firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_can.h"
@@ -71,7 +72,14 @@ /* Flags in ESR register */
#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+
+#define CAN_MODE_MASK ((uint32_t) 0x00000003)
/**
* @}
*/
@@ -134,16 +142,18 @@ void CAN_DeInit(CAN_TypeDef* CANx) /**
* @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * parameters in the CAN_InitStruct.
+ * @param CANx: where x can be 1 or 2 to to select the CAN
+ * peripheral.
* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
- * contains the configuration information for the CAN peripheral.
+ * contains the configuration information for the
+ * CAN peripheral.
* @retval Constant indicates initialization succeed which will be
- * CANINITFAILED or CANINITOK.
+ * CAN_InitStatus_Failed or CAN_InitStatus_Success.
*/
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
{
- uint8_t InitStatus = CANINITFAILED;
+ uint8_t InitStatus = CAN_InitStatus_Failed;
uint32_t wait_ack = 0x00000000;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
@@ -159,7 +169,7 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
- /* exit from sleep mode */
+ /* Exit from sleep mode */
CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
/* Request initialisation */
@@ -171,10 +181,10 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) wait_ack++;
}
- /* ...and check acknowledged */
+ /* Check acknowledge */
if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
- InitStatus = CANINITFAILED;
+ InitStatus = CAN_InitStatus_Failed;
}
else
{
@@ -239,15 +249,17 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) }
/* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+ ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
/* Request leave initialisation */
CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
/* Wait the acknowledge */
- wait_ack = 0x00;
+ wait_ack = 0;
while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
{
@@ -257,11 +269,11 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) /* ...and check acknowledged */
if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
- InitStatus = CANINITFAILED;
+ InitStatus = CAN_InitStatus_Failed;
}
else
{
- InitStatus = CANINITOK ;
+ InitStatus = CAN_InitStatus_Success ;
}
}
@@ -271,9 +283,10 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) /**
* @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_FilterInitStruct.
+ * parameters in the CAN_FilterInitStruct.
* @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
- * structure that contains the configuration information.
+ * structure that contains the configuration
+ * information.
* @retval None.
*/
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
@@ -286,7 +299,7 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
- filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;
+ filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
/* Initialisation mode for the filter */
CAN1->FMR |= FMR_FINIT;
@@ -340,13 +353,13 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) }
/* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
{
/* FIFO 0 assignation for the filter */
CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
}
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
{
/* FIFO 1 assignation for the filter */
CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
@@ -365,32 +378,43 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) /**
* @brief Fills each CAN_InitStruct member with its default value.
* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
- * will be initialized.
+ * will be initialized.
* @retval None.
*/
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
{
/* Reset CAN init structure parameters values */
+
/* Initialize the time triggered communication mode */
CAN_InitStruct->CAN_TTCM = DISABLE;
+
/* Initialize the automatic bus-off management */
CAN_InitStruct->CAN_ABOM = DISABLE;
+
/* Initialize the automatic wake-up mode */
CAN_InitStruct->CAN_AWUM = DISABLE;
+
/* Initialize the no automatic retransmission */
CAN_InitStruct->CAN_NART = DISABLE;
+
/* Initialize the receive FIFO locked mode */
CAN_InitStruct->CAN_RFLM = DISABLE;
+
/* Initialize the transmit FIFO priority */
CAN_InitStruct->CAN_TXFP = DISABLE;
+
/* Initialize the CAN_Mode member */
CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+
/* Initialize the CAN_SJW member */
CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+
/* Initialize the CAN_BS1 member */
CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+
/* Initialize the CAN_BS2 member */
CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+
/* Initialize the CAN_Prescaler member */
CAN_InitStruct->CAN_Prescaler = 1;
}
@@ -405,63 +429,88 @@ void CAN_SlaveStartBank(uint8_t CAN_BankNumber) {
/* Check the parameters */
assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
- /* enter Initialisation mode for the filter */
+
+ /* Enter Initialisation mode for the filter */
CAN1->FMR |= FMR_FINIT;
+
/* Select the start slave bank */
CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+
/* Leave Initialisation mode for the filter */
CAN1->FMR &= ~FMR_FINIT;
}
/**
- * @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * -CAN_IT_TME,
- * -CAN_IT_FMP0,
- * -CAN_IT_FF0,
- * -CAN_IT_FOV0,
- * -CAN_IT_FMP1,
- * -CAN_IT_FF1,
- * -CAN_IT_FOV1,
- * -CAN_IT_EWG,
- * -CAN_IT_EPV,
- * -CAN_IT_LEC,
- * -CAN_IT_ERR,
- * -CAN_IT_WKU or
- * -CAN_IT_SLK.
- * @param NewState: new state of the CAN interrupts.
- * This parameter can be: ENABLE or DISABLE.
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState: new state of the CAN peripheral. This parameter can
+ * be: ENABLE or DISABLE.
* @retval None.
*/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
-
+
if (NewState != DISABLE)
{
- /* Enable the selected CANx interrupt */
- CANx->IER |= CAN_IT;
+ /* Enable Debug Freeze */
+ CANx->MCR |= MCR_DBF;
}
else
{
- /* Disable the selected CANx interrupt */
- CANx->IER &= ~CAN_IT;
+ /* Disable Debug Freeze */
+ CANx->MCR &= ~MCR_DBF;
}
}
+
+/**
+ * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState : Mode new state , can be one of @ref FunctionalState.
+ * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ * and TIME[15:8] in data byte 7
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ * @retval None
+ */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCR |= CAN_MCR_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+ }
+}
/**
* @brief Initiates the transmission of a message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param TxMessage: pointer to a structure which contains CAN Id, CAN
- * DLC and CAN datas.
+ * DLC and CAN data.
* @retval The number of the mailbox that is used for transmission
- * or CAN_NO_MB if there is no empty mailbox.
+ * or CAN_TxStatus_NoMailBox if there is no empty mailbox.
*/
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
{
@@ -487,26 +536,27 @@ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) }
else
{
- transmit_mailbox = CAN_NO_MB;
+ transmit_mailbox = CAN_TxStatus_NoMailBox;
}
- if (transmit_mailbox != CAN_NO_MB)
+ if (transmit_mailbox != CAN_TxStatus_NoMailBox)
{
/* Set up the Id */
CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_ID_STD)
+ if (TxMessage->IDE == CAN_Id_Standard)
{
assert_param(IS_CAN_STDID(TxMessage->StdId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+ TxMessage->RTR);
}
else
{
assert_param(IS_CAN_EXTID(TxMessage->ExtId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE |
- TxMessage->RTR);
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+ TxMessage->IDE | \
+ TxMessage->RTR);
}
-
/* Set up the DLC */
TxMessage->DLC &= (uint8_t)0x0000000F;
CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
@@ -529,57 +579,65 @@ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) /**
* @brief Checks the transmission of a message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.
- * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.
+ * @param CANx: where x can be 1 or 2 to to select the
+ * CAN peripheral.
+ * @param TransmitMailbox: the number of the mailbox that is used for
+ * transmission.
+ * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed
+ * in an other case.
*/
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
{
- /* RQCP, TXOK and TME bits */
- uint8_t state = 0;
+ uint32_t state = 0;
+
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
switch (TransmitMailbox)
{
- case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26);
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
break;
- case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27);
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
break;
- case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28);
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
break;
default:
- state = CANTXFAILED;
+ state = CAN_TxStatus_Failed;
break;
}
switch (state)
{
/* transmit pending */
- case (0x0): state = CANTXPENDING;
+ case (0x0): state = CAN_TxStatus_Pending;
break;
/* transmit failed */
- case (0x5): state = CANTXFAILED;
+ case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
break;
- /* transmit succedeed */
- case (0x7): state = CANTXOK;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
break;
- default:
- state = CANTXFAILED;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+ break;
+ default: state = CAN_TxStatus_Failed;
break;
}
- return state;
+ return (uint8_t) state;
}
/**
* @brief Cancels a transmit request.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param Mailbox: Mailbox number.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Mailbox: Mailbox number.
* @retval None.
*/
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
@@ -590,20 +648,72 @@ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) /* abort transmission */
switch (Mailbox)
{
- case (0): CANx->TSR |= CAN_TSR_ABRQ0;
+ case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
break;
- case (1): CANx->TSR |= CAN_TSR_ABRQ1;
+ case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
break;
- case (2): CANx->TSR |= CAN_TSR_ABRQ2;
+ case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
break;
default:
break;
}
}
+
+/**
+ * @brief Receives a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage: pointer to a structure receive message which contains
+ * CAN Id, CAN DLC, CAN datas and FMI number.
+ * @retval None.
+ */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ if (RxMessage->IDE == CAN_Id_Standard)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R |= CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R |= CAN_RF1R_RFOM1;
+ }
+}
+
/**
- * @brief Releases a FIFO.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @brief Releases the specified FIFO.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
* @retval None.
*/
@@ -626,9 +736,9 @@ void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) /**
* @brief Returns the number of pending messages.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval NbMessage which is the number of pending message.
+ * @retval NbMessage : which is the number of pending message.
*/
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
{
@@ -651,81 +761,101 @@ uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) return message_pending;
}
+
/**
- * @brief Receives a message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: pointer to a structure receive message which
- * contains CAN Id, CAN DLC, CAN datas and FMI number.
- * @retval None.
+ * @brief Select the CAN Operation mode.
+ * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one
+ * of @ref CAN_OperatingMode_TypeDef enumeration.
+ * @retval status of the requested mode which can be
+ * - CAN_ModeStatus_Failed CAN failed entering the specific mode
+ * - CAN_ModeStatus_Success CAN Succeed entering the specific mode
+
*/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
{
+ uint8_t status = CAN_ModeStatus_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INAK_TIMEOUT;
+
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Get the Id */
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_ID_STD)
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
{
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+ /* Request initialisation */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
}
- else
+ else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
{
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
- /* Release the FIFO */
- CAN_FIFORelease(CANx, FIFONumber);
-}
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-/**
- * @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: new state of the CAN peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
{
- /* Enable Debug Freeze */
- CANx->MCR |= MCR_DBF;
+ /* Request Sleep mode */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
}
else
{
- /* Disable Debug Freeze */
- CANx->MCR &= ~MCR_DBF;
+ status = CAN_ModeStatus_Failed;
}
+
+ return (uint8_t) status;
}
/**
* @brief Enters the low power mode.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an
+ * other case.
*/
uint8_t CAN_Sleep(CAN_TypeDef* CANx)
{
- uint8_t sleepstatus = CANSLEEPFAILED;
+ uint8_t sleepstatus = CAN_Sleep_Failed;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
@@ -737,21 +867,22 @@ uint8_t CAN_Sleep(CAN_TypeDef* CANx) if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
{
/* Sleep mode not entered */
- sleepstatus = CANSLEEPOK;
+ sleepstatus = CAN_Sleep_Ok;
}
- /* At this step, sleep mode status */
+ /* return sleep mode status */
return (uint8_t)sleepstatus;
}
/**
* @brief Wakes the CAN up.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an
+ * other case.
*/
uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
{
uint32_t wait_slak = SLAK_TIMEOUT;
- uint8_t wakeupstatus = CANWAKEUPFAILED;
+ uint8_t wakeupstatus = CAN_WakeUp_Failed;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
@@ -766,33 +897,147 @@ uint8_t CAN_WakeUp(CAN_TypeDef* CANx) }
if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
{
- /* Sleep mode exited */
- wakeupstatus = CANWAKEUPOK;
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WakeUp_Ok;
}
- /* At this step, sleep mode status */
+ /* return wakeup status */
return (uint8_t)wakeupstatus;
}
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CAN_ErrorCode: specifies the Error code :
+ * - CAN_ERRORCODE_NoErr No Error
+ * - CAN_ERRORCODE_StuffErr Stuff Error
+ * - CAN_ERRORCODE_FormErr Form Error
+ * - CAN_ERRORCODE_ACKErr Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
+ */
+
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+ uint8_t errorcode=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+
+
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * - CAN_IT_TME,
+ * - CAN_IT_FMP0,
+ * - CAN_IT_FF0,
+ * - CAN_IT_FOV0,
+ * - CAN_IT_FMP1,
+ * - CAN_IT_FF1,
+ * - CAN_IT_FOV1,
+ * - CAN_IT_EWG,
+ * - CAN_IT_EPV,
+ * - CAN_IT_LEC,
+ * - CAN_IT_ERR,
+ * - CAN_IT_WKU or
+ * - CAN_IT_SLK.
+ * @param NewState: new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IT(CAN_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->IER |= CAN_IT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->IER &= ~CAN_IT;
+ }
+}
/**
* @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_FLAG: specifies the flag to check.
- * This parameter can be one of the following flags:
- * - CAN_FLAG_EWG
- * - CAN_FLAG_EPV
- * - CAN_FLAG_BOF
- * - CAN_FLAG_RQCP0
- * - CAN_FLAG_RQCP1
- * - CAN_FLAG_RQCP2
- * - CAN_FLAG_FMP1
- * - CAN_FLAG_FF1
- * - CAN_FLAG_FOV1
- * - CAN_FLAG_FMP0
- * - CAN_FLAG_FF0
- * - CAN_FLAG_FOV0
- * - CAN_FLAG_WKU
- * - CAN_FLAG_SLAK
- * - CAN_FLAG_LEC
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_EWG
+ * - CAN_FLAG_EPV
+ * - CAN_FLAG_BOF
+ * - CAN_FLAG_RQCP0
+ * - CAN_FLAG_RQCP1
+ * - CAN_FLAG_RQCP2
+ * - CAN_FLAG_FMP1
+ * - CAN_FLAG_FF1
+ * - CAN_FLAG_FOV1
+ * - CAN_FLAG_FMP0
+ * - CAN_FLAG_FF0
+ * - CAN_FLAG_FOV0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
* @retval The new state of CAN_FLAG (SET or RESET).
*/
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
@@ -880,19 +1125,19 @@ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) /**
* @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_FLAG: specifies the flag to clear.
- * This parameter can be one of the following flags:
- * - CAN_FLAG_RQCP0
- * - CAN_FLAG_RQCP1
- * - CAN_FLAG_RQCP2
- * - CAN_FLAG_FF1
- * - CAN_FLAG_FOV1
- * - CAN_FLAG_FF0
- * - CAN_FLAG_FOV0
- * - CAN_FLAG_WKU
- * - CAN_FLAG_SLAK
- * - CAN_FLAG_LEC
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_RQCP0
+ * - CAN_FLAG_RQCP1
+ * - CAN_FLAG_RQCP2
+ * - CAN_FLAG_FF1
+ * - CAN_FLAG_FOV1
+ * - CAN_FLAG_FF0
+ * - CAN_FLAG_FOV0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
* @retval None.
*/
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
@@ -936,24 +1181,24 @@ void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) /**
* @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt source to check.
- * This parameter can be one of the following flags:
- * - CAN_IT_TME
- * - CAN_IT_FMP0
- * - CAN_IT_FF0
- * - CAN_IT_FOV0
- * - CAN_IT_FMP1
- * - CAN_IT_FF1
- * - CAN_IT_FOV1
- * - CAN_IT_WKU
- * - CAN_IT_SLK
- * - CAN_IT_EWG
- * - CAN_IT_EPV
- * - CAN_IT_BOF
- * - CAN_IT_LEC
- * - CAN_IT_ERR
- * @retval The current state of CAN_IT (SET or RESET).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following flags:
+ * - CAN_IT_TME
+ * - CAN_IT_FMP0
+ * - CAN_IT_FF0
+ * - CAN_IT_FOV0
+ * - CAN_IT_FMP1
+ * - CAN_IT_FF1
+ * - CAN_IT_FOV1
+ * - CAN_IT_WKU
+ * - CAN_IT_SLK
+ * - CAN_IT_EWG
+ * - CAN_IT_EPV
+ * - CAN_IT_BOF
+ * - CAN_IT_LEC
+ * - CAN_IT_ERR
+ * @retval The current state of CAN_IT (SET or RESET).
*/
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
{
@@ -970,60 +1215,59 @@ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) {
case CAN_IT_TME:
/* Check CAN_TSR_RQCPx bits */
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
+ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
break;
case CAN_IT_FMP0:
/* Check CAN_RF0R_FMP0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
break;
case CAN_IT_FF0:
/* Check CAN_RF0R_FULL0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
break;
case CAN_IT_FOV0:
/* Check CAN_RF0R_FOVR0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
break;
case CAN_IT_FMP1:
/* Check CAN_RF1R_FMP1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
break;
case CAN_IT_FF1:
/* Check CAN_RF1R_FULL1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
break;
case CAN_IT_FOV1:
/* Check CAN_RF1R_FOVR1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
break;
case CAN_IT_WKU:
/* Check CAN_MSR_WKUI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
break;
case CAN_IT_SLK:
/* Check CAN_MSR_SLAKI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
break;
case CAN_IT_EWG:
/* Check CAN_ESR_EWGF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
break;
case CAN_IT_EPV:
/* Check CAN_ESR_EPVF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
break;
case CAN_IT_BOF:
/* Check CAN_ESR_BOFF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
break;
case CAN_IT_LEC:
/* Check CAN_ESR_LEC bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
break;
case CAN_IT_ERR:
- /* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC);
- itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
+ /* Check CAN_MSR_ERRI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
break;
default :
/* in case of error, return RESET */
@@ -1042,21 +1286,21 @@ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) }
/**
- * @brief Clears the CANx�s interrupt pending bits.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
* @param CAN_IT: specifies the interrupt pending bit to clear.
- * - CAN_IT_TME
- * - CAN_IT_FF0
- * - CAN_IT_FOV0
- * - CAN_IT_FF1
- * - CAN_IT_FOV1
- * - CAN_IT_WKU
- * - CAN_IT_SLK
- * - CAN_IT_EWG
- * - CAN_IT_EPV
- * - CAN_IT_BOF
- * - CAN_IT_LEC
- * - CAN_IT_ERR
+ * - CAN_IT_TME
+ * - CAN_IT_FF0
+ * - CAN_IT_FOV0
+ * - CAN_IT_FF1
+ * - CAN_IT_FOV1
+ * - CAN_IT_WKU
+ * - CAN_IT_SLK
+ * - CAN_IT_EWG
+ * - CAN_IT_EPV
+ * - CAN_IT_BOF
+ * - CAN_IT_LEC
+ * - CAN_IT_ERR
* @retval None.
*/
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
@@ -1098,17 +1342,20 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) case CAN_IT_EWG:
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
break;
case CAN_IT_EPV:
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
break;
case CAN_IT_BOF:
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
break;
case CAN_IT_LEC:
/* Clear LEC bits */
@@ -1121,7 +1368,8 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) CANx->ESR = RESET;
/* Clear CAN_MSR_ERRI (rc_w1) */
CANx->MSR = CAN_MSR_ERRI;
- /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+ of the CAN Bus status*/
break;
default :
break;
@@ -1131,7 +1379,7 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) /**
* @brief Checks whether the CAN interrupt has occurred or not.
* @param CAN_Reg: specifies the CAN interrupt register to check.
- * @param It_Bit: specifies the interrupt source bit to check.
+ * @param It_Bit: specifies the interrupt source bit to check.
* @retval The new state of the CAN Interrupt (SET or RESET).
*/
static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
@@ -1151,6 +1399,7 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) return pendingbitstatus;
}
+
/**
* @}
*/
@@ -1163,4 +1412,4 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c index 5b3f9b5138..08b501a0c4 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_cec.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the CEC firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_cec.h"
@@ -277,7 +278,7 @@ void CEC_EndOfMessageCmd(FunctionalState NewState) * @arg CEC_FLAG_SBE: Start Bit Error
* @arg CEC_FLAG_ACKE: Block Acknowledge Error
* @arg CEC_FLAG_LINE: Line Error
- * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error
+ * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
* @arg CEC_FLAG_TEOM: Tx End Of Message
* @arg CEC_FLAG_TERR: Tx Error
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
@@ -429,4 +430,4 @@ void CEC_ClearITPendingBit(uint16_t CEC_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c index 511a7b90e8..ef0c047d8f 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_crc.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the CRC firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_crc.h"
@@ -156,4 +157,4 @@ uint8_t CRC_GetIDRegister(void) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c index 55e91c0a79..025b8e2837 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_dac.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the DAC firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dac.h"
@@ -104,13 +105,13 @@ void DAC_DeInit(void) /**
* @brief Initializes the DAC peripheral according to the specified
- * parameters in the DAC_InitStruct.
+ * parameters in the DAC_InitStruct.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
- * contains the configuration information for the specified DAC channel.
+ * contains the configuration information for the specified DAC channel.
* @retval None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
@@ -126,8 +127,8 @@ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
- mask/amplitude for wave genration */
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
@@ -143,7 +144,7 @@ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) /**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
- * be initialized.
+ * be initialized.
* @retval None
*/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
@@ -330,11 +331,11 @@ void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalSt /**
* @brief Set the specified data holding register value for DAC channel1.
- * @param DAC_Align: Specifies the data alignement for DAC channel1.
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignement selected
- * @arg DAC_Align_12b_L: 12bit left data alignement selected
- * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
@@ -355,11 +356,11 @@ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) /**
* @brief Set the specified data holding register value for DAC channel2.
- * @param DAC_Align: Specifies the data alignement for DAC channel2.
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignement selected
- * @arg DAC_Align_12b_L: 12bit left data alignement selected
- * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
@@ -381,11 +382,11 @@ void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) /**
* @brief Set the specified data holding register value for dual channel
* DAC.
- * @param DAC_Align: Specifies the data alignement for dual channel DAC.
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignement selected
- * @arg DAC_Align_12b_L: 12bit left data alignement selected
- * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
@@ -419,7 +420,7 @@ void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) }
/**
- * @brief Returns the last data output value of the selected DAC cahnnel.
+ * @brief Returns the last data output value of the selected DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
@@ -534,7 +535,7 @@ ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) }
/**
- * @brief Clears the DAC channelx�s interrupt pending bits.
+ * @brief Clears the DAC channelx's interrupt pending bits.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
@@ -567,4 +568,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c index 3f4e627270..d34307b058 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_dbgmcu.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dbgmcu.h"
@@ -158,4 +159,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c index 7f72b54cfc..0c86f9018b 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_dma.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the DMA firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dma.h"
@@ -99,7 +100,7 @@ /**
* @brief Deinitializes the DMAy Channelx registers to their default reset
- * values.
+ * values.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval None
@@ -191,11 +192,11 @@ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) /**
* @brief Initializes the DMAy Channelx according to the specified
- * parameters in the DMA_InitStruct.
+ * parameters in the DMA_InitStruct.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
- * contains the configuration information for the specified DMA Channel.
+ * contains the configuration information for the specified DMA Channel.
* @retval None
*/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
@@ -252,7 +253,7 @@ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruc /**
* @brief Fills each DMA_InitStruct member with its default value.
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
- * be initialized.
+ * be initialized.
* @retval None
*/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
@@ -361,11 +362,11 @@ void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNum /**
* @brief Returns the number of remaining data units in the current
- * DMAy Channelx transfer.
+ * DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval The number of remaining data units in the current DMAy Channelx
- * transfer.
+ * transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
@@ -377,7 +378,7 @@ uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) /**
* @brief Checks whether the specified DMAy Channelx flag is set or not.
- * @param DMA_FLAG: specifies the flag to check.
+ * @param DMAy_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
@@ -427,17 +428,18 @@ uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
- * @retval The new state of DMA_FLAG (SET or RESET).
+ * @retval The new state of DMAy_FLAG (SET or RESET).
*/
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
+
/* Check the parameters */
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
+ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
- /* Calculate the used DMA */
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR ;
@@ -448,25 +450,25 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) tmpreg = DMA1->ISR ;
}
- /* Check the status of the specified DMA flag */
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
+ /* Check the status of the specified DMAy flag */
+ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
- /* DMA_FLAG is set */
+ /* DMAy_FLAG is set */
bitstatus = SET;
}
else
{
- /* DMA_FLAG is reset */
+ /* DMAy_FLAG is reset */
bitstatus = RESET;
}
- /* Return the DMA_FLAG status */
+ /* Return the DMAy_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's pending flags.
- * @param DMA_FLAG: specifies the flag to clear.
+ * @param DMAy_FLAG: specifies the flag to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
@@ -518,27 +520,27 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* @retval None
*/
-void DMA_ClearFlag(uint32_t DMA_FLAG)
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
/* Check the parameters */
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
- /* Calculate the used DMA */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
- /* Clear the selected DMA flags */
- DMA2->IFCR = DMA_FLAG;
+ /* Clear the selected DMAy flags */
+ DMA2->IFCR = DMAy_FLAG;
}
else
{
- /* Clear the selected DMA flags */
- DMA1->IFCR = DMA_FLAG;
+ /* Clear the selected DMAy flags */
+ DMA1->IFCR = DMAy_FLAG;
}
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
- * @param DMA_IT: specifies the DMA interrupt source to check.
+ * @param DMAy_IT: specifies the DMAy interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
@@ -588,36 +590,37 @@ void DMA_ClearFlag(uint32_t DMA_FLAG) * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
- * @retval The new state of DMA_IT (SET or RESET).
+ * @retval The new state of DMAy_IT (SET or RESET).
*/
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
+
/* Check the parameters */
- assert_param(IS_DMA_GET_IT(DMA_IT));
+ assert_param(IS_DMA_GET_IT(DMAy_IT));
/* Calculate the used DMA */
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
- tmpreg = DMA2->ISR ;
+ tmpreg = DMA2->ISR;
}
else
{
/* Get DMA1 ISR register value */
- tmpreg = DMA1->ISR ;
+ tmpreg = DMA1->ISR;
}
- /* Check the status of the specified DMA interrupt */
- if ((tmpreg & DMA_IT) != (uint32_t)RESET)
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
- /* DMA_IT is set */
+ /* DMAy_IT is set */
bitstatus = SET;
}
else
{
- /* DMA_IT is reset */
+ /* DMAy_IT is reset */
bitstatus = RESET;
}
/* Return the DMA_IT status */
@@ -625,8 +628,8 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT) }
/**
- * @brief Clears the DMAy Channelx�s interrupt pending bits.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
+ * @brief Clears the DMAy Channelx's interrupt pending bits.
+ * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
@@ -678,21 +681,21 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT) * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* @retval None
*/
-void DMA_ClearITPendingBit(uint32_t DMA_IT)
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
/* Check the parameters */
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
+ assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
- /* Calculate the used DMA */
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
+ /* Calculate the used DMAy */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
- /* Clear the selected DMA interrupt pending bits */
- DMA2->IFCR = DMA_IT;
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA2->IFCR = DMAy_IT;
}
else
{
- /* Clear the selected DMA interrupt pending bits */
- DMA1->IFCR = DMA_IT;
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA1->IFCR = DMAy_IT;
}
}
@@ -708,4 +711,4 @@ void DMA_ClearITPendingBit(uint32_t DMA_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c index f9467d0dc4..ab7346276c 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_exti.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the EXTI firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_exti.h"
@@ -92,9 +93,9 @@ void EXTI_DeInit(void) /**
* @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
+ * parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
- * that contains the configuration information for the EXTI peripheral.
+ * that contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
@@ -150,7 +151,7 @@ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) /**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
+ * be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
@@ -200,7 +201,7 @@ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) }
/**
- * @brief Clears the EXTI�s line pending flags.
+ * @brief Clears the EXTI's line pending flags.
* @param EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
@@ -240,7 +241,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) }
/**
- * @brief Clears the EXTI�s line pending bits.
+ * @brief Clears the EXTI's line pending bits.
* @param EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
@@ -265,4 +266,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c index 57bb715c85..f6c7bf172d 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_flash.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the FLASH firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_flash.h"
@@ -413,7 +414,7 @@ void FLASH_LockBank2(void) * @note This function can be used for all STM32F10x devices.
* @param Page_Address: The page address to be erased.
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
{
@@ -486,7 +487,7 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address) * @note This function can be used for all STM32F10x devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllPages(void)
{
@@ -549,7 +550,7 @@ FLASH_Status FLASH_EraseAllPages(void) * to FLASH_EraseAllPages function.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllBank1Pages(void)
{
@@ -579,7 +580,7 @@ FLASH_Status FLASH_EraseAllBank1Pages(void) * @note This function can be used only for STM32F10x_XL density devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllBank2Pages(void)
{
@@ -610,7 +611,7 @@ FLASH_Status FLASH_EraseAllBank2Pages(void) * @note This function can be used for all STM32F10x devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseOptionBytes(void)
{
@@ -675,7 +676,7 @@ FLASH_Status FLASH_EraseOptionBytes(void) * @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
{
@@ -852,7 +853,7 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) * @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
{
@@ -923,7 +924,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) * This parameter can be 0x1FFFF804 or 0x1FFFF806.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
{
@@ -969,7 +970,7 @@ FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
* @arg FLASH_WRProt_AllPages
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
{
@@ -1043,7 +1044,7 @@ FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) * @param Newstate: new state of the ReadOut Protection.
* This parameter can be: ENABLE or DISABLE.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
{
@@ -1112,7 +1113,7 @@ FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
{
@@ -1166,7 +1167,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint * in the interrupt vector table).
* For more information, please refer to AN2606 from www.st.com.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
{
@@ -1210,7 +1211,7 @@ FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) * @note This function can be used for all STM32F10x devices.
* @param None
* @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
+ * and RST_STDBY(Bit2).
*/
uint32_t FLASH_GetUserOptionByte(void)
{
@@ -1226,7 +1227,7 @@ uint32_t FLASH_GetUserOptionByte(void) */
uint32_t FLASH_GetWriteProtectionOptionByte(void)
{
- /* Return the Falsh write protection Register value */
+ /* Return the Flash write protection Register value */
return (uint32_t)(FLASH->WRPR);
}
@@ -1428,7 +1429,7 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) }
/**
- * @brief Clears the FLASH�s pending flags.
+ * @brief Clears the FLASH's pending flags.
* @note This function can be used for all STM32F10x devices.
* - For STM32F10X_XL devices, this function clears Bank1 or Bank2�s pending flags
* - For other devices, it clears Bank1�s pending flags.
@@ -1468,10 +1469,10 @@ void FLASH_ClearFlag(uint32_t FLASH_FLAG) /**
* @brief Returns the FLASH Status.
* @note This function can be used for all STM32F10x devices, it is equivalent
- * to FLASH_GetBank1Status function.
+ * to FLASH_GetBank1Status function.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
*/
FLASH_Status FLASH_GetStatus(void)
{
@@ -1506,10 +1507,10 @@ FLASH_Status FLASH_GetStatus(void) /**
* @brief Returns the FLASH Bank1 Status.
* @note This function can be used for all STM32F10x devices, it is equivalent
- * to FLASH_GetStatus function.
+ * to FLASH_GetStatus function.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
*/
FLASH_Status FLASH_GetBank1Status(void)
{
@@ -1547,7 +1548,7 @@ FLASH_Status FLASH_GetBank1Status(void) * @note This function can be used for STM32F10x_XL density devices.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
*/
FLASH_Status FLASH_GetBank2Status(void)
{
@@ -1587,9 +1588,9 @@ FLASH_Status FLASH_GetBank2Status(void) * to complete or a TIMEOUT to occur.
* - For all other devices it waits for a Flash operation to complete
* or a TIMEOUT to occur.
- * @param Timeout: FLASH progamming Timeout
+ * @param Timeout: FLASH programming Timeout
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
{
@@ -1615,9 +1616,9 @@ FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
* @note This function can be used for all STM32F10x devices,
* it is equivalent to FLASH_WaitForLastOperation.
- * @param Timeout: FLASH progamming Timeout
+ * @param Timeout: FLASH programming Timeout
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
{
@@ -1643,9 +1644,9 @@ FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) /**
* @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
* @note This function can be used only for STM32F10x_XL density devices.
- * @param Timeout: FLASH progamming Timeout
+ * @param Timeout: FLASH programming Timeout
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
{
@@ -1680,4 +1681,4 @@ FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c index db9a5aad11..c75137cacb 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_fsmc.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the FSMC firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_fsmc.h"
@@ -89,7 +90,7 @@ /**
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
- * reset values.
+ * reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
@@ -166,10 +167,10 @@ void FSMC_PCCARDDeInit(void) /**
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
- * parameters in the FSMC_NORSRAMInitStruct.
+ * parameters in the FSMC_NORSRAMInitStruct.
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
- * structure that contains the configuration information for
- * the FSMC NOR/SRAM specified Banks.
+ * structure that contains the configuration information for
+ * the FSMC NOR/SRAM specified Banks.
* @retval None
*/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
@@ -252,9 +253,10 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) /**
* @brief Initializes the FSMC NAND Banks according to the specified
- * parameters in the FSMC_NANDInitStruct.
+ * parameters in the FSMC_NANDInitStruct.
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
- * structure that contains the configuration information for the FSMC NAND specified Banks.
+ * structure that contains the configuration information for the FSMC
+ * NAND specified Banks.
* @retval None
*/
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
@@ -317,9 +319,10 @@ void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) /**
* @brief Initializes the FSMC PCCARD Bank according to the specified
- * parameters in the FSMC_PCCARDInitStruct.
+ * parameters in the FSMC_PCCARDInitStruct.
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
- * structure that contains the configuration information for the FSMC PCCARD Bank.
+ * structure that contains the configuration information for the FSMC
+ * PCCARD Bank.
* @retval None
*/
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
@@ -371,7 +374,7 @@ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) /**
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
- * structure which will be initialized.
+ * structure which will be initialized.
* @retval None
*/
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
@@ -409,7 +412,7 @@ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) /**
* @brief Fills each FSMC_NANDInitStruct member with its default value.
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
- * structure which will be initialized.
+ * structure which will be initialized.
* @retval None
*/
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
@@ -435,7 +438,7 @@ void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) /**
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
- * structure which will be initialized.
+ * structure which will be initialized.
* @retval None
*/
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
@@ -728,7 +731,7 @@ FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) }
/**
- * @brief Clears the FSMC�s pending flags.
+ * @brief Clears the FSMC's pending flags.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
@@ -814,7 +817,7 @@ ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) }
/**
- * @brief Clears the FSMC�s interrupt pending bits.
+ * @brief Clears the FSMC's interrupt pending bits.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
@@ -860,4 +863,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c index 4ec05094ed..93dbcd7caf 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_gpio.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the GPIO firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_gpio.h"
@@ -163,10 +164,10 @@ void GPIO_AFIODeInit(void) /**
* @brief Initializes the GPIOx peripheral according to the specified
- * parameters in the GPIO_InitStruct.
+ * parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
- * contains the configuration information for the specified GPIO peripheral.
+ * contains the configuration information for the specified GPIO peripheral.
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
@@ -259,7 +260,7 @@ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) /**
* @brief Fills each GPIO_InitStruct member with its default value.
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
- * be initialized.
+ * be initialized.
* @retval None
*/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
@@ -519,6 +520,8 @@ void GPIO_EventOutputCmd(FunctionalState NewState) * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
+ * When the SPI3/I2S3 is remapped using this function, the SWJ is configured
+ * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
@@ -644,4 +647,4 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c index 5a2521c2ca..889672683f 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_i2c.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the I2C firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_i2c.h"
@@ -672,6 +673,46 @@ void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) }
/**
+ * @brief Selects the specified I2C NACK position in master receiver mode.
+ * This function is useful in I2C Master Receiver mode when the number
+ * of data to be received is equal to 2. In this case, this function
+ * should be called (with parameter I2C_NACKPosition_Next) before data
+ * reception starts,as described in the 2-byte reception procedure
+ * recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition: specifies the NACK position.
+ * This parameter can be one of the following values:
+ * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+ * received byte.
+ * @arg I2C_NACKPosition_Current: indicates that current byte is the last
+ * received byte.
+ *
+ * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
+ * but is intended to be used in I2C mode while I2C_PECPositionConfig()
+ * is intended to used in SMBUS mode.
+ *
+ * @retval None
+ */
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+
+ /* Check the input parameter */
+ if (I2C_NACKPosition == I2C_NACKPosition_Next)
+ {
+ /* Next byte in shift register is the last received byte */
+ I2Cx->CR1 |= I2C_NACKPosition_Next;
+ }
+ else
+ {
+ /* Current byte in shift register is the last received byte */
+ I2Cx->CR1 &= I2C_NACKPosition_Current;
+ }
+}
+
+/**
* @brief Drives the SMBusAlert pin high or low for the specified I2C.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_SMBusAlert: specifies SMBAlert pin level.
@@ -728,6 +769,11 @@ void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) * This parameter can be one of the following values:
* @arg I2C_PECPosition_Next: indicates that the next byte is PEC
* @arg I2C_PECPosition_Current: indicates that current byte is PEC
+ *
+ * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
+ * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
+ * is intended to used in I2C mode.
+ *
* @retval None
*/
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
@@ -748,7 +794,7 @@ void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) }
/**
- * @brief Enables or disables the PEC value calculation of the transfered bytes.
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param NewState: new state of the I2Cx PEC value calculation.
* This parameter can be: ENABLE or DISABLE.
@@ -878,7 +924,7 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * It returns SUCCESS if the current status includes the given flags
* and returns ERROR if one or more flags are missing in the current status.
* - When to use:
- * - This function is suitable for most applciations as well as for startup
+ * - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (RM0008).
* - It is also suitable for users who need to define their own events.
@@ -892,7 +938,7 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * @note
* For error management, it is advised to use the following functions:
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
* in order to determine which error occured.
@@ -907,9 +953,9 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * by 16 bits and concatenated to Status Register 1).
* - When to use:
* - This function is suitable for the same applications above but it allows to
- * overcome the mentionned limitation of I2C_GetFlagStatus() function.
+ * overcome the mentioned limitation of I2C_GetFlagStatus() function.
* The returned value could be compared to events already defined in the
- * library (stm32f10x_i2c.h) or to custom values defiend by user.
+ * library (stm32f10x_i2c.h) or to custom values defined by user.
* - This function is suitable when multiple flags are monitored at the same time.
* - At the opposite of I2C_CheckEvent() function, this function allows user to
* choose when an event is accepted (when all events flags are set and no
@@ -977,7 +1023,7 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) * @note: For detailed description of Events, please refer to section
* I2C_Events in stm32f10x_i2c.h file.
*
- * @retval An ErrorStatus enumuration value:
+ * @retval An ErrorStatus enumeration value:
* - SUCCESS: Last event is equal to the I2C_EVENT
* - ERROR: Last event is different from the I2C_EVENT
*/
@@ -1079,8 +1125,8 @@ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
* @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
* @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) �ADSL�
- * Address matched flag (Slave mode)�ENDAD�
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDA"
* @arg I2C_FLAG_SB: Start bit flag (Master mode)
* @retval The new state of I2C_FLAG (SET or RESET).
*/
@@ -1192,8 +1238,8 @@ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
* @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
* @arg I2C_IT_BTF: Byte transfer finished flag
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) �ADSL�
- * Address matched flag (Slave mode)�ENDAD�
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDAD"
* @arg I2C_IT_SB: Start bit flag (Master mode)
* @retval The new state of I2C_IT (SET or RESET).
*/
@@ -1282,4 +1328,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c index 7738cf3c48..9d3b0e855a 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_iwdg.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the IWDG firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_iwdg.h"
@@ -186,4 +187,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c index 8eeeec200e..147bf0f8d6 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_pwr.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the PWR firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_pwr.h"
@@ -303,4 +304,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c index 9a0b7ca1e0..4b2ec1f104 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_rcc.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the RCC firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_rcc.h"
@@ -867,7 +868,7 @@ void RCC_LSICmd(FunctionalState NewState) /**
* @brief Configures the RTC clock (RTCCLK).
- * @note Once the RTC clock is selected it can�t be changed unless the Backup domain is reset.
+ * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
* @param RCC_RTCCLKSource: specifies the RTC clock source.
* This parameter can be one of the following values:
* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
@@ -1419,7 +1420,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT) }
/**
- * @brief Clears the RCC�s interrupt pending bits.
+ * @brief Clears the RCC's interrupt pending bits.
* @param RCC_IT: specifies the interrupt pending bit to clear.
*
* For @b STM32_Connectivity_line_devices, this parameter can be any combination
@@ -1466,4 +1467,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c index dc69f64bf1..f798d2bd6f 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_rtc.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the RTC firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_rtc.h"
@@ -259,7 +260,7 @@ FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) }
/**
- * @brief Clears the RTC�s pending flags.
+ * @brief Clears the RTC's pending flags.
* @param RTC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
@@ -274,12 +275,12 @@ void RTC_ClearFlag(uint16_t RTC_FLAG) /* Check the parameters */
assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
- /* Clear the coressponding RTC flag */
+ /* Clear the corresponding RTC flag */
RTC->CRL &= (uint16_t)~RTC_FLAG;
}
/**
- * @brief Checks whether the specified RTC interrupt has occured or not.
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
* @param RTC_IT: specifies the RTC interrupts sources to check.
* This parameter can be one of the following values:
* @arg RTC_IT_OW: Overflow interrupt
@@ -306,7 +307,7 @@ ITStatus RTC_GetITStatus(uint16_t RTC_IT) }
/**
- * @brief Clears the RTC�s interrupt pending bits.
+ * @brief Clears the RTC's interrupt pending bits.
* @param RTC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg RTC_IT_OW: Overflow interrupt
@@ -319,7 +320,7 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT) /* Check the parameters */
assert_param(IS_RTC_IT(RTC_IT));
- /* Clear the coressponding RTC pending bit */
+ /* Clear the corresponding RTC pending bit */
RTC->CRL &= (uint16_t)~RTC_IT;
}
@@ -335,4 +336,4 @@ void RTC_ClearITPendingBit(uint16_t RTC_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c index 732cad53b3..d1870cef15 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_sdio.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the SDIO firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_sdio.h"
@@ -172,9 +173,9 @@ void SDIO_DeInit(void) /**
* @brief Initializes the SDIO peripheral according to the specified
- * parameters in the SDIO_InitStruct.
+ * parameters in the SDIO_InitStruct.
* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
- * that contains the configuration information for the SDIO peripheral.
+ * that contains the configuration information for the SDIO peripheral.
* @retval None
*/
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
@@ -337,9 +338,9 @@ void SDIO_DMACmd(FunctionalState NewState) /**
* @brief Initializes the SDIO Command according to the specified
- * parameters in the SDIO_CmdInitStruct and send the command.
+ * parameters in the SDIO_CmdInitStruct and send the command.
* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
- * structure that contains the configuration information for the SDIO command.
+ * structure that contains the configuration information for the SDIO command.
* @retval None
*/
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
@@ -375,7 +376,7 @@ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) /**
* @brief Fills each SDIO_CmdInitStruct member with its default value.
* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
- * structure which will be initialized.
+ * structure which will be initialized.
* @retval None
*/
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
@@ -465,7 +466,7 @@ void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) /**
* @brief Fills each SDIO_DataInitStruct member with its default value.
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
- * will be initialized.
+ * will be initialized.
* @retval None
*/
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
@@ -550,7 +551,7 @@ void SDIO_StopSDIOReadWait(FunctionalState NewState) /**
* @brief Sets one of the two options of inserting read wait interval.
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
- * This parametre can be:
+ * This parameter can be:
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
* @retval None
@@ -757,7 +758,7 @@ ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) }
/**
- * @brief Clears the SDIO�s interrupt pending bits.
+ * @brief Clears the SDIO's interrupt pending bits.
* @param SDIO_IT: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -795,4 +796,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c index badd23d662..51a9cce773 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_spi.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the SPI firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_spi.h"
@@ -111,7 +112,7 @@ /**
* @brief Deinitializes the SPIx peripheral registers to their default
- * reset values (Affects also the I2Ss).
+ * reset values (Affects also the I2Ss).
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @retval None
*/
@@ -148,10 +149,10 @@ void SPI_I2S_DeInit(SPI_TypeDef* SPIx) /**
* @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
+ * parameters in the SPI_InitStruct.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
+ * contains the configuration information for the specified SPI peripheral.
* @retval None
*/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
@@ -202,12 +203,12 @@ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) /**
* @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
+ * parameters in the I2S_InitStruct.
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral
- * (configured in I2S mode).
+ * (configured in I2S mode).
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
* @note
* The function calculates the optimal prescaler needed to obtain the most
* accurate audio frequency (depending on the I2S clock source, the PLL values
@@ -283,7 +284,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) /* Get the value of the PLL3 multiplier */
if((tmp > 5) && (tmp < 15))
{
- /* Multplier is between 8 and 14 (value 15 is forbidden) */
+ /* Multiplier is between 8 and 14 (value 15 is forbidden) */
tmp += 2;
}
else
@@ -316,7 +317,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) sourceclock = RCC_Clocks.SYSCLK_Frequency;
#endif /* STM32F10X_CL */
- /* Compute the Real divider depending on the MCLK output state with a flaoting point */
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
{
/* MCLK output is enabled */
@@ -328,7 +329,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
}
- /* Remove the flaoting point */
+ /* Remove the floating point */
tmp = tmp / 10;
/* Check the parity of the divider */
@@ -653,7 +654,7 @@ void SPI_TransmitCRC(SPI_TypeDef* SPIx) }
/**
- * @brief Enables or disables the CRC value calculation of the transfered bytes.
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param NewState: new state of the SPIx CRC value calculation.
* This parameter can be: ENABLE or DISABLE.
@@ -866,7 +867,7 @@ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) * @param SPIx: where x can be
* - 1, 2 or 3 in SPI mode
* @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR intetrrupt pending bit.
+ * This function clears only CRCERR interrupt pending bit.
* @note
* - OVR (OverRun Error) interrupt pending bit is cleared by software
* sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
@@ -904,4 +905,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c index 780105589a..81c8484e39 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_tim.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the TIM firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_tim.h"
@@ -215,10 +216,11 @@ void TIM_DeInit(TIM_TypeDef* TIMx) /**
* @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
+ * the specified parameters in the TIM_TimeBaseInitStruct.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
- * structure that contains the configuration information for the specified TIM peripheral.
+ * structure that contains the configuration information for the
+ * specified TIM peripheral.
* @retval None
*/
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
@@ -268,10 +270,10 @@ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseIn /**
* @brief Initializes the TIMx Channel1 according to the specified
- * parameters in the TIM_OCInitStruct.
+ * parameters in the TIM_OCInitStruct.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
+ * that contains the configuration information for the specified TIM peripheral.
* @retval None
*/
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
@@ -326,7 +328,7 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output N State */
tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
- /* Reset the Ouput Compare and Output Compare N IDLE State */
+ /* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
@@ -350,11 +352,11 @@ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /**
* @brief Initializes the TIMx Channel2 according to the specified
- * parameters in the TIM_OCInitStruct.
+ * parameters in the TIM_OCInitStruct.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
+ * the TIM peripheral.
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
+ * that contains the configuration information for the specified TIM peripheral.
* @retval None
*/
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
@@ -409,7 +411,7 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output N State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
- /* Reset the Ouput Compare and Output Compare N IDLE State */
+ /* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
@@ -433,10 +435,10 @@ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /**
* @brief Initializes the TIMx Channel3 according to the specified
- * parameters in the TIM_OCInitStruct.
+ * parameters in the TIM_OCInitStruct.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
+ * that contains the configuration information for the specified TIM peripheral.
* @retval None
*/
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
@@ -489,7 +491,7 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /* Set the Output N State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Ouput Compare and Output Compare N IDLE State */
+ /* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
/* Set the Output Idle state */
@@ -512,10 +514,10 @@ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /**
* @brief Initializes the TIMx Channel4 according to the specified
- * parameters in the TIM_OCInitStruct.
+ * parameters in the TIM_OCInitStruct.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
+ * that contains the configuration information for the specified TIM peripheral.
* @retval None
*/
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
@@ -556,7 +558,7 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) if((TIMx == TIM1) || (TIMx == TIM8))
{
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Ouput Compare IDLE State */
+ /* Reset the Output Compare IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
/* Set the Output Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
@@ -576,10 +578,10 @@ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) /**
* @brief Initializes the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct.
+ * parameters in the TIM_ICInitStruct.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
+ * that contains the configuration information for the specified TIM peripheral.
* @retval None
*/
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
@@ -643,10 +645,10 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) /**
* @brief Configures the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
+ * that contains the configuration information for the specified TIM peripheral.
* @retval None
*/
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
@@ -701,10 +703,10 @@ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) /**
* @brief Configures the: Break feature, dead time, Lock level, the OSSI,
- * the OSSR State and the AOE(automatic output enable).
+ * the OSSR State and the AOE(automatic output enable).
* @param TIMx: where x can be 1 or 8 to select the TIM
* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
+ * contains the BDTR Register configuration information for the TIM peripheral.
* @retval None
*/
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
@@ -728,7 +730,7 @@ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) /**
* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
+ * structure which will be initialized.
* @retval None
*/
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
@@ -744,7 +746,7 @@ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) /**
* @brief Fills each TIM_OCInitStruct member with its default value.
* @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
+ * be initialized.
* @retval None
*/
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
@@ -762,8 +764,8 @@ void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) /**
* @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+ * be initialized.
* @retval None
*/
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
@@ -779,7 +781,7 @@ void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) /**
* @brief Fills each TIM_BDTRInitStruct member with its default value.
* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
+ * will be initialized.
* @retval None
*/
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
@@ -915,21 +917,21 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) }
/**
- * @brief Configures the TIMx�s DMA interface.
+ * @brief Configures the TIMx's DMA interface.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
* the TIM peripheral.
* @param TIM_DMABase: DMA Base address.
* This parameter can be one of the following values:
* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
- * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
- * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
- * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
- * TIM_DMABase_DCR.
+ * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+ * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+ * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+ * TIM_DMABase_DCR.
* @param TIM_DMABurstLength: DMA Burst length.
* This parameter can be one value between:
- * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
+ * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
* @retval None
*/
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
@@ -943,7 +945,7 @@ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurs }
/**
- * @brief Enables or disables the TIMx�s DMA Requests.
+ * @brief Enables or disables the TIMx's DMA Requests.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
* to select the TIM peripheral.
* @param TIM_DMASource: specifies the DMA Request sources.
@@ -979,9 +981,9 @@ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewSt }
/**
- * @brief Configures the TIMx interrnal Clock
+ * @brief Configures the TIMx internal Clock
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
- * to select the TIM peripheral.
+ * to select the TIM peripheral.
* @retval None
*/
void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
@@ -1250,11 +1252,11 @@ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
* on the level of the other input.
* @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_ICPolarity_Falling: IC Falling edge.
* @arg TIM_ICPolarity_Rising: IC Rising edge.
* @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_ICPolarity_Falling: IC Falling edge.
* @arg TIM_ICPolarity_Rising: IC Rising edge.
* @retval None
@@ -1448,7 +1450,7 @@ void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) /**
* @brief Selects the TIMx peripheral Capture Compare DMA source.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
- * the TIM peripheral.
+ * the TIM peripheral.
* @param NewState: new state of the Capture Compare DMA source
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1473,7 +1475,7 @@ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) /**
* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
- * to select the TIMx peripheral
+ * to select the TIMx peripheral
* @param NewState: new state of the Capture Compare Preload Control bit
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1522,7 +1524,7 @@ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) /**
* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
+ * the TIM peripheral.
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
* This parameter can be one of the following values:
* @arg TIM_OCPreload_Enable
@@ -1620,7 +1622,7 @@ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) /**
* @brief Configures the TIMx Output Compare 2 Fast feature.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
+ * the TIM peripheral.
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
* This parameter can be one of the following values:
* @arg TIM_OCFast_Enable: TIM output compare fast enable
@@ -1795,7 +1797,7 @@ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) * @brief Configures the TIMx channel 1 polarity.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCPolarity_High: Output Compare active high
* @arg TIM_OCPolarity_Low: Output Compare active low
* @retval None
@@ -1818,7 +1820,7 @@ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Configures the TIMx Channel 1N polarity.
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
* @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCNPolarity_High: Output Compare active high
* @arg TIM_OCNPolarity_Low: Output Compare active low
* @retval None
@@ -1842,7 +1844,7 @@ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) * @brief Configures the TIMx channel 2 polarity.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCPolarity_High: Output Compare active high
* @arg TIM_OCPolarity_Low: Output Compare active low
* @retval None
@@ -1865,7 +1867,7 @@ void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Configures the TIMx Channel 2N polarity.
* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
* @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCNPolarity_High: Output Compare active high
* @arg TIM_OCNPolarity_Low: Output Compare active low
* @retval None
@@ -1889,7 +1891,7 @@ void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) * @brief Configures the TIMx channel 3 polarity.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCPolarity_High: Output Compare active high
* @arg TIM_OCPolarity_Low: Output Compare active low
* @retval None
@@ -1912,7 +1914,7 @@ void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Configures the TIMx Channel 3N polarity.
* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
* @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCNPolarity_High: Output Compare active high
* @arg TIM_OCNPolarity_Low: Output Compare active low
* @retval None
@@ -1937,7 +1939,7 @@ void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) * @brief Configures the TIMx channel 4 polarity.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCPolarity_High: Output Compare active high
* @arg TIM_OCPolarity_Low: Output Compare active low
* @retval None
@@ -1960,7 +1962,7 @@ void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) * @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
* @arg TIM_Channel_2: TIM Channel 2
* @arg TIM_Channel_3: TIM Channel 3
@@ -1991,7 +1993,7 @@ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) * @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
* @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
* @arg TIM_Channel_2: TIM Channel 2
* @arg TIM_Channel_3: TIM Channel 3
@@ -2018,19 +2020,19 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) }
/**
- * @brief Selects the TIM Ouput Compare Mode.
- * @note This function disables the selected channel before changing the Ouput
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
* Compare Mode.
* User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
* @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
* @arg TIM_Channel_2: TIM Channel 2
* @arg TIM_Channel_3: TIM Channel 3
* @arg TIM_Channel_4: TIM Channel 4
* @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This paramter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_OCMode_Timing
* @arg TIM_OCMode_Active
* @arg TIM_OCMode_Toggle
@@ -2133,7 +2135,7 @@ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) }
/**
- * @brief Enables or disables the TIMx�s Hall sensor interface.
+ * @brief Enables or disables the TIMx's Hall sensor interface.
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
* @param NewState: new state of the TIMx Hall sensor interface.
* This parameter can be: ENABLE or DISABLE.
@@ -2157,7 +2159,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) }
/**
- * @brief Selects the TIMx�s One Pulse Mode.
+ * @brief Selects the TIMx's One Pulse Mode.
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
* @param TIM_OPMode: specifies the OPM Mode to be used.
* This parameter can be one of the following values:
@@ -2212,7 +2214,7 @@ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) * @brief Selects the TIMx Slave Mode.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This paramter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
* the counter and triggers an update of the registers.
* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
@@ -2235,7 +2237,7 @@ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) * @brief Sets or Resets the TIMx Master/Slave Mode.
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This paramter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
* and its slaves (through TRGO).
* @arg TIM_MasterSlaveMode_Disable: No action
@@ -2885,4 +2887,4 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c index eb84d977f2..a3f16f15ea 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_usart.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the USART firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_usart.h"
@@ -122,7 +123,8 @@ /**
* @brief Deinitializes the USARTx peripheral registers to their default reset values.
* @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
* @retval None
*/
void USART_DeInit(USART_TypeDef* USARTx)
@@ -162,12 +164,13 @@ void USART_DeInit(USART_TypeDef* USARTx) /**
* @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
+ * parameters in the USART_InitStruct .
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * that contains the configuration information for the specified USART peripheral.
+ * that contains the configuration information for the specified USART
+ * peripheral.
* @retval None
*/
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
@@ -272,7 +275,7 @@ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) /**
* @brief Fills each USART_InitStruct member with its default value.
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * which will be initialized.
+ * which will be initialized.
* @retval None
*/
void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
@@ -288,12 +291,12 @@ void USART_StructInit(USART_InitTypeDef* USART_InitStruct) /**
* @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
+ * specified parameters in the USART_ClockInitStruct .
* @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure that contains the configuration information for the specified
- * USART peripheral.
- * @note The Smart Card mode is not available for UART4 and UART5.
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
* @retval None
*/
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
@@ -324,7 +327,7 @@ void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockI /**
* @brief Fills each USART_ClockInitStruct member with its default value.
* @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure which will be initialized.
+ * structure which will be initialized.
* @retval None
*/
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
@@ -339,10 +342,10 @@ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) /**
* @brief Enables or disables the specified USART peripheral.
* @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
* @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
+ * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
@@ -372,7 +375,7 @@ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) * This parameter can be one of the following values:
* @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
* @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
* @arg USART_IT_IDLE: Idle line detection interrupt
@@ -749,7 +752,7 @@ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) * @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART one bit sampling methode.
+ * @param NewState: new state of the USART one bit sampling method.
* This parameter can be: ENABLE or DISABLE.
* @note
* This function has to be called before calling USART_Init()
@@ -775,11 +778,11 @@ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) }
/**
- * @brief Enables or disables the USART's one bit sampling methode.
+ * @brief Enables or disables the USART's one bit sampling method.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART one bit sampling methode.
+ * @param NewState: new state of the USART one bit sampling method.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
@@ -802,7 +805,7 @@ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) }
/**
- * @brief Configures the USART�s IrDA interface.
+ * @brief Configures the USART's IrDA interface.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
@@ -823,7 +826,7 @@ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) }
/**
- * @brief Enables or disables the USART�s IrDA interface.
+ * @brief Enables or disables the USART's IrDA interface.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
@@ -998,7 +1001,7 @@ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) }
/**
- * @brief Clears the USARTx�s interrupt pending bits.
+ * @brief Clears the USARTx's interrupt pending bits.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* USART1, USART2, USART3, UART4 or UART5.
@@ -1052,4 +1055,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c index 753a710cda..77a7ce517d 100644 --- a/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c +++ b/bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c @@ -2,11 +2,11 @@ ******************************************************************************
* @file stm32f10x_wwdg.c
* @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
+ * @version V3.5.0
+ * @date 11-March-2011
* @brief This file provides all the WWDG firmware functions.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -15,8 +15,9 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_wwdg.h"
@@ -220,4 +221,4 @@ void WWDG_ClearFlag(void) * @}
*/
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/SConscript b/bsp/stm32f107/SConscript index e27f56547c..3acf61424a 100644 --- a/bsp/stm32f107/SConscript +++ b/bsp/stm32f107/SConscript @@ -2,7 +2,7 @@ import rtconfig Import('RTT_ROOT')
from building import *
-src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f10x_it.c', 'system_stm32f10x.c']
+src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f10x_it.c']
src_drv = ['usart.c', 'serial.c']
if GetDepend('RT_USING_DFS'):
@@ -12,8 +12,8 @@ if GetDepend('RT_USING_LWIP'): src_drv += ['stm32_eth.c']
src = src_bsp + src_drv
-CPPPATH = [str(Dir('#'))]
-CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
+CPPPATH = [GetCurrentDir()]
+CPPDEFINES = []
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
diff --git a/bsp/stm32f107/project.uvopt b/bsp/stm32f107/project.uvopt index 387a64c097..b076135a42 100644 --- a/bsp/stm32f107/project.uvopt +++ b/bsp/stm32f107/project.uvopt @@ -102,7 +102,7 @@ <uSim>0</uSim> <uTrg>1</uTrg> <sLdApp>1</sLdApp> - <sGomain>0</sGomain> + <sGomain>1</sGomain> <sRbreak>1</sRbreak> <sRwatch>1</sRwatch> <sRmem>1</sRmem> @@ -133,8 +133,28 @@ <TargetDriverDllRegistry> <SetRegEntry> <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> <Key>JL2CM3</Key> - <Name>-U -O14 -S0 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN0</Name> + <Name>-U12345678 -O14 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06418041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO27 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000</Name> </SetRegEntry> </TargetDriverDllRegistry> <DebugFlag> @@ -145,7 +165,7 @@ <aSer1>0</aSer1> <aSer2>0</aSer2> <aPa>0</aPa> - <viewmode>0</viewmode> + <viewmode>1</viewmode> <vrSel>0</vrSel> <aSym>0</aSym> <aTbox>0</aTbox> @@ -170,7 +190,7 @@ <Group> <GroupName>Startup</GroupName> - <tvExp>0</tvExp> + <tvExp>1</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> <File> @@ -181,8 +201,8 @@ <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>70</TopLine> + <CurrentLine>80</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\application.c</PathWithFileName> <FilenameWithoutPath>application.c</FilenameWithoutPath> @@ -195,8 +215,8 @@ <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>55</TopLine> + <CurrentLine>74</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\startup.c</PathWithFileName> <FilenameWithoutPath>startup.c</FilenameWithoutPath> @@ -240,26 +260,12 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>.\system_stm32f10x.c</PathWithFileName> - <FilenameWithoutPath>system_stm32f10x.c</FilenameWithoutPath> - </File> - <File> - <GroupNumber>1</GroupNumber> - <FileNumber>6</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> - <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> - <bDave2>0</bDave2> <PathWithFileName>.\usart.c</PathWithFileName> <FilenameWithoutPath>usart.c</FilenameWithoutPath> </File> <File> <GroupNumber>1</GroupNumber> - <FileNumber>7</FileNumber> + <FileNumber>6</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -273,14 +279,14 @@ </File> <File> <GroupNumber>1</GroupNumber> - <FileNumber>8</FileNumber> + <FileNumber>7</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> + <ColumnNumber>26</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>3367</TopLine> + <CurrentLine>3367</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\stm32_eth.c</PathWithFileName> <FilenameWithoutPath>stm32_eth.c</FilenameWithoutPath> @@ -294,7 +300,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>2</GroupNumber> - <FileNumber>9</FileNumber> + <FileNumber>8</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -308,7 +314,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>10</FileNumber> + <FileNumber>9</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -322,21 +328,21 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>11</FileNumber> + <FileNumber>10</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>52</TopLine> + <CurrentLine>63</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>..\..\src\idle.c</PathWithFileName> <FilenameWithoutPath>idle.c</FilenameWithoutPath> </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>12</FileNumber> + <FileNumber>11</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -350,7 +356,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>13</FileNumber> + <FileNumber>12</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -364,7 +370,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>14</FileNumber> + <FileNumber>13</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -378,7 +384,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>15</FileNumber> + <FileNumber>14</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -392,7 +398,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>16</FileNumber> + <FileNumber>15</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -406,7 +412,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>17</FileNumber> + <FileNumber>16</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -420,7 +426,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>18</FileNumber> + <FileNumber>17</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -434,7 +440,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>19</FileNumber> + <FileNumber>18</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -448,7 +454,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>20</FileNumber> + <FileNumber>19</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -462,7 +468,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>21</FileNumber> + <FileNumber>20</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -476,7 +482,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>22</FileNumber> + <FileNumber>21</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -490,7 +496,7 @@ </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>23</FileNumber> + <FileNumber>22</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -511,7 +517,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>3</GroupNumber> - <FileNumber>24</FileNumber> + <FileNumber>23</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -525,7 +531,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>25</FileNumber> + <FileNumber>24</FileNumber> <FileType>2</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -539,21 +545,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>26</FileNumber> - <FileType>2</FileType> - <tvExp>0</tvExp> - <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> - <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> - <bDave2>0</bDave2> - <PathWithFileName>..\..\libcpu\arm\stm32\start_rvds.S</PathWithFileName> - <FilenameWithoutPath>start_rvds.S</FilenameWithoutPath> - </File> - <File> - <GroupNumber>3</GroupNumber> - <FileNumber>27</FileNumber> + <FileNumber>25</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -567,7 +559,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>28</FileNumber> + <FileNumber>26</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -581,7 +573,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>29</FileNumber> + <FileNumber>27</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -602,7 +594,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>4</GroupNumber> - <FileNumber>30</FileNumber> + <FileNumber>28</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -616,7 +608,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>31</FileNumber> + <FileNumber>29</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -630,7 +622,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>32</FileNumber> + <FileNumber>30</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -644,7 +636,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>33</FileNumber> + <FileNumber>31</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -658,7 +650,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>34</FileNumber> + <FileNumber>32</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -672,7 +664,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>35</FileNumber> + <FileNumber>33</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -686,7 +678,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>36</FileNumber> + <FileNumber>34</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -700,7 +692,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>37</FileNumber> + <FileNumber>35</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -714,7 +706,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>38</FileNumber> + <FileNumber>36</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -728,7 +720,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>39</FileNumber> + <FileNumber>37</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -742,7 +734,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>40</FileNumber> + <FileNumber>38</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -756,7 +748,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>41</FileNumber> + <FileNumber>39</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -770,7 +762,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>42</FileNumber> + <FileNumber>40</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -791,7 +783,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>5</GroupNumber> - <FileNumber>43</FileNumber> + <FileNumber>41</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -805,7 +797,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>44</FileNumber> + <FileNumber>42</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -819,7 +811,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>45</FileNumber> + <FileNumber>43</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -833,7 +825,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>46</FileNumber> + <FileNumber>44</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -847,7 +839,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>47</FileNumber> + <FileNumber>45</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -861,7 +853,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>48</FileNumber> + <FileNumber>46</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -875,7 +867,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>49</FileNumber> + <FileNumber>47</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -889,7 +881,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>50</FileNumber> + <FileNumber>48</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -903,7 +895,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>51</FileNumber> + <FileNumber>49</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -917,7 +909,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>52</FileNumber> + <FileNumber>50</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -931,7 +923,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>53</FileNumber> + <FileNumber>51</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -945,7 +937,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>54</FileNumber> + <FileNumber>52</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -959,7 +951,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>55</FileNumber> + <FileNumber>53</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -973,7 +965,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>56</FileNumber> + <FileNumber>54</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -987,7 +979,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>57</FileNumber> + <FileNumber>55</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1001,7 +993,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>58</FileNumber> + <FileNumber>56</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1015,7 +1007,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>59</FileNumber> + <FileNumber>57</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1029,7 +1021,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>60</FileNumber> + <FileNumber>58</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1043,7 +1035,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>61</FileNumber> + <FileNumber>59</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1057,7 +1049,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>62</FileNumber> + <FileNumber>60</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1071,7 +1063,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>63</FileNumber> + <FileNumber>61</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1085,7 +1077,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>64</FileNumber> + <FileNumber>62</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1099,7 +1091,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>65</FileNumber> + <FileNumber>63</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1113,7 +1105,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>66</FileNumber> + <FileNumber>64</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1127,7 +1119,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>67</FileNumber> + <FileNumber>65</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1141,7 +1133,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>68</FileNumber> + <FileNumber>66</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1155,7 +1147,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>69</FileNumber> + <FileNumber>67</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1169,7 +1161,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>70</FileNumber> + <FileNumber>68</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1183,7 +1175,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>71</FileNumber> + <FileNumber>69</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1197,7 +1189,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>72</FileNumber> + <FileNumber>70</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1211,7 +1203,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>73</FileNumber> + <FileNumber>71</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1225,7 +1217,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>74</FileNumber> + <FileNumber>72</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1239,7 +1231,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>75</FileNumber> + <FileNumber>73</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1253,7 +1245,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>76</FileNumber> + <FileNumber>74</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1267,7 +1259,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>77</FileNumber> + <FileNumber>75</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1288,7 +1280,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>6</GroupNumber> - <FileNumber>78</FileNumber> + <FileNumber>76</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1302,7 +1294,21 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>79</FileNumber> + <FileNumber>77</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <Focus>0</Focus> + <ColumnNumber>0</ColumnNumber> + <tvExpOptDlg>0</tvExpOptDlg> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> + <bDave2>0</bDave2> + <PathWithFileName>Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c</PathWithFileName> + <FilenameWithoutPath>system_stm32f10x.c</FilenameWithoutPath> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>78</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1316,7 +1322,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>80</FileNumber> + <FileNumber>79</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1330,7 +1336,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>81</FileNumber> + <FileNumber>80</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1344,7 +1350,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>82</FileNumber> + <FileNumber>81</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1358,7 +1364,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>83</FileNumber> + <FileNumber>82</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1372,7 +1378,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>84</FileNumber> + <FileNumber>83</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1386,7 +1392,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>85</FileNumber> + <FileNumber>84</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1400,7 +1406,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>86</FileNumber> + <FileNumber>85</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1414,7 +1420,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>87</FileNumber> + <FileNumber>86</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1428,7 +1434,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>88</FileNumber> + <FileNumber>87</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1442,7 +1448,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>89</FileNumber> + <FileNumber>88</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1456,7 +1462,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>90</FileNumber> + <FileNumber>89</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1470,7 +1476,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>91</FileNumber> + <FileNumber>90</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1484,7 +1490,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>92</FileNumber> + <FileNumber>91</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1498,7 +1504,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>93</FileNumber> + <FileNumber>92</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1512,7 +1518,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>94</FileNumber> + <FileNumber>93</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1526,7 +1532,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>95</FileNumber> + <FileNumber>94</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1540,7 +1546,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>96</FileNumber> + <FileNumber>95</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1554,7 +1560,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>97</FileNumber> + <FileNumber>96</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1568,7 +1574,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>98</FileNumber> + <FileNumber>97</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1582,7 +1588,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>99</FileNumber> + <FileNumber>98</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1596,7 +1602,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>100</FileNumber> + <FileNumber>99</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1610,7 +1616,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>101</FileNumber> + <FileNumber>100</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -1622,6 +1628,20 @@ <PathWithFileName>Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</PathWithFileName> <FilenameWithoutPath>misc.c</FilenameWithoutPath> </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>101</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <Focus>0</Focus> + <ColumnNumber>0</ColumnNumber> + <tvExpOptDlg>0</tvExpOptDlg> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> + <bDave2>0</bDave2> + <PathWithFileName>Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_cl.s</PathWithFileName> + <FilenameWithoutPath>startup_stm32f10x_cl.s</FilenameWithoutPath> + </File> </Group> </ProjectOpt> diff --git a/bsp/stm32f107/project.uvproj b/bsp/stm32f107/project.uvproj index c661ff2a87..f514b87f97 100644 --- a/bsp/stm32f107/project.uvproj +++ b/bsp/stm32f107/project.uvproj @@ -117,7 +117,7 @@ <Simulator> <UseSimulator>0</UseSimulator> <LoadApplicationAtStartup>1</LoadApplicationAtStartup> - <RunToMain>0</RunToMain> + <RunToMain>1</RunToMain> <RestoreBreakpoints>1</RestoreBreakpoints> <RestoreWatchpoints>1</RestoreWatchpoints> <RestoreMemoryDisplay>1</RestoreMemoryDisplay> @@ -160,7 +160,7 @@ <RunIndependent>0</RunIndependent> <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging> <Capability>1</Capability> - <DriverSelection>4098</DriverSelection> + <DriverSelection>4099</DriverSelection> </Flash1> <Flash2>Segger\JL2CM3.dll</Flash2> <Flash3>"" ()</Flash3> @@ -346,7 +346,7 @@ <MiscControls></MiscControls> <Define>STM32F10X_CL, USE_STDPERIPH_DRIVER</Define> <Undefine></Undefine> - <IncludePath>..\stm3210\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\components\net\lwip\src\arch\include;..\..\components\finsh;..\..\components\net\lwip\src\include;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;..\stm3210\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\stm3210\Libraries\CMSIS\CM3\CoreSupport;..\..\libcpu\arm\stm32;..\..\components\net\lwip\src\include\netif</IncludePath> + <IncludePath>Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\components\net\lwip\src\arch\include;..\..\components\finsh;..\..\components\net\lwip\src\include;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;Libraries\CMSIS\CM3\CoreSupport;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\libcpu\arm\stm32;..\..\components\net\lwip\src\include\netif;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x</IncludePath> </VariousControls> </Cads> <Aads> @@ -407,11 +407,6 @@ <FilePath>.\stm32f10x_it.c</FilePath> </File> <File> - <FileName>system_stm32f10x.c</FileName> - <FileType>1</FileType> - <FilePath>.\system_stm32f10x.c</FilePath> - </File> - <File> <FileName>usart.c</FileName> <FileType>1</FileType> <FilePath>.\usart.c</FilePath> @@ -522,11 +517,6 @@ <FilePath>..\..\libcpu\arm\stm32\context_rvds.S</FilePath> </File> <File> - <FileName>start_rvds.S</FileName> - <FileType>2</FileType> - <FilePath>..\..\libcpu\arm\stm32\start_rvds.S</FilePath> - </File> - <File> <FileName>backtrace.c</FileName> <FileType>1</FileType> <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath> @@ -802,6 +792,11 @@ <FilePath>Libraries\CMSIS\CM3\CoreSupport\core_cm3.c</FilePath> </File> <File> + <FileName>system_stm32f10x.c</FileName> + <FileType>1</FileType> + <FilePath>Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c</FilePath> + </File> + <File> <FileName>stm32f10x_crc.c</FileName> <FileType>1</FileType> <FilePath>Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c</FilePath> @@ -916,6 +911,11 @@ <FileType>1</FileType> <FilePath>Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath> </File> + <File> + <FileName>startup_stm32f10x_cl.s</FileName> + <FileType>2</FileType> + <FilePath>Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_cl.s</FilePath> + </File> </Files> </Group> </Groups> diff --git a/bsp/stm32f107/rtconfig.h b/bsp/stm32f107/rtconfig.h index 8c30229d43..e0a68d1c36 100644 --- a/bsp/stm32f107/rtconfig.h +++ b/bsp/stm32f107/rtconfig.h @@ -75,13 +75,20 @@ /* SECTION: device filesystem */
/* #define RT_USING_DFS */
#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_WORD_ACCESS
+/* Reentrancy (thread safe) of the FatFs module. */
+#define RT_DFS_ELM_REENTRANT
+/* Number of volumes (logical drives) to be used. */
+#define RT_DFS_ELM_DRIVES 2
+/* #define RT_DFS_ELM_USE_LFN 1 */
+#define RT_DFS_ELM_MAX_LFN 255
+/* Maximum sector size to be handled. */
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
-/* the max number of cached sector */
-#define DFS_CACHE_MAX_NUM 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
#define RT_USING_LWIP
diff --git a/bsp/stm32f107/rtconfig.py b/bsp/stm32f107/rtconfig.py index 0bc4186ee2..d492fd64d9 100644 --- a/bsp/stm32f107/rtconfig.py +++ b/bsp/stm32f107/rtconfig.py @@ -3,15 +3,18 @@ ARCH='arm' CPU='stm32'
CROSS_TOOL='keil'
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
- EXEC_PATH = 'D:/SourceryGCC/bin'
+ EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'E:/Keil'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
- IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 5.4 Evaluation_0'
+ IAR_PATH = 'E:/Program Files/IAR Systems/Embedded Workbench 6.0'
BUILD = 'debug'
STM32_TYPE = 'STM32F10X_CL'
diff --git a/bsp/stm32f107/stm32f10x_it.c b/bsp/stm32f107/stm32f10x_it.c index ee2c325319..10e197c82c 100644 --- a/bsp/stm32f107/stm32f10x_it.c +++ b/bsp/stm32f107/stm32f10x_it.c @@ -1,14 +1,14 @@ /**
******************************************************************************
- * @file Project/Template/stm32f10x_it.c
+ * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
* @author MCD Application Team
- * @version V3.1.0
- * @date 06/19/2009
+ * @version V3.5.0
+ * @date 08-April-2011
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -17,7 +17,8 @@ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -50,19 +51,6 @@ void NMI_Handler(void) }
/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
@@ -119,6 +107,12 @@ void DebugMon_Handler(void) {
}
+void SysTick_Handler(void)
+{
+ extern void rt_hw_timer_handler(void);
+ rt_hw_timer_handler();
+}
+
/******************************************************************************/
/* STM32F10x Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
diff --git a/bsp/stm32f107/system_stm32f10x.c b/bsp/stm32f107/system_stm32f10x.c deleted file mode 100644 index 50af0dc3f6..0000000000 --- a/bsp/stm32f107/system_stm32f10x.c +++ /dev/null @@ -1,1033 +0,0 @@ -/**
- ******************************************************************************
- * @file system_stm32f10x.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- ******************************************************************************
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x_system
- * @{
- */
-
-/** @addtogroup STM32F10x_System_Private_Includes
- * @{
- */
-
-#include "stm32f10x.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
- frequency (after reset the HSI is used as SYSCLK source)
-
- IMPORTANT NOTE:
- ==============
- 1. After each device reset the HSI is used as System clock source.
-
- 2. Please make sure that the selected System clock doesn't exceed your device's
- maximum frequency.
-
- 3. If none of the define below is enabled, the HSI is used as System clock
- source.
-
- 4. The System clock configuration functions provided within this file assume that:
- - For Low, Medium and High density Value line devices an external 8MHz
- crystal is used to drive the System clock.
- - For Low, Medium and High density devices an external 8MHz crystal is
- used to drive the System clock.
- - For Connectivity line devices an external 25MHz crystal is used to drive
- the System clock.
- If you are using different crystal you have to adapt those functions accordingly.
- */
-
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
- #define SYSCLK_FREQ_24MHz 24000000
-#else
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz 24000000 */
-/* #define SYSCLK_FREQ_36MHz 36000000 */
-/* #define SYSCLK_FREQ_48MHz 48000000 */
-/* #define SYSCLK_FREQ_56MHz 56000000 */
-#define SYSCLK_FREQ_72MHz 72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
- STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x100. */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
- uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
- static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
- static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
- static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
- static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
- static void SetSysClockTo56(void);
-#elif defined SYSCLK_FREQ_72MHz
- static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
- RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
- RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
- /* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= (uint32_t)0xEBFFFFFF;
-
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#else
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
- #ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
- #endif /* DATA_IN_ExtSRAM */
-#endif
-
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
- /* Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock according to Clock Register Values
- * @note None
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef STM32F10X_CL
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
-
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-#ifndef STM32F10X_CL
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- #else
- /* HSE selected as PLL clock entry */
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
- {/* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
- }
- else
- {
- SystemCoreClock = HSE_VALUE * pllmull;
- }
- #endif
- }
-#else
- pllmull = pllmull >> 18;
-
- if (pllmull != 0x0D)
- {
- pllmull += 2;
- }
- else
- { /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmull = 13 / 2;
- }
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {/* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-
- if (prediv1source == 0)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- else
- {/* PLL2 clock selected as PREDIV1 clock entry */
-
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
- }
- }
-#endif /* STM32F10X_CL */
- break;
-
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
- SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
- SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
- SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
- SetSysClockTo72();
-#endif
-
- /* If none of the define above is enabled, the HSI is used as System clock
- source (default after reset) */
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f10x_xx.s/.c before jump to main.
- * This function configures the external SRAM mounted on STM3210E-EVAL
- * board (STM32 High density devices). This SRAM will be used as program
- * data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses */
-
- /* Enable FSMC clock */
- RCC->AHBENR = 0x00000114;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2ENR = 0x000001E0;
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- GPIOD->CRL = 0x44BB44BB;
- GPIOD->CRH = 0xBBBBBBBB;
-
- GPIOE->CRL = 0xB44444BB;
- GPIOE->CRH = 0xBBBBBBBB;
-
- GPIOF->CRL = 0x44BBBBBB;
- GPIOF->CRH = 0xBBBB4444;
-
- GPIOG->CRL = 0x44BBBBBB;
- GPIOG->CRH = 0x44444B44;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- FSMC_Bank1->BTCR[4] = 0x00001011;
- FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
- if (HSE_VALUE <= 24000000)
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
- }
- else
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
- }
-#endif /* STM32F10X_CL */
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-#else
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL7);
-#else
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-#else
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f107/template.Uv2 b/bsp/stm32f107/template.Uv2 deleted file mode 100644 index 86d802dee3..0000000000 --- a/bsp/stm32f107/template.Uv2 +++ /dev/null @@ -1,98 +0,0 @@ -### uVision2 Project, (C) Keil Software
-### Do not modify !
-
-Target (RT-Thread STM32), 0x0004 // Tools: 'ARM-ADS'
-
-
-
-
-Options 1,0,0 // Target 'RT-Thread STM32'
- Device (STM32F103ZE)
- Vendor (STMicroelectronics)
- Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3"))
- FlashUt ()
- StupF ("STARTUP\ST\STM32F10x.s" ("STM32 Startup Code"))
- FlashDR (UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000))
- DevID (4216)
- Rgf (stm32f10x_lib.h)
- Mem ()
- C ()
- A ()
- RL ()
- OH ()
- DBC_IFX ()
- DBC_CMS ()
- DBC_AMS ()
- DBC_LMS ()
- UseEnv=0
- EnvBin ()
- EnvInc ()
- EnvLib ()
- EnvReg (�ST\STM32F10x\)
- OrgReg (�ST\STM32F10x\)
- TgStat=16
- OutDir (.\obj\)
- OutName (rtthread-stm32)
- GenApp=1
- GenLib=0
- GenHex=0
- Debug=1
- Browse=0
- LstDir (.\)
- HexSel=1
- MG32K=0
- TGMORE=0
- RunUsr 0 0 <>
- RunUsr 1 0 <>
- BrunUsr 0 0 <>
- BrunUsr 1 0 <>
- CrunUsr 0 0 <>
- CrunUsr 1 0 <>
- SVCSID <>
- GLFLAGS=1790
- ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ACPUTYP ("Cortex-M3")
- RVDEV ()
- ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
- OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }
- OCMADSIROM { 1,0,0,0,8,0,0,8,0 }
- OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
- OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
- RV_STAVEC ()
- ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ADSCMISC ()
- ADSCDEFN ()
- ADSCUDEF ()
- ADSCINCD ()
- ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ADSAMISC ()
- ADSADEFN ()
- ADSAUDEF ()
- ADSAINCD ()
- PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- IncBld=1
- AlwaysBuild=0
- GenAsm=0
- AsmAsm=0
- PublicsOnly=0
- StopCode=3
- CustArgs ()
- LibMods ()
- ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ADSLDTA (0x08000000)
- ADSLDDA (0x20000000)
- ADSLDSC ()
- ADSLDIB ()
- ADSLDIC ()
- ADSLDMC ()
- ADSLDIF ()
- ADSLDDW ()
- OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE)
- OPTDBG 49142,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
- FLASH1 { 1,0,0,0,1,0,0,0,6,16,0,0,0,0,0,0,0,0,0,0 }
- FLASH2 (Segger\JL2CM3.dll)
- FLASH3 ("" ())
- FLASH4 ()
-EndOpt
-
diff --git a/bsp/stm32f107/template.uvopt b/bsp/stm32f107/template.uvopt new file mode 100644 index 0000000000..b172f6a05b --- /dev/null +++ b/bsp/stm32f107/template.uvopt @@ -0,0 +1,164 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>RT-Thread STM32</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>25000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>1</RunSim> + <RunTarget>0</RunTarget> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>255</CpuCode> + <Books> + <Book> + <Number>0</Number> + <Title>7</Title> + <Path>DATASHTS\ST\STM32F105</Path> + </Book> + <Book> + <Number>1</Number> + <Title>Reference Manual</Title> + <Path>DATASHTS\ST\STM32F10xxx.PDF</Path> + </Book> + </Books> + <DllOpt> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments></SimDllArguments> + <SimDlgDllName>DARMSTM.DLL</SimDlgDllName> + <SimDlgDllArguments>-pSTM32F107VC</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments></TargetDllArguments> + <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName> + <TargetDlgDllArguments>-pSTM32F107VC</TargetDlgDllArguments> + </DllOpt> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>0</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <nTsel>7</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>Segger\JL2CM3.dll</pMon> + </DebugOpt> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>3</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + </TargetOption> + </Target> + +</ProjectOpt> diff --git a/bsp/stm32f107/template.uvproj b/bsp/stm32f107/template.uvproj new file mode 100644 index 0000000000..f0931ef64a --- /dev/null +++ b/bsp/stm32f107/template.uvproj @@ -0,0 +1,388 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd"> + + <SchemaVersion>1.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>RT-Thread STM32</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>STM32F107VC</Device> + <Vendor>STMicroelectronics</Vendor> + <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000)</FlashDriverDll> + <DeviceId>4889</DeviceId> + <RegisterFile>stm32f10x_lib.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>SFD\ST\STM32F107x\STM32F107.sfr</SFDFile> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>ST\STM32F10x\</RegisterFilePath> + <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\obj\</OutputDirectory> + <OutputName>rtthread-stm32</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>0</BrowseInformation> + <ListingPath>.\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments></SimDllArguments> + <SimDlgDll>DARMSTM.DLL</SimDlgDll> + <SimDlgDllArguments>-pSTM32F107VC</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments></TargetDllArguments> + <TargetDlgDll>TARMSTM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pSTM32F107VC</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>0</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>7</TargetSelection> + <SimDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + </SimDlls> + <TargetDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + <Driver>Segger\JL2CM3.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4099</DriverSelection> + </Flash1> + <Flash2>Segger\JL2CM3.dll</Flash2> + <Flash3></Flash3> + <Flash4></Flash4> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M3"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <hadIRAM2>0</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x10000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x40000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x40000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x10000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>1</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x08000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <ScatterFile></ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + </Target> + </Targets> + +</Project> |