diff options
| author | [email protected] <[email protected]> | 2012-04-23 09:59:00 +0000 |
|---|---|---|
| committer | [email protected] <[email protected]> | 2012-04-23 09:59:00 +0000 |
| commit | cbd32a0c32b7d4205ffb45b63e9e981cfad34c32 (patch) | |
| tree | 2e7645ff48639e300ea76e95287761feaa00fbdb /bsp | |
| parent | 209da6823c763c57409fdb52c5ae31484410f19e (diff) | |
upgrade MB9BF506 CMSIS to version 3.01
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2100 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'bsp')
28 files changed, 14658 insertions, 5290 deletions
diff --git a/bsp/mb9bf506r/CMSIS/SConscript b/bsp/mb9bf506r/CMSIS/SConscript deleted file mode 100644 index e058a7aad1..0000000000 --- a/bsp/mb9bf506r/CMSIS/SConscript +++ /dev/null @@ -1,19 +0,0 @@ -Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-src = Glob('*.c')
-
-# add for startup script
-if rtconfig.CROSS_TOOL == 'gcc':
- src = src + ['start_gcc.S']
-elif rtconfig.CROSS_TOOL == 'keil':
- src = src + ['start_rvds.S']
-elif rtconfig.CROSS_TOOL == 'iar':
- src = src + ['start_iar.S']
-
-CPPPATH = [GetCurrentDir()]
-
-group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, LIBRARY = '')
-
-Return('group')
diff --git a/bsp/mb9bf506r/CMSIS/core_cm3.c b/bsp/mb9bf506r/CMSIS/core_cm3.c deleted file mode 100644 index f1bfb2b8e0..0000000000 --- a/bsp/mb9bf506r/CMSIS/core_cm3.c +++ /dev/null @@ -1,359 +0,0 @@ -/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.40
- * @date 18. February 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ########################## Core Instruction Access ######################### */
-
-#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
-
-/**
- * @brief Reverse byte order (16 bit)
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
- /**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __CLREX(void)
-{
- clrex
-}
-#endif /* __ARMCC_VERSION */
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-
-#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Get IPSR Register value
- *
- * @return uint32_t IPSR value
- *
- * return the content of the IPSR register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_IPSR(void)
-{
- mrs r0, ipsr
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Get APSR Register value
- *
- * @return uint32_t APSR value
- *
- * return the content of the APSR register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_APSR(void)
-{
- mrs r0, apsr
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Get xPSR Register value
- *
- * @return uint32_t xPSR value
- *
- * return the content of the xPSR register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_xPSR(void)
-{
- mrs r0, xpsr
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the FPSCR value
- *
- * @return FloatingPointStatusControlRegister
- *
- * Return the content of the FPSCR register
- */
-
-/**
- * @brief Set the FPSCR value
- *
- * @param fpscr FloatingPointStatusControlRegister
- *
- * Set the FPSCR register
- */
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
diff --git a/bsp/mb9bf506r/CMSIS/core_cm3.h b/bsp/mb9bf506r/CMSIS/core_cm3.h deleted file mode 100644 index 43be05e58b..0000000000 --- a/bsp/mb9bf506r/CMSIS/core_cm3.h +++ /dev/null @@ -1,1166 +0,0 @@ -/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.40
- * @date 16. February 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CM3_H__
-#define __CORE_CM3_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - not yet checked
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x40) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-#include <stdint.h> /* Include standard types */
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
-*/
-
-/** @addtogroup CMSIS_ARM_CORE CMSIS ARM Core
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
- @{
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27;
-#else
- uint32_t _reserved0:16;
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7;
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b;
- uint32_t w;
-} APSR_Type;
-
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 00..08 Exception number */
- uint32_t _reserved0:23;
- } b;
- uint32_t w;
-} IPSR_Type;
-
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 00..08 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15;
-#else
- uint32_t _reserved0:7;
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4;
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b;
- uint32_t w;
-} xPSR_Type;
-
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 00 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 01 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 02 FP extension active flag */
- uint32_t _reserved0:29;
- } b;
- uint32_t w;
-} CONTROL_Type;
-
-/*@}*/ /* end of group CMSIS_ARM_CORE */
-
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
- @{
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
-
-
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
- @{
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
-
-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
-
-
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
- @{
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
-
-
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
- @{
- */
-typedef struct
-{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
- @{
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@}*/ /* end of group CMSIS_CM3_MPU */
-#endif
-
-
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
- @{
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
-
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_register */
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-/* ########################## Core Instruction Access ######################### */
-#include "core_cmInstr.h"
-
-/* ########################### Core Function Access ########################### */
-#include "core_cmFunc.h"
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Reset Functions
-*/
-/*@{*/
-
-/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-
-/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
- */
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CORE_CM3_H__ */
-
-/*lint -restore */
diff --git a/bsp/mb9bf506r/CMSIS/core_cmFunc.h b/bsp/mb9bf506r/CMSIS/core_cmFunc.h deleted file mode 100644 index 03c29d35dc..0000000000 --- a/bsp/mb9bf506r/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,912 +0,0 @@ -/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V1.40
- * @date 16. February 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
-
-/* ########################### Core Function Access ########################### */
-
-#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
-/* ARM armcc specific functions */
-
- /**
- * @brief Enable IRQ Interrupts
- *
- * Enables IRQ interrupts by clearing the I-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); */
-
- /**
- * @brief Disable IRQ Interrupts
- *
- * Disables IRQ interrupts by setting the I-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); */
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_CONTROL(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __set_CONTROL(uint32_t control);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Get IPSR Register value
- *
- * @return uint32_t IPSR value
- *
- * return the content of the IPSR register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_IPSR(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Get APSR Register value
- *
- * @return uint32_t APSR value
- *
- * return the content of the APSR register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_APSR(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Get xPSR Register value
- *
- * @return uint32_t xPSR value
- *
- * return the content of the xPSR register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_xPSR(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_PSP(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __set_PSP(uint32_t topOfProcStack);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_MSP(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __set_MSP(uint32_t topOfMainStack);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_MSP(uint32_t mainStackPointer)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = mainStackPointer;
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_PRIMASK(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __set_PRIMASK(uint32_t priMask);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-#endif /* __ARMCC_VERSION */
-
-
-#if (__CORTEX_M >= 0x03)
-
- /**
- * @brief Enable FIQ Interrupts
- *
- * Enables FIQ interrupts by clearing the F-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
- /**
- * @brief Disable FIQ Interrupts
- *
- * Disables FIQ interrupts by setting the F-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_BASEPRI(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __set_BASEPRI(uint32_t basePri);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-#if (__ARMCC_VERSION < 400000)
-extern uint32_t __get_FAULTMASK(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __set_FAULTMASK(uint32_t faultMask);
-#else /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-#endif /* __ARMCC_VERSION */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/**
- * @brief Return the FPSCR value
- *
- * @return FloatingPointStatusControlRegister
- *
- * Return the content of the FPSCR register
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-/**
- * @brief Set the FPSCR value
- *
- * @param fpscr FloatingPointStatusControlRegister
- *
- * Set the FPSCR register
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* IAR iccarm specific functions */
-#if defined (__ICCARM__)
- #include <intrinsics.h> /* IAR Intrinsics */
-#endif
-
-#pragma diag_suppress=Pe940
-
- /**
- * @brief Enable IRQ Interrupts
- *
- * Enables IRQ interrupts by clearing the I-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-#define __enable_irq __enable_interrupt
-
- /**
- * @brief Disable IRQ Interrupts
- *
- * Disables IRQ interrupts by setting the I-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-#define __disable_irq __disable_interrupt
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-/**
- * @brief Get IPSR Register value
- *
- * @return uint32_t IPSR value
- *
- * return the content of the IPSR register
- */
-static uint32_t __get_IPSR(void)
-{
- __ASM("mrs r0, ipsr");
-}
-
-/**
- * @brief Get APSR Register value
- *
- * @return uint32_t APSR value
- *
- * return the content of the APSR register
- */
-/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */
-
-/**
- * @brief Get xPSR Register value
- *
- * @return uint32_t xPSR value
- *
- * return the content of the xPSR register
- */
-static uint32_t __get_xPSR(void)
-{
- __ASM("mrs r0, psr"); // assembler does not know "xpsr"
-}
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
- static uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-static uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
-
-
-#if (__CORTEX_M >= 0x03)
-
- /**
- * @brief Enable FIQ Interrupts
- *
- * Enables FIQ interrupts by clearing the F-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-
- /**
- * @brief Disable FIQ Interrupts
- *
- * Disables FIQ interrupts by setting the F-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/**
- * @brief Return the FPSCR value
- *
- * @return FloatingPointStatusControlRegister
- *
- * Return the content of the FPSCR register
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
- /* not yet implemented */
- return(0);
-#else
- return(0);
-#endif
-}
-
-/**
- * @brief Set the FPSCR value
- *
- * @param fpscr FloatingPointStatusControlRegister
- *
- * Set the FPSCR register
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
- /* not yet implemented */
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
- /**
- * @brief Enable IRQ Interrupts
- *
- * Enables IRQ interrupts by clearing the I-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-
- /**
- * @brief Disable IRQ Interrupts
- *
- * Disables IRQ interrupts by setting the I-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-/**
- * @brief Get IPSR Register value
- *
- * @return uint32_t IPSR value
- *
- * return the content of the IPSR register
- */
-static __INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Get APSR Register value
- *
- * @return uint32_t APSR value
- *
- * return the content of the APSR register
- */
-static __INLINE uint32_t __get_APSR(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Get xPSR Register value
- *
- * @return uint32_t xPSR value
- *
- * return the content of the xPSR register
- */
-static __INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) );
-static __INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result __ASM ("r0") = 0;
-
- __ASM volatile ("MRS %0, psp\n"
- "BX lr \n" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n"
- "BX lr \n" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) );
-static __INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result __ASM ("r0") = 0;
-
- __ASM volatile ("MRS %0, msp\n"
- "BX lr \n" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n"
- "BX lr \n" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
- /**
- * @brief Enable FIQ Interrupts
- *
- * Enables FIQ interrupts by clearing the F-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-
- /**
- * @brief Disable FIQ Interrupts
- *
- * Disables FIQ interrupts by setting the F-bit in the CPSR.
- * Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-
-#if (__CORTEX_M == 0x04)
-
-/**
- * @brief Return the FPSCR value
- *
- * @return FloatingPointStatusControlRegister
- *
- * Return the content of the FPSCR register
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
- return(result);
-#else
- return(0);
-#endif
-}
-
-/**
- * @brief Set the FPSCR value
- *
- * @param fpscr FloatingPointStatusControlRegister
- *
- * Set the FPSCR register
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
- __ASM volatile ("MSR control, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-#endif // __CORE_CMFUNC_H__
diff --git a/bsp/mb9bf506r/CMSIS/core_cmInstr.h b/bsp/mb9bf506r/CMSIS/core_cmInstr.h deleted file mode 100644 index 514cfb2385..0000000000 --- a/bsp/mb9bf506r/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,684 +0,0 @@ -/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V1.40
- * @date 16. February 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
-
-/* ########################## Core Instruction Access ######################### */
-
-#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
-/* ARM armcc specific functions */
-
- /**
- * @brief No Operation
- *
- * No Operation does nothing. This instruction can be used for code alignment
- * purposes.
- */
-#define __NOP __nop
-
- /**
- * @brief Wait For Interrupt
- *
- * Wait For Interrupt is a hint instruction that suspends execution until
- * one of a number of events occurs.
- */
-#define __WFI __wfi
-
- /**
- * @brief Wait For Event
- *
- * Wait For Event is a hint instruction that permits the processor to enter
- * a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
- /**
- * @brief Send Event
- *
- * Send Event is a hint instruction. It causes an event to be signaled
- * to the CPU.
- */
-#define __SEV __sev
-
- /**
- * @brief Instruction Synchronization Barrier
- *
- * Instruction Synchronization Barrier flushes the pipeline in the processor,
- * so that all instructions following the ISB are fetched from cache or
- * memory, after the instruction has been completed
- */
-#define __ISB() __isb(0xF)
-
- /**
- * @brief Data Synchronization Barrier
- *
- * The DSB instruction operation acts as a special kind of Data Memory Barrier.
- * The DSB operation completes when all explicit memory accesses before this
- * instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
- /**
- * @brief Data Memory Barrier
- *
- * DMB ensures the apparent order of the explicit memory operations before
- * and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-/**
- * @brief Reverse byte order (32 bit)
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-#define __REV __rev
-
-/**
- * @brief Reverse byte order (16 bit)
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint16_t value);
-#else /* (__ARMCC_VERSION >= 400677) */
-static __INLINE __ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int16_t value);
-#else /* (__ARMCC_VERSION >= 400677) */
-static __INLINE __ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif /* __ARMCC_VERSION */
-
-
-#if (__CORTEX_M >= 0x03)
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-#define __RBIT __rbit
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
- /**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else /* (__ARMCC_VERSION >= 400000) */
-#define __CLREX __clrex
-#endif /* __ARMCC_VERSION */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* IAR iccarm specific functions */
-#if defined (__ICCARM__)
- #include <intrinsics.h> /* IAR Intrinsics */
-#endif
-
-#pragma diag_suppress=Pe940
-
- /**
- * @brief No Operation
- *
- * No Operation does nothing. This instruction can be used for code alignment
- * purposes.
- */
-#define __NOP __no_operation
-
- /**
- * @brief Wait For Interrupt
- *
- * Wait For Interrupt is a hint instruction that suspends execution until
- * one of a number of events occurs.
- */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-
- /**
- * @brief Wait For Event
- *
- * Wait For Event is a hint instruction that permits the processor to enter
- * a low-power state until one of a number of events occurs.
- */
-static __INLINE void __WFE() { __ASM ("wfe"); }
-
- /**
- * @brief Send Event
- *
- * Send Event is a hint instruction. It causes an event to be signaled
- * to the CPU.
- */
-static __INLINE void __SEV() { __ASM ("sev"); }
-
- /**
- * @brief Instruction Synchronization Barrier
- *
- * Instruction Synchronization Barrier flushes the pipeline in the processor,
- * so that all instructions following the ISB are fetched from cache or
- * memory, after the instruction has been completed
- */
-/* intrinsic void __ISB(void) (see intrinsics.h */
-
- /**
- * @brief Data Synchronization Barrier
- *
- * The DSB instruction operation acts as a special kind of Data Memory Barrier.
- * The DSB operation completes when all explicit memory accesses before this
- * instruction complete.
- */
-/* intrinsic void __DSB(void) (see intrinsics.h */
-
- /**
- * @brief Data Memory Barrier
- *
- * DMB ensures the apparent order of the explicit memory operations before
- * and after the instruction, without ensuring their completion.
- */
-/* intrinsic void __DMB(void) (see intrinsics.h */
-
-/**
- * @brief Reverse byte order (32 bit)
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */
-
-/**
- * @brief Reverse byte order (16 bit)
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-static uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
-
-
-#if (__CORTEX_M >= 0x03)
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-static uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-static uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-static uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */
-static uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-static uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-static uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */
-static uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
-}
-
- /**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
- /**
- * @brief No Operation
- *
- * No Operation does nothing. This instruction can be used for code alignment
- * purposes.
- */
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-
- /**
- * @brief Wait For Interrupt
- *
- * Wait For Interrupt is a hint instruction that suspends execution until
- * one of a number of events occurs.
- */
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-
- /**
- * @brief Wait For Event
- *
- * Wait For Event is a hint instruction that permits the processor to enter
- * a low-power state until one of a number of events occurs.
- */
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-
- /**
- * @brief Send Event
- *
- * Send Event is a hint instruction. It causes an event to be signaled
- * to the CPU.
- */
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-
- /**
- * @brief Instruction Synchronization Barrier
- *
- * Instruction Synchronization Barrier flushes the pipeline in the processor,
- * so that all instructions following the ISB are fetched from cache or
- * memory, after the instruction has been completed
- */
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-
- /**
- * @brief Data Synchronization Barrier
- *
- * The DSB instruction operation acts as a special kind of Data Memory Barrier.
- * The DSB operation completes when all explicit memory accesses before this
- * instruction complete.
- */
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-
- /**
- * @brief Data Memory Barrier
- *
- * DMB ensures the apparent order of the explicit memory operations before
- * and after the instruction, without ensuring their completion.
- */
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-
-/**
- * @brief Reverse byte order (32 bit)
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-static __INLINE uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order (16 bit)
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-static __INLINE uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-static __INLINE int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-static __INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-static __INLINE uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-static __INLINE uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-static __INLINE uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
- /**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-#endif // __CORE_CMINSTR_H__
diff --git a/bsp/mb9bf506r/CMSIS/start_gcc.S b/bsp/mb9bf506r/CMSIS/start_gcc.S deleted file mode 100644 index ad0f8af0c3..0000000000 --- a/bsp/mb9bf506r/CMSIS/start_gcc.S +++ /dev/null @@ -1,360 +0,0 @@ -/*
- * File : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-07-01 lgnq first version
- */
-
-.section .bss.init
-.equ Stack_Size, 0x00000200
-.space Stack_Size
-Initial_spTop:
-
- .syntax unified
- .cpu cortex-m3
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-// .equ Initial_spTop, 0x20000200
-.equ BootRAM, 0xF1E0F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* restore original stack pointer */
- LDR r0, =Initial_spTop
- MSR msp, r0
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-/* Call the application's entry point.*/
- bl main
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word Initial_spTop
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- .word CSV_IRQHandler
- .word SWDT_IRQHandler
- .word LVD_IRQHandler
- .word WFG_IRQHandler
- .word EXINT0_7_IRQHandler
- .word EXINT8_15_IRQHandler
- .word DTIM_QDU_IRQHandler
- .word MFS0RX_IRQHandler
- .word MFS0TX_IRQHandler
- .word MFS1RX_IRQHandler
- .word MFS1TX_IRQHandler
- .word MFS2RX_IRQHandler
- .word MFS2TX_IRQHandler
- .word MFS3RX_IRQHandler
- .word MFS3TX_IRQHandler
- .word MFS4RX_IRQHandler
- .word MFS4TX_IRQHandler
- .word MFS5RX_IRQHandler
- .word MFS5TX_IRQHandler
- .word MFS6RX_IRQHandler
- .word MFS6TX_IRQHandler
- .word MFS7RX_IRQHandler
- .word MFS7TX_IRQHandler
- .word PPG_IRQHandler
- .word OSC_PLL_WC_IRQHandler
- .word ADC0_IRQHandler
- .word ADC1_IRQHandler
- .word ADC2_IRQHandler
- .word FRTIM_IRQHandler
- .word INCAP_IRQHandler
- .word OUTCOMP_IRQHandler
- .word BTIM_IRQHandler
- .word CAN0_IRQHandler
- .word CAN1_IRQHandler
- .word USBF_IRQHandler
- .word USBF_USBH_IRQHandler
- .word RESERVED_1_IRQHandler
- .word RESERVED_2_IRQHandler
- .word DMAC0_IRQHandler
- .word DMAC1_IRQHandler
- .word DMAC2_IRQHandler
- .word DMAC3_IRQHandler
- .word DMAC4_IRQHandler
- .word DMAC5_IRQHandler
- .word DMAC6_IRQHandler
- .word DMAC7_IRQHandler
- .word RESERVED_3_IRQHandler
- .word RESERVED_4_IRQHandler
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak CSV_IRQHandler
- .thumb_set CSV_IRQHandler,Default_Handler
-
- .weak SWDT_IRQHandler
- .thumb_set SWDT_IRQHandler,Default_Handler
-
- .weak LVD_IRQHandler
- .thumb_set LVD_IRQHandler,Default_Handler
-
- .weak WFG_IRQHandler
- .thumb_set WFG_IRQHandler,Default_Handler
-
- .weak EXINT0_7_IRQHandler
- .thumb_set EXINT0_7_IRQHandler,Default_Handler
-
- .weak EXINT8_15_IRQHandler
- .thumb_set EXINT8_15_IRQHandler,Default_Handler
-
- .weak DTIM_QDU_IRQHandler
- .thumb_set DTIM_QDU_IRQHandler,Default_Handler
-
- .weak MFS0RX_IRQHandler
- .thumb_set MFS0RX_IRQHandler,Default_Handler
-
- .weak MFS0TX_IRQHandler
- .thumb_set MFS0TX_IRQHandler,Default_Handler
-
- .weak MFS1RX_IRQHandler
- .thumb_set MFS1RX_IRQHandler,Default_Handler
-
- .weak MFS1TX_IRQHandler
- .thumb_set MFS1TX_IRQHandler,Default_Handler
-
- .weak MFS2RX_IRQHandler
- .thumb_set MFS2RX_IRQHandler,Default_Handler
-
- .weak MFS2TX_IRQHandler
- .thumb_set MFS2TX_IRQHandler,Default_Handler
-
- .weak MFS3RX_IRQHandler
- .thumb_set MFS3RX_IRQHandler,Default_Handler
-
- .weak MFS3TX_IRQHandler
- .thumb_set MFS3TX_IRQHandler,Default_Handler
-
- .weak MFS4RX_IRQHandler
- .thumb_set MFS4RX_IRQHandler,Default_Handler
-
- .weak MFS4TX_IRQHandler
- .thumb_set MFS4TX_IRQHandler,Default_Handler
-
- .weak MFS5RX_IRQHandler
- .thumb_set MFS5RX_IRQHandler,Default_Handler
-
- .weak MFS5TX_IRQHandler
- .thumb_set MFS5TX_IRQHandler,Default_Handler
-
- .weak MFS6RX_IRQHandler
- .thumb_set MFS6RX_IRQHandler,Default_Handler
-
- .weak MFS6TX_IRQHandler
- .thumb_set MFS6TX_IRQHandler,Default_Handler
-
- .weak MFS7RX_IRQHandler
- .thumb_set MFS7RX_IRQHandler,Default_Handler
-
- .weak MFS7TX_IRQHandler
- .thumb_set MFS7TX_IRQHandler,Default_Handler
-
- .weak PPG_IRQHandler
- .thumb_set PPG_IRQHandler,Default_Handler
-
- .weak OSC_PLL_WC_IRQHandler
- .thumb_set OSC_PLL_WC_IRQHandler,Default_Handler
-
- .weak ADC0_IRQHandler
- .thumb_set ADC0_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak ADC2_IRQHandler
- .thumb_set ADC2_IRQHandler,Default_Handler
-
- .weak FRTIM_IRQHandler
- .thumb_set FRTIM_IRQHandler,Default_Handler
-
- .weak INCAP_IRQHandler
- .thumb_set INCAP_IRQHandler,Default_Handler
-
- .weak OUTCOMP_IRQHandler
- .thumb_set OUTCOMP_IRQHandler,Default_Handler
-
- .weak BTIM_IRQHandler
- .thumb_set BTIM_IRQHandler,Default_Handler
-
- .weak CAN0_IRQHandler
- .thumb_set CAN0_IRQHandler,Default_Handler
-
- .weak CAN1_IRQHandler
- .thumb_set CAN1_IRQHandler,Default_Handler
-
- .weak USBF_IRQHandler
- .thumb_set USBF_IRQHandler,Default_Handler
-
- .weak USBF_USBH_IRQHandler
- .thumb_set USBF_USBH_IRQHandler,Default_Handler
-
- .weak RESERVED_1_IRQHandler
- .thumb_set RESERVED_1_IRQHandler,Default_Handler
-
- .weak RESERVED_2_IRQHandler
- .thumb_set RESERVED_2_IRQHandler,Default_Handler
-
- .weak DMAC0_IRQHandler
- .thumb_set DMAC0_IRQHandler,Default_Handler
-
- .weak DMAC1_IRQHandler
- .thumb_set DMAC1_IRQHandler,Default_Handler
-
- .weak DMAC2_IRQHandler
- .thumb_set DMAC2_IRQHandler,Default_Handler
-
- .weak DMAC3_IRQHandler
- .thumb_set DMAC3_IRQHandler,Default_Handler
-
- .weak DMAC4_IRQHandler
- .thumb_set DMAC4_IRQHandler,Default_Handler
-
- .weak DMAC5_IRQHandler
- .thumb_set DMAC5_IRQHandler,Default_Handler
-
- .weak DMAC6_IRQHandler
- .thumb_set DMAC6_IRQHandler,Default_Handler
-
- .weak DMAC7_IRQHandler
- .thumb_set DMAC7_IRQHandler,Default_Handler
-
- .weak RESERVED_3_IRQHandler
- .thumb_set RESERVED_3_IRQHandler,Default_Handler
-
- .weak RESERVED_4_IRQHandler
- .thumb_set RESERVED_4_IRQHandler,Default_Handler
-
diff --git a/bsp/mb9bf506r/CMSIS/start_iar.S b/bsp/mb9bf506r/CMSIS/start_iar.S deleted file mode 100644 index b111ce9b43..0000000000 --- a/bsp/mb9bf506r/CMSIS/start_iar.S +++ /dev/null @@ -1,363 +0,0 @@ -;/*
-; * File : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2009-01-17 Bernard first version
-; * 2009-09-27 Bernard add protect when contex switch occurs
-; */
-
-#include "rtconfig.h"
-
- MODULE ?cstartup
-
-;; ICODE is the same segment as cstartup. By placing __low_level_init
-;; in the same segment, we make sure it can be reached with BL. */
-
- SECTION CSTACK:DATA:NOROOT(3)
- SECTION .icode:CODE:NOROOT(2)
-
-#ifdef RT_USING_UART2
- IMPORT MFS2RX_IRQHandler
-#endif
- PUBLIC __low_level_init
-
- PUBWEAK SystemInit_ExtMemCtl
- SECTION .text:CODE:REORDER(2)
- THUMB
-SystemInit_ExtMemCtl
- BX LR
-
-__low_level_init:
- ;; Initialize hardware.
- LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
- MOV R11, LR
- BLX R0
- LDR R1, =sfe(CSTACK) ; restore original stack pointer
- MSR MSP, R1
- MOV R0,#1
- ;; Return with BX to be independent of mode of caller
- BX R11
-
- ;; Forward declaration of sections.
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD __iar_program_start
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD CSV_IRQHandler ; Clock Super Visor
- DCD SWDT_IRQHandler ; Software Watchdog Timer
- DCD LVD_IRQHandler ; Low Voltage Detector
- DCD WFG_IRQHandler ; Wave Form Generator
- DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7
- DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15
- DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder
- DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0
- DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0
- DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1
- DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1
-#ifdef RT_USING_UART2
- DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2
-#else
- DCD NULL_IRQHandler ; MultiFunction Serial ch.2
-#endif
- DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2
- DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3
- DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3
- DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4
- DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4
- DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5
- DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5
- DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6
- DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6
- DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7
- DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7
- DCD PPG_IRQHandler ; PPG
- DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter
- DCD ADC0_IRQHandler ; ADC0
- DCD ADC1_IRQHandler ; ADC1
- DCD ADC2_IRQHandler ; ADC2
- DCD FRTIM_IRQHandler ; Free-run Timer
- DCD INCAP_IRQHandler ; Input Capture
- DCD OUTCOMP_IRQHandler ; Output Compare
- DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7
- DCD CAN0_IRQHandler ; CAN ch.0
- DCD CAN1_IRQHandler ; CAN ch.1
- DCD USBF_IRQHandler ; USB Function
- DCD USBF_USBH_IRQHandler ; USB Function / USB HOST
- DCD RESERVED_1_IRQHandler ; Reserved_1
- DCD RESERVED_2_IRQHandler ; Reserved_2
- DCD DMAC0_IRQHandler ; DMAC ch.0
- DCD DMAC1_IRQHandler ; DMAC ch.1
- DCD DMAC2_IRQHandler ; DMAC ch.2
- DCD DMAC3_IRQHandler ; DMAC ch.3
- DCD DMAC4_IRQHandler ; DMAC ch.4
- DCD DMAC5_IRQHandler ; DMAC ch.5
- DCD DMAC6_IRQHandler ; DMAC ch.6
- DCD DMAC7_IRQHandler ; DMAC ch.7
- DCD RESERVED_3_IRQHandler ; Reserved_3
- DCD RESERVED_4_IRQHandler ; Reserved_4
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER(1)
-NMI_Handler
- B NMI_Handler
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER(1)
-SVC_Handler
- B SVC_Handler
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
- PUBWEAK CSV_IRQHandler
- SECTION .text:CODE:REORDER(1)
-CSV_IRQHandler
- B CSV_IRQHandler
- PUBWEAK SWDT_IRQHandler
- SECTION .text:CODE:REORDER(1)
-SWDT_IRQHandler
- B SWDT_IRQHandler
- PUBWEAK LVD_IRQHandler
- SECTION .text:CODE:REORDER(1)
-LVD_IRQHandler
- B LVD_IRQHandler
- PUBWEAK WFG_IRQHandler
- SECTION .text:CODE:REORDER(1)
-WFG_IRQHandler
- B WFG_IRQHandler
- PUBWEAK EXINT0_7_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXINT0_7_IRQHandler
- B EXINT0_7_IRQHandler
- PUBWEAK EXINT8_15_IRQHandler
- SECTION .text:CODE:REORDER(1)
-EXINT8_15_IRQHandler
- B EXINT8_15_IRQHandler
- PUBWEAK DTIM_QDU_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DTIM_QDU_IRQHandler
- B DTIM_QDU_IRQHandler
- PUBWEAK MFS0RX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS0RX_IRQHandler
- B MFS0RX_IRQHandler
- PUBWEAK MFS0TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS0TX_IRQHandler
- B MFS0TX_IRQHandler
- PUBWEAK MFS1RX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS1RX_IRQHandler
- B MFS1RX_IRQHandler
- PUBWEAK MFS1TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS1TX_IRQHandler
- B MFS1TX_IRQHandler
- PUBWEAK NULL_IRQHandler
- SECTION .text:CODE:REORDER(1)
-NULL_IRQHandler
- B NULL_IRQHandler
- PUBWEAK MFS2TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS2TX_IRQHandler
- B MFS2TX_IRQHandler
- PUBWEAK MFS3RX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS3RX_IRQHandler
- B MFS3RX_IRQHandler
- PUBWEAK MFS3TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS3TX_IRQHandler
- B MFS3TX_IRQHandler
- PUBWEAK MFS4RX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS4RX_IRQHandler
- B MFS4RX_IRQHandler
- PUBWEAK MFS4TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS4TX_IRQHandler
- B MFS4TX_IRQHandler
- PUBWEAK MFS5RX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS5RX_IRQHandler
- B MFS5RX_IRQHandler
- PUBWEAK MFS5TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS5TX_IRQHandler
- B MFS5TX_IRQHandler
- PUBWEAK MFS6RX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS6RX_IRQHandler
- B MFS6RX_IRQHandler
- PUBWEAK MFS6TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS6TX_IRQHandler
- B MFS6TX_IRQHandler
- PUBWEAK MFS7RX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS7RX_IRQHandler
- B MFS7RX_IRQHandler
- PUBWEAK MFS7TX_IRQHandler
- SECTION .text:CODE:REORDER(1)
-MFS7TX_IRQHandler
- B MFS7TX_IRQHandler
- PUBWEAK PPG_IRQHandler
- SECTION .text:CODE:REORDER(1)
-PPG_IRQHandler
- B PPG_IRQHandler
- PUBWEAK OSC_PLL_WC_IRQHandler
- SECTION .text:CODE:REORDER(1)
-OSC_PLL_WC_IRQHandler
- B OSC_PLL_WC_IRQHandler
- PUBWEAK ADC0_IRQHandler
- SECTION .text:CODE:REORDER(1)
-ADC0_IRQHandler
- B ADC0_IRQHandler
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
- PUBWEAK ADC2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-ADC2_IRQHandler
- B ADC2_IRQHandler
- PUBWEAK FRTIM_IRQHandler
- SECTION .text:CODE:REORDER(1)
-FRTIM_IRQHandler
- B FRTIM_IRQHandler
- PUBWEAK INCAP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-INCAP_IRQHandler
- B INCAP_IRQHandler
- PUBWEAK OUTCOMP_IRQHandler
- SECTION .text:CODE:REORDER(1)
-OUTCOMP_IRQHandler
- B OUTCOMP_IRQHandler
- PUBWEAK BTIM_IRQHandler
- SECTION .text:CODE:REORDER(1)
-BTIM_IRQHandler
- B BTIM_IRQHandler
- PUBWEAK CAN0_IRQHandler
- SECTION .text:CODE:REORDER(1)
-CAN0_IRQHandler
- B CAN0_IRQHandler
- PUBWEAK CAN1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-CAN1_IRQHandler
- B CAN1_IRQHandler
- PUBWEAK USBF_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USBF_IRQHandler
- B USBF_IRQHandler
- PUBWEAK USBF_USBH_IRQHandler
- SECTION .text:CODE:REORDER(1)
-USBF_USBH_IRQHandler
- B USBF_USBH_IRQHandler
- PUBWEAK RESERVED_1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RESERVED_1_IRQHandler
- B RESERVED_1_IRQHandler
- PUBWEAK RESERVED_2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RESERVED_2_IRQHandler
- B RESERVED_2_IRQHandler
- PUBWEAK DMAC0_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC0_IRQHandler
- B DMAC0_IRQHandler
- PUBWEAK DMAC1_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC1_IRQHandler
- B DMAC1_IRQHandler
- PUBWEAK DMAC2_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC2_IRQHandler
- B DMAC2_IRQHandler
- PUBWEAK DMAC3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC3_IRQHandler
- B DMAC3_IRQHandler
- PUBWEAK DMAC4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC4_IRQHandler
- B DMAC4_IRQHandler
- PUBWEAK DMAC5_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC5_IRQHandler
- B DMAC5_IRQHandler
- PUBWEAK DMAC6_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC6_IRQHandler
- B DMAC6_IRQHandler
- PUBWEAK DMAC7_IRQHandler
- SECTION .text:CODE:REORDER(1)
-DMAC7_IRQHandler
- B DMAC7_IRQHandler
- PUBWEAK RESERVED_3_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RESERVED_3_IRQHandler
- B RESERVED_3_IRQHandler
- PUBWEAK RESERVED_4_IRQHandler
- SECTION .text:CODE:REORDER(1)
-RESERVED_4_IRQHandler
- B RESERVED_4_IRQHandler
-
- END
diff --git a/bsp/mb9bf506r/CMSIS/start_rvds.S b/bsp/mb9bf506r/CMSIS/start_rvds.S deleted file mode 100644 index fc755132c1..0000000000 --- a/bsp/mb9bf506r/CMSIS/start_rvds.S +++ /dev/null @@ -1,291 +0,0 @@ -; /*
-; * File : start_rvds.s
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2011-02-23 Bernard first implementation
-; */
-
-;* <<< Use Configuration Wizard in Context Menu >>>
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000200
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0.
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- DCD CSV_Handler ; 0: Clock Super Visor
- DCD SWDT_Handler ; 1: Software Watchdog Timer
- DCD LVD_Handler ; 2: Low Voltage Detector
- DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
- DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
- DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
- DCD DT_Handler ; 6: Dual Timer / Quad Decoder
- DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
- DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
- DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
- DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
- DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
- DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
- DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
- DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
- DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
- DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
- DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
- DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
- DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
- DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
- DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
- DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
- DCD PPG_Handler ; 23: PPG
- DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
- DCD ADC0_IRQHandler ; 25: ADC0
- DCD ADC1_IRQHandler ; 26: ADC1
- DCD ADC2_IRQHandler ; 27: ADC2
- DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
- DCD MFT_IPC_IRQHandler ; 29: Input Capture
- DCD MFT_OPC_IRQHandler ; 30: Output Compare
- DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
- DCD CAN0_IRQHandler ; 32: CAN ch.0
- DCD CAN1_IRQHandler ; 33: CAN ch.1
- DCD USBF_Handler ; 34: USB Function
- DCD USB_Handler ; 35: USB Function / USB HOST
- DCD DummyHandler ; 36: Reserved
- DCD DummyHandler ; 37: Reserved
- DCD DMAC0_Handler ; 38: DMAC ch.0
- DCD DMAC1_Handler ; 39: DMAC ch.1
- DCD DMAC2_Handler ; 40: DMAC ch.2
- DCD DMAC3_Handler ; 41: DMAC ch.3
- DCD DMAC4_Handler ; 42: DMAC ch.4
- DCD DMAC5_Handler ; 43: DMAC ch.5
- DCD DMAC6_Handler ; 44: DMAC ch.6
- DCD DMAC7_Handler ; 45: DMAC ch.7
- DCD DummyHandler ; 46: Reserved
- DCD DummyHandler ; 47: Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R1, = __initial_sp ; restore original stack pointer
- MSR MSP, R1
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT CSV_Handler [WEAK]
- EXPORT SWDT_Handler [WEAK]
- EXPORT LVD_Handler [WEAK]
- EXPORT MFT_WG_IRQHandler [WEAK]
- EXPORT INT0_7_Handler [WEAK]
- EXPORT INT8_15_Handler [WEAK]
- EXPORT DT_Handler [WEAK]
- EXPORT MFS0RX_IRQHandler [WEAK]
- EXPORT MFS0TX_IRQHandler [WEAK]
- EXPORT MFS1RX_IRQHandler [WEAK]
- EXPORT MFS1TX_IRQHandler [WEAK]
- EXPORT MFS2RX_IRQHandler [WEAK]
- EXPORT MFS2TX_IRQHandler [WEAK]
- EXPORT MFS3RX_IRQHandler [WEAK]
- EXPORT MFS3TX_IRQHandler [WEAK]
- EXPORT MFS4RX_IRQHandler [WEAK]
- EXPORT MFS4TX_IRQHandler [WEAK]
- EXPORT MFS5RX_IRQHandler [WEAK]
- EXPORT MFS5TX_IRQHandler [WEAK]
- EXPORT MFS6RX_IRQHandler [WEAK]
- EXPORT MFS6TX_IRQHandler [WEAK]
- EXPORT MFS7RX_IRQHandler [WEAK]
- EXPORT MFS7TX_IRQHandler [WEAK]
- EXPORT PPG_Handler [WEAK]
- EXPORT TIM_IRQHandler [WEAK]
- EXPORT ADC0_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT ADC2_IRQHandler [WEAK]
- EXPORT MFT_FRT_IRQHandler [WEAK]
- EXPORT MFT_IPC_IRQHandler [WEAK]
- EXPORT MFT_OPC_IRQHandler [WEAK]
- EXPORT BT_IRQHandler [WEAK]
- EXPORT CAN0_IRQHandler [WEAK]
- EXPORT CAN1_IRQHandler [WEAK]
- EXPORT USBF_Handler [WEAK]
- EXPORT USB_Handler [WEAK]
- EXPORT DMAC0_Handler [WEAK]
- EXPORT DMAC1_Handler [WEAK]
- EXPORT DMAC2_Handler [WEAK]
- EXPORT DMAC3_Handler [WEAK]
- EXPORT DMAC4_Handler [WEAK]
- EXPORT DMAC5_Handler [WEAK]
- EXPORT DMAC6_Handler [WEAK]
- EXPORT DMAC7_Handler [WEAK]
- EXPORT DummyHandler [WEAK]
-
-CSV_Handler
-SWDT_Handler
-LVD_Handler
-MFT_WG_IRQHandler
-INT0_7_Handler
-INT8_15_Handler
-DT_Handler
-MFS0RX_IRQHandler
-MFS0TX_IRQHandler
-MFS1RX_IRQHandler
-MFS1TX_IRQHandler
-MFS2RX_IRQHandler
-MFS2TX_IRQHandler
-MFS3RX_IRQHandler
-MFS3TX_IRQHandler
-MFS4RX_IRQHandler
-MFS4TX_IRQHandler
-MFS5RX_IRQHandler
-MFS5TX_IRQHandler
-MFS6RX_IRQHandler
-MFS6TX_IRQHandler
-MFS7RX_IRQHandler
-MFS7TX_IRQHandler
-PPG_Handler
-TIM_IRQHandler
-ADC0_IRQHandler
-ADC1_IRQHandler
-ADC2_IRQHandler
-MFT_FRT_IRQHandler
-MFT_IPC_IRQHandler
-MFT_OPC_IRQHandler
-BT_IRQHandler
-CAN0_IRQHandler
-CAN1_IRQHandler
-USBF_Handler
-USB_Handler
-DMAC0_Handler
-DMAC1_Handler
-DMAC2_Handler
-DMAC3_Handler
-DMAC4_Handler
-DMAC5_Handler
-DMAC6_Handler
-DMAC7_Handler
-DummyHandler
- B .
- ENDP
- ALIGN
-
-; User Initial Stack & Heap
-
- IF :DEF:__MICROLIB
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
- ELSE
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
- ENDIF
-
- END
diff --git a/bsp/mb9bf506r/CMSIS/system_mb9bf50x.c b/bsp/mb9bf506r/CMSIS/system_mb9bf50x.c deleted file mode 100644 index 21cd7a3f26..0000000000 --- a/bsp/mb9bf506r/CMSIS/system_mb9bf50x.c +++ /dev/null @@ -1,111 +0,0 @@ -/************************************************************************/
-/* (C) Fujitsu Semiconductor Europe GmbH */
-/* */
-/* The following software deliverable is intended for and must only be */
-/* used for reference and in an evaluation laboratory environment. */
-/* It is provided on an as-is basis without charge and is subject to */
-/* alterations. */
-/* It is the user�s obligation to fully test the software in its */
-/* environment and to ensure proper functionality, qualification and */
-/* compliance with component specifications. */
-/* */
-/* In the event the software deliverable includes the use of open */
-/* source components, the provisions of the governing open source */
-/* license agreement shall apply with respect to such software */
-/* deliverable. */
-/* FSEU does not warrant that the deliverables do not infringe any */
-/* third party intellectual property right (IPR). In the event that */
-/* the deliverables infringe a third party IPR it is the sole */
-/* responsibility of the customer to obtain necessary licenses to */
-/* continue the usage of the deliverable. */
-/* */
-/* To the maximum extent permitted by applicable law FSEU disclaims all */
-/* warranties, whether express or implied, in particular, but not */
-/* limited to, warranties of merchantability and fitness for a */
-/* particular purpose for which the deliverable is not designated. */
-/* */
-/* To the maximum extent permitted by applicable law, FSEU's liability */
-/* is restricted to intention and gross negligence. */
-/* FSEU is not liable for consequential damages. */
-/* */
-/* (V1.4) */
-/************************************************************************/
-
-#include "mb9bf506r.h"
-
-/*
- * 80MHz : Master Clock
- */
-const uint32_t SystemFrequency = 80000000UL;
-
-uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */
-uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */
-uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */
-uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */
-uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */
-
-/*
- * Prototype of internal function
- */
-static void ClockInit(void);
-static void HwwdtDisable(void);
-
-
-/*
- * Setup the microcontroller system
- */
-void SystemInit (void)
-{
- HwwdtDisable(); /* Disable Hardware Watchdog */
- ClockInit(); /* Initialize Clock */
-}
-/*
- * Initialize Clock
- */
-static void ClockInit(void)
-{
- /*set Main clock stabilization
- wait time to 2ms*/
- FM3_CRG->CSW_TMR = 0x79;
- /*Enable Main Oscilator*/
- FM3_CRG->SCM_CTL |= 1<<1;
- /*Wait stabilization end*/
- while(!(FM3_CRG->SCM_STR & 0x02));
-
- /* sub CLK enable */
- //FM3_CRG->SCM_CTL |= 0x08;
- //while(!(FM3_CRG->SCM_STR & 0x08));
-
- /*Set PLL stabilization
- wait time to 512uS*/
- FM3_CRG->PSW_TMR |= 2;
- /*Set PLL to 80MHz*/
- FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/
- FM3_CRG->PLL_CTL2 = 19; /*N = 20*/
- /*Enable PLL*/
- FM3_CRG->SCM_CTL |= 0x10;
- /*Set bus prescalers*/
- FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/
- FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/
- FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/
- FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/
- /*Wait PLL stabilizatoin end*/
- while(!(FM3_CRG->SCM_STR & 0x10));
- /*Select PLL for main clock*/
- FM3_CRG->SCM_CTL |= 2<<5;
- /*Wait PLL to be connected*/
- while((FM3_CRG->SCM_STR & 0xe0) != 0x40);
-
-}
-/*
- * Stop HW Watchdog Timer
- */
-static void HwwdtDisable(void)
-{
- /* UnLock (except WDG_CTL) */
- FM3_HWWDT->WDG_LCK = 0x1ACCE551;
- /* UnLock (WDG_CTL) */
- FM3_HWWDT->WDG_LCK = 0xE5331AAE;
- /* Disable WDG */
- FM3_HWWDT->WDG_CTL = 0x00;
-}
diff --git a/bsp/mb9bf506r/applications/startup.c b/bsp/mb9bf506r/applications/startup.c index 1e07900a95..7cbb64d976 100644 --- a/bsp/mb9bf506r/applications/startup.c +++ b/bsp/mb9bf506r/applications/startup.c @@ -16,7 +16,7 @@ #include <rtthread.h> #include "board.h" -#include "mb9bf506r.h" + #ifdef RT_USING_FINSH #include <finsh.h> #endif @@ -109,9 +109,6 @@ int main(void) { /* disable interrupt first */ rt_hw_interrupt_disable(); - - /* init system setting */ - SystemInit(); /* startup RT-Thread RTOS */ rtthread_startup(); diff --git a/bsp/mb9bf506r/drivers/board.c b/bsp/mb9bf506r/drivers/board.c index 6d0486dd30..fff2233dfe 100644 --- a/bsp/mb9bf506r/drivers/board.c +++ b/bsp/mb9bf506r/drivers/board.c @@ -16,13 +16,11 @@ #include <rtthread.h>
#include "board.h"
-#include "mb9bf506r.h"
+#include "mcu.h"
#include "serial.h"
#include "nand.h"
-extern const uint32_t SystemFrequency;
-
/**
* @addtogroup FM3
*/
@@ -48,8 +46,8 @@ void SysTick_Handler(void) */
void rt_hw_board_init(void)
{
- /* init systick */
- SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND);
+ /* init systick */
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* initialize UART device */
rt_hw_serial_init();
diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h b/bsp/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h new file mode 100644 index 0000000000..e45d004cc4 --- /dev/null +++ b/bsp/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h @@ -0,0 +1,209 @@ +/**************************************************
+ *
+ * This file shall be included in appropriate CMSIS header
+ * files, to provide required functions and intrinsics when
+ * building with the IAR C/C++ Compiler for ARM (iccarm).
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 50409 $
+ *
+ **************************************************/
+
+#ifndef __CMSIS_IAR_H__
+#define __CMSIS_IAR_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#include <intrinsics.h>
+
+#if (__CORE__ == __ARM6M__)
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz
+ #define __SSAT __cmsis_iar_ssat
+#endif
+
+#pragma diag_suppress=Pe940
+#pragma diag_suppress=Pe177
+
+#define __enable_irq __enable_interrupt
+#define __disable_irq __disable_interrupt
+#define __NOP __no_operation
+
+#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
+
+#if (__VER__ < 6010002) /* If iccarm version is older than 6.10.2 ---------- */
+
+static uint32_t __get_APSR(void)
+{
+ __ASM("mrs r0, apsr");
+}
+
+static uint32_t __get_xPSR(void)
+{
+ __ASM("mrs r0, psr"); /* assembler does not know "xpsr" */
+}
+
+#endif /* __VER__ < 6010002 */
+
+static uint32_t __get_IPSR(void)
+{
+ __ASM("mrs r0, ipsr");
+}
+
+static uint32_t __get_PSR(void)
+{
+ __ASM("mrs r0, psr");
+}
+
+static uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+}
+
+static void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+}
+
+static uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+}
+
+static void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+}
+
+static __INLINE void __WFI(void)
+{
+ __ASM ("wfi");
+}
+
+static __INLINE void __WFE(void)
+{
+ __ASM ("wfe");
+}
+
+static __INLINE void __SEV(void)
+{
+ __ASM ("sev");
+}
+
+static uint32_t __REV16(uint32_t value)
+{
+ __ASM("rev16 r0, r0");
+}
+
+#else /* __VER__ < 6020000 */
+
+static uint32_t __get_xPSR(void)
+{
+ return __get_PSR(); /* __get_PSR() intrinsic introduced in iccarm 6.20 */
+}
+
+#endif /* __VER__ < 6020000 */
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
+
+static __INLINE void __enable_fault_irq(void)
+{
+ __ASM ("cpsie f");
+}
+
+static __INLINE void __disable_fault_irq(void)
+{
+ __ASM ("cpsid f");
+}
+
+static uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+}
+
+static uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+}
+
+static uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+}
+
+static uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+}
+
+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+}
+
+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+}
+
+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+}
+
+static __INLINE void __CLREX(void)
+{
+ __ASM ("clrex");
+}
+
+#else /* __VER__ >= 6020000 --------------------- */
+
+#define __LDREXW __LDREX
+#define __STREXW __STREX
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#endif /* __VER__ < 6020000 */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if (__CORTEX_M == 0x04) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
+
+static uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
+ __ASM("vmrs r0, fpscr");
+#else
+ return(0);
+#endif
+}
+
+static void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
+ __ASM("vmsr fpscr, r0");
+#endif
+}
+
+#endif /* __VER__ < 6020000 */
+
+#endif /* (__CORTEX_M == 0x04) */
+
+static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+}
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_IAR_H__ */
diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cm3.h b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..db1716ad95 --- /dev/null +++ b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1612 @@ +/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..adb07b5d34 --- /dev/null +++ b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..624c175fd5 --- /dev/null +++ b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/mb9bf506r/libraries/CMSIS/RTOS/cmsis_os.h b/bsp/mb9bf506r/libraries/CMSIS/RTOS/cmsis_os.h new file mode 100644 index 0000000000..6c9c78bb89 --- /dev/null +++ b/bsp/mb9bf506r/libraries/CMSIS/RTOS/cmsis_os.h @@ -0,0 +1,770 @@ +/* ----------------------------------------------------------------------
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * $Date: 5. March 2012
+ * $Revision: V0.03
+ *
+ * Project: CMSIS-RTOS API
+ * Title: cmsis_os.h RT-Thread header file
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * Version 0.03
+ * osKernelStart added, optional feature: main started as thread
+ * osSemaphores have standard behaviour
+ * osTimerCreate does not start the timer, added osTimerStart
+ * osThreadPass is renamed to osThreadYield
+ * -------------------------------------------------------------------- */
+
+/**
+\page cmsis_os_h Header File Template: cmsis_os.h
+
+The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
+Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
+its implementation.
+
+The file cmsis_os.h contains:
+ - CMSIS-RTOS API function definitions
+ - struct definitions for parameters and return types
+ - status and priority values used by CMSIS-RTOS API functions
+ - macros for defining threads and other kernel objects
+
+
+<b>Name conventions and header file modifications</b>
+
+All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
+Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
+All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
+
+Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
+These definitions can be specific to the underlying RTOS kernel.
+
+Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
+compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
+
+
+<b>Function calls from interrupt service routines</b>
+
+The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
+ - \ref osSignalSet
+ - \ref osSemaphoreRelease
+ - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
+ - \ref osMessagePut, \ref osMessageGet
+ - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
+
+Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
+from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
+
+Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
+If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
+
+
+<b>Define and reference object definitions</b>
+
+With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file
+that is used troughtout a project as shown below:
+
+<i>Header File</i>
+\code
+#include <cmsis_os.h> // CMSIS RTOS header file
+
+// Thread definition
+extern void thread_sample (void const *argument); // function prototype
+osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+// Pool definition
+osPoolDef(MyPool, 10, long);
+\endcode
+
+
+This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
+present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
+used throughout the whole project.
+
+<i>Example</i>
+\code
+#include "osObjects.h" // Definition of the CMSIS-RTOS objects
+\endcode
+
+\code
+#define osObjectExternal // Objects will be defined as external symbols
+#include "osObjects.h" // Reference to the CMSIS-RTOS objects
+\endcode
+
+*/
+
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+
+#include "rtthread.h"
+
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version
+#define osCMSIS 0x00003 ///< API version (main [31:16] .sub [15:0])
+
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number.
+#define osCMSIS_RTT 0x10001 ///< RTOS identification and version (main [31:16] .sub [15:0])
+
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "RT-Thread V1.1.0" ///< RTOS identification string
+
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available
+#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
+#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
+#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
+#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore 30 ///< maximum count for SemaphoreInit function
+#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum {
+ osPriorityIdle = -3, ///< priority: idle (lowest)
+ osPriorityLow = -2, ///< priority: low
+ osPriorityBelowNormal = -1, ///< priority: below normal
+ osPriorityNormal = 0, ///< priority: normal (default)
+ osPriorityAboveNormal = +1, ///< priority: above normal
+ osPriorityHigh = +2, ///< priority: high
+ osPriorityRealtime = +3, ///< priority: realtime (highest)
+ osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+
+/// Timeout value
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value
+
+/// Status code values returned by CMSIS-RTOS functions
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum {
+ osOK = 0, ///< function completed; no event occurred.
+ osEventSignal = 0x08, ///< function completed; signal event occurred.
+ osEventMessage = 0x10, ///< function completed; message event occurred.
+ osEventMail = 0x20, ///< function completed; mail event occurred.
+ osEventTimeout = 0x40, ///< function completed; timeout occurred.
+ osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+ osErrorResource = 0x81, ///< resource not available: a specified resource was not available.
+ osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period.
+ osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+ osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object.
+ osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority.
+ osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+ osErrorValue = 0x86, ///< value of a parameter is out of range.
+ osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
+ os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
+} osStatus;
+
+
+/// Timer type value for the timer definition
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum {
+ osTimerOnce = 0, ///< one-shot timer
+ osTimerPeriodic = 1 ///< repeating timer
+} os_timer_type;
+
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument);
+
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument);
+
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef struct rt_thread *osThreadId;
+
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef struct rt_timer *osTimerId;
+
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef struct rt_mutex *osMutexId;
+
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef struct rt_semaphore *osSemaphoreId;
+
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct rt_mempool *osPoolId;
+
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct rt_messagequeue *osMessageQId;
+
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct rt_mailbox *osMailQId;
+
+
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_thread_def {
+ /* rt object */
+ char name[RT_NAME_MAX]; /**< the name of thread */
+ rt_uint8_t type; /**< type of object */
+ rt_uint8_t flags; /**< thread's flags */
+
+#ifdef RT_USING_MODULE
+ void *module_id; /**< id of application module */
+#endif
+
+ rt_list_t list; /**< the object list */
+ rt_list_t tlist; /**< the thread list */
+
+ /* stack point and entry */
+ void *sp; /**< stack point */
+ void *entry; /**< entry */
+ void *parameter; /**< parameter */
+ void *stack_addr; /**< stack address */
+ rt_uint16_t stack_size; /**< stack size */
+
+ /* error code */
+ rt_err_t error; /**< error code */
+
+ rt_uint8_t stat; /**< thread stat */
+
+ /* priority */
+ osPriority current_priority; /**< current priority */
+ osPriority init_priority; /**< initialized priority */
+#if RT_THREAD_PRIORITY_MAX > 32
+ rt_uint8_t number;
+ rt_uint8_t high_mask;
+#endif
+ rt_uint32_t number_mask;
+
+#if defined(RT_USING_EVENT)
+ /* thread event */
+ rt_uint32_t event_set;
+ rt_uint8_t event_info;
+#endif
+
+ rt_ubase_t init_tick; /**< thread's initialized tick */
+ rt_ubase_t remaining_tick; /**< remaining tick */
+
+ struct rt_timer thread_timer; /**< built-in thread timer */
+
+ void (*cleanup)(struct rt_thread *tid); /**< cleanup function when thread exit */
+
+ rt_uint32_t user_data; /**< private user data beyond this thread */
+} osThreadDef_t;
+
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_timer_def {
+ struct rt_object parent; /**< inherit from rt_object */
+
+ rt_list_t list; /**< the node of timer list */
+
+ void (*timeout_func)(void *parameter); /**< timeout function */
+ void *parameter; /**< timeout function's parameter */
+
+ rt_tick_t init_tick; /**< timer timeout tick */
+ rt_tick_t timeout_tick; /**< timeout tick */
+} osTimerDef_t;
+
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_mutex_def {
+ uint32_t dummy; ///< dummy value.
+} osMutexDef_t;
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_semaphore_def {
+ uint32_t dummy; ///< dummy value.
+} osSemaphoreDef_t;
+
+/// Definition structure for memory block allocation
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_pool_def {
+ uint32_t pool_sz; ///< number of items (elements) in the pool
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< pointer to memory for pool
+} osPoolDef_t;
+
+/// Definition structure for message queue
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_messageQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< memory array for messages
+} osMessageQDef_t;
+
+/// Definition structure for mail queue
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_mailQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< memory array for mail
+} osMailQDef_t;
+
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
+/// However the struct may be extended at the end.
+typedef struct {
+ osStatus status; ///< status code: event or error information
+ union {
+ uint32_t v; ///< message as 32-bit value
+ void *p; ///< message or mail as void pointer
+ int32_t signals; ///< signal flags
+ } value; ///< event value
+ union {
+ osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
+ osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
+ } def; ///< event definition
+} osEvent;
+
+
+// ==== Kernel Control Functions ====
+
+/// Start the RTOS Kernel with executing the specified thread.
+/// \param[in] thread_def thread definition referenced with \ref osThread.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+osStatus osKernelStart (osThreadDef_t *thread_def, void *argument);
+
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+
+
+// ==== Thread Management ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param name name of the thread function.
+/// \param priority initial priority of the thread function.
+/// \param instances number of possible thread instances.
+/// \param stacksz stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osThreadDef(name, priority, instances, stacksz) \
+extern osThreadDef_t os_thread_def_##name
+#else // define the object
+#define osThreadDef(name, priority, instances, stacksz) \
+osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz) }
+#endif
+
+/// Access a Thread defintion.
+/// \param name name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name) \
+&os_thread_def_##name
+
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in] thread_def thread definition referenced with \ref osThread.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+
+/// Change priority of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] priority new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+
+/// Get current priority of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+
+
+
+// ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay)
+/// \param[in] millisec time delay value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+
+#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+osEvent osWait (uint32_t millisec);
+
+#endif // Generic Wait available
+
+
+// ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param name name of the timer object.
+/// \param function name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osTimerDef(name, function) \
+extern osTimerDef_t os_timer_def_##name
+#else // define the object
+#define osTimerDef(name, function) \
+osTimerDef_t os_timer_def_##name = \
+{ (function) }
+#endif
+
+/// Access a Timer definition.
+/// \param name name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create a timer.
+/// \param[in] timer_def timer object referenced with \ref osTimer.
+/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in] argument argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \param[in] millisec time delay value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+
+/// Stop the timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+
+
+// ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signal);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signal);
+
+/// Get Signal Flags status of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalGet (osThreadId thread_id);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+osEvent osSignalWait (int32_t signals, uint32_t millisec);
+
+
+// ==== Mutex Management ====
+
+/// Define a Mutex.
+/// \param name name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osMutexDef(name) \
+extern osMutexDef_t os_mutex_def_##name
+#else // define the object
+#define osMutexDef(name) \
+osMutexDef_t os_mutex_def_##name = { 0 }
+#endif
+
+/// Access a Mutex defintion.
+/// \param name name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name) \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object
+/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/// Release a Mutex that was obtained by \ref osMutexWait
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+
+
+// ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available
+
+/// Define a Semaphore object.
+/// \param name name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osSemaphoreDef(name) \
+extern osSemaphoreDef_t os_semaphore_def_##name
+#else // define the object
+#define osSemaphoreDef(name) \
+osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#endif
+
+/// Access a Semaphore definition.
+/// \param name name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name) \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object used for managing resources
+/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in] count number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphore.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphore.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+
+#endif // Semaphore available
+
+// ==== Memory Pool Management Functions ====
+
+#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
+
+/// \brief Define a Memory Pool.
+/// \param name name of the memory pool.
+/// \param no maximum number of objects (elements) in the memory pool.
+/// \param type data type of a single object (element).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osPoolDef(name, no, type) \
+extern osPoolDef_t os_pool_def_##name
+#else // define the object
+#define osPoolDef(name, no, type) \
+osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param name name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a memory pool
+/// \param[in] pool_def memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a memory pool
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a memory pool and set memory block to zero
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a specific memory pool
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in] block address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif // Memory Pool Management available
+
+
+// ==== Message Queue Management Functions ====
+
+#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available
+
+/// \brief Create a Message Queue Definition.
+/// \param name name of the queue.
+/// \param queue_sz maximum number of messages in the queue.
+/// \param type data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osMessageQDef(name, queue_sz, type) \
+extern osMessageQDef_t os_messageQ_def_##name
+#else // define the object
+#define osMessageQDef(name, queue_sz, type) \
+osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type) }
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param name name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue.
+/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] info message information.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+#endif // Message Queues available
+
+
+// ==== Mail Queue Management Functions ====
+
+#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available
+
+/// \brief Create a Mail Queue Definition
+/// \param name name of the queue
+/// \param queue_sz maximum number of messages in queue
+/// \param type data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern osMailQDef_t os_mailQ_def_##name
+#else // define the object
+#define osMailQDef(name, queue_sz, type) \
+osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof (type) }
+#endif
+
+/// \brief Access a Mail Queue Definition
+/// \param name name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name) \
+&os_mailQ_def_##name
+
+/// Create and Initialize mail queue
+/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block from a mail
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block from a mail and set memory block to zero
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can shall filled with mail or NULL in case error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a mail to a queue
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+
+/// Get a mail from a queue
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+
+/// Free a memory block from a mail
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+
+#endif // Mail Queues available
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _CMSIS_OS_H
diff --git a/bsp/mb9bf506r/CMSIS/mb9bf506r.h b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h index 3f0a9481c3..6ffd751df9 100644 --- a/bsp/mb9bf506r/CMSIS/mb9bf506r.h +++ b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h @@ -32,8 +32,8 @@ /************************************************************************/
/* */
/* Header File for Device MB9BF506R */
-/* Version V1.00 */
-/* Date 2011-01-21 */
+/* Version V1.03 */
+/* Date 2011-05-16 */
/* */
/************************************************************************/
@@ -65,57 +65,57 @@ typedef enum IRQn UsageFault_IRQn = -10, /* 6 Usage Fault */
SVC_IRQn = -5, /* 11 SV Call */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor */
- PendSVC_IRQn = -2, /* 14 Pend SV */
+ PendSV_IRQn = -2, /* 14 Pend SV */
SysTick_IRQn = -1, /* 15 System Tick */
- CSV_IRQn = 0, /* Clock Super Visor */
- SWDT_IRQn = 1, /* Software Watchdog Timer */
- LVD_IRQn = 2, /* Low Voltage Detector */
- WFG_IRQn = 3, /* Wave Form Generator */
- EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */
- EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */
- DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */
- MFS0RX_IRQn = 7, /* MultiFunction Serial ch.0 */
- MFS0TX_IRQn = 8, /* MultiFunction Serial ch.0 */
- MFS1RX_IRQn = 9, /* MultiFunction Serial ch.1 */
- MFS1TX_IRQn = 10, /* MultiFunction Serial ch.1 */
- MFS2RX_IRQn = 11, /* MultiFunction Serial ch.2 */
- MFS2TX_IRQn = 12, /* MultiFunction Serial ch.2 */
- MFS3RX_IRQn = 13, /* MultiFunction Serial ch.3 */
- MFS3TX_IRQn = 14, /* MultiFunction Serial ch.3 */
- MFS4RX_IRQn = 15, /* MultiFunction Serial ch.4 */
- MFS4TX_IRQn = 16, /* MultiFunction Serial ch.4 */
- MFS5RX_IRQn = 17, /* MultiFunction Serial ch.5 */
- MFS5TX_IRQn = 18, /* MultiFunction Serial ch.5 */
- MFS6RX_IRQn = 19, /* MultiFunction Serial ch.6 */
- MFS6TX_IRQn = 20, /* MultiFunction Serial ch.6 */
- MFS7RX_IRQn = 21, /* MultiFunction Serial ch.7 */
- MFS7TX_IRQn = 22, /* MultiFunction Serial ch.7 */
- PPG_IRQn = 23, /* PPG */
- OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */
- ADC0_IRQn = 25, /* ADC0 */
- ADC1_IRQn = 26, /* ADC1 */
- ADC2_IRQn = 27, /* ADC2 */
- FRTIM_IRQn = 28, /* Free-run Timer */
- INCAP_IRQn = 29, /* Input Capture */
- OUTCOMP_IRQn = 30, /* Output Compare */
- BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */
- CAN0_IRQn = 32, /* CAN ch.0 */
- CAN1_IRQn = 33, /* CAN ch.1 */
- USBF_IRQn = 34, /* USB Function */
- USBF_USBH_IRQn = 35, /* USB Function / USB HOST */
- /* Reserved = 36, */
- /* Reserved = 37, */
- DMAC0_IRQn = 38, /* DMAC ch.0 */
- DMAC1_IRQn = 39, /* DMAC ch.1 */
- DMAC2_IRQn = 40, /* DMAC ch.2 */
- DMAC3_IRQn = 41, /* DMAC ch.3 */
- DMAC4_IRQn = 42, /* DMAC ch.4 */
- DMAC5_IRQn = 43, /* DMAC ch.5 */
- DMAC6_IRQn = 44, /* DMAC ch.6 */
- DMAC7_IRQn = 45, /* DMAC ch.7 */
- /* Reserved = 46, */
- /* Reserved = 47, */
+ CSV_IRQn = 0, /* Clock Super Visor */
+ SWDT_IRQn = 1, /* Software Watchdog Timer */
+ LVD_IRQn = 2, /* Low Voltage Detector */
+ WFG_IRQn = 3, /* Wave Form Generator */
+ EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */
+ EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */
+ DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */
+ MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */
+ MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */
+ MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */
+ MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */
+ MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */
+ MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */
+ MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */
+ MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */
+ MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */
+ MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */
+ MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */
+ MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */
+ MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */
+ MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */
+ MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */
+ MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */
+ PPG_IRQn = 23, /* PPG */
+ OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */
+ ADC0_IRQn = 25, /* ADC0 */
+ ADC1_IRQn = 26, /* ADC1 */
+ ADC2_IRQn = 27, /* ADC2 */
+ FRTIM_IRQn = 28, /* Free-run Timer */
+ INCAP_IRQn = 29, /* Input Capture */
+ OUTCOMP_IRQn = 30, /* Output Compare */
+ BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */
+ CAN0_IRQn = 32, /* CAN ch.0 */
+ CAN1_IRQn = 33, /* CAN ch.1 */
+ USBF_IRQn = 34, /* USB Function */
+ USBF_USBH_IRQn = 35, /* USB Function / USB HOST */
+ /* Reserved = 36 */
+ /* Reserved = 37 */
+ DMAC0_IRQn = 38, /* DMAC ch.0 */
+ DMAC1_IRQn = 39, /* DMAC ch.1 */
+ DMAC2_IRQn = 40, /* DMAC ch.2 */
+ DMAC3_IRQn = 41, /* DMAC ch.3 */
+ DMAC4_IRQn = 42, /* DMAC ch.4 */
+ DMAC5_IRQn = 43, /* DMAC ch.5 */
+ DMAC6_IRQn = 44, /* DMAC ch.6 */
+ DMAC7_IRQn = 45 /* DMAC ch.7 */
+ /* Reserved = 46 */
+ /* Reserved = 47 */
} IRQn_Type;
@@ -140,19 +140,6391 @@ typedef enum IRQn #endif
/******************************************************************************
+ * Peripheral register bit fields
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash_IF_MODULE register bit fields */
+typedef struct stc_flash_if_faszr_field
+{
+ __IO uint32_t ASZ0 : 1;
+ __IO uint32_t ASZ1 : 1;
+} stc_flash_if_faszr_field_t;
+
+typedef struct stc_flash_if_frwtr_field
+{
+ __IO uint32_t RWT0 : 1;
+ __IO uint32_t RWT1 : 1;
+} stc_flash_if_frwtr_field_t;
+
+typedef struct stc_flash_if_fstr_field
+{
+ __IO uint32_t RDY : 1;
+ __IO uint32_t HNG : 1;
+ __IO uint32_t EER : 1;
+} stc_flash_if_fstr_field_t;
+
+typedef struct stc_flash_if_fsyndn_field
+{
+ __IO uint32_t SD0 : 1;
+ __IO uint32_t SD1 : 1;
+ __IO uint32_t SD2 : 1;
+} stc_flash_if_fsyndn_field_t;
+
+typedef struct stc_flash_if_crtrmm_field
+{
+ __IO uint32_t TRMM0 : 1;
+ __IO uint32_t TRMM1 : 1;
+ __IO uint32_t TRMM2 : 1;
+ __IO uint32_t TRMM3 : 1;
+ __IO uint32_t TRMM4 : 1;
+ __IO uint32_t TRMM5 : 1;
+ __IO uint32_t TRMM6 : 1;
+ __IO uint32_t TRMM7 : 1;
+ __IO uint32_t TRMM8 : 1;
+ __IO uint32_t TRMM9 : 1;
+} stc_flash_if_crtrmm_field_t;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock_Reset_MODULE register bit fields */
+typedef struct stc_crg_scm_ctl_field
+{
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t MOSCE : 1;
+ uint8_t RESERVED2 : 1;
+ __IO uint8_t SOSCE : 1;
+ __IO uint8_t PLLE : 1;
+ __IO uint8_t RCS0 : 1;
+ __IO uint8_t RCS1 : 1;
+ __IO uint8_t RCS2 : 1;
+} stc_crg_scm_ctl_field_t;
+
+typedef struct stc_crg_scm_str_field
+{
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t MORDY : 1;
+ uint8_t RESERVED2 : 1;
+ __IO uint8_t SORDY : 1;
+ __IO uint8_t PLRDY : 1;
+ __IO uint8_t RCM0 : 1;
+ __IO uint8_t RCM1 : 1;
+ __IO uint8_t RCM2 : 1;
+} stc_crg_scm_str_field_t;
+
+typedef struct stc_crg_rst_str_field
+{
+ __IO uint16_t PONR : 1;
+ __IO uint16_t INITX : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t SWDT : 1;
+ __IO uint16_t HWDT : 1;
+ __IO uint16_t CSVR : 1;
+ __IO uint16_t FCSR : 1;
+ __IO uint16_t SRST : 1;
+} stc_crg_rst_str_field_t;
+
+typedef struct stc_crg_bsc_psr_field
+{
+ __IO uint8_t BSR0 : 1;
+ __IO uint8_t BSR1 : 1;
+ __IO uint8_t BSR2 : 1;
+} stc_crg_bsc_psr_field_t;
+
+typedef struct stc_crg_apbc0_psr_field
+{
+ __IO uint8_t APBC00 : 1;
+ __IO uint8_t APBC01 : 1;
+} stc_crg_apbc0_psr_field_t;
+
+typedef struct stc_crg_apbc1_psr_field
+{
+ __IO uint8_t APBC10 : 1;
+ __IO uint8_t APBC11 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t APBC1RST : 1;
+ uint8_t RESERVED2 : 2;
+ __IO uint8_t APBC1EN : 1;
+} stc_crg_apbc1_psr_field_t;
+
+typedef struct stc_crg_apbc2_psr_field
+{
+ __IO uint8_t APBC20 : 1;
+ __IO uint8_t APBC21 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t APBC2RST : 1;
+ uint8_t RESERVED2 : 2;
+ __IO uint8_t APBC2EN : 1;
+} stc_crg_apbc2_psr_field_t;
+
+typedef struct stc_crg_swc_psr_field
+{
+ __IO uint8_t SWDS0 : 1;
+ __IO uint8_t SWDS1 : 1;
+ uint8_t RESERVED1 : 5;
+ __IO uint8_t TESTB : 1;
+} stc_crg_swc_psr_field_t;
+
+typedef struct stc_crg_ttc_psr_field
+{
+ __IO uint8_t TTC : 1;
+} stc_crg_ttc_psr_field_t;
+
+typedef struct stc_crg_csw_tmr_field
+{
+ __IO uint8_t MOWT0 : 1;
+ __IO uint8_t MOWT1 : 1;
+ __IO uint8_t MOWT2 : 1;
+ __IO uint8_t MOWT3 : 1;
+ __IO uint8_t SOWT0 : 1;
+ __IO uint8_t SOWT1 : 1;
+ __IO uint8_t SOWT2 : 1;
+} stc_crg_csw_tmr_field_t;
+
+typedef struct stc_crg_psw_tmr_field
+{
+ __IO uint8_t POWT0 : 1;
+ __IO uint8_t POWT1 : 1;
+ __IO uint8_t POWT2 : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t PINC : 1;
+} stc_crg_psw_tmr_field_t;
+
+typedef struct stc_crg_pll_ctl1_field
+{
+ __IO uint8_t PLLM0 : 1;
+ __IO uint8_t PLLM1 : 1;
+ __IO uint8_t PLLM2 : 1;
+ __IO uint8_t PLLM3 : 1;
+ __IO uint8_t PLLK0 : 1;
+ __IO uint8_t PLLK1 : 1;
+ __IO uint8_t PLLK2 : 1;
+ __IO uint8_t PLLK3 : 1;
+} stc_crg_pll_ctl1_field_t;
+
+typedef struct stc_crg_pll_ctl2_field
+{
+ __IO uint8_t PLLN0 : 1;
+ __IO uint8_t PLLN1 : 1;
+ __IO uint8_t PLLN2 : 1;
+ __IO uint8_t PLLN3 : 1;
+ __IO uint8_t PLLN4 : 1;
+ __IO uint8_t PLLN5 : 1;
+} stc_crg_pll_ctl2_field_t;
+
+typedef struct stc_crg_csv_ctl_field
+{
+ __IO uint16_t MCSVE : 1;
+ __IO uint16_t SCSVE : 1;
+ uint16_t RESERVED1 : 6;
+ __IO uint16_t FCSDE : 1;
+ __IO uint16_t FCSRE : 1;
+ uint16_t RESERVED2 : 2;
+ __IO uint16_t FCD0 : 1;
+ __IO uint16_t FCD1 : 1;
+ __IO uint16_t FCD2 : 1;
+} stc_crg_csv_ctl_field_t;
+
+typedef struct stc_crg_csv_str_field
+{
+ __IO uint8_t MCMF : 1;
+ __IO uint8_t SCMF : 1;
+} stc_crg_csv_str_field_t;
+
+typedef struct stc_crg_dbwdt_ctl_field
+{
+ uint8_t RESERVED1 : 5;
+ __IO uint8_t DPSWBE : 1;
+ uint8_t RESERVED2 : 1;
+ __IO uint8_t DPHWBE : 1;
+} stc_crg_dbwdt_ctl_field_t;
+
+typedef struct stc_crg_int_enr_field
+{
+ __IO uint8_t MCSE : 1;
+ __IO uint8_t SCSE : 1;
+ __IO uint8_t PCSE : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t FCSE : 1;
+} stc_crg_int_enr_field_t;
+
+typedef struct stc_crg_int_str_field
+{
+ __IO uint8_t MCSI : 1;
+ __IO uint8_t SCSI : 1;
+ __IO uint8_t PCSI : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t FCSI : 1;
+} stc_crg_int_str_field_t;
+
+typedef struct stc_crg_int_clr_field
+{
+ __IO uint8_t MCSC : 1;
+ __IO uint8_t SCSC : 1;
+ __IO uint8_t PCSC : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t FCSC : 1;
+} stc_crg_int_clr_field_t;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* HWWDT_MODULE register bit fields */
+typedef struct stc_hwwdt_wdg_ctl_field
+{
+ __IO uint8_t INTEN : 1;
+ __IO uint8_t RESEN : 1;
+} stc_hwwdt_wdg_ctl_field_t;
+
+typedef struct stc_hwwdt_wdg_ris_field
+{
+ __IO uint8_t RIS : 1;
+} stc_hwwdt_wdg_ris_field_t;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* SWWDT_MODULE register bit fields */
+typedef struct stc_swwdt_wdogcontrol_field
+{
+ __IO uint8_t INTEN : 1;
+ __IO uint8_t RESEN : 1;
+} stc_swwdt_wdogcontrol_field_t;
+
+typedef struct stc_swwdt_wdogris_field
+{
+ __IO uint8_t RIS : 1;
+} stc_swwdt_wdogris_field_t;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* DTIM_MODULE register bit fields */
+typedef struct stc_dtim_timer1control_field
+{
+ __IO uint32_t ONESHOT : 1;
+ __IO uint32_t TIMERSIZE : 1;
+ __IO uint32_t TIMERPRE0 : 1;
+ __IO uint32_t TIMERPRE1 : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t INTENABLE : 1;
+ __IO uint32_t TIMERMODE : 1;
+ __IO uint32_t TIMEREN : 1;
+} stc_dtim_timer1control_field_t;
+
+typedef struct stc_dtim_timer1ris_field
+{
+ __IO uint32_t TIMERXRIS : 1;
+} stc_dtim_timer1ris_field_t;
+
+typedef struct stc_dtim_timer1mis_field
+{
+ __IO uint32_t TIMERXRIS : 1;
+} stc_dtim_timer1mis_field_t;
+
+typedef struct stc_dtim_timer2control_field
+{
+ __IO uint32_t ONESHOT : 1;
+ __IO uint32_t TIMERSIZE : 1;
+ __IO uint32_t TIMERPRE0 : 1;
+ __IO uint32_t TIMERPRE1 : 1;
+ uint32_t RESERVED1 : 1;
+ __IO uint32_t INTENABLE : 1;
+ __IO uint32_t TIMERMODE : 1;
+ __IO uint32_t TIMEREN : 1;
+} stc_dtim_timer2control_field_t;
+
+typedef struct stc_dtim_timer2ris_field
+{
+ __IO uint32_t TIMERXRIS : 1;
+} stc_dtim_timer2ris_field_t;
+
+typedef struct stc_dtim_timer2mis_field
+{
+ __IO uint32_t TIMERXRIS : 1;
+} stc_dtim_timer2mis_field_t;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* MFT_FRT_MODULE register bit fields */
+typedef struct stc_mft_frt_tcsa0_field
+{
+ __IO uint16_t CLK0 : 1;
+ __IO uint16_t CLK1 : 1;
+ __IO uint16_t CLK2 : 1;
+ __IO uint16_t CLK3 : 1;
+ __IO uint16_t SCLR : 1;
+ __IO uint16_t MODE : 1;
+ __IO uint16_t STOP : 1;
+ __IO uint16_t BFE : 1;
+ __IO uint16_t ICRE : 1;
+ __IO uint16_t ICLR : 1;
+ uint16_t RESERVED1 : 3;
+ __IO uint16_t IRQZE : 1;
+ __IO uint16_t IRQZF : 1;
+ __IO uint16_t ECKE : 1;
+} stc_mft_frt_tcsa0_field_t;
+
+typedef struct stc_mft_frt_tcsb0_field
+{
+ __IO uint16_t AD0E : 1;
+ __IO uint16_t AD1E : 1;
+ __IO uint16_t AD2E : 1;
+} stc_mft_frt_tcsb0_field_t;
+
+typedef struct stc_mft_frt_tcsa1_field
+{
+ __IO uint16_t CLK0 : 1;
+ __IO uint16_t CLK1 : 1;
+ __IO uint16_t CLK2 : 1;
+ __IO uint16_t CLK3 : 1;
+ __IO uint16_t SCLR : 1;
+ __IO uint16_t MODE : 1;
+ __IO uint16_t STOP : 1;
+ __IO uint16_t BFE : 1;
+ __IO uint16_t ICRE : 1;
+ __IO uint16_t ICLR : 1;
+ uint16_t RESERVED1 : 3;
+ __IO uint16_t IRQZE : 1;
+ __IO uint16_t IRQZF : 1;
+ __IO uint16_t ECKE : 1;
+} stc_mft_frt_tcsa1_field_t;
+
+typedef struct stc_mft_frt_tcsb1_field
+{
+ __IO uint16_t AD0E : 1;
+ __IO uint16_t AD1E : 1;
+ __IO uint16_t AD2E : 1;
+} stc_mft_frt_tcsb1_field_t;
+
+typedef struct stc_mft_frt_tcsa2_field
+{
+ __IO uint16_t CLK0 : 1;
+ __IO uint16_t CLK1 : 1;
+ __IO uint16_t CLK2 : 1;
+ __IO uint16_t CLK3 : 1;
+ __IO uint16_t SCLR : 1;
+ __IO uint16_t MODE : 1;
+ __IO uint16_t STOP : 1;
+ __IO uint16_t BFE : 1;
+ __IO uint16_t ICRE : 1;
+ __IO uint16_t ICLR : 1;
+ uint16_t RESERVED1 : 3;
+ __IO uint16_t IRQZE : 1;
+ __IO uint16_t IRQZF : 1;
+ __IO uint16_t ECKE : 1;
+} stc_mft_frt_tcsa2_field_t;
+
+typedef struct stc_mft_frt_tcsb2_field
+{
+ __IO uint16_t AD0E : 1;
+ __IO uint16_t AD1E : 1;
+ __IO uint16_t AD2E : 1;
+} stc_mft_frt_tcsb2_field_t;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* MFT_OCU_MODULE register bit fields */
+typedef struct stc_mft_ocu_ocsa10_field
+{
+ __IO uint8_t CST0 : 1;
+ __IO uint8_t CST1 : 1;
+ __IO uint8_t BDIS0 : 1;
+ __IO uint8_t BDIS1 : 1;
+ __IO uint8_t IOE0 : 1;
+ __IO uint8_t IOE1 : 1;
+ __IO uint8_t IOP0 : 1;
+ __IO uint8_t IOP1 : 1;
+} stc_mft_ocu_ocsa10_field_t;
+
+typedef struct stc_mft_ocu_ocsb10_field
+{
+ __IO uint8_t OTD0 : 1;
+ __IO uint8_t OTD1 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t CMOD : 1;
+ __IO uint8_t BTS0 : 1;
+ __IO uint8_t BTS1 : 1;
+} stc_mft_ocu_ocsb10_field_t;
+
+typedef struct stc_mft_ocu_ocsa32_field
+{
+ __IO uint8_t CST2 : 1;
+ __IO uint8_t CST3 : 1;
+ __IO uint8_t BDIS2 : 1;
+ __IO uint8_t BDIS3 : 1;
+ __IO uint8_t IOE2 : 1;
+ __IO uint8_t IOE3 : 1;
+ __IO uint8_t IOP2 : 1;
+ __IO uint8_t IOP3 : 1;
+} stc_mft_ocu_ocsa32_field_t;
+
+typedef struct stc_mft_ocu_ocsb32_field
+{
+ __IO uint8_t OTD2 : 1;
+ __IO uint8_t OTD3 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t CMOD : 1;
+ __IO uint8_t BTS2 : 1;
+ __IO uint8_t BTS3 : 1;
+} stc_mft_ocu_ocsb32_field_t;
+
+typedef struct stc_mft_ocu_ocsa54_field
+{
+ __IO uint8_t CST4 : 1;
+ __IO uint8_t CST5 : 1;
+ __IO uint8_t BDIS4 : 1;
+ __IO uint8_t BDIS5 : 1;
+ __IO uint8_t IOE4 : 1;
+ __IO uint8_t IOE5 : 1;
+ __IO uint8_t IOP4 : 1;
+ __IO uint8_t IOP5 : 1;
+} stc_mft_ocu_ocsa54_field_t;
+
+typedef struct stc_mft_ocu_ocsb54_field
+{
+ __IO uint8_t OTD4 : 1;
+ __IO uint8_t OTD5 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t CMOD : 1;
+ __IO uint8_t BTS4 : 1;
+ __IO uint8_t BTS5 : 1;
+} stc_mft_ocu_ocsb54_field_t;
+
+typedef struct stc_mft_ocu_ocsc_field
+{
+ __IO uint8_t MOD0 : 1;
+ __IO uint8_t MOD1 : 1;
+ __IO uint8_t MOD2 : 1;
+ __IO uint8_t MOD3 : 1;
+ __IO uint8_t MOD4 : 1;
+ __IO uint8_t MOD5 : 1;
+} stc_mft_ocu_ocsc_field_t;
+
+typedef struct stc_mft_ocu_ocfs10_field
+{
+ __IO uint8_t FSO00 : 1;
+ __IO uint8_t FSO01 : 1;
+ __IO uint8_t FSO02 : 1;
+ __IO uint8_t FSO03 : 1;
+ __IO uint8_t FSO10 : 1;
+ __IO uint8_t FSO11 : 1;
+ __IO uint8_t FSO12 : 1;
+ __IO uint8_t FSO13 : 1;
+} stc_mft_ocu_ocfs10_field_t;
+
+typedef struct stc_mft_ocu_ocfs32_field
+{
+ __IO uint8_t FSO20 : 1;
+ __IO uint8_t FSO21 : 1;
+ __IO uint8_t FSO22 : 1;
+ __IO uint8_t FSO23 : 1;
+ __IO uint8_t FSO30 : 1;
+ __IO uint8_t FSO31 : 1;
+ __IO uint8_t FSO32 : 1;
+ __IO uint8_t FSO33 : 1;
+} stc_mft_ocu_ocfs32_field_t;
+
+typedef struct stc_mft_ocu_ocfs54_field
+{
+ __IO uint8_t FSO40 : 1;
+ __IO uint8_t FSO41 : 1;
+ __IO uint8_t FSO42 : 1;
+ __IO uint8_t FSO43 : 1;
+ __IO uint8_t FSO50 : 1;
+ __IO uint8_t FSO51 : 1;
+ __IO uint8_t FSO52 : 1;
+ __IO uint8_t FSO53 : 1;
+} stc_mft_ocu_ocfs54_field_t;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* MFT_WFG_MODULE register bit fields */
+typedef struct stc_mft_wfg_wfsa10_field
+{
+ __IO uint16_t DCK0 : 1;
+ __IO uint16_t DCK1 : 1;
+ __IO uint16_t DCK2 : 1;
+ __IO uint16_t TMD0 : 1;
+ __IO uint16_t TMD1 : 1;
+ __IO uint16_t TMD2 : 1;
+ __IO uint16_t GTEN0 : 1;
+ __IO uint16_t GTEN1 : 1;
+ __IO uint16_t PSEL0 : 1;
+ __IO uint16_t PSEL1 : 1;
+ __IO uint16_t PGEN0 : 1;
+ __IO uint16_t PGEN1 : 1;
+ __IO uint16_t DMOD : 1;
+} stc_mft_wfg_wfsa10_field_t;
+
+typedef struct stc_mft_wfg_wfsa32_field
+{
+ __IO uint16_t DCK0 : 1;
+ __IO uint16_t DCK1 : 1;
+ __IO uint16_t DCK2 : 1;
+ __IO uint16_t TMD0 : 1;
+ __IO uint16_t TMD1 : 1;
+ __IO uint16_t TMD2 : 1;
+ __IO uint16_t GTEN0 : 1;
+ __IO uint16_t GTEN1 : 1;
+ __IO uint16_t PSEL0 : 1;
+ __IO uint16_t PSEL1 : 1;
+ __IO uint16_t PGEN0 : 1;
+ __IO uint16_t PGEN1 : 1;
+ __IO uint16_t DMOD : 1;
+} stc_mft_wfg_wfsa32_field_t;
+
+typedef struct stc_mft_wfg_wfsa54_field
+{
+ __IO uint16_t DCK0 : 1;
+ __IO uint16_t DCK1 : 1;
+ __IO uint16_t DCK2 : 1;
+ __IO uint16_t TMD0 : 1;
+ __IO uint16_t TMD1 : 1;
+ __IO uint16_t TMD2 : 1;
+ __IO uint16_t GTEN0 : 1;
+ __IO uint16_t GTEN1 : 1;
+ __IO uint16_t PSEL0 : 1;
+ __IO uint16_t PSEL1 : 1;
+ __IO uint16_t PGEN0 : 1;
+ __IO uint16_t PGEN1 : 1;
+ __IO uint16_t DMOD : 1;
+} stc_mft_wfg_wfsa54_field_t;
+
+typedef struct stc_mft_wfg_wfir_field
+{
+ __IO uint16_t DTIF : 1;
+ __IO uint16_t DTIC : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t TMIF10 : 1;
+ __IO uint16_t TMIC10 : 1;
+ __IO uint16_t TMIE10 : 1;
+ __IO uint16_t TMIS10 : 1;
+ __IO uint16_t TMIF32 : 1;
+ __IO uint16_t TMIC32 : 1;
+ __IO uint16_t TMIE32 : 1;
+ __IO uint16_t TMIS32 : 1;
+ __IO uint16_t TMIF54 : 1;
+ __IO uint16_t TMIC54 : 1;
+ __IO uint16_t TMIE54 : 1;
+ __IO uint16_t TMIS54 : 1;
+} stc_mft_wfg_wfir_field_t;
+
+typedef struct stc_mft_wfg_nzcl_field
+{
+ __IO uint16_t DTIE : 1;
+ __IO uint16_t NWS0 : 1;
+ __IO uint16_t NWS1 : 1;
+ __IO uint16_t NWS2 : 1;
+ __IO uint16_t SDTI : 1;
+} stc_mft_wfg_nzcl_field_t;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* MFT_ICU_MODULE register bit fields */
+typedef struct stc_mft_icu_icfs10_field
+{
+ __IO uint8_t FSI00 : 1;
+ __IO uint8_t FSI01 : 1;
+ __IO uint8_t FSI02 : 1;
+ __IO uint8_t FSI03 : 1;
+ __IO uint8_t FSI10 : 1;
+ __IO uint8_t FSI11 : 1;
+ __IO uint8_t FSI12 : 1;
+ __IO uint8_t FSI13 : 1;
+} stc_mft_icu_icfs10_field_t;
+
+typedef struct stc_mft_icu_icfs32_field
+{
+ __IO uint8_t FSI20 : 1;
+ __IO uint8_t FSI21 : 1;
+ __IO uint8_t FSI22 : 1;
+ __IO uint8_t FSI23 : 1;
+ __IO uint8_t FSI30 : 1;
+ __IO uint8_t FSI31 : 1;
+ __IO uint8_t FSI32 : 1;
+ __IO uint8_t FSI33 : 1;
+} stc_mft_icu_icfs32_field_t;
+
+typedef struct stc_mft_icu_icsa10_field
+{
+ __IO uint8_t EG00 : 1;
+ __IO uint8_t EG01 : 1;
+ __IO uint8_t EG10 : 1;
+ __IO uint8_t EG11 : 1;
+ __IO uint8_t ICE0 : 1;
+ __IO uint8_t ICE1 : 1;
+ __IO uint8_t ICP0 : 1;
+ __IO uint8_t ICP1 : 1;
+} stc_mft_icu_icsa10_field_t;
+
+typedef struct stc_mft_icu_icsb10_field
+{
+ __IO uint8_t IEI0 : 1;
+ __IO uint8_t IEI1 : 1;
+} stc_mft_icu_icsb10_field_t;
+
+typedef struct stc_mft_icu_icsa32_field
+{
+ __IO uint8_t EG20 : 1;
+ __IO uint8_t EG21 : 1;
+ __IO uint8_t EG30 : 1;
+ __IO uint8_t EG31 : 1;
+ __IO uint8_t ICE2 : 1;
+ __IO uint8_t ICE3 : 1;
+ __IO uint8_t ICP2 : 1;
+ __IO uint8_t ICP3 : 1;
+} stc_mft_icu_icsa32_field_t;
+
+typedef struct stc_mft_icu_icsb32_field
+{
+ __IO uint8_t IEI2 : 1;
+ __IO uint8_t IEI3 : 1;
+} stc_mft_icu_icsb32_field_t;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* MFT_ADCMP_MODULE register bit fields */
+typedef struct stc_mft_adcmp_acsb_field
+{
+ __IO uint8_t BDIS0 : 1;
+ __IO uint8_t BDIS1 : 1;
+ __IO uint8_t BDIS2 : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t BTS0 : 1;
+ __IO uint8_t BTS1 : 1;
+ __IO uint8_t BTS2 : 1;
+} stc_mft_adcmp_acsb_field_t;
+
+typedef struct stc_mft_adcmp_acsa_field
+{
+ __IO uint16_t CE00 : 1;
+ __IO uint16_t CE01 : 1;
+ __IO uint16_t CE10 : 1;
+ __IO uint16_t CE11 : 1;
+ __IO uint16_t CE20 : 1;
+ __IO uint16_t CE21 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t SEL00 : 1;
+ __IO uint16_t SEL01 : 1;
+ __IO uint16_t SEL10 : 1;
+ __IO uint16_t SEL11 : 1;
+ __IO uint16_t SEL20 : 1;
+ __IO uint16_t SEL21 : 1;
+} stc_mft_adcmp_acsa_field_t;
+
+typedef struct stc_mft_adcmp_atsa_field
+{
+ __IO uint16_t AD0S0 : 1;
+ __IO uint16_t AD0S1 : 1;
+ __IO uint16_t AD1S0 : 1;
+ __IO uint16_t AD1S1 : 1;
+ __IO uint16_t AD2S0 : 1;
+ __IO uint16_t AD2S1 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t AD0P0 : 1;
+ __IO uint16_t AD0P1 : 1;
+ __IO uint16_t AD1P0 : 1;
+ __IO uint16_t AD1P1 : 1;
+ __IO uint16_t AD2P0 : 1;
+ __IO uint16_t AD2P1 : 1;
+} stc_mft_adcmp_atsa_field_t;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* MFT_PPG_MODULE register bit fields */
+typedef struct stc_mft_ppg_ttcr0_field
+{
+ __IO uint8_t STR0 : 1;
+ __IO uint8_t MONI0 : 1;
+ __IO uint8_t CS00 : 1;
+ __IO uint8_t CS01 : 1;
+ __IO uint8_t TRG0O : 1;
+ __IO uint8_t TRG2O : 1;
+ __IO uint8_t TRG4O : 1;
+ __IO uint8_t TRG6O : 1;
+} stc_mft_ppg_ttcr0_field_t;
+
+typedef struct stc_mft_ppg_ttcr1_field
+{
+ __IO uint8_t STR1 : 1;
+ __IO uint8_t MONI1 : 1;
+ __IO uint8_t CS10 : 1;
+ __IO uint8_t CS11 : 1;
+ __IO uint8_t TRG1O : 1;
+ __IO uint8_t TRG3O : 1;
+ __IO uint8_t TRG5O : 1;
+ __IO uint8_t TRG7O : 1;
+} stc_mft_ppg_ttcr1_field_t;
+
+typedef struct stc_mft_ppg_trg_field
+{
+ __IO uint16_t PEN00 : 1;
+ __IO uint16_t PEN01 : 1;
+ __IO uint16_t PEN02 : 1;
+ __IO uint16_t PEN03 : 1;
+ __IO uint16_t PEN04 : 1;
+ __IO uint16_t PEN05 : 1;
+ __IO uint16_t PEN06 : 1;
+ __IO uint16_t PEN07 : 1;
+ __IO uint16_t PEN08 : 1;
+ __IO uint16_t PEN09 : 1;
+ __IO uint16_t PEN10 : 1;
+ __IO uint16_t PEN11 : 1;
+ __IO uint16_t PEN12 : 1;
+ __IO uint16_t PEN13 : 1;
+ __IO uint16_t PEN14 : 1;
+ __IO uint16_t PEN15 : 1;
+} stc_mft_ppg_trg_field_t;
+
+typedef struct stc_mft_ppg_revc_field
+{
+ __IO uint16_t REV00 : 1;
+ __IO uint16_t REV01 : 1;
+ __IO uint16_t REV02 : 1;
+ __IO uint16_t REV03 : 1;
+ __IO uint16_t REV04 : 1;
+ __IO uint16_t REV05 : 1;
+ __IO uint16_t REV06 : 1;
+ __IO uint16_t REV07 : 1;
+ __IO uint16_t REV08 : 1;
+ __IO uint16_t REV09 : 1;
+ __IO uint16_t REV10 : 1;
+ __IO uint16_t REV11 : 1;
+ __IO uint16_t REV12 : 1;
+ __IO uint16_t REV13 : 1;
+ __IO uint16_t REV14 : 1;
+ __IO uint16_t REV15 : 1;
+} stc_mft_ppg_revc_field_t;
+
+typedef struct stc_mft_ppg_ppgc1_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc0_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc0_field_t;
+
+typedef struct stc_mft_ppg_ppgc3_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc3_field_t;
+
+typedef struct stc_mft_ppg_ppgc2_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc2_field_t;
+
+typedef struct stc_mft_ppg_gatec0_field
+{
+ __IO uint8_t EDGE0 : 1;
+ __IO uint8_t STRG0 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t EDGE2 : 1;
+ __IO uint8_t STRG2 : 1;
+} stc_mft_ppg_gatec0_field_t;
+
+typedef struct stc_mft_ppg_ppgc5_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc5_field_t;
+
+typedef struct stc_mft_ppg_ppgc4_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc4_field_t;
+
+typedef struct stc_mft_ppg_ppgc7_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc7_field_t;
+
+typedef struct stc_mft_ppg_ppgc6_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc6_field_t;
+
+typedef struct stc_mft_ppg_gatec4_field
+{
+ __IO uint8_t EDGE4 : 1;
+ __IO uint8_t STRG4 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t EDGE6 : 1;
+ __IO uint8_t STRG6 : 1;
+} stc_mft_ppg_gatec4_field_t;
+
+typedef struct stc_mft_ppg_ppgc9_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc9_field_t;
+
+typedef struct stc_mft_ppg_ppgc8_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc8_field_t;
+
+typedef struct stc_mft_ppg_ppgc11_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc11_field_t;
+
+typedef struct stc_mft_ppg_ppgc10_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc10_field_t;
+
+typedef struct stc_mft_ppg_gatec8_field
+{
+ __IO uint8_t EDGE8 : 1;
+ __IO uint8_t STRG8 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t EDGE10 : 1;
+ __IO uint8_t STRG10 : 1;
+} stc_mft_ppg_gatec8_field_t;
+
+typedef struct stc_mft_ppg_ppgc13_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc13_field_t;
+
+typedef struct stc_mft_ppg_ppgc12_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc12_field_t;
+
+typedef struct stc_mft_ppg_ppgc15_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc15_field_t;
+
+typedef struct stc_mft_ppg_ppgc14_field
+{
+ __IO uint8_t TTRG : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t PCS0 : 1;
+ __IO uint8_t PCS1 : 1;
+ __IO uint8_t INTM : 1;
+ __IO uint8_t PUF : 1;
+ __IO uint8_t PIE : 1;
+} stc_mft_ppg_ppgc14_field_t;
+
+typedef struct stc_mft_ppg_gatec12_field
+{
+ __IO uint8_t EDGE12 : 1;
+ __IO uint8_t STRG12 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t EDGE14 : 1;
+ __IO uint8_t STRG14 : 1;
+} stc_mft_ppg_gatec12_field_t;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* BT_PPG_MODULE register bit fields */
+typedef struct stc_bt_ppg_tmcr_field
+{
+ __IO uint16_t STRG : 1;
+ __IO uint16_t CTEN : 1;
+ __IO uint16_t MDSE : 1;
+ __IO uint16_t OSEL : 1;
+ __IO uint16_t FMD0 : 1;
+ __IO uint16_t FMD1 : 1;
+ __IO uint16_t FMD2 : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t EGS0 : 1;
+ __IO uint16_t EGS1 : 1;
+ __IO uint16_t PMSK : 1;
+ __IO uint16_t RTGEN : 1;
+ __IO uint16_t CKS0 : 1;
+ __IO uint16_t CKS1 : 1;
+ __IO uint16_t CKS2 : 1;
+} stc_bt_ppg_tmcr_field_t;
+
+typedef struct stc_bt_ppg_stc_field
+{
+ __IO uint8_t UDIR : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t TGIR : 1;
+ uint8_t RESERVED2 : 1;
+ __IO uint8_t UDIE : 1;
+ uint8_t RESERVED3 : 1;
+ __IO uint8_t TGIE : 1;
+} stc_bt_ppg_stc_field_t;
+
+typedef struct stc_bt_ppg_tmcr2_field
+{
+ __IO uint8_t CKS3 : 1;
+} stc_bt_ppg_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* BT_PWM_MODULE register bit fields */
+typedef struct stc_bt_pwm_tmcr_field
+{
+ __IO uint16_t STRG : 1;
+ __IO uint16_t CTEN : 1;
+ __IO uint16_t MDSE : 1;
+ __IO uint16_t OSEL : 1;
+ __IO uint16_t FMD0 : 1;
+ __IO uint16_t FMD1 : 1;
+ __IO uint16_t FMD2 : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t EGS0 : 1;
+ __IO uint16_t EGS1 : 1;
+ __IO uint16_t PMSK : 1;
+ __IO uint16_t RTGEN : 1;
+ __IO uint16_t CKS0 : 1;
+ __IO uint16_t CKS1 : 1;
+ __IO uint16_t CKS2 : 1;
+} stc_bt_pwm_tmcr_field_t;
+
+typedef struct stc_bt_pwm_stc_field
+{
+ __IO uint8_t UDIR : 1;
+ __IO uint8_t DTIR : 1;
+ __IO uint8_t TGIR : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t UDIE : 1;
+ __IO uint8_t DTIE : 1;
+ __IO uint8_t TGIE : 1;
+} stc_bt_pwm_stc_field_t;
+
+typedef struct stc_bt_pwm_tmcr2_field
+{
+ __IO uint8_t CKS3 : 1;
+} stc_bt_pwm_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* BT_RT_MODULE register bit fields */
+typedef struct stc_bt_rt_tmcr_field
+{
+ __IO uint16_t STRG : 1;
+ __IO uint16_t CTEN : 1;
+ __IO uint16_t MDSE : 1;
+ __IO uint16_t OSEL : 1;
+ __IO uint16_t FMD0 : 1;
+ __IO uint16_t FMD1 : 1;
+ __IO uint16_t FMD2 : 1;
+ __IO uint16_t T32 : 1;
+ __IO uint16_t EGS0 : 1;
+ __IO uint16_t EGS1 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t CKS0 : 1;
+ __IO uint16_t CKS1 : 1;
+ __IO uint16_t CKS2 : 1;
+} stc_bt_rt_tmcr_field_t;
+
+typedef struct stc_bt_rt_stc_field
+{
+ __IO uint8_t UDIR : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t TGIR : 1;
+ uint8_t RESERVED2 : 1;
+ __IO uint8_t UDIE : 1;
+ uint8_t RESERVED3 : 1;
+ __IO uint8_t TGIE : 1;
+} stc_bt_rt_stc_field_t;
+
+typedef struct stc_bt_rt_tmcr2_field
+{
+ __IO uint8_t CKS3 : 1;
+} stc_bt_rt_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* BT_PWC_MODULE register bit fields */
+typedef struct stc_bt_pwc_tmcr_field
+{
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t CTEN : 1;
+ __IO uint16_t MDSE : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t FMD0 : 1;
+ __IO uint16_t FMD1 : 1;
+ __IO uint16_t FMD2 : 1;
+ __IO uint16_t T32 : 1;
+ __IO uint16_t EGS0 : 1;
+ __IO uint16_t EGS1 : 1;
+ __IO uint16_t EGS2 : 1;
+ uint16_t RESERVED3 : 1;
+ __IO uint16_t CKS0 : 1;
+ __IO uint16_t CKS1 : 1;
+ __IO uint16_t CKS2 : 1;
+} stc_bt_pwc_tmcr_field_t;
+
+typedef struct stc_bt_pwc_stc_field
+{
+ __IO uint8_t OVIR : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t EDIR : 1;
+ uint8_t RESERVED2 : 1;
+ __IO uint8_t OVIE : 1;
+ uint8_t RESERVED3 : 1;
+ __IO uint8_t EDIE : 1;
+ __IO uint8_t ERR : 1;
+} stc_bt_pwc_stc_field_t;
+
+typedef struct stc_bt_pwc_tmcr2_field
+{
+ __IO uint8_t CKS3 : 1;
+} stc_bt_pwc_tmcr2_field_t;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* BTIOSEL03_MODULE register bit fields */
+typedef struct stc_btiosel03_btsel0123_field
+{
+ __IO uint8_t SEL01_0 : 1;
+ __IO uint8_t SEL01_1 : 1;
+ __IO uint8_t SEL01_2 : 1;
+ __IO uint8_t SEL01_3 : 1;
+ __IO uint8_t SEL23_0 : 1;
+ __IO uint8_t SEL23_1 : 1;
+ __IO uint8_t SEL23_2 : 1;
+ __IO uint8_t SEL23_3 : 1;
+} stc_btiosel03_btsel0123_field_t;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* BTIOSEL47_MODULE register bit fields */
+typedef struct stc_btiosel47_btsel4567_field
+{
+ __IO uint8_t SEL45_0 : 1;
+ __IO uint8_t SEL45_1 : 1;
+ __IO uint8_t SEL45_2 : 1;
+ __IO uint8_t SEL45_3 : 1;
+ __IO uint8_t SEL67_0 : 1;
+ __IO uint8_t SEL67_1 : 1;
+ __IO uint8_t SEL67_2 : 1;
+ __IO uint8_t SEL67_3 : 1;
+} stc_btiosel47_btsel4567_field_t;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* SBSSR_MODULE register bit fields */
+typedef struct stc_sbssr_btsssr_field
+{
+ __IO uint16_t SSR0 : 1;
+ __IO uint16_t SSR1 : 1;
+ __IO uint16_t SSR2 : 1;
+ __IO uint16_t SSR3 : 1;
+ __IO uint16_t SSR4 : 1;
+ __IO uint16_t SSR5 : 1;
+ __IO uint16_t SSR6 : 1;
+ __IO uint16_t SSR7 : 1;
+ __IO uint16_t SSR8 : 1;
+ __IO uint16_t SSR9 : 1;
+ __IO uint16_t SSR10 : 1;
+ __IO uint16_t SSR11 : 1;
+ __IO uint16_t SSR12 : 1;
+ __IO uint16_t SSR13 : 1;
+ __IO uint16_t SSR14 : 1;
+ __IO uint16_t SSR15 : 1;
+} stc_sbssr_btsssr_field_t;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* QPRC_MODULE register bit fields */
+typedef struct stc_qprc_qicr_field
+{
+ __IO uint16_t QPCMIE : 1;
+ __IO uint16_t QPCMF : 1;
+ __IO uint16_t QPRCMIE : 1;
+ __IO uint16_t QPRCMF : 1;
+ __IO uint16_t OUZIE : 1;
+ __IO uint16_t UFDF : 1;
+ __IO uint16_t OFDF : 1;
+ __IO uint16_t ZIIF : 1;
+ __IO uint16_t CDCIE : 1;
+ __IO uint16_t CDCF : 1;
+ __IO uint16_t DIRPC : 1;
+ __IO uint16_t DIROU : 1;
+ __IO uint16_t QPCNRCMIE : 1;
+ __IO uint16_t QPCNRCMF : 1;
+} stc_qprc_qicr_field_t;
+
+typedef struct stc_qprc_qicrl_field
+{
+ __IO uint8_t QPCMIE : 1;
+ __IO uint8_t QPCMF : 1;
+ __IO uint8_t QPRCMIE : 1;
+ __IO uint8_t QPRCMF : 1;
+ __IO uint8_t OUZIE : 1;
+ __IO uint8_t UFDF : 1;
+ __IO uint8_t OFDF : 1;
+ __IO uint8_t ZIIF : 1;
+} stc_qprc_qicrl_field_t;
+
+typedef struct stc_qprc_qicrh_field
+{
+ __IO uint8_t CDCIE : 1;
+ __IO uint8_t CDCF : 1;
+ __IO uint8_t DIRPC : 1;
+ __IO uint8_t DIROU : 1;
+ __IO uint8_t QPCNRCMIE : 1;
+ __IO uint8_t QPCNRCMF : 1;
+} stc_qprc_qicrh_field_t;
+
+typedef struct stc_qprc_qcr_field
+{
+ __IO uint16_t PCM0 : 1;
+ __IO uint16_t PCM1 : 1;
+ __IO uint16_t RCM0 : 1;
+ __IO uint16_t RCM1 : 1;
+ __IO uint16_t PSTP : 1;
+ __IO uint16_t CGSC : 1;
+ __IO uint16_t RSEL : 1;
+ __IO uint16_t SWAP : 1;
+ __IO uint16_t PCRM0 : 1;
+ __IO uint16_t PCRM1 : 1;
+ __IO uint16_t AES0 : 1;
+ __IO uint16_t AES1 : 1;
+ __IO uint16_t BES0 : 1;
+ __IO uint16_t BES1 : 1;
+ __IO uint16_t CGE0 : 1;
+ __IO uint16_t CGE1 : 1;
+} stc_qprc_qcr_field_t;
+
+typedef struct stc_qprc_qcrl_field
+{
+ __IO uint8_t PCM0 : 1;
+ __IO uint8_t PCM1 : 1;
+ __IO uint8_t RCM0 : 1;
+ __IO uint8_t RCM1 : 1;
+ __IO uint8_t PSTP : 1;
+ __IO uint8_t CGSC : 1;
+ __IO uint8_t RSEL : 1;
+ __IO uint8_t SWAP : 1;
+} stc_qprc_qcrl_field_t;
+
+typedef struct stc_qprc_qcrh_field
+{
+ __IO uint8_t PCRM0 : 1;
+ __IO uint8_t PCRM1 : 1;
+ __IO uint8_t AES0 : 1;
+ __IO uint8_t AES1 : 1;
+ __IO uint8_t BES0 : 1;
+ __IO uint8_t BES1 : 1;
+ __IO uint8_t CGE0 : 1;
+ __IO uint8_t CGE1 : 1;
+} stc_qprc_qcrh_field_t;
+
+typedef struct stc_qprc_qecr_field
+{
+ __IO uint16_t ORNGMD : 1;
+ __IO uint16_t ORNGF : 1;
+ __IO uint16_t ORNGIE : 1;
+} stc_qprc_qecr_field_t;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* ADC12_MODULE register bit fields */
+typedef struct stc_adc_adsr_field
+{
+ __IO uint8_t SCS : 1;
+ __IO uint8_t PCS : 1;
+ __IO uint8_t PCNS : 1;
+ uint8_t RESERVED1 : 3;
+ __IO uint8_t FDAS : 1;
+ __IO uint8_t ADSTP : 1;
+} stc_adc_adsr_field_t;
+
+typedef struct stc_adc_adcr_field
+{
+ __IO uint8_t OVRIE : 1;
+ __IO uint8_t CMPIE : 1;
+ __IO uint8_t PCIE : 1;
+ __IO uint8_t SCIE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t CMPIF : 1;
+ __IO uint8_t PCIF : 1;
+ __IO uint8_t SCIF : 1;
+} stc_adc_adcr_field_t;
+
+typedef struct stc_adc_sfns_field
+{
+ __IO uint8_t SFS0 : 1;
+ __IO uint8_t SFS1 : 1;
+ __IO uint8_t SFS2 : 1;
+ __IO uint8_t SFS3 : 1;
+} stc_adc_sfns_field_t;
+
+typedef struct stc_adc_sccr_field
+{
+ __IO uint8_t SSTR : 1;
+ __IO uint8_t SHEN : 1;
+ __IO uint8_t RPT : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t SFCLR : 1;
+ __IO uint8_t SOVR : 1;
+ __IO uint8_t SFUL : 1;
+ __IO uint8_t SEMP : 1;
+} stc_adc_sccr_field_t;
+
+typedef struct stc_adc_scfd_field
+{
+ __IO uint32_t SC0 : 1;
+ __IO uint32_t SC1 : 1;
+ __IO uint32_t SC2 : 1;
+ __IO uint32_t SC3 : 1;
+ __IO uint32_t SC4 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t RS0 : 1;
+ __IO uint32_t RS1 : 1;
+ uint32_t RESERVED2 : 2;
+ __IO uint32_t INVL : 1;
+ uint32_t RESERVED3 : 7;
+ __IO uint32_t SD0 : 1;
+ __IO uint32_t SD1 : 1;
+ __IO uint32_t SD2 : 1;
+ __IO uint32_t SD3 : 1;
+ __IO uint32_t SD4 : 1;
+ __IO uint32_t SD5 : 1;
+ __IO uint32_t SD6 : 1;
+ __IO uint32_t SD7 : 1;
+ __IO uint32_t SD8 : 1;
+ __IO uint32_t SD9 : 1;
+ __IO uint32_t SD10 : 1;
+ __IO uint32_t SD11 : 1;
+} stc_adc_scfd_field_t;
+
+typedef struct stc_adc_scfdl_field
+{
+ __IO uint16_t SC0 : 1;
+ __IO uint16_t SC1 : 1;
+ __IO uint16_t SC2 : 1;
+ __IO uint16_t SC3 : 1;
+ __IO uint16_t SC4 : 1;
+ uint16_t RESERVED1 : 3;
+ __IO uint16_t RS0 : 1;
+ __IO uint16_t RS1 : 1;
+ uint16_t RESERVED2 : 2;
+ __IO uint16_t INVL : 1;
+} stc_adc_scfdl_field_t;
+
+typedef struct stc_adc_scfdh_field
+{
+ uint16_t RESERVED1 : 4;
+ __IO uint16_t SD0 : 1;
+ __IO uint16_t SD1 : 1;
+ __IO uint16_t SD2 : 1;
+ __IO uint16_t SD3 : 1;
+ __IO uint16_t SD4 : 1;
+ __IO uint16_t SD5 : 1;
+ __IO uint16_t SD6 : 1;
+ __IO uint16_t SD7 : 1;
+ __IO uint16_t SD8 : 1;
+ __IO uint16_t SD9 : 1;
+ __IO uint16_t SD10 : 1;
+ __IO uint16_t SD11 : 1;
+} stc_adc_scfdh_field_t;
+
+typedef struct stc_adc_scis23_field
+{
+ __IO uint16_t AN16 : 1;
+ __IO uint16_t AN17 : 1;
+ __IO uint16_t AN18 : 1;
+ __IO uint16_t AN19 : 1;
+ __IO uint16_t AN20 : 1;
+ __IO uint16_t AN21 : 1;
+ __IO uint16_t AN22 : 1;
+ __IO uint16_t AN23 : 1;
+ __IO uint16_t AN24 : 1;
+ __IO uint16_t AN25 : 1;
+ __IO uint16_t AN26 : 1;
+ __IO uint16_t AN27 : 1;
+ __IO uint16_t AN28 : 1;
+ __IO uint16_t AN29 : 1;
+ __IO uint16_t AN30 : 1;
+ __IO uint16_t AN31 : 1;
+} stc_adc_scis23_field_t;
+
+typedef struct stc_adc_scis2_field
+{
+ __IO uint8_t AN16 : 1;
+ __IO uint8_t AN17 : 1;
+ __IO uint8_t AN18 : 1;
+ __IO uint8_t AN19 : 1;
+ __IO uint8_t AN20 : 1;
+ __IO uint8_t AN21 : 1;
+ __IO uint8_t AN22 : 1;
+ __IO uint8_t AN23 : 1;
+} stc_adc_scis2_field_t;
+
+typedef struct stc_adc_scis3_field
+{
+ __IO uint8_t AN24 : 1;
+ __IO uint8_t AN25 : 1;
+ __IO uint8_t AN26 : 1;
+ __IO uint8_t AN27 : 1;
+ __IO uint8_t AN28 : 1;
+ __IO uint8_t AN29 : 1;
+ __IO uint8_t AN30 : 1;
+ __IO uint8_t AN31 : 1;
+} stc_adc_scis3_field_t;
+
+typedef struct stc_adc_scis01_field
+{
+ __IO uint16_t AN0 : 1;
+ __IO uint16_t AN1 : 1;
+ __IO uint16_t AN2 : 1;
+ __IO uint16_t AN3 : 1;
+ __IO uint16_t AN4 : 1;
+ __IO uint16_t AN5 : 1;
+ __IO uint16_t AN6 : 1;
+ __IO uint16_t AN7 : 1;
+ __IO uint16_t AN8 : 1;
+ __IO uint16_t AN9 : 1;
+ __IO uint16_t AN10 : 1;
+ __IO uint16_t AN11 : 1;
+ __IO uint16_t AN12 : 1;
+ __IO uint16_t AN13 : 1;
+ __IO uint16_t AN14 : 1;
+ __IO uint16_t AN15 : 1;
+} stc_adc_scis01_field_t;
+
+typedef struct stc_adc_scis0_field
+{
+ __IO uint8_t AN0 : 1;
+ __IO uint8_t AN1 : 1;
+ __IO uint8_t AN2 : 1;
+ __IO uint8_t AN3 : 1;
+ __IO uint8_t AN4 : 1;
+ __IO uint8_t AN5 : 1;
+ __IO uint8_t AN6 : 1;
+ __IO uint8_t AN7 : 1;
+} stc_adc_scis0_field_t;
+
+typedef struct stc_adc_scis1_field
+{
+ __IO uint8_t AN8 : 1;
+ __IO uint8_t AN9 : 1;
+ __IO uint8_t AN10 : 1;
+ __IO uint8_t AN11 : 1;
+ __IO uint8_t AN12 : 1;
+ __IO uint8_t AN13 : 1;
+ __IO uint8_t AN14 : 1;
+ __IO uint8_t AN15 : 1;
+} stc_adc_scis1_field_t;
+
+typedef struct stc_adc_pfns_field
+{
+ __IO uint8_t PFS0 : 1;
+ __IO uint8_t PFS1 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t TEST0 : 1;
+ __IO uint8_t TEST1 : 1;
+} stc_adc_pfns_field_t;
+
+typedef struct stc_adc_pccr_field
+{
+ __IO uint8_t PSTR : 1;
+ __IO uint8_t PHEN : 1;
+ __IO uint8_t PEEN : 1;
+ __IO uint8_t ESCE : 1;
+ __IO uint8_t PFCLR : 1;
+ __IO uint8_t POVR : 1;
+ __IO uint8_t PFUL : 1;
+ __IO uint8_t PEMP : 1;
+} stc_adc_pccr_field_t;
+
+typedef struct stc_adc_pcfd_field
+{
+ __IO uint32_t PC0 : 1;
+ __IO uint32_t PC1 : 1;
+ __IO uint32_t PC2 : 1;
+ __IO uint32_t PC3 : 1;
+ __IO uint32_t PC4 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t RS0 : 1;
+ __IO uint32_t RS1 : 1;
+ __IO uint32_t RS2 : 1;
+ uint32_t RESERVED2 : 1;
+ __IO uint32_t INVL : 1;
+ uint32_t RESERVED3 : 7;
+ __IO uint32_t PD0 : 1;
+ __IO uint32_t PD1 : 1;
+ __IO uint32_t PD2 : 1;
+ __IO uint32_t PD3 : 1;
+ __IO uint32_t PD4 : 1;
+ __IO uint32_t PD5 : 1;
+ __IO uint32_t PD6 : 1;
+ __IO uint32_t PD7 : 1;
+ __IO uint32_t PD8 : 1;
+ __IO uint32_t PD9 : 1;
+ __IO uint32_t PD10 : 1;
+ __IO uint32_t PD11 : 1;
+} stc_adc_pcfd_field_t;
+
+typedef struct stc_adc_pcfdl_field
+{
+ __IO uint16_t PC0 : 1;
+ __IO uint16_t PC1 : 1;
+ __IO uint16_t PC2 : 1;
+ __IO uint16_t PC3 : 1;
+ __IO uint16_t PC4 : 1;
+ uint16_t RESERVED1 : 3;
+ __IO uint16_t RS0 : 1;
+ __IO uint16_t RS1 : 1;
+ __IO uint16_t RS2 : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t INVL : 1;
+} stc_adc_pcfdl_field_t;
+
+typedef struct stc_adc_pcfdh_field
+{
+ uint16_t RESERVED1 : 4;
+ __IO uint16_t PD0 : 1;
+ __IO uint16_t PD1 : 1;
+ __IO uint16_t PD2 : 1;
+ __IO uint16_t PD3 : 1;
+ __IO uint16_t PD4 : 1;
+ __IO uint16_t PD5 : 1;
+ __IO uint16_t PD6 : 1;
+ __IO uint16_t PD7 : 1;
+ __IO uint16_t PD8 : 1;
+ __IO uint16_t PD9 : 1;
+ __IO uint16_t PD10 : 1;
+ __IO uint16_t PD11 : 1;
+} stc_adc_pcfdh_field_t;
+
+typedef struct stc_adc_pcis_field
+{
+ __IO uint8_t P1A0 : 1;
+ __IO uint8_t P1A1 : 1;
+ __IO uint8_t P1A2 : 1;
+ __IO uint8_t P2A0 : 1;
+ __IO uint8_t P2A1 : 1;
+ __IO uint8_t P2A2 : 1;
+ __IO uint8_t P2A3 : 1;
+ __IO uint8_t P2A4 : 1;
+} stc_adc_pcis_field_t;
+
+typedef struct stc_adc_cmpcr_field
+{
+ __IO uint8_t CCH0 : 1;
+ __IO uint8_t CCH1 : 1;
+ __IO uint8_t CCH2 : 1;
+ __IO uint8_t CCH3 : 1;
+ __IO uint8_t CCH4 : 1;
+ __IO uint8_t CMD0 : 1;
+ __IO uint8_t CMD1 : 1;
+ __IO uint8_t CMPEN : 1;
+} stc_adc_cmpcr_field_t;
+
+typedef struct stc_adc_cmpd_field
+{
+ uint16_t RESERVED1 : 6;
+ __IO uint16_t CMAD2 : 1;
+ __IO uint16_t CMAD3 : 1;
+ __IO uint16_t CMAD4 : 1;
+ __IO uint16_t CMAD5 : 1;
+ __IO uint16_t CMAD6 : 1;
+ __IO uint16_t CMAD7 : 1;
+ __IO uint16_t CMAD8 : 1;
+ __IO uint16_t CMAD9 : 1;
+ __IO uint16_t CMAD10 : 1;
+ __IO uint16_t CMAD11 : 1;
+} stc_adc_cmpd_field_t;
+
+typedef struct stc_adc_adss23_field
+{
+ __IO uint16_t TS16 : 1;
+ __IO uint16_t TS17 : 1;
+ __IO uint16_t TS18 : 1;
+ __IO uint16_t TS19 : 1;
+ __IO uint16_t TS20 : 1;
+ __IO uint16_t TS21 : 1;
+ __IO uint16_t TS22 : 1;
+ __IO uint16_t TS23 : 1;
+ __IO uint16_t TS24 : 1;
+ __IO uint16_t TS25 : 1;
+ __IO uint16_t TS26 : 1;
+ __IO uint16_t TS27 : 1;
+ __IO uint16_t TS28 : 1;
+ __IO uint16_t TS29 : 1;
+ __IO uint16_t TS30 : 1;
+ __IO uint16_t TS31 : 1;
+} stc_adc_adss23_field_t;
+
+typedef struct stc_adc_adss2_field
+{
+ __IO uint8_t TS16 : 1;
+ __IO uint8_t TS17 : 1;
+ __IO uint8_t TS18 : 1;
+ __IO uint8_t TS19 : 1;
+ __IO uint8_t TS20 : 1;
+ __IO uint8_t TS21 : 1;
+ __IO uint8_t TS22 : 1;
+ __IO uint8_t TS23 : 1;
+} stc_adc_adss2_field_t;
+
+typedef struct stc_adc_adss3_field
+{
+ __IO uint8_t TS24 : 1;
+ __IO uint8_t TS25 : 1;
+ __IO uint8_t TS26 : 1;
+ __IO uint8_t TS27 : 1;
+ __IO uint8_t TS28 : 1;
+ __IO uint8_t TS29 : 1;
+ __IO uint8_t TS30 : 1;
+ __IO uint8_t TS31 : 1;
+} stc_adc_adss3_field_t;
+
+typedef struct stc_adc_adss01_field
+{
+ __IO uint16_t TS0 : 1;
+ __IO uint16_t TS1 : 1;
+ __IO uint16_t TS2 : 1;
+ __IO uint16_t TS3 : 1;
+ __IO uint16_t TS4 : 1;
+ __IO uint16_t TS5 : 1;
+ __IO uint16_t TS6 : 1;
+ __IO uint16_t TS7 : 1;
+ __IO uint16_t TS8 : 1;
+ __IO uint16_t TS9 : 1;
+ __IO uint16_t TS10 : 1;
+ __IO uint16_t TS11 : 1;
+ __IO uint16_t TS12 : 1;
+ __IO uint16_t TS13 : 1;
+ __IO uint16_t TS14 : 1;
+ __IO uint16_t TS15 : 1;
+} stc_adc_adss01_field_t;
+
+typedef struct stc_adc_adss0_field
+{
+ __IO uint8_t TS0 : 1;
+ __IO uint8_t TS1 : 1;
+ __IO uint8_t TS2 : 1;
+ __IO uint8_t TS3 : 1;
+ __IO uint8_t TS4 : 1;
+ __IO uint8_t TS5 : 1;
+ __IO uint8_t TS6 : 1;
+ __IO uint8_t TS7 : 1;
+} stc_adc_adss0_field_t;
+
+typedef struct stc_adc_adss1_field
+{
+ __IO uint8_t TS8 : 1;
+ __IO uint8_t TS9 : 1;
+ __IO uint8_t TS10 : 1;
+ __IO uint8_t TS11 : 1;
+ __IO uint8_t TS12 : 1;
+ __IO uint8_t TS13 : 1;
+ __IO uint8_t TS14 : 1;
+ __IO uint8_t TS15 : 1;
+} stc_adc_adss1_field_t;
+
+typedef struct stc_adc_adst01_field
+{
+ __IO uint16_t ST10 : 1;
+ __IO uint16_t ST11 : 1;
+ __IO uint16_t ST12 : 1;
+ __IO uint16_t ST13 : 1;
+ __IO uint16_t ST14 : 1;
+ __IO uint16_t STX10 : 1;
+ __IO uint16_t STX11 : 1;
+ __IO uint16_t STX12 : 1;
+ __IO uint16_t ST00 : 1;
+ __IO uint16_t ST01 : 1;
+ __IO uint16_t ST02 : 1;
+ __IO uint16_t ST03 : 1;
+ __IO uint16_t ST04 : 1;
+ __IO uint16_t STX00 : 1;
+ __IO uint16_t STX01 : 1;
+ __IO uint16_t STX02 : 1;
+} stc_adc_adst01_field_t;
+
+typedef struct stc_adc_adst1_field
+{
+ __IO uint8_t ST10 : 1;
+ __IO uint8_t ST11 : 1;
+ __IO uint8_t ST12 : 1;
+ __IO uint8_t ST13 : 1;
+ __IO uint8_t ST14 : 1;
+ __IO uint8_t STX10 : 1;
+ __IO uint8_t STX11 : 1;
+ __IO uint8_t STX12 : 1;
+} stc_adc_adst1_field_t;
+
+typedef struct stc_adc_adst0_field
+{
+ __IO uint8_t ST00 : 1;
+ __IO uint8_t ST01 : 1;
+ __IO uint8_t ST02 : 1;
+ __IO uint8_t ST03 : 1;
+ __IO uint8_t ST04 : 1;
+ __IO uint8_t STX00 : 1;
+ __IO uint8_t STX01 : 1;
+ __IO uint8_t STX02 : 1;
+} stc_adc_adst0_field_t;
+
+typedef struct stc_adc_adct_field
+{
+ __IO uint8_t CT0 : 1;
+ __IO uint8_t CT1 : 1;
+ __IO uint8_t CT2 : 1;
+ __IO uint8_t CT3 : 1;
+ __IO uint8_t CT4 : 1;
+ __IO uint8_t CT5 : 1;
+ __IO uint8_t CT6 : 1;
+ __IO uint8_t CT7 : 1;
+} stc_adc_adct_field_t;
+
+typedef struct stc_adc_prtsl_field
+{
+ __IO uint8_t PRTSL0 : 1;
+ __IO uint8_t PRTSL1 : 1;
+ __IO uint8_t PRTSL2 : 1;
+ __IO uint8_t PRTSL3 : 1;
+} stc_adc_prtsl_field_t;
+
+typedef struct stc_adc_sctsl_field
+{
+ __IO uint8_t SCTSL0 : 1;
+ __IO uint8_t SCTSL1 : 1;
+ __IO uint8_t SCTSL2 : 1;
+ __IO uint8_t SCTSL3 : 1;
+} stc_adc_sctsl_field_t;
+
+typedef struct stc_adc_adcen_field
+{
+ __IO uint8_t ENBL : 1;
+ __IO uint8_t READY : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t CYCLSL0 : 1;
+ __IO uint8_t CYCLSL1 : 1;
+} stc_adc_adcen_field_t;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CRTRIM_MODULE register bit fields */
+typedef struct stc_crtrim_mcr_psr_field
+{
+ __IO uint8_t CSR0 : 1;
+ __IO uint8_t CSR1 : 1;
+} stc_crtrim_mcr_psr_field_t;
+
+typedef struct stc_crtrim_mcr_ftrm_field
+{
+ __IO uint16_t TRD0 : 1;
+ __IO uint16_t TRD1 : 1;
+ __IO uint16_t TRD2 : 1;
+ __IO uint16_t TRD3 : 1;
+ __IO uint16_t TRD4 : 1;
+ __IO uint16_t TRD5 : 1;
+ __IO uint16_t TRD6 : 1;
+ __IO uint16_t TRD7 : 1;
+ __IO uint16_t TRD8 : 1;
+ __IO uint16_t TRD9 : 1;
+} stc_crtrim_mcr_ftrm_field_t;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* EXTI_MODULE register bit fields */
+typedef struct stc_exti_enir_field
+{
+ __IO uint16_t EN0 : 1;
+ __IO uint16_t EN1 : 1;
+ __IO uint16_t EN2 : 1;
+ __IO uint16_t EN3 : 1;
+ __IO uint16_t EN4 : 1;
+ __IO uint16_t EN5 : 1;
+ __IO uint16_t EN6 : 1;
+ __IO uint16_t EN7 : 1;
+ __IO uint16_t EN8 : 1;
+ __IO uint16_t EN9 : 1;
+ __IO uint16_t EN10 : 1;
+ __IO uint16_t EN11 : 1;
+ __IO uint16_t EN12 : 1;
+ __IO uint16_t EN13 : 1;
+ __IO uint16_t EN14 : 1;
+ __IO uint16_t EN15 : 1;
+} stc_exti_enir_field_t;
+
+typedef struct stc_exti_eirr_field
+{
+ __IO uint16_t ER0 : 1;
+ __IO uint16_t ER1 : 1;
+ __IO uint16_t ER2 : 1;
+ __IO uint16_t ER3 : 1;
+ __IO uint16_t ER4 : 1;
+ __IO uint16_t ER5 : 1;
+ __IO uint16_t ER6 : 1;
+ __IO uint16_t ER7 : 1;
+ __IO uint16_t ER8 : 1;
+ __IO uint16_t ER9 : 1;
+ __IO uint16_t ER10 : 1;
+ __IO uint16_t ER11 : 1;
+ __IO uint16_t ER12 : 1;
+ __IO uint16_t ER13 : 1;
+ __IO uint16_t ER14 : 1;
+ __IO uint16_t ER15 : 1;
+} stc_exti_eirr_field_t;
+
+typedef struct stc_exti_eicl_field
+{
+ __IO uint16_t ECL0 : 1;
+ __IO uint16_t ECL1 : 1;
+ __IO uint16_t ECL2 : 1;
+ __IO uint16_t ECL3 : 1;
+ __IO uint16_t ECL4 : 1;
+ __IO uint16_t ECL5 : 1;
+ __IO uint16_t ECL6 : 1;
+ __IO uint16_t ECL7 : 1;
+ __IO uint16_t ECL8 : 1;
+ __IO uint16_t ECL9 : 1;
+ __IO uint16_t ECL10 : 1;
+ __IO uint16_t ECL11 : 1;
+ __IO uint16_t ECL12 : 1;
+ __IO uint16_t ECL13 : 1;
+ __IO uint16_t ECL14 : 1;
+ __IO uint16_t ECL15 : 1;
+} stc_exti_eicl_field_t;
+
+typedef struct stc_exti_elvr_field
+{
+ __IO uint32_t LA0 : 1;
+ __IO uint32_t LB0 : 1;
+ __IO uint32_t LA1 : 1;
+ __IO uint32_t LB1 : 1;
+ __IO uint32_t LA2 : 1;
+ __IO uint32_t LB2 : 1;
+ __IO uint32_t LA3 : 1;
+ __IO uint32_t LB3 : 1;
+ __IO uint32_t LA4 : 1;
+ __IO uint32_t LB4 : 1;
+ __IO uint32_t LA5 : 1;
+ __IO uint32_t LB5 : 1;
+ __IO uint32_t LA6 : 1;
+ __IO uint32_t LB6 : 1;
+ __IO uint32_t LA7 : 1;
+ __IO uint32_t LB7 : 1;
+ __IO uint32_t LA8 : 1;
+ __IO uint32_t LB8 : 1;
+ __IO uint32_t LA9 : 1;
+ __IO uint32_t LB9 : 1;
+ __IO uint32_t LA10 : 1;
+ __IO uint32_t LB10 : 1;
+ __IO uint32_t LA11 : 1;
+ __IO uint32_t LB11 : 1;
+ __IO uint32_t LA12 : 1;
+ __IO uint32_t LB12 : 1;
+ __IO uint32_t LA13 : 1;
+ __IO uint32_t LB13 : 1;
+ __IO uint32_t LA14 : 1;
+ __IO uint32_t LB14 : 1;
+ __IO uint32_t LA15 : 1;
+ __IO uint32_t LB15 : 1;
+} stc_exti_elvr_field_t;
+
+typedef struct stc_exti_nmirr_field
+{
+ __IO uint8_t NR0 : 1;
+} stc_exti_nmirr_field_t;
+
+typedef struct stc_exti_nmicl_field
+{
+ __IO uint8_t NCL0 : 1;
+} stc_exti_nmicl_field_t;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* INTREQ_MODULE register bit fields */
+typedef struct stc_intreq_drqsel_field
+{
+ __IO uint32_t DRQSEL0 : 1;
+ __IO uint32_t DRQSEL1 : 1;
+ __IO uint32_t DRQSEL2 : 1;
+ __IO uint32_t DRQSEL3 : 1;
+ __IO uint32_t DRQSEL4 : 1;
+ __IO uint32_t DRQSEL5 : 1;
+ __IO uint32_t DRQSEL6 : 1;
+ __IO uint32_t DRQSEL7 : 1;
+ __IO uint32_t DRQSEL8 : 1;
+ __IO uint32_t DRQSEL9 : 1;
+ __IO uint32_t DRQSEL10 : 1;
+ __IO uint32_t DRQSEL11 : 1;
+ __IO uint32_t DRQSEL12 : 1;
+ __IO uint32_t DRQSEL13 : 1;
+ __IO uint32_t DRQSEL14 : 1;
+ __IO uint32_t DRQSEL15 : 1;
+ __IO uint32_t DRQSEL16 : 1;
+ __IO uint32_t DRQSEL17 : 1;
+ __IO uint32_t DRQSEL18 : 1;
+ __IO uint32_t DRQSEL19 : 1;
+ __IO uint32_t DRQSEL20 : 1;
+ __IO uint32_t DRQSEL21 : 1;
+ __IO uint32_t DRQSEL22 : 1;
+ __IO uint32_t DRQSEL23 : 1;
+ __IO uint32_t DRQSEL24 : 1;
+ __IO uint32_t DRQSEL25 : 1;
+ __IO uint32_t DRQSEL26 : 1;
+ __IO uint32_t DRQSEL27 : 1;
+ __IO uint32_t DRQSEL28 : 1;
+ __IO uint32_t DRQSEL29 : 1;
+ __IO uint32_t DRQSEL30 : 1;
+ __IO uint32_t DRQSEL31 : 1;
+} stc_intreq_drqsel_field_t;
+
+typedef struct stc_intreq_exc02mon_field
+{
+ __IO uint32_t NMI : 1;
+ __IO uint32_t HWINT : 1;
+} stc_intreq_exc02mon_field_t;
+
+typedef struct stc_intreq_irq00mon_field
+{
+ __IO uint32_t FCSINT : 1;
+} stc_intreq_irq00mon_field_t;
+
+typedef struct stc_intreq_irq01mon_field
+{
+ __IO uint32_t SWWDTINT : 1;
+} stc_intreq_irq01mon_field_t;
+
+typedef struct stc_intreq_irq02mon_field
+{
+ __IO uint32_t LVDINT : 1;
+} stc_intreq_irq02mon_field_t;
+
+typedef struct stc_intreq_irq03mon_field
+{
+ __IO uint32_t WAVE0INT0 : 1;
+ __IO uint32_t WAVE0INT1 : 1;
+ __IO uint32_t WAVE0INT2 : 1;
+ __IO uint32_t WAVE0INT3 : 1;
+ __IO uint32_t WAVE1INT0 : 1;
+ __IO uint32_t WAVE1INT1 : 1;
+ __IO uint32_t WAVE1INT2 : 1;
+ __IO uint32_t WAVE1INT3 : 1;
+} stc_intreq_irq03mon_field_t;
+
+typedef struct stc_intreq_irq04mon_field
+{
+ __IO uint32_t EXTINT0 : 1;
+ __IO uint32_t EXTINT1 : 1;
+ __IO uint32_t EXTINT2 : 1;
+ __IO uint32_t EXTINT3 : 1;
+ __IO uint32_t EXTINT4 : 1;
+ __IO uint32_t EXTINT5 : 1;
+ __IO uint32_t EXTINT6 : 1;
+ __IO uint32_t EXTINT7 : 1;
+} stc_intreq_irq04mon_field_t;
+
+typedef struct stc_intreq_irq05mon_field
+{
+ __IO uint32_t EXTINT0 : 1;
+ __IO uint32_t EXTINT1 : 1;
+ __IO uint32_t EXTINT2 : 1;
+ __IO uint32_t EXTINT3 : 1;
+ __IO uint32_t EXTINT4 : 1;
+ __IO uint32_t EXTINT5 : 1;
+ __IO uint32_t EXTINT6 : 1;
+ __IO uint32_t EXTINT7 : 1;
+} stc_intreq_irq05mon_field_t;
+
+typedef struct stc_intreq_irq06mon_field
+{
+ __IO uint32_t TIMINT0 : 1;
+ __IO uint32_t TIMINT1 : 1;
+ __IO uint32_t QUD0INT0 : 1;
+ __IO uint32_t QUD0INT1 : 1;
+ __IO uint32_t QUD0INT2 : 1;
+ __IO uint32_t QUD0INT3 : 1;
+ __IO uint32_t QUD0INT4 : 1;
+ __IO uint32_t QUD0INT5 : 1;
+ __IO uint32_t QUD1INT0 : 1;
+ __IO uint32_t QUD1INT1 : 1;
+ __IO uint32_t QUD1INT2 : 1;
+ __IO uint32_t QUD1INT3 : 1;
+ __IO uint32_t QUD1INT4 : 1;
+ __IO uint32_t QUD1INT5 : 1;
+} stc_intreq_irq06mon_field_t;
+
+typedef struct stc_intreq_irq07mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq07mon_field_t;
+
+typedef struct stc_intreq_irq08mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq08mon_field_t;
+
+typedef struct stc_intreq_irq09mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq09mon_field_t;
+
+typedef struct stc_intreq_irq10mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq10mon_field_t;
+
+typedef struct stc_intreq_irq11mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq11mon_field_t;
+
+typedef struct stc_intreq_irq12mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq12mon_field_t;
+
+typedef struct stc_intreq_irq13mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq13mon_field_t;
+
+typedef struct stc_intreq_irq14mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq14mon_field_t;
+
+typedef struct stc_intreq_irq15mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq15mon_field_t;
+
+typedef struct stc_intreq_irq16mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq16mon_field_t;
+
+typedef struct stc_intreq_irq17mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq17mon_field_t;
+
+typedef struct stc_intreq_irq18mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq18mon_field_t;
+
+typedef struct stc_intreq_irq19mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq19mon_field_t;
+
+typedef struct stc_intreq_irq20mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq20mon_field_t;
+
+typedef struct stc_intreq_irq21mon_field
+{
+ __IO uint32_t FMSINT : 1;
+} stc_intreq_irq21mon_field_t;
+
+typedef struct stc_intreq_irq22mon_field
+{
+ __IO uint32_t MFSINT0 : 1;
+ __IO uint32_t MFSINT1 : 1;
+} stc_intreq_irq22mon_field_t;
+
+typedef struct stc_intreq_irq23mon_field
+{
+ __IO uint32_t PPGINT0 : 1;
+ __IO uint32_t PPGINT1 : 1;
+ __IO uint32_t PPGINT2 : 1;
+ __IO uint32_t PPGINT3 : 1;
+ __IO uint32_t PPGINT4 : 1;
+ __IO uint32_t PPGINT5 : 1;
+} stc_intreq_irq23mon_field_t;
+
+typedef struct stc_intreq_irq24mon_field
+{
+ __IO uint32_t MOSCINT : 1;
+ __IO uint32_t SOSCINT : 1;
+ __IO uint32_t MPLLINT : 1;
+ __IO uint32_t UPLLINT : 1;
+ __IO uint32_t WCINT : 1;
+} stc_intreq_irq24mon_field_t;
+
+typedef struct stc_intreq_irq25mon_field
+{
+ __IO uint32_t ADCINT0 : 1;
+ __IO uint32_t ADCINT1 : 1;
+ __IO uint32_t ADCINT2 : 1;
+ __IO uint32_t ADCINT3 : 1;
+} stc_intreq_irq25mon_field_t;
+
+typedef struct stc_intreq_irq26mon_field
+{
+ __IO uint32_t ADCINT0 : 1;
+ __IO uint32_t ADCINT1 : 1;
+ __IO uint32_t ADCINT2 : 1;
+ __IO uint32_t ADCINT3 : 1;
+} stc_intreq_irq26mon_field_t;
+
+typedef struct stc_intreq_irq27mon_field
+{
+ __IO uint32_t ADCINT0 : 1;
+ __IO uint32_t ADCINT1 : 1;
+ __IO uint32_t ADCINT2 : 1;
+ __IO uint32_t ADCINT3 : 1;
+} stc_intreq_irq27mon_field_t;
+
+typedef struct stc_intreq_irq28mon_field
+{
+ __IO uint32_t FRT0INT0 : 1;
+ __IO uint32_t FRT0INT1 : 1;
+ __IO uint32_t FRT0INT2 : 1;
+ __IO uint32_t FRT0INT3 : 1;
+ __IO uint32_t FRT0INT4 : 1;
+ __IO uint32_t FRT0INT5 : 1;
+ __IO uint32_t FRT1INT0 : 1;
+ __IO uint32_t FRT1INT1 : 1;
+ __IO uint32_t FRT1INT2 : 1;
+ __IO uint32_t FRT1INT3 : 1;
+ __IO uint32_t FRT1INT4 : 1;
+ __IO uint32_t FRT1INT5 : 1;
+} stc_intreq_irq28mon_field_t;
+
+typedef struct stc_intreq_irq29mon_field
+{
+ __IO uint32_t ICU0INT0 : 1;
+ __IO uint32_t ICU0INT1 : 1;
+ __IO uint32_t ICU0INT2 : 1;
+ __IO uint32_t ICU0INT3 : 1;
+ __IO uint32_t ICU1INT0 : 1;
+ __IO uint32_t ICU1INT1 : 1;
+ __IO uint32_t ICU1INT2 : 1;
+ __IO uint32_t ICU1INT3 : 1;
+} stc_intreq_irq29mon_field_t;
+
+typedef struct stc_intreq_irq30mon_field
+{
+ __IO uint32_t OCU0INT0 : 1;
+ __IO uint32_t OCU0INT1 : 1;
+ __IO uint32_t OCU0INT2 : 1;
+ __IO uint32_t OCU0INT3 : 1;
+ __IO uint32_t OCU0INT4 : 1;
+ __IO uint32_t OCU0INT5 : 1;
+ __IO uint32_t OCU1INT0 : 1;
+ __IO uint32_t OCU1INT1 : 1;
+ __IO uint32_t OCU1INT2 : 1;
+ __IO uint32_t OCU1INT3 : 1;
+ __IO uint32_t OCU1INT4 : 1;
+ __IO uint32_t OCU1INT5 : 1;
+} stc_intreq_irq30mon_field_t;
+
+typedef struct stc_intreq_irq31mon_field
+{
+ __IO uint32_t BTINT0 : 1;
+ __IO uint32_t BTINT1 : 1;
+ __IO uint32_t BTINT2 : 1;
+ __IO uint32_t BTINT3 : 1;
+ __IO uint32_t BTINT4 : 1;
+ __IO uint32_t BTINT5 : 1;
+ __IO uint32_t BTINT6 : 1;
+ __IO uint32_t BTINT7 : 1;
+ __IO uint32_t BTINT8 : 1;
+ __IO uint32_t BTINT9 : 1;
+ __IO uint32_t BTINT10 : 1;
+ __IO uint32_t BTINT11 : 1;
+ __IO uint32_t BTINT12 : 1;
+ __IO uint32_t BTINT13 : 1;
+ __IO uint32_t BTINT14 : 1;
+ __IO uint32_t BTINT15 : 1;
+} stc_intreq_irq31mon_field_t;
+
+typedef struct stc_intreq_irq32mon_field
+{
+ __IO uint32_t CANINT : 1;
+} stc_intreq_irq32mon_field_t;
+
+typedef struct stc_intreq_irq33mon_field
+{
+ __IO uint32_t CANINT : 1;
+} stc_intreq_irq33mon_field_t;
+
+typedef struct stc_intreq_irq34mon_field
+{
+ __IO uint32_t USB0INT0 : 1;
+ __IO uint32_t USB0INT1 : 1;
+ __IO uint32_t USB0INT2 : 1;
+ __IO uint32_t USB0INT3 : 1;
+ __IO uint32_t USB0INT4 : 1;
+} stc_intreq_irq34mon_field_t;
+
+typedef struct stc_intreq_irq35mon_field
+{
+ __IO uint32_t USB0INT0 : 1;
+ __IO uint32_t USB0INT1 : 1;
+ __IO uint32_t USB0INT2 : 1;
+ __IO uint32_t USB0INT3 : 1;
+ __IO uint32_t USB0INT4 : 1;
+ __IO uint32_t USB0INT5 : 1;
+} stc_intreq_irq35mon_field_t;
+
+typedef struct stc_intreq_irq38mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq38mon_field_t;
+
+typedef struct stc_intreq_irq39mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq39mon_field_t;
+
+typedef struct stc_intreq_irq40mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq40mon_field_t;
+
+typedef struct stc_intreq_irq41mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq41mon_field_t;
+
+typedef struct stc_intreq_irq42mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq42mon_field_t;
+
+typedef struct stc_intreq_irq43mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq43mon_field_t;
+
+typedef struct stc_intreq_irq44mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq44mon_field_t;
+
+typedef struct stc_intreq_irq45mon_field
+{
+ __IO uint32_t DMAINT : 1;
+} stc_intreq_irq45mon_field_t;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* GPIO_MODULE register bit fields */
+typedef struct stc_gpio_pfr0_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pfr0_field_t;
+
+typedef struct stc_gpio_pfr1_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pfr1_field_t;
+
+typedef struct stc_gpio_pfr2_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pfr2_field_t;
+
+typedef struct stc_gpio_pfr3_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pfr3_field_t;
+
+typedef struct stc_gpio_pfr4_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+} stc_gpio_pfr4_field_t;
+
+typedef struct stc_gpio_pfr5_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+} stc_gpio_pfr5_field_t;
+
+typedef struct stc_gpio_pfr6_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pfr6_field_t;
+
+typedef struct stc_gpio_pfr7_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+} stc_gpio_pfr7_field_t;
+
+typedef struct stc_gpio_pfr8_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+} stc_gpio_pfr8_field_t;
+
+typedef struct stc_gpio_pcr0_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pcr0_field_t;
+
+typedef struct stc_gpio_pcr1_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pcr1_field_t;
+
+typedef struct stc_gpio_pcr2_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pcr2_field_t;
+
+typedef struct stc_gpio_pcr3_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pcr3_field_t;
+
+typedef struct stc_gpio_pcr4_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+} stc_gpio_pcr4_field_t;
+
+typedef struct stc_gpio_pcr5_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+} stc_gpio_pcr5_field_t;
+
+typedef struct stc_gpio_pcr6_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pcr6_field_t;
+
+typedef struct stc_gpio_pcr7_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+} stc_gpio_pcr7_field_t;
+
+typedef struct stc_gpio_ddr0_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_ddr0_field_t;
+
+typedef struct stc_gpio_ddr1_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_ddr1_field_t;
+
+typedef struct stc_gpio_ddr2_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_ddr2_field_t;
+
+typedef struct stc_gpio_ddr3_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_ddr3_field_t;
+
+typedef struct stc_gpio_ddr4_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+} stc_gpio_ddr4_field_t;
+
+typedef struct stc_gpio_ddr5_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+} stc_gpio_ddr5_field_t;
+
+typedef struct stc_gpio_ddr6_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_ddr6_field_t;
+
+typedef struct stc_gpio_ddr7_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+} stc_gpio_ddr7_field_t;
+
+typedef struct stc_gpio_ddr8_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+} stc_gpio_ddr8_field_t;
+
+typedef struct stc_gpio_pdir0_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pdir0_field_t;
+
+typedef struct stc_gpio_pdir1_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pdir1_field_t;
+
+typedef struct stc_gpio_pdir2_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pdir2_field_t;
+
+typedef struct stc_gpio_pdir3_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pdir3_field_t;
+
+typedef struct stc_gpio_pdir4_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+} stc_gpio_pdir4_field_t;
+
+typedef struct stc_gpio_pdir5_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+} stc_gpio_pdir5_field_t;
+
+typedef struct stc_gpio_pdir6_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pdir6_field_t;
+
+typedef struct stc_gpio_pdir7_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+} stc_gpio_pdir7_field_t;
+
+typedef struct stc_gpio_pdir8_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+} stc_gpio_pdir8_field_t;
+
+typedef struct stc_gpio_pdor0_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pdor0_field_t;
+
+typedef struct stc_gpio_pdor1_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pdor1_field_t;
+
+typedef struct stc_gpio_pdor2_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pdor2_field_t;
+
+typedef struct stc_gpio_pdor3_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+ __IO uint32_t PF : 1;
+} stc_gpio_pdor3_field_t;
+
+typedef struct stc_gpio_pdor4_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t PC : 1;
+ __IO uint32_t PD : 1;
+ __IO uint32_t PE : 1;
+} stc_gpio_pdor4_field_t;
+
+typedef struct stc_gpio_pdor5_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+ __IO uint32_t P9 : 1;
+ __IO uint32_t PA : 1;
+ __IO uint32_t PB : 1;
+} stc_gpio_pdor5_field_t;
+
+typedef struct stc_gpio_pdor6_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+ __IO uint32_t P5 : 1;
+ __IO uint32_t P6 : 1;
+ __IO uint32_t P7 : 1;
+ __IO uint32_t P8 : 1;
+} stc_gpio_pdor6_field_t;
+
+typedef struct stc_gpio_pdor7_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+ __IO uint32_t P2 : 1;
+ __IO uint32_t P3 : 1;
+ __IO uint32_t P4 : 1;
+} stc_gpio_pdor7_field_t;
+
+typedef struct stc_gpio_pdor8_field
+{
+ __IO uint32_t P0 : 1;
+ __IO uint32_t P1 : 1;
+} stc_gpio_pdor8_field_t;
+
+typedef struct stc_gpio_ade_field
+{
+ __IO uint32_t AN0 : 1;
+ __IO uint32_t AN1 : 1;
+ __IO uint32_t AN2 : 1;
+ __IO uint32_t AN3 : 1;
+ __IO uint32_t AN4 : 1;
+ __IO uint32_t AN5 : 1;
+ __IO uint32_t AN6 : 1;
+ __IO uint32_t AN7 : 1;
+ __IO uint32_t AN8 : 1;
+ __IO uint32_t AN9 : 1;
+ __IO uint32_t ANA : 1;
+ __IO uint32_t ANB : 1;
+ __IO uint32_t ANC : 1;
+ __IO uint32_t AND : 1;
+ __IO uint32_t ANE : 1;
+ __IO uint32_t ANF : 1;
+} stc_gpio_ade_field_t;
+
+typedef struct stc_gpio_spsr_field
+{
+ __IO uint32_t SUBXC : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t USB0C : 1;
+} stc_gpio_spsr_field_t;
+
+typedef struct stc_gpio_epfr00_field
+{
+ __IO uint32_t NMIS : 1;
+ __IO uint32_t CROUTE : 1;
+ uint32_t RESERVED1 : 7;
+ __IO uint32_t USB0PE : 1;
+ uint32_t RESERVED2 : 6;
+ __IO uint32_t JTAGEN0B : 1;
+ __IO uint32_t JTAGEN1S : 1;
+ uint32_t RESERVED3 : 6;
+ __IO uint32_t TRC0E : 1;
+ __IO uint32_t TRC1E : 1;
+} stc_gpio_epfr00_field_t;
+
+typedef struct stc_gpio_epfr01_field
+{
+ __IO uint32_t RTO00E0 : 1;
+ __IO uint32_t RTO00E1 : 1;
+ __IO uint32_t RTO01E0 : 1;
+ __IO uint32_t RTO01E1 : 1;
+ __IO uint32_t RTO02E0 : 1;
+ __IO uint32_t RTO02E1 : 1;
+ __IO uint32_t RTO03E0 : 1;
+ __IO uint32_t RTO03E1 : 1;
+ __IO uint32_t RTO04E0 : 1;
+ __IO uint32_t RTO04E1 : 1;
+ __IO uint32_t RTO05E0 : 1;
+ __IO uint32_t RTO05E1 : 1;
+ __IO uint32_t DTTI0C : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t DTTI0S0 : 1;
+ __IO uint32_t DTTI0S1 : 1;
+ __IO uint32_t FRCK0S0 : 1;
+ __IO uint32_t FRCK0S1 : 1;
+ __IO uint32_t IC00S0 : 1;
+ __IO uint32_t IC00S1 : 1;
+ __IO uint32_t IC00S2 : 1;
+ __IO uint32_t IC01S0 : 1;
+ __IO uint32_t IC01S1 : 1;
+ __IO uint32_t IC01S2 : 1;
+ __IO uint32_t IC02S0 : 1;
+ __IO uint32_t IC02S1 : 1;
+ __IO uint32_t IC02S2 : 1;
+ __IO uint32_t IC03S0 : 1;
+ __IO uint32_t IC03S1 : 1;
+ __IO uint32_t IC03S2 : 1;
+} stc_gpio_epfr01_field_t;
+
+typedef struct stc_gpio_epfr02_field
+{
+ __IO uint32_t RTO10E0 : 1;
+ __IO uint32_t RTO10E1 : 1;
+ __IO uint32_t RTO11E0 : 1;
+ __IO uint32_t RTO11E1 : 1;
+ __IO uint32_t RTO12E0 : 1;
+ __IO uint32_t RTO12E1 : 1;
+ __IO uint32_t RTO13E0 : 1;
+ __IO uint32_t RTO13E1 : 1;
+ __IO uint32_t RTO14E0 : 1;
+ __IO uint32_t RTO14E1 : 1;
+ __IO uint32_t RTO15E0 : 1;
+ __IO uint32_t RTO15E1 : 1;
+ __IO uint32_t DTTI1C : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t DTTI1S0 : 1;
+ __IO uint32_t DTTI1S1 : 1;
+ __IO uint32_t FRCK1S0 : 1;
+ __IO uint32_t FRCK1S1 : 1;
+ __IO uint32_t IC10S0 : 1;
+ __IO uint32_t IC10S1 : 1;
+ __IO uint32_t IC10S2 : 1;
+ __IO uint32_t IC11S0 : 1;
+ __IO uint32_t IC11S1 : 1;
+ __IO uint32_t IC11S2 : 1;
+ __IO uint32_t IC12S0 : 1;
+ __IO uint32_t IC12S1 : 1;
+ __IO uint32_t IC12S2 : 1;
+ __IO uint32_t IC13S0 : 1;
+ __IO uint32_t IC13S1 : 1;
+ __IO uint32_t IC13S2 : 1;
+} stc_gpio_epfr02_field_t;
+
+typedef struct stc_gpio_epfr04_field
+{
+ uint32_t RESERVED1 : 2;
+ __IO uint32_t TIOA0E0 : 1;
+ __IO uint32_t TIOA0E1 : 1;
+ __IO uint32_t TIOB0S0 : 1;
+ __IO uint32_t TIOB0S1 : 1;
+ uint32_t RESERVED2 : 2;
+ __IO uint32_t TIOA1S0 : 1;
+ __IO uint32_t TIOA1S1 : 1;
+ __IO uint32_t TIOA1E0 : 1;
+ __IO uint32_t TIOA1E1 : 1;
+ __IO uint32_t TIOB1S0 : 1;
+ __IO uint32_t TIOB1S1 : 1;
+ uint32_t RESERVED3 : 4;
+ __IO uint32_t TIOA2E0 : 1;
+ __IO uint32_t TIOA2E1 : 1;
+ __IO uint32_t TIOB2S0 : 1;
+ __IO uint32_t TIOB2S1 : 1;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t TIOA3S0 : 1;
+ __IO uint32_t TIOA3S1 : 1;
+ __IO uint32_t TIOA3E0 : 1;
+ __IO uint32_t TIOA3E1 : 1;
+ __IO uint32_t TIOB3S0 : 1;
+ __IO uint32_t TIOB3S1 : 1;
+} stc_gpio_epfr04_field_t;
+
+typedef struct stc_gpio_epfr05_field
+{
+ uint32_t RESERVED1 : 2;
+ __IO uint32_t TIOA4E0 : 1;
+ __IO uint32_t TIOA4E1 : 1;
+ __IO uint32_t TIOB4S0 : 1;
+ __IO uint32_t TIOB4S1 : 1;
+ uint32_t RESERVED2 : 2;
+ __IO uint32_t TIOA5S0 : 1;
+ __IO uint32_t TIOA5S1 : 1;
+ __IO uint32_t TIOA5E0 : 1;
+ __IO uint32_t TIOA5E1 : 1;
+ __IO uint32_t TIOB5S0 : 1;
+ __IO uint32_t TIOB5S1 : 1;
+ uint32_t RESERVED3 : 4;
+ __IO uint32_t TIOA6E0 : 1;
+ __IO uint32_t TIOA6E1 : 1;
+ __IO uint32_t TIOB6S0 : 1;
+ __IO uint32_t TIOB6S1 : 1;
+ uint32_t RESERVED4 : 2;
+ __IO uint32_t TIOA7S0 : 1;
+ __IO uint32_t TIOA7S1 : 1;
+ __IO uint32_t TIOA7E0 : 1;
+ __IO uint32_t TIOA7E1 : 1;
+ __IO uint32_t TIOB7S0 : 1;
+ __IO uint32_t TIOB7S1 : 1;
+} stc_gpio_epfr05_field_t;
+
+typedef struct stc_gpio_epfr06_field
+{
+ __IO uint32_t EINT00S0 : 1;
+ __IO uint32_t EINT00S1 : 1;
+ __IO uint32_t EINT01S0 : 1;
+ __IO uint32_t EINT01S1 : 1;
+ __IO uint32_t EINT02S0 : 1;
+ __IO uint32_t EINT02S1 : 1;
+ __IO uint32_t EINT03S0 : 1;
+ __IO uint32_t EINT03S1 : 1;
+ __IO uint32_t EINT04S0 : 1;
+ __IO uint32_t EINT04S1 : 1;
+ __IO uint32_t EINT05S0 : 1;
+ __IO uint32_t EINT05S1 : 1;
+ __IO uint32_t EINT06S0 : 1;
+ __IO uint32_t EINT06S1 : 1;
+ __IO uint32_t EINT07S0 : 1;
+ __IO uint32_t EINT07S1 : 1;
+ __IO uint32_t EINT08S0 : 1;
+ __IO uint32_t EINT08S1 : 1;
+ __IO uint32_t EINT09S0 : 1;
+ __IO uint32_t EINT09S1 : 1;
+ __IO uint32_t EINT10S0 : 1;
+ __IO uint32_t EINT10S1 : 1;
+ __IO uint32_t EINT11S0 : 1;
+ __IO uint32_t EINT11S1 : 1;
+ __IO uint32_t EINT12S0 : 1;
+ __IO uint32_t EINT12S1 : 1;
+ __IO uint32_t EINT13S0 : 1;
+ __IO uint32_t EINT13S1 : 1;
+ __IO uint32_t EINT14S0 : 1;
+ __IO uint32_t EINT14S1 : 1;
+ __IO uint32_t EINT15S0 : 1;
+ __IO uint32_t EINT15S1 : 1;
+} stc_gpio_epfr06_field_t;
+
+typedef struct stc_gpio_epfr07_field
+{
+ uint32_t RESERVED1 : 4;
+ __IO uint32_t SIN0S0 : 1;
+ __IO uint32_t SIN0S1 : 1;
+ __IO uint32_t SOT0B0 : 1;
+ __IO uint32_t SOT0B1 : 1;
+ __IO uint32_t SCK0B0 : 1;
+ __IO uint32_t SCK0B1 : 1;
+ __IO uint32_t SIN1S0 : 1;
+ __IO uint32_t SIN1S1 : 1;
+ __IO uint32_t SOT1B0 : 1;
+ __IO uint32_t SOT1B1 : 1;
+ __IO uint32_t SCK1B0 : 1;
+ __IO uint32_t SCK1B1 : 1;
+ __IO uint32_t SIN2S0 : 1;
+ __IO uint32_t SIN2S1 : 1;
+ __IO uint32_t SOT2B0 : 1;
+ __IO uint32_t SOT2B1 : 1;
+ __IO uint32_t SCK2B0 : 1;
+ __IO uint32_t SCK2B1 : 1;
+ __IO uint32_t SIN3S0 : 1;
+ __IO uint32_t SIN3S1 : 1;
+ __IO uint32_t SOT3B0 : 1;
+ __IO uint32_t SOT3B1 : 1;
+ __IO uint32_t SCK3B0 : 1;
+ __IO uint32_t SCK3B1 : 1;
+} stc_gpio_epfr07_field_t;
+
+typedef struct stc_gpio_epfr08_field
+{
+ __IO uint32_t RTS4E0 : 1;
+ __IO uint32_t RTS4E1 : 1;
+ __IO uint32_t CTS4S0 : 1;
+ __IO uint32_t CTS4S1 : 1;
+ __IO uint32_t SIN4S0 : 1;
+ __IO uint32_t SIN4S1 : 1;
+ __IO uint32_t SOT4B0 : 1;
+ __IO uint32_t SOT4B1 : 1;
+ __IO uint32_t SCK4B0 : 1;
+ __IO uint32_t SCK4B1 : 1;
+ __IO uint32_t SIN5S0 : 1;
+ __IO uint32_t SIN5S1 : 1;
+ __IO uint32_t SOT5B0 : 1;
+ __IO uint32_t SOT5B1 : 1;
+ __IO uint32_t SCK5B0 : 1;
+ __IO uint32_t SCK5B1 : 1;
+ __IO uint32_t SIN6S0 : 1;
+ __IO uint32_t SIN6S1 : 1;
+ __IO uint32_t SOT6B0 : 1;
+ __IO uint32_t SOT6B1 : 1;
+ __IO uint32_t SCK6B0 : 1;
+ __IO uint32_t SCK6B1 : 1;
+ __IO uint32_t SIN7S0 : 1;
+ __IO uint32_t SIN7S1 : 1;
+ __IO uint32_t SOT7B0 : 1;
+ __IO uint32_t SOT7B1 : 1;
+ __IO uint32_t SCK7B0 : 1;
+ __IO uint32_t SCK7B1 : 1;
+} stc_gpio_epfr08_field_t;
+
+typedef struct stc_gpio_epfr09_field
+{
+ __IO uint32_t QAIN0S0 : 1;
+ __IO uint32_t QAIN0S1 : 1;
+ __IO uint32_t QBIN0S0 : 1;
+ __IO uint32_t QBIN0S1 : 1;
+ __IO uint32_t QZIN0S0 : 1;
+ __IO uint32_t QZIN0S1 : 1;
+ __IO uint32_t QAIN1S0 : 1;
+ __IO uint32_t QAIN1S1 : 1;
+ __IO uint32_t QBIN1S0 : 1;
+ __IO uint32_t QBIN1S1 : 1;
+ __IO uint32_t QZIN1S0 : 1;
+ __IO uint32_t QZIN1S1 : 1;
+ __IO uint32_t ADTRG0S0 : 1;
+ __IO uint32_t ADTRG0S1 : 1;
+ __IO uint32_t ADTRG0S2 : 1;
+ __IO uint32_t ADTRG0S3 : 1;
+ __IO uint32_t ADTRG1S0 : 1;
+ __IO uint32_t ADTRG1S1 : 1;
+ __IO uint32_t ADTRG1S2 : 1;
+ __IO uint32_t ADTRG1S3 : 1;
+ __IO uint32_t ADTRG2S0 : 1;
+ __IO uint32_t ADTRG2S1 : 1;
+ __IO uint32_t ADTRG2S2 : 1;
+ __IO uint32_t ADTRG2S3 : 1;
+ __IO uint32_t CRX0S0 : 1;
+ __IO uint32_t CRX0S1 : 1;
+ __IO uint32_t CTX0E0 : 1;
+ __IO uint32_t CTX0E1 : 1;
+ __IO uint32_t CRX1S0 : 1;
+ __IO uint32_t CRX1S1 : 1;
+ __IO uint32_t CTX1E0 : 1;
+ __IO uint32_t CTX1E1 : 1;
+} stc_gpio_epfr09_field_t;
+
+typedef struct stc_gpio_epfr10_field
+{
+ __IO uint32_t UEDEFB : 1;
+ __IO uint32_t UEDTHB : 1;
+ __IO uint32_t TESTB : 1;
+ __IO uint32_t UEWEXE : 1;
+ __IO uint32_t UEDQME : 1;
+ __IO uint32_t UEOEXE : 1;
+ __IO uint32_t UEFLSE : 1;
+ __IO uint32_t UECS1E : 1;
+ __IO uint32_t UECS2E : 1;
+ __IO uint32_t UECS3E : 1;
+ __IO uint32_t UECS4E : 1;
+ __IO uint32_t UECS5E : 1;
+ __IO uint32_t UECS6E : 1;
+ __IO uint32_t UECS7E : 1;
+ __IO uint32_t UEAOOE : 1;
+ __IO uint32_t UEA08E : 1;
+ __IO uint32_t UEA09E : 1;
+ __IO uint32_t UEA10E : 1;
+ __IO uint32_t UEA11E : 1;
+ __IO uint32_t UEA12E : 1;
+ __IO uint32_t UEA13E : 1;
+ __IO uint32_t UEA14E : 1;
+ __IO uint32_t UEA15E : 1;
+ __IO uint32_t UEA16E : 1;
+ __IO uint32_t UEA17E : 1;
+ __IO uint32_t UEA18E : 1;
+ __IO uint32_t UEA19E : 1;
+ __IO uint32_t UEA20E : 1;
+ __IO uint32_t UEA21E : 1;
+ __IO uint32_t UEA22E : 1;
+ __IO uint32_t UEA23E : 1;
+ __IO uint32_t UEA24E : 1;
+} stc_gpio_epfr10_field_t;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* LVD_MODULE register bit fields */
+typedef struct stc_lvd_lvd_ctl_field
+{
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t SVHI0 : 1;
+ __IO uint8_t SVHI1 : 1;
+ __IO uint8_t SVHI2 : 1;
+ __IO uint8_t SVHI3 : 1;
+ uint8_t RESERVED2 : 1;
+ __IO uint8_t LVDIE : 1;
+} stc_lvd_lvd_ctl_field_t;
+
+typedef struct stc_lvd_lvd_str_field
+{
+ uint8_t RESERVED1 : 7;
+ __IO uint8_t LVDIR : 1;
+} stc_lvd_lvd_str_field_t;
+
+typedef struct stc_lvd_lvd_clr_field
+{
+ uint8_t RESERVED1 : 7;
+ __IO uint8_t LVDCL : 1;
+} stc_lvd_lvd_clr_field_t;
+
+typedef struct stc_lvd_lvd_str2_field
+{
+ uint8_t RESERVED1 : 7;
+ __IO uint8_t LVDIRDY : 1;
+} stc_lvd_lvd_str2_field_t;
+
+/******************************************************************************
+ * USBCLK
+ ******************************************************************************/
+/* USBCLK register bit fields */
+typedef struct stc_usbclk_uccr_field
+{
+ __IO uint8_t UCEN : 1;
+ __IO uint8_t UCSEL : 1;
+} stc_usbclk_uccr_field_t;
+
+typedef struct stc_usbclk_upcr1_field
+{
+ __IO uint8_t UPLLEN : 1;
+ __IO uint8_t UPINC : 1;
+} stc_usbclk_upcr1_field_t;
+
+typedef struct stc_usbclk_upcr2_field
+{
+ __IO uint8_t UPOWT0 : 1;
+ __IO uint8_t UPOWT1 : 1;
+ __IO uint8_t UPOWT2 : 1;
+} stc_usbclk_upcr2_field_t;
+
+typedef struct stc_usbclk_upcr3_field
+{
+ __IO uint8_t UPLLK0 : 1;
+ __IO uint8_t UPLLK1 : 1;
+ __IO uint8_t UPLLK2 : 1;
+ __IO uint8_t UPLLK3 : 1;
+ __IO uint8_t UPLLK4 : 1;
+} stc_usbclk_upcr3_field_t;
+
+typedef struct stc_usbclk_upcr4_field
+{
+ __IO uint8_t UPLLN0 : 1;
+ __IO uint8_t UPLLN1 : 1;
+ __IO uint8_t UPLLN2 : 1;
+ __IO uint8_t UPLLN3 : 1;
+ __IO uint8_t UPLLN4 : 1;
+} stc_usbclk_upcr4_field_t;
+
+typedef struct stc_usbclk_up_str_field
+{
+ __IO uint8_t UPRDY : 1;
+} stc_usbclk_up_str_field_t;
+
+typedef struct stc_usbclk_upint_enr_field
+{
+ __IO uint8_t UPCSE : 1;
+} stc_usbclk_upint_enr_field_t;
+
+typedef struct stc_usbclk_upint_clr_field
+{
+ __IO uint8_t UPCSC : 1;
+} stc_usbclk_upint_clr_field_t;
+
+typedef struct stc_usbclk_upint_str_field
+{
+ __IO uint8_t UPCSI : 1;
+} stc_usbclk_upint_str_field_t;
+
+typedef struct stc_usbclk_usben_field
+{
+ __IO uint8_t USBEN : 1;
+} stc_usbclk_usben_field_t;
+
+/******************************************************************************
+ * CANPRE_MODULE
+ ******************************************************************************/
+/* CANPRE_MODULE register bit fields */
+typedef struct stc_canpre_canpre_field
+{
+ __IO uint8_t CANPRE0 : 1;
+ __IO uint8_t CANPRE1 : 1;
+ __IO uint8_t CANPRE2 : 1;
+ __IO uint8_t CANPRE3 : 1;
+} stc_canpre_canpre_field_t;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* MFS03_UART_MODULE register bit fields */
+typedef struct stc_mfs03_uart_smr_field
+{
+ __IO uint8_t SOE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t BDS : 1;
+ __IO uint8_t SBL : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs03_uart_smr_field_t;
+
+typedef struct stc_mfs03_uart_scr_field
+{
+ __IO uint8_t TXE : 1;
+ __IO uint8_t RXE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t UPCL : 1;
+} stc_mfs03_uart_scr_field_t;
+
+typedef struct stc_mfs03_uart_escr_field
+{
+ __IO uint8_t L0 : 1;
+ __IO uint8_t L1 : 1;
+ __IO uint8_t L2 : 1;
+ __IO uint8_t P : 1;
+ __IO uint8_t PEN : 1;
+ __IO uint8_t INV : 1;
+ __IO uint8_t ESBL : 1;
+ __IO uint8_t FLWEN : 1;
+} stc_mfs03_uart_escr_field_t;
+
+typedef struct stc_mfs03_uart_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ __IO uint8_t FRE : 1;
+ __IO uint8_t PE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t REC : 1;
+} stc_mfs03_uart_ssr_field_t;
+
+typedef struct stc_mfs03_uart_rdr_field
+{
+ uint16_t RESERVED1 : 8;
+ __IO uint16_t AD : 1;
+} stc_mfs03_uart_rdr_field_t;
+
+typedef struct stc_mfs03_uart_tdr_field
+{
+ uint16_t RESERVED1 : 8;
+ __IO uint16_t AD : 1;
+} stc_mfs03_uart_tdr_field_t;
+
+typedef struct stc_mfs03_uart_bgr_field
+{
+ uint16_t RESERVED1 : 15;
+ __IO uint16_t EXT : 1;
+} stc_mfs03_uart_bgr_field_t;
+
+typedef struct stc_mfs03_uart_bgr1_field
+{
+ uint8_t RESERVED1 : 7;
+ __IO uint8_t EXT : 1;
+} stc_mfs03_uart_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* MFS03_CSIO_MODULE register bit fields */
+typedef struct stc_mfs03_csio_smr_field
+{
+ __IO uint8_t SOE : 1;
+ __IO uint8_t SCKE : 1;
+ __IO uint8_t BDS : 1;
+ __IO uint8_t SCINV : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs03_csio_smr_field_t;
+
+typedef struct stc_mfs03_csio_scr_field
+{
+ __IO uint8_t TXE : 1;
+ __IO uint8_t RXE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ __IO uint8_t SPI : 1;
+ __IO uint8_t MS : 1;
+ __IO uint8_t UPCL : 1;
+} stc_mfs03_csio_scr_field_t;
+
+typedef struct stc_mfs03_csio_escr_field
+{
+ __IO uint8_t L0 : 1;
+ __IO uint8_t L1 : 1;
+ __IO uint8_t L2 : 1;
+ __IO uint8_t WT0 : 1;
+ __IO uint8_t WT1 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t SOP : 1;
+} stc_mfs03_csio_escr_field_t;
+
+typedef struct stc_mfs03_csio_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ uint8_t RESERVED1 : 3;
+ __IO uint8_t REC : 1;
+} stc_mfs03_csio_ssr_field_t;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* MFS03_LIN_MODULE register bit fields */
+typedef struct stc_mfs03_lin_smr_field
+{
+ __IO uint8_t SOE : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t SBL : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs03_lin_smr_field_t;
+
+typedef struct stc_mfs03_lin_scr_field
+{
+ __IO uint8_t TXE : 1;
+ __IO uint8_t RXE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ __IO uint8_t LBR : 1;
+ __IO uint8_t MS : 1;
+ __IO uint8_t UPCL : 1;
+} stc_mfs03_lin_scr_field_t;
+
+typedef struct stc_mfs03_lin_escr_field
+{
+ __IO uint8_t DEL0 : 1;
+ __IO uint8_t DEL1 : 1;
+ __IO uint8_t LBL0 : 1;
+ __IO uint8_t LBL1 : 1;
+ __IO uint8_t LBIE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t ESBL : 1;
+} stc_mfs03_lin_escr_field_t;
+
+typedef struct stc_mfs03_lin_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ __IO uint8_t FRE : 1;
+ __IO uint8_t LBD : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t REC : 1;
+} stc_mfs03_lin_ssr_field_t;
+
+typedef struct stc_mfs03_lin_bgr_field
+{
+ uint16_t RESERVED1 : 15;
+ __IO uint16_t EXT : 1;
+} stc_mfs03_lin_bgr_field_t;
+
+typedef struct stc_mfs03_lin_bgr1_field
+{
+ uint8_t RESERVED1 : 7;
+ __IO uint8_t EXT : 1;
+} stc_mfs03_lin_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* MFS03_I2C_MODULE register bit fields */
+typedef struct stc_mfs03_i2c_smr_field
+{
+ __IO uint8_t ITST0 : 1;
+ __IO uint8_t ITST1 : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs03_i2c_smr_field_t;
+
+typedef struct stc_mfs03_i2c_ibcr_field
+{
+ __IO uint8_t INT : 1;
+ __IO uint8_t BER : 1;
+ __IO uint8_t INTE : 1;
+ __IO uint8_t CNDE : 1;
+ __IO uint8_t WSEL : 1;
+ __IO uint8_t ACKE : 1;
+ __IO uint8_t SCC : 1;
+ __IO uint8_t MSS : 1;
+} stc_mfs03_i2c_ibcr_field_t;
+
+typedef struct stc_mfs03_i2c_ibsr_field
+{
+ __IO uint8_t BB : 1;
+ __IO uint8_t SPC : 1;
+ __IO uint8_t RSC : 1;
+ __IO uint8_t AL : 1;
+ __IO uint8_t TRX : 1;
+ __IO uint8_t RSA : 1;
+ __IO uint8_t RACK : 1;
+ __IO uint8_t FBT : 1;
+} stc_mfs03_i2c_ibsr_field_t;
+
+typedef struct stc_mfs03_i2c_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t DMA : 1;
+ __IO uint8_t TSET : 1;
+ __IO uint8_t REC : 1;
+} stc_mfs03_i2c_ssr_field_t;
+
+typedef struct stc_mfs03_i2c_isba_field
+{
+ __IO uint8_t SA0 : 1;
+ __IO uint8_t SA1 : 1;
+ __IO uint8_t SA2 : 1;
+ __IO uint8_t SA3 : 1;
+ __IO uint8_t SA4 : 1;
+ __IO uint8_t SA5 : 1;
+ __IO uint8_t SA6 : 1;
+ __IO uint8_t SAEN : 1;
+} stc_mfs03_i2c_isba_field_t;
+
+typedef struct stc_mfs03_i2c_ismk_field
+{
+ __IO uint8_t SM0 : 1;
+ __IO uint8_t SM1 : 1;
+ __IO uint8_t SM2 : 1;
+ __IO uint8_t SM3 : 1;
+ __IO uint8_t SM4 : 1;
+ __IO uint8_t SM5 : 1;
+ __IO uint8_t SM6 : 1;
+ __IO uint8_t EN : 1;
+} stc_mfs03_i2c_ismk_field_t;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* MFS47_UART_MODULE register bit fields */
+typedef struct stc_mfs47_uart_smr_field
+{
+ __IO uint8_t SOE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t BDS : 1;
+ __IO uint8_t SBL : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs47_uart_smr_field_t;
+
+typedef struct stc_mfs47_uart_scr_field
+{
+ __IO uint8_t TXE : 1;
+ __IO uint8_t RXE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t UPCL : 1;
+} stc_mfs47_uart_scr_field_t;
+
+typedef struct stc_mfs47_uart_escr_field
+{
+ __IO uint8_t L0 : 1;
+ __IO uint8_t L1 : 1;
+ __IO uint8_t L2 : 1;
+ __IO uint8_t P : 1;
+ __IO uint8_t PEN : 1;
+ __IO uint8_t INV : 1;
+ __IO uint8_t ESBL : 1;
+ __IO uint8_t FLWEN : 1;
+} stc_mfs47_uart_escr_field_t;
+
+typedef struct stc_mfs47_uart_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ __IO uint8_t FRE : 1;
+ __IO uint8_t PE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t REC : 1;
+} stc_mfs47_uart_ssr_field_t;
+
+typedef struct stc_mfs47_uart_rdr_field
+{
+ uint16_t RESERVED1 : 8;
+ __IO uint16_t AD : 1;
+} stc_mfs47_uart_rdr_field_t;
+
+typedef struct stc_mfs47_uart_tdr_field
+{
+ uint16_t RESERVED1 : 8;
+ __IO uint16_t AD : 1;
+} stc_mfs47_uart_tdr_field_t;
+
+typedef struct stc_mfs47_uart_bgr_field
+{
+ uint16_t RESERVED1 : 15;
+ __IO uint16_t EXT : 1;
+} stc_mfs47_uart_bgr_field_t;
+
+typedef struct stc_mfs47_uart_bgr1_field
+{
+ uint8_t RESERVED1 : 7;
+ __IO uint8_t EXT : 1;
+} stc_mfs47_uart_bgr1_field_t;
+
+typedef struct stc_mfs47_uart_fcr_field
+{
+ __IO uint16_t FE1 : 1;
+ __IO uint16_t FE2 : 1;
+ __IO uint16_t FCL1 : 1;
+ __IO uint16_t FCL2 : 1;
+ __IO uint16_t FSET : 1;
+ __IO uint16_t FLD : 1;
+ __IO uint16_t FLST : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t FSEL : 1;
+ __IO uint16_t FTIE : 1;
+ __IO uint16_t FDRQ : 1;
+ __IO uint16_t FRIE : 1;
+ __IO uint16_t FLSTE : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t FTST0 : 1;
+ __IO uint16_t FTST1 : 1;
+} stc_mfs47_uart_fcr_field_t;
+
+typedef struct stc_mfs47_uart_fcr0_field
+{
+ __IO uint8_t FE1 : 1;
+ __IO uint8_t FE2 : 1;
+ __IO uint8_t FCL1 : 1;
+ __IO uint8_t FCL2 : 1;
+ __IO uint8_t FSET : 1;
+ __IO uint8_t FLD : 1;
+ __IO uint8_t FLST : 1;
+} stc_mfs47_uart_fcr0_field_t;
+
+typedef struct stc_mfs47_uart_fcr1_field
+{
+ __IO uint8_t FSEL : 1;
+ __IO uint8_t FTIE : 1;
+ __IO uint8_t FDRQ : 1;
+ __IO uint8_t FRIE : 1;
+ __IO uint8_t FLSTE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t FTST0 : 1;
+ __IO uint8_t FTST1 : 1;
+} stc_mfs47_uart_fcr1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte_field
+{
+ __IO uint16_t FD0 : 1;
+ __IO uint16_t FD1 : 1;
+ __IO uint16_t FD2 : 1;
+ __IO uint16_t FD3 : 1;
+ __IO uint16_t FD4 : 1;
+ __IO uint16_t FD5 : 1;
+ __IO uint16_t FD6 : 1;
+ __IO uint16_t FD7 : 1;
+ __IO uint16_t FD8 : 1;
+ __IO uint16_t FD9 : 1;
+ __IO uint16_t FD10 : 1;
+ __IO uint16_t FD11 : 1;
+ __IO uint16_t FD12 : 1;
+ __IO uint16_t FD13 : 1;
+ __IO uint16_t FD14 : 1;
+ __IO uint16_t FD15 : 1;
+} stc_mfs47_uart_fbyte_field_t;
+
+typedef struct stc_mfs47_uart_fbyte1_field
+{
+ __IO uint8_t FD0 : 1;
+ __IO uint8_t FD1 : 1;
+ __IO uint8_t FD2 : 1;
+ __IO uint8_t FD3 : 1;
+ __IO uint8_t FD4 : 1;
+ __IO uint8_t FD5 : 1;
+ __IO uint8_t FD6 : 1;
+ __IO uint8_t FD7 : 1;
+} stc_mfs47_uart_fbyte1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte2_field
+{
+ __IO uint8_t FD8 : 1;
+ __IO uint8_t FD9 : 1;
+ __IO uint8_t FD10 : 1;
+ __IO uint8_t FD11 : 1;
+ __IO uint8_t FD12 : 1;
+ __IO uint8_t FD13 : 1;
+ __IO uint8_t FD14 : 1;
+ __IO uint8_t FD15 : 1;
+} stc_mfs47_uart_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* MFS47_CSIO_MODULE register bit fields */
+typedef struct stc_mfs47_csio_smr_field
+{
+ __IO uint8_t SOE : 1;
+ __IO uint8_t SCKE : 1;
+ __IO uint8_t BDS : 1;
+ __IO uint8_t SCINV : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs47_csio_smr_field_t;
+
+typedef struct stc_mfs47_csio_scr_field
+{
+ __IO uint8_t TXE : 1;
+ __IO uint8_t RXE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ __IO uint8_t SPI : 1;
+ __IO uint8_t MS : 1;
+ __IO uint8_t UPCL : 1;
+} stc_mfs47_csio_scr_field_t;
+
+typedef struct stc_mfs47_csio_escr_field
+{
+ __IO uint8_t L0 : 1;
+ __IO uint8_t L1 : 1;
+ __IO uint8_t L2 : 1;
+ __IO uint8_t WT0 : 1;
+ __IO uint8_t WT1 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t SOP : 1;
+} stc_mfs47_csio_escr_field_t;
+
+typedef struct stc_mfs47_csio_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ uint8_t RESERVED1 : 3;
+ __IO uint8_t REC : 1;
+} stc_mfs47_csio_ssr_field_t;
+
+typedef struct stc_mfs47_csio_fcr_field
+{
+ __IO uint16_t FE1 : 1;
+ __IO uint16_t FE2 : 1;
+ __IO uint16_t FCL1 : 1;
+ __IO uint16_t FCL2 : 1;
+ __IO uint16_t FSET : 1;
+ __IO uint16_t FLD : 1;
+ __IO uint16_t FLST : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t FSEL : 1;
+ __IO uint16_t FTIE : 1;
+ __IO uint16_t FDRQ : 1;
+ __IO uint16_t FRIE : 1;
+ __IO uint16_t FLSTE : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t FTST0 : 1;
+ __IO uint16_t FTST1 : 1;
+} stc_mfs47_csio_fcr_field_t;
+
+typedef struct stc_mfs47_csio_fcr0_field
+{
+ __IO uint8_t FE1 : 1;
+ __IO uint8_t FE2 : 1;
+ __IO uint8_t FCL1 : 1;
+ __IO uint8_t FCL2 : 1;
+ __IO uint8_t FSET : 1;
+ __IO uint8_t FLD : 1;
+ __IO uint8_t FLST : 1;
+} stc_mfs47_csio_fcr0_field_t;
+
+typedef struct stc_mfs47_csio_fcr1_field
+{
+ __IO uint8_t FSEL : 1;
+ __IO uint8_t FTIE : 1;
+ __IO uint8_t FDRQ : 1;
+ __IO uint8_t FRIE : 1;
+ __IO uint8_t FLSTE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t FTST0 : 1;
+ __IO uint8_t FTST1 : 1;
+} stc_mfs47_csio_fcr1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte_field
+{
+ __IO uint16_t FD0 : 1;
+ __IO uint16_t FD1 : 1;
+ __IO uint16_t FD2 : 1;
+ __IO uint16_t FD3 : 1;
+ __IO uint16_t FD4 : 1;
+ __IO uint16_t FD5 : 1;
+ __IO uint16_t FD6 : 1;
+ __IO uint16_t FD7 : 1;
+ __IO uint16_t FD8 : 1;
+ __IO uint16_t FD9 : 1;
+ __IO uint16_t FD10 : 1;
+ __IO uint16_t FD11 : 1;
+ __IO uint16_t FD12 : 1;
+ __IO uint16_t FD13 : 1;
+ __IO uint16_t FD14 : 1;
+ __IO uint16_t FD15 : 1;
+} stc_mfs47_csio_fbyte_field_t;
+
+typedef struct stc_mfs47_csio_fbyte1_field
+{
+ __IO uint8_t FD0 : 1;
+ __IO uint8_t FD1 : 1;
+ __IO uint8_t FD2 : 1;
+ __IO uint8_t FD3 : 1;
+ __IO uint8_t FD4 : 1;
+ __IO uint8_t FD5 : 1;
+ __IO uint8_t FD6 : 1;
+ __IO uint8_t FD7 : 1;
+} stc_mfs47_csio_fbyte1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte2_field
+{
+ __IO uint8_t FD8 : 1;
+ __IO uint8_t FD9 : 1;
+ __IO uint8_t FD10 : 1;
+ __IO uint8_t FD11 : 1;
+ __IO uint8_t FD12 : 1;
+ __IO uint8_t FD13 : 1;
+ __IO uint8_t FD14 : 1;
+ __IO uint8_t FD15 : 1;
+} stc_mfs47_csio_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* MFS47_LIN_MODULE register bit fields */
+typedef struct stc_mfs47_lin_smr_field
+{
+ __IO uint8_t SOE : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t SBL : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs47_lin_smr_field_t;
+
+typedef struct stc_mfs47_lin_scr_field
+{
+ __IO uint8_t TXE : 1;
+ __IO uint8_t RXE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ __IO uint8_t LBR : 1;
+ __IO uint8_t MS : 1;
+ __IO uint8_t UPCL : 1;
+} stc_mfs47_lin_scr_field_t;
+
+typedef struct stc_mfs47_lin_escr_field
+{
+ __IO uint8_t DEL0 : 1;
+ __IO uint8_t DEL1 : 1;
+ __IO uint8_t LBL0 : 1;
+ __IO uint8_t LBL1 : 1;
+ __IO uint8_t LBIE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t ESBL : 1;
+} stc_mfs47_lin_escr_field_t;
+
+typedef struct stc_mfs47_lin_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ __IO uint8_t FRE : 1;
+ __IO uint8_t LBD : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t REC : 1;
+} stc_mfs47_lin_ssr_field_t;
+
+typedef struct stc_mfs47_lin_bgr_field
+{
+ uint16_t RESERVED1 : 15;
+ __IO uint16_t EXT : 1;
+} stc_mfs47_lin_bgr_field_t;
+
+typedef struct stc_mfs47_lin_bgr1_field
+{
+ uint8_t RESERVED1 : 7;
+ __IO uint8_t EXT : 1;
+} stc_mfs47_lin_bgr1_field_t;
+
+typedef struct stc_mfs47_lin_fcr_field
+{
+ __IO uint16_t FE1 : 1;
+ __IO uint16_t FE2 : 1;
+ __IO uint16_t FCL1 : 1;
+ __IO uint16_t FCL2 : 1;
+ __IO uint16_t FSET : 1;
+ __IO uint16_t FLD : 1;
+ __IO uint16_t FLST : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t FSEL : 1;
+ __IO uint16_t FTIE : 1;
+ __IO uint16_t FDRQ : 1;
+ __IO uint16_t FRIE : 1;
+ __IO uint16_t FLSTE : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t FTST0 : 1;
+ __IO uint16_t FTST1 : 1;
+} stc_mfs47_lin_fcr_field_t;
+
+typedef struct stc_mfs47_lin_fcr0_field
+{
+ __IO uint8_t FE1 : 1;
+ __IO uint8_t FE2 : 1;
+ __IO uint8_t FCL1 : 1;
+ __IO uint8_t FCL2 : 1;
+ __IO uint8_t FSET : 1;
+ __IO uint8_t FLD : 1;
+ __IO uint8_t FLST : 1;
+} stc_mfs47_lin_fcr0_field_t;
+
+typedef struct stc_mfs47_lin_fcr1_field
+{
+ __IO uint8_t FSEL : 1;
+ __IO uint8_t FTIE : 1;
+ __IO uint8_t FDRQ : 1;
+ __IO uint8_t FRIE : 1;
+ __IO uint8_t FLSTE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t FTST0 : 1;
+ __IO uint8_t FTST1 : 1;
+} stc_mfs47_lin_fcr1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte_field
+{
+ __IO uint16_t FD0 : 1;
+ __IO uint16_t FD1 : 1;
+ __IO uint16_t FD2 : 1;
+ __IO uint16_t FD3 : 1;
+ __IO uint16_t FD4 : 1;
+ __IO uint16_t FD5 : 1;
+ __IO uint16_t FD6 : 1;
+ __IO uint16_t FD7 : 1;
+ __IO uint16_t FD8 : 1;
+ __IO uint16_t FD9 : 1;
+ __IO uint16_t FD10 : 1;
+ __IO uint16_t FD11 : 1;
+ __IO uint16_t FD12 : 1;
+ __IO uint16_t FD13 : 1;
+ __IO uint16_t FD14 : 1;
+ __IO uint16_t FD15 : 1;
+} stc_mfs47_lin_fbyte_field_t;
+
+typedef struct stc_mfs47_lin_fbyte1_field
+{
+ __IO uint8_t FD0 : 1;
+ __IO uint8_t FD1 : 1;
+ __IO uint8_t FD2 : 1;
+ __IO uint8_t FD3 : 1;
+ __IO uint8_t FD4 : 1;
+ __IO uint8_t FD5 : 1;
+ __IO uint8_t FD6 : 1;
+ __IO uint8_t FD7 : 1;
+} stc_mfs47_lin_fbyte1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte2_field
+{
+ __IO uint8_t FD8 : 1;
+ __IO uint8_t FD9 : 1;
+ __IO uint8_t FD10 : 1;
+ __IO uint8_t FD11 : 1;
+ __IO uint8_t FD12 : 1;
+ __IO uint8_t FD13 : 1;
+ __IO uint8_t FD14 : 1;
+ __IO uint8_t FD15 : 1;
+} stc_mfs47_lin_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* MFS47_I2C_MODULE register bit fields */
+typedef struct stc_mfs47_i2c_smr_field
+{
+ __IO uint8_t ITST0 : 1;
+ __IO uint8_t ITST1 : 1;
+ __IO uint8_t TIE : 1;
+ __IO uint8_t RIE : 1;
+ __IO uint8_t WUCR : 1;
+ __IO uint8_t MD0 : 1;
+ __IO uint8_t MD1 : 1;
+ __IO uint8_t MD2 : 1;
+} stc_mfs47_i2c_smr_field_t;
+
+typedef struct stc_mfs47_i2c_ibcr_field
+{
+ __IO uint8_t INT : 1;
+ __IO uint8_t BER : 1;
+ __IO uint8_t INTE : 1;
+ __IO uint8_t CNDE : 1;
+ __IO uint8_t WSEL : 1;
+ __IO uint8_t ACKE : 1;
+ __IO uint8_t SCC : 1;
+ __IO uint8_t MSS : 1;
+} stc_mfs47_i2c_ibcr_field_t;
+
+typedef struct stc_mfs47_i2c_ibsr_field
+{
+ __IO uint8_t BB : 1;
+ __IO uint8_t SPC : 1;
+ __IO uint8_t RSC : 1;
+ __IO uint8_t AL : 1;
+ __IO uint8_t TRX : 1;
+ __IO uint8_t RSA : 1;
+ __IO uint8_t RACK : 1;
+ __IO uint8_t FBT : 1;
+} stc_mfs47_i2c_ibsr_field_t;
+
+typedef struct stc_mfs47_i2c_ssr_field
+{
+ __IO uint8_t TBI : 1;
+ __IO uint8_t TDRE : 1;
+ __IO uint8_t RDRF : 1;
+ __IO uint8_t ORE : 1;
+ __IO uint8_t TBIE : 1;
+ __IO uint8_t DMA : 1;
+ __IO uint8_t TSET : 1;
+ __IO uint8_t REC : 1;
+} stc_mfs47_i2c_ssr_field_t;
+
+typedef struct stc_mfs47_i2c_isba_field
+{
+ __IO uint8_t SA0 : 1;
+ __IO uint8_t SA1 : 1;
+ __IO uint8_t SA2 : 1;
+ __IO uint8_t SA3 : 1;
+ __IO uint8_t SA4 : 1;
+ __IO uint8_t SA5 : 1;
+ __IO uint8_t SA6 : 1;
+ __IO uint8_t SAEN : 1;
+} stc_mfs47_i2c_isba_field_t;
+
+typedef struct stc_mfs47_i2c_ismk_field
+{
+ __IO uint8_t SM0 : 1;
+ __IO uint8_t SM1 : 1;
+ __IO uint8_t SM2 : 1;
+ __IO uint8_t SM3 : 1;
+ __IO uint8_t SM4 : 1;
+ __IO uint8_t SM5 : 1;
+ __IO uint8_t SM6 : 1;
+ __IO uint8_t EN : 1;
+} stc_mfs47_i2c_ismk_field_t;
+
+typedef struct stc_mfs47_i2c_fcr_field
+{
+ __IO uint16_t FE1 : 1;
+ __IO uint16_t FE2 : 1;
+ __IO uint16_t FCL1 : 1;
+ __IO uint16_t FCL2 : 1;
+ __IO uint16_t FSET : 1;
+ __IO uint16_t FLD : 1;
+ __IO uint16_t FLST : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t FSEL : 1;
+ __IO uint16_t FTIE : 1;
+ __IO uint16_t FDRQ : 1;
+ __IO uint16_t FRIE : 1;
+ __IO uint16_t FLSTE : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t FTST0 : 1;
+ __IO uint16_t FTST1 : 1;
+} stc_mfs47_i2c_fcr_field_t;
+
+typedef struct stc_mfs47_i2c_fcr0_field
+{
+ __IO uint8_t FE1 : 1;
+ __IO uint8_t FE2 : 1;
+ __IO uint8_t FCL1 : 1;
+ __IO uint8_t FCL2 : 1;
+ __IO uint8_t FSET : 1;
+ __IO uint8_t FLD : 1;
+ __IO uint8_t FLST : 1;
+} stc_mfs47_i2c_fcr0_field_t;
+
+typedef struct stc_mfs47_i2c_fcr1_field
+{
+ __IO uint8_t FSEL : 1;
+ __IO uint8_t FTIE : 1;
+ __IO uint8_t FDRQ : 1;
+ __IO uint8_t FRIE : 1;
+ __IO uint8_t FLSTE : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t FTST0 : 1;
+ __IO uint8_t FTST1 : 1;
+} stc_mfs47_i2c_fcr1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte_field
+{
+ __IO uint16_t FD0 : 1;
+ __IO uint16_t FD1 : 1;
+ __IO uint16_t FD2 : 1;
+ __IO uint16_t FD3 : 1;
+ __IO uint16_t FD4 : 1;
+ __IO uint16_t FD5 : 1;
+ __IO uint16_t FD6 : 1;
+ __IO uint16_t FD7 : 1;
+ __IO uint16_t FD8 : 1;
+ __IO uint16_t FD9 : 1;
+ __IO uint16_t FD10 : 1;
+ __IO uint16_t FD11 : 1;
+ __IO uint16_t FD12 : 1;
+ __IO uint16_t FD13 : 1;
+ __IO uint16_t FD14 : 1;
+ __IO uint16_t FD15 : 1;
+} stc_mfs47_i2c_fbyte_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte1_field
+{
+ __IO uint8_t FD0 : 1;
+ __IO uint8_t FD1 : 1;
+ __IO uint8_t FD2 : 1;
+ __IO uint8_t FD3 : 1;
+ __IO uint8_t FD4 : 1;
+ __IO uint8_t FD5 : 1;
+ __IO uint8_t FD6 : 1;
+ __IO uint8_t FD7 : 1;
+} stc_mfs47_i2c_fbyte1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte2_field
+{
+ __IO uint8_t FD8 : 1;
+ __IO uint8_t FD9 : 1;
+ __IO uint8_t FD10 : 1;
+ __IO uint8_t FD11 : 1;
+ __IO uint8_t FD12 : 1;
+ __IO uint8_t FD13 : 1;
+ __IO uint8_t FD14 : 1;
+ __IO uint8_t FD15 : 1;
+} stc_mfs47_i2c_fbyte2_field_t;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC_MODULE register bit fields */
+typedef struct stc_crc_crccr_field
+{
+ __IO uint8_t INIT : 1;
+ __IO uint8_t CRC32 : 1;
+ __IO uint8_t LTLEND : 1;
+ __IO uint8_t LSBFST : 1;
+ __IO uint8_t CRCLTE : 1;
+ __IO uint8_t CRCLSF : 1;
+ __IO uint8_t FXOR : 1;
+} stc_crc_crccr_field_t;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* WC_MODULE register bit fields */
+typedef struct stc_wc_wcrd_field
+{
+ __IO uint8_t CTR0 : 1;
+ __IO uint8_t CTR1 : 1;
+ __IO uint8_t CTR2 : 1;
+ __IO uint8_t CTR3 : 1;
+ __IO uint8_t CTR4 : 1;
+ __IO uint8_t CTR5 : 1;
+} stc_wc_wcrd_field_t;
+
+typedef struct stc_wc_wcrl_field
+{
+ __IO uint8_t RLC0 : 1;
+ __IO uint8_t RLC1 : 1;
+ __IO uint8_t RLC2 : 1;
+ __IO uint8_t RLC3 : 1;
+ __IO uint8_t RLC4 : 1;
+ __IO uint8_t RLC5 : 1;
+} stc_wc_wcrl_field_t;
+
+typedef struct stc_wc_wccr_field
+{
+ __IO uint8_t WCIF : 1;
+ __IO uint8_t WCIE : 1;
+ __IO uint8_t CS0 : 1;
+ __IO uint8_t CS1 : 1;
+ uint8_t RESERVED1 : 2;
+ __IO uint8_t WCOP : 1;
+ __IO uint8_t WCEN : 1;
+} stc_wc_wccr_field_t;
+
+typedef struct stc_wc_clk_sel_field
+{
+ __IO uint16_t SEL_IN : 1;
+ uint16_t RESERVED1 : 7;
+ __IO uint16_t SEL_OUT : 1;
+} stc_wc_clk_sel_field_t;
+
+typedef struct stc_wc_clk_en_field
+{
+ __IO uint8_t CLK_EN : 1;
+ __IO uint8_t CLK_EN_R : 1;
+} stc_wc_clk_en_field_t;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* EXBUS_MODULE register bit fields */
+typedef struct stc_exbus_mode0_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode0_field_t;
+
+typedef struct stc_exbus_mode1_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode1_field_t;
+
+typedef struct stc_exbus_mode2_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode2_field_t;
+
+typedef struct stc_exbus_mode3_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode3_field_t;
+
+typedef struct stc_exbus_mode4_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode4_field_t;
+
+typedef struct stc_exbus_mode5_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode5_field_t;
+
+typedef struct stc_exbus_mode6_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode6_field_t;
+
+typedef struct stc_exbus_mode7_field
+{
+ __IO uint32_t WDTH0 : 1;
+ __IO uint32_t WDTH1 : 1;
+ __IO uint32_t RBMON : 1;
+ __IO uint32_t WEOFF : 1;
+ __IO uint32_t NAND : 1;
+ __IO uint32_t PAGE : 1;
+ __IO uint32_t TEST : 1;
+} stc_exbus_mode7_field_t;
+
+typedef struct stc_exbus_tim0_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim0_field_t;
+
+typedef struct stc_exbus_tim1_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim1_field_t;
+
+typedef struct stc_exbus_tim2_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim2_field_t;
+
+typedef struct stc_exbus_tim3_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim3_field_t;
+
+typedef struct stc_exbus_tim4_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim4_field_t;
+
+typedef struct stc_exbus_tim5_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim5_field_t;
+
+typedef struct stc_exbus_tim6_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim6_field_t;
+
+typedef struct stc_exbus_tim7_field
+{
+ __IO uint32_t RACC0 : 1;
+ __IO uint32_t RACC1 : 1;
+ __IO uint32_t RACC2 : 1;
+ __IO uint32_t RACC3 : 1;
+ __IO uint32_t RADC0 : 1;
+ __IO uint32_t RADC1 : 1;
+ __IO uint32_t RADC2 : 1;
+ __IO uint32_t RADC3 : 1;
+ __IO uint32_t FRADC0 : 1;
+ __IO uint32_t FRADC1 : 1;
+ __IO uint32_t FRADC2 : 1;
+ __IO uint32_t FRADC3 : 1;
+ __IO uint32_t RIDLC0 : 1;
+ __IO uint32_t RIDLC1 : 1;
+ __IO uint32_t RIDLC2 : 1;
+ __IO uint32_t RIDLC3 : 1;
+ __IO uint32_t WACC0 : 1;
+ __IO uint32_t WACC1 : 1;
+ __IO uint32_t WACC2 : 1;
+ __IO uint32_t WACC3 : 1;
+ __IO uint32_t WADC0 : 1;
+ __IO uint32_t WADC1 : 1;
+ __IO uint32_t WADC2 : 1;
+ __IO uint32_t WADC3 : 1;
+ __IO uint32_t WWEC0 : 1;
+ __IO uint32_t WWEC1 : 1;
+ __IO uint32_t WWEC2 : 1;
+ __IO uint32_t WWEC3 : 1;
+ __IO uint32_t WIDLC0 : 1;
+ __IO uint32_t WIDLC1 : 1;
+ __IO uint32_t WIDLC2 : 1;
+ __IO uint32_t WIDLC3 : 1;
+} stc_exbus_tim7_field_t;
+
+typedef struct stc_exbus_area0_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area0_field_t;
+
+typedef struct stc_exbus_area1_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area1_field_t;
+
+typedef struct stc_exbus_area2_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area2_field_t;
+
+typedef struct stc_exbus_area3_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area3_field_t;
+
+typedef struct stc_exbus_area4_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area4_field_t;
+
+typedef struct stc_exbus_area5_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area5_field_t;
+
+typedef struct stc_exbus_area6_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area6_field_t;
+
+typedef struct stc_exbus_area7_field
+{
+ __IO uint32_t ADDR0 : 1;
+ __IO uint32_t ADDR1 : 1;
+ __IO uint32_t ADDR2 : 1;
+ __IO uint32_t ADDR3 : 1;
+ __IO uint32_t ADDR4 : 1;
+ __IO uint32_t ADDR5 : 1;
+ __IO uint32_t ADDR6 : 1;
+ __IO uint32_t ADDR7 : 1;
+ uint32_t RESERVED1 : 8;
+ __IO uint32_t MASK0 : 1;
+ __IO uint32_t MASK1 : 1;
+ __IO uint32_t MASK2 : 1;
+ __IO uint32_t MASK3 : 1;
+ __IO uint32_t MASK4 : 1;
+ __IO uint32_t MASK5 : 1;
+ __IO uint32_t MASK6 : 1;
+} stc_exbus_area7_field_t;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB_MODULE register bit fields */
+typedef struct stc_usb_hcnt_field
+{
+ __IO uint16_t HOST : 1;
+ __IO uint16_t URST : 1;
+ __IO uint16_t SOFIRE : 1;
+ __IO uint16_t DIRE : 1;
+ __IO uint16_t CNNIRE : 1;
+ __IO uint16_t CMPIRE : 1;
+ __IO uint16_t URIRE : 1;
+ __IO uint16_t RWKIRE : 1;
+ __IO uint16_t RETRY : 1;
+ __IO uint16_t CANCEL : 1;
+ __IO uint16_t SOFSTEP : 1;
+} stc_usb_hcnt_field_t;
+
+typedef struct stc_usb_hcnt0_field
+{
+ __IO uint8_t HOST : 1;
+ __IO uint8_t URST : 1;
+ __IO uint8_t SOFIRE : 1;
+ __IO uint8_t DIRE : 1;
+ __IO uint8_t CNNIRE : 1;
+ __IO uint8_t CMPIRE : 1;
+ __IO uint8_t URIRE : 1;
+ __IO uint8_t RWKIRE : 1;
+} stc_usb_hcnt0_field_t;
+
+typedef struct stc_usb_hcnt1_field
+{
+ __IO uint8_t RETRY : 1;
+ __IO uint8_t CANCEL : 1;
+ __IO uint8_t SOFSTEP : 1;
+} stc_usb_hcnt1_field_t;
+
+typedef struct stc_usb_hirq_field
+{
+ __IO uint8_t SOFIRQ : 1;
+ __IO uint8_t DIRQ : 1;
+ __IO uint8_t CNNIRQ : 1;
+ __IO uint8_t CMPIRQ : 1;
+ __IO uint8_t URIRQ : 1;
+ __IO uint8_t RWKIRQ : 1;
+ uint8_t RESERVED1 : 1;
+ __IO uint8_t TCAN : 1;
+} stc_usb_hirq_field_t;
+
+typedef struct stc_usb_herr_field
+{
+ __IO uint8_t HS0 : 1;
+ __IO uint8_t HS1 : 1;
+ __IO uint8_t STUFF : 1;
+ __IO uint8_t TGERR : 1;
+ __IO uint8_t CRC : 1;
+ __IO uint8_t TOUT : 1;
+ __IO uint8_t RERR : 1;
+ __IO uint8_t LSTOF : 1;
+} stc_usb_herr_field_t;
+
+typedef struct stc_usb_hstate_field
+{
+ __IO uint8_t CSTAT : 1;
+ __IO uint8_t TMODE : 1;
+ __IO uint8_t SUSP : 1;
+ __IO uint8_t SOFBUSY : 1;
+ __IO uint8_t CLKSEL : 1;
+ __IO uint8_t ALIVE : 1;
+} stc_usb_hstate_field_t;
+
+typedef struct stc_usb_hfcomp_field
+{
+ __IO uint8_t FRAMECOMP0 : 1;
+ __IO uint8_t FRAMECOMP1 : 1;
+ __IO uint8_t FRAMECOMP2 : 1;
+ __IO uint8_t FRAMECOMP3 : 1;
+ __IO uint8_t FRAMECOMP4 : 1;
+ __IO uint8_t FRAMECOMP5 : 1;
+ __IO uint8_t FRAMECOMP6 : 1;
+ __IO uint8_t FRAMECOMP7 : 1;
+} stc_usb_hfcomp_field_t;
+
+typedef struct stc_usb_hrtimer_field
+{
+ __IO uint16_t RTIMER0 : 1;
+ __IO uint16_t RTIMER1 : 1;
+ __IO uint16_t RTIMER2 : 1;
+ __IO uint16_t RTIMER3 : 1;
+ __IO uint16_t RTIMER4 : 1;
+ __IO uint16_t RTIMER5 : 1;
+ __IO uint16_t RTIMER6 : 1;
+ __IO uint16_t RTIMER7 : 1;
+ __IO uint16_t RTIMER8 : 1;
+ __IO uint16_t RTIMER9 : 1;
+ __IO uint16_t RTIMER10 : 1;
+ __IO uint16_t RTIMER11 : 1;
+ __IO uint16_t RTIMER12 : 1;
+ __IO uint16_t RTIMER13 : 1;
+ __IO uint16_t RTIMER14 : 1;
+ __IO uint16_t RTIMER15 : 1;
+} stc_usb_hrtimer_field_t;
+
+typedef struct stc_usb_hrtimer0_field
+{
+ __IO uint8_t RTIMER00 : 1;
+ __IO uint8_t RTIMER01 : 1;
+ __IO uint8_t RTIMER02 : 1;
+ __IO uint8_t RTIMER03 : 1;
+ __IO uint8_t RTIMER04 : 1;
+ __IO uint8_t RTIMER05 : 1;
+ __IO uint8_t RTIMER06 : 1;
+ __IO uint8_t RTIMER07 : 1;
+} stc_usb_hrtimer0_field_t;
+
+typedef struct stc_usb_hrtimer1_field
+{
+ __IO uint8_t RTIMER10 : 1;
+ __IO uint8_t RTIMER11 : 1;
+ __IO uint8_t RTIMER12 : 1;
+ __IO uint8_t RTIMER13 : 1;
+ __IO uint8_t RTIMER14 : 1;
+ __IO uint8_t RTIMER15 : 1;
+ __IO uint8_t RTIMER16 : 1;
+ __IO uint8_t RTIMER17 : 1;
+} stc_usb_hrtimer1_field_t;
+
+typedef struct stc_usb_hrtimer2_field
+{
+ __IO uint8_t RTIMER20 : 1;
+ __IO uint8_t RTIMER21 : 1;
+ __IO uint8_t RTIMER22 : 1;
+} stc_usb_hrtimer2_field_t;
+
+typedef struct stc_usb_hadr_field
+{
+ __IO uint8_t ADDRESS0 : 1;
+ __IO uint8_t ADDRESS1 : 1;
+ __IO uint8_t ADDRESS2 : 1;
+ __IO uint8_t ADDRESS3 : 1;
+ __IO uint8_t ADDRESS4 : 1;
+ __IO uint8_t ADDRESS5 : 1;
+ __IO uint8_t ADDRESS6 : 1;
+} stc_usb_hadr_field_t;
+
+typedef struct stc_usb_heof_field
+{
+ __IO uint16_t EOF0 : 1;
+ __IO uint16_t EOF1 : 1;
+ __IO uint16_t EOF2 : 1;
+ __IO uint16_t EOF3 : 1;
+ __IO uint16_t EOF4 : 1;
+ __IO uint16_t EOF5 : 1;
+ __IO uint16_t EOF6 : 1;
+ __IO uint16_t EOF7 : 1;
+ __IO uint16_t EOF8 : 1;
+ __IO uint16_t EOF9 : 1;
+ __IO uint16_t EOF10 : 1;
+ __IO uint16_t EOF11 : 1;
+ __IO uint16_t EOF12 : 1;
+ __IO uint16_t EOF13 : 1;
+ __IO uint16_t EOF14 : 1;
+ __IO uint16_t EOF15 : 1;
+} stc_usb_heof_field_t;
+
+typedef struct stc_usb_heof0_field
+{
+ __IO uint8_t EOF00 : 1;
+ __IO uint8_t EOF01 : 1;
+ __IO uint8_t EOF02 : 1;
+ __IO uint8_t EOF03 : 1;
+ __IO uint8_t EOF04 : 1;
+ __IO uint8_t EOF05 : 1;
+ __IO uint8_t EOF06 : 1;
+ __IO uint8_t EOF07 : 1;
+} stc_usb_heof0_field_t;
+
+typedef struct stc_usb_heof1_field
+{
+ __IO uint8_t EOF10 : 1;
+ __IO uint8_t EOF11 : 1;
+ __IO uint8_t EOF12 : 1;
+ __IO uint8_t EOF13 : 1;
+ __IO uint8_t EOF14 : 1;
+ __IO uint8_t EOF15 : 1;
+} stc_usb_heof1_field_t;
+
+typedef struct stc_usb_hframe_field
+{
+ __IO uint16_t FRAME0 : 1;
+ __IO uint16_t FRAME1 : 1;
+ __IO uint16_t FRAME2 : 1;
+ __IO uint16_t FRAME3 : 1;
+ __IO uint16_t FRAME4 : 1;
+ __IO uint16_t FRAME5 : 1;
+ __IO uint16_t FRAME6 : 1;
+ __IO uint16_t FRAME7 : 1;
+ __IO uint16_t FRAME8 : 1;
+ __IO uint16_t FRAME9 : 1;
+ __IO uint16_t FRAME10 : 1;
+} stc_usb_hframe_field_t;
+
+typedef struct stc_usb_hframe0_field
+{
+ __IO uint8_t FRAME00 : 1;
+ __IO uint8_t FRAME01 : 1;
+ __IO uint8_t FRAME02 : 1;
+ __IO uint8_t FRAME03 : 1;
+ __IO uint8_t FRAME04 : 1;
+ __IO uint8_t FRAME05 : 1;
+ __IO uint8_t FRAME06 : 1;
+ __IO uint8_t FRAME07 : 1;
+} stc_usb_hframe0_field_t;
+
+typedef struct stc_usb_hframe1_field
+{
+ __IO uint8_t FRAME10 : 1;
+ __IO uint8_t FRAME11 : 1;
+ __IO uint8_t FRAME12 : 1;
+ __IO uint8_t FRAME13 : 1;
+} stc_usb_hframe1_field_t;
+
+typedef struct stc_usb_htoken_field
+{
+ __IO uint8_t ENDPT0 : 1;
+ __IO uint8_t ENDPT1 : 1;
+ __IO uint8_t ENDPT2 : 1;
+ __IO uint8_t ENDPT3 : 1;
+ __IO uint8_t TKNEN0 : 1;
+ __IO uint8_t TKNEN1 : 1;
+ __IO uint8_t TKNEN2 : 1;
+ __IO uint8_t TGGL : 1;
+} stc_usb_htoken_field_t;
+
+typedef struct stc_usb_udcc_field
+{
+ __IO uint16_t PWC : 1;
+ __IO uint16_t RFBK : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t STALCLREN : 1;
+ __IO uint16_t USTP : 1;
+ __IO uint16_t HCONX : 1;
+ __IO uint16_t RESUM : 1;
+ __IO uint16_t RST : 1;
+} stc_usb_udcc_field_t;
+
+typedef struct stc_usb_ep0c_field
+{
+ __IO uint16_t PKS00 : 1;
+ __IO uint16_t PKS01 : 1;
+ __IO uint16_t PKS02 : 1;
+ __IO uint16_t PKS03 : 1;
+ __IO uint16_t PKS04 : 1;
+ __IO uint16_t PKS05 : 1;
+ __IO uint16_t PKS06 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t STAL : 1;
+} stc_usb_ep0c_field_t;
+
+typedef struct stc_usb_ep1c_field
+{
+ __IO uint16_t PKS10 : 1;
+ __IO uint16_t PKS11 : 1;
+ __IO uint16_t PKS12 : 1;
+ __IO uint16_t PKS13 : 1;
+ __IO uint16_t PKS14 : 1;
+ __IO uint16_t PKS15 : 1;
+ __IO uint16_t PKS16 : 1;
+ __IO uint16_t PKS17 : 1;
+ __IO uint16_t PKS18 : 1;
+ __IO uint16_t STAL : 1;
+ __IO uint16_t NULE : 1;
+ __IO uint16_t DMAE : 1;
+ __IO uint16_t DIR : 1;
+ __IO uint16_t TYPE0 : 1;
+ __IO uint16_t TYPE1 : 1;
+ __IO uint16_t EPEN : 1;
+} stc_usb_ep1c_field_t;
+
+typedef struct stc_usb_ep2c_field
+{
+ __IO uint16_t PKS20 : 1;
+ __IO uint16_t PKS21 : 1;
+ __IO uint16_t PKS22 : 1;
+ __IO uint16_t PKS23 : 1;
+ __IO uint16_t PKS24 : 1;
+ __IO uint16_t PKS25 : 1;
+ __IO uint16_t PKS26 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t STAL : 1;
+ __IO uint16_t NULE : 1;
+ __IO uint16_t DMAE : 1;
+ __IO uint16_t DIR : 1;
+ __IO uint16_t TYPE0 : 1;
+ __IO uint16_t TYPE1 : 1;
+ __IO uint16_t EPEN : 1;
+} stc_usb_ep2c_field_t;
+
+typedef struct stc_usb_ep3c_field
+{
+ __IO uint16_t PKS30 : 1;
+ __IO uint16_t PKS31 : 1;
+ __IO uint16_t PKS32 : 1;
+ __IO uint16_t PKS33 : 1;
+ __IO uint16_t PKS34 : 1;
+ __IO uint16_t PKS35 : 1;
+ __IO uint16_t PKS36 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t STAL : 1;
+ __IO uint16_t NULE : 1;
+ __IO uint16_t DMAE : 1;
+ __IO uint16_t DIR : 1;
+ __IO uint16_t TYPE0 : 1;
+ __IO uint16_t TYPE1 : 1;
+ __IO uint16_t EPEN : 1;
+} stc_usb_ep3c_field_t;
+
+typedef struct stc_usb_ep4c_field
+{
+ __IO uint16_t PKS40 : 1;
+ __IO uint16_t PKS41 : 1;
+ __IO uint16_t PKS42 : 1;
+ __IO uint16_t PKS43 : 1;
+ __IO uint16_t PKS44 : 1;
+ __IO uint16_t PKS45 : 1;
+ __IO uint16_t PKS46 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t STAL : 1;
+ __IO uint16_t NULE : 1;
+ __IO uint16_t DMAE : 1;
+ __IO uint16_t DIR : 1;
+ __IO uint16_t TYPE0 : 1;
+ __IO uint16_t TYPE1 : 1;
+ __IO uint16_t EPEN : 1;
+} stc_usb_ep4c_field_t;
+
+typedef struct stc_usb_ep5c_field
+{
+ __IO uint16_t PKS50 : 1;
+ __IO uint16_t PKS51 : 1;
+ __IO uint16_t PKS52 : 1;
+ __IO uint16_t PKS53 : 1;
+ __IO uint16_t PKS54 : 1;
+ __IO uint16_t PKS55 : 1;
+ __IO uint16_t PKS56 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t STAL : 1;
+ __IO uint16_t NULE : 1;
+ __IO uint16_t DMAE : 1;
+ __IO uint16_t DIR : 1;
+ __IO uint16_t TYPE0 : 1;
+ __IO uint16_t TYPE1 : 1;
+ __IO uint16_t EPEN : 1;
+} stc_usb_ep5c_field_t;
+
+typedef struct stc_usb_tmsp_field
+{
+ __IO uint16_t TMSP0 : 1;
+ __IO uint16_t TMSP1 : 1;
+ __IO uint16_t TMSP2 : 1;
+ __IO uint16_t TMSP3 : 1;
+ __IO uint16_t TMSP4 : 1;
+ __IO uint16_t TMSP5 : 1;
+ __IO uint16_t TMSP6 : 1;
+ __IO uint16_t TMSP7 : 1;
+ __IO uint16_t TMSP8 : 1;
+ __IO uint16_t TMSP9 : 1;
+ __IO uint16_t TMSP10 : 1;
+} stc_usb_tmsp_field_t;
+
+typedef struct stc_usb_udcs_field
+{
+ __IO uint8_t CONF : 1;
+ __IO uint8_t SETP : 1;
+ __IO uint8_t WKUP : 1;
+ __IO uint8_t BRST : 1;
+ __IO uint8_t SOF : 1;
+ __IO uint8_t SUSP : 1;
+} stc_usb_udcs_field_t;
+
+typedef struct stc_usb_udcie_field
+{
+ __IO uint8_t CONFIE : 1;
+ __IO uint8_t CONFN : 1;
+ __IO uint8_t WKUPIE : 1;
+ __IO uint8_t BRSTIE : 1;
+ __IO uint8_t SOFIE : 1;
+ __IO uint8_t SUSPIE : 1;
+} stc_usb_udcie_field_t;
+
+typedef struct stc_usb_ep0is_field
+{
+ uint16_t RESERVED1 : 10;
+ __IO uint16_t DRQI : 1;
+ uint16_t RESERVED2 : 3;
+ __IO uint16_t DRQIIE : 1;
+ __IO uint16_t BFINI : 1;
+} stc_usb_ep0is_field_t;
+
+typedef struct stc_usb_ep0os_field
+{
+ __IO uint16_t SIZE0 : 1;
+ __IO uint16_t SIZE1 : 1;
+ __IO uint16_t SIZE2 : 1;
+ __IO uint16_t SIZE3 : 1;
+ __IO uint16_t SIZE4 : 1;
+ __IO uint16_t SIZE5 : 1;
+ __IO uint16_t SIZE6 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t SPK : 1;
+ __IO uint16_t DRQO : 1;
+ uint16_t RESERVED2 : 2;
+ __IO uint16_t SPKIE : 1;
+ __IO uint16_t DRQOIE : 1;
+ __IO uint16_t BFINI : 1;
+} stc_usb_ep0os_field_t;
+
+typedef struct stc_usb_ep1s_field
+{
+ __IO uint16_t SIZE10 : 1;
+ __IO uint16_t SIZE11 : 1;
+ __IO uint16_t SIZE12 : 1;
+ __IO uint16_t SIZE13 : 1;
+ __IO uint16_t SIZE14 : 1;
+ __IO uint16_t SIZE15 : 1;
+ __IO uint16_t SIZE16 : 1;
+ __IO uint16_t SIZE17 : 1;
+ __IO uint16_t SIZE18 : 1;
+ __IO uint16_t SPK : 1;
+ __IO uint16_t DRQ : 1;
+ __IO uint16_t BUSY : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t SPKIE : 1;
+ __IO uint16_t DRQIE : 1;
+ __IO uint16_t BFINI : 1;
+} stc_usb_ep1s_field_t;
+
+typedef struct stc_usb_ep2s_field
+{
+ __IO uint16_t SIZE20 : 1;
+ __IO uint16_t SIZE21 : 1;
+ __IO uint16_t SIZE22 : 1;
+ __IO uint16_t SIZE23 : 1;
+ __IO uint16_t SIZE24 : 1;
+ __IO uint16_t SIZE25 : 1;
+ __IO uint16_t SIZE26 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t SPK : 1;
+ __IO uint16_t DRQ : 1;
+ __IO uint16_t BUSY : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t SPKIE : 1;
+ __IO uint16_t DRQIE : 1;
+ __IO uint16_t BFINI : 1;
+} stc_usb_ep2s_field_t;
+
+typedef struct stc_usb_ep4s_field
+{
+ __IO uint16_t SIZE40 : 1;
+ __IO uint16_t SIZE41 : 1;
+ __IO uint16_t SIZE42 : 1;
+ __IO uint16_t SIZE43 : 1;
+ __IO uint16_t SIZE44 : 1;
+ __IO uint16_t SIZE45 : 1;
+ __IO uint16_t SIZE46 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t SPK : 1;
+ __IO uint16_t DRQ : 1;
+ __IO uint16_t BUSY : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t SPKIE : 1;
+ __IO uint16_t DRQIE : 1;
+ __IO uint16_t BFINI : 1;
+} stc_usb_ep4s_field_t;
+
+typedef struct stc_usb_ep5s_field
+{
+ __IO uint16_t SIZE50 : 1;
+ __IO uint16_t SIZE51 : 1;
+ __IO uint16_t SIZE52 : 1;
+ __IO uint16_t SIZE53 : 1;
+ __IO uint16_t SIZE54 : 1;
+ __IO uint16_t SIZE55 : 1;
+ __IO uint16_t SIZE56 : 1;
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t SPK : 1;
+ __IO uint16_t DRQ : 1;
+ __IO uint16_t BUSY : 1;
+ uint16_t RESERVED2 : 1;
+ __IO uint16_t SPKIE : 1;
+ __IO uint16_t DRQIE : 1;
+ __IO uint16_t BFINI : 1;
+} stc_usb_ep5s_field_t;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMAC_MODULE register bit fields */
+typedef struct stc_dmac_dmacr_field
+{
+ uint32_t RESERVED1 : 24;
+ __IO uint32_t DH0 : 1;
+ __IO uint32_t DH1 : 1;
+ __IO uint32_t DH2 : 1;
+ __IO uint32_t DH3 : 1;
+ __IO uint32_t PR : 1;
+ uint32_t RESERVED2 : 1;
+ __IO uint32_t DS : 1;
+ __IO uint32_t DE : 1;
+} stc_dmac_dmacr_field_t;
+
+typedef struct stc_dmac_dmaca0_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca0_field_t;
+
+typedef struct stc_dmac_dmacb0_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb0_field_t;
+
+typedef struct stc_dmac_dmaca1_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca1_field_t;
+
+typedef struct stc_dmac_dmacb1_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb1_field_t;
+
+typedef struct stc_dmac_dmaca2_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca2_field_t;
+
+typedef struct stc_dmac_dmacb2_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb2_field_t;
+
+typedef struct stc_dmac_dmaca3_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca3_field_t;
+
+typedef struct stc_dmac_dmacb3_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb3_field_t;
+
+typedef struct stc_dmac_dmaca4_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca4_field_t;
+
+typedef struct stc_dmac_dmacb4_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb4_field_t;
+
+typedef struct stc_dmac_dmaca5_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca5_field_t;
+
+typedef struct stc_dmac_dmacb5_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb5_field_t;
+
+typedef struct stc_dmac_dmaca6_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca6_field_t;
+
+typedef struct stc_dmac_dmacb6_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb6_field_t;
+
+typedef struct stc_dmac_dmaca7_field
+{
+ __IO uint32_t TC0 : 1;
+ __IO uint32_t TC1 : 1;
+ __IO uint32_t TC2 : 1;
+ __IO uint32_t TC3 : 1;
+ __IO uint32_t TC4 : 1;
+ __IO uint32_t TC5 : 1;
+ __IO uint32_t TC6 : 1;
+ __IO uint32_t TC7 : 1;
+ __IO uint32_t TC8 : 1;
+ __IO uint32_t TC9 : 1;
+ __IO uint32_t TC10 : 1;
+ __IO uint32_t TC11 : 1;
+ __IO uint32_t TC12 : 1;
+ __IO uint32_t TC13 : 1;
+ __IO uint32_t TC14 : 1;
+ __IO uint32_t TC15 : 1;
+ __IO uint32_t BC0 : 1;
+ __IO uint32_t BC1 : 1;
+ __IO uint32_t BC2 : 1;
+ __IO uint32_t BC3 : 1;
+ uint32_t RESERVED1 : 3;
+ __IO uint32_t IS0 : 1;
+ __IO uint32_t IS1 : 1;
+ __IO uint32_t IS2 : 1;
+ __IO uint32_t IS3 : 1;
+ __IO uint32_t IS4 : 1;
+ __IO uint32_t IS5 : 1;
+ __IO uint32_t ST : 1;
+ __IO uint32_t PB : 1;
+ __IO uint32_t EB : 1;
+} stc_dmac_dmaca7_field_t;
+
+typedef struct stc_dmac_dmacb7_field
+{
+ __IO uint32_t EM : 1;
+ uint32_t RESERVED1 : 15;
+ __IO uint32_t SS0 : 1;
+ __IO uint32_t SS1 : 1;
+ __IO uint32_t SS2 : 1;
+ __IO uint32_t CI : 1;
+ __IO uint32_t EI : 1;
+ __IO uint32_t RD : 1;
+ __IO uint32_t RS : 1;
+ __IO uint32_t RC : 1;
+ __IO uint32_t FD : 1;
+ __IO uint32_t FS : 1;
+ __IO uint32_t TW0 : 1;
+ __IO uint32_t TW1 : 1;
+ __IO uint32_t MS0 : 1;
+ __IO uint32_t MS1 : 1;
+} stc_dmac_dmacb7_field_t;
+
+/******************************************************************************
+ * CAN_MODULE
+ ******************************************************************************/
+/* CAN_MODULE register bit fields */
+typedef struct stc_can_ctrlr_field
+{
+ __IO uint16_t INIT : 1;
+ __IO uint16_t IE : 1;
+ __IO uint16_t SIE : 1;
+ __IO uint16_t EIE : 1;
+ uint16_t RESERVED1 : 1;
+ __IO uint16_t DAR : 1;
+ __IO uint16_t CCE : 1;
+ __IO uint16_t TEST : 1;
+} stc_can_ctrlr_field_t;
+
+typedef struct stc_can_statr_field
+{
+ __IO uint16_t LEC0 : 1;
+ __IO uint16_t LEC1 : 1;
+ __IO uint16_t LEC2 : 1;
+ __IO uint16_t TXOK : 1;
+ __IO uint16_t RXOK : 1;
+ __IO uint16_t EPASS : 1;
+ __IO uint16_t EWARM : 1;
+ __IO uint16_t BOFF : 1;
+} stc_can_statr_field_t;
+
+typedef struct stc_can_errcnt_field
+{
+ __IO uint16_t TEC0 : 1;
+ __IO uint16_t TEC1 : 1;
+ __IO uint16_t TEC2 : 1;
+ __IO uint16_t TEC3 : 1;
+ __IO uint16_t TEC4 : 1;
+ __IO uint16_t TEC5 : 1;
+ __IO uint16_t TEC6 : 1;
+ __IO uint16_t TEC7 : 1;
+ __IO uint16_t REC0 : 1;
+ __IO uint16_t REC1 : 1;
+ __IO uint16_t REC2 : 1;
+ __IO uint16_t REC3 : 1;
+ __IO uint16_t REC4 : 1;
+ __IO uint16_t REC5 : 1;
+ __IO uint16_t REC6 : 1;
+ __IO uint16_t RP : 1;
+} stc_can_errcnt_field_t;
+
+typedef struct stc_can_btr_field
+{
+ __IO uint16_t BRP0 : 1;
+ __IO uint16_t BRP1 : 1;
+ __IO uint16_t BRP2 : 1;
+ __IO uint16_t BRP3 : 1;
+ __IO uint16_t BRP4 : 1;
+ __IO uint16_t BRP5 : 1;
+ __IO uint16_t SJW0 : 1;
+ __IO uint16_t SJW1 : 1;
+ __IO uint16_t TSEG10 : 1;
+ __IO uint16_t TSEG11 : 1;
+ __IO uint16_t TSEG12 : 1;
+ __IO uint16_t TSEG13 : 1;
+ __IO uint16_t TSEG20 : 1;
+ __IO uint16_t TSEG21 : 1;
+ __IO uint16_t TSEG22 : 1;
+} stc_can_btr_field_t;
+
+typedef struct stc_can_intr_field
+{
+ __IO uint16_t INTID0 : 1;
+ __IO uint16_t INTID1 : 1;
+ __IO uint16_t INTID2 : 1;
+ __IO uint16_t INTID3 : 1;
+ __IO uint16_t INTID4 : 1;
+ __IO uint16_t INTID5 : 1;
+ __IO uint16_t INTID6 : 1;
+ __IO uint16_t INTID7 : 1;
+ __IO uint16_t INTID8 : 1;
+ __IO uint16_t INTID9 : 1;
+ __IO uint16_t INTID10 : 1;
+ __IO uint16_t INTID11 : 1;
+ __IO uint16_t INTID12 : 1;
+ __IO uint16_t INTID13 : 1;
+ __IO uint16_t INTID14 : 1;
+ __IO uint16_t INTID15 : 1;
+} stc_can_intr_field_t;
+
+typedef struct stc_can_testr_field
+{
+ uint16_t RESERVED1 : 2;
+ __IO uint16_t BASIC : 1;
+ __IO uint16_t SILENT : 1;
+ __IO uint16_t LBACK : 1;
+ __IO uint16_t TX0 : 1;
+ __IO uint16_t TX1 : 1;
+ __IO uint16_t RX : 1;
+} stc_can_testr_field_t;
+
+typedef struct stc_can_brper_field
+{
+ __IO uint16_t BRPE0 : 1;
+ __IO uint16_t BRPE1 : 1;
+ __IO uint16_t BRPE2 : 1;
+ __IO uint16_t BRPE3 : 1;
+} stc_can_brper_field_t;
+
+typedef struct stc_can_if1creq_field
+{
+ uint16_t RESERVED1 : 15;
+ __IO uint16_t BUSY : 1;
+} stc_can_if1creq_field_t;
+
+typedef struct stc_can_if1cmsk_field
+{
+ __IO uint16_t DATAB : 1;
+ __IO uint16_t DATAA : 1;
+ __IO uint16_t NEWDAT : 1;
+ __IO uint16_t CIP : 1;
+ __IO uint16_t CONTROL : 1;
+ __IO uint16_t ARB : 1;
+ __IO uint16_t MASK : 1;
+ __IO uint16_t WRRD : 1;
+} stc_can_if1cmsk_field_t;
+
+typedef struct stc_can_if1msk_field
+{
+ uint32_t RESERVED1 : 30;
+ __IO uint32_t MDIR : 1;
+ __IO uint32_t MXTD : 1;
+} stc_can_if1msk_field_t;
+
+typedef struct stc_can_if1msk2_field
+{
+ uint16_t RESERVED1 : 14;
+ __IO uint16_t MDIR : 1;
+ __IO uint16_t MXTD : 1;
+} stc_can_if1msk2_field_t;
+
+typedef struct stc_can_if1arb_field
+{
+ uint32_t RESERVED1 : 29;
+ __IO uint32_t DIR : 1;
+ __IO uint32_t XTD : 1;
+ __IO uint32_t MSGVAL : 1;
+} stc_can_if1arb_field_t;
+
+typedef struct stc_can_if1arb2_field
+{
+ uint16_t RESERVED1 : 13;
+ __IO uint16_t DIR : 1;
+ __IO uint16_t XTD : 1;
+ __IO uint16_t MSGVAL : 1;
+} stc_can_if1arb2_field_t;
+
+typedef struct stc_can_if1mctr_field
+{
+ __IO uint16_t DLC0 : 1;
+ __IO uint16_t DLC1 : 1;
+ __IO uint16_t DLC2 : 1;
+ __IO uint16_t DLC3 : 1;
+ uint16_t RESERVED1 : 3;
+ __IO uint16_t EOB : 1;
+ __IO uint16_t TXRQST : 1;
+ __IO uint16_t RMTEN : 1;
+ __IO uint16_t RXIE : 1;
+ __IO uint16_t TXIE : 1;
+ __IO uint16_t UMASK : 1;
+ __IO uint16_t INTPND : 1;
+ __IO uint16_t MSGLST : 1;
+ __IO uint16_t NEWDAT : 1;
+} stc_can_if1mctr_field_t;
+
+typedef struct stc_can_if2creq_field
+{
+ uint16_t RESERVED1 : 15;
+ __IO uint16_t BUSY : 1;
+} stc_can_if2creq_field_t;
+
+typedef struct stc_can_if2cmsk_field
+{
+ __IO uint16_t DATAB : 1;
+ __IO uint16_t DATAA : 1;
+ __IO uint16_t NEWDAT : 1;
+ __IO uint16_t CIP : 1;
+ __IO uint16_t CONTROL : 1;
+ __IO uint16_t ARB : 1;
+ __IO uint16_t MASK : 1;
+ __IO uint16_t WRRD : 1;
+} stc_can_if2cmsk_field_t;
+
+typedef struct stc_can_if2msk_field
+{
+ uint32_t RESERVED1 : 30;
+ __IO uint32_t MDIR : 1;
+ __IO uint32_t MXTD : 1;
+} stc_can_if2msk_field_t;
+
+typedef struct stc_can_if2msk2_field
+{
+ uint16_t RESERVED1 : 14;
+ __IO uint16_t MDIR : 1;
+ __IO uint16_t MXTD : 1;
+} stc_can_if2msk2_field_t;
+
+typedef struct stc_can_if2arb2_field
+{
+ uint16_t RESERVED1 : 13;
+ __IO uint16_t DIR : 1;
+ __IO uint16_t XTD : 1;
+ __IO uint16_t MSGVAL : 1;
+} stc_can_if2arb2_field_t;
+
+typedef struct stc_can_if2mctr_field
+{
+ __IO uint16_t DLC0 : 1;
+ __IO uint16_t DLC1 : 1;
+ __IO uint16_t DLC2 : 1;
+ __IO uint16_t DLC3 : 1;
+ uint16_t RESERVED1 : 3;
+ __IO uint16_t EOB : 1;
+ __IO uint16_t TXRQST : 1;
+ __IO uint16_t RMTEN : 1;
+ __IO uint16_t RXIE : 1;
+ __IO uint16_t TXIE : 1;
+ __IO uint16_t UMASK : 1;
+ __IO uint16_t INTPND : 1;
+ __IO uint16_t MSGLST : 1;
+ __IO uint16_t NEWDAT : 1;
+} stc_can_if2mctr_field_t;
+
+typedef struct stc_can_treqr_field
+{
+ __IO uint32_t TXRQST1 : 1;
+ __IO uint32_t TXRQST2 : 1;
+ __IO uint32_t TXRQST3 : 1;
+ __IO uint32_t TXRQST4 : 1;
+ __IO uint32_t TXRQST5 : 1;
+ __IO uint32_t TXRQST6 : 1;
+ __IO uint32_t TXRQST7 : 1;
+ __IO uint32_t TXRQST8 : 1;
+ __IO uint32_t TXRQST9 : 1;
+ __IO uint32_t TXRQST10 : 1;
+ __IO uint32_t TXRQST11 : 1;
+ __IO uint32_t TXRQST12 : 1;
+ __IO uint32_t TXRQST13 : 1;
+ __IO uint32_t TXRQST14 : 1;
+ __IO uint32_t TXRQST15 : 1;
+ __IO uint32_t TXRQST16 : 1;
+ __IO uint32_t TXRQST17 : 1;
+ __IO uint32_t TXRQST18 : 1;
+ __IO uint32_t TXRQST19 : 1;
+ __IO uint32_t TXRQST20 : 1;
+ __IO uint32_t TXRQST21 : 1;
+ __IO uint32_t TXRQST22 : 1;
+ __IO uint32_t TXRQST23 : 1;
+ __IO uint32_t TXRQST24 : 1;
+ __IO uint32_t TXRQST25 : 1;
+ __IO uint32_t TXRQST26 : 1;
+ __IO uint32_t TXRQST27 : 1;
+ __IO uint32_t TXRQST28 : 1;
+ __IO uint32_t TXRQST29 : 1;
+ __IO uint32_t TXRQST30 : 1;
+ __IO uint32_t TXRQST31 : 1;
+ __IO uint32_t TXRQST32 : 1;
+} stc_can_treqr_field_t;
+
+typedef struct stc_can_treqr1_field
+{
+ __IO uint16_t TXRQST1 : 1;
+ __IO uint16_t TXRQST2 : 1;
+ __IO uint16_t TXRQST3 : 1;
+ __IO uint16_t TXRQST4 : 1;
+ __IO uint16_t TXRQST5 : 1;
+ __IO uint16_t TXRQST6 : 1;
+ __IO uint16_t TXRQST7 : 1;
+ __IO uint16_t TXRQST8 : 1;
+ __IO uint16_t TXRQST9 : 1;
+ __IO uint16_t TXRQST10 : 1;
+ __IO uint16_t TXRQST11 : 1;
+ __IO uint16_t TXRQST12 : 1;
+ __IO uint16_t TXRQST13 : 1;
+ __IO uint16_t TXRQST14 : 1;
+ __IO uint16_t TXRQST15 : 1;
+ __IO uint16_t TXRQST16 : 1;
+} stc_can_treqr1_field_t;
+
+typedef struct stc_can_treqr2_field
+{
+ __IO uint16_t TXRQST17 : 1;
+ __IO uint16_t TXRQST18 : 1;
+ __IO uint16_t TXRQST19 : 1;
+ __IO uint16_t TXRQST20 : 1;
+ __IO uint16_t TXRQST21 : 1;
+ __IO uint16_t TXRQST22 : 1;
+ __IO uint16_t TXRQST23 : 1;
+ __IO uint16_t TXRQST24 : 1;
+ __IO uint16_t TXRQST25 : 1;
+ __IO uint16_t TXRQST26 : 1;
+ __IO uint16_t TXRQST27 : 1;
+ __IO uint16_t TXRQST28 : 1;
+ __IO uint16_t TXRQST29 : 1;
+ __IO uint16_t TXRQST30 : 1;
+ __IO uint16_t TXRQST31 : 1;
+ __IO uint16_t TXRQST32 : 1;
+} stc_can_treqr2_field_t;
+
+typedef struct stc_can_newdt_field
+{
+ __IO uint32_t NEWDAT1 : 1;
+ __IO uint32_t NEWDAT2 : 1;
+ __IO uint32_t NEWDAT3 : 1;
+ __IO uint32_t NEWDAT4 : 1;
+ __IO uint32_t NEWDAT5 : 1;
+ __IO uint32_t NEWDAT6 : 1;
+ __IO uint32_t NEWDAT7 : 1;
+ __IO uint32_t NEWDAT8 : 1;
+ __IO uint32_t NEWDAT9 : 1;
+ __IO uint32_t NEWDAT10 : 1;
+ __IO uint32_t NEWDAT11 : 1;
+ __IO uint32_t NEWDAT12 : 1;
+ __IO uint32_t NEWDAT13 : 1;
+ __IO uint32_t NEWDAT14 : 1;
+ __IO uint32_t NEWDAT15 : 1;
+ __IO uint32_t NEWDAT16 : 1;
+ __IO uint32_t NEWDAT17 : 1;
+ __IO uint32_t NEWDAT18 : 1;
+ __IO uint32_t NEWDAT19 : 1;
+ __IO uint32_t NEWDAT20 : 1;
+ __IO uint32_t NEWDAT21 : 1;
+ __IO uint32_t NEWDAT22 : 1;
+ __IO uint32_t NEWDAT23 : 1;
+ __IO uint32_t NEWDAT24 : 1;
+ __IO uint32_t NEWDAT25 : 1;
+ __IO uint32_t NEWDAT26 : 1;
+ __IO uint32_t NEWDAT27 : 1;
+ __IO uint32_t NEWDAT28 : 1;
+ __IO uint32_t NEWDAT29 : 1;
+ __IO uint32_t NEWDAT30 : 1;
+ __IO uint32_t NEWDAT31 : 1;
+ __IO uint32_t NEWDAT32 : 1;
+} stc_can_newdt_field_t;
+
+typedef struct stc_can_newdt1_field
+{
+ __IO uint16_t NEWDAT1 : 1;
+ __IO uint16_t NEWDAT2 : 1;
+ __IO uint16_t NEWDAT3 : 1;
+ __IO uint16_t NEWDAT4 : 1;
+ __IO uint16_t NEWDAT5 : 1;
+ __IO uint16_t NEWDAT6 : 1;
+ __IO uint16_t NEWDAT7 : 1;
+ __IO uint16_t NEWDAT8 : 1;
+ __IO uint16_t NEWDAT9 : 1;
+ __IO uint16_t NEWDAT10 : 1;
+ __IO uint16_t NEWDAT11 : 1;
+ __IO uint16_t NEWDAT12 : 1;
+ __IO uint16_t NEWDAT13 : 1;
+ __IO uint16_t NEWDAT14 : 1;
+ __IO uint16_t NEWDAT15 : 1;
+ __IO uint16_t NEWDAT16 : 1;
+} stc_can_newdt1_field_t;
+
+typedef struct stc_can_intpnd_field
+{
+ __IO uint32_t INTPND1 : 1;
+ __IO uint32_t INTPND2 : 1;
+ __IO uint32_t INTPND3 : 1;
+ __IO uint32_t INTPND4 : 1;
+ __IO uint32_t INTPND5 : 1;
+ __IO uint32_t INTPND6 : 1;
+ __IO uint32_t INTPND7 : 1;
+ __IO uint32_t INTPND8 : 1;
+ __IO uint32_t INTPND9 : 1;
+ __IO uint32_t INTPND10 : 1;
+ __IO uint32_t INTPND11 : 1;
+ __IO uint32_t INTPND12 : 1;
+ __IO uint32_t INTPND13 : 1;
+ __IO uint32_t INTPND14 : 1;
+ __IO uint32_t INTPND15 : 1;
+ __IO uint32_t INTPND16 : 1;
+ __IO uint32_t INTPND17 : 1;
+ __IO uint32_t INTPND18 : 1;
+ __IO uint32_t INTPND19 : 1;
+ __IO uint32_t INTPND20 : 1;
+ __IO uint32_t INTPND21 : 1;
+ __IO uint32_t INTPND22 : 1;
+ __IO uint32_t INTPND23 : 1;
+ __IO uint32_t INTPND24 : 1;
+ __IO uint32_t INTPND25 : 1;
+ __IO uint32_t INTPND26 : 1;
+ __IO uint32_t INTPND27 : 1;
+ __IO uint32_t INTPND28 : 1;
+ __IO uint32_t INTPND29 : 1;
+ __IO uint32_t INTPND30 : 1;
+ __IO uint32_t INTPND31 : 1;
+ __IO uint32_t INTPND32 : 1;
+} stc_can_intpnd_field_t;
+
+typedef struct stc_can_intpnd1_field
+{
+ __IO uint16_t INTPND1 : 1;
+ __IO uint16_t INTPND2 : 1;
+ __IO uint16_t INTPND3 : 1;
+ __IO uint16_t INTPND4 : 1;
+ __IO uint16_t INTPND5 : 1;
+ __IO uint16_t INTPND6 : 1;
+ __IO uint16_t INTPND7 : 1;
+ __IO uint16_t INTPND8 : 1;
+ __IO uint16_t INTPND9 : 1;
+ __IO uint16_t INTPND10 : 1;
+ __IO uint16_t INTPND11 : 1;
+ __IO uint16_t INTPND12 : 1;
+ __IO uint16_t INTPND13 : 1;
+ __IO uint16_t INTPND14 : 1;
+ __IO uint16_t INTPND15 : 1;
+ __IO uint16_t INTPND16 : 1;
+} stc_can_intpnd1_field_t;
+
+typedef struct stc_can_intpnd2_field
+{
+ __IO uint16_t INTPND17 : 1;
+ __IO uint16_t INTPND18 : 1;
+ __IO uint16_t INTPND19 : 1;
+ __IO uint16_t INTPND20 : 1;
+ __IO uint16_t INTPND21 : 1;
+ __IO uint16_t INTPND22 : 1;
+ __IO uint16_t INTPND23 : 1;
+ __IO uint16_t INTPND24 : 1;
+ __IO uint16_t INTPND25 : 1;
+ __IO uint16_t INTPND26 : 1;
+ __IO uint16_t INTPND27 : 1;
+ __IO uint16_t INTPND28 : 1;
+ __IO uint16_t INTPND29 : 1;
+ __IO uint16_t INTPND30 : 1;
+ __IO uint16_t INTPND31 : 1;
+ __IO uint16_t INTPND32 : 1;
+} stc_can_intpnd2_field_t;
+
+typedef struct stc_can_msgval_field
+{
+ __IO uint32_t MSGVAL1 : 1;
+ __IO uint32_t MSGVAL2 : 1;
+ __IO uint32_t MSGVAL3 : 1;
+ __IO uint32_t MSGVAL4 : 1;
+ __IO uint32_t MSGVAL5 : 1;
+ __IO uint32_t MSGVAL6 : 1;
+ __IO uint32_t MSGVAL7 : 1;
+ __IO uint32_t MSGVAL8 : 1;
+ __IO uint32_t MSGVAL9 : 1;
+ __IO uint32_t MSGVAL10 : 1;
+ __IO uint32_t MSGVAL11 : 1;
+ __IO uint32_t MSGVAL12 : 1;
+ __IO uint32_t MSGVAL13 : 1;
+ __IO uint32_t MSGVAL14 : 1;
+ __IO uint32_t MSGVAL15 : 1;
+ __IO uint32_t MSGVAL16 : 1;
+ __IO uint32_t MSGVAL17 : 1;
+ __IO uint32_t MSGVAL18 : 1;
+ __IO uint32_t MSGVAL19 : 1;
+ __IO uint32_t MSGVAL20 : 1;
+ __IO uint32_t MSGVAL21 : 1;
+ __IO uint32_t MSGVAL22 : 1;
+ __IO uint32_t MSGVAL23 : 1;
+ __IO uint32_t MSGVAL24 : 1;
+ __IO uint32_t MSGVAL25 : 1;
+ __IO uint32_t MSGVAL26 : 1;
+ __IO uint32_t MSGVAL27 : 1;
+ __IO uint32_t MSGVAL28 : 1;
+ __IO uint32_t MSGVAL29 : 1;
+ __IO uint32_t MSGVAL30 : 1;
+ __IO uint32_t MSGVAL31 : 1;
+ __IO uint32_t MSGVAL32 : 1;
+} stc_can_msgval_field_t;
+
+typedef struct stc_can_msgval1_field
+{
+ __IO uint16_t MSGVAL1 : 1;
+ __IO uint16_t MSGVAL2 : 1;
+ __IO uint16_t MSGVAL3 : 1;
+ __IO uint16_t MSGVAL4 : 1;
+ __IO uint16_t MSGVAL5 : 1;
+ __IO uint16_t MSGVAL6 : 1;
+ __IO uint16_t MSGVAL7 : 1;
+ __IO uint16_t MSGVAL8 : 1;
+ __IO uint16_t MSGVAL9 : 1;
+ __IO uint16_t MSGVAL10 : 1;
+ __IO uint16_t MSGVAL11 : 1;
+ __IO uint16_t MSGVAL12 : 1;
+ __IO uint16_t MSGVAL13 : 1;
+ __IO uint16_t MSGVAL14 : 1;
+ __IO uint16_t MSGVAL15 : 1;
+ __IO uint16_t MSGVAL16 : 1;
+} stc_can_msgval1_field_t;
+
+typedef struct stc_can_msgval2_field
+{
+ __IO uint16_t MSGVAL17 : 1;
+ __IO uint16_t MSGVAL18 : 1;
+ __IO uint16_t MSGVAL19 : 1;
+ __IO uint16_t MSGVAL20 : 1;
+ __IO uint16_t MSGVAL21 : 1;
+ __IO uint16_t MSGVAL22 : 1;
+ __IO uint16_t MSGVAL23 : 1;
+ __IO uint16_t MSGVAL24 : 1;
+ __IO uint16_t MSGVAL25 : 1;
+ __IO uint16_t MSGVAL26 : 1;
+ __IO uint16_t MSGVAL27 : 1;
+ __IO uint16_t MSGVAL28 : 1;
+ __IO uint16_t MSGVAL29 : 1;
+ __IO uint16_t MSGVAL30 : 1;
+ __IO uint16_t MSGVAL31 : 1;
+ __IO uint16_t MSGVAL32 : 1;
+} stc_can_msgval2_field_t;
+
+
+/******************************************************************************
+ * Peripheral register structures
+ ******************************************************************************/
+
+/******************************************************************************
* Flash_IF_MODULE
******************************************************************************/
/* Flash interface registers */
typedef struct
{
- __IO uint32_t FASZR;
- __IO uint32_t FRWTR;
- __IO uint32_t FSTR;
+ union {
+ __IO uint32_t FASZR;
+ stc_flash_if_faszr_field_t FASZR_f;
+ };
+ union {
+ __IO uint32_t FRWTR;
+ stc_flash_if_frwtr_field_t FRWTR_f;
+ };
+ union {
+ __IO uint32_t FSTR;
+ stc_flash_if_fstr_field_t FSTR_f;
+ };
uint8_t RESERVED0[4];
- __IO uint32_t FSYNDN;
+ union {
+ __IO uint32_t FSYNDN;
+ stc_flash_if_fsyndn_field_t FSYNDN_f;
+ };
uint8_t RESERVED1[236];
- __IO uint32_t CRTRMM;
-}FM3_FIF_TypeDef;
+ union {
+ __IO uint32_t CRTRMM;
+ stc_flash_if_crtrmm_field_t CRTRMM_f;
+ };
+}FM3_FLASH_IF_TypeDef;
/******************************************************************************
* Clock_Reset_MODULE
@@ -160,36 +6532,81 @@ typedef struct /* Clock and reset registers */
typedef struct
{
- __IO uint8_t SCM_CTL;
+ union {
+ __IO uint8_t SCM_CTL;
+ stc_crg_scm_ctl_field_t SCM_CTL_f;
+ };
uint8_t RESERVED0[3];
- __IO uint8_t SCM_STR;
+ union {
+ __IO uint8_t SCM_STR;
+ stc_crg_scm_str_field_t SCM_STR_f;
+ };
uint8_t RESERVED1[3];
__IO uint32_t STB_CTL;
- __IO uint16_t RST_STR;
+ union {
+ __IO uint16_t RST_STR;
+ stc_crg_rst_str_field_t RST_STR_f;
+ };
uint8_t RESERVED2[2];
- __IO uint8_t BSC_PSR;
+ union {
+ __IO uint8_t BSC_PSR;
+ stc_crg_bsc_psr_field_t BSC_PSR_f;
+ };
uint8_t RESERVED3[3];
- __IO uint8_t APBC0_PSR;
+ union {
+ __IO uint8_t APBC0_PSR;
+ stc_crg_apbc0_psr_field_t APBC0_PSR_f;
+ };
uint8_t RESERVED4[3];
- __IO uint8_t APBC1_PSR;
+ union {
+ __IO uint8_t APBC1_PSR;
+ stc_crg_apbc1_psr_field_t APBC1_PSR_f;
+ };
uint8_t RESERVED5[3];
- __IO uint8_t APBC2_PSR;
+ union {
+ __IO uint8_t APBC2_PSR;
+ stc_crg_apbc2_psr_field_t APBC2_PSR_f;
+ };
uint8_t RESERVED6[3];
- __IO uint8_t SWC_PSR;
+ union {
+ __IO uint8_t SWC_PSR;
+ stc_crg_swc_psr_field_t SWC_PSR_f;
+ };
uint8_t RESERVED7[7];
- __IO uint8_t TTC_PSR;
+ union {
+ __IO uint8_t TTC_PSR;
+ stc_crg_ttc_psr_field_t TTC_PSR_f;
+ };
uint8_t RESERVED8[7];
- __IO uint8_t CSW_TMR;
+ union {
+ __IO uint8_t CSW_TMR;
+ stc_crg_csw_tmr_field_t CSW_TMR_f;
+ };
uint8_t RESERVED9[3];
- __IO uint8_t PSW_TMR;
+ union {
+ __IO uint8_t PSW_TMR;
+ stc_crg_psw_tmr_field_t PSW_TMR_f;
+ };
uint8_t RESERVED10[3];
- __IO uint8_t PLL_CTL1;
+ union {
+ __IO uint8_t PLL_CTL1;
+ stc_crg_pll_ctl1_field_t PLL_CTL1_f;
+ };
uint8_t RESERVED11[3];
- __IO uint8_t PLL_CTL2;
+ union {
+ __IO uint8_t PLL_CTL2;
+ stc_crg_pll_ctl2_field_t PLL_CTL2_f;
+ };
uint8_t RESERVED12[3];
- __IO uint16_t CSV_CTL;
+ union {
+ __IO uint16_t CSV_CTL;
+ stc_crg_csv_ctl_field_t CSV_CTL_f;
+ };
uint8_t RESERVED13[2];
- __IO uint8_t CSV_STR;
+ union {
+ __IO uint8_t CSV_STR;
+ stc_crg_csv_str_field_t CSV_STR_f;
+ };
uint8_t RESERVED14[3];
__IO uint16_t FCSWH_CTL;
uint8_t RESERVED15[2];
@@ -197,13 +6614,25 @@ typedef struct uint8_t RESERVED16[2];
__IO uint16_t FCSWD_CTL;
uint8_t RESERVED17[2];
- __IO uint8_t DBWDT_CTL;
+ union {
+ __IO uint8_t DBWDT_CTL;
+ stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;
+ };
uint8_t RESERVED18[11];
- __IO uint8_t INT_ENR;
+ union {
+ __IO uint8_t INT_ENR;
+ stc_crg_int_enr_field_t INT_ENR_f;
+ };
uint8_t RESERVED19[3];
- __IO uint8_t INT_STR;
+ union {
+ __IO uint8_t INT_STR;
+ stc_crg_int_str_field_t INT_STR_f;
+ };
uint8_t RESERVED20[3];
- __IO uint8_t INT_CLR;
+ union {
+ __IO uint8_t INT_CLR;
+ stc_crg_int_clr_field_t INT_CLR_f;
+ };
}FM3_CRG_TypeDef;
/******************************************************************************
@@ -214,11 +6643,17 @@ typedef struct {
__IO uint32_t WDG_LDR;
__IO uint32_t WDG_VLR;
- __IO uint8_t WDG_CTL;
+ union {
+ __IO uint8_t WDG_CTL;
+ stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;
+ };
uint8_t RESERVED0[3];
__IO uint8_t WDG_ICL;
uint8_t RESERVED1[3];
- __IO uint8_t WDG_RIS;
+ union {
+ __IO uint8_t WDG_RIS;
+ stc_hwwdt_wdg_ris_field_t WDG_RIS_f;
+ };
uint8_t RESERVED2[3055];
__IO uint32_t WDG_LCK;
}FM3_HWWDT_TypeDef;
@@ -231,10 +6666,16 @@ typedef struct {
__IO uint32_t WDOGLOAD;
__IO uint32_t WDOGVALUE;
- __IO uint8_t WDOGCONTROL;
+ union {
+ __IO uint8_t WDOGCONTROL;
+ stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;
+ };
uint8_t RESERVED0[3];
__IO uint32_t WDOGINTCLR;
- __IO uint8_t WDOGRIS;
+ union {
+ __IO uint8_t WDOGRIS;
+ stc_swwdt_wdogris_field_t WDOGRIS_f;
+ };
uint8_t RESERVED1[3055];
__IO uint32_t WDOGLOCK;
}FM3_SWWDT_TypeDef;
@@ -247,18 +6688,36 @@ typedef struct {
__IO uint32_t TIMER1LOAD;
__IO uint32_t TIMER1VALUE;
- __IO uint32_t TIMER1CONTROL;
+ union {
+ __IO uint32_t TIMER1CONTROL;
+ stc_dtim_timer1control_field_t TIMER1CONTROL_f;
+ };
__IO uint32_t TIMER1INTCLR;
- __IO uint32_t TIMER1RIS;
- __IO uint32_t TIMER1MIS;
+ union {
+ __IO uint32_t TIMER1RIS;
+ stc_dtim_timer1ris_field_t TIMER1RIS_f;
+ };
+ union {
+ __IO uint32_t TIMER1MIS;
+ stc_dtim_timer1mis_field_t TIMER1MIS_f;
+ };
__IO uint32_t TIMER1BGLOAD;
uint8_t RESERVED0[4];
__IO uint32_t TIMER2LOAD;
__IO uint32_t TIMER2VALUE;
- __IO uint32_t TIMER2CONTROL;
+ union {
+ __IO uint32_t TIMER2CONTROL;
+ stc_dtim_timer2control_field_t TIMER2CONTROL_f;
+ };
__IO uint32_t TIMER2INTCLR;
- __IO uint32_t TIMER2RIS;
- __IO uint32_t TIMER2MIS;
+ union {
+ __IO uint32_t TIMER2RIS;
+ stc_dtim_timer2ris_field_t TIMER2RIS_f;
+ };
+ union {
+ __IO uint32_t TIMER2MIS;
+ stc_dtim_timer2mis_field_t TIMER2MIS_f;
+ };
__IO uint32_t TIMER2BGLOAD;
}FM3_DTIM_TypeDef;
@@ -273,25 +6732,43 @@ typedef struct uint8_t RESERVED1[2];
__IO uint16_t TCDT0;
uint8_t RESERVED2[2];
- __IO uint16_t TCSA0;
+ union {
+ __IO uint16_t TCSA0;
+ stc_mft_frt_tcsa0_field_t TCSA0_f;
+ };
uint8_t RESERVED3[2];
- __IO uint16_t TCSB0;
+ union {
+ __IO uint16_t TCSB0;
+ stc_mft_frt_tcsb0_field_t TCSB0_f;
+ };
uint8_t RESERVED4[2];
__IO uint16_t TCCP1;
uint8_t RESERVED5[2];
__IO uint16_t TCDT1;
uint8_t RESERVED6[2];
- __IO uint16_t TCSA1;
+ union {
+ __IO uint16_t TCSA1;
+ stc_mft_frt_tcsa1_field_t TCSA1_f;
+ };
uint8_t RESERVED7[2];
- __IO uint16_t TCSB1;
+ union {
+ __IO uint16_t TCSB1;
+ stc_mft_frt_tcsb1_field_t TCSB1_f;
+ };
uint8_t RESERVED8[2];
__IO uint16_t TCCP2;
uint8_t RESERVED9[2];
__IO uint16_t TCDT2;
uint8_t RESERVED10[2];
- __IO uint16_t TCSA2;
+ union {
+ __IO uint16_t TCSA2;
+ stc_mft_frt_tcsa2_field_t TCSA2_f;
+ };
uint8_t RESERVED11[2];
- __IO uint16_t TCSB2;
+ union {
+ __IO uint16_t TCSB2;
+ stc_mft_frt_tcsb2_field_t TCSB2_f;
+ };
}FM3_MFT_FRT_TypeDef;
/******************************************************************************
@@ -312,21 +6789,51 @@ typedef struct uint8_t RESERVED4[2];
__IO uint16_t OCCP5;
uint8_t RESERVED5[2];
- __IO uint8_t OCSA10;
- __IO uint8_t OCSB10;
+ union {
+ __IO uint8_t OCSA10;
+ stc_mft_ocu_ocsa10_field_t OCSA10_f;
+ };
+ union {
+ __IO uint8_t OCSB10;
+ stc_mft_ocu_ocsb10_field_t OCSB10_f;
+ };
uint8_t RESERVED6[2];
- __IO uint8_t OCSA32;
- __IO uint8_t OCSB32;
+ union {
+ __IO uint8_t OCSA32;
+ stc_mft_ocu_ocsa32_field_t OCSA32_f;
+ };
+ union {
+ __IO uint8_t OCSB32;
+ stc_mft_ocu_ocsb32_field_t OCSB32_f;
+ };
uint8_t RESERVED7[2];
- __IO uint8_t OCSA54;
- __IO uint8_t OCSB54;
+ union {
+ __IO uint8_t OCSA54;
+ stc_mft_ocu_ocsa54_field_t OCSA54_f;
+ };
+ union {
+ __IO uint8_t OCSB54;
+ stc_mft_ocu_ocsb54_field_t OCSB54_f;
+ };
uint8_t RESERVED8[3];
- __IO uint8_t OCSC;
+ union {
+ __IO uint8_t OCSC;
+ stc_mft_ocu_ocsc_field_t OCSC_f;
+ };
uint8_t RESERVED9[50];
- __IO uint8_t OCFS10;
- __IO uint8_t OCFS32;
+ union {
+ __IO uint8_t OCFS10;
+ stc_mft_ocu_ocfs10_field_t OCFS10_f;
+ };
+ union {
+ __IO uint8_t OCFS32;
+ stc_mft_ocu_ocfs32_field_t OCFS32_f;
+ };
uint8_t RESERVED10[2];
- __IO uint8_t OCFS54;
+ union {
+ __IO uint8_t OCFS54;
+ stc_mft_ocu_ocfs54_field_t OCFS54_f;
+ };
}FM3_MFT_OCU_TypeDef;
/******************************************************************************
@@ -342,15 +6849,30 @@ typedef struct uint8_t RESERVED2[2];
__IO uint16_t WFTM54;
uint8_t RESERVED3[2];
- __IO uint16_t WFSA10;
+ union {
+ __IO uint16_t WFSA10;
+ stc_mft_wfg_wfsa10_field_t WFSA10_f;
+ };
uint8_t RESERVED4[2];
- __IO uint16_t WFSA32;
+ union {
+ __IO uint16_t WFSA32;
+ stc_mft_wfg_wfsa32_field_t WFSA32_f;
+ };
uint8_t RESERVED5[2];
- __IO uint16_t WFSA54;
+ union {
+ __IO uint16_t WFSA54;
+ stc_mft_wfg_wfsa54_field_t WFSA54_f;
+ };
uint8_t RESERVED6[2];
- __IO uint16_t WFIR;
+ union {
+ __IO uint16_t WFIR;
+ stc_mft_wfg_wfir_field_t WFIR_f;
+ };
uint8_t RESERVED7[2];
- __IO uint16_t NZCL;
+ union {
+ __IO uint16_t NZCL;
+ stc_mft_wfg_nzcl_field_t NZCL_f;
+ };
}FM3_MFT_WFG_TypeDef;
/******************************************************************************
@@ -360,8 +6882,14 @@ typedef struct typedef struct
{
uint8_t RESERVED0[96];
- __IO uint8_t ICFS10;
- __IO uint8_t ICFS32;
+ union {
+ __IO uint8_t ICFS10;
+ stc_mft_icu_icfs10_field_t ICFS10_f;
+ };
+ union {
+ __IO uint8_t ICFS32;
+ stc_mft_icu_icfs32_field_t ICFS32_f;
+ };
uint8_t RESERVED1[6];
__IO uint16_t ICCP0;
uint8_t RESERVED2[2];
@@ -371,11 +6899,23 @@ typedef struct uint8_t RESERVED4[2];
__IO uint16_t ICCP3;
uint8_t RESERVED5[2];
- __IO uint8_t ICSA10;
- __IO uint8_t ICSB10;
+ union {
+ __IO uint8_t ICSA10;
+ stc_mft_icu_icsa10_field_t ICSA10_f;
+ };
+ union {
+ __IO uint8_t ICSB10;
+ stc_mft_icu_icsb10_field_t ICSB10_f;
+ };
uint8_t RESERVED6[2];
- __IO uint8_t ICSA32;
- __IO uint8_t ICSB32;
+ union {
+ __IO uint8_t ICSA32;
+ stc_mft_icu_icsa32_field_t ICSA32_f;
+ };
+ union {
+ __IO uint8_t ICSB32;
+ stc_mft_icu_icsb32_field_t ICSB32_f;
+ };
}FM3_MFT_ICU_TypeDef;
/******************************************************************************
@@ -397,11 +6937,20 @@ typedef struct uint8_t RESERVED5[2];
__IO uint16_t ACCPDN2;
uint8_t RESERVED6[2];
- __IO uint8_t ACSB;
+ union {
+ __IO uint8_t ACSB;
+ stc_mft_adcmp_acsb_field_t ACSB_f;
+ };
uint8_t RESERVED7[3];
- __IO uint16_t ACSA;
+ union {
+ __IO uint16_t ACSA;
+ stc_mft_adcmp_acsa_field_t ACSA_f;
+ };
uint8_t RESERVED8[2];
- __IO uint16_t ATSA;
+ union {
+ __IO uint16_t ATSA;
+ stc_mft_adcmp_atsa_field_t ATSA_f;
+ };
}FM3_MFT_ADCMP_TypeDef;
/******************************************************************************
@@ -411,7 +6960,10 @@ typedef struct typedef struct
{
uint8_t RESERVED0;
- __IO uint8_t TTCR0;
+ union {
+ __IO uint8_t TTCR0;
+ stc_mft_ppg_ttcr0_field_t TTCR0_f;
+ };
uint8_t RESERVED1[7];
__IO uint8_t COMP0;
uint8_t RESERVED2[2];
@@ -421,7 +6973,10 @@ typedef struct uint8_t RESERVED4[2];
__IO uint8_t COMP6;
uint8_t RESERVED5[12];
- __IO uint8_t TTCR1;
+ union {
+ __IO uint8_t TTCR1;
+ stc_mft_ppg_ttcr1_field_t TTCR1_f;
+ };
uint8_t RESERVED6[7];
__IO uint8_t COMP1;
uint8_t RESERVED7[2];
@@ -431,15 +6986,33 @@ typedef struct uint8_t RESERVED9[2];
__IO uint8_t COMP7;
uint8_t RESERVED10[203];
- __IO uint16_t TRG;
+ union {
+ __IO uint16_t TRG;
+ stc_mft_ppg_trg_field_t TRG_f;
+ };
uint8_t RESERVED11[2];
- __IO uint16_t REVC;
+ union {
+ __IO uint16_t REVC;
+ stc_mft_ppg_revc_field_t REVC_f;
+ };
uint8_t RESERVED12[250];
- __IO uint8_t PPGC1;
- __IO uint8_t PPGC0;
+ union {
+ __IO uint8_t PPGC1;
+ stc_mft_ppg_ppgc1_field_t PPGC1_f;
+ };
+ union {
+ __IO uint8_t PPGC0;
+ stc_mft_ppg_ppgc0_field_t PPGC0_f;
+ };
uint8_t RESERVED13[2];
- __IO uint8_t PPGC3;
- __IO uint8_t PPGC2;
+ union {
+ __IO uint8_t PPGC3;
+ stc_mft_ppg_ppgc3_field_t PPGC3_f;
+ };
+ union {
+ __IO uint8_t PPGC2;
+ stc_mft_ppg_ppgc2_field_t PPGC2_f;
+ };
uint8_t RESERVED14[2];
union {
__IO uint16_t PRL0;
@@ -473,13 +7046,28 @@ typedef struct };
};
uint8_t RESERVED18[2];
- __IO uint8_t GATEC0;
+ union {
+ __IO uint8_t GATEC0;
+ stc_mft_ppg_gatec0_field_t GATEC0_f;
+ };
uint8_t RESERVED19[39];
- __IO uint8_t PPGC5;
- __IO uint8_t PPGC4;
+ union {
+ __IO uint8_t PPGC5;
+ stc_mft_ppg_ppgc5_field_t PPGC5_f;
+ };
+ union {
+ __IO uint8_t PPGC4;
+ stc_mft_ppg_ppgc4_field_t PPGC4_f;
+ };
uint8_t RESERVED20[2];
- __IO uint8_t PPGC7;
- __IO uint8_t PPGC6;
+ union {
+ __IO uint8_t PPGC7;
+ stc_mft_ppg_ppgc7_field_t PPGC7_f;
+ };
+ union {
+ __IO uint8_t PPGC6;
+ stc_mft_ppg_ppgc6_field_t PPGC6_f;
+ };
uint8_t RESERVED21[2];
union {
__IO uint16_t PRL4;
@@ -513,13 +7101,28 @@ typedef struct };
};
uint8_t RESERVED25[2];
- __IO uint8_t GATEC4;
+ union {
+ __IO uint8_t GATEC4;
+ stc_mft_ppg_gatec4_field_t GATEC4_f;
+ };
uint8_t RESERVED26[39];
- __IO uint8_t PPGC9;
- __IO uint8_t PPGC8;
+ union {
+ __IO uint8_t PPGC9;
+ stc_mft_ppg_ppgc9_field_t PPGC9_f;
+ };
+ union {
+ __IO uint8_t PPGC8;
+ stc_mft_ppg_ppgc8_field_t PPGC8_f;
+ };
uint8_t RESERVED27[2];
- __IO uint8_t PPGC11;
- __IO uint8_t PPGC10;
+ union {
+ __IO uint8_t PPGC11;
+ stc_mft_ppg_ppgc11_field_t PPGC11_f;
+ };
+ union {
+ __IO uint8_t PPGC10;
+ stc_mft_ppg_ppgc10_field_t PPGC10_f;
+ };
uint8_t RESERVED28[2];
union {
__IO uint16_t PRL8;
@@ -553,13 +7156,28 @@ typedef struct };
};
uint8_t RESERVED32[2];
- __IO uint8_t GATEC8;
+ union {
+ __IO uint8_t GATEC8;
+ stc_mft_ppg_gatec8_field_t GATEC8_f;
+ };
uint8_t RESERVED33[39];
- __IO uint8_t PPGC13;
- __IO uint8_t PPGC12;
+ union {
+ __IO uint8_t PPGC13;
+ stc_mft_ppg_ppgc13_field_t PPGC13_f;
+ };
+ union {
+ __IO uint8_t PPGC12;
+ stc_mft_ppg_ppgc12_field_t PPGC12_f;
+ };
uint8_t RESERVED34[2];
- __IO uint8_t PPGC15;
- __IO uint8_t PPGC14;
+ union {
+ __IO uint8_t PPGC15;
+ stc_mft_ppg_ppgc15_field_t PPGC15_f;
+ };
+ union {
+ __IO uint8_t PPGC14;
+ stc_mft_ppg_ppgc14_field_t PPGC14_f;
+ };
uint8_t RESERVED35[2];
union {
__IO uint16_t PRL12;
@@ -593,7 +7211,10 @@ typedef struct };
};
uint8_t RESERVED39[2];
- __IO uint8_t GATEC12;
+ union {
+ __IO uint8_t GATEC12;
+ stc_mft_ppg_gatec12_field_t GATEC12_f;
+ };
}FM3_MFT_PPG_TypeDef;
/******************************************************************************
@@ -608,10 +7229,19 @@ typedef struct uint8_t RESERVED1[2];
__IO uint16_t TMR;
uint8_t RESERVED2[2];
- __IO uint16_t TMCR;
+ union {
+ __IO uint16_t TMCR;
+ stc_bt_ppg_tmcr_field_t TMCR_f;
+ };
uint8_t RESERVED3[2];
- __IO uint8_t STC;
- __IO uint8_t TMCR2;
+ union {
+ __IO uint8_t STC;
+ stc_bt_ppg_stc_field_t STC_f;
+ };
+ union {
+ __IO uint8_t TMCR2;
+ stc_bt_ppg_tmcr2_field_t TMCR2_f;
+ };
}FM3_BT_PPG_TypeDef;
/******************************************************************************
@@ -626,10 +7256,19 @@ typedef struct uint8_t RESERVED1[2];
__IO uint16_t TMR;
uint8_t RESERVED2[2];
- __IO uint16_t TMCR;
+ union {
+ __IO uint16_t TMCR;
+ stc_bt_pwm_tmcr_field_t TMCR_f;
+ };
uint8_t RESERVED3[2];
- __IO uint8_t STC;
- __IO uint8_t TMCR2;
+ union {
+ __IO uint8_t STC;
+ stc_bt_pwm_stc_field_t STC_f;
+ };
+ union {
+ __IO uint8_t TMCR2;
+ stc_bt_pwm_tmcr2_field_t TMCR2_f;
+ };
}FM3_BT_PWM_TypeDef;
/******************************************************************************
@@ -642,10 +7281,19 @@ typedef struct uint8_t RESERVED0[6];
__IO uint16_t TMR;
uint8_t RESERVED1[2];
- __IO uint16_t TMCR;
+ union {
+ __IO uint16_t TMCR;
+ stc_bt_rt_tmcr_field_t TMCR_f;
+ };
uint8_t RESERVED2[2];
- __IO uint8_t STC;
- __IO uint8_t TMCR2;
+ union {
+ __IO uint8_t STC;
+ stc_bt_rt_stc_field_t STC_f;
+ };
+ union {
+ __IO uint8_t TMCR2;
+ stc_bt_rt_tmcr2_field_t TMCR2_f;
+ };
}FM3_BT_RT_TypeDef;
/******************************************************************************
@@ -657,10 +7305,19 @@ typedef struct uint8_t RESERVED0[4];
__IO uint16_t DTBF;
uint8_t RESERVED1[6];
- __IO uint16_t TMCR;
+ union {
+ __IO uint16_t TMCR;
+ stc_bt_pwc_tmcr_field_t TMCR_f;
+ };
uint8_t RESERVED2[2];
- __IO uint8_t STC;
- __IO uint8_t TMCR2;
+ union {
+ __IO uint8_t STC;
+ stc_bt_pwc_stc_field_t STC_f;
+ };
+ union {
+ __IO uint8_t TMCR2;
+ stc_bt_pwc_tmcr2_field_t TMCR2_f;
+ };
}FM3_BT_PWC_TypeDef;
/******************************************************************************
@@ -670,7 +7327,10 @@ typedef struct typedef struct
{
uint8_t RESERVED0;
- __IO uint8_t BTSEL0123;
+ union {
+ __IO uint8_t BTSEL0123;
+ stc_btiosel03_btsel0123_field_t BTSEL0123_f;
+ };
}FM3_BTIOSEL03_TypeDef;
/******************************************************************************
@@ -680,7 +7340,10 @@ typedef struct typedef struct
{
uint8_t RESERVED0;
- __IO uint8_t BTSEL4567;
+ union {
+ __IO uint8_t BTSEL4567;
+ stc_btiosel47_btsel4567_field_t BTSEL4567_f;
+ };
}FM3_BTIOSEL47_TypeDef;
/******************************************************************************
@@ -689,7 +7352,10 @@ typedef struct /* Software based Simulation Startup (Base Timer) register */
typedef struct
{
- __IO uint16_t BTSSSR;
+ union {
+ __IO uint16_t BTSSSR;
+ stc_sbssr_btsssr_field_t BTSSSR_f;
+ };
}FM3_SBSSR_TypeDef;
/******************************************************************************
@@ -709,22 +7375,43 @@ typedef struct __IO uint16_t QMPR;
uint8_t RESERVED4[2];
union {
- __IO uint16_t QICR;
+ union {
+ __IO uint16_t QICR;
+ stc_qprc_qicr_field_t QICR_f;
+ };
struct {
- __IO uint8_t QICRL;
- __IO uint8_t QICRH;
+ union {
+ __IO uint8_t QICRL;
+ stc_qprc_qicrl_field_t QICRL_f;
+ };
+ union {
+ __IO uint8_t QICRH;
+ stc_qprc_qicrh_field_t QICRH_f;
+ };
};
};
uint8_t RESERVED5[2];
union {
- __IO uint16_t QCR;
+ union {
+ __IO uint16_t QCR;
+ stc_qprc_qcr_field_t QCR_f;
+ };
struct {
- __IO uint8_t QCRL;
- __IO uint8_t QCRH;
+ union {
+ __IO uint8_t QCRL;
+ stc_qprc_qcrl_field_t QCRL_f;
+ };
+ union {
+ __IO uint8_t QCRH;
+ stc_qprc_qcrh_field_t QCRH_f;
+ };
};
};
uint8_t RESERVED6[2];
- __IO uint16_t QECR;
+ union {
+ __IO uint16_t QECR;
+ stc_qprc_qecr_field_t QECR_f;
+ };
}FM3_QPRC_TypeDef;
/******************************************************************************
@@ -733,80 +7420,182 @@ typedef struct /* 12-bit ADC unit 0 registers */
typedef struct
{
- __IO uint8_t ADSR;
- __IO uint8_t ADCR;
+ union {
+ __IO uint8_t ADSR;
+ stc_adc_adsr_field_t ADSR_f;
+ };
+ union {
+ __IO uint8_t ADCR;
+ stc_adc_adcr_field_t ADCR_f;
+ };
uint8_t RESERVED0[6];
- __IO uint8_t SFNS;
- __IO uint8_t SCCR;
+ union {
+ __IO uint8_t SFNS;
+ stc_adc_sfns_field_t SFNS_f;
+ };
+ union {
+ __IO uint8_t SCCR;
+ stc_adc_sccr_field_t SCCR_f;
+ };
uint8_t RESERVED1[2];
union {
- __IO uint32_t SCFD;
+ union {
+ __IO uint32_t SCFD;
+ stc_adc_scfd_field_t SCFD_f;
+ };
struct {
- __IO uint16_t SCFDL;
- __IO uint16_t SCFDH;
+ union {
+ __IO uint16_t SCFDL;
+ stc_adc_scfdl_field_t SCFDL_f;
+ };
+ union {
+ __IO uint16_t SCFDH;
+ stc_adc_scfdh_field_t SCFDH_f;
+ };
};
};
union {
- __IO uint16_t SCIS23;
+ union {
+ __IO uint16_t SCIS23;
+ stc_adc_scis23_field_t SCIS23_f;
+ };
struct {
- __IO uint8_t SCIS2;
- __IO uint8_t SCIS3;
+ union {
+ __IO uint8_t SCIS2;
+ stc_adc_scis2_field_t SCIS2_f;
+ };
+ union {
+ __IO uint8_t SCIS3;
+ stc_adc_scis3_field_t SCIS3_f;
+ };
};
};
uint8_t RESERVED2[2];
union {
- __IO uint16_t SCIS01;
+ union {
+ __IO uint16_t SCIS01;
+ stc_adc_scis01_field_t SCIS01_f;
+ };
struct {
- __IO uint8_t SCIS0;
- __IO uint8_t SCIS1;
+ union {
+ __IO uint8_t SCIS0;
+ stc_adc_scis0_field_t SCIS0_f;
+ };
+ union {
+ __IO uint8_t SCIS1;
+ stc_adc_scis1_field_t SCIS1_f;
+ };
};
};
uint8_t RESERVED3[2];
- __IO uint8_t PFNS;
- __IO uint8_t PCCR;
+ union {
+ __IO uint8_t PFNS;
+ stc_adc_pfns_field_t PFNS_f;
+ };
+ union {
+ __IO uint8_t PCCR;
+ stc_adc_pccr_field_t PCCR_f;
+ };
uint8_t RESERVED4[2];
union {
- __IO uint32_t PCFD;
+ union {
+ __IO uint32_t PCFD;
+ stc_adc_pcfd_field_t PCFD_f;
+ };
struct {
- __IO uint16_t PCFDL;
- __IO uint16_t PCFDH;
+ union {
+ __IO uint16_t PCFDL;
+ stc_adc_pcfdl_field_t PCFDL_f;
+ };
+ union {
+ __IO uint16_t PCFDH;
+ stc_adc_pcfdh_field_t PCFDH_f;
+ };
};
};
- __IO uint8_t PCIS;
+ union {
+ __IO uint8_t PCIS;
+ stc_adc_pcis_field_t PCIS_f;
+ };
uint8_t RESERVED5[3];
- __IO uint8_t CMPCR;
+ union {
+ __IO uint8_t CMPCR;
+ stc_adc_cmpcr_field_t CMPCR_f;
+ };
uint8_t RESERVED6;
- __IO uint16_t CMPD;
union {
- __IO uint16_t ADSS23;
+ __IO uint16_t CMPD;
+ stc_adc_cmpd_field_t CMPD_f;
+ };
+ union {
+ union {
+ __IO uint16_t ADSS23;
+ stc_adc_adss23_field_t ADSS23_f;
+ };
struct {
- __IO uint8_t ADSS2;
- __IO uint8_t ADSS3;
+ union {
+ __IO uint8_t ADSS2;
+ stc_adc_adss2_field_t ADSS2_f;
+ };
+ union {
+ __IO uint8_t ADSS3;
+ stc_adc_adss3_field_t ADSS3_f;
+ };
};
};
uint8_t RESERVED7[2];
union {
- __IO uint16_t ADSS01;
+ union {
+ __IO uint16_t ADSS01;
+ stc_adc_adss01_field_t ADSS01_f;
+ };
struct {
- __IO uint8_t ADSS0;
- __IO uint8_t ADSS1;
+ union {
+ __IO uint8_t ADSS0;
+ stc_adc_adss0_field_t ADSS0_f;
+ };
+ union {
+ __IO uint8_t ADSS1;
+ stc_adc_adss1_field_t ADSS1_f;
+ };
};
};
uint8_t RESERVED8[2];
union {
- __IO uint16_t ADST01;
+ union {
+ __IO uint16_t ADST01;
+ stc_adc_adst01_field_t ADST01_f;
+ };
struct {
- __IO uint8_t ADST1;
- __IO uint8_t ADST0;
+ union {
+ __IO uint8_t ADST1;
+ stc_adc_adst1_field_t ADST1_f;
+ };
+ union {
+ __IO uint8_t ADST0;
+ stc_adc_adst0_field_t ADST0_f;
+ };
};
};
uint8_t RESERVED9[2];
- __IO uint8_t ADCT;
+ union {
+ __IO uint8_t ADCT;
+ stc_adc_adct_field_t ADCT_f;
+ };
uint8_t RESERVED10[3];
- __IO uint8_t PRTSL;
- __IO uint8_t SCTSL;
+ union {
+ __IO uint8_t PRTSL;
+ stc_adc_prtsl_field_t PRTSL_f;
+ };
+ union {
+ __IO uint8_t SCTSL;
+ stc_adc_sctsl_field_t SCTSL_f;
+ };
uint8_t RESERVED11[2];
- __IO uint8_t ADCEN;
+ union {
+ __IO uint8_t ADCEN;
+ stc_adc_adcen_field_t ADCEN_f;
+ };
}FM3_ADC_TypeDef;
/******************************************************************************
@@ -815,9 +7604,15 @@ typedef struct /* CR trimming registers */
typedef struct
{
- __IO uint8_t MCR_PSR;
+ union {
+ __IO uint8_t MCR_PSR;
+ stc_crtrim_mcr_psr_field_t MCR_PSR_f;
+ };
uint8_t RESERVED0[3];
- __IO uint16_t MCR_FTRM;
+ union {
+ __IO uint16_t MCR_FTRM;
+ stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;
+ };
uint8_t RESERVED1[6];
__IO uint32_t MCR_RLR;
}FM3_CRTRIM_TypeDef;
@@ -828,17 +7623,35 @@ typedef struct /* External interrupt registers */
typedef struct
{
- __IO uint16_t ENIR;
+ union {
+ __IO uint16_t ENIR;
+ stc_exti_enir_field_t ENIR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint16_t EIRR;
+ union {
+ __IO uint16_t EIRR;
+ stc_exti_eirr_field_t EIRR_f;
+ };
uint8_t RESERVED1[2];
- __IO uint16_t EICL;
+ union {
+ __IO uint16_t EICL;
+ stc_exti_eicl_field_t EICL_f;
+ };
uint8_t RESERVED2[2];
- __IO uint32_t ELVR;
+ union {
+ __IO uint32_t ELVR;
+ stc_exti_elvr_field_t ELVR_f;
+ };
uint8_t RESERVED3[4];
- __IO uint8_t NMIRR;
+ union {
+ __IO uint8_t NMIRR;
+ stc_exti_nmirr_field_t NMIRR_f;
+ };
uint8_t RESERVED4[3];
- __IO uint8_t NMICL;
+ union {
+ __IO uint8_t NMICL;
+ stc_exti_nmicl_field_t NMICL_f;
+ };
}FM3_EXTI_TypeDef;
/******************************************************************************
@@ -847,55 +7660,193 @@ typedef struct /* Interrupt request read registers */
typedef struct
{
- __IO uint32_t DRQSEL;
+ union {
+ __IO uint32_t DRQSEL;
+ stc_intreq_drqsel_field_t DRQSEL_f;
+ };
uint8_t RESERVED0[12];
- __IO uint32_t EXC02MON;
- __IO uint32_t IRQ00MON;
- __IO uint32_t IRQ01MON;
- __IO uint32_t IRQ02MON;
- __IO uint32_t IRQ03MON;
- __IO uint32_t IRQ04MON;
- __IO uint32_t IRQ05MON;
- __IO uint32_t IRQ06MON;
- __IO uint32_t IRQ07MON;
- __IO uint32_t IRQ08MON;
- __IO uint32_t IRQ09MON;
- __IO uint32_t IRQ10MON;
- __IO uint32_t IRQ11MON;
- __IO uint32_t IRQ12MON;
- __IO uint32_t IRQ13MON;
- __IO uint32_t IRQ14MON;
- __IO uint32_t IRQ15MON;
- __IO uint32_t IRQ16MON;
- __IO uint32_t IRQ17MON;
- __IO uint32_t IRQ18MON;
- __IO uint32_t IRQ19MON;
- __IO uint32_t IRQ20MON;
- __IO uint32_t IRQ21MON;
- __IO uint32_t IRQ22MON;
- __IO uint32_t IRQ23MON;
- __IO uint32_t IRQ24MON;
- __IO uint32_t IRQ25MON;
- __IO uint32_t IRQ26MON;
- __IO uint32_t IRQ27MON;
- __IO uint32_t IRQ28MON;
- __IO uint32_t IRQ29MON;
- __IO uint32_t IRQ30MON;
- __IO uint32_t IRQ31MON;
- __IO uint32_t IRQ32MON;
- __IO uint32_t IRQ33MON;
- __IO uint32_t IRQ34MON;
- __IO uint32_t IRQ35MON;
+ union {
+ __IO uint32_t EXC02MON;
+ stc_intreq_exc02mon_field_t EXC02MON_f;
+ };
+ union {
+ __IO uint32_t IRQ00MON;
+ stc_intreq_irq00mon_field_t IRQ00MON_f;
+ };
+ union {
+ __IO uint32_t IRQ01MON;
+ stc_intreq_irq01mon_field_t IRQ01MON_f;
+ };
+ union {
+ __IO uint32_t IRQ02MON;
+ stc_intreq_irq02mon_field_t IRQ02MON_f;
+ };
+ union {
+ __IO uint32_t IRQ03MON;
+ stc_intreq_irq03mon_field_t IRQ03MON_f;
+ };
+ union {
+ __IO uint32_t IRQ04MON;
+ stc_intreq_irq04mon_field_t IRQ04MON_f;
+ };
+ union {
+ __IO uint32_t IRQ05MON;
+ stc_intreq_irq05mon_field_t IRQ05MON_f;
+ };
+ union {
+ __IO uint32_t IRQ06MON;
+ stc_intreq_irq06mon_field_t IRQ06MON_f;
+ };
+ union {
+ __IO uint32_t IRQ07MON;
+ stc_intreq_irq07mon_field_t IRQ07MON_f;
+ };
+ union {
+ __IO uint32_t IRQ08MON;
+ stc_intreq_irq08mon_field_t IRQ08MON_f;
+ };
+ union {
+ __IO uint32_t IRQ09MON;
+ stc_intreq_irq09mon_field_t IRQ09MON_f;
+ };
+ union {
+ __IO uint32_t IRQ10MON;
+ stc_intreq_irq10mon_field_t IRQ10MON_f;
+ };
+ union {
+ __IO uint32_t IRQ11MON;
+ stc_intreq_irq11mon_field_t IRQ11MON_f;
+ };
+ union {
+ __IO uint32_t IRQ12MON;
+ stc_intreq_irq12mon_field_t IRQ12MON_f;
+ };
+ union {
+ __IO uint32_t IRQ13MON;
+ stc_intreq_irq13mon_field_t IRQ13MON_f;
+ };
+ union {
+ __IO uint32_t IRQ14MON;
+ stc_intreq_irq14mon_field_t IRQ14MON_f;
+ };
+ union {
+ __IO uint32_t IRQ15MON;
+ stc_intreq_irq15mon_field_t IRQ15MON_f;
+ };
+ union {
+ __IO uint32_t IRQ16MON;
+ stc_intreq_irq16mon_field_t IRQ16MON_f;
+ };
+ union {
+ __IO uint32_t IRQ17MON;
+ stc_intreq_irq17mon_field_t IRQ17MON_f;
+ };
+ union {
+ __IO uint32_t IRQ18MON;
+ stc_intreq_irq18mon_field_t IRQ18MON_f;
+ };
+ union {
+ __IO uint32_t IRQ19MON;
+ stc_intreq_irq19mon_field_t IRQ19MON_f;
+ };
+ union {
+ __IO uint32_t IRQ20MON;
+ stc_intreq_irq20mon_field_t IRQ20MON_f;
+ };
+ union {
+ __IO uint32_t IRQ21MON;
+ stc_intreq_irq21mon_field_t IRQ21MON_f;
+ };
+ union {
+ __IO uint32_t IRQ22MON;
+ stc_intreq_irq22mon_field_t IRQ22MON_f;
+ };
+ union {
+ __IO uint32_t IRQ23MON;
+ stc_intreq_irq23mon_field_t IRQ23MON_f;
+ };
+ union {
+ __IO uint32_t IRQ24MON;
+ stc_intreq_irq24mon_field_t IRQ24MON_f;
+ };
+ union {
+ __IO uint32_t IRQ25MON;
+ stc_intreq_irq25mon_field_t IRQ25MON_f;
+ };
+ union {
+ __IO uint32_t IRQ26MON;
+ stc_intreq_irq26mon_field_t IRQ26MON_f;
+ };
+ union {
+ __IO uint32_t IRQ27MON;
+ stc_intreq_irq27mon_field_t IRQ27MON_f;
+ };
+ union {
+ __IO uint32_t IRQ28MON;
+ stc_intreq_irq28mon_field_t IRQ28MON_f;
+ };
+ union {
+ __IO uint32_t IRQ29MON;
+ stc_intreq_irq29mon_field_t IRQ29MON_f;
+ };
+ union {
+ __IO uint32_t IRQ30MON;
+ stc_intreq_irq30mon_field_t IRQ30MON_f;
+ };
+ union {
+ __IO uint32_t IRQ31MON;
+ stc_intreq_irq31mon_field_t IRQ31MON_f;
+ };
+ union {
+ __IO uint32_t IRQ32MON;
+ stc_intreq_irq32mon_field_t IRQ32MON_f;
+ };
+ union {
+ __IO uint32_t IRQ33MON;
+ stc_intreq_irq33mon_field_t IRQ33MON_f;
+ };
+ union {
+ __IO uint32_t IRQ34MON;
+ stc_intreq_irq34mon_field_t IRQ34MON_f;
+ };
+ union {
+ __IO uint32_t IRQ35MON;
+ stc_intreq_irq35mon_field_t IRQ35MON_f;
+ };
__IO uint32_t IRQ36MON;
__IO uint32_t IRQ37MON;
- __IO uint32_t IRQ38MON;
- __IO uint32_t IRQ39MON;
- __IO uint32_t IRQ40MON;
- __IO uint32_t IRQ41MON;
- __IO uint32_t IRQ42MON;
- __IO uint32_t IRQ43MON;
- __IO uint32_t IRQ44MON;
- __IO uint32_t IRQ45MON;
+ union {
+ __IO uint32_t IRQ38MON;
+ stc_intreq_irq38mon_field_t IRQ38MON_f;
+ };
+ union {
+ __IO uint32_t IRQ39MON;
+ stc_intreq_irq39mon_field_t IRQ39MON_f;
+ };
+ union {
+ __IO uint32_t IRQ40MON;
+ stc_intreq_irq40mon_field_t IRQ40MON_f;
+ };
+ union {
+ __IO uint32_t IRQ41MON;
+ stc_intreq_irq41mon_field_t IRQ41MON_f;
+ };
+ union {
+ __IO uint32_t IRQ42MON;
+ stc_intreq_irq42mon_field_t IRQ42MON_f;
+ };
+ union {
+ __IO uint32_t IRQ43MON;
+ stc_intreq_irq43mon_field_t IRQ43MON_f;
+ };
+ union {
+ __IO uint32_t IRQ44MON;
+ stc_intreq_irq44mon_field_t IRQ44MON_f;
+ };
+ union {
+ __IO uint32_t IRQ45MON;
+ stc_intreq_irq45mon_field_t IRQ45MON_f;
+ };
__IO uint32_t IRQ46MON;
__IO uint32_t IRQ47MON;
}FM3_INTREQ_TypeDef;
@@ -906,70 +7857,238 @@ typedef struct /* General purpose I/O registers */
typedef struct
{
- __IO uint32_t PFR0;
- __IO uint32_t PFR1;
- __IO uint32_t PFR2;
- __IO uint32_t PFR3;
- __IO uint32_t PFR4;
- __IO uint32_t PFR5;
- __IO uint32_t PFR6;
- __IO uint32_t PFR7;
- __IO uint32_t PFR8;
+ union {
+ __IO uint32_t PFR0;
+ stc_gpio_pfr0_field_t PFR0_f;
+ };
+ union {
+ __IO uint32_t PFR1;
+ stc_gpio_pfr1_field_t PFR1_f;
+ };
+ union {
+ __IO uint32_t PFR2;
+ stc_gpio_pfr2_field_t PFR2_f;
+ };
+ union {
+ __IO uint32_t PFR3;
+ stc_gpio_pfr3_field_t PFR3_f;
+ };
+ union {
+ __IO uint32_t PFR4;
+ stc_gpio_pfr4_field_t PFR4_f;
+ };
+ union {
+ __IO uint32_t PFR5;
+ stc_gpio_pfr5_field_t PFR5_f;
+ };
+ union {
+ __IO uint32_t PFR6;
+ stc_gpio_pfr6_field_t PFR6_f;
+ };
+ union {
+ __IO uint32_t PFR7;
+ stc_gpio_pfr7_field_t PFR7_f;
+ };
+ union {
+ __IO uint32_t PFR8;
+ stc_gpio_pfr8_field_t PFR8_f;
+ };
uint8_t RESERVED0[220];
- __IO uint32_t PCR0;
- __IO uint32_t PCR1;
- __IO uint32_t PCR2;
- __IO uint32_t PCR3;
- __IO uint32_t PCR4;
- __IO uint32_t PCR5;
- __IO uint32_t PCR6;
- __IO uint32_t PCR7;
+ union {
+ __IO uint32_t PCR0;
+ stc_gpio_pcr0_field_t PCR0_f;
+ };
+ union {
+ __IO uint32_t PCR1;
+ stc_gpio_pcr1_field_t PCR1_f;
+ };
+ union {
+ __IO uint32_t PCR2;
+ stc_gpio_pcr2_field_t PCR2_f;
+ };
+ union {
+ __IO uint32_t PCR3;
+ stc_gpio_pcr3_field_t PCR3_f;
+ };
+ union {
+ __IO uint32_t PCR4;
+ stc_gpio_pcr4_field_t PCR4_f;
+ };
+ union {
+ __IO uint32_t PCR5;
+ stc_gpio_pcr5_field_t PCR5_f;
+ };
+ union {
+ __IO uint32_t PCR6;
+ stc_gpio_pcr6_field_t PCR6_f;
+ };
+ union {
+ __IO uint32_t PCR7;
+ stc_gpio_pcr7_field_t PCR7_f;
+ };
uint8_t RESERVED1[224];
- __IO uint32_t DDR0;
- __IO uint32_t DDR1;
- __IO uint32_t DDR2;
- __IO uint32_t DDR3;
- __IO uint32_t DDR4;
- __IO uint32_t DDR5;
- __IO uint32_t DDR6;
- __IO uint32_t DDR7;
- __IO uint32_t DDR8;
+ union {
+ __IO uint32_t DDR0;
+ stc_gpio_ddr0_field_t DDR0_f;
+ };
+ union {
+ __IO uint32_t DDR1;
+ stc_gpio_ddr1_field_t DDR1_f;
+ };
+ union {
+ __IO uint32_t DDR2;
+ stc_gpio_ddr2_field_t DDR2_f;
+ };
+ union {
+ __IO uint32_t DDR3;
+ stc_gpio_ddr3_field_t DDR3_f;
+ };
+ union {
+ __IO uint32_t DDR4;
+ stc_gpio_ddr4_field_t DDR4_f;
+ };
+ union {
+ __IO uint32_t DDR5;
+ stc_gpio_ddr5_field_t DDR5_f;
+ };
+ union {
+ __IO uint32_t DDR6;
+ stc_gpio_ddr6_field_t DDR6_f;
+ };
+ union {
+ __IO uint32_t DDR7;
+ stc_gpio_ddr7_field_t DDR7_f;
+ };
+ union {
+ __IO uint32_t DDR8;
+ stc_gpio_ddr8_field_t DDR8_f;
+ };
uint8_t RESERVED2[220];
- __IO uint32_t PDIR0;
- __IO uint32_t PDIR1;
- __IO uint32_t PDIR2;
- __IO uint32_t PDIR3;
- __IO uint32_t PDIR4;
- __IO uint32_t PDIR5;
- __IO uint32_t PDIR6;
- __IO uint32_t PDIR7;
- __IO uint32_t PDIR8;
+ union {
+ __IO uint32_t PDIR0;
+ stc_gpio_pdir0_field_t PDIR0_f;
+ };
+ union {
+ __IO uint32_t PDIR1;
+ stc_gpio_pdir1_field_t PDIR1_f;
+ };
+ union {
+ __IO uint32_t PDIR2;
+ stc_gpio_pdir2_field_t PDIR2_f;
+ };
+ union {
+ __IO uint32_t PDIR3;
+ stc_gpio_pdir3_field_t PDIR3_f;
+ };
+ union {
+ __IO uint32_t PDIR4;
+ stc_gpio_pdir4_field_t PDIR4_f;
+ };
+ union {
+ __IO uint32_t PDIR5;
+ stc_gpio_pdir5_field_t PDIR5_f;
+ };
+ union {
+ __IO uint32_t PDIR6;
+ stc_gpio_pdir6_field_t PDIR6_f;
+ };
+ union {
+ __IO uint32_t PDIR7;
+ stc_gpio_pdir7_field_t PDIR7_f;
+ };
+ union {
+ __IO uint32_t PDIR8;
+ stc_gpio_pdir8_field_t PDIR8_f;
+ };
uint8_t RESERVED3[220];
- __IO uint32_t PDOR0;
- __IO uint32_t PDOR1;
- __IO uint32_t PDOR2;
- __IO uint32_t PDOR3;
- __IO uint32_t PDOR4;
- __IO uint32_t PDOR5;
- __IO uint32_t PDOR6;
- __IO uint32_t PDOR7;
- __IO uint32_t PDOR8;
+ union {
+ __IO uint32_t PDOR0;
+ stc_gpio_pdor0_field_t PDOR0_f;
+ };
+ union {
+ __IO uint32_t PDOR1;
+ stc_gpio_pdor1_field_t PDOR1_f;
+ };
+ union {
+ __IO uint32_t PDOR2;
+ stc_gpio_pdor2_field_t PDOR2_f;
+ };
+ union {
+ __IO uint32_t PDOR3;
+ stc_gpio_pdor3_field_t PDOR3_f;
+ };
+ union {
+ __IO uint32_t PDOR4;
+ stc_gpio_pdor4_field_t PDOR4_f;
+ };
+ union {
+ __IO uint32_t PDOR5;
+ stc_gpio_pdor5_field_t PDOR5_f;
+ };
+ union {
+ __IO uint32_t PDOR6;
+ stc_gpio_pdor6_field_t PDOR6_f;
+ };
+ union {
+ __IO uint32_t PDOR7;
+ stc_gpio_pdor7_field_t PDOR7_f;
+ };
+ union {
+ __IO uint32_t PDOR8;
+ stc_gpio_pdor8_field_t PDOR8_f;
+ };
uint8_t RESERVED4[220];
- __IO uint32_t ADE;
+ union {
+ __IO uint32_t ADE;
+ stc_gpio_ade_field_t ADE_f;
+ };
uint8_t RESERVED5[124];
- __IO uint32_t SPSR;
+ union {
+ __IO uint32_t SPSR;
+ stc_gpio_spsr_field_t SPSR_f;
+ };
uint8_t RESERVED6[124];
- __IO uint32_t EPFR00;
- __IO uint32_t EPFR01;
- __IO uint32_t EPFR02;
+ union {
+ __IO uint32_t EPFR00;
+ stc_gpio_epfr00_field_t EPFR00_f;
+ };
+ union {
+ __IO uint32_t EPFR01;
+ stc_gpio_epfr01_field_t EPFR01_f;
+ };
+ union {
+ __IO uint32_t EPFR02;
+ stc_gpio_epfr02_field_t EPFR02_f;
+ };
uint8_t RESERVED7[4];
- __IO uint32_t EPFR04;
- __IO uint32_t EPFR05;
- __IO uint32_t EPFR06;
- __IO uint32_t EPFR07;
- __IO uint32_t EPFR08;
- __IO uint32_t EPFR09;
- __IO uint32_t EPFR10;
+ union {
+ __IO uint32_t EPFR04;
+ stc_gpio_epfr04_field_t EPFR04_f;
+ };
+ union {
+ __IO uint32_t EPFR05;
+ stc_gpio_epfr05_field_t EPFR05_f;
+ };
+ union {
+ __IO uint32_t EPFR06;
+ stc_gpio_epfr06_field_t EPFR06_f;
+ };
+ union {
+ __IO uint32_t EPFR07;
+ stc_gpio_epfr07_field_t EPFR07_f;
+ };
+ union {
+ __IO uint32_t EPFR08;
+ stc_gpio_epfr08_field_t EPFR08_f;
+ };
+ union {
+ __IO uint32_t EPFR09;
+ stc_gpio_epfr09_field_t EPFR09_f;
+ };
+ union {
+ __IO uint32_t EPFR10;
+ stc_gpio_epfr10_field_t EPFR10_f;
+ };
}FM3_GPIO_TypeDef;
/******************************************************************************
@@ -978,14 +8097,26 @@ typedef struct /* Low voltage detection registers */
typedef struct
{
- __IO uint8_t LVD_CTL;
+ union {
+ __IO uint8_t LVD_CTL;
+ stc_lvd_lvd_ctl_field_t LVD_CTL_f;
+ };
uint8_t RESERVED0[3];
- __IO uint8_t LVD_STR;
+ union {
+ __IO uint8_t LVD_STR;
+ stc_lvd_lvd_str_field_t LVD_STR_f;
+ };
uint8_t RESERVED1[3];
- __IO uint8_t LVD_CLR;
+ union {
+ __IO uint8_t LVD_CLR;
+ stc_lvd_lvd_clr_field_t LVD_CLR_f;
+ };
uint8_t RESERVED2[3];
__IO uint32_t LVD_RLR;
- __IO uint8_t LVD_STR2;
+ union {
+ __IO uint8_t LVD_STR2;
+ stc_lvd_lvd_str2_field_t LVD_STR2_f;
+ };
}FM3_LVD_TypeDef;
/******************************************************************************
@@ -994,25 +8125,55 @@ typedef struct /* USB clock registers */
typedef struct
{
- __IO uint8_t UCCR;
+ union {
+ __IO uint8_t UCCR;
+ stc_usbclk_uccr_field_t UCCR_f;
+ };
uint8_t RESERVED0[3];
- __IO uint8_t UPCR1;
+ union {
+ __IO uint8_t UPCR1;
+ stc_usbclk_upcr1_field_t UPCR1_f;
+ };
uint8_t RESERVED1[3];
- __IO uint8_t UPCR2;
+ union {
+ __IO uint8_t UPCR2;
+ stc_usbclk_upcr2_field_t UPCR2_f;
+ };
uint8_t RESERVED2[3];
- __IO uint8_t UPCR3;
+ union {
+ __IO uint8_t UPCR3;
+ stc_usbclk_upcr3_field_t UPCR3_f;
+ };
uint8_t RESERVED3[3];
- __IO uint8_t UPCR4;
+ union {
+ __IO uint8_t UPCR4;
+ stc_usbclk_upcr4_field_t UPCR4_f;
+ };
uint8_t RESERVED4[3];
- __IO uint8_t UP_STR;
+ union {
+ __IO uint8_t UP_STR;
+ stc_usbclk_up_str_field_t UP_STR_f;
+ };
uint8_t RESERVED5[3];
- __IO uint8_t UPINT_ENR;
+ union {
+ __IO uint8_t UPINT_ENR;
+ stc_usbclk_upint_enr_field_t UPINT_ENR_f;
+ };
uint8_t RESERVED6[3];
- __IO uint8_t UPINT_CLR;
+ union {
+ __IO uint8_t UPINT_CLR;
+ stc_usbclk_upint_clr_field_t UPINT_CLR_f;
+ };
uint8_t RESERVED7[3];
- __IO uint8_t UPINT_STR;
+ union {
+ __IO uint8_t UPINT_STR;
+ stc_usbclk_upint_str_field_t UPINT_STR_f;
+ };
uint8_t RESERVED8[15];
- __IO uint8_t USBEN;
+ union {
+ __IO uint8_t USBEN;
+ stc_usbclk_usben_field_t USBEN_f;
+ };
}FM3_USBCLK_TypeDef;
/******************************************************************************
@@ -1021,7 +8182,10 @@ typedef struct /* CAN prescaler register */
typedef struct
{
- __IO uint8_t CANPRE;
+ union {
+ __IO uint8_t CANPRE;
+ stc_canpre_canpre_field_t CANPRE_f;
+ };
}FM3_CANPRE_TypeDef;
/******************************************************************************
@@ -1030,22 +8194,46 @@ typedef struct /* UART asynchronous channel 0 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t SCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs03_uart_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t SCR;
+ stc_mfs03_uart_scr_field_t SCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t ESCR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t ESCR;
+ stc_mfs03_uart_escr_field_t ESCR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs03_uart_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
- __IO uint16_t RDR;
- __IO uint16_t TDR;
+ union {
+ __IO uint16_t RDR;
+ stc_mfs03_uart_rdr_field_t RDR_f;
+ };
+ union {
+ __IO uint16_t TDR;
+ stc_mfs03_uart_tdr_field_t TDR_f;
+ };
};
uint8_t RESERVED2[2];
union {
- __IO uint16_t BGR;
+ union {
+ __IO uint16_t BGR;
+ stc_mfs03_uart_bgr_field_t BGR_f;
+ };
struct {
__IO uint8_t BGR0;
- __IO uint8_t BGR1;
+ union {
+ __IO uint8_t BGR1;
+ stc_mfs03_uart_bgr1_field_t BGR1_f;
+ };
};
};
}FM3_MFS03_UART_TypeDef;
@@ -1056,11 +8244,23 @@ typedef struct /* UART synchronous channel 0 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t SCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs03_csio_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t SCR;
+ stc_mfs03_csio_scr_field_t SCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t ESCR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t ESCR;
+ stc_mfs03_csio_escr_field_t ESCR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs03_csio_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
@@ -1082,11 +8282,23 @@ typedef struct /* UART LIN channel 0 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t SCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs03_lin_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t SCR;
+ stc_mfs03_lin_scr_field_t SCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t ESCR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t ESCR;
+ stc_mfs03_lin_escr_field_t ESCR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs03_lin_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
@@ -1094,10 +8306,16 @@ typedef struct };
uint8_t RESERVED2[2];
union {
- __IO uint16_t BGR;
+ union {
+ __IO uint16_t BGR;
+ stc_mfs03_lin_bgr_field_t BGR_f;
+ };
struct {
__IO uint8_t BGR0;
- __IO uint8_t BGR1;
+ union {
+ __IO uint8_t BGR1;
+ stc_mfs03_lin_bgr1_field_t BGR1_f;
+ };
};
};
}FM3_MFS03_LIN_TypeDef;
@@ -1108,11 +8326,23 @@ typedef struct /* I2C channel 0 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t IBCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs03_i2c_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t IBCR;
+ stc_mfs03_i2c_ibcr_field_t IBCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t IBSR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t IBSR;
+ stc_mfs03_i2c_ibsr_field_t IBSR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs03_i2c_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
@@ -1127,8 +8357,14 @@ typedef struct };
};
uint8_t RESERVED3[2];
- __IO uint8_t ISBA;
- __IO uint8_t ISMK;
+ union {
+ __IO uint8_t ISBA;
+ stc_mfs03_i2c_isba_field_t ISBA_f;
+ };
+ union {
+ __IO uint8_t ISMK;
+ stc_mfs03_i2c_ismk_field_t ISMK_f;
+ };
}FM3_MFS03_I2C_TypeDef;
/******************************************************************************
@@ -1137,38 +8373,80 @@ typedef struct /* UART asynchronous channel 4 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t SCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs47_uart_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t SCR;
+ stc_mfs47_uart_scr_field_t SCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t ESCR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t ESCR;
+ stc_mfs47_uart_escr_field_t ESCR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs47_uart_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
- __IO uint16_t RDR;
- __IO uint16_t TDR;
+ union {
+ __IO uint16_t RDR;
+ stc_mfs47_uart_rdr_field_t RDR_f;
+ };
+ union {
+ __IO uint16_t TDR;
+ stc_mfs47_uart_tdr_field_t TDR_f;
+ };
};
uint8_t RESERVED2[2];
union {
- __IO uint16_t BGR;
+ union {
+ __IO uint16_t BGR;
+ stc_mfs47_uart_bgr_field_t BGR_f;
+ };
struct {
__IO uint8_t BGR0;
- __IO uint8_t BGR1;
+ union {
+ __IO uint8_t BGR1;
+ stc_mfs47_uart_bgr1_field_t BGR1_f;
+ };
};
};
uint8_t RESERVED3[6];
union {
- __IO uint16_t FCR;
+ union {
+ __IO uint16_t FCR;
+ stc_mfs47_uart_fcr_field_t FCR_f;
+ };
struct {
- __IO uint8_t FCR0;
- __IO uint8_t FCR1;
+ union {
+ __IO uint8_t FCR0;
+ stc_mfs47_uart_fcr0_field_t FCR0_f;
+ };
+ union {
+ __IO uint8_t FCR1;
+ stc_mfs47_uart_fcr1_field_t FCR1_f;
+ };
};
};
uint8_t RESERVED4[2];
union {
- __IO uint16_t FBYTE;
+ union {
+ __IO uint16_t FBYTE;
+ stc_mfs47_uart_fbyte_field_t FBYTE_f;
+ };
struct {
- __IO uint8_t FBYTE1;
- __IO uint8_t FBYTE2;
+ union {
+ __IO uint8_t FBYTE1;
+ stc_mfs47_uart_fbyte1_field_t FBYTE1_f;
+ };
+ union {
+ __IO uint8_t FBYTE2;
+ stc_mfs47_uart_fbyte2_field_t FBYTE2_f;
+ };
};
};
}FM3_MFS47_UART_TypeDef;
@@ -1179,11 +8457,23 @@ typedef struct /* UART synchronous channel 4 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t SCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs47_csio_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t SCR;
+ stc_mfs47_csio_scr_field_t SCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t ESCR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t ESCR;
+ stc_mfs47_csio_escr_field_t ESCR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs47_csio_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
@@ -1199,18 +8489,36 @@ typedef struct };
uint8_t RESERVED3[6];
union {
- __IO uint16_t FCR;
+ union {
+ __IO uint16_t FCR;
+ stc_mfs47_csio_fcr_field_t FCR_f;
+ };
struct {
- __IO uint8_t FCR0;
- __IO uint8_t FCR1;
+ union {
+ __IO uint8_t FCR0;
+ stc_mfs47_csio_fcr0_field_t FCR0_f;
+ };
+ union {
+ __IO uint8_t FCR1;
+ stc_mfs47_csio_fcr1_field_t FCR1_f;
+ };
};
};
uint8_t RESERVED4[2];
union {
- __IO uint16_t FBYTE;
+ union {
+ __IO uint16_t FBYTE;
+ stc_mfs47_csio_fbyte_field_t FBYTE_f;
+ };
struct {
- __IO uint8_t FBYTE1;
- __IO uint8_t FBYTE2;
+ union {
+ __IO uint8_t FBYTE1;
+ stc_mfs47_csio_fbyte1_field_t FBYTE1_f;
+ };
+ union {
+ __IO uint8_t FBYTE2;
+ stc_mfs47_csio_fbyte2_field_t FBYTE2_f;
+ };
};
};
}FM3_MFS47_CSIO_TypeDef;
@@ -1221,11 +8529,23 @@ typedef struct /* UART LIN channel 4 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t SCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs47_lin_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t SCR;
+ stc_mfs47_lin_scr_field_t SCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t ESCR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t ESCR;
+ stc_mfs47_lin_escr_field_t ESCR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs47_lin_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
@@ -1233,26 +8553,50 @@ typedef struct };
uint8_t RESERVED2[2];
union {
- __IO uint16_t BGR;
+ union {
+ __IO uint16_t BGR;
+ stc_mfs47_lin_bgr_field_t BGR_f;
+ };
struct {
__IO uint8_t BGR0;
- __IO uint8_t BGR1;
+ union {
+ __IO uint8_t BGR1;
+ stc_mfs47_lin_bgr1_field_t BGR1_f;
+ };
};
};
uint8_t RESERVED3[6];
union {
- __IO uint16_t FCR;
+ union {
+ __IO uint16_t FCR;
+ stc_mfs47_lin_fcr_field_t FCR_f;
+ };
struct {
- __IO uint8_t FCR0;
- __IO uint8_t FCR1;
+ union {
+ __IO uint8_t FCR0;
+ stc_mfs47_lin_fcr0_field_t FCR0_f;
+ };
+ union {
+ __IO uint8_t FCR1;
+ stc_mfs47_lin_fcr1_field_t FCR1_f;
+ };
};
};
uint8_t RESERVED4[2];
union {
- __IO uint16_t FBYTE;
+ union {
+ __IO uint16_t FBYTE;
+ stc_mfs47_lin_fbyte_field_t FBYTE_f;
+ };
struct {
- __IO uint8_t FBYTE1;
- __IO uint8_t FBYTE2;
+ union {
+ __IO uint8_t FBYTE1;
+ stc_mfs47_lin_fbyte1_field_t FBYTE1_f;
+ };
+ union {
+ __IO uint8_t FBYTE2;
+ stc_mfs47_lin_fbyte2_field_t FBYTE2_f;
+ };
};
};
}FM3_MFS47_LIN_TypeDef;
@@ -1263,11 +8607,23 @@ typedef struct /* I2C channel 4 registers */
typedef struct
{
- __IO uint8_t SMR;
- __IO uint8_t IBCR;
+ union {
+ __IO uint8_t SMR;
+ stc_mfs47_i2c_smr_field_t SMR_f;
+ };
+ union {
+ __IO uint8_t IBCR;
+ stc_mfs47_i2c_ibcr_field_t IBCR_f;
+ };
uint8_t RESERVED0[2];
- __IO uint8_t IBSR;
- __IO uint8_t SSR;
+ union {
+ __IO uint8_t IBSR;
+ stc_mfs47_i2c_ibsr_field_t IBSR_f;
+ };
+ union {
+ __IO uint8_t SSR;
+ stc_mfs47_i2c_ssr_field_t SSR_f;
+ };
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
@@ -1282,22 +8638,46 @@ typedef struct };
};
uint8_t RESERVED3[2];
- __IO uint8_t ISBA;
- __IO uint8_t ISMK;
+ union {
+ __IO uint8_t ISBA;
+ stc_mfs47_i2c_isba_field_t ISBA_f;
+ };
+ union {
+ __IO uint8_t ISMK;
+ stc_mfs47_i2c_ismk_field_t ISMK_f;
+ };
uint8_t RESERVED4[2];
union {
- __IO uint16_t FCR;
+ union {
+ __IO uint16_t FCR;
+ stc_mfs47_i2c_fcr_field_t FCR_f;
+ };
struct {
- __IO uint8_t FCR0;
- __IO uint8_t FCR1;
+ union {
+ __IO uint8_t FCR0;
+ stc_mfs47_i2c_fcr0_field_t FCR0_f;
+ };
+ union {
+ __IO uint8_t FCR1;
+ stc_mfs47_i2c_fcr1_field_t FCR1_f;
+ };
};
};
uint8_t RESERVED5[2];
union {
- __IO uint16_t FBYTE;
+ union {
+ __IO uint16_t FBYTE;
+ stc_mfs47_i2c_fbyte_field_t FBYTE_f;
+ };
struct {
- __IO uint8_t FBYTE1;
- __IO uint8_t FBYTE2;
+ union {
+ __IO uint8_t FBYTE1;
+ stc_mfs47_i2c_fbyte1_field_t FBYTE1_f;
+ };
+ union {
+ __IO uint8_t FBYTE2;
+ stc_mfs47_i2c_fbyte2_field_t FBYTE2_f;
+ };
};
};
}FM3_MFS47_I2C_TypeDef;
@@ -1308,7 +8688,10 @@ typedef struct /* CRC registers */
typedef struct
{
- __IO uint8_t CRCCR;
+ union {
+ __IO uint8_t CRCCR;
+ stc_crc_crccr_field_t CRCCR_f;
+ };
uint8_t RESERVED0[3];
__IO uint32_t CRCINIT;
union {
@@ -1339,13 +8722,28 @@ typedef struct /* Watch counter registers */
typedef struct
{
- __IO uint8_t WCRD;
- __IO uint8_t WCRL;
- __IO uint8_t WCCR;
+ union {
+ __IO uint8_t WCRD;
+ stc_wc_wcrd_field_t WCRD_f;
+ };
+ union {
+ __IO uint8_t WCRL;
+ stc_wc_wcrl_field_t WCRL_f;
+ };
+ union {
+ __IO uint8_t WCCR;
+ stc_wc_wccr_field_t WCCR_f;
+ };
uint8_t RESERVED0[13];
- __IO uint16_t CLK_SEL;
+ union {
+ __IO uint16_t CLK_SEL;
+ stc_wc_clk_sel_field_t CLK_SEL_f;
+ };
uint8_t RESERVED1[2];
- __IO uint8_t CLK_EN;
+ union {
+ __IO uint8_t CLK_EN;
+ stc_wc_clk_en_field_t CLK_EN_f;
+ };
}FM3_WC_TypeDef;
/******************************************************************************
@@ -1354,30 +8752,102 @@ typedef struct /* External bus interface registers */
typedef struct
{
- __IO uint32_t MODE0;
- __IO uint32_t MODE1;
- __IO uint32_t MODE2;
- __IO uint32_t MODE3;
- __IO uint32_t MODE4;
- __IO uint32_t MODE5;
- __IO uint32_t MODE6;
- __IO uint32_t MODE7;
- __IO uint32_t TIM0;
- __IO uint32_t TIM1;
- __IO uint32_t TIM2;
- __IO uint32_t TIM3;
- __IO uint32_t TIM4;
- __IO uint32_t TIM5;
- __IO uint32_t TIM6;
- __IO uint32_t TIM7;
- __IO uint32_t AREA0;
- __IO uint32_t AREA1;
- __IO uint32_t AREA2;
- __IO uint32_t AREA3;
- __IO uint32_t AREA4;
- __IO uint32_t AREA5;
- __IO uint32_t AREA6;
- __IO uint32_t AREA7;
+ union {
+ __IO uint32_t MODE0;
+ stc_exbus_mode0_field_t MODE0_f;
+ };
+ union {
+ __IO uint32_t MODE1;
+ stc_exbus_mode1_field_t MODE1_f;
+ };
+ union {
+ __IO uint32_t MODE2;
+ stc_exbus_mode2_field_t MODE2_f;
+ };
+ union {
+ __IO uint32_t MODE3;
+ stc_exbus_mode3_field_t MODE3_f;
+ };
+ union {
+ __IO uint32_t MODE4;
+ stc_exbus_mode4_field_t MODE4_f;
+ };
+ union {
+ __IO uint32_t MODE5;
+ stc_exbus_mode5_field_t MODE5_f;
+ };
+ union {
+ __IO uint32_t MODE6;
+ stc_exbus_mode6_field_t MODE6_f;
+ };
+ union {
+ __IO uint32_t MODE7;
+ stc_exbus_mode7_field_t MODE7_f;
+ };
+ union {
+ __IO uint32_t TIM0;
+ stc_exbus_tim0_field_t TIM0_f;
+ };
+ union {
+ __IO uint32_t TIM1;
+ stc_exbus_tim1_field_t TIM1_f;
+ };
+ union {
+ __IO uint32_t TIM2;
+ stc_exbus_tim2_field_t TIM2_f;
+ };
+ union {
+ __IO uint32_t TIM3;
+ stc_exbus_tim3_field_t TIM3_f;
+ };
+ union {
+ __IO uint32_t TIM4;
+ stc_exbus_tim4_field_t TIM4_f;
+ };
+ union {
+ __IO uint32_t TIM5;
+ stc_exbus_tim5_field_t TIM5_f;
+ };
+ union {
+ __IO uint32_t TIM6;
+ stc_exbus_tim6_field_t TIM6_f;
+ };
+ union {
+ __IO uint32_t TIM7;
+ stc_exbus_tim7_field_t TIM7_f;
+ };
+ union {
+ __IO uint32_t AREA0;
+ stc_exbus_area0_field_t AREA0_f;
+ };
+ union {
+ __IO uint32_t AREA1;
+ stc_exbus_area1_field_t AREA1_f;
+ };
+ union {
+ __IO uint32_t AREA2;
+ stc_exbus_area2_field_t AREA2_f;
+ };
+ union {
+ __IO uint32_t AREA3;
+ stc_exbus_area3_field_t AREA3_f;
+ };
+ union {
+ __IO uint32_t AREA4;
+ stc_exbus_area4_field_t AREA4_f;
+ };
+ union {
+ __IO uint32_t AREA5;
+ stc_exbus_area5_field_t AREA5_f;
+ };
+ union {
+ __IO uint32_t AREA6;
+ stc_exbus_area6_field_t AREA6_f;
+ };
+ union {
+ __IO uint32_t AREA7;
+ stc_exbus_area7_field_t AREA7_f;
+ };
}FM3_EXBUS_TypeDef;
/******************************************************************************
@@ -1387,80 +8857,185 @@ typedef struct typedef struct
{
union {
- __IO uint16_t HCNT;
+ union {
+ __IO uint16_t HCNT;
+ stc_usb_hcnt_field_t HCNT_f;
+ };
struct {
- __IO uint8_t HCNT0;
- __IO uint8_t HCNT1;
+ union {
+ __IO uint8_t HCNT0;
+ stc_usb_hcnt0_field_t HCNT0_f;
+ };
+ union {
+ __IO uint8_t HCNT1;
+ stc_usb_hcnt1_field_t HCNT1_f;
+ };
};
};
uint8_t RESERVED0[2];
- __IO uint8_t HIRQ;
- __IO uint8_t HERR;
+ union {
+ __IO uint8_t HIRQ;
+ stc_usb_hirq_field_t HIRQ_f;
+ };
+ union {
+ __IO uint8_t HERR;
+ stc_usb_herr_field_t HERR_f;
+ };
uint8_t RESERVED1[2];
- __IO uint8_t HSTATE;
- __IO uint8_t HFCOMP;
+ union {
+ __IO uint8_t HSTATE;
+ stc_usb_hstate_field_t HSTATE_f;
+ };
+ union {
+ __IO uint8_t HFCOMP;
+ stc_usb_hfcomp_field_t HFCOMP_f;
+ };
uint8_t RESERVED2[2];
union {
- __IO uint16_t HRTIMER;
+ union {
+ __IO uint16_t HRTIMER;
+ stc_usb_hrtimer_field_t HRTIMER_f;
+ };
struct {
- __IO uint8_t HRTIMER0;
- __IO uint8_t HRTIMER1;
+ union {
+ __IO uint8_t HRTIMER0;
+ stc_usb_hrtimer0_field_t HRTIMER0_f;
+ };
+ union {
+ __IO uint8_t HRTIMER1;
+ stc_usb_hrtimer1_field_t HRTIMER1_f;
+ };
};
};
uint8_t RESERVED3[2];
- __IO uint8_t HRTIMER2;
- __IO uint8_t HADR;
+ union {
+ __IO uint8_t HRTIMER2;
+ stc_usb_hrtimer2_field_t HRTIMER2_f;
+ };
+ union {
+ __IO uint8_t HADR;
+ stc_usb_hadr_field_t HADR_f;
+ };
uint8_t RESERVED4[2];
union {
- __IO uint16_t HEOF;
+ union {
+ __IO uint16_t HEOF;
+ stc_usb_heof_field_t HEOF_f;
+ };
struct {
- __IO uint8_t HEOF0;
- __IO uint8_t HEOF1;
+ union {
+ __IO uint8_t HEOF0;
+ stc_usb_heof0_field_t HEOF0_f;
+ };
+ union {
+ __IO uint8_t HEOF1;
+ stc_usb_heof1_field_t HEOF1_f;
+ };
};
};
uint8_t RESERVED5[2];
union {
- __IO uint16_t HFRAME;
+ union {
+ __IO uint16_t HFRAME;
+ stc_usb_hframe_field_t HFRAME_f;
+ };
struct {
- __IO uint8_t HFRAME0;
- __IO uint8_t HFRAME1;
+ union {
+ __IO uint8_t HFRAME0;
+ stc_usb_hframe0_field_t HFRAME0_f;
+ };
+ union {
+ __IO uint8_t HFRAME1;
+ stc_usb_hframe1_field_t HFRAME1_f;
+ };
};
};
uint8_t RESERVED6[2];
- __IO uint8_t HTOKEN;
+ union {
+ __IO uint8_t HTOKEN;
+ stc_usb_htoken_field_t HTOKEN_f;
+ };
uint8_t RESERVED7[3];
- __IO uint16_t UDCC;
+ union {
+ __IO uint16_t UDCC;
+ stc_usb_udcc_field_t UDCC_f;
+ };
uint8_t RESERVED8[2];
- __IO uint16_t EP0C;
+ union {
+ __IO uint16_t EP0C;
+ stc_usb_ep0c_field_t EP0C_f;
+ };
uint8_t RESERVED9[2];
- __IO uint16_t EP1C;
+ union {
+ __IO uint16_t EP1C;
+ stc_usb_ep1c_field_t EP1C_f;
+ };
uint8_t RESERVED10[2];
- __IO uint16_t EP2C;
+ union {
+ __IO uint16_t EP2C;
+ stc_usb_ep2c_field_t EP2C_f;
+ };
uint8_t RESERVED11[2];
- __IO uint16_t EP3C;
+ union {
+ __IO uint16_t EP3C;
+ stc_usb_ep3c_field_t EP3C_f;
+ };
uint8_t RESERVED12[2];
- __IO uint16_t EP4C;
+ union {
+ __IO uint16_t EP4C;
+ stc_usb_ep4c_field_t EP4C_f;
+ };
uint8_t RESERVED13[2];
- __IO uint16_t EP5C;
+ union {
+ __IO uint16_t EP5C;
+ stc_usb_ep5c_field_t EP5C_f;
+ };
uint8_t RESERVED14[2];
- __IO uint16_t TMSP;
+ union {
+ __IO uint16_t TMSP;
+ stc_usb_tmsp_field_t TMSP_f;
+ };
uint8_t RESERVED15[2];
- __IO uint8_t UDCS;
- __IO uint8_t UDCIE;
+ union {
+ __IO uint8_t UDCS;
+ stc_usb_udcs_field_t UDCS_f;
+ };
+ union {
+ __IO uint8_t UDCIE;
+ stc_usb_udcie_field_t UDCIE_f;
+ };
uint8_t RESERVED16[2];
- __IO uint16_t EP0IS;
+ union {
+ __IO uint16_t EP0IS;
+ stc_usb_ep0is_field_t EP0IS_f;
+ };
uint8_t RESERVED17[2];
- __IO uint16_t EP0OS;
+ union {
+ __IO uint16_t EP0OS;
+ stc_usb_ep0os_field_t EP0OS_f;
+ };
uint8_t RESERVED18[2];
- __IO uint16_t EP1S;
+ union {
+ __IO uint16_t EP1S;
+ stc_usb_ep1s_field_t EP1S_f;
+ };
uint8_t RESERVED19[2];
- __IO uint16_t EP2S;
+ union {
+ __IO uint16_t EP2S;
+ stc_usb_ep2s_field_t EP2S_f;
+ };
uint8_t RESERVED20[2];
__IO uint16_t EP3S;
uint8_t RESERVED21[2];
- __IO uint16_t EP4S;
+ union {
+ __IO uint16_t EP4S;
+ stc_usb_ep4s_field_t EP4S_f;
+ };
uint8_t RESERVED22[2];
- __IO uint16_t EP5S;
+ union {
+ __IO uint16_t EP5S;
+ stc_usb_ep5s_field_t EP5S_f;
+ };
uint8_t RESERVED23[2];
union {
__IO uint16_t EP0DT;
@@ -1517,38 +9092,89 @@ typedef struct /* DMA controller */
typedef struct
{
- __IO uint32_t DMACR;
+ union {
+ __IO uint32_t DMACR;
+ stc_dmac_dmacr_field_t DMACR_f;
+ };
uint8_t RESERVED0[12];
- __IO uint32_t DMACA0;
- __IO uint32_t DMACB0;
+ union {
+ __IO uint32_t DMACA0;
+ stc_dmac_dmaca0_field_t DMACA0_f;
+ };
+ union {
+ __IO uint32_t DMACB0;
+ stc_dmac_dmacb0_field_t DMACB0_f;
+ };
__IO uint32_t DMACSA0;
__IO uint32_t DMACDA0;
- __IO uint32_t DMACA1;
- __IO uint32_t DMACB1;
+ union {
+ __IO uint32_t DMACA1;
+ stc_dmac_dmaca1_field_t DMACA1_f;
+ };
+ union {
+ __IO uint32_t DMACB1;
+ stc_dmac_dmacb1_field_t DMACB1_f;
+ };
__IO uint32_t DMACSA1;
__IO uint32_t DMACDA1;
- __IO uint32_t DMACA2;
- __IO uint32_t DMACB2;
+ union {
+ __IO uint32_t DMACA2;
+ stc_dmac_dmaca2_field_t DMACA2_f;
+ };
+ union {
+ __IO uint32_t DMACB2;
+ stc_dmac_dmacb2_field_t DMACB2_f;
+ };
__IO uint32_t DMACSA2;
__IO uint32_t DMACDA2;
- __IO uint32_t DMACA3;
- __IO uint32_t DMACB3;
+ union {
+ __IO uint32_t DMACA3;
+ stc_dmac_dmaca3_field_t DMACA3_f;
+ };
+ union {
+ __IO uint32_t DMACB3;
+ stc_dmac_dmacb3_field_t DMACB3_f;
+ };
__IO uint32_t DMACSA3;
__IO uint32_t DMACDA3;
- __IO uint32_t DMACA4;
- __IO uint32_t DMACB4;
+ union {
+ __IO uint32_t DMACA4;
+ stc_dmac_dmaca4_field_t DMACA4_f;
+ };
+ union {
+ __IO uint32_t DMACB4;
+ stc_dmac_dmacb4_field_t DMACB4_f;
+ };
__IO uint32_t DMACSA4;
__IO uint32_t DMACDA4;
- __IO uint32_t DMACA5;
- __IO uint32_t DMACB5;
+ union {
+ __IO uint32_t DMACA5;
+ stc_dmac_dmaca5_field_t DMACA5_f;
+ };
+ union {
+ __IO uint32_t DMACB5;
+ stc_dmac_dmacb5_field_t DMACB5_f;
+ };
__IO uint32_t DMACSA5;
__IO uint32_t DMACDA5;
- __IO uint32_t DMACA6;
- __IO uint32_t DMACB6;
+ union {
+ __IO uint32_t DMACA6;
+ stc_dmac_dmaca6_field_t DMACA6_f;
+ };
+ union {
+ __IO uint32_t DMACB6;
+ stc_dmac_dmacb6_field_t DMACB6_f;
+ };
__IO uint32_t DMACSA6;
__IO uint32_t DMACDA6;
- __IO uint32_t DMACA7;
- __IO uint32_t DMACB7;
+ union {
+ __IO uint32_t DMACA7;
+ stc_dmac_dmaca7_field_t DMACA7_f;
+ };
+ union {
+ __IO uint32_t DMACB7;
+ stc_dmac_dmacb7_field_t DMACB7_f;
+ };
__IO uint32_t DMACSA7;
__IO uint32_t DMACDA7;
}FM3_DMAC_TypeDef;
@@ -1559,31 +9185,73 @@ typedef struct /* CAN channel 0 registers */
typedef struct
{
- __IO uint16_t CTRLR;
- __IO uint16_t STATR;
- __IO uint16_t ERRCNT;
- __IO uint16_t BTR;
- __IO uint16_t INTR;
- __IO uint16_t TESTR;
- __IO uint16_t BRPER;
+ union {
+ __IO uint16_t CTRLR;
+ stc_can_ctrlr_field_t CTRLR_f;
+ };
+ union {
+ __IO uint16_t STATR;
+ stc_can_statr_field_t STATR_f;
+ };
+ union {
+ __IO uint16_t ERRCNT;
+ stc_can_errcnt_field_t ERRCNT_f;
+ };
+ union {
+ __IO uint16_t BTR;
+ stc_can_btr_field_t BTR_f;
+ };
+ union {
+ __IO uint16_t INTR;
+ stc_can_intr_field_t INTR_f;
+ };
+ union {
+ __IO uint16_t TESTR;
+ stc_can_testr_field_t TESTR_f;
+ };
+ union {
+ __IO uint16_t BRPER;
+ stc_can_brper_field_t BRPER_f;
+ };
uint8_t RESERVED0[2];
- __IO uint16_t IF1CREQ;
- __IO uint16_t IF1CMSK;
union {
- __IO uint32_t IF1MSK;
+ __IO uint16_t IF1CREQ;
+ stc_can_if1creq_field_t IF1CREQ_f;
+ };
+ union {
+ __IO uint16_t IF1CMSK;
+ stc_can_if1cmsk_field_t IF1CMSK_f;
+ };
+ union {
+ union {
+ __IO uint32_t IF1MSK;
+ stc_can_if1msk_field_t IF1MSK_f;
+ };
struct {
__IO uint16_t IF1MSK1;
- __IO uint16_t IF1MSK2;
+ union {
+ __IO uint16_t IF1MSK2;
+ stc_can_if1msk2_field_t IF1MSK2_f;
+ };
};
};
union {
- __IO uint32_t IF1ARB;
+ union {
+ __IO uint32_t IF1ARB;
+ stc_can_if1arb_field_t IF1ARB_f;
+ };
struct {
__IO uint16_t IF1ARB1;
- __IO uint16_t IF1ARB2;
+ union {
+ __IO uint16_t IF1ARB2;
+ stc_can_if1arb2_field_t IF1ARB2_f;
+ };
};
};
- __IO uint16_t IF1MCTR;
+ union {
+ __IO uint16_t IF1MCTR;
+ stc_can_if1mctr_field_t IF1MCTR_f;
+ };
uint8_t RESERVED1[2];
union {
__IO uint32_t IF1DTA_L;
@@ -1615,23 +9283,41 @@ typedef struct };
};
uint8_t RESERVED3[8];
- __IO uint16_t IF2CREQ;
- __IO uint16_t IF2CMSK;
union {
- __IO uint32_t IF2MSK;
+ __IO uint16_t IF2CREQ;
+ stc_can_if2creq_field_t IF2CREQ_f;
+ };
+ union {
+ __IO uint16_t IF2CMSK;
+ stc_can_if2cmsk_field_t IF2CMSK_f;
+ };
+ union {
+ union {
+ __IO uint32_t IF2MSK;
+ stc_can_if2msk_field_t IF2MSK_f;
+ };
struct {
__IO uint16_t IF2MSK1;
- __IO uint16_t IF2MSK2;
+ union {
+ __IO uint16_t IF2MSK2;
+ stc_can_if2msk2_field_t IF2MSK2_f;
+ };
};
};
union {
__IO uint32_t IF2ARB;
struct {
__IO uint16_t IF2ARB1;
- __IO uint16_t IF2ARB2;
+ union {
+ __IO uint16_t IF2ARB2;
+ stc_can_if2arb2_field_t IF2ARB2_f;
+ };
};
};
- __IO uint16_t IF2MCTR;
+ union {
+ __IO uint16_t IF2MCTR;
+ stc_can_if2mctr_field_t IF2MCTR_f;
+ };
uint8_t RESERVED4[2];
union {
__IO uint32_t IF2DTA_L;
@@ -1664,34 +9350,67 @@ typedef struct };
uint8_t RESERVED6[24];
union {
- __IO uint32_t TREQR;
+ union {
+ __IO uint32_t TREQR;
+ stc_can_treqr_field_t TREQR_f;
+ };
struct {
- __IO uint16_t TREQR1;
- __IO uint16_t TREQR2;
+ union {
+ __IO uint16_t TREQR1;
+ stc_can_treqr1_field_t TREQR1_f;
+ };
+ union {
+ __IO uint16_t TREQR2;
+ stc_can_treqr2_field_t TREQR2_f;
+ };
};
};
uint8_t RESERVED7[12];
union {
- __IO uint32_t NEWDT;
+ union {
+ __IO uint32_t NEWDT;
+ stc_can_newdt_field_t NEWDT_f;
+ };
struct {
- __IO uint16_t NEWDT1;
+ union {
+ __IO uint16_t NEWDT1;
+ stc_can_newdt1_field_t NEWDT1_f;
+ };
__IO uint16_t NEWDT2;
};
};
uint8_t RESERVED8[12];
union {
- __IO uint32_t INTPND;
+ union {
+ __IO uint32_t INTPND;
+ stc_can_intpnd_field_t INTPND_f;
+ };
struct {
- __IO uint16_t INTPND1;
- __IO uint16_t INTPND2;
+ union {
+ __IO uint16_t INTPND1;
+ stc_can_intpnd1_field_t INTPND1_f;
+ };
+ union {
+ __IO uint16_t INTPND2;
+ stc_can_intpnd2_field_t INTPND2_f;
+ };
};
};
uint8_t RESERVED9[12];
union {
- __IO uint32_t MSGVAL;
+ union {
+ __IO uint32_t MSGVAL;
+ stc_can_msgval_field_t MSGVAL_f;
+ };
struct {
- __IO uint16_t MSGVAL1;
- __IO uint16_t MSGVAL2;
+ union {
+ __IO uint16_t MSGVAL1;
+ stc_can_msgval1_field_t MSGVAL1_f;
+ };
+ union {
+ __IO uint16_t MSGVAL2;
+ stc_can_msgval2_field_t MSGVAL2_f;
+ };
};
};
}FM3_CAN_TypeDef;
@@ -1810,7 +9529,7 @@ typedef struct /******************************************************************************
* Peripheral declaration
******************************************************************************/
-#define FM3_FLASH_IF ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE)
+#define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE)
#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE)
#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)
#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)
@@ -1924,6 +9643,7 @@ typedef struct #define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL))
#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL))
#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL))
+#define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL))
#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL))
#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL))
#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL))
@@ -1999,6 +9719,7 @@ typedef struct #define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL))
#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL))
#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL))
+#define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL))
#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL))
#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL))
#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL))
@@ -2257,8 +9978,8 @@ typedef struct #define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL))
#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL))
#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL))
-#define bFM3_MFT0_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42400F18UL))
-#define bFM3_MFT0_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42400F1CUL))
+#define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL))
#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL))
#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL))
#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL))
@@ -2267,8 +9988,8 @@ typedef struct #define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL))
#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL))
#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL))
-#define bFM3_MFT0_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42400F98UL))
-#define bFM3_MFT0_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42400F9CUL))
+#define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL))
#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL))
#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL))
@@ -2508,8 +10229,8 @@ typedef struct #define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL))
#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL))
#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL))
-#define bFM3_MFT1_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42420F18UL))
-#define bFM3_MFT1_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42420F1CUL))
+#define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL))
#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL))
#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL))
#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL))
@@ -2518,8 +10239,8 @@ typedef struct #define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL))
#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL))
#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL))
-#define bFM3_MFT1_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42420F98UL))
-#define bFM3_MFT1_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42420F9CUL))
+#define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL))
#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL))
#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL))
@@ -3896,6 +11617,11 @@ typedef struct #define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL))
#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL))
#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL))
+#define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL))
+#define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL))
+#define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL))
+#define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL))
+#define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL))
#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL))
#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL))
#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL))
@@ -3906,6 +11632,8 @@ typedef struct #define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL))
#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL))
#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL))
+#define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL))
+#define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL))
/* 12-bit ADC unit 1 registers */
#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL))
@@ -4214,6 +11942,11 @@ typedef struct #define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL))
#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL))
#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL))
+#define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL))
+#define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL))
+#define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL))
+#define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL))
+#define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL))
#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL))
#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL))
#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL))
@@ -4224,6 +11957,8 @@ typedef struct #define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL))
#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL))
#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL))
+#define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL))
+#define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL))
/* 12-bit ADC unit 2 registers */
#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL))
@@ -4532,6 +12267,11 @@ typedef struct #define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL))
#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL))
#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL))
+#define bFM3_ADC2_ADCT_CT3 *((volatile unsigned int*)(0x424E468CUL))
+#define bFM3_ADC2_ADCT_CT4 *((volatile unsigned int*)(0x424E4690UL))
+#define bFM3_ADC2_ADCT_CT5 *((volatile unsigned int*)(0x424E4694UL))
+#define bFM3_ADC2_ADCT_CT6 *((volatile unsigned int*)(0x424E4698UL))
+#define bFM3_ADC2_ADCT_CT7 *((volatile unsigned int*)(0x424E469CUL))
#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL))
#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL))
#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL))
@@ -4542,6 +12282,8 @@ typedef struct #define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL))
#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL))
#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL))
+#define bFM3_ADC2_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E4790UL))
+#define bFM3_ADC2_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E4794UL))
/* CR trimming registers */
#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL))
@@ -4824,6 +12566,7 @@ typedef struct #define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL))
#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL))
#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL))
#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL))
#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL))
#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL))
@@ -6398,14 +14141,14 @@ typedef struct #define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL))
#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL))
#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL))
-#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL))
/* UART LIN channel 4 registers */
#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL))
@@ -6489,14 +14232,14 @@ typedef struct #define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL))
#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL))
#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL))
-#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL))
-#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL))
-#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL))
-#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL))
-#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL))
-#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL))
-#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL))
-#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL))
/* I2C channel 4 registers */
#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL))
@@ -6600,14 +14343,14 @@ typedef struct #define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL))
#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL))
#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL))
-#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL))
-#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL))
-#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL))
-#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL))
-#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL))
-#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL))
-#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL))
-#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL))
/* UART asynchronous channel 5 registers */
#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL))
@@ -6783,14 +14526,14 @@ typedef struct #define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL))
#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL))
#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL))
-#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL))
/* UART LIN channel 5 registers */
#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL))
@@ -6874,14 +14617,14 @@ typedef struct #define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL))
#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL))
#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL))
-#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL))
-#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL))
-#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL))
-#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL))
-#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL))
-#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL))
-#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL))
-#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL))
/* I2C channel 5 registers */
#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL))
@@ -6985,14 +14728,14 @@ typedef struct #define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL))
#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL))
#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL))
-#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL))
-#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL))
-#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL))
-#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL))
-#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL))
-#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL))
-#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL))
-#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL))
/* UART asynchronous channel 6 registers */
#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL))
@@ -7168,14 +14911,14 @@ typedef struct #define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL))
#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL))
#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL))
-#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL))
/* UART LIN channel 6 registers */
#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL))
@@ -7259,14 +15002,14 @@ typedef struct #define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL))
#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL))
#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL))
-#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL))
-#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL))
-#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL))
-#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL))
-#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL))
-#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL))
-#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL))
-#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL))
/* I2C channel 6 registers */
#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL))
@@ -7370,14 +15113,14 @@ typedef struct #define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL))
#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL))
#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL))
-#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL))
-#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL))
-#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL))
-#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL))
-#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL))
-#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL))
-#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL))
-#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL))
/* UART asynchronous channel 7 registers */
#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL))
@@ -7553,14 +15296,14 @@ typedef struct #define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL))
#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL))
#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL))
-#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL))
/* UART LIN channel 7 registers */
#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL))
@@ -7644,14 +15387,14 @@ typedef struct #define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL))
#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL))
#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL))
-#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL))
-#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL))
-#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL))
-#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL))
-#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL))
-#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL))
-#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL))
-#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL))
/* I2C channel 7 registers */
#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL))
@@ -7755,14 +15498,14 @@ typedef struct #define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL))
#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL))
#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL))
-#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL))
-#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL))
-#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL))
-#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL))
-#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL))
-#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL))
-#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL))
-#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL))
/* CRC registers */
#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL))
@@ -8409,7 +16152,7 @@ typedef struct #define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL))
#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL))
#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL))
-#define bFM3_USB0_EP1C_PSK18 *((volatile unsigned int*)(0x42842520UL))
+#define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL))
#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL))
#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL))
#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL))
@@ -8519,6 +16262,7 @@ typedef struct #define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL))
#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL))
#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL))
+#define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL))
#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL))
#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL))
#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL))
diff --git a/bsp/mb9bf506r/CMSIS/system_mb9bf50x.h b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h index 4b4789d5df..481cfca627 100644 --- a/bsp/mb9bf506r/CMSIS/system_mb9bf50x.h +++ b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h @@ -30,42 +30,33 @@ /* */
/* (V1.5) */
/************************************************************************/
-
-#ifndef _SYSTEM_MB9BF50X_H_
-#define _SYSTEM_MB9BF50X_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
+ ******************************************************************************
+ ** \file mcu.h
+ **
+ ** Header File for device dependent includes
+ **
+ ** History:
+ ** 2011-05-19 V1.00 MWi first version
+ **
+ ******************************************************************************/
/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
+ ******************************************************************************
+ ** \brief MCU header file include
+ **
+ ******************************************************************************/
+#ifndef _MB9BF506R_H_
+ #include "mb9bf506r.h"
+#endif
-#ifdef __cplusplus
-}
+/**
+ ******************************************************************************
+ ** \brief MCU system start-up header file include
+ **
+ ******************************************************************************/
+#ifndef _SYSTEM_MB9BF50X_H_
+ #include "system_mb9bf50x.h"
#endif
-#endif /* __SYSTEM_MB9BF50X_H */
+
diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h new file mode 100644 index 0000000000..452b54b129 --- /dev/null +++ b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h @@ -0,0 +1,679 @@ +/************************************************************************/
+/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
+/* */
+/* The following software deliverable is intended for and must only be */
+/* used for reference and in an evaluation laboratory environment. */
+/* It is provided on an as-is basis without charge and is subject to */
+/* alterations. */
+/* It is the user's obligation to fully test the software in its */
+/* environment and to ensure proper functionality, qualification and */
+/* compliance with component specifications. */
+/* */
+/* In the event the software deliverable includes the use of open */
+/* source components, the provisions of the governing open source */
+/* license agreement shall apply with respect to such software */
+/* deliverable. */
+/* FSEU does not warrant that the deliverables do not infringe any */
+/* third party intellectual property right (IPR). In the event that */
+/* the deliverables infringe a third party IPR it is the sole */
+/* responsibility of the customer to obtain necessary licenses to */
+/* continue the usage of the deliverable. */
+/* */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not */
+/* limited to, warranties of merchantability and fitness for a */
+/* particular purpose for which the deliverable is not designated. */
+/* */
+/* To the maximum extent permitted by applicable law, FSEU's liability */
+/* is restricted to intentional misconduct and gross negligence. */
+/* FSEU is not liable for consequential damages. */
+/* */
+/* (V1.5) */
+/************************************************************************/
+/** \file system_mb9bf50x.h
+ **
+ ** Headerfile for FM3 system parameters
+ **
+ ** User clock definitions can be done for the following clock settings:
+ ** - CLOCK_SETUP : Execute the clock settings form the settings below in
+ ** SystemInit()
+ ** - __CLKMO : External clock frequency for main oscillion
+ ** - __CLKSO : External clock frequency for sub oscillion
+ ** - SCM_CTL : System Clock Mode Control Register
+ ** - BSC_PSR : Base Clock Prescaler Register
+ ** - APBC0_PSR : APB0 Prescaler Register
+ ** - APBC1_PSR : APB1 Prescaler Register
+ ** - APBC2_PSR : APB2 Prescaler Register
+ ** - SWC_PSR : Software Watchdog Clock Prescaler Register
+ ** - TTC_PSR : Trace Clock Prescaler Register
+ ** - CSW_TMR : Clock Stabilization Wait Time Register
+ ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register
+ ** - PLL_CTL1 : PLL Control Register 1
+ ** - PLL_CTL2 : PLL Control Register 2
+ **
+ ** The register settings are check for correct values of reserved bits.
+ ** Otherwise a preprocessor error is output and stops the build process.
+ ** Furthermore the 'master clock' is retrieved from the register settings
+ ** and the system clock (HCLK) is calculated from the Base Clock Prescaler
+ ** Register (BSC_PSR). This value is used for the global CMSIS variable
+ ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is
+ ** is checked. Note that not all possible wrong setting are checked! The
+ ** user has to take care to fulfill the settings stated in the according
+ ** device's data sheet!
+ **
+ ** User definition for Hardware Watchdog:
+ ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit()
+ **
+ ** User definition for CR Trimming:
+ ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit()
+ **
+ ** History:
+ ** 2011-05-16 V1.0 MWi original version
+ ** 2011-12-20 V1.1 EH corresponded to C++
+ *****************************************************************************/
+
+#ifndef _SYSTEM_MB9BF50X_H_
+#define _SYSTEM_MB9BF50X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/* Global pre-processor symbols/macros ('define') */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* START OF USER SETTINGS HERE */
+/* =========================== */
+/* */
+/* All lines with '<<<' can be set by user. */
+/* */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Clock Setup Enable
+ ** <i>(USER SETTING)</i>
+ **
+ ** - 0 = No clock setup done by system_mb9xfxxx.c
+ ** - 1 = Clock setup done by system_mb9xfxxx.c
+ ******************************************************************************/
+#define CLOCK_SETUP 1 // <<< Define clock setup here
+
+/**
+ ******************************************************************************
+ ** \brief External Main Clock Frequency (in Hz, [value]UL)
+ ** <i>(USER SETTING)</i>
+ ******************************************************************************/
+#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief External Sub Clock Frequency (in Hz, [value]UL)
+ ** <i>(USER SETTING)</i>
+ ******************************************************************************/
+#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief System Clock Mode Control Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** SCM_CTL
+ **
+ ** Bit#7-5 : RCS[2:0]
+ ** - 0 = Internal high-speed CR oscillation (default)
+ ** - 1 = Main oscillation clock
+ ** - 2 = PLL oscillation clock
+ ** - 3 = (not allowed)
+ ** - 4 = Internal low-speed CR oscillation
+ ** - 5 = Sub clock oscillation
+ ** - 6 = (not allowed)
+ ** - 7 = (not allowed)
+ **
+ ** Bit#4 : PLLE
+ ** - 0 = Disable PLL (default)
+ ** - 1 = Enable PLL
+ **
+ ** Bit#3 : SOSCE
+ ** - 0 = Disable sub oscillation (default)
+ ** - 1 = Enable sub oscillation
+ **
+ ** Bit#2 : (reserved)
+ **
+ ** Bit#1 : MOSCE
+ ** - 0 = Disable main oscillation (default)
+ ** - 1 = Enable main oscillation
+ **
+ ** Bit#0 : (reserved)
+ ******************************************************************************/
+#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here
+
+/**
+ ******************************************************************************
+ ** \brief Base Clock Prescaler Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** BSC_PSR
+ **
+ ** Bit#7-3 : (reserved)
+ **
+ ** Bit#2-0 : BSR[2:0]
+ ** - 0 = HCLK = Master Clock
+ ** - 1 = HCLK = Master Clock / 2
+ ** - 2 = HCLK = Master Clock / 3
+ ** - 3 = HCLK = Master Clock / 4
+ ** - 4 = HCLK = Master Clock / 6
+ ** - 5 = HCLK = Master Clock / 8
+ ** - 6 = HCLK = Master Clock / 16
+ ** - 7 = (reserved)
+ ******************************************************************************/
+#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief APB0 Prescaler Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** APBC0_PSR
+ **
+ ** Bit#7-2 : (reserved)
+ **
+ ** Bit#1-0 : BSR[2:0]
+ ** - 0 = PCLK0 = HCLK
+ ** - 1 = PCLK0 = HCLK / 2
+ ** - 2 = PCLK0 = HCLK / 4
+ ** - 3 = PCLK0 = HCLK / 8
+ ******************************************************************************/
+#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief APB1 Prescaler Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** APBC1_PSR
+ **
+ ** Bit#7 : APBC1EN
+ ** - 0 = Disable PCLK1 output
+ ** - 1 = Enables PCLK1 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ **
+ ** Bit#4 : APBC1RST
+ ** - 0 = APB1 bus reset, inactive (default)
+ ** - 1 = APB1 bus reset, active
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC1[2:0]
+ ** - 0 = PCLK1 = HCLK
+ ** - 1 = PCLK1 = HCLK / 2
+ ** - 2 = PCLK1 = HCLK / 4
+ ** - 3 = PCLK1 = HCLK / 8
+ ******************************************************************************/
+#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief APB2 Prescaler Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** APBC2_PSR
+ **
+ ** Bit#7 : APBC2EN
+ ** - 0 = Disable PCLK2 output
+ ** - 1 = Enables PCLK2 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ **
+ ** Bit#4 : APBC2RST
+ ** - 0 = APB2 bus reset, inactive (default)
+ ** - 1 = APB2 bus reset, active
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC2[1:0]
+ ** - 0 = PCLK2 = HCLK
+ ** - 1 = PCLK2 = HCLK / 2
+ ** - 2 = PCLK2 = HCLK / 4
+ ** - 3 = PCLK2 = HCLK / 8
+ ******************************************************************************/
+#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Software Watchdog Clock Prescaler Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** SWC_PSR
+ **
+ ** Bit#7 : TESTB
+ ** - 0 = (not allowed)
+ ** - 1 = (always write "1" to this bit)
+ **
+ ** Bit#6-2 : (reserved)
+ **
+ ** Bit#1-0 : SWDS[2:0]
+ ** - 0 = SWDGOGCLK = PCLK0
+ ** - 1 = SWDGOGCLK = PCLK0 / 2
+ ** - 2 = SWDGOGCLK = PCLK0 / 4
+ ** - 3 = SWDGOGCLK = PCLK0 / 8
+ ******************************************************************************/
+#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Trace Clock Prescaler Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** TTC_PSR
+ **
+ ** Bit#7-1 : (reserved)
+ **
+ ** Bit#0 : TTC
+ ** - 0 = TPIUCLK = HCLK
+ ** - 1 = TPIUCLK = HCLK / 2
+ ******************************************************************************/
+#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Clock Stabilization Wait Time Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** CSW_TMR
+ **
+ ** Bit#7 : (reserved)
+ **
+ ** Bit#6-4 : SOWT[2:0]
+ ** - 0 = ~10.3 ms (default)
+ ** - 1 = ~20.5 ms
+ ** - 2 = ~41 ms
+ ** - 3 = ~82 ms
+ ** - 4 = ~164 ms
+ ** - 5 = ~327 ms
+ ** - 6 = ~655 ms
+ ** - 7 = ~1.31 s
+ **
+ ** Bit#3-0 : MOWT[3:0]
+ ** - 0 = ~500 ns (default)
+ ** - 1 = ~8 us
+ ** - 2 = ~16 us
+ ** - 3 = ~32 us
+ ** - 4 = ~64 us
+ ** - 5 = ~128 us
+ ** - 6 = ~256 us
+ ** - 7 = ~512 us
+ ** - 8 = ~1.0 ms
+ ** - 9 = ~2.0 ms
+ ** - 10 = ~4.0 ms
+ ** - 11 = ~8.0 ms
+ ** - 12 = ~33.0 ms
+ ** - 13 = ~131 ms
+ ** - 14 = ~524 ms
+ ** - 15 = ~2.0 s
+ ******************************************************************************/
+#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Clock Stabilization Wait Time Setup Register value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** PSW_TMR
+ **
+ ** Bit#7-5 : (reserved)
+ **
+ ** Bit#4 : PINC
+ ** - 0 = Selects CLKMO (main oscillation) (default)
+ ** - 1 = (setting diabled)
+ **
+ ** Bit#3 : (reserved)
+ **
+ ** Bit#2-0 : POWT[2:0]
+ ** - 0 = ~128 us (default)
+ ** - 1 = ~256 us
+ ** - 2 = ~512 us
+ ** - 3 = ~1.02 ms
+ ** - 4 = ~2.05 ms
+ ** - 5 = ~4.10 ms
+ ** - 6 = ~8.20 ms
+ ** - 7 = ~16.40 ms
+ ******************************************************************************/
+#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 1 value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** PLL_CTL1
+ **
+ ** Bit#7-4 : PLLK[3:0]
+ ** - 0 = Division(PLLK) = 1/1 (default)
+ ** - 1 = Division(PLLK) = 1/2
+ ** - 2 = Division(PLLK) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLK) = 1/16
+ **
+ ** Bit#3-0 : PLLM[3:0]
+ ** - 0 = Division(PLLM) = 1/1 (default)
+ ** - 1 = Division(PLLM) = 1/2
+ ** - 2 = Division(PLLM) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLM) = 1/16
+ ******************************************************************************/
+#define PLL_CTL1_Val 0x00000000 // <<< Define PLL_CTL1 here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 2 value definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** PLL_CTL2
+ **
+ ** Bit#7-6 : (reserved)
+ **
+ ** Bit#5-0 : PLLN[5:0]
+ ** - 0 = Division(PLLN) = 1/1 (default)
+ ** - 1 = Division(PLLN) = 1/2
+ ** - 2 = Division(PLLN) = 1/3
+ ** - . . .
+ ** - 63 = Division(PLLN) = 1/64
+ ******************************************************************************/
+#define PLL_CTL2_Val 0x00000013 // <<< Define PLL_CTL2 here
+
+/**
+ ******************************************************************************
+ ** \brief Hardware Watchdog disable definition
+ ** <i>(USER SETTING)</i>
+ **
+ ** - 0 = Hardware Watchdog enable
+ ** - 1 = Hardware Watchdog disable
+ ******************************************************************************/
+#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here
+
+/**
+ ******************************************************************************
+ ** \brief Trimming CR
+ ** <i>(USER SETTING)</i>
+ **
+ ** - 0 = CR is not trimmed at startup
+ ** - 1 = CR is trimmed at startup
+ ******************************************************************************/
+#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here
+
+
+/******************************************************************************/
+/* */
+/* END OF USER SETTINGS HERE */
+/* ========================= */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Device dependent System Clock absolute maximum ranges */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL)
+ ** <i>(USER SETTING)</i>
+ ******************************************************************************/
+#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */
+
+/**
+ ******************************************************************************
+ ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL)
+ ** <i>(USER SETTING)</i>
+ ******************************************************************************/
+#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL)
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __CLKMOMIN ( 4000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Maximum Main Clock frequency using external clock
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __CLKMOMAX ( 48000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Sub Clock frequency
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __CLKSOMIN ( 32000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Maximum Sub Clock frequency using external clock
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __CLKSOMAX ( 100000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL input frequency
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __PLLCLKINMIN ( 4000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL input frequency
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __PLLCLKINMAX ( 30000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL oscillation frequency
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __PLLCLKMIN ( 60000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL oscillation frequency
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __PLLCLKMAX (120000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum System Clock frequency (HCLK)
+ ** <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/
+#define __HCLKMAX ( 80000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking range (clock settings)
+ ******************************************************************************/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking bits with mask (clock settings)
+ ******************************************************************************/
+#define CHECK_RSVD(val, mask) (val & mask)
+
+
+/******************************************************************************/
+/* Check register settings */
+/******************************************************************************/
+#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA))
+ #error "SCM_CTL: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
+ #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
+#endif
+
+#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F))
+ #error "CSW_TMR: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */
+ #if (CHECK_RSVD((PSW_TMR_val), ~0x00000007))
+ #error "PSW_TMR: Invalid values of reserved bits!"
+ #endif
+
+ #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
+ #error "PLL_CTL1: Invalid values of reserved bits!"
+ #endif
+
+ #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F))
+ #error "PLL_CTL2: Invalid values of reserved bits!"
+ #endif
+#endif
+
+#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007))
+ #error "BSC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003))
+ #error "APBC0_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083))
+ #error "APBC1_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083))
+ #error "APBC2_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003))
+ #error "SWC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001))
+ #error "TTC_PSR: Invalid values of reserved bits!"
+#endif
+
+/******************************************************************************/
+/* Define clocks with checking settings */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL K factor from settings
+ ******************************************************************************/
+#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL N factor from settings
+ ******************************************************************************/
+#define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL M factor from settings
+ ******************************************************************************/
+#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL output frequency from settings
+ ******************************************************************************/
+#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK)
+
+/******************************************************************************/
+/* Determine core clock frequency according to settings */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Define Master Clock from settings
+ ******************************************************************************/
+#if (((SCM_CTL_Val >> 5) & 0x07) == 0)
+ #define __MASTERCLK (__CLKHC)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
+ #define __MASTERCLK (__CLKMO)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
+ #define __MASTERCLK (__PLLCLK)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
+ #define __MASTERCLK (__CLKLC)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
+ #define __MASTERCLK (__CLKSO)
+#else
+ #define __MASTERCLK (0UL)
+#endif
+
+/**
+ ******************************************************************************
+ ** \brief Define System Clock Frequency (Core Clock) from settings
+ ******************************************************************************/
+#if ((BSC_PSR_Val & 0x07) == 0)
+ #define __HCLK (__MASTERCLK / 1)
+#elif ((BSC_PSR_Val & 0x07) == 1)
+ #define __HCLK (__MASTERCLK / 2)
+#elif ((BSC_PSR_Val & 0x07) == 2)
+ #define __HCLK (__MASTERCLK / 3)
+#elif ((BSC_PSR_Val & 0x07) == 3)
+ #define __HCLK (__MASTERCLK / 4)
+#elif ((BSC_PSR_Val & 0x07) == 4)
+ #define __HCLK (__MASTERCLK / 6)
+#elif ((BSC_PSR_Val & 0x07) == 5)
+ #define __HCLK (__MASTERCLK / 8)
+#elif ((BSC_PSR_Val & 0x07) == 6)
+ #define __HCLK (__MASTERCLK /16)
+#else
+ #define __HCLK (0UL)
+#endif
+
+/******************************************************************************/
+/* HCLK range check */
+/******************************************************************************/
+#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0)
+ #error "Main Oscillator Clock (CLKMO) out of range!"
+#endif
+
+#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0)
+ #error "Sub Oscillator Clock (CLKMO) out of range!"
+#endif
+
+#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0)
+ #error "PLL input frequency out of range!"
+#endif
+
+#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0)
+ #error "PLL oscillation frequency out of range!"
+#endif
+
+#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0)
+ #error "System Clock (HCLK) out of range!"
+#endif
+
+/******************************************************************************/
+/* Global function prototypes ('extern', definition in C source) */
+/******************************************************************************/
+
+extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
+
+extern void SystemInit (void); // Initialize the system
+
+extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_MB9BF50X_H */
diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S new file mode 100644 index 0000000000..bdfa296352 --- /dev/null +++ b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S @@ -0,0 +1,327 @@ +;/************************************************************************/
+;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
+;/* */
+;/* The following software deliverable is intended for and must only be */
+;/* used for reference and in an evaluation laboratory environment. */
+;/* It is provided on an as-is basis without charge and is subject to */
+;/* alterations. */
+;/* It is the user's obligation to fully test the software in its */
+;/* environment and to ensure proper functionality, qualification and */
+;/* compliance with component specifications. */
+;/* */
+;/* In the event the software deliverable includes the use of open */
+;/* source components, the provisions of the governing open source */
+;/* license agreement shall apply with respect to such software */
+;/* deliverable. */
+;/* FSEU does not warrant that the deliverables do not infringe any */
+;/* third party intellectual property right (IPR). In the event that */
+;/* the deliverables infringe a third party IPR it is the sole */
+;/* responsibility of the customer to obtain necessary licenses to */
+;/* continue the usage of the deliverable. */
+;/* */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not */
+;/* limited to, warranties of merchantability and fitness for a */
+;/* particular purpose for which the deliverable is not designated. */
+;/* */
+;/* To the maximum extent permitted by applicable law, FSEU's liability */
+;/* is restricted to intentional misconduct and gross negligence. */
+;/* FSEU is not liable for consequential damages. */
+;/* */
+;/* (V1.5) */
+;/************************************************************************/
+;/* Startup for ARM */
+;/* Version V1.02 */
+;/* Date 2011-01-12 */
+;/* Target-mcu MB9B5xx */
+;/************************************************************************/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ DCD CSV_Handler ; 0: Clock Super Visor
+ DCD SWDT_Handler ; 1: Software Watchdog Timer
+ DCD LVD_Handler ; 2: Low Voltage Detector
+ DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
+ DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
+ DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
+ DCD DT_Handler ; 6: Dual Timer / Quad Decoder
+ DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
+ DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
+ DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
+ DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
+ DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
+ DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
+ DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
+ DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
+ DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
+ DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
+ DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
+ DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
+ DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
+ DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
+ DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
+ DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
+ DCD PPG_Handler ; 23: PPG
+ DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
+ DCD ADC0_IRQHandler ; 25: ADC0
+ DCD ADC1_IRQHandler ; 26: ADC1
+ DCD ADC2_IRQHandler ; 27: ADC2
+ DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
+ DCD MFT_IPC_IRQHandler ; 29: Input Capture
+ DCD MFT_OPC_IRQHandler ; 30: Output Compare
+ DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
+ DCD CAN0_IRQHandler ; 32: CAN ch.0
+ DCD CAN1_IRQHandler ; 33: CAN ch.1
+ DCD USBF_Handler ; 34: USB Function
+ DCD USB_Handler ; 35: USB Function / USB HOST
+ DCD DummyHandler ; 36: Reserved
+ DCD DummyHandler ; 37: Reserved
+ DCD DMAC0_Handler ; 38: DMAC ch.0
+ DCD DMAC1_Handler ; 39: DMAC ch.1
+ DCD DMAC2_Handler ; 40: DMAC ch.2
+ DCD DMAC3_Handler ; 41: DMAC ch.3
+ DCD DMAC4_Handler ; 42: DMAC ch.4
+ DCD DMAC5_Handler ; 43: DMAC ch.5
+ DCD DMAC6_Handler ; 44: DMAC ch.6
+ DCD DMAC7_Handler ; 45: DMAC ch.7
+ DCD DummyHandler ; 46: Reserved
+ DCD DummyHandler ; 47: Reserved
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT CSV_Handler [WEAK]
+ EXPORT SWDT_Handler [WEAK]
+ EXPORT LVD_Handler [WEAK]
+ EXPORT MFT_WG_IRQHandler [WEAK]
+ EXPORT INT0_7_Handler [WEAK]
+ EXPORT INT8_15_Handler [WEAK]
+ EXPORT DT_Handler [WEAK]
+ EXPORT MFS0RX_IRQHandler [WEAK]
+ EXPORT MFS0TX_IRQHandler [WEAK]
+ EXPORT MFS1RX_IRQHandler [WEAK]
+ EXPORT MFS1TX_IRQHandler [WEAK]
+ EXPORT MFS2RX_IRQHandler [WEAK]
+ EXPORT MFS2TX_IRQHandler [WEAK]
+ EXPORT MFS3RX_IRQHandler [WEAK]
+ EXPORT MFS3TX_IRQHandler [WEAK]
+ EXPORT MFS4RX_IRQHandler [WEAK]
+ EXPORT MFS4TX_IRQHandler [WEAK]
+ EXPORT MFS5RX_IRQHandler [WEAK]
+ EXPORT MFS5TX_IRQHandler [WEAK]
+ EXPORT MFS6RX_IRQHandler [WEAK]
+ EXPORT MFS6TX_IRQHandler [WEAK]
+ EXPORT MFS7RX_IRQHandler [WEAK]
+ EXPORT MFS7TX_IRQHandler [WEAK]
+ EXPORT PPG_Handler [WEAK]
+ EXPORT TIM_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT ADC2_IRQHandler [WEAK]
+ EXPORT MFT_FRT_IRQHandler [WEAK]
+ EXPORT MFT_IPC_IRQHandler [WEAK]
+ EXPORT MFT_OPC_IRQHandler [WEAK]
+ EXPORT BT_IRQHandler [WEAK]
+ EXPORT CAN0_IRQHandler [WEAK]
+ EXPORT CAN1_IRQHandler [WEAK]
+ EXPORT USBF_Handler [WEAK]
+ EXPORT USB_Handler [WEAK]
+ EXPORT DMAC0_Handler [WEAK]
+ EXPORT DMAC1_Handler [WEAK]
+ EXPORT DMAC2_Handler [WEAK]
+ EXPORT DMAC3_Handler [WEAK]
+ EXPORT DMAC4_Handler [WEAK]
+ EXPORT DMAC5_Handler [WEAK]
+ EXPORT DMAC6_Handler [WEAK]
+ EXPORT DMAC7_Handler [WEAK]
+ EXPORT DummyHandler [WEAK]
+
+CSV_Handler
+SWDT_Handler
+LVD_Handler
+MFT_WG_IRQHandler
+INT0_7_Handler
+INT8_15_Handler
+DT_Handler
+MFS0RX_IRQHandler
+MFS0TX_IRQHandler
+MFS1RX_IRQHandler
+MFS1TX_IRQHandler
+MFS2RX_IRQHandler
+MFS2TX_IRQHandler
+MFS3RX_IRQHandler
+MFS3TX_IRQHandler
+MFS4RX_IRQHandler
+MFS4TX_IRQHandler
+MFS5RX_IRQHandler
+MFS5TX_IRQHandler
+MFS6RX_IRQHandler
+MFS6TX_IRQHandler
+MFS7RX_IRQHandler
+MFS7TX_IRQHandler
+PPG_Handler
+TIM_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+ADC2_IRQHandler
+MFT_FRT_IRQHandler
+MFT_IPC_IRQHandler
+MFT_OPC_IRQHandler
+BT_IRQHandler
+CAN0_IRQHandler
+CAN1_IRQHandler
+USBF_Handler
+USB_Handler
+DMAC0_Handler
+DMAC1_Handler
+DMAC2_Handler
+DMAC3_Handler
+DMAC4_Handler
+DMAC5_Handler
+DMAC6_Handler
+DMAC7_Handler
+DummyHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S new file mode 100644 index 0000000000..9f137532b3 --- /dev/null +++ b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S @@ -0,0 +1,288 @@ +/**************************************************************************//**
+ * @file startup_<Device>.s
+ * @brief CMSIS Cortex-M# Core Device Startup File for
+ * Device <Device>
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note Version CodeSourcery Sourcery G++ Lite (with CS3)
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+/*
+// <h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Stack_Size, 0x00000400
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+// <h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Heap_Size, 0x00000100
+
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack /* Top of Stack */
+ .long __cs3_reset /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+/* ToDo: Add here the vectors for the device specific external interrupts handler */
+ .long CSV_Handler /* 0: Clock Super Visor */
+ .long SWDT_Handler /* 1: Software Watchdog Timer */
+ .long LVD_Handler /* 2: Low Voltage Detector */
+ .long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */
+ .long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */
+ .long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */
+ .long DT_Handler /* 6: Dual Timer / Quad Decoder */
+ .long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */
+ .long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */
+ .long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */
+ .long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */
+ .long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */
+ .long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */
+ .long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */
+ .long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */
+ .long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */
+ .long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */
+ .long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */
+ .long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */
+ .long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */
+ .long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */
+ .long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */
+ .long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */
+ .long PPG_Handler /* 23: PPG */
+ .long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */
+ .long ADC0_IRQHandler /* 25: ADC0 */
+ .long ADC1_IRQHandler /* 26: ADC1 */
+ .long ADC2_IRQHandler /* 27: ADC2 */
+ .long MFT_FRT_IRQHandler /* 28: Free-run Timer */
+ .long MFT_IPC_IRQHandler /* 29: Input Capture */
+ .long MFT_OPC_IRQHandler /* 30: Output Compare */
+ .long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */
+ .long CAN0_IRQHandler /* 32: CAN ch.0 */
+ .long CAN1_IRQHandler /* 33: CAN ch.1 */
+ .long USBF_Handler /* 34: USB Function */
+ .long USB_Handler /* 35: USB Function / USB HOST */
+ .long RESERVED_1_IRQHandler /* 36: Reserved */
+ .long RESERVED_2_IRQHandler /* 37: Reserved */
+ .long DMAC0_Handler /* 38: DMAC ch.0 */
+ .long DMAC1_Handler /* 39: DMAC ch.1 */
+ .long DMAC2_Handler /* 40: DMAC ch.2 */
+ .long DMAC3_Handler /* 41: DMAC ch.3 */
+ .long DMAC4_Handler /* 42: DMAC ch.4 */
+ .long DMAC5_Handler /* 43: DMAC ch.5 */
+ .long DMAC6_Handler /* 44: DMAC ch.6 */
+ .long DMAC7_Handler /* 45: DMAC ch.7 */
+ .long RESERVED_3_IRQHandler /* 46: Reserved */
+ .long RESERVED_4_IRQHandler /* 47: Reserved */
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+ .thumb
+
+
+/* Reset Handler */
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0,=_start
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+/* Exception Handlers */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak MemManage_Handler
+ .type MemManage_Handler, %function
+MemManage_Handler:
+ B .
+ .size MemManage_Handler, . - MemManage_Handler
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ B .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+/* ToDo: Add here the export definition for the device specific external interrupts handler */
+/* ToDo: Add here the names for the device specific external interrupts handler */
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ CSV_Handler /* 0: Clock Super Visor */
+ IRQ SWDT_Handler /* 1: Software Watchdog Timer */
+ IRQ LVD_Handler /* 2: Low Voltage Detector */
+ IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */
+ IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */
+ IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */
+ IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */
+ IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */
+ IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */
+ IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */
+ IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */
+ IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */
+ IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */
+ IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */
+ IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */
+ IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */
+ IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */
+ IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */
+ IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */
+ IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */
+ IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */
+ IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */
+ IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */
+ IRQ PPG_Handler /* 23: PPG */
+ IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */
+ IRQ ADC0_IRQHandler /* 25: ADC0 */
+ IRQ ADC1_IRQHandler /* 26: ADC1 */
+ IRQ ADC2_IRQHandler /* 27: ADC2 */
+ IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */
+ IRQ MFT_IPC_IRQHandler /* 29: Input Capture */
+ IRQ MFT_OPC_IRQHandler /* 30: Output Compare */
+ IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */
+ IRQ CAN0_IRQHandler /* 32: CAN ch.0 */
+ IRQ CAN1_IRQHandler /* 33: CAN ch.1 */
+ IRQ USBF_Handler /* 34: USB Function */
+ IRQ USB_Handler /* 35: USB Function / USB HOST */
+ IRQ RESERVED_1_IRQHandler /* 36: Reserved */
+ IRQ RESERVED_2_IRQHandler /* 37: Reserved */
+ IRQ DMAC0_Handler /* 38: DMAC ch.0 */
+ IRQ DMAC1_Handler /* 39: DMAC ch.1 */
+ IRQ DMAC2_Handler /* 40: DMAC ch.2 */
+ IRQ DMAC3_Handler /* 41: DMAC ch.3 */
+ IRQ DMAC4_Handler /* 42: DMAC ch.4 */
+ IRQ DMAC5_Handler /* 43: DMAC ch.5 */
+ IRQ DMAC6_Handler /* 44: DMAC ch.6 */
+ IRQ DMAC7_Handler /* 45: DMAC ch.7 */
+ IRQ RESERVED_3_IRQHandler /* 46: Reserved */
+ IRQ RESERVED_4_IRQHandler /* 47: Reserved */
+
+ .end
diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S new file mode 100644 index 0000000000..ebbbff95b0 --- /dev/null +++ b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S @@ -0,0 +1,402 @@ +;/************************************************************************/
+;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
+;/* */
+;/* The following software deliverable is intended for and must only be */
+;/* used for reference and in an evaluation laboratory environment. */
+;/* It is provided on an as-is basis without charge and is subject to */
+;/* alterations. */
+;/* It is the user's obligation to fully test the software in its */
+;/* environment and to ensure proper functionality, qualification and */
+;/* compliance with component specifications. */
+;/* */
+;/* In the event the software deliverable includes the use of open */
+;/* source components, the provisions of the governing open source */
+;/* license agreement shall apply with respect to such software */
+;/* deliverable. */
+;/* FSEU does not warrant that the deliverables do not infringe any */
+;/* third party intellectual property right (IPR). In the event that */
+;/* the deliverables infringe a third party IPR it is the sole */
+;/* responsibility of the customer to obtain necessary licenses to */
+;/* continue the usage of the deliverable. */
+;/* */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not */
+;/* limited to, warranties of merchantability and fitness for a */
+;/* particular purpose for which the deliverable is not designated. */
+;/* */
+;/* To the maximum extent permitted by applicable law, FSEU's liability */
+;/* is restricted to intentional misconduct and gross negligence. */
+;/* FSEU is not liable for consequential damages. */
+;/* */
+;/* (V1.5) */
+;/************************************************************************/
+;/* Startup for IAR */
+;/* Version V1.02 */
+;/* Date 2011-01-05 */
+;/* Target-mcu MB9B5xx */
+;/************************************************************************/
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset
+ DCD NMI_Handler ; NMI
+ DCD HardFault_Handler ; Hard Fault
+ DCD MemManage_Handler ; MPU Fault
+ DCD BusFault_Handler ; Bus Fault
+ DCD UsageFault_Handler ; Usage Fault
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall
+ DCD DebugMon_Handler ; Debug Monitor
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV
+ DCD SysTick_Handler ; SysTick
+
+ DCD CSV_Handler ; 0: Clock Super Visor
+ DCD SWDT_Handler ; 1: Software Watchdog Timer
+ DCD LVD_Handler ; 2: Low Voltage Detector
+ DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
+ DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
+ DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
+ DCD DT_Handler ; 6: Dual Timer / Quad Decoder
+ DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
+ DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
+ DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
+ DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
+ DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
+ DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
+ DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
+ DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
+ DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
+ DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
+ DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
+ DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
+ DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
+ DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
+ DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
+ DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
+ DCD PPG_Handler ; 23: PPG
+ DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
+ DCD ADC0_IRQHandler ; 25: ADC0
+ DCD ADC1_IRQHandler ; 26: ADC1
+ DCD ADC2_IRQHandler ; 27: ADC2
+ DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
+ DCD MFT_IPC_IRQHandler ; 29: Input Capture
+ DCD MFT_OPC_IRQHandler ; 30: Output Compare
+ DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
+ DCD CAN0_IRQHandler ; 32: CAN ch.0
+ DCD CAN1_IRQHandler ; 33: CAN ch.1
+ DCD USBF_Handler ; 34: USB Function
+ DCD USB_Handler ; 35: USB Function / USB HOST
+ DCD DummyHandler ; 36: Reserved
+ DCD DummyHandler ; 37: Reserved
+ DCD DMAC0_Handler ; 38: DMAC ch.0
+ DCD DMAC1_Handler ; 39: DMAC ch.1
+ DCD DMAC2_Handler ; 40: DMAC ch.2
+ DCD DMAC3_Handler ; 41: DMAC ch.3
+ DCD DMAC4_Handler ; 42: DMAC ch.4
+ DCD DMAC5_Handler ; 43: DMAC ch.5
+ DCD DMAC6_Handler ; 44: DMAC ch.6
+ DCD DMAC7_Handler ; 45: DMAC ch.7
+ DCD DummyHandler ; 46: Reserved
+ DCD DummyHandler ; 47: Reserved
+
+ THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+
+
+ PUBWEAK CSV_Handler
+ SECTION .text:CODE:REORDER(1)
+CSV_Handler
+ B CSV_Handler
+
+ PUBWEAK SWDT_Handler
+ SECTION .text:CODE:REORDER(1)
+SWDT_Handler
+ B SWDT_Handler
+
+ PUBWEAK LVD_Handler
+ SECTION .text:CODE:REORDER(1)
+LVD_Handler
+ B LVD_Handler
+
+ PUBWEAK MFT_WG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFT_WG_IRQHandler
+ B MFT_WG_IRQHandler
+
+ PUBWEAK INT0_7_Handler
+ SECTION .text:CODE:REORDER(1)
+INT0_7_Handler
+ B INT0_7_Handler
+
+ PUBWEAK INT8_15_Handler
+ SECTION .text:CODE:REORDER(1)
+INT8_15_Handler
+ B INT8_15_Handler
+
+ PUBWEAK DT_Handler
+ SECTION .text:CODE:REORDER(1)
+DT_Handler
+ B DT_Handler
+
+ PUBWEAK MFS0RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS0RX_IRQHandler
+ B MFS0RX_IRQHandler
+
+ PUBWEAK MFS0TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS0TX_IRQHandler
+ B MFS0TX_IRQHandler
+
+ PUBWEAK MFS1RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS1RX_IRQHandler
+ B MFS1RX_IRQHandler
+
+ PUBWEAK MFS1TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS1TX_IRQHandler
+ B MFS1TX_IRQHandler
+
+ PUBWEAK MFS2RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS2RX_IRQHandler
+ B MFS2RX_IRQHandler
+
+ PUBWEAK MFS2TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS2TX_IRQHandler
+ B MFS2TX_IRQHandler
+
+ PUBWEAK MFS3RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS3RX_IRQHandler
+ B MFS3RX_IRQHandler
+
+ PUBWEAK MFS3TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS3TX_IRQHandler
+ B MFS3TX_IRQHandler
+
+ PUBWEAK MFS4RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS4RX_IRQHandler
+ B MFS4RX_IRQHandler
+
+ PUBWEAK MFS4TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS4TX_IRQHandler
+ B MFS4TX_IRQHandler
+
+ PUBWEAK MFS5RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS5RX_IRQHandler
+ B MFS5RX_IRQHandler
+
+ PUBWEAK MFS5TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS5TX_IRQHandler
+ B MFS5TX_IRQHandler
+
+ PUBWEAK MFS6RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS6RX_IRQHandler
+ B MFS6RX_IRQHandler
+
+ PUBWEAK MFS6TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS6TX_IRQHandler
+ B MFS6TX_IRQHandler
+
+ PUBWEAK MFS7RX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS7RX_IRQHandler
+ B MFS7RX_IRQHandler
+
+ PUBWEAK MFS7TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFS7TX_IRQHandler
+ B MFS7TX_IRQHandler
+
+ PUBWEAK PPG_Handler
+ SECTION .text:CODE:REORDER(1)
+PPG_Handler
+ B PPG_Handler
+
+ PUBWEAK TIM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM_IRQHandler
+ B TIM_IRQHandler
+
+ PUBWEAK ADC0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC0_IRQHandler
+ B ADC0_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK ADC2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC2_IRQHandler
+ B ADC2_IRQHandler
+
+ PUBWEAK MFT_FRT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFT_FRT_IRQHandler
+ B MFT_FRT_IRQHandler
+
+ PUBWEAK MFT_IPC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFT_IPC_IRQHandler
+ B MFT_IPC_IRQHandler
+
+ PUBWEAK MFT_OPC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MFT_OPC_IRQHandler
+ B MFT_OPC_IRQHandler
+
+ PUBWEAK BT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+BT_IRQHandler
+ B BT_IRQHandler
+
+ PUBWEAK CAN0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN0_IRQHandler
+ B CAN0_IRQHandler
+
+ PUBWEAK CAN1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_IRQHandler
+ B CAN1_IRQHandler
+
+ PUBWEAK USBF_Handler
+ SECTION .text:CODE:REORDER(1)
+USBF_Handler
+ B USBF_Handler
+
+ PUBWEAK USB_Handler
+ SECTION .text:CODE:REORDER(1)
+USB_Handler
+ B USB_Handler
+
+ PUBWEAK DMAC0_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC0_Handler
+ B DMAC0_Handler
+
+
+ PUBWEAK DMAC1_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC1_Handler
+ B DMAC1_Handler
+
+ PUBWEAK DMAC2_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC2_Handler
+ B DMAC2_Handler
+
+ PUBWEAK DMAC3_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC3_Handler
+ B DMAC3_Handler
+
+ PUBWEAK DMAC4_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC4_Handler
+ B DMAC4_Handler
+
+ PUBWEAK DMAC5_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC5_Handler
+ B DMAC5_Handler
+
+ PUBWEAK DMAC6_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC6_Handler
+ B DMAC6_Handler
+
+ PUBWEAK DMAC7_Handler
+ SECTION .text:CODE:REORDER(1)
+DMAC7_Handler
+ B DMAC7_Handler
+
+ PUBWEAK DummyHandler
+ SECTION .text:CODE:REORDER(1)
+DummyHandler
+ B DummyHandler
+
+ END
diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c new file mode 100644 index 0000000000..e3efeca48a --- /dev/null +++ b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c @@ -0,0 +1,202 @@ +/************************************************************************/
+/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
+/* */
+/* The following software deliverable is intended for and must only be */
+/* used for reference and in an evaluation laboratory environment. */
+/* It is provided on an as-is basis without charge and is subject to */
+/* alterations. */
+/* It is the user's obligation to fully test the software in its */
+/* environment and to ensure proper functionality, qualification and */
+/* compliance with component specifications. */
+/* */
+/* In the event the software deliverable includes the use of open */
+/* source components, the provisions of the governing open source */
+/* license agreement shall apply with respect to such software */
+/* deliverable. */
+/* FSEU does not warrant that the deliverables do not infringe any */
+/* third party intellectual property right (IPR). In the event that */
+/* the deliverables infringe a third party IPR it is the sole */
+/* responsibility of the customer to obtain necessary licenses to */
+/* continue the usage of the deliverable. */
+/* */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not */
+/* limited to, warranties of merchantability and fitness for a */
+/* particular purpose for which the deliverable is not designated. */
+/* */
+/* To the maximum extent permitted by applicable law, FSEU's liability */
+/* is restricted to intentional misconduct and gross negligence. */
+/* FSEU is not liable for consequential damages. */
+/* */
+/* (V1.5) */
+/************************************************************************/
+
+#include "mcu.h"
+
+/** \file system_mb9bf50x.c
+ **
+ ** FM3 system initialization functions
+ ** All adjustments can be done in belonging header file.
+ **
+ ** History:
+ ** 2011-05-16 V1.0 MWi original version
+ ******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** System Clock Frequency (Core Clock) Variable according CMSIS
+ ******************************************************************************/
+uint32_t SystemCoreClock = __HCLK;
+
+/**
+ ******************************************************************************
+ ** \brief Update the System Core Clock with current core Clock retrieved from
+ ** cpu registers.
+ ** \param none
+ ** \return none
+ ******************************************************************************/
+void SystemCoreClockUpdate (void) {
+ uint32_t masterClk;
+ uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
+
+ switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
+ case 0: /* internal High-speed Cr osc. */
+ masterClk = __CLKHC;
+ break;
+
+ case 1: /* external main osc. */
+ masterClk = __CLKMO;
+ break;
+
+ case 2: /* PLL clock */
+ // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+ // violation:
+ // "Unordered accesses to a volatile location"
+ u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
+ masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
+ break;
+
+ case 4: /* internal Low-speed CR osc. */
+ masterClk = __CLKLC;
+ break;
+
+ case 5: /* external Sub osc. */
+ masterClk = __CLKSO;
+ break;
+
+ default:
+ masterClk = 0Ul;
+ break;
+ }
+
+ switch (FM3_CRG->BSC_PSR & 0x07) {
+ case 0:
+ SystemCoreClock = masterClk;
+ break;
+
+ case 1:
+ SystemCoreClock = masterClk / 2;
+ break;
+
+ case 2:
+ SystemCoreClock = masterClk / 3;
+ break;
+
+ case 3:
+ SystemCoreClock = masterClk / 4;
+ break;
+
+ case 4:
+ SystemCoreClock = masterClk / 6;
+ break;
+
+ case 5:
+ SystemCoreClock = masterClk /8;
+ break;
+
+ case 6:
+ SystemCoreClock = masterClk /16;
+ break;
+
+ default:
+ SystemCoreClock = 0Ul;
+ break;
+ }
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief Setup the microcontroller system. Initialize the System and update
+ ** the SystemCoreClock variable.
+ **
+ ** \param none
+ ** \return none
+ ******************************************************************************/
+void SystemInit (void) {
+
+ static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance
+
+#if (HWWD_DISABLE) /* HW Watchdog Disable */
+ FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */
+ FM3_HWWDT->WDG_LCK = 0xE5331AAE;
+ FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */
+#endif
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */
+ FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */
+ FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */
+ FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */
+ FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */
+ FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */
+
+ FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */
+
+ if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */
+ FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */
+ while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */
+ }
+
+ if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
+ FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
+ while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
+ }
+
+ FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */
+ FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */
+ FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */
+
+ if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */
+ FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */
+ while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */
+ }
+
+ FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */
+
+ // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+ // violations:
+ // "Unordered reads and writes to or from same location" and
+ // "Unordered accesses to a volatile location"
+ do
+ {
+ u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
+ }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);
+#endif // (CLOCK_SETUP)
+
+#if (CR_TRIM_SETUP)
+ /* CR Trimming Data */
+ if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
+ {
+ /* UnLock (MCR_FTRM) */
+ FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
+ /* Set MCR_FTRM */
+ FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
+ /* Lock (MCR_FTRM) */
+ FM3_CRTRIM->MCR_RLR = 0x00000000;
+ }
+#endif // (CR_TRIM_SETUP)
+}
+
+
+
diff --git a/bsp/mb9bf506r/libraries/SConscript b/bsp/mb9bf506r/libraries/SConscript new file mode 100644 index 0000000000..267f8334ab --- /dev/null +++ b/bsp/mb9bf506r/libraries/SConscript @@ -0,0 +1,20 @@ +Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+src = ['Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c']
+
+# add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += ['Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += ['Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += ['Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S']
+
+CPPPATH = [cwd + '/CMSIS/Include', cwd + '/CMSIS/RTOS', cwd + '/Device/FUJISTU/MB9BF50x/Include']
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/mb9bf506r/project.ewp b/bsp/mb9bf506r/project.ewp index 8799fb18f4..b708add684 100644 --- a/bsp/mb9bf506r/project.ewp +++ b/bsp/mb9bf506r/project.ewp @@ -1,3 +1,5 @@ +<?xml version="1.0" encoding="iso-8859-1"?> + <project> <fileVersion>2</fileVersion> <configuration> @@ -10,7 +12,7 @@ <name>General</name> <archiveVersion>3</archiveVersion> <data> - <version>20</version> + <version>21</version> <wantNonLocal>1</wantNonLocal> <debug>1</debug> <option> @@ -27,7 +29,7 @@ </option> <option> <name>Variant</name> - <version>18</version> + <version>19</version> <state>37</state> </option> <option> @@ -36,8 +38,8 @@ </option> <option> <name>Input variant</name> - <version>1</version> - <state>0</state> + <version>3</version> + <state>1</state> </option> <option> <name>Input description</name> @@ -45,8 +47,8 @@ </option> <option> <name>Output variant</name> - <version>0</version> - <state>0</state> + <version>2</version> + <state>1</state> </option> <option> <name>Output description</name> @@ -85,7 +87,7 @@ </option> <option> <name>OGLastSavedByProductVersion</name> - <state>6.10.3.52260</state> + <state>6.30.6.53380</state> </option> <option> <name>GeneralEnableMisra</name> @@ -135,26 +137,34 @@ </option> <option> <name>GFPUCoreSlave</name> - <version>18</version> + <version>19</version> <state>37</state> </option> <option> <name>GBECoreSlave</name> - <version>18</version> + <version>19</version> <state>37</state> </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> </data> </settings> <settings> <name>ICCARM</name> <archiveVersion>2</archiveVersion> <data> - <version>26</version> + <version>28</version> <wantNonLocal>1</wantNonLocal> <debug>1</debug> <option> <name>CCDefines</name> - <state /> + <state></state> </option> <option> <name>CCPreprocFile</name> @@ -198,15 +208,15 @@ </option> <option> <name>CCDiagRemark</name> - <state /> + <state></state> </option> <option> <name>CCDiagWarning</name> - <state /> + <state></state> </option> <option> <name>CCDiagError</name> - <state /> + <state></state> </option> <option> <name>CCObjPrefix</name> @@ -235,7 +245,7 @@ </option> <option> <name>IExtraOptions</name> - <state /> + <state></state> </option> <option> <name>CCLangConformance</name> @@ -275,7 +285,7 @@ </option> <option> <name>PreInclude</name> - <state /> + <state></state> </option> <option> <name>CompilerMisraOverride</name> @@ -283,17 +293,19 @@ </option> <option> <name>CCIncludePath2</name> - <state /> + <state></state> + <state>$PROJ_DIR$\..\..\components\dfs\include</state> + <state>$PROJ_DIR$\libraries\CMSIS\Include</state> <state>$PROJ_DIR$\..\..\include</state> - <state>$PROJ_DIR$\CMSIS</state> + <state>$PROJ_DIR$\drivers</state> <state>$PROJ_DIR$\..\..\components\dfs</state> <state>$PROJ_DIR$\.</state> <state>$PROJ_DIR$\applications</state> + <state>$PROJ_DIR$\libraries\CMSIS\RTOS</state> <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3</state> <state>$PROJ_DIR$\..\..\libcpu\arm\common</state> <state>$PROJ_DIR$\..\..\components\finsh</state> - <state>$PROJ_DIR$\drivers</state> - <state>$PROJ_DIR$\..\..\components\dfs\include</state> + <state>$PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Include</state> </option> <option> <name>CCStdIncCheck</name> @@ -375,11 +387,15 @@ <state>1</state> </option> <option> - <name>IccRelaxedFpPrecision</name> + <name>IccCppInlineSemantics</name> <state>0</state> </option> <option> - <name>IccCppInlineSemantics</name> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> <state>0</state> </option> </data> @@ -418,15 +434,15 @@ </option> <option> <name>AWarnOne</name> - <state /> + <state></state> </option> <option> <name>AWarnRange1</name> - <state /> + <state></state> </option> <option> <name>AWarnRange2</name> - <state /> + <state></state> </option> <option> <name>ADebug</name> @@ -438,7 +454,7 @@ </option> <option> <name>ADefines</name> - <state /> + <state></state> </option> <option> <name>AList</name> @@ -542,7 +558,7 @@ </option> <option> <name>AExtraOptionsV2</name> - <state /> + <state></state> </option> </data> </settings> @@ -580,28 +596,28 @@ <name>CUSTOM</name> <archiveVersion>3</archiveVersion> <data> - <extensions /> - <cmdline /> + <extensions></extensions> + <cmdline></cmdline> </data> </settings> <settings> <name>BICOMP</name> <archiveVersion>0</archiveVersion> - <data /> + <data/> </settings> <settings> <name>BUILDACTION</name> <archiveVersion>1</archiveVersion> <data> - <prebuild /> - <postbuild /> + <prebuild></prebuild> + <postbuild></postbuild> </data> </settings> <settings> <name>ILINK</name> <archiveVersion>0</archiveVersion> <data> - <version>11</version> + <version>14</version> <wantNonLocal>1</wantNonLocal> <debug>1</debug> <option> @@ -626,31 +642,31 @@ </option> <option> <name>IlinkKeepSymbols</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinaryFile</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinarySymbol</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinarySegment</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinaryAlign</name> - <state /> + <state></state> </option> <option> <name>IlinkDefines</name> - <state /> + <state></state> </option> <option> <name>IlinkConfigDefines</name> - <state /> + <state></state> </option> <option> <name>IlinkMapFile</name> @@ -686,7 +702,7 @@ </option> <option> <name>IlinkIcfFileSlave</name> - <state /> + <state></state> </option> <option> <name>IlinkEnableRemarks</name> @@ -694,19 +710,19 @@ </option> <option> <name>IlinkSuppressDiags</name> - <state /> + <state></state> </option> <option> <name>IlinkTreatAsRem</name> - <state /> + <state></state> </option> <option> <name>IlinkTreatAsWarn</name> - <state /> + <state></state> </option> <option> <name>IlinkTreatAsErr</name> - <state /> + <state></state> </option> <option> <name>IlinkWarningsAreErrors</name> @@ -718,7 +734,7 @@ </option> <option> <name>IlinkExtraOptions</name> - <state /> + <state></state> </option> <option> <name>IlinkLowLevelInterfaceSlave</name> @@ -730,7 +746,7 @@ </option> <option> <name>IlinkAdditionalLibs</name> - <state /> + <state></state> </option> <option> <name>IlinkOverrideProgramEntryLabel</name> @@ -847,6 +863,34 @@ <name>IlinkOptExceptionsForce</name> <state>0</state> </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> </data> </settings> <settings> @@ -858,7 +902,7 @@ <debug>1</debug> <option> <name>IarchiveInputs</name> - <state /> + <state></state> </option> <option> <name>IarchiveOverride</name> @@ -873,7 +917,7 @@ <settings> <name>BILINK</name> <archiveVersion>0</archiveVersion> - <data /> + <data/> </settings> </configuration> <configuration> @@ -886,7 +930,7 @@ <name>General</name> <archiveVersion>3</archiveVersion> <data> - <version>20</version> + <version>21</version> <wantNonLocal>1</wantNonLocal> <debug>0</debug> <option> @@ -903,7 +947,7 @@ </option> <option> <name>Variant</name> - <version>18</version> + <version>19</version> <state>0</state> </option> <option> @@ -912,21 +956,21 @@ </option> <option> <name>Input variant</name> - <version>1</version> - <state>0</state> + <version>3</version> + <state>1</state> </option> <option> <name>Input description</name> - <state /> + <state></state> </option> <option> <name>Output variant</name> - <version>0</version> - <state>0</state> + <version>2</version> + <state>1</state> </option> <option> <name>Output description</name> - <state /> + <state></state> </option> <option> <name>GOutputBinary</name> @@ -953,7 +997,7 @@ </option> <option> <name>RTDescription</name> - <state /> + <state></state> </option> <option> <name>OGProductVersion</name> @@ -961,7 +1005,7 @@ </option> <option> <name>OGLastSavedByProductVersion</name> - <state /> + <state></state> </option> <option> <name>GeneralEnableMisra</name> @@ -973,7 +1017,7 @@ </option> <option> <name>OGChipSelectEditMenu</name> - <state /> + <state></state> </option> <option> <name>GenLowLevelInterface</name> @@ -1007,25 +1051,33 @@ </option> <option> <name>RTConfigPath2</name> - <state /> + <state></state> </option> <option> <name>GFPUCoreSlave</name> - <version>18</version> + <version>19</version> <state>1</state> </option> <option> <name>GBECoreSlave</name> - <version>18</version> + <version>19</version> <state>1</state> </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> </data> </settings> <settings> <name>ICCARM</name> <archiveVersion>2</archiveVersion> <data> - <version>26</version> + <version>28</version> <wantNonLocal>1</wantNonLocal> <debug>0</debug> <option> @@ -1070,19 +1122,19 @@ </option> <option> <name>CCDiagSuppress</name> - <state /> + <state></state> </option> <option> <name>CCDiagRemark</name> - <state /> + <state></state> </option> <option> <name>CCDiagWarning</name> - <state /> + <state></state> </option> <option> <name>CCDiagError</name> - <state /> + <state></state> </option> <option> <name>CCObjPrefix</name> @@ -1111,7 +1163,7 @@ </option> <option> <name>IExtraOptions</name> - <state /> + <state></state> </option> <option> <name>CCLangConformance</name> @@ -1143,7 +1195,7 @@ </option> <option> <name>OutputFile</name> - <state /> + <state></state> </option> <option> <name>CCLibConfigHeader</name> @@ -1151,7 +1203,7 @@ </option> <option> <name>PreInclude</name> - <state /> + <state></state> </option> <option> <name>CompilerMisraOverride</name> @@ -1159,17 +1211,19 @@ </option> <option> <name>CCIncludePath2</name> - <state /> + <state></state> + <state>$PROJ_DIR$\..\..\components\dfs\include</state> + <state>$PROJ_DIR$\libraries\CMSIS\Include</state> <state>$PROJ_DIR$\..\..\include</state> - <state>$PROJ_DIR$\CMSIS</state> + <state>$PROJ_DIR$\drivers</state> <state>$PROJ_DIR$\..\..\components\dfs</state> <state>$PROJ_DIR$\.</state> <state>$PROJ_DIR$\applications</state> + <state>$PROJ_DIR$\libraries\CMSIS\RTOS</state> <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3</state> <state>$PROJ_DIR$\..\..\libcpu\arm\common</state> <state>$PROJ_DIR$\..\..\components\finsh</state> - <state>$PROJ_DIR$\drivers</state> - <state>$PROJ_DIR$\..\..\components\dfs\include</state> + <state>$PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Include</state> </option> <option> <name>CCStdIncCheck</name> @@ -1251,11 +1305,15 @@ <state>1</state> </option> <option> - <name>IccRelaxedFpPrecision</name> + <name>IccCppInlineSemantics</name> <state>0</state> </option> <option> - <name>IccCppInlineSemantics</name> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> <state>0</state> </option> </data> @@ -1294,15 +1352,15 @@ </option> <option> <name>AWarnOne</name> - <state /> + <state></state> </option> <option> <name>AWarnRange1</name> - <state /> + <state></state> </option> <option> <name>AWarnRange2</name> - <state /> + <state></state> </option> <option> <name>ADebug</name> @@ -1314,7 +1372,7 @@ </option> <option> <name>ADefines</name> - <state /> + <state></state> </option> <option> <name>AList</name> @@ -1390,7 +1448,7 @@ </option> <option> <name>AOutputFile</name> - <state /> + <state></state> </option> <option> <name>AMultibyteSupport</name> @@ -1410,7 +1468,7 @@ </option> <option> <name>AUserIncludes</name> - <state /> + <state></state> </option> <option> <name>AExtraOptionsCheckV2</name> @@ -1418,7 +1476,7 @@ </option> <option> <name>AExtraOptionsV2</name> - <state /> + <state></state> </option> </data> </settings> @@ -1440,7 +1498,7 @@ </option> <option> <name>OOCOutputFile</name> - <state /> + <state></state> </option> <option> <name>OOCCommandLineProducer</name> @@ -1456,28 +1514,28 @@ <name>CUSTOM</name> <archiveVersion>3</archiveVersion> <data> - <extensions /> - <cmdline /> + <extensions></extensions> + <cmdline></cmdline> </data> </settings> <settings> <name>BICOMP</name> <archiveVersion>0</archiveVersion> - <data /> + <data/> </settings> <settings> <name>BUILDACTION</name> <archiveVersion>1</archiveVersion> <data> - <prebuild /> - <postbuild /> + <prebuild></prebuild> + <postbuild></postbuild> </data> </settings> <settings> <name>ILINK</name> <archiveVersion>0</archiveVersion> <data> - <version>11</version> + <version>14</version> <wantNonLocal>1</wantNonLocal> <debug>0</debug> <option> @@ -1502,31 +1560,31 @@ </option> <option> <name>IlinkKeepSymbols</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinaryFile</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinarySymbol</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinarySegment</name> - <state /> + <state></state> </option> <option> <name>IlinkRawBinaryAlign</name> - <state /> + <state></state> </option> <option> <name>IlinkDefines</name> - <state /> + <state></state> </option> <option> <name>IlinkConfigDefines</name> - <state /> + <state></state> </option> <option> <name>IlinkMapFile</name> @@ -1562,7 +1620,7 @@ </option> <option> <name>IlinkIcfFileSlave</name> - <state /> + <state></state> </option> <option> <name>IlinkEnableRemarks</name> @@ -1570,19 +1628,19 @@ </option> <option> <name>IlinkSuppressDiags</name> - <state /> + <state></state> </option> <option> <name>IlinkTreatAsRem</name> - <state /> + <state></state> </option> <option> <name>IlinkTreatAsWarn</name> - <state /> + <state></state> </option> <option> <name>IlinkTreatAsErr</name> - <state /> + <state></state> </option> <option> <name>IlinkWarningsAreErrors</name> @@ -1594,7 +1652,7 @@ </option> <option> <name>IlinkExtraOptions</name> - <state /> + <state></state> </option> <option> <name>IlinkLowLevelInterfaceSlave</name> @@ -1606,7 +1664,7 @@ </option> <option> <name>IlinkAdditionalLibs</name> - <state /> + <state></state> </option> <option> <name>IlinkOverrideProgramEntryLabel</name> @@ -1618,7 +1676,7 @@ </option> <option> <name>IlinkProgramEntryLabel</name> - <state /> + <state></state> </option> <option> <name>DoFill</name> @@ -1723,6 +1781,34 @@ <name>IlinkOptExceptionsForce</name> <state>0</state> </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> </data> </settings> <settings> @@ -1734,7 +1820,7 @@ <debug>0</debug> <option> <name>IarchiveInputs</name> - <state /> + <state></state> </option> <option> <name>IarchiveOverride</name> @@ -1749,7 +1835,7 @@ <settings> <name>BILINK</name> <archiveVersion>0</archiveVersion> - <data /> + <data/> </settings> </configuration> <group> @@ -1764,154 +1850,153 @@ <group> <name>CMSIS</name> <file> - <name>$PROJ_DIR$\CMSIS\core_cm3.c</name> + <name>$PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Source\IAR\startup_mb9bf50x.S</name> </file> <file> - <name>$PROJ_DIR$\CMSIS\system_mb9bf50x.c</name> - </file> - <file> - <name>$PROJ_DIR$\CMSIS\start_iar.S</name> + <name>$PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c</name> </file> </group> <group> - <name>Drivers</name> + <name>CORTEX-M3</name> <file> - <name>$PROJ_DIR$\drivers\board.c</name> + <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name> </file> <file> - <name>$PROJ_DIR$\drivers\console.c</name> + <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S</name> </file> <file> - <name>$PROJ_DIR$\drivers\led.c</name> + <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c</name> </file> <file> - <name>$PROJ_DIR$\drivers\nand.c</name> + <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name> </file> <file> - <name>$PROJ_DIR$\drivers\serial.c</name> + <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name> </file> </group> <group> - <name>Kernel</name> + <name>Drivers</name> <file> - <name>$PROJ_DIR$\..\..\src\clock.c</name> + <name>$PROJ_DIR$\drivers\board.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\device.c</name> + <name>$PROJ_DIR$\drivers\console.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\idle.c</name> + <name>$PROJ_DIR$\drivers\led.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\ipc.c</name> + <name>$PROJ_DIR$\drivers\nand.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\irq.c</name> + <name>$PROJ_DIR$\drivers\serial.c</name> </file> + </group> + <group> + <name>Filesystem</name> <file> - <name>$PROJ_DIR$\..\..\src\kservice.c</name> + <name>$PROJ_DIR$\..\..\components\dfs\src\dfs.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\mem.c</name> + <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\memheap.c</name> + <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_file.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\mempool.c</name> + <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\object.c</name> + <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\scheduler.c</name> + <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c</name> </file> + </group> + <group> + <name>finsh</name> <file> - <name>$PROJ_DIR$\..\..\src\thread.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\src\timer.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name> </file> - </group> - <group> - <name>CORTEX-M3</name> <file> - <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name> </file> - </group> - <group> - <name>Filesystem</name> <file> - <name>$PROJ_DIR$\..\..\components\dfs\src\dfs.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_file.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c</name> + <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name> </file> </group> <group> - <name>finsh</name> + <name>Kernel</name> <file> - <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name> + <name>$PROJ_DIR$\..\..\src\clock.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name> + <name>$PROJ_DIR$\..\..\src\device.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name> + <name>$PROJ_DIR$\..\..\src\idle.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name> + <name>$PROJ_DIR$\..\..\src\ipc.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name> + <name>$PROJ_DIR$\..\..\src\irq.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name> + <name>$PROJ_DIR$\..\..\src\kservice.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name> + <name>$PROJ_DIR$\..\..\src\mem.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name> + <name>$PROJ_DIR$\..\..\src\memheap.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name> + <name>$PROJ_DIR$\..\..\src\mempool.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name> + <name>$PROJ_DIR$\..\..\src\object.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name> + <name>$PROJ_DIR$\..\..\src\scheduler.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name> + <name>$PROJ_DIR$\..\..\src\thread.c</name> </file> <file> - <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name> + <name>$PROJ_DIR$\..\..\src\timer.c</name> </file> </group> </project> + + diff --git a/bsp/mb9bf506r/project.uvopt b/bsp/mb9bf506r/project.uvopt index 08005113f2..d1898ed6c2 100644 --- a/bsp/mb9bf506r/project.uvopt +++ b/bsp/mb9bf506r/project.uvopt @@ -137,13 +137,14 @@ <SetRegEntry> <Number>0</Number> <Key>JL2CM3</Key> - <Name>-U11111117 -O78 -S9 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO11 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000</Name> + <Name>-U68000019 -O78 -S9 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO11 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000</Name> </SetRegEntry> </TargetDriverDllRegistry> + <Breakpoint/> <DebugFlag> <trace>0</trace> <periodic>0</periodic> - <aLwin>0</aLwin> + <aLwin>1</aLwin> <aCover>0</aCover> <aSer1>0</aSer1> <aSer2>0</aSer2> @@ -182,10 +183,10 @@ <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> + <ColumnNumber>48</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>43</TopLine> + <CurrentLine>43</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>applications\application.c</PathWithFileName> <FilenameWithoutPath>application.c</FilenameWithoutPath> @@ -198,8 +199,8 @@ <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>78</TopLine> + <CurrentLine>109</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>applications\startup.c</PathWithFileName> <FilenameWithoutPath>startup.c</FilenameWithoutPath> @@ -207,7 +208,7 @@ </Group> <Group> - <GroupName>CMSIS</GroupName> + <GroupName>Drivers</GroupName> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> @@ -222,8 +223,8 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>CMSIS\core_cm3.c</PathWithFileName> - <FilenameWithoutPath>core_cm3.c</FilenameWithoutPath> + <PathWithFileName>drivers\board.c</PathWithFileName> + <FilenameWithoutPath>board.c</FilenameWithoutPath> </File> <File> <GroupNumber>2</GroupNumber> @@ -236,13 +237,13 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>CMSIS\system_mb9bf50x.c</PathWithFileName> - <FilenameWithoutPath>system_mb9bf50x.c</FilenameWithoutPath> + <PathWithFileName>drivers\console.c</PathWithFileName> + <FilenameWithoutPath>console.c</FilenameWithoutPath> </File> <File> <GroupNumber>2</GroupNumber> <FileNumber>5</FileNumber> - <FileType>2</FileType> + <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> @@ -250,18 +251,11 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>CMSIS\start_rvds.S</PathWithFileName> - <FilenameWithoutPath>start_rvds.S</FilenameWithoutPath> + <PathWithFileName>drivers\led.c</PathWithFileName> + <FilenameWithoutPath>led.c</FilenameWithoutPath> </File> - </Group> - - <Group> - <GroupName>Drivers</GroupName> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <cbSel>0</cbSel> <File> - <GroupNumber>3</GroupNumber> + <GroupNumber>2</GroupNumber> <FileNumber>6</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> @@ -271,11 +265,11 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>drivers\board.c</PathWithFileName> - <FilenameWithoutPath>board.c</FilenameWithoutPath> + <PathWithFileName>drivers\nand.c</PathWithFileName> + <FilenameWithoutPath>nand.c</FilenameWithoutPath> </File> <File> - <GroupNumber>3</GroupNumber> + <GroupNumber>2</GroupNumber> <FileNumber>7</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> @@ -285,9 +279,16 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>drivers\console.c</PathWithFileName> - <FilenameWithoutPath>console.c</FilenameWithoutPath> + <PathWithFileName>drivers\serial.c</PathWithFileName> + <FilenameWithoutPath>serial.c</FilenameWithoutPath> </File> + </Group> + + <Group> + <GroupName>CMSIS</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> <File> <GroupNumber>3</GroupNumber> <FileNumber>8</FileNumber> @@ -299,36 +300,22 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>drivers\led.c</PathWithFileName> - <FilenameWithoutPath>led.c</FilenameWithoutPath> + <PathWithFileName>libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c</PathWithFileName> + <FilenameWithoutPath>system_mb9bf50x.c</FilenameWithoutPath> </File> <File> <GroupNumber>3</GroupNumber> <FileNumber>9</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> - <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> - <bDave2>0</bDave2> - <PathWithFileName>drivers\nand.c</PathWithFileName> - <FilenameWithoutPath>nand.c</FilenameWithoutPath> - </File> - <File> - <GroupNumber>3</GroupNumber> - <FileNumber>10</FileNumber> - <FileType>1</FileType> + <FileType>2</FileType> <tvExp>0</tvExp> <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>138</TopLine> + <CurrentLine>149</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>drivers\serial.c</PathWithFileName> - <FilenameWithoutPath>serial.c</FilenameWithoutPath> + <PathWithFileName>libraries\Device\FUJISTU\MB9BF50x\Source\ARM\startup_mb9bf50x.S</PathWithFileName> + <FilenameWithoutPath>startup_mb9bf50x.S</FilenameWithoutPath> </File> </Group> @@ -339,7 +326,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>4</GroupNumber> - <FileNumber>11</FileNumber> + <FileNumber>10</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -353,7 +340,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>12</FileNumber> + <FileNumber>11</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -367,21 +354,21 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>13</FileNumber> + <FileNumber>12</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>140</TopLine> + <CurrentLine>159</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>..\..\src\idle.c</PathWithFileName> <FilenameWithoutPath>idle.c</FilenameWithoutPath> </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>14</FileNumber> + <FileNumber>13</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -395,7 +382,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>15</FileNumber> + <FileNumber>14</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -409,7 +396,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>16</FileNumber> + <FileNumber>15</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -423,7 +410,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>17</FileNumber> + <FileNumber>16</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -437,7 +424,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>18</FileNumber> + <FileNumber>17</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -451,7 +438,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>19</FileNumber> + <FileNumber>18</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -465,7 +452,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>20</FileNumber> + <FileNumber>19</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -479,7 +466,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>21</FileNumber> + <FileNumber>20</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -493,7 +480,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>22</FileNumber> + <FileNumber>21</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -507,7 +494,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>23</FileNumber> + <FileNumber>22</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -528,7 +515,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>5</GroupNumber> - <FileNumber>24</FileNumber> + <FileNumber>23</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -542,7 +529,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>25</FileNumber> + <FileNumber>24</FileNumber> <FileType>2</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -556,7 +543,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>26</FileNumber> + <FileNumber>25</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -570,7 +557,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>27</FileNumber> + <FileNumber>26</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -584,7 +571,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>28</FileNumber> + <FileNumber>27</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -605,7 +592,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>6</GroupNumber> - <FileNumber>29</FileNumber> + <FileNumber>28</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -619,7 +606,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>30</FileNumber> + <FileNumber>29</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -633,7 +620,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>31</FileNumber> + <FileNumber>30</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -647,7 +634,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>32</FileNumber> + <FileNumber>31</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -661,7 +648,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>33</FileNumber> + <FileNumber>32</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -675,7 +662,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>34</FileNumber> + <FileNumber>33</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -696,7 +683,7 @@ <cbSel>0</cbSel> <File> <GroupNumber>7</GroupNumber> - <FileNumber>35</FileNumber> + <FileNumber>34</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -710,7 +697,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>36</FileNumber> + <FileNumber>35</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -724,7 +711,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>37</FileNumber> + <FileNumber>36</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -738,7 +725,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>38</FileNumber> + <FileNumber>37</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -752,7 +739,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>39</FileNumber> + <FileNumber>38</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -766,7 +753,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>40</FileNumber> + <FileNumber>39</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -780,7 +767,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>41</FileNumber> + <FileNumber>40</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -794,7 +781,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>42</FileNumber> + <FileNumber>41</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -808,7 +795,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>43</FileNumber> + <FileNumber>42</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -822,7 +809,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>44</FileNumber> + <FileNumber>43</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -836,7 +823,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>45</FileNumber> + <FileNumber>44</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -850,7 +837,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>46</FileNumber> + <FileNumber>45</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -864,7 +851,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>47</FileNumber> + <FileNumber>46</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> diff --git a/bsp/mb9bf506r/project.uvproj b/bsp/mb9bf506r/project.uvproj index fe10c8c00c..b10a09c0e7 100644 --- a/bsp/mb9bf506r/project.uvproj +++ b/bsp/mb9bf506r/project.uvproj @@ -61,6 +61,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> </BeforeCompile> <BeforeMake> <RunUserProg1>0</RunUserProg1> @@ -346,7 +348,7 @@ <MiscControls></MiscControls> <Define></Define> <Undefine></Undefine> - <IncludePath>.;..\..\components\dfs;..\..\components\dfs\include;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;CMSIS;applications;drivers</IncludePath> + <IncludePath>.;..\..\components\dfs;..\..\components\dfs\include;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;applications;drivers;libraries\CMSIS\Include;libraries\CMSIS\RTOS;libraries\Device\FUJISTU\MB9BF50x\Include</IncludePath> </VariousControls> </Cads> <Aads> @@ -376,7 +378,7 @@ <ScatterFile></ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> - <Misc>--keep __fsym_* --keep __vsym_*</Misc> + <Misc> --keep __fsym_* --keep __vsym_* </Misc> <LinkerInputFile></LinkerInputFile> <DisabledWarnings></DisabledWarnings> </LDads> @@ -399,26 +401,6 @@ </Files> </Group> <Group> - <GroupName>CMSIS</GroupName> - <Files> - <File> - <FileName>core_cm3.c</FileName> - <FileType>1</FileType> - <FilePath>CMSIS\core_cm3.c</FilePath> - </File> - <File> - <FileName>system_mb9bf50x.c</FileName> - <FileType>1</FileType> - <FilePath>CMSIS\system_mb9bf50x.c</FilePath> - </File> - <File> - <FileName>start_rvds.S</FileName> - <FileType>2</FileType> - <FilePath>CMSIS\start_rvds.S</FilePath> - </File> - </Files> - </Group> - <Group> <GroupName>Drivers</GroupName> <Files> <File> @@ -449,6 +431,21 @@ </Files> </Group> <Group> + <GroupName>CMSIS</GroupName> + <Files> + <File> + <FileName>system_mb9bf50x.c</FileName> + <FileType>1</FileType> + <FilePath>libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c</FilePath> + </File> + <File> + <FileName>startup_mb9bf50x.S</FileName> + <FileType>2</FileType> + <FilePath>libraries\Device\FUJISTU\MB9BF50x\Source\ARM\startup_mb9bf50x.S</FilePath> + </File> + </Files> + </Group> + <Group> <GroupName>Kernel</GroupName> <Files> <File> diff --git a/bsp/mb9bf506r/rtthread-mb9bf506.ld b/bsp/mb9bf506r/rtthread-mb9bf506.ld index 4f79480bb0..bdb11adf32 100644 --- a/bsp/mb9bf506r/rtthread-mb9bf506.ld +++ b/bsp/mb9bf506r/rtthread-mb9bf506.ld @@ -1,25 +1,116 @@ -/* Program Entry, set to mark it as "used" and avoid gc */
+/* Linker script to configure memory regions
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+
MEMORY
{
- CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
- DATA (rw) : ORIGIN = 0x1FFF8000, LENGTH = 0x00010000
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512k */
+ ram (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 0x00010000 /* 32k */
}
-ENTRY(Reset_Handler)
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
SECTIONS
{
- .text :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- *(.text) /* remaining code */
- *(.text.*) /* remaining code */
- *(.rodata) /* read-only data (constants) */
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- *(.gnu.linkonce.t*)
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
/* section information for finsh shell */
. = ALIGN(4);
@@ -31,92 +122,92 @@ SECTIONS KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
+ }
- . = ALIGN(4);
- _etext = .;
- } > CODE = 0
-
- /* .ARM.exidx is sorted, so has to go in its own output section. */
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-
- /* This is used by the startup in order to initialize the .data secion */
- _sidata = .;
- } > CODE
- __exidx_end = .;
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
- /* .data section which is used for initialized data */
-
- .data : AT (_sidata)
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _sdata = . ;
-
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d*)
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ .heap :
+ {
+ *(.heap)
+ } >ram
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _edata = . ;
- } >DATA
+ __bss_end = .;
- __bss_start = .;
- .bss :
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .;
+ .stack (__cs3_stack - __cs3_stack_size) :
+ {
+ *(.stack)
+ } >ram
- *(.bss)
- *(.bss.*)
- *(COMMON)
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _ebss = . ;
- _estack = .;
-
- *(.bss.init)
- } > DATA
- __bss_end = .;
-
- _end = .;
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- * Symbols in the DWARF debugging sections are relative to the beginning
- * of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
}
|