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authorAubr.Cool <[email protected]>2017-07-14 13:55:19 +0800
committerAubr.Cool <[email protected]>2017-07-20 11:56:21 +0800
commit2c1ee84347adf34c7381c5fcd05097cee4d68f3f (patch)
tree8ef1ee708d8f3070790c9fa2ac56a63c59e39403 /bsp
parent6ab027677b6ff69f5fe1b93d0e55957b36487dd1 (diff)
BSP stm32f10x add watchdog driver
Diffstat (limited to 'bsp')
-rw-r--r--bsp/stm32f10x/drivers/SConscript4
-rw-r--r--bsp/stm32f10x/drivers/stm32f1_wdg.c118
2 files changed, 122 insertions, 0 deletions
diff --git a/bsp/stm32f10x/drivers/SConscript b/bsp/stm32f10x/drivers/SConscript
index 6a1ab42bb7..1629fc691a 100644
--- a/bsp/stm32f10x/drivers/SConscript
+++ b/bsp/stm32f10x/drivers/SConscript
@@ -39,6 +39,10 @@ if GetDepend('RT_USING_RTGUI'):
elif rtconfig.RT_USING_LCD_TYPE == 'SSD1289':
src += ['ssd1289.c']
+# add wdt driver.
+if GetDepend('RT_USING_WDT'):
+ src += ['stm32f1_wdg.c']
+
CPPPATH = [cwd]
diff --git a/bsp/stm32f10x/drivers/stm32f1_wdg.c b/bsp/stm32f10x/drivers/stm32f1_wdg.c
new file mode 100644
index 0000000000..fae575abc7
--- /dev/null
+++ b/bsp/stm32f10x/drivers/stm32f1_wdg.c
@@ -0,0 +1,118 @@
+/*
+ * File : stm32f1_wdg.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2017-01-18 [email protected] 1st version
+ */
+#include "stm32f10x.h"
+#include <rtdevice.h>
+
+#ifdef RT_USING_WDT
+
+static rt_err_t stm32f1_wdg_init(rt_watchdog_t *wdt)
+{
+ return RT_EOK;
+}
+static rt_err_t stm32f1_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+ rt_uint32_t timeout_ms = 0;
+ rt_uint32_t timeout_pow = 1;
+ switch(cmd)
+ {
+ case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+ timeout_ms = (rt_uint32_t) arg;
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
+ if(timeout_ms >= 13107)
+ {
+ if(timeout_ms >= 26214)
+ {
+ timeout_ms = 26214;
+ }
+ IWDG_SetPrescaler(IWDG_Prescaler_256);
+ timeout_pow = 256;
+ }
+ else if(timeout_ms >= 6553)
+ {
+ IWDG_SetPrescaler(IWDG_Prescaler_128);
+ timeout_pow = 128;
+ }
+ else if(timeout_ms >= 3276)
+ {
+ IWDG_SetPrescaler(IWDG_Prescaler_64);
+ timeout_pow = 64;
+ }
+ else if(timeout_ms >= 1638)
+ {
+ IWDG_SetPrescaler(IWDG_Prescaler_32);
+ timeout_pow = 32;
+ }
+ else if(timeout_ms >= 819)
+ {
+ IWDG_SetPrescaler(IWDG_Prescaler_16);
+ timeout_pow = 16;
+ }
+ else if(timeout_ms >= 409)
+ {
+ IWDG_SetPrescaler(IWDG_Prescaler_8);
+ timeout_pow = 8;
+ }
+ else
+ {
+ IWDG_SetPrescaler(IWDG_Prescaler_4);
+ timeout_pow = 4;
+ }
+ timeout_ms = timeout_ms * 40 / timeout_pow;
+ if(timeout_ms > 0xFFF)
+ {
+ timeout_ms = 0xFFF;
+ }
+ IWDG_SetReload(timeout_ms);
+ IWDG_ReloadCounter();
+ break;
+ case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+ timeout_pow = IWDG->PR;
+ if(timeout_pow > 6)
+ {
+ timeout_pow = 6;
+ }
+ timeout_pow = 1 << (2 + timeout_pow);
+ timeout_ms = IWDG->RLR;
+ timeout_ms &= 0xFFF;
+ *((rt_uint32_t *) arg) = timeout_ms * timeout_pow / 40;
+ break;
+ case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+ IWDG_ReloadCounter();
+ break;
+ case RT_DEVICE_CTRL_WDT_START:
+ IWDG_Enable();
+ break;
+ default:
+ return RT_EIO;
+ }
+ return RT_EOK;
+}
+
+static const struct rt_watchdog_ops stm32f1_wdg_pos =
+{
+ stm32f1_wdg_init,
+ stm32f1_wdg_control,
+};
+static rt_watchdog_t stm32f1_wdg;
+
+int rt_hw_wdg_init(void)
+{
+ stm32f1_wdg.ops = &stm32f1_wdg_pos;
+ rt_hw_watchdog_register(&stm32f1_wdg, "wdg", 0, RT_NULL);
+ return RT_EOK;
+}
+
+INIT_BOARD_EXPORT(rt_hw_wdg_init);
+
+#endif /*RT_USING_WDT*/