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authortanek liang <[email protected]>2017-06-14 16:41:23 +0800
committertanek liang <[email protected]>2017-06-14 16:43:07 +0800
commit81fce5d00096f89829e27ffa699c3d23774edf0b (patch)
treef4b473ad0fba9795c053170b65af7b55a68a1c14 /bsp
parentf537194d0146182510bdc14d60a236846c8507af (diff)
[bsp] replace error_handler() by RT_ASSERT(RT_NULL)
Diffstat (limited to 'bsp')
-rw-r--r--bsp/stm32l072/board/board.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c
index 963ea5bbe9..80c7946a04 100644
--- a/bsp/stm32l072/board/board.c
+++ b/bsp/stm32l072/board/board.c
@@ -68,7 +68,10 @@ static void RCC_Configuration(void)
OscInit.PLL.PLLDIV = RCC_PLLDIV_2;
OscInit.PLL.PLLMUL = RCC_PLLMUL_4;
OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- HAL_RCC_OscConfig(&OscInit);
+ if (HAL_RCC_OscConfig(&OscInit) != HAL_OK)
+ {
+ RT_ASSERT(RT_NULL);
+ }
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
@@ -83,7 +86,7 @@ static void RCC_Configuration(void)
ClkInit.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK)
{
- error_handler();
+ RT_ASSERT(RT_NULL);
}
}