diff options
| author | liuhy <[email protected]> | 2021-10-15 14:47:01 +0800 |
|---|---|---|
| committer | liuhy <[email protected]> | 2021-10-15 14:47:01 +0800 |
| commit | 2e5fb6bf7eaf2d42fc95e32f83f32f93a6179838 (patch) | |
| tree | f4514cc0ffd8e47df4930d950d81b15e1d1ecff9 /bsp | |
| parent | 7516c14fa54130a53b383186f0318fc81f01f7c3 (diff) | |
[bsp][essemi] add bsp es32f365x
Diffstat (limited to 'bsp')
51 files changed, 23816 insertions, 0 deletions
diff --git a/bsp/essemi/es32f365x/.config b/bsp/essemi/es32f365x/.config new file mode 100644 index 0000000000..1b588eb1fe --- /dev/null +++ b/bsp/essemi/es32f365x/.config @@ -0,0 +1,570 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +CONFIG_SOC_ES32F3656LT=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set + +# +# SPI Drivers +# +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set + +# +# I2C Drivers +# +# CONFIG_BSP_USING_I2C0 is not set +# CONFIG_BSP_USING_I2C1 is not set + +# +# CAN Drivers +# +# CONFIG_BSP_USING_CAN0 is not set + +# +# ADC Drivers +# +# CONFIG_BSP_USING_ADC0 is not set +# CONFIG_BSP_USING_ADC1 is not set + +# +# RTC Drivers +# +# CONFIG_BSP_USING_RTC is not set + +# +# HWTIMER Drivers +# +# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_AD16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_BS16T0_HWTIMER is not set +# CONFIG_BSP_USING_BS16T1_HWTIMER is not set + +# +# PWM Drivers +# +# CONFIG_BSP_USING_AD16C4T0_PWM is not set +# CONFIG_BSP_USING_AD16C4T1_PWM is not set +# CONFIG_BSP_USING_GP32C4T0_PWM is not set +# CONFIG_BSP_USING_GP32C4T1_PWM is not set +# CONFIG_BSP_USING_GP16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T1_PWM is not set + +# +# PM Drivers +# +# CONFIG_BSP_USING_PM is not set + +# +# Onboard Peripheral Drivers +# + +# +# Offboard Peripheral Drivers +# + +# +# Peripheral Drivers test example +# +# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set +# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set +# CONFIG_BSP_USING_EXAMPLE_I2C is not set +# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set +# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set +# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set +# CONFIG_BSP_USING_EXAMPLE_RTC is not set +# CONFIG_BSP_USING_EXAMPLE_SPI is not set +# CONFIG_BSP_USING_EXAMPLE_UART is not set +# CONFIG_BSP_USING_EXAMPLE_CAN is not set +# CONFIG_BSP_USING_EXAMPLE_PM is not set diff --git a/bsp/essemi/es32f365x/Kconfig b/bsp/essemi/es32f365x/Kconfig new file mode 100644 index 0000000000..b9233eeb6c --- /dev/null +++ b/bsp/essemi/es32f365x/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ES32F3696LT + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/essemi/es32f365x/README.md b/bsp/essemi/es32f365x/README.md new file mode 100644 index 0000000000..908c11c72b --- /dev/null +++ b/bsp/essemi/es32f365x/README.md @@ -0,0 +1,104 @@ +# ES-PDS-ES32F365x 开发板 BSP 说明 +标签： EastSoft、国产MCU、Cortex-M3、ES32F365x + +## 1. 简介 + +本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F365x 开发板提供的 BSP (板级支持包) 说明。 +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +主要内容如下： +ES-PDS-ES32F365x 是东软载波微电子官方推出的一款基于 ARM Cortex-M3 内核的开发板，最高主频为 96MHz，可满足基础功能测试及高端功能扩展等开发需求。 + + + +该开发板常用 **板载资源** 如下： + +- MCU：ES32F3656LT，主频 96MHz，64KB SRAM，512KB FLASH，50 GPIOs +- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B) +- 常用接口：GPIO、UART、SPI、I2C、CAN +- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 + +外设支持: + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :-------------- | +| SPI FLASH | 支持 | SPI0 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | 50 GPIOs | +| UART | 支持 | UART0/1/2/3/4/5 | +| SPI | 支持 | SPI0/1/2 | +| I2C | 支持 | I2C0/1 | +| CAN | 支持 | CAN0 | +| PWM | 支持 | PWM0/1 | +| TIMER | 支持 | TIMER0/1 | +| RTC | 支持 | RTC | +| ADC | 支持 | ADC0 | + +### 1.2 注意事项 + +更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) + +## 2. 快速上手 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +**注意**：es32f365x的bsp 依赖 es32f369x的bsp。（ es32f369x的bsp中的库为es32f36xx） + + es32f365x与es32f369x相比，SRAM较小，且没有USB。 + +### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 + +### 运行结果 + +下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Oct 11 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +## 3. 进阶使用 + +此 BSP 默认只开启了 GPIO 和 uart0 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + + a）如果需要使用内核用例，先配置rt-thread内核，如图： + +  + + 然后配置内核用例，如图： + +  + + b）如果需要使用驱动用例：先使能驱动，如图： + +  + + 然后配置驱动用例，如图： + +  + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +## 4. 联系人信息 + +- [liuhongyan](https://gitee.com/liuhongyan98) + +## 5. 参考 + +- [ EastSoft 官网](http://www.essemi.com) + diff --git a/bsp/essemi/es32f365x/SConscript b/bsp/essemi/es32f365x/SConscript new file mode 100644 index 0000000000..468297b6a9 --- /dev/null +++ b/bsp/essemi/es32f365x/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +objs = [] +cwd = str(Dir('#')) +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/essemi/es32f365x/SConstruct b/bsp/essemi/es32f365x/SConstruct new file mode 100644 index 0000000000..c13a0c9123 --- /dev/null +++ b/bsp/essemi/es32f365x/SConstruct @@ -0,0 +1,54 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +ESSEMI_ROOT = os.path.abspath('./') + +es32f36xx_lib_path_prefix = os.path.dirname(ESSEMI_ROOT) + '/es32f369x' + +ES32F36XX_DRV_ROOT = es32f36xx_lib_path_prefix + '/drivers' + +Export('ES32F36XX_DRV_ROOT') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +es32f36xx_library = 'libraries' + +rtconfig.BSP_LIBRARY_TYPE = es32f36xx_library +# include libraries +objs.extend(SConscript(os.path.join(es32f36xx_lib_path_prefix, es32f36xx_library, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es32f365x/applications/SConscript b/bsp/essemi/es32f365x/applications/SConscript new file mode 100644 index 0000000000..e0c84e8f14 --- /dev/null +++ b/bsp/essemi/es32f365x/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') + +CPPPATH = [cwd, str(Dir('#'))] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es32f365x/applications/main.c b/bsp/essemi/es32f365x/applications/main.c new file mode 100644 index 0000000000..ed064d6f0a --- /dev/null +++ b/bsp/essemi/es32f365x/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include "drv_gpio.h" + +#define LED_PIN GET_PIN( F , 0 ) + +int main(void) +{ + int count = 1; + /* set pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + return RT_EOK; +} diff --git a/bsp/essemi/es32f365x/drivers/ES/Kconfig b/bsp/essemi/es32f365x/drivers/ES/Kconfig new file mode 100644 index 0000000000..906bdb042e --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/Kconfig @@ -0,0 +1,267 @@ +menu "UART Drivers" + + config BSP_USING_UART0 + bool "Register UART0 " + select RT_USING_SERIAL + default y + + if BSP_USING_UART0 + config BSP_UART0_TX_USING_DMA + bool "UART0 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_USING_DMA + bool "UART0 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_UART1 + bool "Register UART1 " + select RT_USING_SERIAL + default n + + if BSP_USING_UART1 + config BSP_UART1_TX_USING_DMA + bool "UART1 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_USING_DMA + bool "UART1 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_UART2 + bool "Register UART2 " + select RT_USING_SERIAL + default n + + if BSP_USING_UART2 + config BSP_UART2_TX_USING_DMA + bool "UART2 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_USING_DMA + bool "UART2 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_UART3 + bool "Register UART3 " + select RT_USING_SERIAL + default n + + if BSP_USING_UART3 + config BSP_UART3_TX_USING_DMA + bool "UART3 using DMA TX" + default n + config BSP_UART3_RX_USING_DMA + bool "UART3 using DMA RX" + default n + endif + + config BSP_USING_UART4 + bool "Register UART4 " + select RT_USING_SERIAL + default n + + if BSP_USING_UART4 + config BSP_UART4_TX_USING_DMA + bool "UART4 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_USING_DMA + bool "UART4 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_UART5 + bool "Register UART5 " + select RT_USING_SERIAL + default n + + if BSP_USING_UART5 + config BSP_UART5_TX_USING_DMA + bool "UART5 using DMA TX" + select RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_USING_DMA + bool "UART5 using DMA RX" + select RT_SERIAL_USING_DMA + default n + endif + +endmenu + +menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Register SPI0 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Register SPI1 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI2 + bool "Register SPI2 " + select RT_USING_SPI + select RT_USING_PIN + default n + +endmenu + +menu "I2C Drivers" + + config BSP_USING_I2C0 + bool "Register I2C0 " + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Register I2C1 " + select RT_USING_I2C + default n + +endmenu + +menu "CAN Drivers" + + config BSP_USING_CAN0 + bool "Register CAN0 " + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_CAN + default n + +endmenu + +menu "ADC Drivers" + + config BSP_USING_ADC0 + bool "Register ADC0 " + select RT_USING_ADC + default n + + config BSP_USING_ADC1 + bool "Register ADC1 " + select RT_USING_ADC + default n + +endmenu + +menu "RTC Drivers" + + config BSP_USING_RTC + bool "Register RTC " + select RT_USING_RTC + default n + +endmenu + +menu "HWTIMER Drivers" + + config BSP_USING_AD16C4T0_HWTIMER + bool "Register HWTIMER0 " + select RT_USING_HWTIMER + default n + + config BSP_USING_AD16C4T1_HWTIMER + bool "Register HWTIMER1 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T0_HWTIMER + bool "Register HWTIMER2 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T1_HWTIMER + bool "Register HWTIMER3 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T0_HWTIMER + bool "Register HWTIMER4 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T1_HWTIMER + bool "Register HWTIMER5 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T0_HWTIMER + bool "Register HWTIMER6 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T1_HWTIMER + bool "Register HWTIMER7 " + select RT_USING_HWTIMER + default n + +endmenu + +menu "PWM Drivers" + + config BSP_USING_AD16C4T0_PWM + bool "Register PWM0 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T0_HWTIMER + + config BSP_USING_AD16C4T1_PWM + bool "Register PWM1 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T1_HWTIMER + + config BSP_USING_GP32C4T0_PWM + bool "Register PWM2 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T0_HWTIMER + + config BSP_USING_GP32C4T1_PWM + bool "Register PWM3 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T1_HWTIMER + + config BSP_USING_GP16C4T0_PWM + bool "Register PWM4 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T0_HWTIMER + + config BSP_USING_GP16C4T1_PWM + bool "Register PWM5 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T1_HWTIMER + +endmenu + +menu "PM Drivers" + + config BSP_USING_PM + bool "Register PM " + select RT_USING_PM + default n + +endmenu + +menu "DMA Drivers" + config BSP_USING_DMA0 + bool "Using DMA0 " + select ES_CONF_DMA_ENABLE + default n +endmenu diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_adc.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_adc.h new file mode 100644 index 0000000000..576f806e35 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_adc.h @@ -0,0 +1,97 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_ADC_H__ +#define __ES_CONF_INFO_ADC_H__ + +#include "es_conf_info_map.h" + +#include <ald_adc.h> + + +#define ES_C_ADC_CLK_DIV_1 ADC_CKDIV_1 +#define ES_C_ADC_CLK_DIV_2 ADC_CKDIV_2 +#define ES_C_ADC_CLK_DIV_4 ADC_CKDIV_4 +#define ES_C_ADC_CLK_DIV_8 ADC_CKDIV_8 +#define ES_C_ADC_CLK_DIV_16 ADC_CKDIV_16 +#define ES_C_ADC_CLK_DIV_32 ADC_CKDIV_32 +#define ES_C_ADC_CLK_DIV_64 ADC_CKDIV_64 +#define ES_C_ADC_CLK_DIV_128 ADC_CKDIV_128 + +#define ES_C_ADC_ALIGN_RIGHT ADC_DATAALIGN_RIGHT +#define ES_C_ADC_ALIGN_LEFT ADC_DATAALIGN_LEFT + +#define ES_C_ADC_CONV_BIT_6 ADC_CONV_BIT_6 +#define ES_C_ADC_CONV_BIT_8 ADC_CONV_BIT_8 +#define ES_C_ADC_CONV_BIT_10 ADC_CONV_BIT_10 +#define ES_C_ADC_CONV_BIT_12 ADC_CONV_BIT_12 + +#define ES_C_ADC_SAMPLE_TIME_1 ADC_SAMPLETIME_1 +#define ES_C_ADC_SAMPLE_TIME_2 ADC_SAMPLETIME_2 +#define ES_C_ADC_SAMPLE_TIME_4 ADC_SAMPLETIME_4 +#define ES_C_ADC_SAMPLE_TIME_15 ADC_SAMPLETIME_15 + +/* ADC 配置 */ + +/* codes_main */ + + +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 + +#ifndef ES_DEVICE_NAME_ADC0 +#define ES_DEVICE_NAME_ADC0 "adc0" +#endif +#ifndef ES_DEVICE_NAME_ADC1 +#define ES_DEVICE_NAME_ADC1 "adc1" +#endif + +#ifndef ES_ADC0_CLK_DIV +#define ES_ADC0_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC0_ALIGN +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC0_DATA_BIT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC0_NCH_SAMPLETIME +#define ES_ADC0_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#ifndef ES_ADC1_CLK_DIV +#define ES_ADC1_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC1_ALIGN +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC1_DATA_BIT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC1_NCH_SAMPLETIME +#define ES_ADC1_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_can.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_can.h new file mode 100644 index 0000000000..7254f5660b --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_can.h @@ -0,0 +1,73 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CAN_H__ +#define __ES_CONF_INFO_CAN_H__ + +#include "es_conf_info_map.h" +#include <ald_can.h> +#include <ald_gpio.h> + + +/*默认的CAN硬件过滤器的编号 0 */ +#define ES_C_CAN_DEFAULT_FILTER_NUMBER 0 + +/*硬件过滤器，过滤帧类型*/ +#define ES_C_CAN_FILTER_FRAME_TYPE 0 + + +#define ES_C_CAN_SJW_NUM_1 CAN_SJW_1 +#define ES_C_CAN_SJW_NUM_2 CAN_SJW_2 +#define ES_C_CAN_SJW_NUM_3 CAN_SJW_3 +#define ES_C_CAN_SJW_NUM_4 CAN_SJW_4 + + + +/* CAN 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_CAN0 +#define ES_DEVICE_NAME_CAN0 "can0" +#endif + +#ifndef ES_CAN0_AUTO_BAN_RE_T +#define ES_CAN0_AUTO_BAN_RE_T ES_C_DISABLE +#endif +#ifndef ES_CAN0_SPEED +#define ES_CAN0_SPEED 1000000 +#endif +#ifndef ES_CAN0_SJW +#define ES_CAN0_SJW ES_C_CAN_SJW_NUM_4 +#endif + +#define ES_CAN0_CONFIG \ +{ \ + ES_CAN0_SPEED, \ + RT_CANMSG_BOX_SZ, \ + RT_CANSND_BOX_NUM, \ + RT_CAN_MODE_NORMAL, \ +}; +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_cmu.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_cmu.h new file mode 100644 index 0000000000..416de51dd2 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_cmu.h @@ -0,0 +1,89 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CMU_H__ +#define __ES_CONF_INFO_CMU_H__ + + +#include <ald_cmu.h> + + +/* 时钟树 配置 */ + +#define ES_C_MUL_9 CMU_PLL1_OUTPUT_36M +#define ES_C_MUL_12 CMU_PLL1_OUTPUT_48M +#define ES_C_MUL_18 CMU_PLL1_OUTPUT_72M +#define ES_C_MUL_24 CMU_PLL1_OUTPUT_96M + +#define ES_C_DIV_1 CMU_DIV_1 +#define ES_C_DIV_2 CMU_DIV_2 +#define ES_C_DIV_4 CMU_DIV_4 +#define ES_C_DIV_8 CMU_DIV_8 +#define ES_C_DIV_16 CMU_DIV_16 +#define ES_C_DIV_32 CMU_DIV_32 +#define ES_C_DIV_64 CMU_DIV_64 +#define ES_C_DIV_128 CMU_DIV_128 +#define ES_C_DIV_256 CMU_DIV_256 +#define ES_C_DIV_512 CMU_DIV_512 +#define ES_C_DIV_1024 CMU_DIV_1024 +#define ES_C_DIV_2048 CMU_DIV_2048 +#define ES_C_DIV_4096 CMU_DIV_4096 + +#define ES_C_HOSC_DIV_1 CMU_PLL1_INPUT_HOSC +#define ES_C_HOSC_DIV_2 CMU_PLL1_INPUT_HOSC_2 +#define ES_C_HOSC_DIV_3 CMU_PLL1_INPUT_HOSC_3 +#define ES_C_HOSC_DIV_4 CMU_PLL1_INPUT_HOSC_4 +#define ES_C_HOSC_DIV_5 CMU_PLL1_INPUT_HOSC_5 +#define ES_C_HOSC_DIV_6 CMU_PLL1_INPUT_HOSC_6 +#define ES_C_HRC_DIV_6 CMU_PLL1_INPUT_HRC_6 + + + + + +#define ES_PLL1_REFER_CLK ES_C_HOSC_DIV_3 +#define ES_PLL1_OUT_CLK ES_C_MUL_18 +#define ES_CMU_PLL1_EN ES_C_ENABLE +#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE +#define ES_CMU_LOSC_EN ES_C_ENABLE +#define ES_CMU_LRC_EN ES_C_ENABLE +#define ES_CMU_HOSC_EN ES_C_ENABLE +#define ES_CMU_HRC_EN ES_C_ENABLE +#define ES_CMU_SYS_DIV ES_C_DIV_1 +#define ES_CMU_HCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_HCLK_2_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_2_DIV ES_C_DIV_4 +#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL1 +#define ES_PLL_CLK 72000000 +#define ES_SYS_SOURCE_CLK 72000000 +#define ES_SYS_CLK 72000000 +#define ES_PCLK1_CLK 36000000 +#define ES_PCLK2_CLK 18000000 +#define ES_HCLK1_CLK 36000000 +#define ES_HCLK2_CLK 36000000 +#define ES_CMU_EXTERN_CLK_LOSC 32768 +#define ES_CMU_EXTERN_CLK_HOSC 12000000 + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_dma.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_dma.h new file mode 100644 index 0000000000..3f61f286d1 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_dma.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. + * + */ + +#ifndef __ES_CONF_INFO_DMA_H__ +#define __ES_CONF_INFO_DMA_H__ + +#include "es_conf_info_map.h" +#include <rtdevice.h> +#include <ald_dma.h> +#ifdef BSP_USING_DMA0 +#define ES_CONF_DMA_ENABLE +#endif + +enum ES_DMA_CHANNELS +{ +#if defined(ES_CONF_UART0_DMA_TX)||defined(BSP_UART0_TX_USING_DMA) + ES_UART0_DMATX_CHANNEL, +#endif +#if defined(ES_CONF_UART0_DMA_RX)||defined(BSP_UART0_RX_USING_DMA) + ES_UART0_DMARX_CHANNEL, +#endif +#if defined(ES_CONF_UART1_DMA_TX)||defined(BSP_UART1_TX_USING_DMA) + ES_UART1_DMATX_CHANNEL, +#endif +#if defined(ES_CONF_UART1_DMA_RX)||defined(BSP_UART1_RX_USING_DMA) + ES_UART1_DMARX_CHANNEL, +#endif +#if defined(ES_CONF_UART2_DMA_TX)||defined(BSP_UART2_TX_USING_DMA) + ES_UART2_DMATX_CHANNEL, +#endif +#if defined(ES_CONF_UART2_DMA_RX)||defined(BSP_UART2_RX_USING_DMA) + ES_UART2_DMARX_CHANNEL, +#endif +#if defined(ES_CONF_UART3_DMA_TX)||defined(BSP_UART3_TX_USING_DMA) + ES_UART3_DMATX_CHANNEL, +#endif +#if defined(ES_CONF_UART3_DMA_RX)||defined(BSP_UART3_RX_USING_DMA) + ES_UART3_DMARX_CHANNEL, +#endif +#if defined(ES_CONF_UART4_DMA_TX)||defined(BSP_UART4_TX_USING_DMA) + ES_UART4_DMATX_CHANNEL, +#endif +#if defined(ES_CONF_UART4_DMA_RX)||defined(BSP_UART4_RX_USING_DMA) + ES_UART4_DMARX_CHANNEL, +#endif +#if defined(ES_CONF_UART5_DMA_TX)||defined(BSP_UART5_TX_USING_DMA) + ES_UART5_DMATX_CHANNEL, +#endif +#if defined(ES_CONF_UART5_DMA_RX)||defined(BSP_UART5_RX_USING_DMA) + ES_UART5_DMARX_CHANNEL, +#endif + ES_DMA_CHANNEL_NUM +}; +#define ES_DMA_INVAILD_CHANNEL (DMA_CH_COUNT) +#define ES_DMA_USER_CHANNEL (ES_DMA_CHANNEL_NUM) + +#endif /* __ES_CONF_INFO_DMA_H__ */ diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_gpio.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_gpio.h new file mode 100644 index 0000000000..7c766b7fad --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_gpio.h @@ -0,0 +1,5157 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_GPIO_H__ +#define __ES_CONF_INFO_GPIO_H__ + +#include "es_conf_info_map.h" + +#include <rthw.h> +#include <rtdevice.h> +#include <ald_cmu.h> + +/* GPIO 配置 */ + +typedef struct { + uint8_t pin; + uint8_t pin_mode; + uint8_t pin_level; + uint8_t irq_en; + uint8_t irq_mode; + void (*callback)(void *arg); +} gpio_conf_t; + +/*参数的定义*/ + +#define ES_C_GPIO_LEVEL_HIGH PIN_HIGH +#define ES_C_GPIO_LEVEL_LOW PIN_LOW + +#define ES_C_GPIO_MODE_OUTPUT PIN_MODE_OUTPUT +#define ES_C_GPIO_MODE_INPUT PIN_MODE_INPUT +#define ES_C_GPIO_MODE_INPUT_PULLUP PIN_MODE_INPUT_PULLUP +#define ES_C_GPIO_MODE_INPUT_PULLDOWN PIN_MODE_INPUT_PULLDOWN +#define ES_C_GPIO_MODE_OUTPUT_OD PIN_MODE_OUTPUT_OD + +#define ES_C_GPIO_IRQ_ENABLE PIN_IRQ_ENABLE +#define ES_C_GPIO_IRQ_DISABLE PIN_IRQ_DISABLE + +#define ES_C_GPIO_IRQ_MODE_FALL PIN_IRQ_MODE_FALLING +#define ES_C_GPIO_IRQ_MODE_RISE PIN_IRQ_MODE_RISING +#define ES_C_GPIO_IRQ_MODE_R_F PIN_IRQ_MODE_RISING_FALLING + + + + + +/* codes_main */ + + + + +#ifndef ES_DEVICE_NAME_PIN +#define ES_DEVICE_NAME_PIN "pin" +#endif + +/*GPIO外部中断回调函数控制需要，补充是否中断*/ +#if 11111 + +#ifndef ES_INIT_GPIO_A_0_IRQ_EN +#define ES_INIT_GPIO_A_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_1_IRQ_EN +#define ES_INIT_GPIO_A_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_2_IRQ_EN +#define ES_INIT_GPIO_A_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_3_IRQ_EN +#define ES_INIT_GPIO_A_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_4_IRQ_EN +#define ES_INIT_GPIO_A_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_5_IRQ_EN +#define ES_INIT_GPIO_A_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_6_IRQ_EN +#define ES_INIT_GPIO_A_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_7_IRQ_EN +#define ES_INIT_GPIO_A_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_8_IRQ_EN +#define ES_INIT_GPIO_A_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_9_IRQ_EN +#define ES_INIT_GPIO_A_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_10_IRQ_EN +#define ES_INIT_GPIO_A_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_11_IRQ_EN +#define ES_INIT_GPIO_A_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_12_IRQ_EN +#define ES_INIT_GPIO_A_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_13_IRQ_EN +#define ES_INIT_GPIO_A_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_14_IRQ_EN +#define ES_INIT_GPIO_A_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_15_IRQ_EN +#define ES_INIT_GPIO_A_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_0_IRQ_EN +#define ES_INIT_GPIO_B_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_1_IRQ_EN +#define ES_INIT_GPIO_B_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_2_IRQ_EN +#define ES_INIT_GPIO_B_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_3_IRQ_EN +#define ES_INIT_GPIO_B_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_4_IRQ_EN +#define ES_INIT_GPIO_B_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_5_IRQ_EN +#define ES_INIT_GPIO_B_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_6_IRQ_EN +#define ES_INIT_GPIO_B_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_7_IRQ_EN +#define ES_INIT_GPIO_B_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_8_IRQ_EN +#define ES_INIT_GPIO_B_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_9_IRQ_EN +#define ES_INIT_GPIO_B_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_10_IRQ_EN +#define ES_INIT_GPIO_B_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_11_IRQ_EN +#define ES_INIT_GPIO_B_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_12_IRQ_EN +#define ES_INIT_GPIO_B_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_13_IRQ_EN +#define ES_INIT_GPIO_B_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_14_IRQ_EN +#define ES_INIT_GPIO_B_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_15_IRQ_EN +#define ES_INIT_GPIO_B_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_0_IRQ_EN +#define ES_INIT_GPIO_C_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_1_IRQ_EN +#define ES_INIT_GPIO_C_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_2_IRQ_EN +#define ES_INIT_GPIO_C_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_3_IRQ_EN +#define ES_INIT_GPIO_C_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_4_IRQ_EN +#define ES_INIT_GPIO_C_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_5_IRQ_EN +#define ES_INIT_GPIO_C_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_6_IRQ_EN +#define ES_INIT_GPIO_C_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_7_IRQ_EN +#define ES_INIT_GPIO_C_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_8_IRQ_EN +#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_9_IRQ_EN +#define ES_INIT_GPIO_C_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_10_IRQ_EN +#define ES_INIT_GPIO_C_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_11_IRQ_EN +#define ES_INIT_GPIO_C_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_12_IRQ_EN +#define ES_INIT_GPIO_C_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_13_IRQ_EN +#define ES_INIT_GPIO_C_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_14_IRQ_EN +#define ES_INIT_GPIO_C_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_15_IRQ_EN +#define ES_INIT_GPIO_C_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_0_IRQ_EN +#define ES_INIT_GPIO_D_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_1_IRQ_EN +#define ES_INIT_GPIO_D_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_2_IRQ_EN +#define ES_INIT_GPIO_D_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_3_IRQ_EN +#define ES_INIT_GPIO_D_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_4_IRQ_EN +#define ES_INIT_GPIO_D_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_5_IRQ_EN +#define ES_INIT_GPIO_D_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_6_IRQ_EN +#define ES_INIT_GPIO_D_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_7_IRQ_EN +#define ES_INIT_GPIO_D_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_8_IRQ_EN +#define ES_INIT_GPIO_D_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_9_IRQ_EN +#define ES_INIT_GPIO_D_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_10_IRQ_EN +#define ES_INIT_GPIO_D_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_11_IRQ_EN +#define ES_INIT_GPIO_D_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_12_IRQ_EN +#define ES_INIT_GPIO_D_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_13_IRQ_EN +#define ES_INIT_GPIO_D_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_14_IRQ_EN +#define ES_INIT_GPIO_D_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_15_IRQ_EN +#define ES_INIT_GPIO_D_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_0_IRQ_EN +#define ES_INIT_GPIO_E_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_1_IRQ_EN +#define ES_INIT_GPIO_E_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_2_IRQ_EN +#define ES_INIT_GPIO_E_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_3_IRQ_EN +#define ES_INIT_GPIO_E_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_4_IRQ_EN +#define ES_INIT_GPIO_E_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_5_IRQ_EN +#define ES_INIT_GPIO_E_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_6_IRQ_EN +#define ES_INIT_GPIO_E_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_7_IRQ_EN +#define ES_INIT_GPIO_E_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_8_IRQ_EN +#define ES_INIT_GPIO_E_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_9_IRQ_EN +#define ES_INIT_GPIO_E_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_10_IRQ_EN +#define ES_INIT_GPIO_E_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_11_IRQ_EN +#define ES_INIT_GPIO_E_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_12_IRQ_EN +#define ES_INIT_GPIO_E_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_13_IRQ_EN +#define ES_INIT_GPIO_E_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_14_IRQ_EN +#define ES_INIT_GPIO_E_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_15_IRQ_EN +#define ES_INIT_GPIO_E_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_0_IRQ_EN +#define ES_INIT_GPIO_F_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_1_IRQ_EN +#define ES_INIT_GPIO_F_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_2_IRQ_EN +#define ES_INIT_GPIO_F_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_3_IRQ_EN +#define ES_INIT_GPIO_F_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_4_IRQ_EN +#define ES_INIT_GPIO_F_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_5_IRQ_EN +#define ES_INIT_GPIO_F_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_6_IRQ_EN +#define ES_INIT_GPIO_F_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_7_IRQ_EN +#define ES_INIT_GPIO_F_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_8_IRQ_EN +#define ES_INIT_GPIO_F_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_9_IRQ_EN +#define ES_INIT_GPIO_F_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_10_IRQ_EN +#define ES_INIT_GPIO_F_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_11_IRQ_EN +#define ES_INIT_GPIO_F_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_12_IRQ_EN +#define ES_INIT_GPIO_F_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_13_IRQ_EN +#define ES_INIT_GPIO_F_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_14_IRQ_EN +#define ES_INIT_GPIO_F_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_15_IRQ_EN +#define ES_INIT_GPIO_F_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_0_IRQ_EN +#define ES_INIT_GPIO_G_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_1_IRQ_EN +#define ES_INIT_GPIO_G_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_2_IRQ_EN +#define ES_INIT_GPIO_G_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_3_IRQ_EN +#define ES_INIT_GPIO_G_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_4_IRQ_EN +#define ES_INIT_GPIO_G_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_5_IRQ_EN +#define ES_INIT_GPIO_G_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_6_IRQ_EN +#define ES_INIT_GPIO_G_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_7_IRQ_EN +#define ES_INIT_GPIO_G_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_8_IRQ_EN +#define ES_INIT_GPIO_G_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_9_IRQ_EN +#define ES_INIT_GPIO_G_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_10_IRQ_EN +#define ES_INIT_GPIO_G_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_11_IRQ_EN +#define ES_INIT_GPIO_G_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_12_IRQ_EN +#define ES_INIT_GPIO_G_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_13_IRQ_EN +#define ES_INIT_GPIO_G_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_14_IRQ_EN +#define ES_INIT_GPIO_G_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_15_IRQ_EN +#define ES_INIT_GPIO_G_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_0_IRQ_EN +#define ES_INIT_GPIO_H_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_1_IRQ_EN +#define ES_INIT_GPIO_H_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_2_IRQ_EN +#define ES_INIT_GPIO_H_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_3_IRQ_EN +#define ES_INIT_GPIO_H_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_4_IRQ_EN +#define ES_INIT_GPIO_H_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_5_IRQ_EN +#define ES_INIT_GPIO_H_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_6_IRQ_EN +#define ES_INIT_GPIO_H_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_7_IRQ_EN +#define ES_INIT_GPIO_H_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_8_IRQ_EN +#define ES_INIT_GPIO_H_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_9_IRQ_EN +#define ES_INIT_GPIO_H_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_10_IRQ_EN +#define ES_INIT_GPIO_H_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_11_IRQ_EN +#define ES_INIT_GPIO_H_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_12_IRQ_EN +#define ES_INIT_GPIO_H_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_13_IRQ_EN +#define ES_INIT_GPIO_H_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_14_IRQ_EN +#define ES_INIT_GPIO_H_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_15_IRQ_EN +#define ES_INIT_GPIO_H_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#endif //11111 + + + +/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/ +#if 11111 + +#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)|| \ + (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN) +#define ES_CONF_EXTI_IRQ_0 +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)|| \ + (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN) +#define ES_CONF_EXTI_IRQ_1 +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)|| \ + (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN) +#define ES_CONF_EXTI_IRQ_2 +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)|| \ + (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN) +#define ES_CONF_EXTI_IRQ_3 +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)|| \ + (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN) +#define ES_CONF_EXTI_IRQ_4 +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)|| \ + (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN) +#define ES_CONF_EXTI_IRQ_5 +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)|| \ + (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN) +#define ES_CONF_EXTI_IRQ_6 +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)|| \ + (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN) +#define ES_CONF_EXTI_IRQ_7 +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)|| \ + (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN) +#define ES_CONF_EXTI_IRQ_8 +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)|| \ + (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN) +#define ES_CONF_EXTI_IRQ_9 +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)|| \ + (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN) +#define ES_CONF_EXTI_IRQ_10 +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)|| \ + (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN) +#define ES_CONF_EXTI_IRQ_11 +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)|| \ + (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN) +#define ES_CONF_EXTI_IRQ_12 +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)|| \ + (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN) +#define ES_CONF_EXTI_IRQ_13 +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)|| \ + (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN) +#define ES_CONF_EXTI_IRQ_14 +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)|| \ + (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN) +#define ES_CONF_EXTI_IRQ_15 +#endif + +#endif //11111 + + +/*GPIO外部中断 声明*/ +#if 11111 + +#ifdef ES_CONF_EXTI_IRQ_0 +void irq_pin0_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 +void irq_pin1_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 +void irq_pin2_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 +void irq_pin3_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 +void irq_pin4_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 +void irq_pin5_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 +void irq_pin6_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 +void irq_pin7_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 +void irq_pin8_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 +void irq_pin9_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 +void irq_pin10_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 +void irq_pin11_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 +void irq_pin12_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 +void irq_pin13_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 +void irq_pin14_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 +void irq_pin15_callback(void* arg); +#endif + + +#endif //11111 + + + + +/*是否有配置的管脚*/ +#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \ + defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \ + defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \ + defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \ + defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \ + defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \ + defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \ + defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \ + defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \ + defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \ + defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \ + defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \ + defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \ + defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \ + defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \ + defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \ + defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \ + defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \ + defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \ + defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \ + defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \ + defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \ + defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \ + defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \ + defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \ + defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \ + defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \ + defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \ + defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \ + defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \ + defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \ + defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15) + +#define ES_INIT_GPIOS + +#endif + + +#ifdef ES_INIT_GPIOS + +static gpio_conf_t gpio_conf_all[] = +{ + +#ifdef ES_INIT_PIN_GPIO_A_0 + + { + ES_PIN_GPIO_A_0 , + +#ifdef ES_INIT_GPIO_A_0_MODE + ES_INIT_GPIO_A_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_0_LEVEL + ES_INIT_GPIO_A_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_0_IRQ_MODE + ES_INIT_GPIO_A_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_1 + + { + ES_PIN_GPIO_A_1 , + +#ifdef ES_INIT_GPIO_A_1_MODE + ES_INIT_GPIO_A_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_1_LEVEL + ES_INIT_GPIO_A_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_1_IRQ_MODE + ES_INIT_GPIO_A_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_2 + + { + ES_PIN_GPIO_A_2 , + +#ifdef ES_INIT_GPIO_A_2_MODE + ES_INIT_GPIO_A_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_2_LEVEL + ES_INIT_GPIO_A_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_2_IRQ_MODE + ES_INIT_GPIO_A_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_3 + + { + ES_PIN_GPIO_A_3 , + +#ifdef ES_INIT_GPIO_A_3_MODE + ES_INIT_GPIO_A_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_3_LEVEL + ES_INIT_GPIO_A_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_3_IRQ_MODE + ES_INIT_GPIO_A_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_4 + + { + ES_PIN_GPIO_A_4 , + +#ifdef ES_INIT_GPIO_A_4_MODE + ES_INIT_GPIO_A_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_4_LEVEL + ES_INIT_GPIO_A_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_4_IRQ_MODE + ES_INIT_GPIO_A_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_5 + + { + ES_PIN_GPIO_A_5 , + +#ifdef ES_INIT_GPIO_A_5_MODE + ES_INIT_GPIO_A_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_5_LEVEL + ES_INIT_GPIO_A_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_5_IRQ_MODE + ES_INIT_GPIO_A_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_6 + + { + ES_PIN_GPIO_A_6 , + +#ifdef ES_INIT_GPIO_A_6_MODE + ES_INIT_GPIO_A_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_6_LEVEL + ES_INIT_GPIO_A_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_6_IRQ_MODE + ES_INIT_GPIO_A_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_7 + + { + ES_PIN_GPIO_A_7 , + +#ifdef ES_INIT_GPIO_A_7_MODE + ES_INIT_GPIO_A_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_7_LEVEL + ES_INIT_GPIO_A_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_7_IRQ_MODE + ES_INIT_GPIO_A_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_8 + + { + ES_PIN_GPIO_A_8 , + +#ifdef ES_INIT_GPIO_A_8_MODE + ES_INIT_GPIO_A_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_8_LEVEL + ES_INIT_GPIO_A_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_8_IRQ_MODE + ES_INIT_GPIO_A_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_9 + + { + ES_PIN_GPIO_A_9 , + +#ifdef ES_INIT_GPIO_A_9_MODE + ES_INIT_GPIO_A_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_9_LEVEL + ES_INIT_GPIO_A_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_9_IRQ_MODE + ES_INIT_GPIO_A_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_10 + + { + ES_PIN_GPIO_A_10 , + +#ifdef ES_INIT_GPIO_A_10_MODE + ES_INIT_GPIO_A_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_10_LEVEL + ES_INIT_GPIO_A_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_10_IRQ_MODE + ES_INIT_GPIO_A_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_11 + + { + ES_PIN_GPIO_A_11 , + +#ifdef ES_INIT_GPIO_A_11_MODE + ES_INIT_GPIO_A_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_11_LEVEL + ES_INIT_GPIO_A_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_11_IRQ_MODE + ES_INIT_GPIO_A_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_12 + + { + ES_PIN_GPIO_A_12 , + +#ifdef ES_INIT_GPIO_A_12_MODE + ES_INIT_GPIO_A_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_12_LEVEL + ES_INIT_GPIO_A_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_12_IRQ_MODE + ES_INIT_GPIO_A_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_13 + + { + ES_PIN_GPIO_A_13 , + +#ifdef ES_INIT_GPIO_A_13_MODE + ES_INIT_GPIO_A_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_13_LEVEL + ES_INIT_GPIO_A_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_13_IRQ_MODE + ES_INIT_GPIO_A_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_14 + + { + ES_PIN_GPIO_A_14 , + +#ifdef ES_INIT_GPIO_A_14_MODE + ES_INIT_GPIO_A_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_14_LEVEL + ES_INIT_GPIO_A_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_14_IRQ_MODE + ES_INIT_GPIO_A_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_15 + + { + ES_PIN_GPIO_A_15 , + +#ifdef ES_INIT_GPIO_A_15_MODE + ES_INIT_GPIO_A_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_15_LEVEL + ES_INIT_GPIO_A_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_15_IRQ_MODE + ES_INIT_GPIO_A_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_0 + + { + ES_PIN_GPIO_B_0 , + +#ifdef ES_INIT_GPIO_B_0_MODE + ES_INIT_GPIO_B_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_0_LEVEL + ES_INIT_GPIO_B_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_0_IRQ_MODE + ES_INIT_GPIO_B_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_1 + + { + ES_PIN_GPIO_B_1 , + +#ifdef ES_INIT_GPIO_B_1_MODE + ES_INIT_GPIO_B_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_1_LEVEL + ES_INIT_GPIO_B_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_1_IRQ_MODE + ES_INIT_GPIO_B_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_2 + + { + ES_PIN_GPIO_B_2 , + +#ifdef ES_INIT_GPIO_B_2_MODE + ES_INIT_GPIO_B_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_2_LEVEL + ES_INIT_GPIO_B_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_2_IRQ_MODE + ES_INIT_GPIO_B_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_3 + + { + ES_PIN_GPIO_B_3 , + +#ifdef ES_INIT_GPIO_B_3_MODE + ES_INIT_GPIO_B_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_3_LEVEL + ES_INIT_GPIO_B_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_3_IRQ_MODE + ES_INIT_GPIO_B_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_4 + + { + ES_PIN_GPIO_B_4 , + +#ifdef ES_INIT_GPIO_B_4_MODE + ES_INIT_GPIO_B_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_4_LEVEL + ES_INIT_GPIO_B_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_4_IRQ_MODE + ES_INIT_GPIO_B_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_5 + + { + ES_PIN_GPIO_B_5 , + +#ifdef ES_INIT_GPIO_B_5_MODE + ES_INIT_GPIO_B_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_5_LEVEL + ES_INIT_GPIO_B_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_5_IRQ_MODE + ES_INIT_GPIO_B_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_6 + + { + ES_PIN_GPIO_B_6 , + +#ifdef ES_INIT_GPIO_B_6_MODE + ES_INIT_GPIO_B_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_6_LEVEL + ES_INIT_GPIO_B_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_6_IRQ_MODE + ES_INIT_GPIO_B_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_7 + + { + ES_PIN_GPIO_B_7 , + +#ifdef ES_INIT_GPIO_B_7_MODE + ES_INIT_GPIO_B_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_7_LEVEL + ES_INIT_GPIO_B_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_7_IRQ_MODE + ES_INIT_GPIO_B_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_8 + + { + ES_PIN_GPIO_B_8 , + +#ifdef ES_INIT_GPIO_B_8_MODE + ES_INIT_GPIO_B_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_8_LEVEL + ES_INIT_GPIO_B_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_8_IRQ_MODE + ES_INIT_GPIO_B_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_9 + + { + ES_PIN_GPIO_B_9 , + +#ifdef ES_INIT_GPIO_B_9_MODE + ES_INIT_GPIO_B_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_9_LEVEL + ES_INIT_GPIO_B_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_9_IRQ_MODE + ES_INIT_GPIO_B_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_10 + + { + ES_PIN_GPIO_B_10 , + +#ifdef ES_INIT_GPIO_B_10_MODE + ES_INIT_GPIO_B_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_10_LEVEL + ES_INIT_GPIO_B_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_10_IRQ_MODE + ES_INIT_GPIO_B_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_11 + + { + ES_PIN_GPIO_B_11 , + +#ifdef ES_INIT_GPIO_B_11_MODE + ES_INIT_GPIO_B_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_11_LEVEL + ES_INIT_GPIO_B_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_11_IRQ_MODE + ES_INIT_GPIO_B_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_12 + + { + ES_PIN_GPIO_B_12 , + +#ifdef ES_INIT_GPIO_B_12_MODE + ES_INIT_GPIO_B_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_12_LEVEL + ES_INIT_GPIO_B_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_12_IRQ_MODE + ES_INIT_GPIO_B_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_13 + + { + ES_PIN_GPIO_B_13 , + +#ifdef ES_INIT_GPIO_B_13_MODE + ES_INIT_GPIO_B_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_13_LEVEL + ES_INIT_GPIO_B_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_13_IRQ_MODE + ES_INIT_GPIO_B_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_14 + + { + ES_PIN_GPIO_B_14 , + +#ifdef ES_INIT_GPIO_B_14_MODE + ES_INIT_GPIO_B_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_14_LEVEL + ES_INIT_GPIO_B_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_14_IRQ_MODE + ES_INIT_GPIO_B_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_15 + + { + ES_PIN_GPIO_B_15 , + +#ifdef ES_INIT_GPIO_B_15_MODE + ES_INIT_GPIO_B_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_15_LEVEL + ES_INIT_GPIO_B_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_15_IRQ_MODE + ES_INIT_GPIO_B_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_0 + + { + ES_PIN_GPIO_C_0 , + +#ifdef ES_INIT_GPIO_C_0_MODE + ES_INIT_GPIO_C_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_0_LEVEL + ES_INIT_GPIO_C_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_0_IRQ_MODE + ES_INIT_GPIO_C_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_1 + + { + ES_PIN_GPIO_C_1 , + +#ifdef ES_INIT_GPIO_C_1_MODE + ES_INIT_GPIO_C_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_1_LEVEL + ES_INIT_GPIO_C_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_1_IRQ_MODE + ES_INIT_GPIO_C_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_2 + + { + ES_PIN_GPIO_C_2 , + +#ifdef ES_INIT_GPIO_C_2_MODE + ES_INIT_GPIO_C_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_2_LEVEL + ES_INIT_GPIO_C_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_2_IRQ_MODE + ES_INIT_GPIO_C_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_3 + + { + ES_PIN_GPIO_C_3 , + +#ifdef ES_INIT_GPIO_C_3_MODE + ES_INIT_GPIO_C_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_3_LEVEL + ES_INIT_GPIO_C_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_3_IRQ_MODE + ES_INIT_GPIO_C_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_4 + + { + ES_PIN_GPIO_C_4 , + +#ifdef ES_INIT_GPIO_C_4_MODE + ES_INIT_GPIO_C_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_4_LEVEL + ES_INIT_GPIO_C_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_4_IRQ_MODE + ES_INIT_GPIO_C_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_5 + + { + ES_PIN_GPIO_C_5 , + +#ifdef ES_INIT_GPIO_C_5_MODE + ES_INIT_GPIO_C_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_5_LEVEL + ES_INIT_GPIO_C_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_5_IRQ_MODE + ES_INIT_GPIO_C_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_6 + + { + ES_PIN_GPIO_C_6 , + +#ifdef ES_INIT_GPIO_C_6_MODE + ES_INIT_GPIO_C_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_6_LEVEL + ES_INIT_GPIO_C_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_6_IRQ_MODE + ES_INIT_GPIO_C_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_7 + + { + ES_PIN_GPIO_C_7 , + +#ifdef ES_INIT_GPIO_C_7_MODE + ES_INIT_GPIO_C_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_7_LEVEL + ES_INIT_GPIO_C_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_7_IRQ_MODE + ES_INIT_GPIO_C_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_8 + + { + ES_PIN_GPIO_C_8 , + +#ifdef ES_INIT_GPIO_C_8_MODE + ES_INIT_GPIO_C_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_8_LEVEL + ES_INIT_GPIO_C_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_8_IRQ_MODE + ES_INIT_GPIO_C_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_9 + + { + ES_PIN_GPIO_C_9 , + +#ifdef ES_INIT_GPIO_C_9_MODE + ES_INIT_GPIO_C_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_9_LEVEL + ES_INIT_GPIO_C_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_9_IRQ_MODE + ES_INIT_GPIO_C_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_10 + + { + ES_PIN_GPIO_C_10 , + +#ifdef ES_INIT_GPIO_C_10_MODE + ES_INIT_GPIO_C_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_10_LEVEL + ES_INIT_GPIO_C_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_10_IRQ_MODE + ES_INIT_GPIO_C_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_11 + + { + ES_PIN_GPIO_C_11 , + +#ifdef ES_INIT_GPIO_C_11_MODE + ES_INIT_GPIO_C_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_11_LEVEL + ES_INIT_GPIO_C_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_11_IRQ_MODE + ES_INIT_GPIO_C_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_12 + + { + ES_PIN_GPIO_C_12 , + +#ifdef ES_INIT_GPIO_C_12_MODE + ES_INIT_GPIO_C_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_12_LEVEL + ES_INIT_GPIO_C_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_12_IRQ_MODE + ES_INIT_GPIO_C_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_13 + + { + ES_PIN_GPIO_C_13 , + +#ifdef ES_INIT_GPIO_C_13_MODE + ES_INIT_GPIO_C_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_13_LEVEL + ES_INIT_GPIO_C_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_13_IRQ_MODE + ES_INIT_GPIO_C_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_14 + + { + ES_PIN_GPIO_C_14 , + +#ifdef ES_INIT_GPIO_C_14_MODE + ES_INIT_GPIO_C_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_14_LEVEL + ES_INIT_GPIO_C_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_14_IRQ_MODE + ES_INIT_GPIO_C_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_15 + + { + ES_PIN_GPIO_C_15 , + +#ifdef ES_INIT_GPIO_C_15_MODE + ES_INIT_GPIO_C_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_15_LEVEL + ES_INIT_GPIO_C_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_15_IRQ_MODE + ES_INIT_GPIO_C_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_0 + + { + ES_PIN_GPIO_D_0 , + +#ifdef ES_INIT_GPIO_D_0_MODE + ES_INIT_GPIO_D_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_0_LEVEL + ES_INIT_GPIO_D_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_0_IRQ_MODE + ES_INIT_GPIO_D_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_1 + + { + ES_PIN_GPIO_D_1 , + +#ifdef ES_INIT_GPIO_D_1_MODE + ES_INIT_GPIO_D_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_1_LEVEL + ES_INIT_GPIO_D_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_1_IRQ_MODE + ES_INIT_GPIO_D_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_2 + + { + ES_PIN_GPIO_D_2 , + +#ifdef ES_INIT_GPIO_D_2_MODE + ES_INIT_GPIO_D_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_2_LEVEL + ES_INIT_GPIO_D_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_2_IRQ_MODE + ES_INIT_GPIO_D_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_3 + + { + ES_PIN_GPIO_D_3 , + +#ifdef ES_INIT_GPIO_D_3_MODE + ES_INIT_GPIO_D_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_3_LEVEL + ES_INIT_GPIO_D_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_3_IRQ_MODE + ES_INIT_GPIO_D_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_4 + + { + ES_PIN_GPIO_D_4 , + +#ifdef ES_INIT_GPIO_D_4_MODE + ES_INIT_GPIO_D_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_4_LEVEL + ES_INIT_GPIO_D_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_4_IRQ_MODE + ES_INIT_GPIO_D_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_5 + + { + ES_PIN_GPIO_D_5 , + +#ifdef ES_INIT_GPIO_D_5_MODE + ES_INIT_GPIO_D_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_5_LEVEL + ES_INIT_GPIO_D_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_5_IRQ_MODE + ES_INIT_GPIO_D_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_6 + + { + ES_PIN_GPIO_D_6 , + +#ifdef ES_INIT_GPIO_D_6_MODE + ES_INIT_GPIO_D_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_6_LEVEL + ES_INIT_GPIO_D_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_6_IRQ_MODE + ES_INIT_GPIO_D_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_7 + + { + ES_PIN_GPIO_D_7 , + +#ifdef ES_INIT_GPIO_D_7_MODE + ES_INIT_GPIO_D_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_7_LEVEL + ES_INIT_GPIO_D_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_7_IRQ_MODE + ES_INIT_GPIO_D_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_8 + + { + ES_PIN_GPIO_D_8 , + +#ifdef ES_INIT_GPIO_D_8_MODE + ES_INIT_GPIO_D_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_8_LEVEL + ES_INIT_GPIO_D_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_8_IRQ_MODE + ES_INIT_GPIO_D_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_9 + + { + ES_PIN_GPIO_D_9 , + +#ifdef ES_INIT_GPIO_D_9_MODE + ES_INIT_GPIO_D_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_9_LEVEL + ES_INIT_GPIO_D_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_9_IRQ_MODE + ES_INIT_GPIO_D_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_10 + + { + ES_PIN_GPIO_D_10 , + +#ifdef ES_INIT_GPIO_D_10_MODE + ES_INIT_GPIO_D_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_10_LEVEL + ES_INIT_GPIO_D_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_10_IRQ_MODE + ES_INIT_GPIO_D_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_11 + + { + ES_PIN_GPIO_D_11 , + +#ifdef ES_INIT_GPIO_D_11_MODE + ES_INIT_GPIO_D_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_11_LEVEL + ES_INIT_GPIO_D_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_11_IRQ_MODE + ES_INIT_GPIO_D_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_12 + + { + ES_PIN_GPIO_D_12 , + +#ifdef ES_INIT_GPIO_D_12_MODE + ES_INIT_GPIO_D_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_12_LEVEL + ES_INIT_GPIO_D_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_12_IRQ_MODE + ES_INIT_GPIO_D_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_13 + + { + ES_PIN_GPIO_D_13 , + +#ifdef ES_INIT_GPIO_D_13_MODE + ES_INIT_GPIO_D_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_13_LEVEL + ES_INIT_GPIO_D_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_13_IRQ_MODE + ES_INIT_GPIO_D_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_14 + + { + ES_PIN_GPIO_D_14 , + +#ifdef ES_INIT_GPIO_D_14_MODE + ES_INIT_GPIO_D_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_14_LEVEL + ES_INIT_GPIO_D_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_14_IRQ_MODE + ES_INIT_GPIO_D_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_15 + + { + ES_PIN_GPIO_D_15 , + +#ifdef ES_INIT_GPIO_D_15_MODE + ES_INIT_GPIO_D_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_15_LEVEL + ES_INIT_GPIO_D_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_15_IRQ_MODE + ES_INIT_GPIO_D_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_0 + + { + ES_PIN_GPIO_E_0 , + +#ifdef ES_INIT_GPIO_E_0_MODE + ES_INIT_GPIO_E_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_0_LEVEL + ES_INIT_GPIO_E_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_0_IRQ_MODE + ES_INIT_GPIO_E_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_1 + + { + ES_PIN_GPIO_E_1 , + +#ifdef ES_INIT_GPIO_E_1_MODE + ES_INIT_GPIO_E_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_1_LEVEL + ES_INIT_GPIO_E_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_1_IRQ_MODE + ES_INIT_GPIO_E_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_2 + + { + ES_PIN_GPIO_E_2 , + +#ifdef ES_INIT_GPIO_E_2_MODE + ES_INIT_GPIO_E_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_2_LEVEL + ES_INIT_GPIO_E_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_2_IRQ_MODE + ES_INIT_GPIO_E_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_3 + + { + ES_PIN_GPIO_E_3 , + +#ifdef ES_INIT_GPIO_E_3_MODE + ES_INIT_GPIO_E_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_3_LEVEL + ES_INIT_GPIO_E_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_3_IRQ_MODE + ES_INIT_GPIO_E_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_4 + + { + ES_PIN_GPIO_E_4 , + +#ifdef ES_INIT_GPIO_E_4_MODE + ES_INIT_GPIO_E_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_4_LEVEL + ES_INIT_GPIO_E_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_4_IRQ_MODE + ES_INIT_GPIO_E_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_5 + + { + ES_PIN_GPIO_E_5 , + +#ifdef ES_INIT_GPIO_E_5_MODE + ES_INIT_GPIO_E_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_5_LEVEL + ES_INIT_GPIO_E_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_5_IRQ_MODE + ES_INIT_GPIO_E_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_6 + + { + ES_PIN_GPIO_E_6 , + +#ifdef ES_INIT_GPIO_E_6_MODE + ES_INIT_GPIO_E_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_6_LEVEL + ES_INIT_GPIO_E_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_6_IRQ_MODE + ES_INIT_GPIO_E_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_7 + + { + ES_PIN_GPIO_E_7 , + +#ifdef ES_INIT_GPIO_E_7_MODE + ES_INIT_GPIO_E_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_7_LEVEL + ES_INIT_GPIO_E_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_7_IRQ_MODE + ES_INIT_GPIO_E_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_8 + + { + ES_PIN_GPIO_E_8 , + +#ifdef ES_INIT_GPIO_E_8_MODE + ES_INIT_GPIO_E_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_8_LEVEL + ES_INIT_GPIO_E_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_8_IRQ_MODE + ES_INIT_GPIO_E_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_9 + + { + ES_PIN_GPIO_E_9 , + +#ifdef ES_INIT_GPIO_E_9_MODE + ES_INIT_GPIO_E_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_9_LEVEL + ES_INIT_GPIO_E_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_9_IRQ_MODE + ES_INIT_GPIO_E_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_10 + + { + ES_PIN_GPIO_E_10 , + +#ifdef ES_INIT_GPIO_E_10_MODE + ES_INIT_GPIO_E_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_10_LEVEL + ES_INIT_GPIO_E_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_10_IRQ_MODE + ES_INIT_GPIO_E_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_11 + + { + ES_PIN_GPIO_E_11 , + +#ifdef ES_INIT_GPIO_E_11_MODE + ES_INIT_GPIO_E_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_11_LEVEL + ES_INIT_GPIO_E_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_11_IRQ_MODE + ES_INIT_GPIO_E_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_12 + + { + ES_PIN_GPIO_E_12 , + +#ifdef ES_INIT_GPIO_E_12_MODE + ES_INIT_GPIO_E_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_12_LEVEL + ES_INIT_GPIO_E_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_12_IRQ_MODE + ES_INIT_GPIO_E_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_13 + + { + ES_PIN_GPIO_E_13 , + +#ifdef ES_INIT_GPIO_E_13_MODE + ES_INIT_GPIO_E_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_13_LEVEL + ES_INIT_GPIO_E_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_13_IRQ_MODE + ES_INIT_GPIO_E_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_14 + + { + ES_PIN_GPIO_E_14 , + +#ifdef ES_INIT_GPIO_E_14_MODE + ES_INIT_GPIO_E_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_14_LEVEL + ES_INIT_GPIO_E_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_14_IRQ_MODE + ES_INIT_GPIO_E_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_15 + + { + ES_PIN_GPIO_E_15 , + +#ifdef ES_INIT_GPIO_E_15_MODE + ES_INIT_GPIO_E_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_15_LEVEL + ES_INIT_GPIO_E_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_15_IRQ_MODE + ES_INIT_GPIO_E_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_0 + + { + ES_PIN_GPIO_F_0 , + +#ifdef ES_INIT_GPIO_F_0_MODE + ES_INIT_GPIO_F_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_0_LEVEL + ES_INIT_GPIO_F_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_0_IRQ_MODE + ES_INIT_GPIO_F_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_1 + + { + ES_PIN_GPIO_F_1 , + +#ifdef ES_INIT_GPIO_F_1_MODE + ES_INIT_GPIO_F_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_1_LEVEL + ES_INIT_GPIO_F_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_1_IRQ_MODE + ES_INIT_GPIO_F_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_2 + + { + ES_PIN_GPIO_F_2 , + +#ifdef ES_INIT_GPIO_F_2_MODE + ES_INIT_GPIO_F_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_2_LEVEL + ES_INIT_GPIO_F_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_2_IRQ_MODE + ES_INIT_GPIO_F_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_3 + + { + ES_PIN_GPIO_F_3 , + +#ifdef ES_INIT_GPIO_F_3_MODE + ES_INIT_GPIO_F_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_3_LEVEL + ES_INIT_GPIO_F_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_3_IRQ_MODE + ES_INIT_GPIO_F_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_4 + + { + ES_PIN_GPIO_F_4 , + +#ifdef ES_INIT_GPIO_F_4_MODE + ES_INIT_GPIO_F_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_4_LEVEL + ES_INIT_GPIO_F_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_4_IRQ_MODE + ES_INIT_GPIO_F_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_5 + + { + ES_PIN_GPIO_F_5 , + +#ifdef ES_INIT_GPIO_F_5_MODE + ES_INIT_GPIO_F_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_5_LEVEL + ES_INIT_GPIO_F_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_5_IRQ_MODE + ES_INIT_GPIO_F_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_6 + + { + ES_PIN_GPIO_F_6 , + +#ifdef ES_INIT_GPIO_F_6_MODE + ES_INIT_GPIO_F_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_6_LEVEL + ES_INIT_GPIO_F_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_6_IRQ_MODE + ES_INIT_GPIO_F_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_7 + + { + ES_PIN_GPIO_F_7 , + +#ifdef ES_INIT_GPIO_F_7_MODE + ES_INIT_GPIO_F_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_7_LEVEL + ES_INIT_GPIO_F_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_7_IRQ_MODE + ES_INIT_GPIO_F_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_8 + + { + ES_PIN_GPIO_F_8 , + +#ifdef ES_INIT_GPIO_F_8_MODE + ES_INIT_GPIO_F_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_8_LEVEL + ES_INIT_GPIO_F_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_8_IRQ_MODE + ES_INIT_GPIO_F_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_9 + + { + ES_PIN_GPIO_F_9 , + +#ifdef ES_INIT_GPIO_F_9_MODE + ES_INIT_GPIO_F_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_9_LEVEL + ES_INIT_GPIO_F_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_9_IRQ_MODE + ES_INIT_GPIO_F_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_10 + + { + ES_PIN_GPIO_F_10 , + +#ifdef ES_INIT_GPIO_F_10_MODE + ES_INIT_GPIO_F_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_10_LEVEL + ES_INIT_GPIO_F_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_10_IRQ_MODE + ES_INIT_GPIO_F_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_11 + + { + ES_PIN_GPIO_F_11 , + +#ifdef ES_INIT_GPIO_F_11_MODE + ES_INIT_GPIO_F_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_11_LEVEL + ES_INIT_GPIO_F_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_11_IRQ_MODE + ES_INIT_GPIO_F_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_12 + + { + ES_PIN_GPIO_F_12 , + +#ifdef ES_INIT_GPIO_F_12_MODE + ES_INIT_GPIO_F_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_12_LEVEL + ES_INIT_GPIO_F_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_12_IRQ_MODE + ES_INIT_GPIO_F_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_13 + + { + ES_PIN_GPIO_F_13 , + +#ifdef ES_INIT_GPIO_F_13_MODE + ES_INIT_GPIO_F_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_13_LEVEL + ES_INIT_GPIO_F_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_13_IRQ_MODE + ES_INIT_GPIO_F_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_14 + + { + ES_PIN_GPIO_F_14 , + +#ifdef ES_INIT_GPIO_F_14_MODE + ES_INIT_GPIO_F_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_14_LEVEL + ES_INIT_GPIO_F_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_14_IRQ_MODE + ES_INIT_GPIO_F_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_15 + + { + ES_PIN_GPIO_F_15 , + +#ifdef ES_INIT_GPIO_F_15_MODE + ES_INIT_GPIO_F_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_15_LEVEL + ES_INIT_GPIO_F_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_15_IRQ_MODE + ES_INIT_GPIO_F_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_0 + + { + ES_PIN_GPIO_G_0 , + +#ifdef ES_INIT_GPIO_G_0_MODE + ES_INIT_GPIO_G_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_0_LEVEL + ES_INIT_GPIO_G_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_0_IRQ_MODE + ES_INIT_GPIO_G_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_1 + + { + ES_PIN_GPIO_G_1 , + +#ifdef ES_INIT_GPIO_G_1_MODE + ES_INIT_GPIO_G_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_1_LEVEL + ES_INIT_GPIO_G_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_1_IRQ_MODE + ES_INIT_GPIO_G_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_2 + + { + ES_PIN_GPIO_G_2 , + +#ifdef ES_INIT_GPIO_G_2_MODE + ES_INIT_GPIO_G_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_2_LEVEL + ES_INIT_GPIO_G_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_2_IRQ_MODE + ES_INIT_GPIO_G_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_3 + + { + ES_PIN_GPIO_G_3 , + +#ifdef ES_INIT_GPIO_G_3_MODE + ES_INIT_GPIO_G_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_3_LEVEL + ES_INIT_GPIO_G_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_3_IRQ_MODE + ES_INIT_GPIO_G_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_4 + + { + ES_PIN_GPIO_G_4 , + +#ifdef ES_INIT_GPIO_G_4_MODE + ES_INIT_GPIO_G_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_4_LEVEL + ES_INIT_GPIO_G_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_4_IRQ_MODE + ES_INIT_GPIO_G_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_5 + + { + ES_PIN_GPIO_G_5 , + +#ifdef ES_INIT_GPIO_G_5_MODE + ES_INIT_GPIO_G_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_5_LEVEL + ES_INIT_GPIO_G_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_5_IRQ_MODE + ES_INIT_GPIO_G_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_6 + + { + ES_PIN_GPIO_G_6 , + +#ifdef ES_INIT_GPIO_G_6_MODE + ES_INIT_GPIO_G_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_6_LEVEL + ES_INIT_GPIO_G_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_6_IRQ_MODE + ES_INIT_GPIO_G_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_7 + + { + ES_PIN_GPIO_G_7 , + +#ifdef ES_INIT_GPIO_G_7_MODE + ES_INIT_GPIO_G_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_7_LEVEL + ES_INIT_GPIO_G_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_7_IRQ_MODE + ES_INIT_GPIO_G_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_8 + + { + ES_PIN_GPIO_G_8 , + +#ifdef ES_INIT_GPIO_G_8_MODE + ES_INIT_GPIO_G_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_8_LEVEL + ES_INIT_GPIO_G_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_8_IRQ_MODE + ES_INIT_GPIO_G_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_9 + + { + ES_PIN_GPIO_G_9 , + +#ifdef ES_INIT_GPIO_G_9_MODE + ES_INIT_GPIO_G_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_9_LEVEL + ES_INIT_GPIO_G_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_9_IRQ_MODE + ES_INIT_GPIO_G_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_10 + + { + ES_PIN_GPIO_G_10 , + +#ifdef ES_INIT_GPIO_G_10_MODE + ES_INIT_GPIO_G_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_10_LEVEL + ES_INIT_GPIO_G_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_10_IRQ_MODE + ES_INIT_GPIO_G_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_11 + + { + ES_PIN_GPIO_G_11 , + +#ifdef ES_INIT_GPIO_G_11_MODE + ES_INIT_GPIO_G_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_11_LEVEL + ES_INIT_GPIO_G_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_11_IRQ_MODE + ES_INIT_GPIO_G_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_12 + + { + ES_PIN_GPIO_G_12 , + +#ifdef ES_INIT_GPIO_G_12_MODE + ES_INIT_GPIO_G_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_12_LEVEL + ES_INIT_GPIO_G_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_12_IRQ_MODE + ES_INIT_GPIO_G_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_13 + + { + ES_PIN_GPIO_G_13 , + +#ifdef ES_INIT_GPIO_G_13_MODE + ES_INIT_GPIO_G_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_13_LEVEL + ES_INIT_GPIO_G_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_13_IRQ_MODE + ES_INIT_GPIO_G_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_14 + + { + ES_PIN_GPIO_G_14 , + +#ifdef ES_INIT_GPIO_G_14_MODE + ES_INIT_GPIO_G_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_14_LEVEL + ES_INIT_GPIO_G_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_14_IRQ_MODE + ES_INIT_GPIO_G_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_15 + + { + ES_PIN_GPIO_G_15 , + +#ifdef ES_INIT_GPIO_G_15_MODE + ES_INIT_GPIO_G_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_15_LEVEL + ES_INIT_GPIO_G_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_15_IRQ_MODE + ES_INIT_GPIO_G_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_0 + + { + ES_PIN_GPIO_H_0 , + +#ifdef ES_INIT_GPIO_H_0_MODE + ES_INIT_GPIO_H_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_0_LEVEL + ES_INIT_GPIO_H_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_0_IRQ_MODE + ES_INIT_GPIO_H_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_1 + + { + ES_PIN_GPIO_H_1 , + +#ifdef ES_INIT_GPIO_H_1_MODE + ES_INIT_GPIO_H_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_1_LEVEL + ES_INIT_GPIO_H_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_1_IRQ_MODE + ES_INIT_GPIO_H_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_2 + + { + ES_PIN_GPIO_H_2 , + +#ifdef ES_INIT_GPIO_H_2_MODE + ES_INIT_GPIO_H_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_2_LEVEL + ES_INIT_GPIO_H_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_2_IRQ_MODE + ES_INIT_GPIO_H_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_3 + + { + ES_PIN_GPIO_H_3 , + +#ifdef ES_INIT_GPIO_H_3_MODE + ES_INIT_GPIO_H_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_3_LEVEL + ES_INIT_GPIO_H_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_3_IRQ_MODE + ES_INIT_GPIO_H_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_4 + + { + ES_PIN_GPIO_H_4 , + +#ifdef ES_INIT_GPIO_H_4_MODE + ES_INIT_GPIO_H_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_4_LEVEL + ES_INIT_GPIO_H_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_4_IRQ_MODE + ES_INIT_GPIO_H_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_5 + + { + ES_PIN_GPIO_H_5 , + +#ifdef ES_INIT_GPIO_H_5_MODE + ES_INIT_GPIO_H_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_5_LEVEL + ES_INIT_GPIO_H_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_5_IRQ_MODE + ES_INIT_GPIO_H_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_6 + + { + ES_PIN_GPIO_H_6 , + +#ifdef ES_INIT_GPIO_H_6_MODE + ES_INIT_GPIO_H_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_6_LEVEL + ES_INIT_GPIO_H_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_6_IRQ_MODE + ES_INIT_GPIO_H_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_7 + + { + ES_PIN_GPIO_H_7 , + +#ifdef ES_INIT_GPIO_H_7_MODE + ES_INIT_GPIO_H_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_7_LEVEL + ES_INIT_GPIO_H_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_7_IRQ_MODE + ES_INIT_GPIO_H_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_8 + + { + ES_PIN_GPIO_H_8 , + +#ifdef ES_INIT_GPIO_H_8_MODE + ES_INIT_GPIO_H_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_8_LEVEL + ES_INIT_GPIO_H_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_8_IRQ_MODE + ES_INIT_GPIO_H_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_9 + + { + ES_PIN_GPIO_H_9 , + +#ifdef ES_INIT_GPIO_H_9_MODE + ES_INIT_GPIO_H_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_9_LEVEL + ES_INIT_GPIO_H_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_9_IRQ_MODE + ES_INIT_GPIO_H_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_10 + + { + ES_PIN_GPIO_H_10 , + +#ifdef ES_INIT_GPIO_H_10_MODE + ES_INIT_GPIO_H_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_10_LEVEL + ES_INIT_GPIO_H_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_10_IRQ_MODE + ES_INIT_GPIO_H_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_11 + + { + ES_PIN_GPIO_H_11 , + +#ifdef ES_INIT_GPIO_H_11_MODE + ES_INIT_GPIO_H_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_11_LEVEL + ES_INIT_GPIO_H_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_11_IRQ_MODE + ES_INIT_GPIO_H_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_12 + + { + ES_PIN_GPIO_H_12 , + +#ifdef ES_INIT_GPIO_H_12_MODE + ES_INIT_GPIO_H_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_12_LEVEL + ES_INIT_GPIO_H_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_12_IRQ_MODE + ES_INIT_GPIO_H_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_13 + + { + ES_PIN_GPIO_H_13 , + +#ifdef ES_INIT_GPIO_H_13_MODE + ES_INIT_GPIO_H_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_13_LEVEL + ES_INIT_GPIO_H_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_13_IRQ_MODE + ES_INIT_GPIO_H_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_14 + + { + ES_PIN_GPIO_H_14 , + +#ifdef ES_INIT_GPIO_H_14_MODE + ES_INIT_GPIO_H_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_14_LEVEL + ES_INIT_GPIO_H_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_14_IRQ_MODE + ES_INIT_GPIO_H_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_15 + + { + ES_PIN_GPIO_H_15 , + +#ifdef ES_INIT_GPIO_H_15_MODE + ES_INIT_GPIO_H_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_15_LEVEL + ES_INIT_GPIO_H_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_15_IRQ_MODE + ES_INIT_GPIO_H_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + + + +}; + +#endif + + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_hwtimer.h new file mode 100644 index 0000000000..18f2ff8aa0 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_hwtimer.h @@ -0,0 +1,102 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_HWTIMER_H__ +#define __ES_CONF_INFO_HWTIMER_H__ + +#include <ald_cmu.h> +#include <ald_timer.h> + +#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP +#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW + +/* HWTIMER 配置 */ + +/* codes_main */ + + + +#ifndef ES_AD16C4T0_HWTIMER_MODE +#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_AD16C4T1_HWTIMER_MODE +#define ES_AD16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T0_HWTIMER_MODE +#define ES_GP32C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T1_HWTIMER_MODE +#define ES_GP32C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T0_HWTIMER_MODE +#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T1_HWTIMER_MODE +#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T0_HWTIMER_MODE +#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T1_HWTIMER_MODE +#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + + + + +#define ES_AD16C4T0_HWTIMER_PRES 1 +#define ES_AD16C4T1_HWTIMER_PRES 1 +#define ES_GP16C4T0_HWTIMER_PRES 1 +#define ES_GP16C4T1_HWTIMER_PRES 1 +#define ES_GP32C4T0_HWTIMER_PRES 1 +#define ES_GP32C4T1_HWTIMER_PRES 1 +#define ES_BS16T0_HWTIMER_PRES 1 +#define ES_BS16T1_HWTIMER_PRES 1 + +#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER +#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_HWTIMER +#define ES_DEVICE_NAME_AD16C4T1_HWTIMER "timer1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_HWTIMER +#define ES_DEVICE_NAME_GP32C4T0_HWTIMER "timer2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_HWTIMER +#define ES_DEVICE_NAME_GP32C4T1_HWTIMER "timer3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER +#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER +#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer5" +#endif +#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER +#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer6" +#endif +#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER +#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer7" +#endif + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_i2c.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_i2c.h new file mode 100644 index 0000000000..8a488bfe60 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_i2c.h @@ -0,0 +1,95 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_I2C_H__ +#define __ES_CONF_INFO_I2C_H__ + +#include "es_conf_info_map.h" +#include <ald_i2c.h> +#include <ald_gpio.h> +#include <rtdbg.h> + +#define ES_C_I2C_STRETCH I2C_NOSTRETCH_DISABLE +#define ES_C_I2C_NO_STRETCH I2C_NOSTRETCH_ENABLE + +#define ES_C_I2C_GENERALCALL I2C_GENERALCALL_ENABLE +#define ES_C_I2C_NO_GENERALCALL I2C_GENERALCALL_DISABLE + + +#define ES_C_I2C_ADDR_7_MODE I2C_ADDR_7BIT +#define ES_C_I2C_ADDR_10_MODE I2C_ADDR_10BIT + + +/* I2C 配置 */ + + + +/* codes_main */ + + + + + +#ifndef ES_DEVICE_NAME_I2C0 +#define ES_DEVICE_NAME_I2C0 "i2c0" +#endif + +#ifndef ES_DEVICE_NAME_I2C1 +#define ES_DEVICE_NAME_I2C1 "i2c1" +#endif + +#ifndef ES_I2C0_CLK_SPEED +#define ES_I2C0_CLK_SPEED 100000 +#endif +#ifndef ES_I2C0_OWN_ADDR1 +#define ES_I2C0_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C0_GENERAL_CALL +#define ES_I2C0_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C0_STRETCH +#define ES_I2C0_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C0_ADDR_MODE +#define ES_I2C0_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + +#ifndef ES_I2C1_CLK_SPEED +#define ES_I2C1_CLK_SPEED 100000 +#endif +#ifndef ES_I2C1_OWN_ADDR1 +#define ES_I2C1_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C1_GENERAL_CALL +#define ES_I2C1_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C1_STRETCH +#define ES_I2C1_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C1_ADDR_MODE +#define ES_I2C1_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_map.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_map.h new file mode 100644 index 0000000000..67609d04d7 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_map.h @@ -0,0 +1,2908 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __es_conf_info_map_H__ +#define __es_conf_info_map_H__ + +#include <ald_gpio.h> + + + +#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES_PIN_DEFAULT {-1, 0, 0} + +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + + +#define ES_GPIO_ADC_CH0_GPIO GPIOC +#define ES_GPIO_ADC_CH1_GPIO GPIOC +#define ES_GPIO_ADC_CH2_GPIO GPIOC +#define ES_GPIO_ADC_CH3_GPIO GPIOC +#define ES_GPIO_ADC_CH4_GPIO GPIOA +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH8_GPIO GPIOA +#define ES_GPIO_ADC_CH9_GPIO GPIOA +#define ES_GPIO_ADC_CH10_GPIO GPIOA +#define ES_GPIO_ADC_CH11_GPIO GPIOA +#define ES_GPIO_ADC_CH12_GPIO GPIOC +#define ES_GPIO_ADC_CH13_GPIO GPIOC +#define ES_GPIO_ADC_CH14_GPIO GPIOB +#define ES_GPIO_ADC_CH15_GPIO GPIOB + +#define ES_GPIO_ADC_CH0_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH5_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH6_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH7_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH8_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH9_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH10_PIN GPIO_PIN_6 +#define ES_GPIO_ADC_CH11_PIN GPIO_PIN_7 +#define ES_GPIO_ADC_CH12_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH13_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH14_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_1 + + + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(2, C, 13), + __ES_PIN(3, C, 14), + __ES_PIN(4, C, 15), + __ES_PIN(5, H, 0), + __ES_PIN(6, H, 1), + __ES_PIN_DEFAULT, + __ES_PIN(8, C, 0), + __ES_PIN(9, C, 1), + __ES_PIN(10, C, 2), + __ES_PIN(11, C, 3), + __ES_PIN(12, H, 3), + __ES_PIN(13, H, 4), + __ES_PIN(14, A, 0), + __ES_PIN(15, A, 1), + __ES_PIN(16, A, 2), + __ES_PIN(17, A, 3), + __ES_PIN(18, F, 0), + __ES_PIN(19, F, 1), + __ES_PIN(20, A, 4), + __ES_PIN(21, A, 5), + __ES_PIN(22, A, 6), + __ES_PIN(23, A, 7), + __ES_PIN(24, C, 4), + __ES_PIN(25, C, 5), + __ES_PIN(26, B, 0), + __ES_PIN(27, B, 1), + __ES_PIN(28, B, 2), + __ES_PIN(29, B, 10), + __ES_PIN(30, B, 11), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(33, B, 12), + __ES_PIN(34, B, 13), + __ES_PIN(35, B, 14), + __ES_PIN(36, B, 15), + __ES_PIN(37, C, 6), + __ES_PIN(38, C, 7), + __ES_PIN(39, C, 8), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(46, A, 13), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(49, A, 14), + __ES_PIN(50, A, 15), + __ES_PIN(51, C, 10), + __ES_PIN(52, C, 11), + __ES_PIN(53, C, 12), + __ES_PIN(54, D, 2), + __ES_PIN(55, B, 3), + __ES_PIN(56, B, 4), + __ES_PIN(57, B, 5), + __ES_PIN(58, B, 6), + __ES_PIN(59, B, 7), + __ES_PIN(60, H, 2), + __ES_PIN(61, B, 8), + __ES_PIN(62, B, 9), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, +}; + +#define ES_PIN_GPIO_C_13 2 +#define ES_PIN_GPIO_C_14 3 +#define ES_PIN_GPIO_C_15 4 +#define ES_PIN_GPIO_H_0 5 +#define ES_PIN_GPIO_H_1 6 +#define ES_PIN_GPIO_C_0 8 +#define ES_PIN_GPIO_C_1 9 +#define ES_PIN_GPIO_C_2 10 +#define ES_PIN_GPIO_C_3 11 +#define ES_PIN_GPIO_H_3 12 +#define ES_PIN_GPIO_H_4 13 +#define ES_PIN_GPIO_A_0 14 +#define ES_PIN_GPIO_A_1 15 +#define ES_PIN_GPIO_A_2 16 +#define ES_PIN_GPIO_A_3 17 +#define ES_PIN_GPIO_F_0 18 +#define ES_PIN_GPIO_F_1 19 +#define ES_PIN_GPIO_A_4 20 +#define ES_PIN_GPIO_A_5 21 +#define ES_PIN_GPIO_A_6 22 +#define ES_PIN_GPIO_A_7 23 +#define ES_PIN_GPIO_C_4 24 +#define ES_PIN_GPIO_C_5 25 +#define ES_PIN_GPIO_B_0 26 +#define ES_PIN_GPIO_B_1 27 +#define ES_PIN_GPIO_B_2 28 +#define ES_PIN_GPIO_B_10 29 +#define ES_PIN_GPIO_B_11 30 +#define ES_PIN_GPIO_B_12 33 +#define ES_PIN_GPIO_B_13 34 +#define ES_PIN_GPIO_B_14 35 +#define ES_PIN_GPIO_B_15 36 +#define ES_PIN_GPIO_C_6 37 +#define ES_PIN_GPIO_C_7 38 +#define ES_PIN_GPIO_C_8 39 +#define ES_PIN_GPIO_A_13 46 +#define ES_PIN_GPIO_A_14 49 +#define ES_PIN_GPIO_A_15 50 +#define ES_PIN_GPIO_C_10 51 +#define ES_PIN_GPIO_C_11 52 +#define ES_PIN_GPIO_C_12 53 +#define ES_PIN_GPIO_D_2 54 +#define ES_PIN_GPIO_B_3 55 +#define ES_PIN_GPIO_B_4 56 +#define ES_PIN_GPIO_B_5 57 +#define ES_PIN_GPIO_B_6 58 +#define ES_PIN_GPIO_B_7 59 +#define ES_PIN_GPIO_H_2 60 +#define ES_PIN_GPIO_B_8 61 +#define ES_PIN_GPIO_B_9 62 + + + +/* UART_TX */ + + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_UART0_TX_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_UART0_TX_PIN ES_PIN_GPIO_H_0 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_D_8 +#define ES_UART0_TX_PIN ES_PIN_GPIO_D_8 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_UART1_TX_PIN ES_PIN_GPIO_A_13 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART1_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_E_2 +#define ES_UART2_TX_PIN ES_PIN_GPIO_E_2 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART2_TX_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_UART2_TX_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_UART3_TX_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART3_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_UART3_TX_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART4_TX_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_UART4_TX_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART4_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART4_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_UART5_TX_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_UART5_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART5_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + + +/* UART_RX */ + + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_UART0_RX_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_UART0_RX_PIN ES_PIN_GPIO_H_1 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_D_9 +#define ES_UART0_RX_PIN ES_PIN_GPIO_D_9 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_UART1_RX_PIN ES_PIN_GPIO_A_14 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART1_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_UART2_RX_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_E_3 +#define ES_UART2_RX_PIN ES_PIN_GPIO_E_3 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART2_RX_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_UART3_RX_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART3_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_UART3_RX_PIN ES_PIN_GPIO_D_13 +#endif +#endif + +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART4_RX_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_UART4_RX_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART4_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART4_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_UART5_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_UART5_RX_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART5_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + + +/* UART_RTS */ + + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_E_5 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_E_5 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART4_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART4_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART4_RTS_PIN +#ifdef ES_PIN_GPIO_E_1 +#define ES_UART4_RTS_PIN ES_PIN_GPIO_E_1 +#endif +#endif + +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART5_RTS_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_UART5_RTS_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART5_RTS_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_UART5_RTS_PIN ES_PIN_GPIO_D_4 +#endif +#endif + + +/* UART_CTS */ + + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_D_11 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_D_11 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_E_4 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_E_4 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART4_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART4_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART4_CTS_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_UART4_CTS_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART5_CTS_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_UART5_CTS_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART5_CTS_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_UART5_CTS_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* UART_CK */ + + +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART4_CK_PIN +#ifdef ES_PIN_GPIO_E_6 +#define ES_UART4_CK_PIN ES_PIN_GPIO_E_6 +#endif +#endif + +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART4_CK_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_UART4_CK_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_UART5_CK_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_UART5_CK_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_UART5_CK_PIN ES_PIN_GPIO_E_0 +#endif +#endif + + +/* USART_TX */ + + + +/* USART_RX */ + + + +/* USART_RTS */ + + + +/* USART_CTS */ + + + +/* USART_CK */ + + + +/* I2C_SCL */ + + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_H_0 +#endif +#endif + + +/* I2C_SDA */ + + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_H_1 +#endif +#endif + + +/* SPI_MISO */ + + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_D_4 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI2_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI2_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI2_MISO_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_SPI2_MISO_PIN ES_PIN_GPIO_B_0 +#endif +#endif + + +/* SPI_MOSI */ + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI2_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI2_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI2_MOSI_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_SPI2_MOSI_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* SPI_SCK */ + + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_D_3 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI2_SCK_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_SPI2_SCK_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI2_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI2_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + + +/* SPI_NSS */ + + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_B_12 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_B_12 +#endif +#endif + +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI2_NSS_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_SPI2_NSS_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI2_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI2_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + + +/* CAN_TX */ + + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_CAN0_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_CAN0_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + + +/* CAN_RX */ + + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_CAN0_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_CAN0_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* AD16C4T_CH1 */ + + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_E_9 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_E_9 +#endif +#endif + +#ifndef ES_AD16C4T1_CH1_GPIO_FUNC +#define ES_AD16C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PORT +#define ES_AD16C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PIN +#define ES_AD16C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_AD16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_AD16C4T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + + +/* AD16C4T_CH2 */ + + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_AD16C4T1_CH2_GPIO_FUNC +#define ES_AD16C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PORT +#define ES_AD16C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PIN +#define ES_AD16C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_AD16C4T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + + +/* AD16C4T_CH3 */ + + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_AD16C4T1_CH3_GPIO_FUNC +#define ES_AD16C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PORT +#define ES_AD16C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PIN +#define ES_AD16C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_AD16C4T1_CH3_PIN ES_PIN_GPIO_C_8 +#endif +#endif + + +/* AD16C4T_CH4 */ + + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_E_14 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_E_14 +#endif +#endif + + +/* AD16C4T_CH1N */ + + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_E_8 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_E_8 +#endif +#endif + +#ifndef ES_AD16C4T1_CH1N_GPIO_FUNC +#define ES_AD16C4T1_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PORT +#define ES_AD16C4T1_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PIN +#define ES_AD16C4T1_CH1N_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T1_CH1N_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T1_CH1N_PIN ES_PIN_GPIO_A_7 +#endif +#endif + + +/* AD16C4T_CH2N */ + + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_AD16C4T1_CH2N_GPIO_FUNC +#define ES_AD16C4T1_CH2N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PORT +#define ES_AD16C4T1_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PIN +#define ES_AD16C4T1_CH2N_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T1_CH2N_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_AD16C4T1_CH2N_PIN ES_PIN_GPIO_B_0 +#endif +#endif + + +/* AD16C4T_CH3N */ + + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_AD16C4T1_CH3N_GPIO_FUNC +#define ES_AD16C4T1_CH3N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PORT +#define ES_AD16C4T1_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PIN +#define ES_AD16C4T1_CH3N_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T1_CH3N_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_AD16C4T1_CH3N_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* AD16C4T_CH4N */ + + + +/* AD16C4T_ET */ + + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_AD16C4T1_ET_GPIO_FUNC +#define ES_AD16C4T1_ET_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PORT +#define ES_AD16C4T1_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PIN +#define ES_AD16C4T1_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_AD16C4T1_ET_PIN ES_PIN_GPIO_A_0 +#endif +#endif + + +/* GP32C4T_CH1 */ + + +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP32C4T0_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP32C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP32C4T0_CH1_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_B_4 +#endif +#endif + + +/* GP32C4T_CH2 */ + + +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP32C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP32C4T0_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP32C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_GP32C4T0_CH2_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + + +/* GP32C4T_CH3 */ + + +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP32C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP32C4T0_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_GP32C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_GP32C4T0_CH3_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_GP32C4T1_CH3_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP32C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_GP32C4T1_CH3_PIN ES_PIN_GPIO_C_8 +#endif +#endif + + +/* GP32C4T_CH4 */ + + +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_GP32C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_GP32C4T0_CH4_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP32C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_GP32C4T0_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_GP32C4T1_CH4_GPIO_FUNC +#define ES_GP32C4T1_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PORT +#define ES_GP32C4T1_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PIN +#define ES_GP32C4T1_CH4_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP32C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_GP32C4T1_CH4_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* GP32C4T_ET */ + + +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP32C4T0_ET_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP32C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP32C4T0_ET_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP32C4T1_ET_GPIO_FUNC +#define ES_GP32C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PORT +#define ES_GP32C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PIN +#define ES_GP32C4T1_ET_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP32C4T1_ET_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_GP32C4T1_ET_PIN ES_PIN_GPIO_D_2 +#endif +#endif + + +/* GP16C4T_CH1 */ + + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_GP16C4T1_CH1_GPIO_FUNC +#define ES_GP16C4T1_CH1_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PORT +#define ES_GP16C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PIN +#define ES_GP16C4T1_CH1_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP16C4T1_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif + + +/* GP16C4T_CH2 */ + + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_D_13 +#endif +#endif + +#ifndef ES_GP16C4T1_CH2_GPIO_FUNC +#define ES_GP16C4T1_CH2_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PORT +#define ES_GP16C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PIN +#define ES_GP16C4T1_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP16C4T1_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + + +/* GP16C4T_CH3 */ + + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_GP16C4T1_CH3_GPIO_FUNC +#define ES_GP16C4T1_CH3_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PORT +#define ES_GP16C4T1_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PIN +#define ES_GP16C4T1_CH3_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP16C4T1_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif + + +/* GP16C4T_CH4 */ + + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_D_15 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_D_15 +#endif +#endif + +#ifndef ES_GP16C4T1_CH4_GPIO_FUNC +#define ES_GP16C4T1_CH4_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PORT +#define ES_GP16C4T1_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PIN +#define ES_GP16C4T1_CH4_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_GP16C4T1_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif + + +/* GP16C4T_ET */ + + +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_GP16C4T1_ET_GPIO_FUNC +#define ES_GP16C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PORT +#define ES_GP16C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PIN +#define ES_GP16C4T1_ET_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_GP16C4T1_ET_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* GP16C2T_CH1 */ + + + +/* GP16C2T_CH2 */ + + + +/* GP16C2T_CH1N */ + + + +/* GP16C2T_CH2N */ + + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_pm.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_pm.h new file mode 100644 index 0000000000..68cf747791 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_pm.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PM_H__ +#define __ES_CONF_INFO_PM_H__ + +#include <ald_cmu.h> +#include <ald_pmu.h> + +#define ES_PMU_SAVE_LOAD_UART + +/* PM 配置 */ + + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_pwm.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_pwm.h new file mode 100644 index 0000000000..cdf83c6b21 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_pwm.h @@ -0,0 +1,78 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PWM_H__ +#define __ES_CONF_INFO_PWM_H__ + +#include "es_conf_info_map.h" +#include <ald_cmu.h> +#include <ald_timer.h> +#include <ald_gpio.h> + + +#define ES_C_PWM_OC_POL_HIGH TIMER_OC_POLARITY_HIGH +#define ES_C_PWM_OC_POL_LOW TIMER_OC_POLARITY_LOW + +#define ES_C_PWM_OC_MODE_PWM1 TIMER_OC_MODE_PWM1 +#define ES_C_PWM_OC_MODE_PWM2 TIMER_OC_MODE_PWM2 + + + +/* PWM 配置 */ + + +/* codes_main */ + + + +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 + +#ifndef ES_PWM_OC_POLARITY +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#endif +#ifndef ES_PWM_OC_MODE +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 +#endif + +#ifndef ES_DEVICE_NAME_AD16C4T0_PWM +#define ES_DEVICE_NAME_AD16C4T0_PWM "pwm0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_PWM +#define ES_DEVICE_NAME_AD16C4T1_PWM "pwm1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_PWM +#define ES_DEVICE_NAME_GP32C4T0_PWM "pwm2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_PWM +#define ES_DEVICE_NAME_GP32C4T1_PWM "pwm3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_PWM +#define ES_DEVICE_NAME_GP16C4T0_PWM "pwm4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_PWM +#define ES_DEVICE_NAME_GP16C4T1_PWM "pwm5" +#endif + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_rtc.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_rtc.h new file mode 100644 index 0000000000..c03cd2b790 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_RTC_H__ +#define __ES_CONF_INFO_RTC_H__ + +#include <ald_cmu.h> +#include <ald_rtc.h> + +/* RTC 配置 */ + +#define ES_C_RTC_SOURCE_LRC RTC_SOURCE_LRC +#define ES_C_RTC_SOURCE_LOSC RTC_SOURCE_LOSC + +#define ES_RTC_CLK_SOURCE ES_C_RTC_SOURCE_LOSC + + + + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_RTC +#define ES_DEVICE_NAME_RTC "rtc" +#endif + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_select.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_select.h new file mode 100644 index 0000000000..be5f3d882e --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_select.h @@ -0,0 +1,43 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SELECT_H__ +#define __ES_CONF_INFO_SELECT_H__ + + +#define ES_C_ENABLE 1 +#define ES_C_DISABLE 0 + + +/* codes_main */ + +#ifndef ES_USE_ASSERT +#define ES_USE_ASSERT ES_C_DISABLE +#endif + + +#if ES_USE_ASSERT + #define USE_ASSERT +#endif + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_spi.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_spi.h new file mode 100644 index 0000000000..00abeda129 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_spi.h @@ -0,0 +1,159 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SPI_H__ +#define __ES_CONF_INFO_SPI_H__ + +#include "es_conf_info_map.h" +#include <ald_spi.h> +#include <ald_gpio.h> +#include <ald_cmu.h> + +/* SPI 配置 */ + +#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ + _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ + ES_SPI##_I_##_WIRE_3_4 | \ + ES_SPI##_I_##_CPHA_1_2 | \ + ES_SPI##_I_##_CPOL_H_L | \ + ES_SPI##_I_##_CS | \ + ES_SPI##_I_##_M_L_SB ); \ + _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ + _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ + }while(0) + + +// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ +// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ +// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ +// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ +// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ +// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ +// spi_config.data_width = 8; /* 数据长度：8 */ +// spi_config.max_hz = 2000000; /* 最快时钟频率 */ + +#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL +#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL + +#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA +#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA + +#define ES_C_SPI_MSB RT_SPI_MSB +#define ES_C_SPI_LSB RT_SPI_LSB + +#define ES_C_SPI_CS_LOW_LEVEL 0 +#define ES_C_SPI_CS_HIGH_LEVEL 1 + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_SPI0_BUS +#define ES_DEVICE_NAME_SPI0_BUS "spi0" +#endif +#ifndef ES_DEVICE_NAME_SPI0_DEV0 +#define ES_DEVICE_NAME_SPI0_DEV0 "spi00" +#endif + +#ifndef ES_DEVICE_NAME_SPI1_BUS +#define ES_DEVICE_NAME_SPI1_BUS "spi1" +#endif +#ifndef ES_DEVICE_NAME_SPI1_DEV0 +#define ES_DEVICE_NAME_SPI1_DEV0 "spi10" +#endif + +#ifndef ES_DEVICE_NAME_SPI2_BUS +#define ES_DEVICE_NAME_SPI2_BUS "spi2" +#endif +#ifndef ES_DEVICE_NAME_SPI2_DEV0 +#define ES_DEVICE_NAME_SPI2_DEV0 "spi20" +#endif + + +#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL + +#ifndef ES_SPI0_CPHA_1_2 +#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI0_CPOL_H_L +#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI0_M_L_SB +#define ES_SPI0_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI0_MAX_HZ +#define ES_SPI0_MAX_HZ 2000000 +#endif +#ifndef ES_SPI0_NSS_PIN +#define ES_SPI0_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI1_CPHA_1_2 +#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI1_CPOL_H_L +#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI1_M_L_SB +#define ES_SPI1_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI1_MAX_HZ +#define ES_SPI1_MAX_HZ 2000000 +#endif +#ifndef ES_SPI1_NSS_PIN +#define ES_SPI1_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI2_CPHA_1_2 +#define ES_SPI2_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI2_CPOL_H_L +#define ES_SPI2_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI2_M_L_SB +#define ES_SPI2_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI2_MAX_HZ +#define ES_SPI2_MAX_HZ 2000000 +#endif +#ifndef ES_SPI2_NSS_PIN +#define ES_SPI2_NSS_PIN 0xFFFFFFFF +#endif + + +#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI0_CS RT_SPI_NO_CS +#define ES_SPI0_DATA_W 8 + +#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI1_CS RT_SPI_NO_CS +#define ES_SPI1_DATA_W 8 + +#define ES_SPI2_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI2_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI2_CS RT_SPI_NO_CS +#define ES_SPI2_DATA_W 8 + + +#endif diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_uart.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_uart.h new file mode 100644 index 0000000000..4f68e223cd --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_uart.h @@ -0,0 +1,205 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_UART_H__ +#define __ES_CONF_INFO_UART_H__ + +#include "es_conf_info_map.h" +#include <ald_gpio.h> +#include <ald_uart.h> +#include <ald_cmu.h> + + + +#define ES_C_UART_PARITY_NONE PARITY_NONE +#define ES_C_UART_PARITY_ODD PARITY_ODD +#define ES_C_UART_PARITY_EVEN PARITY_EVEN + +#define ES_C_UART_STOP_1 STOP_BITS_1 +#define ES_C_UART_STOP_2 STOP_BITS_2 + + +/* UART 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_UART0 +#define ES_DEVICE_NAME_UART0 "uart0" +#endif +#ifndef ES_DEVICE_NAME_UART1 +#define ES_DEVICE_NAME_UART1 "uart1" +#endif +#ifndef ES_DEVICE_NAME_UART2 +#define ES_DEVICE_NAME_UART2 "uart2" +#endif +#ifndef ES_DEVICE_NAME_UART3 +#define ES_DEVICE_NAME_UART3 "uart3" +#endif +#ifndef ES_DEVICE_NAME_UART4 +#define ES_DEVICE_NAME_UART4 "uart4" +#endif +#ifndef ES_DEVICE_NAME_UART5 +#define ES_DEVICE_NAME_UART5 "uart5" +#endif + +#ifndef ES_CONF_UART0_BAUD_RATE +#define ES_CONF_UART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART0_PARITY +#define ES_CONF_UART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART0_STOP_BITS +#define ES_CONF_UART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART1_BAUD_RATE +#define ES_CONF_UART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART1_PARITY +#define ES_CONF_UART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART1_STOP_BITS +#define ES_CONF_UART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART2_BAUD_RATE +#define ES_CONF_UART2_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART2_PARITY +#define ES_CONF_UART2_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART2_STOP_BITS +#define ES_CONF_UART2_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART3_BAUD_RATE +#define ES_CONF_UART3_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART3_PARITY +#define ES_CONF_UART3_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART3_STOP_BITS +#define ES_CONF_UART3_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART4_BAUD_RATE +#define ES_CONF_UART4_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART4_PARITY +#define ES_CONF_UART4_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART4_STOP_BITS +#define ES_CONF_UART4_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART5_BAUD_RATE +#define ES_CONF_UART5_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART5_PARITY +#define ES_CONF_UART5_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART5_STOP_BITS +#define ES_CONF_UART5_STOP_BITS ES_C_UART_STOP_1 +#endif + + +#define ES_UART0_CONFIG \ +{ \ + ES_CONF_UART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART0_STOP_BITS, \ + ES_CONF_UART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART1_CONFIG \ +{ \ + ES_CONF_UART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART1_STOP_BITS, \ + ES_CONF_UART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART2_CONFIG \ +{ \ + ES_CONF_UART2_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART2_STOP_BITS, \ + ES_CONF_UART2_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART3_CONFIG \ +{ \ + ES_CONF_UART3_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART3_STOP_BITS, \ + ES_CONF_UART3_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART4_CONFIG \ +{ \ + ES_CONF_UART4_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART4_STOP_BITS, \ + ES_CONF_UART4_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART5_CONFIG \ +{ \ + ES_CONF_UART5_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART5_STOP_BITS, \ + ES_CONF_UART5_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + +#endif diff --git a/bsp/essemi/es32f365x/drivers/Kconfig b/bsp/essemi/es32f365x/drivers/Kconfig new file mode 100644 index 0000000000..6e70e9674c --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/Kconfig @@ -0,0 +1,98 @@ +menu "Hardware Drivers Config" + + + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + source "drivers/ES/Kconfig" + + endmenu + + menu "Onboard Peripheral Drivers" + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi0)" + select BSP_USING_SPI + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + +if BSP_USING_SPI_FLASH + + config ES_DEVICE_NAME_SPI_DEV + string "The name of spi device (registered)" + default "spi00" + + config ES_DEVICE_NAME_SPI_FALSH_DEV + string "The name of spi flash device" + default "W25Q64" +endif + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + + + menu "Peripheral Drivers test example" + + config BSP_USING_EXAMPLE_ADC_VOL + bool "BSP_USING_EXAMPLE_ADC_VOL" + default n + + config BSP_USING_EXAMPLE_HWTIMER + bool "BSP_USING_EXAMPLE_HWTIMER" + default n + + config BSP_USING_EXAMPLE_I2C + bool "BSP_USING_EXAMPLE_I2C" + default n + + config BSP_USING_EXAMPLE_I2C_E2PROM + bool "BSP_USING_EXAMPLE_I2C_E2PROM" + default n + + config BSP_USING_EXAMPLE_LED_BLINK + bool "BSP_USING_EXAMPLE_LED_BLINK" + default n + + config BSP_USING_EXAMPLE_PIN_BEEP + bool "BSP_USING_EXAMPLE_PIN_BEEP" + default n + + config BSP_USING_EXAMPLE_PWM_LED + bool "BSP_USING_EXAMPLE_PWM_LED" + default n + + config BSP_USING_EXAMPLE_RTC + bool "BSP_USING_EXAMPLE_RTC" + default n + + config BSP_USING_EXAMPLE_SPI + bool "BSP_USING_EXAMPLE_SPI" + default n + + config BSP_USING_EXAMPLE_UART + bool "BSP_USING_EXAMPLE_UART" + default n + + config BSP_USING_EXAMPLE_UART_DMA + bool "BSP_USING_EXAMPLE_UART_DMA" + default n + + config BSP_USING_EXAMPLE_CAN + bool "BSP_USING_EXAMPLE_CAN" + default n + + config BSP_USING_EXAMPLE_PM + bool "BSP_USING_EXAMPLE_PM" + default n + + endmenu + +endmenu diff --git a/bsp/essemi/es32f365x/drivers/SConscript b/bsp/essemi/es32f365x/drivers/SConscript new file mode 100644 index 0000000000..9b38fc3661 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/SConscript @@ -0,0 +1,118 @@ +from building import * + + +Import('ES32F36XX_DRV_ROOT') + +cwd = GetCurrentDir() + +objs = [] + +# add the general drivers. +src = Split(''' +board.c +''') + + +# add gpio code +if GetDepend('RT_USING_PIN'): + src += [ES32F36XX_DRV_ROOT+'/drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \ + GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \ + GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5'): + src += [ES32F36XX_DRV_ROOT+'/drv_uart.c'] + +# add spi driver code +if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'): + src += [ES32F36XX_DRV_ROOT+'/drv_spi.c'] + +# add i2c driver code +if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): + src += [ES32F36XX_DRV_ROOT+'/drv_i2c.c'] + +# add can driver code +if GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'): + src += [ES32F36XX_DRV_ROOT+'/drv_can.c'] + +# add adc driver code +if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC1'): + src += [ES32F36XX_DRV_ROOT+'/drv_adc.c'] + +# add rtc driver code +if GetDepend(['BSP_USING_RTC']): + src += [ES32F36XX_DRV_ROOT+'/drv_rtc.c'] + +# add spi flash driver code +if GetDepend('BSP_USING_SPI_FLASH'): + src += [ES32F36XX_DRV_ROOT+'/drv_spiflash.c'] + +# add hwtimer driver code +if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMER'): + src += [ES32F36XX_DRV_ROOT+'/drv_hwtimer.c'] + +# add pwm driver code +if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ + GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'): + src += [ES32F36XX_DRV_ROOT+'/drv_pwm.c'] + +# add pm driver code +if GetDepend(['BSP_USING_PM']): + src += [ES32F36XX_DRV_ROOT+'/drv_pm.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) +objs = objs + group + +src = [] +cwd = GetCurrentDir() +include_path = [cwd + '/ES'] + +if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/adc_vol_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/hwtimer_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_I2C'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/i2c_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_I2C_E2PROM'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/i2c_e2_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/led_blink_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/pin_beep_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PWM_LED'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/pwm_led_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_RTC'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/rtc_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_UART'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/uart_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_UART_DMA'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/uart_dma_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_SPI'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/spi_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_CAN'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/can_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PM'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/pm_sample.c'] + +group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path) + +objs = objs + group +Return('objs') diff --git a/bsp/essemi/es32f365x/drivers/board.c b/bsp/essemi/es32f365x/drivers/board.c new file mode 100644 index 0000000000..39744002d8 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/board.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#include <rthw.h> +#include <rtthread.h> +#include "board.h" +#include "drv_uart.h" +#include "drv_gpio.h" +#include <ald_gpio.h> +#include "ald_dma.h" + +/** + * @addtogroup es32f3 + */ + +/*@{*/ + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +} + +/******************************************************************************* + * Function Name : SystemClock_Configuration + * Description : Configures the System Clock. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SystemClock_Config(void) +{ + + SYSCFG_UNLOCK(); +#if ES_CMU_LRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#endif /*ES_CMU_LRC_EN*/ + +#if ES_CMU_LOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#endif /*ES_CMU_LOSC_EN*/ + +#if ES_CMU_HRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#endif /*ES_CMU_HRC_EN*/ + +#if ES_CMU_HOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#endif /*ES_CMU_HOSC_EN*/ + + SYSCFG_LOCK(); + +#if ES_CMU_PLL1_EN + /*PLL的源必须是4M*/ + ald_cmu_pll1_config(ES_PLL1_REFER_CLK, ES_PLL1_OUT_CLK); + + #if ES_CMU_PLL1_SAFE_EN + ald_cmu_pll_safe_config(ENABLE); + #else + ald_cmu_pll_safe_config(DISABLE); + #endif + +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); +#endif /*ES_CMU_PLL1_EN*/ + + ald_cmu_clock_config(ES_SYS_CLK_SOURSE, ES_SYS_CLK); + + ald_cmu_div_config(CMU_SYS,ES_CMU_SYS_DIV); + ald_cmu_div_config(CMU_HCLK_1,ES_CMU_HCLK_1_DIV); + ald_cmu_div_config(CMU_HCLK_2,ES_CMU_HCLK_2_DIV); + ald_cmu_div_config(CMU_PCLK_1,ES_CMU_PCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_2,ES_CMU_PCLK_2_DIV); + + ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE); + +/*低功耗时钟使能*/ +#ifdef RT_USING_PM + SYSCFG_UNLOCK(); + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); + SYSCFG_LOCK(); +#endif + +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + /* ticks = sysclk / RT_TICK_PER_SECOND */ + SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); + + __systick_interval = 1; +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + ald_inc_tick(); + rt_tick_increase(); + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This is the cmu interrupt service. + * + */ +void CMU_Handler(void) +{ + ald_cmu_irq_handler(); +} +/** + * This is the DMA interrupt service. + * + */ +void DMA_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + ald_dma_irq_handler(); + /* leave interrupt */ + rt_interrupt_leave(); +} +/*@}*/ +/** + * This function will initial ES32F3 board. + */ +void rt_hw_board_init(void) +{ + /* NVIC Configuration */ + NVIC_Configuration(); + /*System Clock Configuration */ + SystemClock_Config(); + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +#ifdef BSP_USING_DMA0 + ald_cmu_perh_clock_config(CMU_PERH_DMA, ENABLE); + ald_dma_init(DMA0); +#endif +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + unsigned int start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} diff --git a/bsp/essemi/es32f365x/drivers/board.h b/bsp/essemi/es32f365x/drivers/board.h new file mode 100644 index 0000000000..796121513a --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2021-10-11 liuhy the first version + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include <es32f36xx.h> +#include "es_conf_info_cmu.h" + +#define ES32F3_SRAM_SIZE 0x10000 +#define ES32F3_SRAM_END (0x20000000 + ES32F3_SRAM_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END ES32F3_SRAM_END + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_adc.h b/bsp/essemi/es32f365x/drivers/drv_adc.h new file mode 100644 index 0000000000..fa51cdbb21 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_adc.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-04-03 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_ADC_H__ +#define DRV_ADC_H__ + +#include "es_conf_info_adc.h" + +int rt_hw_adc_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_can.h b/bsp/essemi/es32f365x/drivers/drv_can.h new file mode 100644 index 0000000000..aac7c86c79 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_can.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_CAN_H__ +#define DRV_CAN_H__ + +#include <board.h> +#include <rtdevice.h> +#include <rtthread.h> +#include "es_conf_info_can.h" + +#ifdef RT_USING_CAN +/* es32f3 can device */ +struct es32f3_can +{ + can_handle_t CanHandle; + can_filter_t FilterConfig; + struct rt_can_device device; /* inherit from can device */ +}; + +int rt_hw_can_init(void); + +#endif +#endif /*DRV_CAN_H__ */ diff --git a/bsp/essemi/es32f365x/drivers/drv_gpio.h b/bsp/essemi/es32f365x/drivers/drv_gpio.h new file mode 100644 index 0000000000..4fd4a15fe6 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_gpio.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +#include "es_conf_info_gpio.h" + +#define GET_PIN(port,pin) (ES_PIN_GPIO_##port##_##pin) + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_hwtimer.h b/bsp/essemi/es32f365x/drivers/drv_hwtimer.h new file mode 100644 index 0000000000..bbf51a4771 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_hwtimer.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-3-19 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_HWTIMER_H__ +#define DRV_HWTIMER_H__ + +#include "es_conf_info_hwtimer.h" +int rt_hw_hwtimer_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_i2c.h b/bsp/essemi/es32f365x/drivers/drv_i2c.h new file mode 100644 index 0000000000..d04b05c361 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_i2c.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_I2C_H__ +#define DRV_I2C_H__ + +#include "es_conf_info_i2c.h" + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_pm.h b/bsp/essemi/es32f365x/drivers/drv_pm.h new file mode 100644 index 0000000000..cc4a847703 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_pm.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-04-01 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_PM_H__ +#define DRV_PM_H__ + +#include <rthw.h> +#include <board.h> +#include <rtdevice.h> +#include "es_conf_info_pm.h" +#include <string.h> + +int rt_hw_pm_init(void); + +extern void save_register(void *p_head,uint32_t size,void *p_save); + +extern void load_register(void *p_head,uint32_t size,void *p_load); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_pwm.h b/bsp/essemi/es32f365x/drivers/drv_pwm.h new file mode 100644 index 0000000000..f4fcfe7cff --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_pwm.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-11 wangyq the first version + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_rtc.h b/bsp/essemi/es32f365x/drivers/drv_rtc.h new file mode 100644 index 0000000000..417a10c3b6 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_rtc.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-03-22 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_RTC_H__ +#define DRV_RTC_H__ + +#include "es_conf_info_rtc.h" +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_spi.h b/bsp/essemi/es32f365x/drivers/drv_spi.h new file mode 100644 index 0000000000..0938f9aed4 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_spi.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +#include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> + +#include "es_conf_info_spi.h" + +struct es32f3_hw_spi_cs +{ + rt_uint32_t pin; +}; + +/* cannot be used before completion init */ +rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name); +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_spiflash.h b/bsp/essemi/es32f365x/drivers/drv_spiflash.h new file mode 100644 index 0000000000..9c90e1caf2 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_spiflash.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-15 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_NOR_FLASH_H__ +#define DRV_NOR_FLASH_H__ + +#include "es_conf_info_spi.h" + +int rt_hw_spi_flash_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_uart.h b/bsp/essemi/es32f365x/drivers/drv_uart.h new file mode 100644 index 0000000000..6e9b7703e0 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/drv_uart.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf b/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..d8055f6f83 --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/linker_scripts/link.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, last block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file diff --git a/bsp/essemi/es32f365x/drivers/linker_scripts/link.sct b/bsp/essemi/es32f365x/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..4db4359d4c --- /dev/null +++ b/bsp/essemi/es32f365x/drivers/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/essemi/es32f365x/project.ewd b/bsp/essemi/es32f365x/project.ewd new file mode 100644 index 0000000000..e9ca6c4c40 --- /dev/null +++ b/bsp/essemi/es32f365x/project.ewd @@ -0,0 +1,2810 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>rt-thread</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>28</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state></state> + </option> + <option> + <name>RunToEnable</name> + <state>0</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>0</state> + </option> + <option> + <name>OCProductVersion</name> + <state>8.11.1.13270</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>CMSISDAP_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>8.11.1.13270</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreMaster</name> + <state>0</state> + </option> + <option> + <name>OCMulticorePort</name> + <state>53461</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>4</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>1</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>1</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>1</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>1</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>1</state> + </option> + <option> + <name>CatchINTERR</name> + <state>1</state> + </option> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>1</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state></state> + </option> + <option> + <name>CMSISDAPProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPSelectedCPUBehaviour</name> + <state>0</state> + </option> + <option> + <name>ICpuName</name> + <state></state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNoSelect</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>GDBSERVER_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJTagBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJTagDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJTagUpdateBreakpoints</name> + <state>_call_main</state> + </option> + </data> + </settings> + <settings> + <name>IJET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>8</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>IjetResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>IjetHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>IjetHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>IjetPowerFromProbe</name> + <state>1</state> + </option> + <option> + <name>IjetPowerRadio</name> + <state>0</state> + </option> + <option> + <name>IjetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>IjetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>IjetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>IjetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTarget</name> + <state>0</state> + </option> + <option> + <name>IjetScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>IjetIRLength</name> + <state>0</state> + </option> + <option> + <name>IjetJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetProtocolRadio</name> + <state>0</state> + </option> + <option> + <name>IjetSwoPin</name> + <state>0</state> + </option> + <option> + <name>IjetCpuClockEdit</name> + <state></state> + </option> + <option> + <name>IjetSwoPrescalerList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>IjetBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>IjetRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>IjetUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>1</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>1</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>1</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>1</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>1</state> + </option> + <option> + <name>CatchINTERR</name> + <state>1</state> + </option> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>1</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state></state> + </option> + <option> + <name>IjetProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>IjetMultiCPUEnable</name> + <state>0</state> + </option> + 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<state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file> + <loadFlag>1</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/bsp/essemi/es32f365x/project.ewp b/bsp/essemi/es32f365x/project.ewp new file mode 100644 index 0000000000..e63488a756 --- /dev/null +++ b/bsp/essemi/es32f365x/project.ewp @@ -0,0 +1,2283 @@ +<project>
+ <fileVersion>3</fileVersion>
+ <configuration>
+ <name>rt-thread</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>rt-thread\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>rt-thread\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>rt-thread\List</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>8.11.1.13270</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>8.11.1.13270</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>ES32F3656LT Eastsoft ES32F3656LT</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>25</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibThreads</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CoreVariant</name>
+ <version>25</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>GFPUDeviceSlave</name>
+ <state>ES32F3656LT Eastsoft ES32F3656LT</state>
+ </option>
+ <option>
+ <name>FPU2</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NrRegs</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NEON</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave2</name>
+ <version>25</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>OGCMSISPackSelectDevice</name>
+ </option>
+ <option>
+ <name>OgLibHeap</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGLibAdditionalLocale</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenLocaleTags</name>
+ <state />
+ </option>
+ <option>
+ <name>GenLocaleDisplayOnly</name>
+ <state />
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>34</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state />
+ <state>ES32F36xx</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state>Pa050</state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state />
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state />
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state />
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>00000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state />
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state />
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state />
+ <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3</state>
+ <state>$PROJ_DIR$\..\..\..\components\finsh</state>
+ <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
+ <state>$PROJ_DIR$\libraries\CMSIS\Include</state>
+ <state>$PROJ_DIR$\drivers</state>
+ <state>$PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Include</state>
+ <state>$PROJ_DIR$\.</state>
+ <state>$PROJ_DIR$\applications</state>
+ <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
+ <state>$PROJ_DIR$\..\..\..\include</state>
+ <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
+ <state>$PROJ_DIR$\libraries\CMSIS\Device\EastSoft\ES32F36xx\Include</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCNoLiteralPool</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptStrategySlave</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCGuardCalls</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutputBom</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncInput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccExceptions2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccRTTI2</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>10</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state />
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state />
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state />
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state />
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
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+ <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
+ </file>
+ </group>
+ <group>
+ <name>libc</name>
+ </group>
+</project>
diff --git a/bsp/essemi/es32f365x/project.eww b/bsp/essemi/es32f365x/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/essemi/es32f365x/project.eww @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\project.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/bsp/essemi/es32f365x/project.uvoptx b/bsp/essemi/es32f365x/project.uvoptx new file mode 100644 index 0000000000..8c2dbf3985 --- /dev/null +++ b/bsp/essemi/es32f365x/project.uvoptx @@ -0,0 +1,1093 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>rt-thread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\build\keil\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>255</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>3</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\CMSIS_AGDI.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0es32f36xx -FL080000 -FS00 -FP0($$Device:ES32F3656LT$Flash\es32f36xx.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>CMSIS_AGDI</Key> + <Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0es32f36xx.FLM -FS00 -FL080000 -FP0($$Device:ES32F3656LT$Flash\es32f36xx.FLM)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Group> + <GroupName>Applications</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>1</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>applications\main.c</PathWithFileName> + <FilenameWithoutPath>main.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>CPU</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>2</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName> + <FilenameWithoutPath>showmem.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>3</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\common\backtrace.c</PathWithFileName> + <FilenameWithoutPath>backtrace.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>4</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName> + <FilenameWithoutPath>div0.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>5</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</PathWithFileName> + <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>6</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\libcpu\arm\cortex-m3\cpuport.c</PathWithFileName> + <FilenameWithoutPath>cpuport.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>DeviceDrivers</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>7</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\misc\pin.c</PathWithFileName> + <FilenameWithoutPath>pin.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>8</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\..\components\drivers\serial\serial.c</PathWithFileName> + <FilenameWithoutPath>serial.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>9</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + 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<FileName>ald_trng.c</FileName> + <FileType>1</FileType> + <FilePath>..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c</FilePath> + </File> + <File> + <FileName>ald_adc.c</FileName> + <FileType>1</FileType> + <FilePath>..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c</FilePath> + </File> + <File> + <FileName>ald_dma.c</FileName> + <FileType>1</FileType> + <FilePath>..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c</FilePath> + </File> + <File> + <FileName>ald_i2c.c</FileName> + <FileType>1</FileType> + <FilePath>..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c</FilePath> + </File> + <File> + <FileName>ald_wdt.c</FileName> + <FileType>1</FileType> + <FilePath>..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c</FilePath> + </File> + <File> + <FileName>ald_rtchw.c</FileName> + <FileType>1</FileType> + <FilePath>..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> + + <RTE> + <apis/> + <components/> + <files/> + </RTE> + +</Project> diff --git a/bsp/essemi/es32f365x/rtconfig.h b/bsp/essemi/es32f365x/rtconfig.h new file mode 100644 index 0000000000..0ee0711a70 --- /dev/null +++ b/bsp/essemi/es32f365x/rtconfig.h @@ -0,0 +1,197 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40003 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* games: games run on RT-Thread console */ + +#define SOC_ES32F3656LT + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART0 + +/* SPI Drivers */ + + +/* I2C Drivers */ + + +/* CAN Drivers */ + + +/* ADC Drivers */ + + +/* RTC Drivers */ + + +/* HWTIMER Drivers */ + + +/* PWM Drivers */ + + +/* PM Drivers */ + + +/* Onboard Peripheral Drivers */ + +/* Offboard Peripheral Drivers */ + +/* Peripheral Drivers test example */ + + +#endif diff --git a/bsp/essemi/es32f365x/rtconfig.py b/bsp/essemi/es32f365x/rtconfig.py new file mode 100644 index 0000000000..69c567cc5c --- /dev/null +++ b/bsp/essemi/es32f365x/rtconfig.py @@ -0,0 +1,135 @@ +import os +import sys + +# toolchains options +CROSS_TOOL = 'keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# device options +ARCH = 'arm' +CPU = 'cortex-m3' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': # not support gcc yet + PLATFORM = 'gcc' + EXEC_PATH = 'C:/GCC' + +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' + +elif CROSS_TOOL == 'iar': # not support iar yet + PLATFORM = 'iar' + EXEC_PATH = 'C:/IAR' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config "drivers\linker_scripts\link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS += ' --entry __iar_program_start' + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/essemi/es32f365x/template.ewd b/bsp/essemi/es32f365x/template.ewd new file mode 100644 index 0000000000..b74153e203 --- /dev/null +++ b/bsp/essemi/es32f365x/template.ewd @@ -0,0 +1,2810 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>rt-thread</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>28</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state>$TOOLKIT_DIR$\CONFIG\debugger\Eastsoft\ES32F3656LT.ddf</state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>0</state> + </option> + <option> + <name>OCProductVersion</name> + <state>8.11.1.13270</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>CMSISDAP_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>8.11.1.13270</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\Eastsoft\FlashES32F3656x.board</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreMaster</name> + <state>0</state> + </option> + <option> + <name>OCMulticorePort</name> + <state>53461</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>4</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>1</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>1</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>1</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>1</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>1</state> + </option> + <option> + <name>CatchINTERR</name> + <state>1</state> + </option> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>1</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state></state> + </option> + <option> + <name>CMSISDAPProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPSelectedCPUBehaviour</name> + <state>0</state> + </option> + <option> + <name>ICpuName</name> + <state>0</state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNoSelect</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>GDBSERVER_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJTagBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJTagDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJTagUpdateBreakpoints</name> + <state>_call_main</state> + </option> + </data> + </settings> + <settings> + <name>IJET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>8</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>IjetResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>IjetHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>IjetHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>IjetPowerFromProbe</name> + <state>1</state> + </option> + <option> + <name>IjetPowerRadio</name> + <state>0</state> + </option> + <option> + <name>IjetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>IjetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>IjetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>IjetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTarget</name> + <state>0</state> + </option> + <option> + <name>IjetScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>IjetIRLength</name> + <state>0</state> + </option> + <option> + <name>IjetJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetProtocolRadio</name> + <state>0</state> + </option> + <option> + <name>IjetSwoPin</name> + <state>0</state> + </option> + <option> + <name>IjetCpuClockEdit</name> + <state></state> + </option> + <option> + <name>IjetSwoPrescalerList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>IjetBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>IjetRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>IjetUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>1</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>1</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>1</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>1</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>1</state> + </option> + <option> + <name>CatchINTERR</name> + <state>1</state> + </option> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + 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</option> + <option> + <name>CCSTLinkJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCSTLinkDAPNumber</name> + <state></state> + </option> + <option> + <name>CCSTLinkDebugAccessPortRadio</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>THIRDPARTY_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CThirdPartyDriverDll</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CThirdPartyLogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CThirdPartyLogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>TIFET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVccTypeDefault</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>6</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file> + <loadFlag>1</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/bsp/essemi/es32f365x/template.ewp b/bsp/essemi/es32f365x/template.ewp new file mode 100644 index 0000000000..5d982d93cd --- /dev/null +++ b/bsp/essemi/es32f365x/template.ewp @@ -0,0 +1,2024 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<project>
+ <fileVersion>3</fileVersion>
+ <configuration>
+ <name>rt-thread</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>rt-thread\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>rt-thread\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>rt-thread\List</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>8.11.1.13270</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>8.11.1.13270</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>ES32F3656LT Eastsoft ES32F3656LT</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>25</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibThreads</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CoreVariant</name>
+ <version>25</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>GFPUDeviceSlave</name>
+ <state>ES32F3656LT Eastsoft ES32F3656LT</state>
+ </option>
+ <option>
+ <name>FPU2</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NrRegs</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NEON</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave2</name>
+ <version>25</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>OGCMSISPackSelectDevice</name>
+ </option>
+ <option>
+ <name>OgLibHeap</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGLibAdditionalLocale</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenLocaleTags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>GenLocaleDisplayOnly</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>34</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state>Pa050</state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>00000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCNoLiteralPool</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptStrategySlave</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCGuardCalls</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutputBom</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncInput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccExceptions2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccRTTI2</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>10</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AsmNoLiteralPool</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>3</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state>../../../rtthread.bin</state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ <hasPrio>0</hasPrio>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data />
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>20</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>rtthread.out</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
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+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkMapFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogInitialization</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogSection</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>$PROJ_DIR$\drivers\linker_scripts\link.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
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+ <option>
+ <name>IlinkTreatAsWarn</name>
+ <state></state>
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+ <option>
+ <name>IlinkTreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state>__iar_program_start</state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
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+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>FillerEnd</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CrcAlgorithm</name>
+ <version>1</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcUnitSize</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkThreadsSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogCallGraph</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile_AltDefault</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEncInput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkEncOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkEncOutputBom</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkHeapSelect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLocaleSelect</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data />
+ </settings>
+ </configuration>
+ <configuration>
+ <name>Release</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>0</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>ExePath</name>
+ <state>Release\Exe</state>
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+ <option>
+ <name>ObjPath</name>
+ <state>Release\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Release\List</state>
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+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
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+ <option>
+ <name>Input description</name>
+ <state></state>
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+ <option>
+ <name>Output description</name>
+ <state></state>
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+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>0</state>
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+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
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+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
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+ <option>
+ <name>RTDescription</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>8.11.1.13270</state>
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+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state></state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state></state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>0</state>
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+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
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+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
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+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+ <name>RTConfigPath2</name>
+ <state></state>
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+ <name>GBECoreSlave</name>
+ <version>25</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>0</state>
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+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
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+ <option>
+ <name>GRuntimeLibThreads</name>
+ <state>0</state>
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+ <option>
+ <name>CoreVariant</name>
+ <version>25</version>
+ <state>38</state>
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+ <option>
+ <name>GFPUDeviceSlave</name>
+ <state>-</state>
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+ <option>
+ <name>FPU2</name>
+ <version>0</version>
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+ </option>
+ <option>
+ <name>NrRegs</name>
+ <version>0</version>
+ <state>0</state>
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+ <option>
+ <name>NEON</name>
+ <state>0</state>
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+ <option>
+ <name>GFPUCoreSlave2</name>
+ <version>25</version>
+ <state>38</state>
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+ <option>
+ <name>OGCMSISPackSelectDevice</name>
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+ <option>
+ <name>OgLibHeap</name>
+ <state>0</state>
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+ <name>OGLibAdditionalLocale</name>
+ <state>0</state>
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+ <option>
+ <name>OGPrintfVariant</name>
+ <version>0</version>
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+ <option>
+ <name>OGPrintfMultibyteSupport</name>
+ <state>0</state>
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+ <option>
+ <name>OGScanfVariant</name>
+ <version>0</version>
+ <state>0</state>
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+ <option>
+ <name>OGScanfMultibyteSupport</name>
+ <state>0</state>
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+ <option>
+ <name>GenLocaleTags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>GenLocaleDisplayOnly</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>34</version>
+ <wantNonLocal>1</wantNonLocal>
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+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
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+ <option>
+ <name>CCDefines</name>
+ <state></state>
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+ <name>CCPreprocFile</name>
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+ <name>CCPreprocComments</name>
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+ <option>
+ <name>CCPreprocLine</name>
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+ <name>CCListCFile</name>
+ <state>0</state>
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+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
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+ <name>CCListCMessages</name>
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+ <name>CCListAssFile</name>
+ <state>0</state>
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+ <name>CCListAssSource</name>
+ <state>0</state>
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+ <name>CCEnableRemarks</name>
+ <state>0</state>
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+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
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+ <name>CCDiagRemark</name>
+ <state></state>
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+ <name>CCDiagWarning</name>
+ <state></state>
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+ <option>
+ <name>CCDiagError</name>
+ <state></state>
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+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
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+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>11111110</state>
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+ <name>CCDebugInfo</name>
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+ <option>
+ <name>IEndianMode</name>
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+ <name>IProcessor</name>
+ <state>1</state>
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+ <name>IExtraOptionsCheck</name>
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+ <name>IExtraOptions</name>
+ <state></state>
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+ <name>CCLangConformance</name>
+ <state>0</state>
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+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
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+ <name>CCRequirePrototypes</name>
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+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
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+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
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+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
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+ <name>OutputFile</name>
+ <state></state>
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+ <name>CCLibConfigHeader</name>
+ <state>1</state>
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+ <option>
+ <name>PreInclude</name>
+ <state></state>
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+ <name>CompilerMisraOverride</name>
+ <state>0</state>
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+ <option>
+ <name>CCIncludePath2</name>
+ <state></state>
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+ <name>CCStdIncCheck</name>
+ <state>0</state>
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+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
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+ <name>IProcessorMode2</name>
+ <state>1</state>
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+ <option>
+ <name>CCOptLevel</name>
+ <state>3</state>
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+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
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+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
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+ <name>CompilerMisraRules98</name>
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+ <name>CCPosIndRwpi</name>
+ <state>0</state>
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+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
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+ <option>
+ <name>IccLang</name>
+ <state>0</state>
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+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
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+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
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+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
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+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
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+ <option>
+ <name>CCNoLiteralPool</name>
+ <state>0</state>
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+ <option>
+ <name>CCOptStrategySlave</name>
+ <version>0</version>
+ <state>0</state>
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+ <option>
+ <name>CCGuardCalls</name>
+ <state>1</state>
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+ <option>
+ <name>CCEncSource</name>
+ <state>0</state>
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+ <option>
+ <name>CCEncOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutputBom</name>
+ <state>1</state>
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+ <option>
+ <name>CCEncInput</name>
+ <state>0</state>
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+ <option>
+ <name>IccExceptions2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccRTTI2</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>10</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AsmNoLiteralPool</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ <hasPrio>0</hasPrio>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data />
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>20</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>###Unitialized###</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkMapFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogInitialization</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogSection</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>lnk0t.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>FillerEnd</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CrcAlgorithm</name>
+ <version>1</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcUnitSize</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkThreadsSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogCallGraph</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile_AltDefault</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEncInput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkEncOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkEncOutputBom</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkHeapSelect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLocaleSelect</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data />
+ </settings>
+ </configuration>
+</project>
diff --git a/bsp/essemi/es32f365x/template.eww b/bsp/essemi/es32f365x/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/essemi/es32f365x/template.eww @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\template.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/bsp/essemi/es32f365x/template.uvoptx b/bsp/essemi/es32f365x/template.uvoptx new file mode 100644 index 0000000000..8e6583c22c --- /dev/null +++ b/bsp/essemi/es32f365x/template.uvoptx @@ -0,0 +1,177 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>rt-thread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\build\keil\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>255</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>3</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\CMSIS_AGDI.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0es32f36xx -FL080000 -FS00 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>CMSIS_AGDI</Key> + <Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0es32f36xx.FLM -FS00 -FL080000 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + +</ProjectOpt> diff --git a/bsp/essemi/es32f365x/template.uvprojx b/bsp/essemi/es32f365x/template.uvprojx new file mode 100644 index 0000000000..5b17737066 --- /dev/null +++ b/bsp/essemi/es32f365x/template.uvprojx @@ -0,0 +1,390 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + + <SchemaVersion>2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>rt-thread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>ES32F3656LT</Device> + <Vendor>Eastsoft</Vendor> + <PackID>Eastsoft.ES32_DFP.7.2350</PackID> + <PackURL>http://www.essemi.com</PackURL> + <Cpu>IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0es32f36xx -FS00 -FL080000 -FP0($$Device:ES32F3656LT$Flash\es32f36xx.FLM))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:ES32F3656LT$Device\Include\es32f36xx.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:ES32F3656LT$SVD\es32f36xx.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\keil\</OutputDirectory> + <OutputName>rtthread</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\build\keil\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>1</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments> -MPU</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM3</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments> -MPU</TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3></Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M3"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> + <hadIRAM2>0</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <nSecure>0</nSecure> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x10000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x80000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x10000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <uClangAs>0</uClangAs> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>1</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x08000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase></pXoBase> + <ScatterFile></ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + </Target> + </Targets> + + <RTE> + <apis/> + <components/> + <files/> + </RTE> + +</Project> |