diff options
| author | 会飞的猪 <[email protected]> | 2023-04-09 15:27:51 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-04-09 03:27:51 -0400 |
| commit | 422a9ec167f6bf27bf8d438cc68a2f462e30e7e0 (patch) | |
| tree | f6c8b0bf79ef3fc911ff31a81a83b47718c7c976 /bsp | |
| parent | 85294a8e86db1175159bbc4250f3932ac45463a8 (diff) | |
[bsp/wch]ch32v307 PCLK1(APB1)分频注释纠错
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/system_ch32v30x.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/system_ch32v30x.c b/bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/system_ch32v30x.c index 89df42f23c..999c92fe7e 100644 --- a/bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/system_ch32v30x.c +++ b/bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/system_ch32v30x.c @@ -369,7 +369,7 @@ static void SetSysClockTo48(void) RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ + /* PCLK1 = HCLK/2 */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ @@ -441,7 +441,7 @@ static void SetSysClockTo56(void) RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ + /* PCLK1 = HCLK/2 */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ @@ -514,7 +514,7 @@ static void SetSysClockTo72(void) RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ + /* PCLK1 = HCLK/2 */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ @@ -588,7 +588,7 @@ static void SetSysClockTo96(void) RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ + /* PCLK1 = HCLK/2 */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ @@ -662,7 +662,7 @@ static void SetSysClockTo120(void) RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ + /* PCLK1 = HCLK/2 */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ @@ -736,7 +736,7 @@ static void SetSysClockTo144(void) RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ + /* PCLK1 = HCLK/2 */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ |