summaryrefslogtreecommitdiff
path: root/bsp
diff options
context:
space:
mode:
authorhydevcode <[email protected]>2024-09-30 08:47:39 +0800
committerGitHub <[email protected]>2024-09-29 20:47:39 -0400
commit66d54ea8c0f6eae5713985a7fffd099ef3eea621 (patch)
treef8ffdefca14a723c4c157c710affd4b0cfdedd23 /bsp
parente7e44ec7e8ad8ea5a8642a09ad51bdfb1ca73408 (diff)
[bsp][nxp][rsoc] Fix compilation issues with bsp of nxp/lxp series
Diffstat (limited to 'bsp')
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c272
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c250
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c814
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c1102
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.libbin0 -> 14156 bytes
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower.abin0 -> 6054 bytes
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h46
-rw-r--r--bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h2
-rw-r--r--bsp/nxp/lpc/lpc5410x/applications/board.h11
-rw-r--r--bsp/nxp/lpc/lpc5410x/drivers/drv_uart.c1
-rw-r--r--bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.libbin0 -> 9650 bytes
-rw-r--r--bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.abin0 -> 18500 bytes
-rw-r--r--bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.abin0 -> 9512 bytes
-rw-r--r--bsp/nxp/lpc/lpc54114-lite/drivers/drv_spi.c2
14 files changed, 1301 insertions, 1199 deletions
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c
index 1cd349e94d..fcc4820860 100644
--- a/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c
@@ -1,23 +1,9 @@
-//*****************************************************************************
-//
-// Startup code for use with GNU tools.
-//
-//*****************************************************************************
-
-
-//*****************************************************************************
-//
-// Forward declaration of the default fault handlers.
-//
-//*****************************************************************************
+/* Startup code for use with GNU tools.*/
+/* Forward declaration of the default fault handlers.*/
static void Reset_Handler(void);
static void Default_Handler(void);
-//*****************************************************************************
-//
-// External declaration for the interrupt handler used by the application.
-//
-//*****************************************************************************
+/* External declaration for the interrupt handler used by the application.*/
void NMI_Handler(void) __attribute__((weak, alias("Default_Handler")));
void HardFault_Handler(void) __attribute__((weak, alias("Default_Handler")));
void MemManage_Handler(void) __attribute__((weak, alias("Default_Handler")));
@@ -59,182 +45,161 @@ void ADC_SEQA_IRQHandler(void) __attribute__((weak, alias("Default_Handler"
void ADC_SEQB_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void ADC_THCMP_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void RTC_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
-//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
+/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
void MAILBOX_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void GINT1_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT4_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT5_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT6_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void PIN_INT7_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
-//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
-//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
-//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
+/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
+/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
+/*void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));*/
void RIT_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved41_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved42_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved43_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
void Reserved44_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
-//*****************************************************************************
-//
-// The entry point for the application.
-//
-//*****************************************************************************
+/* The entry point for the application.*/
extern int main(void);
-//*****************************************************************************
-//
-// Reserve space for the system stack.
-//
-//*****************************************************************************
+/* Reserve space for the system stack.*/
static unsigned long pulStack[512];
-//*****************************************************************************
-//
-// The vector table. Note that the proper constructs must be placed on this to
-// ensure that it ends up at physical address 0x0000.0000.
-//
-//*****************************************************************************
+/* The vector table. Note that the proper constructs must be placed on this to*/
+/* ensure that it ends up at physical address 0x0000.0000.*/
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
(void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
- // The initial stack pointer
- Reset_Handler, // Reset Handler
- NMI_Handler, // NMI Handler
- HardFault_Handler, // Hard Fault Handler
- MemManage_Handler, // MPU Fault Handler
- BusFault_Handler, // Bus Fault Handler
- UsageFault_Handler, // Usage Fault Handler
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- SVC_Handler, // SVCall Handler
- DebugMon_Handler, // Debug Monitor Handler
- 0, // Reserved
- PendSV_Handler, // PendSV Handler
- SysTick_Handler, // SysTick Handler
+ /* The initial stack pointer*/
+ Reset_Handler, /* Reset Handler*/
+ NMI_Handler, /* NMI Handler*/
+ HardFault_Handler, /* Hard Fault Handler*/
+ MemManage_Handler, /* MPU Fault Handler*/
+ BusFault_Handler, /* Bus Fault Handler*/
+ UsageFault_Handler, /* Usage Fault Handler*/
+ 0, /* Reserved*/
+ 0, /* Reserved*/
+ 0, /* Reserved*/
+ 0, /* Reserved*/
+ SVC_Handler, /* SVCall Handler*/
+ DebugMon_Handler, /* Debug Monitor Handler*/
+ 0, /* Reserved*/
+ PendSV_Handler, /* PendSV Handler*/
+ SysTick_Handler, /* SysTick Handler*/
- // External Interrupts
- WDT_IRQHandler,
- BOD_IRQHandler,
- Reserved_IRQHandler,
- DMA_IRQHandler,
- GINT0_IRQHandler,
- PIN_INT0_IRQHandler,
- PIN_INT1_IRQHandler,
- PIN_INT2_IRQHandler,
- PIN_INT3_IRQHandler,
- UTICK_IRQHandler,
- MRT_IRQHandler,
- CT32B0_IRQHandler,
- CT32B1_IRQHandler,
- CT32B2_IRQHandler,
- CT32B3_IRQHandler,
- CT32B4_IRQHandler,
- SCT0_IRQHandler,
- UART0_IRQHandler,
- UART1_IRQHandler,
- UART2_IRQHandler,
- UART3_IRQHandler,
- I2C0_IRQHandler,
- I2C1_IRQHandler,
- I2C2_IRQHandler,
- SPI0_IRQHandler,
- SPI1_IRQHandler,
- ADC_SEQA_IRQHandler,
- ADC_SEQB_IRQHandler,
- ADC_THCMP_IRQHandler,
- RTC_IRQHandler,
- Reserved_IRQHandler,
- MAILBOX_IRQHandler,
- GINT1_IRQHandler,
- PIN_INT4_IRQHandler,
- PIN_INT5_IRQHandler,
- PIN_INT6_IRQHandler,
- PIN_INT7_IRQHandler,
- Reserved_IRQHandler,
- Reserved_IRQHandler,
- Reserved_IRQHandler,
- RIT_IRQHandler,
- Reserved41_IRQHandler,
- Reserved42_IRQHandler,
- Reserved43_IRQHandler,
- Reserved44_IRQHandler,
+ /* External Interrupts*/
+ WDT_IRQHandler,
+ BOD_IRQHandler,
+ Reserved_IRQHandler,
+ DMA_IRQHandler,
+ GINT0_IRQHandler,
+ PIN_INT0_IRQHandler,
+ PIN_INT1_IRQHandler,
+ PIN_INT2_IRQHandler,
+ PIN_INT3_IRQHandler,
+ UTICK_IRQHandler,
+ MRT_IRQHandler,
+ CT32B0_IRQHandler,
+ CT32B1_IRQHandler,
+ CT32B2_IRQHandler,
+ CT32B3_IRQHandler,
+ CT32B4_IRQHandler,
+ SCT0_IRQHandler,
+ UART0_IRQHandler,
+ UART1_IRQHandler,
+ UART2_IRQHandler,
+ UART3_IRQHandler,
+ I2C0_IRQHandler,
+ I2C1_IRQHandler,
+ I2C2_IRQHandler,
+ SPI0_IRQHandler,
+ SPI1_IRQHandler,
+ ADC_SEQA_IRQHandler,
+ ADC_SEQB_IRQHandler,
+ ADC_THCMP_IRQHandler,
+ RTC_IRQHandler,
+ Reserved_IRQHandler,
+ MAILBOX_IRQHandler,
+ GINT1_IRQHandler,
+ PIN_INT4_IRQHandler,
+ PIN_INT5_IRQHandler,
+ PIN_INT6_IRQHandler,
+ PIN_INT7_IRQHandler,
+ Reserved_IRQHandler,
+ Reserved_IRQHandler,
+ Reserved_IRQHandler,
+ RIT_IRQHandler,
+ Reserved41_IRQHandler,
+ Reserved42_IRQHandler,
+ Reserved43_IRQHandler,
+ Reserved44_IRQHandler,
};
-//**RIT_IRQHandler ***************************************************************************
-// Reserved41_IRQHandler
-// TReserved42_IRQHandler he following are constructs created by the linker, indicating where the
-// tReserved43_IRQHandler he "data" and "bss" segments reside in memory. The initializers for the
-// fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment.
-//
-//*****************************************************************************
+/* RIT_IRQHandler */
+/* Reserved41_IRQHandler*/
+/* TReserved42_IRQHandler he following are constructs created by the linker, indicating where the*/
+/* tReserved43_IRQHandler he "data" and "bss" segments reside in memory. The initializers for the*/
+/* fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment.*/
extern unsigned long _etext;
extern unsigned long _data;
extern unsigned long _edata;
extern unsigned long _bss;
extern unsigned long _ebss;
-//*****************************************************************************
-//
-// This is the code that gets called when the processor first starts execution
-// following a reset event. Only the absolutely necessary set is performed,
-// after which the application supplied entry() routine is called. Any fancy
-// actions (such as making decisions based on the reset cause register, and
-// resetting the bits in that register) are left solely in the hands of the
-// application.
-//
-//*****************************************************************************
+/* This is the code that gets called when the processor first starts execution*/
+/* following a reset event. Only the absolutely necessary set is performed,*/
+/* after which the application supplied entry() routine is called. Any fancy*/
+/* actions (such as making decisions based on the reset cause register, and*/
+/* resetting the bits in that register) are left solely in the hands of the*/
+/* application.*/
static void Reset_Handler(void)
{
unsigned long *pulSrc, *pulDest;
- //
- // Copy the data segment initializers from flash to SRAM.
- //
+ /* Copy the data segment initializers from flash to SRAM.*/
pulSrc = &_etext;
+ /* cppcheck-suppress comparePointers */
for(pulDest = &_data; pulDest < &_edata; )
{
*pulDest++ = *pulSrc++;
}
-
-
+
+
#if !defined (__USE_LPCOPEN)
-// LPCOpen init code deals with FP and VTOR initialisation
+/* LPCOpen init code deals with FP and VTOR initialisation*/
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
/*
* Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/
- // CPACR is located at address 0xE000ED88
+ /* CPACR is located at address 0xE000ED88*/
asm("LDR.W R0, =0xE000ED88");
- // Read CPACR
+ /* Read CPACR*/
asm("LDR R1, [R0]");
- // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ /* Set bits 20-23 to enable CP10 and CP11 coprocessors*/
asm(" ORR R1, R1, #(0xF << 20)");
- // Write back the modified value to the CPACR
+ /* Write back the modified value to the CPACR*/
asm("STR R1, [R0]");
-#endif // (__VFP_FP__) && !(__SOFTFP__)
- // ******************************
- // Check to see if we are running the code from a non-zero
- // address (eg RAM, external flash), in which case we need
- // to modify the VTOR register to tell the CPU that the
- // vector table is located at a non-0x0 address.
+#endif /* (__VFP_FP__) && !(__SOFTFP__)*/
+ /* Check to see if we are running the code from a non-zero*/
+ /* address (eg RAM, external flash), in which case we need*/
+ /* to modify the VTOR register to tell the CPU that the*/
+ /* vector table is located at a non-0x0 address.*/
- // Note that we do not use the CMSIS register access mechanism,
- // as there is no guarantee that the project has been configured
- // to use CMSIS.
+ /* Note that we do not use the CMSIS register access mechanism,*/
+ /* as there is no guarantee that the project has been configured*/
+ /* to use CMSIS.*/
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
- if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
- // CMSIS : SCB->VTOR = <address of vector table>
+ if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000)
+ {
+ /* CMSIS : SCB->VTOR = <address of vector table>*/
*pSCB_VTOR = (unsigned int) g_pfnVectors;
}
#endif
-
- //
- // Zero fill the bss segment.
- //
+
+ /* Zero fill the bss segment.*/
__asm(" ldr r0, =_bss\n"
" ldr r1, =_ebss\n"
" mov r2, #0\n"
@@ -245,28 +210,21 @@ static void Reset_Handler(void)
" strlt r2, [r0], #4\n"
" blt zero_loop");
- // call system init.
- SystemInit();
+ /* call system init.*/
+ extern void SystemInit(void);
+ SystemInit();
- //
- // Call the application's entry point.
- //
+ /* Call the application's entry point.*/
main();
}
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives an unexpected
-// interrupt. This simply enters an infinite loop, preserving the system state
-// for examination by a debugger.
-//
-//*****************************************************************************
+/* This is the code that gets called when the processor receives an unexpected*/
+/* interrupt. This simply enters an infinite loop, preserving the system state*/
+/* for examination by a debugger.*/
static void Default_Handler(void)
{
- //
- // Go into an infinite loop.
- //
+ /* Go into an infinite loop.*/
while(1)
{
}
-}
+} \ No newline at end of file
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c
index 775200c1fc..4f7aa8c5e9 100644
--- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_i2cmond.c
@@ -38,171 +38,189 @@
/* Private data structure used for the I2C monitor driver, holds the driver and
peripheral context */
typedef struct {
- void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
- LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */
- i2cMonCapReadyCB pCapCompCB; /*!< Capture complete callback */
- i2cMonSetupDMACB pDmaSetupCB; /*!< DMA setup callback */
- ROM_I2CMON_CAP_T *pCap; /*!< Pointer to current capture descriptor */
- ErrorCode_t pendingStatus; /*!< Pending monitor transfer status before clocking transfer */
+ void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
+ LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */
+ i2cMonCapReadyCB pCapCompCB; /*!< Capture complete callback */
+ i2cMonSetupDMACB pDmaSetupCB; /*!< DMA setup callback */
+ ROM_I2CMON_CAP_T *pCap; /*!< Pointer to current capture descriptor */
+ ErrorCode_t pendingStatus; /*!< Pending monitor transfer status before clocking transfer */
} I2CMON_DATACONTEXT_T;
void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
;
-// **********************************************************
+/* ********************************************************** */
uint32_t i2cmon_get_mem_size(void)
{
- return sizeof(I2CMON_DATACONTEXT_T);
+ return sizeof(I2CMON_DATACONTEXT_T);
}
ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit)
{
- I2CMON_DATACONTEXT_T *pDrv;
- uint32_t reg;
+ I2CMON_DATACONTEXT_T *pDrv;
+ uint32_t reg;
- /* Verify alignment is at least 4 bytes */
- if (((uint32_t) mem & 0x3) != 0) {
- return NULL;
- }
+ /* Verify alignment is at least 4 bytes */
+ if (((uint32_t) mem & 0x3) != 0)
+ {
+ return NULL;
+ }
- pDrv = (I2CMON_DATACONTEXT_T *) mem;
- memset(pDrv, 0, sizeof(I2CMON_DATACONTEXT_T));
+ pDrv = (I2CMON_DATACONTEXT_T *) mem;
+ memset(pDrv, 0, sizeof(I2CMON_DATACONTEXT_T));
- /* Save base of peripheral and pointer to user data */
- pDrv->pUserData = pInit->pUserData;
- pDrv->base = (LPC_I2C_T *) pInit->base;
+ /* Save base of peripheral and pointer to user data */
+ pDrv->pUserData = pInit->pUserData;
+ pDrv->base = (LPC_I2C_T *) pInit->base;
- /* Clear pending monitor statuses */
- pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
- while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) {
- /* Toss input data */
- reg = pDrv->base->MONRXDAT;
- }
+ /* Clear pending monitor statuses */
+ pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
+ while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0)
+ {
+ /* Toss input data */
+ reg = pDrv->base->MONRXDAT;
+ }
- /* Enable I2C monitor interface */
- reg = pDrv->base->CFG | I2C_CFG_MONEN;
- if (pInit->stretch != 0) {
- reg |= I2C_CFG_MONCLKSTR;
- }
- pDrv->base->CFG = reg;
+ /* Enable I2C monitor interface */
+ reg = pDrv->base->CFG | I2C_CFG_MONEN;
+ if (pInit->stretch != 0)
+ {
+ reg |= I2C_CFG_MONCLKSTR;
+ }
+ pDrv->base->CFG = reg;
- return pDrv;
+ return pDrv;
}
void i2cmom_register_callback(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB)
{
- I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
+ I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
- if (cbIndex == ROM_I2CMON_CAPTUREREADY_CB) {
- pDrv->pCapCompCB = (i2cMonCapReadyCB) pCB;
- }
- else if (cbIndex == ROM_I2CMON_DMASETUP_CB) {
- pDrv->pDmaSetupCB = (i2cMonSetupDMACB) pCB;
- }
+ if (cbIndex == ROM_I2CMON_CAPTUREREADY_CB)
+ {
+ pDrv->pCapCompCB = (i2cMonCapReadyCB) pCB;
+ }
+ else if (cbIndex == ROM_I2CMON_DMASETUP_CB)
+ {
+ pDrv->pDmaSetupCB = (i2cMonSetupDMACB) pCB;
+ }
}
ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap)
{
- I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
+ I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
- /* I2C master controller should be pending and idle */
- if (pCap == NULL) {
- return ERR_I2C_PARAM;
- }
+ /* I2C master controller should be pending and idle */
+ if (pCap == NULL)
+ {
+ return ERR_I2C_PARAM;
+ }
- /* Verify receive buffer alignment */
- if ((pCap->startBuff == NULL) || ((((uint32_t) pCap->startBuff) & 0x1) != 0) || (pCap->startBuffSz == 0)) {
- pCap->status = ERR_I2C_PARAM;
- return ERR_I2C_PARAM;
- }
+ /* Verify receive buffer alignment */
+ if ((pCap->startBuff == NULL) || ((((uint32_t) pCap->startBuff) & 0x1) != 0) || (pCap->startBuffSz == 0))
+ {
+ pCap->status = ERR_I2C_PARAM;
+ return ERR_I2C_PARAM;
+ }
- pDrv->pCap = pCap;
- pCap->capStartBuffSz = 0;
- pDrv->pendingStatus = LPC_OK;
- pCap->status = ERR_I2C_BUSY;
+ pDrv->pCap = pCap;
+ pCap->capStartBuffSz = 0;
+ pDrv->pendingStatus = LPC_OK;
+ pCap->status = ERR_I2C_BUSY;
- if ((pCap->flags & ROM_I2CMON_FLAG_FLUSH) != 0) {
- while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0) {
- /* Toss input data */
- volatile uint32_t reg = pDrv->base->MONRXDAT;
- }
- }
+ if ((pCap->flags & ROM_I2CMON_FLAG_FLUSH) != 0)
+ {
+ while ((pDrv->base->STAT & I2C_STAT_MONRDY) != 0)
+ {
+ /* Toss input data */
+ volatile uint32_t reg = pDrv->base->MONRXDAT;
+ (void)reg;
+ }
+ }
- /* Clear controller state */
- pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
+ /* Clear controller state */
+ pDrv->base->STAT = (I2C_STAT_MONIDLE | I2C_STAT_MONOV);
- if (((pCap->flags & ROM_I2CMON_FLAG_DMARX) != 0) && (pDrv->pDmaSetupCB)) {
- pDrv->pDmaSetupCB(pHandle, pCap);
+ if (((pCap->flags & ROM_I2CMON_FLAG_DMARX) != 0) && (pDrv->pDmaSetupCB))
+ {
+ pDrv->pDmaSetupCB(pHandle, pCap);
- /* Enable supported monitor interrupts */
- pDrv->base->INTENSET = (I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE);
- }
- else {
- pCap->flags &= ~ROM_I2CMON_FLAG_DMARX;
+ /* Enable supported monitor interrupts */
+ pDrv->base->INTENSET = (I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE);
+ }
+ else {
+ pCap->flags &= ~ROM_I2CMON_FLAG_DMARX;
- /* Enable supported monitor interrupts */
- pDrv->base->INTENSET = (I2C_INTENSET_MONRDY | I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE);
- }
+ /* Enable supported monitor interrupts */
+ pDrv->base->INTENSET = (I2C_INTENSET_MONRDY | I2C_INTENSET_MONOV | I2C_INTENSET_MONIDLE);
+ }
- /* Is transfer blocking? */
- if ((pCap->flags & ROM_I2CMON_FLAG_BLOCKING) != 0) {
- while (pCap->status == ERR_I2C_BUSY) {
- i2cmon_transfer_handler(pHandle);
- }
- }
+ /* Is transfer blocking? */
+ if ((pCap->flags & ROM_I2CMON_FLAG_BLOCKING) != 0)
+ {
+ while (pCap->status == ERR_I2C_BUSY)
+ {
+ i2cmon_transfer_handler(pHandle);
+ }
+ }
- return pCap->status;
+ return pCap->status;
}
-// Otime = "optimize for speed of code execution"
-// ...add this pragma 1 line above the interrupt service routine function.
+/* Otime = "optimize for speed of code execution"*/
+/* ...add this pragma 1 line above the interrupt service routine function.*/
void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle)
{
- I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
- ROM_I2CMON_CAP_T *pCap = pDrv->pCap;
- uint16_t data = 0, *pData;
+ I2CMON_DATACONTEXT_T *pDrv = (I2CMON_DATACONTEXT_T *) pHandle;
+ ROM_I2CMON_CAP_T *pCap = pDrv->pCap;
+ uint16_t data = 0, *pData;
- uint32_t status = pDrv->base->STAT;
+ uint32_t status = pDrv->base->STAT;
- if (status & I2C_STAT_MONOV) {
- /* Monitor data overflow */
- data = pDrv->base->MONRXDAT;
- pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
+ if (status & I2C_STAT_MONOV)
+ {
+ /* Monitor data overflow */
+ data = pDrv->base->MONRXDAT;
+ pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
- /* Clear Status Flags */
- pDrv->base->STAT = I2C_STAT_MONOV;
- }
- else if (status & I2C_STAT_MONRDY) {
- /* Monitor ready */
- data = pDrv->base->MONRXDAT;
+ /* Clear Status Flags */
+ pDrv->base->STAT = I2C_STAT_MONOV;
+ }
+ else if (status & I2C_STAT_MONRDY)
+ {
+ /* Monitor ready */
+ data = pDrv->base->MONRXDAT;
- /* Enough room to place this data? */
- if (pCap->capStartBuffSz >= pCap->startBuffSz) {
- /* Data overflow */
- pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
- }
- else {
- pData = (uint16_t *) pCap->startBuff;
+ /* Enough room to place this data? */
+ if (pCap->capStartBuffSz >= pCap->startBuffSz)
+ {
+ /* Data overflow */
+ pDrv->pendingStatus = ERR_I2C_BUFFER_OVERFLOW;
+ }
+ else {
+ pData = (uint16_t *) pCap->startBuff;
- pData[pCap->capStartBuffSz] = data;
- pCap->capStartBuffSz++;
- }
- }
+ pData[pCap->capStartBuffSz] = data;
+ pCap->capStartBuffSz++;
+ }
+ }
- /* Capture complete? */
- if ((status & I2C_INTSTAT_MONIDLE) != 0) {
- pDrv->base->INTENCLR = (I2C_INTENCLR_MONRDY | I2C_INTENCLR_MONOV |
- I2C_INTENCLR_MONIDLE);
- pCap->status = pDrv->pendingStatus;
- if (pDrv->pCapCompCB) {
- pDrv->pCapCompCB(pHandle, pCap);
- }
- }
+ /* Capture complete? */
+ if ((status & I2C_INTSTAT_MONIDLE) != 0)
+ {
+ pDrv->base->INTENCLR = (I2C_INTENCLR_MONRDY | I2C_INTENCLR_MONOV |
+ I2C_INTENCLR_MONIDLE);
+ pCap->status = pDrv->pendingStatus;
+ if (pDrv->pCapCompCB)
+ {
+ pDrv->pCapCompCB(pHandle, pCap);
+ }
+ }
}
uint32_t i2cmon_get_driver_version(void)
{
- return DRVVERSION;
+ return DRVVERSION;
}
-// *********************************************************
+/* ********************************************************** */
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c
index f8fcf0207b..b9bf27c518 100644
--- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_uart.c
@@ -32,564 +32,638 @@
#include "error.h"
#include "hw_uart_rom_api.h"
-#define UART_IDLE_FIX /* Remove once IDLE problem is fixed */
+#define UART_IDLE_FIX /* Remove once IDLE problem is fixed */
/* UART Driver internal data structure */
typedef struct {
- void *pUserData; /* Pointer to user data */
- UART_REGS_T *pREGS; /* Pointer to Registers */
- UART_DATA_T xfer[2]; /* TX/RX transfer data */
+ void *pUserData; /* Pointer to user data */
+ UART_REGS_T *pREGS; /* Pointer to Registers */
+ UART_DATA_T xfer[2]; /* TX/RX transfer data */
#ifdef UART_IDLE_FIX
- uint32_t dly; /* Delay to count 1 bit time; REMOVE: when H/W is fixed */
+ uint32_t dly; /* Delay to count 1 bit time; REMOVE: when H/W is fixed */
#endif
- void(*cbTable[UART_CB_RESERVED]) (UART_HANDLE_T, UART_EVENT_T, void *); /* Call-back index table */
+ void(*cbTable[UART_CB_RESERVED]) (UART_HANDLE_T, UART_EVENT_T, void *); /* Call-back index table */
} UART_DRIVER_T;
/* PRIVATE: Division logic to divide without integer overflow */
static uint32_t _UART_DivClk(uint32_t pclk, uint32_t m)
{
- uint32_t q, r, u = pclk >> 24, l = pclk << 8;
- m = m + 256;
- q = (1 << 24) / m;
- r = (1 << 24) - (q * m);
- return ((q * u) << 8) + (((r * u) << 8) + l) / m;
+ uint32_t q, r, u = pclk >> 24, l = pclk << 8;
+ m = m + 256;
+ q = (1 << 24) / m;
+ r = (1 << 24) - (q * m);
+ return ((q * u) << 8) + (((r * u) << 8) + l) / m;
}
/* PRIVATE: Get highest Over sampling value */
static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict)
{
- int32_t i, max = strict ? 16 : 5;
- for (i = 16; i >= max; i--) {
- if (!(val % i)) {
- return i;
- }
- }
- return 0;
+ int32_t i, max = strict ? 16 : 5;
+ for (i = 16; i >= max; i--)
+ {
+ if (!(val % i))
+ {
+ return i;
+ }
+ }
+ return 0;
}
/* PRIVATE: Queue a transfer in UART */
static ErrorCode_t _UART_Xfer(UART_DRIVER_T *pUART, void *buff, uint16_t len, uint8_t op)
{
- UART_DATA_T *xfr = &pUART->xfer[op];
+ UART_DATA_T *xfr = &pUART->xfer[op];
- /* Xfer of 0 bytes in a UART should always be successful */
- if (!len) {
- return LPC_OK;
- }
+ /* Xfer of 0 bytes in a UART should always be successful */
+ if (!len)
+ {
+ return LPC_OK;
+ }
- /* Check if a Xfer is alredy in progress */
- if (xfr->count > xfr->offset) {
- return ERR_BUSY;
- }
+ /* Check if a Xfer is alredy in progress */
+ if (xfr->count > xfr->offset)
+ {
+ return ERR_BUSY;
+ }
- xfr->buf = (void *) buff;
- xfr->count = len;
- xfr->offset = 0;
- xfr->state = UART_ST_BUSY;
- if (!op) {
- pUART->pREGS->INTENSET = UART_INT_TXRDY;
- }
- else {
- pUART->pREGS->INTENSET = UART_INT_RXRDY | UART_INT_FRMERR | UART_INT_RXNOISE | UART_INT_START | UART_INT_OVR;
- }
+ xfr->buf = (void *) buff;
+ xfr->count = len;
+ xfr->offset = 0;
+ xfr->state = UART_ST_BUSY;
+ if (!op)
+ {
+ pUART->pREGS->INTENSET = UART_INT_TXRDY;
+ }
+ else {
+ pUART->pREGS->INTENSET = UART_INT_RXRDY | UART_INT_FRMERR | UART_INT_RXNOISE | UART_INT_START | UART_INT_OVR;
+ }
- return LPC_OK;
+ return LPC_OK;
}
/* Calculate error difference */
static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev)
{
- uint32_t err = n - (n / d) * d;
- uint32_t herr = ((n / d) + 1) * d - n;
- if (herr < err) {
- err = herr;
- }
+ uint32_t err = n - (n / d) * d;
+ uint32_t herr = ((n / d) + 1) * d - n;
+ if (herr < err)
+ {
+ err = herr;
+ }
- if (*prev <= err) {
- return 0;
- }
- *prev = err;
- return (herr == err) + 1;
+ if (*prev <= err)
+ {
+ return 0;
+ }
+ *prev = err;
+ return (herr == err) + 1;
}
/* Calculate the base DIV value */
static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub)
{
- int32_t i = 0;
- uint32_t perr = ~0UL;
+ int32_t i = 0;
+ uint32_t perr = ~0UL;
- if (!ub->div) {
- i = ub->ovr ? ub->ovr : 16;
- }
+ if (!ub->div)
+ {
+ i = ub->ovr ? ub->ovr : 16;
+ }
- for (; i > 4; i--) {
- int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr);
+ for (; i > 4; i--)
+ {
+ int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr);
- /* Continue when no improvement seen in err value */
- if (!tmp) {
- continue;
- }
+ /* Continue when no improvement seen in err value */
+ if (!tmp)
+ {
+ continue;
+ }
- ub->div = tmp - 1;
- if (ub->ovr == i) {
- break;
- }
- ub->ovr = i;
- }
+ ub->div = tmp - 1;
+ if (ub->ovr == i)
+ {
+ break;
+ }
+ ub->ovr = i;
+ }
- if (!ub->ovr) {
- return ERR_UART_BAUDRATE;
- }
+ if (!ub->ovr)
+ {
+ return ERR_UART_BAUDRATE;
+ }
- ub->div += ub->clk / (ub->baud * ub->ovr);
- if (!ub->div) {
- return ERR_UART_BAUDRATE;
- }
+ ub->div += ub->clk / (ub->baud * ub->ovr);
+ if (!ub->div)
+ {
+ return ERR_UART_BAUDRATE;
+ }
- ub->baud = ub->clk / (ub->div * ub->ovr);
- return LPC_OK;
+ ub->baud = ub->clk / (ub->div * ub->ovr);
+ return LPC_OK;
}
/* Calculate the best MUL value */
static void _UART_CalcMul(UART_BAUD_T *ub)
{
- uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr;
+ uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr;
- /* If clock is UART's base clock calculate only the divider */
- for (m = 0; m < 256; m++) {
- uint32_t ov = ovr, x, v, tmp;
+ /* If clock is UART's base clock calculate only the divider */
+ for (m = 0; m < 256; m++)
+ {
+ uint32_t ov = ovr, x, v, tmp;
- /* Get clock and calculate error */
- x = _UART_DivClk(pclk, m);
- tmp = _CalcErr(x, ub->baud, &perr);
- v = (x / ub->baud) + tmp - 1;
+ /* Get clock and calculate error */
+ x = _UART_DivClk(pclk, m);
+ tmp = _CalcErr(x, ub->baud, &perr);
+ v = (x / ub->baud) + tmp - 1;
- /* Update if new error is better than previous best */
- if (!tmp || (ovr && (v % ovr)) ||
- (!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0))) {
- continue;
- }
+ /* Update if new error is better than previous best */
+ if (!tmp || (ovr && (v % ovr)) ||
+ (!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0)))
+ {
+ continue;
+ }
- ub->ovr = ov;
- ub->mul = m;
- ub->clk = x;
- ub->div = tmp - 1;
- }
+ ub->ovr = ov;
+ ub->mul = m;
+ ub->clk = x;
+ ub->div = tmp - 1;
+ }
}
/* PRIVATE: Invoke UART Call back functions */
static void _UART_InvokeCB(UART_DRIVER_T *pUART, UART_EVENT_T event, void *arg)
{
- void (*cbfn)(UART_HANDLE_T, UART_EVENT_T, void *);
- cbfn = pUART->cbTable[(uint32_t) event >> 1];
- if (cbfn != NULL) {
- cbfn((UART_HANDLE_T) pUART, event, arg);
- }
+ void (*cbfn)(UART_HANDLE_T, UART_EVENT_T, void *);
+ cbfn = pUART->cbTable[(uint32_t) event >> 1];
+ if (cbfn != NULL)
+ {
+ cbfn((UART_HANDLE_T) pUART, event, arg);
+ }
}
/* PRIVATE: Handler for data transfers */
static void _UART_HandleTxRx(UART_HANDLE_T hUART, UART_EVENT_T event, void *arg)
{
- UART_DATA_T *dat = (UART_DATA_T *) arg;
- UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
- uint16_t *buf16 = dat->buf;
- uint8_t *buf8 = dat->buf;
+ UART_DATA_T *dat = (UART_DATA_T *) arg;
+ UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
+ uint16_t *buf16 = dat->buf;
+ uint8_t *buf8 = dat->buf;
- /* Transmit data */
- if (event == UART_TX_DATA) {
- while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_TXRDY)) {
- if (dat->dwidth) {
- pUART->pREGS->TXDAT = *buf16++;
- }
- else {
- pUART->pREGS->TXDAT = *buf8++;
- }
- dat->count--;
- }
- return;
- }
+ /* Transmit data */
+ if (event == UART_TX_DATA)
+ {
+ while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_TXRDY))
+ {
+ if (dat->dwidth)
+ {
+ pUART->pREGS->TXDAT = *buf16++;
+ }
+ else {
+ pUART->pREGS->TXDAT = *buf8++;
+ }
+ dat->count--;
+ }
+ return;
+ }
- /* Receive data */
- while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_RXRDY)) {
- if (dat->dwidth) {
- *buf16++ = pUART->pREGS->RXDAT & 0x1FF;
- }
- else {
- *buf8++ = pUART->pREGS->RXDAT & 0xFF;
- }
- dat->count--;
- }
+ /* Receive data */
+ while (dat->count && (pUART->pREGS->INTSTAT & UART_INT_RXRDY))
+ {
+ if (dat->dwidth)
+ {
+ *buf16++ = pUART->pREGS->RXDAT & 0x1FF;
+ }
+ else {
+ *buf8++ = pUART->pREGS->RXDAT & 0xFF;
+ }
+ dat->count--;
+ }
}
/* Handle UART Receive event */
static int32_t _UART_HandleXfer(UART_DRIVER_T *pUART, uint8_t op)
{
- UART_DATA_T dat;
- UART_DATA_T *xfr = &pUART->xfer[op];
+ UART_DATA_T dat;
+ UART_DATA_T *xfr = &pUART->xfer[op];
- /* See if the transfer is already complete */
- if (xfr->offset >= xfr->count) {
- return 2;
- }
+ /* See if the transfer is already complete */
+ if (xfr->offset >= xfr->count)
+ {
+ return 2;
+ }
- /* Fill the buffer data structure */
- dat.count = xfr->count - xfr->offset;
- dat.dwidth = ((pUART->pREGS->CFG >> 2) & 3) > 1;
- if (dat.dwidth) {
- dat.buf = &((uint16_t *) xfr->buf)[xfr->offset];
- }
- else {
- dat.buf = &((uint8_t *) xfr->buf)[xfr->offset];
- }
+ /* Fill the buffer data structure */
+ dat.count = xfr->count - xfr->offset;
+ dat.dwidth = ((pUART->pREGS->CFG >> 2) & 3) > 1;
+ if (dat.dwidth)
+ {
+ dat.buf = &((uint16_t *) xfr->buf)[xfr->offset];
+ }
+ else {
+ dat.buf = &((uint8_t *) xfr->buf)[xfr->offset];
+ }
- if (!xfr->offset && xfr->count) {
- _UART_InvokeCB(pUART, UART_TX_START, xfr);
- }
+ if (!xfr->offset && xfr->count)
+ {
+ _UART_InvokeCB(pUART, UART_TX_START, xfr);
+ }
- pUART->cbTable[UART_CB_DATA]((UART_HANDLE_T) pUART, (UART_EVENT_T) (UART_TX_DATA + op), &dat);
- xfr->offset = (xfr->count - dat.count);
+ pUART->cbTable[UART_CB_DATA]((UART_HANDLE_T) pUART, (UART_EVENT_T) (UART_TX_DATA + op), &dat);
+ xfr->offset = (xfr->count - dat.count);
- if (xfr->offset >= xfr->count) {
- if (!op) {
- pUART->pREGS->INTENCLR = UART_INT_TXRDY;
- }
- else {
- pUART->pREGS->INTENCLR = UART_INT_RXRDY;
- }
+ if (xfr->offset >= xfr->count)
+ {
+ if (!op)
+ {
+ pUART->pREGS->INTENCLR = UART_INT_TXRDY;
+ }
+ else {
+ pUART->pREGS->INTENCLR = UART_INT_RXRDY;
+ }
- _UART_InvokeCB(pUART, (UART_EVENT_T) (UART_TX_DONE + op), xfr);
- if (xfr->state == UART_ST_BUSY) {
- xfr->state = UART_ST_DONE;
- }
- return 1;
- }
- return 0;
+ _UART_InvokeCB(pUART, (UART_EVENT_T) (UART_TX_DONE + op), xfr);
+ if (xfr->state == UART_ST_BUSY)
+ {
+ xfr->state = UART_ST_DONE;
+ }
+ return 1;
+ }
+ return 0;
}
/* STOP Receive under progress */
static void _UART_StopRx(UART_HANDLE_T hUART)
{
- UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
- UART_DATA_T *rx = &pUART->xfer[1];
- volatile uint16_t *idx = (volatile uint16_t *) &rx->offset;
+ UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
+ UART_DATA_T *rx = &pUART->xfer[1];
+ volatile uint16_t *idx = (volatile uint16_t *) &rx->offset;
- if (*idx >= rx->count) {
- return;
- }
+ if (*idx >= rx->count)
+ {
+ return;
+ }
- /* Disable further receive interrupts */
- pUART->pREGS->INTENCLR = UART_INT_RXRDY;
- rx->count = *idx;
- _UART_InvokeCB(pUART, UART_RX_DONE, rx);
+ /* Disable further receive interrupts */
+ pUART->pREGS->INTENCLR = UART_INT_RXRDY;
+ rx->count = *idx;
+ _UART_InvokeCB(pUART, UART_RX_DONE, rx);
}
/* EXPROTED API: Returns memory required for UART ROM driver */
uint32_t UART_GetMemSize(void)
{
- return sizeof(UART_DRIVER_T);
+ return sizeof(UART_DRIVER_T);
}
/* EXPORTED API: Calculate UART Baudrate divisors */
ErrorCode_t UART_CalculateBaud(UART_BAUD_T *ub)
{
- if (!ub->mul) {
- _UART_CalcMul(ub);
- }
+ if (!ub->mul)
+ {
+ _UART_CalcMul(ub);
+ }
- return _UART_CalcDiv(ub);
+ return _UART_CalcDiv(ub);
}
/* EXPORTED API: UART Initialization function */
UART_HANDLE_T UART_Init(void *mem, uint32_t base_addr, void *args)
{
- UART_DRIVER_T *pUART;
+ UART_DRIVER_T *pUART;
- /* Check if the memory is word aligned */
- if ((uint32_t) mem & 0x3) {
- return NULL;
- }
+ /* Check if the memory is word aligned */
+ if ((uint32_t) mem & 0x3)
+ {
+ return NULL;
+ }
- /* Assign memory provided by application */
- pUART = (UART_DRIVER_T *) mem;
- memset(pUART, 0, sizeof(UART_DRIVER_T));
+ /* Assign memory provided by application */
+ pUART = (UART_DRIVER_T *) mem;
+ memset(pUART, 0, sizeof(UART_DRIVER_T));
- /* Assign the base address */
- pUART->pREGS = (UART_REGS_T *) base_addr;
- pUART->pUserData = args;
+ /* Assign the base address */
+ pUART->pREGS = (UART_REGS_T *) base_addr;
+ pUART->pUserData = args;
- /* Set default handler for TX and RX */
- pUART->cbTable[UART_CB_DATA] = _UART_HandleTxRx;
- return (UART_HANDLE_T) pUART;
+ /* Set default handler for TX and RX */
+ pUART->cbTable[UART_CB_DATA] = _UART_HandleTxRx;
+ return (UART_HANDLE_T) pUART;
}
/* EXPORTED API: Configure UART parameters */
ErrorCode_t UART_Configure(UART_HANDLE_T hUART, const UART_CFG_T *cfg)
{
- UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
- UART_REGS_T *pREGS = pUART->pREGS;
+ UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
+ UART_REGS_T *pREGS = pUART->pREGS;
- if (((cfg->cfg & UART_PAR_MASK) == (1 << 4)) ||
- ( (cfg->cfg & UART_DATA_MASK) == (3 << 2)) ) {
- return ERR_UART_PARAM;
- }
+ if (((cfg->cfg & UART_PAR_MASK) == (1 << 4)) ||
+ ( (cfg->cfg & UART_DATA_MASK) == (3 << 2)) )
+ {
+ return ERR_UART_PARAM;
+ }
- /* Enable parity error when parity is enabled */
- if ((cfg->cfg & UART_PAR_MASK) >> 4) {
- pREGS->INTENSET = UART_INT_PARERR;
- }
+ /* Enable parity error when parity is enabled */
+ if ((cfg->cfg & UART_PAR_MASK) >> 4)
+ {
+ pREGS->INTENSET = UART_INT_PARERR;
+ }
- if (((int32_t) cfg->div <= 0) || ((int32_t) cfg->ovr <= 0)) {
- return ERR_UART_PARAM;
- }
+ if (((int32_t) cfg->div <= 0) || ((int32_t) cfg->ovr <= 0))
+ {
+ return ERR_UART_PARAM;
+ }
- pREGS->OSR = (cfg->ovr - 1) & 0x0F;
- pREGS->BRG = (cfg->div - 1) & 0xFFFF;
- pREGS->CFG = UART_CFG_ENABLE | (cfg->cfg & ~UART_CFG_RES);
+ pREGS->OSR = (cfg->ovr - 1) & 0x0F;
+ pREGS->BRG = (cfg->div - 1) & 0xFFFF;
+ pREGS->CFG = UART_CFG_ENABLE | (cfg->cfg & ~UART_CFG_RES);
- /* Enabled RX of BREAK event */
- if (cfg->cfg & UART_CFG_BRKRX) {
- pREGS->INTENSET = UART_INT_BREAK;
- }
+ /* Enabled RX of BREAK event */
+ if (cfg->cfg & UART_CFG_BRKRX)
+ {
+ pREGS->INTENSET = UART_INT_BREAK;
+ }
- /* Enable CTS interrupt if requested */
- if (cfg->cfg & UART_CFG_CTSEV) {
- pREGS->INTENSET = UART_INT_CTS;
- }
+ /* Enable CTS interrupt if requested */
+ if (cfg->cfg & UART_CFG_CTSEV)
+ {
+ pREGS->INTENSET = UART_INT_CTS;
+ }
#ifdef UART_IDLE_FIX
- /* REMOVE: if/else block after H/W idle is fixed */
- if (cfg->res > 224) {
- pUART->dly = 3072 * (cfg->res - 224);
- }
- else {
- pUART->dly = cfg->res << 2;
- }
+ /* REMOVE: if/else block after H/W idle is fixed */
+ if (cfg->res > 224)
+ {
+ pUART->dly = 3072 * (cfg->res - 224);
+ }
+ else {
+ pUART->dly = cfg->res << 2;
+ }
#endif
- return LPC_OK;
+ return LPC_OK;
}
/* EXPORTED API: UART setup special operation like BREAK etc. */
void UART_SetControl(UART_HANDLE_T hUART, uint32_t cfg)
{
- uint32_t en, dis;
- UART_REGS_T *pREGS = ((UART_DRIVER_T *) hUART)->pREGS;
+ uint32_t en, dis;
+ UART_REGS_T *pREGS = ((UART_DRIVER_T *) hUART)->pREGS;
- /* Get list of enabled and disabled options */
- en = ((cfg >> 16) & (cfg & 0xFFFF)) << 1;
- dis = ((cfg >> 16) & ~(cfg & 0xFFFF)) << 1;
+ /* Get list of enabled and disabled options */
+ en = ((cfg >> 16) & (cfg & 0xFFFF)) << 1;
+ dis = ((cfg >> 16) & ~(cfg & 0xFFFF)) << 1;
- /* See if it is RX Stop request */
- if (cfg & UART_RX_STOP) {
- _UART_StopRx(hUART);
- }
+ /* See if it is RX Stop request */
+ if (cfg & UART_RX_STOP)
+ {
+ _UART_StopRx(hUART);
+ }
- /* See if any IDLEs are enabled */
- if (cfg & (UART_IDLE_MASK << 16)) {
- pREGS->INTENSET = (en >> 1) & UART_IDLE_MASK;
- pREGS->INTENCLR = (dis >> 1) & UART_IDLE_MASK;
- }
+ /* See if any IDLEs are enabled */
+ if (cfg & (UART_IDLE_MASK << 16))
+ {
+ pREGS->INTENSET = (en >> 1) & UART_IDLE_MASK;
+ pREGS->INTENCLR = (dis >> 1) & UART_IDLE_MASK;
+ }
- /* See if it is a request BREAK after TX */
- if (en & UART_CTL_TXDIS) {
- if (en & UART_CTL_TXBRKEN) {
- pREGS->CTL = (pREGS->CTL & ~UART_CTL_RES) | UART_CTL_TXDIS;
- while (!(pREGS->STAT & UART_INT_TXDIS)) {}
+ /* See if it is a request BREAK after TX */
+ if (en & UART_CTL_TXDIS)
+ {
+ if (en & UART_CTL_TXBRKEN)
+ {
+ pREGS->CTL = (pREGS->CTL & ~UART_CTL_RES) | UART_CTL_TXDIS;
+ while (!(pREGS->STAT & UART_INT_TXDIS))
+ {}
#ifdef UART_IDLE_FIX
- if (1) {
- volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
- while (dly--) {}/* Provide some idling time H/W does not do this */
- }
+ if (1)
+ {
+ volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
+ while (dly--)
+ {}/* Provide some idling time H/W does not do this */
+ }
#endif
- }
- else {
- pREGS->INTENSET = UART_INT_TXDIS;
- }
- }
+ }
+ else {
+ pREGS->INTENSET = UART_INT_TXDIS;
+ }
+ }
- /* See if we are releasing break and resume TX operation */
- if ((dis & UART_CTL_TXDIS) && (dis & UART_CTL_TXBRKEN)) {
- pREGS->CTL = pREGS->CTL & ~(UART_CTL_RES | UART_CTL_TXBRKEN);
+ /* See if we are releasing break and resume TX operation */
+ if ((dis & UART_CTL_TXDIS) && (dis & UART_CTL_TXBRKEN))
+ {
+ pREGS->CTL = pREGS->CTL & ~(UART_CTL_RES | UART_CTL_TXBRKEN);
#ifdef UART_IDLE_FIX
- if (1) {
- volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
- while (dly--) {} /* Provide some idling time H/W does not do this */
- }
+ if (1)
+ {
+ volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
+ while (dly--)
+ {} /* Provide some idling time H/W does not do this */
+ }
#endif
- }
+ }
- /* Check for autobaud and enable autobaud err interrupt */
- if (en & UART_CTL_AUTOBAUD) {
- pREGS->INTENSET = UART_INT_ABAUDERR;
- }
+ /* Check for autobaud and enable autobaud err interrupt */
+ if (en & UART_CTL_AUTOBAUD)
+ {
+ pREGS->INTENSET = UART_INT_ABAUDERR;
+ }
- pREGS->CTL = ((pREGS->CTL | en) & ~dis) & ~UART_CTL_RES;
+ pREGS->CTL = ((pREGS->CTL | en) & ~dis) & ~UART_CTL_RES;
}
/* EXPORTED API: Register a call-back function */
ErrorCode_t UART_RegisterCB(UART_HANDLE_T hUART,
- UART_CBINDEX_T idx,
- void (*cb_func)(UART_HANDLE_T, UART_EVENT_T, void *))
+ UART_CBINDEX_T idx,
+ void (*cb_func)(UART_HANDLE_T, UART_EVENT_T, void *))
{
- if (idx < UART_CB_RESERVED) {
- ((UART_DRIVER_T *) hUART)->cbTable[idx] = cb_func;
- }
- else {
- return ERR_UART_PARAM;
- }
+ if (idx < UART_CB_RESERVED)
+ {
+ ((UART_DRIVER_T *) hUART)->cbTable[idx] = cb_func;
+ }
+ else {
+ return ERR_UART_PARAM;
+ }
- /* Restore internal data handlers when external ones are un-registered */
- if ((idx == UART_CB_DATA) && (cb_func == NULL)) {
- ((UART_DRIVER_T *) hUART)->cbTable[idx] = _UART_HandleTxRx;
- }
+ /* Restore internal data handlers when external ones are un-registered */
+ if ((idx == UART_CB_DATA) && (cb_func == NULL))
+ {
+ ((UART_DRIVER_T *) hUART)->cbTable[idx] = _UART_HandleTxRx;
+ }
- return LPC_OK;
+ return LPC_OK;
}
/* EXPORTED API: UART Event handler */
void UART_Handler(UART_HANDLE_T hUART)
{
- UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
- uint32_t flags = pUART->pREGS->INTENSET & pUART->pREGS->INTSTAT;
+ UART_DRIVER_T *pUART = (UART_DRIVER_T *) hUART;
+ uint32_t flags = pUART->pREGS->INTENSET & pUART->pREGS->INTSTAT;
- if (flags & UART_INT_TXRDY) {
- _UART_HandleXfer(pUART, 0);
- }
+ if (flags & UART_INT_TXRDY)
+ {
+ _UART_HandleXfer(pUART, 0);
+ }
- if (flags & UART_INT_FRMERR) {
- pUART->pREGS->STAT = UART_INT_FRMERR;
- if (pUART->xfer[1].state == UART_ST_BUSY) {
- pUART->xfer[1].state = UART_ST_ERRFRM;
- }
- _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_FRAME);
- }
+ if (flags & UART_INT_FRMERR)
+ {
+ pUART->pREGS->STAT = UART_INT_FRMERR;
+ if (pUART->xfer[1].state == UART_ST_BUSY)
+ {
+ pUART->xfer[1].state = UART_ST_ERRFRM;
+ }
+ _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_FRAME);
+ }
- if (flags & UART_INT_PARERR) {
- pUART->pREGS->STAT = UART_INT_PARERR;
- if (pUART->xfer[1].state == UART_ST_BUSY) {
- pUART->xfer[1].state = UART_ST_ERRPAR;
- }
- _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_PARITY);
- }
+ if (flags & UART_INT_PARERR)
+ {
+ pUART->pREGS->STAT = UART_INT_PARERR;
+ if (pUART->xfer[1].state == UART_ST_BUSY)
+ {
+ pUART->xfer[1].state = UART_ST_ERRPAR;
+ }
+ _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_PARITY);
+ }
- if (flags & UART_INT_ABAUDERR) {
- pUART->pREGS->STAT = UART_INT_ABAUDERR;
- if (pUART->xfer[1].state == UART_ST_BUSY) {
- pUART->xfer[1].state = UART_ST_ERR;
- }
- _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_AUTOBAUD);
- }
+ if (flags & UART_INT_ABAUDERR)
+ {
+ pUART->pREGS->STAT = UART_INT_ABAUDERR;
+ if (pUART->xfer[1].state == UART_ST_BUSY)
+ {
+ pUART->xfer[1].state = UART_ST_ERR;
+ }
+ _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_AUTOBAUD);
+ }
- if (flags & UART_INT_RXNOISE) {
- pUART->pREGS->STAT = UART_INT_RXNOISE;
- if (pUART->xfer[1].state == UART_ST_BUSY) {
- pUART->xfer[1].state = UART_ST_ERRNOISE;
- }
- _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_RXNOISE);
- }
+ if (flags & UART_INT_RXNOISE)
+ {
+ pUART->pREGS->STAT = UART_INT_RXNOISE;
+ if (pUART->xfer[1].state == UART_ST_BUSY)
+ {
+ pUART->xfer[1].state = UART_ST_ERRNOISE;
+ }
+ _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_RXNOISE);
+ }
- if (flags & UART_INT_OVR) {
- pUART->pREGS->STAT = UART_INT_OVR;
- if (pUART->xfer[1].state == UART_ST_BUSY) {
- pUART->xfer[1].state = UART_ST_ERROVR;
- }
- _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_OVERRUN);
- }
+ if (flags & UART_INT_OVR)
+ {
+ pUART->pREGS->STAT = UART_INT_OVR;
+ if (pUART->xfer[1].state == UART_ST_BUSY)
+ {
+ pUART->xfer[1].state = UART_ST_ERROVR;
+ }
+ _UART_InvokeCB(pUART, UART_EV_ERROR, (void *) UART_ERROR_OVERRUN);
+ }
- if (flags & UART_INT_RXRDY) {
- _UART_HandleXfer(pUART, 1);
+ if (flags & UART_INT_RXRDY)
+ {
+ _UART_HandleXfer(pUART, 1);
#ifdef UART_IDLE_FIX
- if (1) {
- volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
- while ((pUART->pREGS->STAT & UART_STAT_RXIDLE) && dly--) {}
- }
+ if (1)
+ {
+ volatile uint32_t dly = ((UART_DRIVER_T *) hUART)->dly;
+ while ((pUART->pREGS->STAT & UART_STAT_RXIDLE) && dly--)
+ {}
+ }
#else
- while (pUART->pREGS->STAT & UART_STAT_RXIDLE) {}
+ while (pUART->pREGS->STAT & UART_STAT_RXIDLE)
+ {}
#endif
- _UART_InvokeCB(pUART, (UART_EVENT_T) (UART_RX_INPROG + ((pUART->pREGS->STAT >> 1) & 1)), &pUART->xfer[1]);
- }
+ _UART_InvokeCB(pUART, (UART_EVENT_T) (UART_RX_INPROG + ((pUART->pREGS->STAT >> 1) & 1)), &pUART->xfer[1]);
+ }
- if (flags & UART_INT_TXIDLE) {
- _UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXIDLE);
- }
+ if (flags & UART_INT_TXIDLE)
+ {
+ _UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXIDLE);
+ }
- if (flags & UART_INT_TXDIS) {
- pUART->pREGS->INTENCLR = UART_INT_TXDIS;/* Disable interrupt */
- _UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXPAUSED);
- }
+ if (flags & UART_INT_TXDIS)
+ {
+ pUART->pREGS->INTENCLR = UART_INT_TXDIS;/* Disable interrupt */
+ _UART_InvokeCB(pUART, UART_EV_EVENT, (void *) UART_EVENT_TXPAUSED);
+ }
- if (flags & UART_INT_CTS) {
- pUART->pREGS->STAT = UART_INT_CTS;
- _UART_InvokeCB(pUART, UART_EV_EVENT,
- (void *) ((pUART->pREGS->STAT & UART_STAT_CTS) ? UART_EVENT_CTSHI : UART_EVENT_CTSLO));
- }
+ if (flags & UART_INT_CTS)
+ {
+ pUART->pREGS->STAT = UART_INT_CTS;
+ _UART_InvokeCB(pUART, UART_EV_EVENT,
+ (void *) ((pUART->pREGS->STAT & UART_STAT_CTS) ? UART_EVENT_CTSHI : UART_EVENT_CTSLO));
+ }
- if (flags & UART_INT_BREAK) {
- pUART->pREGS->STAT = UART_INT_BREAK | UART_INT_FRMERR;
- _UART_InvokeCB(pUART, UART_EV_EVENT,
- (void *) ((pUART->pREGS->STAT & UART_STAT_BREAK) ? UART_EVENT_BREAK : UART_EVENT_NOBREAK));
- }
+ if (flags & UART_INT_BREAK)
+ {
+ pUART->pREGS->STAT = UART_INT_BREAK | UART_INT_FRMERR;
+ _UART_InvokeCB(pUART, UART_EV_EVENT,
+ (void *) ((pUART->pREGS->STAT & UART_STAT_BREAK) ? UART_EVENT_BREAK : UART_EVENT_NOBREAK));
+ }
- if (flags & UART_INT_START) {
- pUART->pREGS->STAT = UART_INT_START;
- _UART_InvokeCB(pUART, UART_RX_START, &pUART->xfer[1]);
- }
+ if (flags & UART_INT_START)
+ {
+ pUART->pREGS->STAT = UART_INT_START;
+ _UART_InvokeCB(pUART, UART_RX_START, &pUART->xfer[1]);
+ }
}
/* EXPORTED API: UART Transmit API */
ErrorCode_t UART_Tx(UART_HANDLE_T hUART, const void *buff, uint16_t len)
{
- return _UART_Xfer((UART_DRIVER_T *) hUART, (void *) buff, len, 0);
+ return _UART_Xfer((UART_DRIVER_T *) hUART, (void *) buff, len, 0);
}
/* EXPORTED API: UART Receive API */
ErrorCode_t UART_Rx(UART_HANDLE_T hUART, void *buff, uint16_t len)
{
- return _UART_Xfer((UART_DRIVER_T *) hUART, buff, len, 1);
+ return _UART_Xfer((UART_DRIVER_T *) hUART, buff, len, 1);
}
/* EXPORTED API: Flush the TX buffer */
void UART_WaitTX(UART_HANDLE_T hUART)
{
- while (!_UART_HandleXfer(hUART, 0)) {}
+ while (!_UART_HandleXfer(hUART, 0))
+ {}
}
/* EXPORTED API: Fetch the data from UART into RX buffer */
void UART_WaitRX(UART_HANDLE_T hUART)
{
- UART_REGS_T *pREGS = ((UART_DRIVER_T *) hUART)->pREGS;
- /* See if the data needs to be discarded */
- if (_UART_HandleXfer(hUART, 1) == 2) {
- volatile uint32_t dummy;
- while ((pREGS->STAT & UART_INT_RXRDY) || !(pREGS->STAT & UART_STAT_RXIDLE)) {
- dummy = pREGS->RXDAT;
- }
- }
- while (!_UART_HandleXfer(hUART, 1)) {}
+ UART_REGS_T *pREGS = ((UART_DRIVER_T *) hUART)->pREGS;
+ /* See if the data needs to be discarded */
+ if (_UART_HandleXfer(hUART, 1) == 2)
+ {
+ volatile uint32_t dummy;
+ while ((pREGS->STAT & UART_INT_RXRDY) || !(pREGS->STAT & UART_STAT_RXIDLE))
+ {
+ dummy = pREGS->RXDAT;
+ (void)dummy;
+ }
+ }
+ while (!_UART_HandleXfer(hUART, 1))
+ {}
}
/* EXPORTED API: Function to Get the firmware Version */
uint32_t UART_GetDriverVersion(void)
{
- return UART_DRIVER_VERSION;
+ return UART_DRIVER_VERSION;
}
/**
- * @brief Table of the addresses of all the UART ROM APIs
- * @note This table of function pointers is the API interface.
+ * @brief Table of the addresses of all the UART ROM APIs
+ * @note This table of function pointers is the API interface.
*/
const ROM_UART_API_T uartrom_api = {
- UART_GetMemSize,
- UART_CalculateBaud,
- UART_Init,
- UART_Configure,
- UART_SetControl,
- UART_RegisterCB,
- UART_Handler,
- UART_Tx,
- UART_Rx,
- UART_WaitTX,
- UART_WaitRX,
- UART_GetDriverVersion,
+ UART_GetMemSize,
+ UART_CalculateBaud,
+ UART_Init,
+ UART_Configure,
+ UART_SetControl,
+ UART_RegisterCB,
+ UART_Handler,
+ UART_Tx,
+ UART_Rx,
+ UART_WaitTX,
+ UART_WaitRX,
+ UART_GetDriverVersion,
};
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c
index d99fd85916..242bed455f 100644
--- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/pll_5410x.c
@@ -40,44 +40,44 @@
#define MVALMAX (0x8000)
/* SYS PLL related bit fields */
-#define SYS_PLL_SELR(d) (((d) & 0xf) << 0) /*!< Bandwidth select R value */
-#define SYS_PLL_SELI(d) (((d) & 0x3f) << 4) /*!< Bandwidth select I value */
-#define SYS_PLL_SELP(d) (((d) & 0x1f) << 10) /*!< Bandwidth select P value */
-#define SYS_PLL_BYPASS (1 << 15) /*!< Enable PLL bypass */
-#define SYS_PLL_BYPASSCCODIV2 (1 << 16) /*!< Enable bypass of extra divider by 2 */
-#define SYS_PLL_UPLIMOFF (1 << 17) /*!< Enable spread spectrum/fractional mode */
-#define SYS_PLL_BANDSEL (1 << 18) /*!< Enable MDEC control */
-#define SYS_PLL_DIRECTI (1 << 19) /*!< PLL0 direct input enable */
-#define SYS_PLL_DIRECTO (1 << 20) /*!< PLL0 direct output enable */
+#define SYS_PLL_SELR(d) (((d) & 0xf) << 0) /*!< Bandwidth select R value */
+#define SYS_PLL_SELI(d) (((d) & 0x3f) << 4) /*!< Bandwidth select I value */
+#define SYS_PLL_SELP(d) (((d) & 0x1f) << 10) /*!< Bandwidth select P value */
+#define SYS_PLL_BYPASS (1 << 15) /*!< Enable PLL bypass */
+#define SYS_PLL_BYPASSCCODIV2 (1 << 16) /*!< Enable bypass of extra divider by 2 */
+#define SYS_PLL_UPLIMOFF (1 << 17) /*!< Enable spread spectrum/fractional mode */
+#define SYS_PLL_BANDSEL (1 << 18) /*!< Enable MDEC control */
+#define SYS_PLL_DIRECTI (1 << 19) /*!< PLL0 direct input enable */
+#define SYS_PLL_DIRECTO (1 << 20) /*!< PLL0 direct output enable */
-// #define FRAC_BITS_SELI (8) // For retaining fractions in divisions
-#define PLL_SSCG0_MDEC_VAL_P (0) // MDEC is in bits 16 downto 0
-#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) // NDEC is in bits 9 downto 0
-#define PLL_NDEC_VAL_P (0) // NDEC is in bits 9:0
+/* #define FRAC_BITS_SELI (8) // For retaining fractions in divisions*/
+#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0*/
+#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0*/
+#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0*/
#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
-#define PLL_PDEC_VAL_P (0) // PDEC is in bits 6:0
+#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0*/
#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
#define PLL_MIN_CCO_FREQ_MHZ (75000000)
#define PLL_MAX_CCO_FREQ_MHZ (150000000)
-#define PLL_LOWER_IN_LIMIT (4000) /*!< Minimum PLL input rate */
+#define PLL_LOWER_IN_LIMIT (4000) /*!< Minimum PLL input rate */
#define PLL_MIN_IN_SSMODE (2000000)
#define PLL_MAX_IN_SSMODE (4000000)
-// Middle of the range values for spread-spectrum
+/* Middle of the range values for spread-spectrum*/
#define PLL_SSCG_MF_FREQ_VALUE 4
#define PLL_SSCG_MC_COMP_VALUE 2
#define PLL_SSCG_MR_DEPTH_VALUE 4
#define PLL_SSCG_DITHER_VALUE 0
-// pll SYSPLLCTRL Bits
+/* pll SYSPLLCTRL Bits*/
#define SYSCON_SYSPLLCTRL_SELR_P 0
#define SYSCON_SYSPLLCTRL_SELR_M (0xFUL << SYSCON_SYSPLLCTRL_SELR_P)
#define SYSCON_SYSPLLCTRL_SELI_P 4
#define SYSCON_SYSPLLCTRL_SELI_M (0x3FUL << SYSCON_SYSPLLCTRL_SELI_P)
#define SYSCON_SYSPLLCTRL_SELP_P 10
#define SYSCON_SYSPLLCTRL_SELP_M (0x1FUL << SYSCON_SYSPLLCTRL_SELP_P)
-#define SYSCON_SYSPLLCTRL_BYPASS_P 15 // sys_pll150_ctrl
+#define SYSCON_SYSPLLCTRL_BYPASS_P 15 /* sys_pll150_ctrl*/
#define SYSCON_SYSPLLCTRL_BYPASS (1UL << SYSCON_SYSPLLCTRL_BYPASS_P)
#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P 16
#define SYSCON_SYSPLLCTRL_BYPASS_FBDIV2 (1UL << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P)
@@ -93,7 +93,7 @@
#define SYSCON_SYSPLLSTAT_LOCK_P 0
#define SYSCON_SYSPLLSTAT_LOCK (1UL << SYSCON_SYSPLLSTAT_LOCK_P)
-#define PLL_CTRL_BYPASS_P 15 // sys_pll150_ctrl
+#define PLL_CTRL_BYPASS_P 15 /* sys_pll150_ctrl*/
#define PLL_CTRL_BYPASS_FBDIV2_P 16
#define PLL_CTRL_UPLIMOFF_P 17
#define PLL_CTRL_BANDSEL_SSCGREG_N_P 18
@@ -107,14 +107,14 @@
#define PLL_CTRL_BANDSEL_SSCGREG_N (1 << PLL_CTRL_BANDSEL_SSCGREG_N_P)
#define PLL_CTRL_BYPASS_FBDIV2 (1 << PLL_CTRL_BYPASS_FBDIV2_P)
-// SSCG control[0]
-// #define PLL_SSCG0_MDEC_VAL_P 0 // MDEC is in bits 16 downto 0
+/* SSCG control[0]*/
+/* #define PLL_SSCG0_MDEC_VAL_P 0 // MDEC is in bits 16 downto 0*/
#define PLL_SSCG0_MREQ_P 17
#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18
#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P)
#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P)
-// SSCG control[1]
+/* SSCG control[1]*/
#define PLL_SSCG1_MD_REQ_P 19
#define PLL_SSCG1_MOD_PD_SSCGCLK_N_P 28
#define PLL_SSCG1_DITHER_P 29
@@ -122,24 +122,24 @@
#define PLL_SSCG1_DITHER (1 << PLL_SSCG1_DITHER_P)
#define PLL_SSCG1_MD_REQ (1 << PLL_SSCG1_MD_REQ_P)
-// PLL NDEC reg
+/* PLL NDEC reg*/
#define PLL_NDEC_VAL_SET(value) (((unsigned long) (value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
#define PLL_NDEC_NREQ_P 10
#define PLL_NDEC_NREQ (1 << PLL_NDEC_NREQ_P)
-// PLL PDEC reg
+/* PLL PDEC reg*/
#define PLL_PDEC_VAL_SET(value) (((unsigned long) (value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
#define PLL_PDEC_PREQ_P 7
#define PLL_PDEC_PREQ (1 << PLL_PDEC_PREQ_P)
-// SSCG control[0]
+/* SSCG control[0]*/
#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long) (value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M)
#define PLL_SSCG0_MREQ_P 17
#define PLL_SSCG0_MREQ (1 << PLL_SSCG0_MREQ_P)
#define PLL_SSCG0_SEL_EXT_SSCG_N_P 18
#define PLL_SSCG0_SEL_EXT_SSCG_N (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P)
-// SSCG control[1]
+/* SSCG control[1]*/
#define PLL_SSCG1_MD_FRACT_P 0
#define PLL_SSCG1_MD_INT_P 11
#define PLL_SSCG1_MF_P 20
@@ -153,17 +153,20 @@
#define PLL_SSCG1_MR_M (0x7UL << PLL_SSCG1_MR_P)
#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long) (value) << \
- PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M)
+ PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M)
#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long) (value) << \
- PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M)
-// #define PLL_SSCG1_MF_SET(value) (((unsigned long) (value) << \
-// // PLL_SSCG1_MF_P) & PLL_SSCG1_MF_M)
-// #define PLL_SSCG1_MC_SET(value) (((unsigned long) (value) << \
-// // PLL_SSCG1_MC_P) & PLL_SSCG1_MC_M)
-// #define PLL_SSCG1_MR_SET(value) (((unsigned long) (value) << \
-// // PLL_SSCG1_MR_P) & PLL_SSCG1_MR_M)
+ PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M)
+/*
+#define PLL_SSCG1_MF_SET(value) (((unsigned long) (value) << \
+ PLL_SSCG1_MF_P) & PLL_SSCG1_MF_M)
+#define PLL_SSCG1_MC_SET(value) (((unsigned long) (value) << \
+ PLL_SSCG1_MC_P) & PLL_SSCG1_MC_M)
+#define PLL_SSCG1_MR_SET(value) (((unsigned long) (value) << \
+ PLL_SSCG1_MR_P) & PLL_SSCG1_MR_M)
+*/
+
+/* Middle of the range values for spread-spectrum*/
-// Middle of the range values for spread-spectrum
#define PLL0_SSCG_MF_FREQ_VALUE 4
#define PLL0_SSCG_MC_COMP_VALUE 2
#define PLL0_SSCG_MR_DEPTH_VALUE 4
@@ -186,469 +189,514 @@ static uint32_t curPllRate;
/* Find encoded NDEC value for raw N value, max N = NVALMAX */
static uint32_t pllEncodeN(uint32_t N)
{
- uint32_t x, i;
+ uint32_t x, i;
- /* Find NDec */
- switch (N) {
- case 0:
- x = 0xFFF;
- break;
+ /* Find NDec */
+ switch (N)
+ {
+ case 0:
+ x = 0xFFF;
+ break;
- case 1:
- x = 0x302;
- break;
+ case 1:
+ x = 0x302;
+ break;
- case 2:
- x = 0x202;
- break;
+ case 2:
+ x = 0x202;
+ break;
- default:
- x = 0x080;
- for (i = N; i <= NVALMAX; i++) {
- x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
- }
- break;
- }
+ default:
+ x = 0x080;
+ for (i = N; i <= NVALMAX; i++)
+ {
+ x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+ }
+ break;
+ }
- return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
+ return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
}
/* Find decoded N value for raw NDEC value */
static uint32_t pllDecodeN(uint32_t NDEC)
{
- uint32_t n, x, i;
+ uint32_t n, x, i;
- /* Find NDec */
- switch (NDEC) {
- case 0xFFF:
- n = 0;
- break;
+ /* Find NDec */
+ switch (NDEC)
+ {
+ case 0xFFF:
+ n = 0;
+ break;
- case 0x302:
- n = 1;
- break;
+ case 0x302:
+ n = 1;
+ break;
- case 0x202:
- n = 2;
- break;
+ case 0x202:
+ n = 2;
+ break;
- default:
- x = 0x080;
- n = 0xFFFFFFFF;
- for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) {
- x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
- if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) {
- /* Decoded value of NDEC */
- n = i;
- }
- }
- break;
- }
+ default:
+ x = 0x080;
+ n = 0xFFFFFFFF;
+ for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--)
+ {
+ x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+ if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+ {
+ /* Decoded value of NDEC */
+ n = i;
+ }
+ }
+ break;
+ }
- return n;
+ return n;
}
/* Find encoded PDEC value for raw P value, max P = PVALMAX */
static uint32_t pllEncodeP(uint32_t P)
{
- uint32_t x, i;
+ uint32_t x, i;
- /* Find PDec */
- switch (P) {
- case 0:
- x = 0xFF;
- break;
+ /* Find PDec */
+ switch (P)
+ {
+ case 0:
+ x = 0xFF;
+ break;
- case 1:
- x = 0x62;
- break;
+ case 1:
+ x = 0x62;
+ break;
- case 2:
- x = 0x42;
- break;
+ case 2:
+ x = 0x42;
+ break;
- default:
- x = 0x10;
- for (i = P; i <= PVALMAX; i++) {
- x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
- }
- break;
- }
+ default:
+ x = 0x10;
+ for (i = P; i <= PVALMAX; i++)
+ {
+ x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
+ }
+ break;
+ }
- return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
+ return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
}
/* Find decoded P value for raw PDEC value */
static uint32_t pllDecodeP(uint32_t PDEC)
{
- uint32_t p, x, i;
+ uint32_t p, x, i;
- /* Find PDec */
- switch (PDEC) {
- case 0xFF:
- p = 0;
- break;
+ /* Find PDec */
+ switch (PDEC)
+ {
+ case 0xFF:
+ p = 0;
+ break;
- case 0x62:
- p = 1;
- break;
+ case 0x62:
+ p = 1;
+ break;
- case 0x42:
- p = 2;
- break;
+ case 0x42:
+ p = 2;
+ break;
- default:
- x = 0x10;
- p = 0xFFFFFFFF;
- for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) {
- x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
- if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) {
- /* Decoded value of PDEC */
- p = i;
- }
- }
- break;
- }
+ default:
+ x = 0x10;
+ p = 0xFFFFFFFF;
+ for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--)
+ {
+ x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
+ if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+ {
+ /* Decoded value of PDEC */
+ p = i;
+ }
+ }
+ break;
+ }
- return p;
+ return p;
}
/* Find encoded MDEC value for raw M value, max M = MVALMAX */
static uint32_t pllEncodeM(uint32_t M)
{
- uint32_t i, x;
+ uint32_t i, x;
- /* Find MDec */
- switch (M) {
- case 0:
- x = 0xFFFFF;
- break;
+ /* Find MDec */
+ switch (M)
+ {
+ case 0:
+ x = 0xFFFFF;
+ break;
- case 1:
- x = 0x18003;
- break;
+ case 1:
+ x = 0x18003;
+ break;
- case 2:
- x = 0x10003;
- break;
+ case 2:
+ x = 0x10003;
+ break;
- default:
- x = 0x04000;
- for (i = M; i <= MVALMAX; i++) {
- x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
- }
- break;
- }
+ default:
+ x = 0x04000;
+ for (i = M; i <= MVALMAX; i++)
+ {
+ x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+ }
+ break;
+ }
- return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P);
+ return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P);
}
/* Find decoded M value for raw MDEC value */
static uint32_t pllDecodeM(uint32_t MDEC)
{
- uint32_t m, i, x;
+ uint32_t m, i, x;
- /* Find MDec */
- switch (MDEC) {
- case 0xFFFFF:
- m = 0;
- break;
+ /* Find MDec */
+ switch (MDEC)
+ {
+ case 0xFFFFF:
+ m = 0;
+ break;
- case 0x18003:
- m = 1;
- break;
+ case 0x18003:
+ m = 1;
+ break;
- case 0x10003:
- m = 2;
- break;
+ case 0x10003:
+ m = 2;
+ break;
- default:
- x = 0x04000;
- m = 0xFFFFFFFF;
- for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) {
- x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
- if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) {
- /* Decoded value of MDEC */
- m = i;
- }
- }
- break;
- }
+ default:
+ x = 0x04000;
+ m = 0xFFFFFFFF;
+ for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--)
+ {
+ x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+ if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
+ {
+ /* Decoded value of MDEC */
+ m = i;
+ }
+ }
+ break;
+ }
- return m;
+ return m;
}
/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
{
- /* Bypass divider? */
- if (bypassFBDIV2) {
- M = M / 2;
- }
+ /* Bypass divider? */
+ if (bypassFBDIV2)
+ {
+ M = M / 2;
+ }
- /* bandwidth: compute selP from Multiplier */
- if (M < 60) {
- *pSelP = (M >> 1) + 1;
- }
- else {
- *pSelP = PVALMAX - 1;
- }
+ /* bandwidth: compute selP from Multiplier */
+ if (M < 60)
+ {
+ *pSelP = (M >> 1) + 1;
+ }
+ else {
+ *pSelP = PVALMAX - 1;
+ }
- /* bandwidth: compute selI from Multiplier */
- if (M > 16384) {
- *pSelI = 1;
- }
- else if (M > 8192) {
- *pSelI = 2;
- }
- else if (M > 2048) {
- *pSelI = 4;
- }
- else if (M >= 501) {
- *pSelI = 8;
- }
- else if (M >= 60) {
- *pSelI = 4 * (1024 / (M + 9));
- }
- else {
- *pSelI = (M & 0x3C) + 4;
- }
+ /* bandwidth: compute selI from Multiplier */
+ if (M > 16384)
+ {
+ *pSelI = 1;
+ }
+ else if (M > 8192)
+ {
+ *pSelI = 2;
+ }
+ else if (M > 2048)
+ {
+ *pSelI = 4;
+ }
+ else if (M >= 501)
+ {
+ *pSelI = 8;
+ }
+ else if (M >= 60)
+ {
+ *pSelI = 4 * (1024 / (M + 9));
+ }
+ else {
+ *pSelI = (M & 0x3C) + 4;
+ }
- if (*pSelI > (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P)) {
- *pSelI = (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P);
- }
+ if (*pSelI > (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P))
+ {
+ *pSelI = (SYSCON_SYSPLLCTRL_SELI_M >> SYSCON_SYSPLLCTRL_SELI_P);
+ }
- *pSelR = 0;
+ *pSelR = 0;
}
/* Get predivider (N) from PLL NDEC setting */
uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
{
- uint32_t preDiv = 1;
+ uint32_t preDiv = 1;
- /* Direct input is not used? */
- if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI) == 0) {
- /* Decode NDEC value to get (N) pre divider */
- preDiv = pllDecodeN(nDecReg & 0x3FF);
- if (preDiv == 0) {
- preDiv = 1;
- }
- }
+ /* Direct input is not used? */
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI) == 0)
+ {
+ /* Decode NDEC value to get (N) pre divider */
+ preDiv = pllDecodeN(nDecReg & 0x3FF);
+ if (preDiv == 0)
+ {
+ preDiv = 1;
+ }
+ }
- /* Adjusted by 1, directi is used to bypass */
- return preDiv;
+ /* Adjusted by 1, directi is used to bypass */
+ return preDiv;
}
/* Get postdivider (P) from PLL PDEC setting */
uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
{
- uint32_t postDiv = 1;
+ uint32_t postDiv = 1;
- /* Direct input is not used? */
- if ((ctrlReg & SYS_PLL_DIRECTO) == 0) {
- /* Decode PDEC value to get (P) post divider */
- postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
- if (postDiv == 0) {
- postDiv = 2;
- }
- }
+ /* Direct input is not used? */
+ if ((ctrlReg & SYS_PLL_DIRECTO) == 0)
+ {
+ /* Decode PDEC value to get (P) post divider */
+ postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
+ if (postDiv == 0)
+ {
+ postDiv = 2;
+ }
+ }
- /* Adjusted by 1, directo is used to bypass */
- return postDiv;
+ /* Adjusted by 1, directo is used to bypass */
+ return postDiv;
}
/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
{
- uint32_t mMult = 1;
+ uint32_t mMult = 1;
- /* Decode MDEC value to get (M) multiplier */
- mMult = pllDecodeM(mDecReg & 0x1FFFF);
+ /* Decode MDEC value to get (M) multiplier */
+ mMult = pllDecodeM(mDecReg & 0x1FFFF);
- /* Extra divided by 2 needed? */
- if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASS_FBDIV2) == 0) {
- mMult = mMult >> 1;
- }
+ /* Extra divided by 2 needed? */
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASS_FBDIV2) == 0)
+ {
+ mMult = mMult >> 1;
+ }
- if (mMult == 0) {
- mMult = 1;
- }
+ if (mMult == 0)
+ {
+ mMult = 1;
+ }
- return mMult;
+ return mMult;
}
static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
{
- uint32_t tmp;
+ uint32_t tmp;
- while (n != 0) {
- tmp = n;
- n = m % n;
- m = tmp;
- }
+ while (n != 0)
+ {
+ tmp = n;
+ n = m % n;
+ m = tmp;
+ }
- return m;
+ return m;
}
/* Set PLL output based on desired output rate */
static PLL_ERROR_T Chip_Clock_GetPllConfig(uint32_t finHz, uint32_t foutHz, PLL_SETUP_T *pSetup,
- bool useFeedbackDiv2, bool useSS)
+ bool useFeedbackDiv2, bool useSS)
{
- uint32_t nDivOutHz, fccoHz, multFccoDiv;
- uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider;
- uint32_t pllDirectInput, pllDirectOutput;
- uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff;
+ uint32_t nDivOutHz, fccoHz, multFccoDiv;
+ uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider;
+ uint32_t pllDirectInput, pllDirectOutput;
+ uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff;
- /* Baseline parameters (no input or output dividers) */
- pllPreDivider = 1; /* 1 implies pre-divider will be disabled */
- pllPostDivider = 0; /* 0 implies post-divider will be disabled */
- pllDirectOutput = 1;
- if (useFeedbackDiv2) {
- /* Using feedback divider for M, so disable bypass */
- pllBypassFBDIV2 = 0;
- }
- else {
- pllBypassFBDIV2 = 1;
- }
- multFccoDiv = (2 - pllBypassFBDIV2);
+ /* Baseline parameters (no input or output dividers) */
+ pllPreDivider = 1; /* 1 implies pre-divider will be disabled */
+ pllPostDivider = 0; /* 0 implies post-divider will be disabled */
+ pllDirectOutput = 1;
+ if (useFeedbackDiv2)
+ {
+ /* Using feedback divider for M, so disable bypass */
+ pllBypassFBDIV2 = 0;
+ }
+ else {
+ pllBypassFBDIV2 = 1;
+ }
+ multFccoDiv = (2 - pllBypassFBDIV2);
- /* Verify output rate parameter */
- if (foutHz > PLL_MAX_CCO_FREQ_MHZ) {
- /* Maximum PLL output with post divider=1 cannot go above this frequency */
- return PLL_ERROR_OUTPUT_TOO_HIGH;
- }
- if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1))) {
- /* Minmum PLL output with maximum post divider cannot go below this frequency */
- return PLL_ERROR_OUTPUT_TOO_LOW;
- }
+ /* Verify output rate parameter */
+ if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
+ {
+ /* Maximum PLL output with post divider=1 cannot go above this frequency */
+ return PLL_ERROR_OUTPUT_TOO_HIGH;
+ }
+ if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1)))
+ {
+ /* Minmum PLL output with maximum post divider cannot go below this frequency */
+ return PLL_ERROR_OUTPUT_TOO_LOW;
+ }
- /* If using SS mode, input clock needs to be between 2MHz and 4MHz */
- if (useSS) {
- /* Verify input rate parameter */
- if (finHz < PLL_MIN_IN_SSMODE) {
- /* Input clock into the PLL cannot be lower than this */
- return PLL_ERROR_INPUT_TOO_LOW;
- }
+ /* If using SS mode, input clock needs to be between 2MHz and 4MHz */
+ if (useSS)
+ {
+ /* Verify input rate parameter */
+ if (finHz < PLL_MIN_IN_SSMODE)
+ {
+ /* Input clock into the PLL cannot be lower than this */
+ return PLL_ERROR_INPUT_TOO_LOW;
+ }
- /* PLL input in SS mode must be under 4MHz */
- pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2);
- if (pllPreDivider > NVALMAX) {
- return PLL_ERROR_INPUT_TOO_HIGH;
- }
- }
- else {
- /* Verify input rate parameter */
- if (finHz < PLL_LOWER_IN_LIMIT) {
- /* Input clock into the PLL cannot be lower than this */
- return PLL_ERROR_INPUT_TOO_LOW;
- }
- }
+ /* PLL input in SS mode must be under 4MHz */
+ pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2);
+ if (pllPreDivider > NVALMAX)
+ {
+ return PLL_ERROR_INPUT_TOO_HIGH;
+ }
+ }
+ else {
+ /* Verify input rate parameter */
+ if (finHz < PLL_LOWER_IN_LIMIT)
+ {
+ /* Input clock into the PLL cannot be lower than this */
+ return PLL_ERROR_INPUT_TOO_LOW;
+ }
+ }
- /* Find the optimal CCO frequency for the output and input that
- will keep it inside the PLL CCO range. This may require
- tweaking the post-divider for the PLL. */
- fccoHz = foutHz;
- while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) {
- /* CCO output is less than minimum CCO range, so the CCO output
- needs to be bumped up and the post-divider is used to bring
- the PLL output back down. */
- pllPostDivider++;
- if (pllPostDivider > PVALMAX) {
- return PLL_ERROR_OUTSIDE_INTLIMIT;
- }
+ /* Find the optimal CCO frequency for the output and input that
+ will keep it inside the PLL CCO range. This may require
+ tweaking the post-divider for the PLL. */
+ fccoHz = foutHz;
+ while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
+ {
+ /* CCO output is less than minimum CCO range, so the CCO output
+ needs to be bumped up and the post-divider is used to bring
+ the PLL output back down. */
+ pllPostDivider++;
+ if (pllPostDivider > PVALMAX)
+ {
+ return PLL_ERROR_OUTSIDE_INTLIMIT;
+ }
- /* Target CCO goes up, PLL output goes down */
- fccoHz = foutHz * (pllPostDivider * 2);
- pllDirectOutput = 0;
- }
+ /* Target CCO goes up, PLL output goes down */
+ fccoHz = foutHz * (pllPostDivider * 2);
+ pllDirectOutput = 0;
+ }
- /* Determine if a pre-divider is needed to get the best frequency */
- if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) {
- uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
+ /* Determine if a pre-divider is needed to get the best frequency */
+ if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false))
+ {
+ uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
- if (a > 20000) {
- a = (multFccoDiv * finHz) / a;
- if ((a != 0) && (a < PLL_MAX_N_DIV)) {
- pllPreDivider = a;
- }
- }
- }
+ if (a > 20000)
+ {
+ a = (multFccoDiv * finHz) / a;
+ if ((a != 0) && (a < PLL_MAX_N_DIV))
+ {
+ pllPreDivider = a;
+ }
+ }
+ }
- /* Bypass pre-divider hardware if pre-divider is 1 */
- if (pllPreDivider > 1) {
- pllDirectInput = 0;
- }
- else {
- pllDirectInput = 1;
- }
+ /* Bypass pre-divider hardware if pre-divider is 1 */
+ if (pllPreDivider > 1)
+ {
+ pllDirectInput = 0;
+ }
+ else {
+ pllDirectInput = 1;
+ }
- /* Determine PLL multipler */
- nDivOutHz = (finHz / pllPreDivider);
- pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
+ /* Determine PLL multipler */
+ nDivOutHz = (finHz / pllPreDivider);
+ pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
- /* Find optimal values for filter */
- if (useSS == false) {
- /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
- if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2) + 1)) < (fccoHz * 2)) {
- pllMultiplier++;
- }
+ /* Find optimal values for filter */
+ if (useSS == false)
+ {
+ /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
+ if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2) + 1)) < (fccoHz * 2))
+ {
+ pllMultiplier++;
+ }
- /* Setup filtering */
- pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR);
- bandsel = 1;
- uplimoff = 0;
+ /* Setup filtering */
+ pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR);
+ bandsel = 1;
+ uplimoff = 0;
- /* Get encoded value for M (mult) and use manual filter, disable SS mode */
- pSetup->SYSPLLSSCTRL[0] = (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) |
- (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P));
+ /* Get encoded value for M (mult) and use manual filter, disable SS mode */
+ pSetup->SYSPLLSSCTRL[0] = (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) |
+ (1 << PLL_SSCG0_SEL_EXT_SSCG_N_P));
- /* Power down SSC, not used */
- pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MOD_PD_SSCGCLK_N;
- }
- else {
- uint64_t fc;
+ /* Power down SSC, not used */
+ pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MOD_PD_SSCGCLK_N;
+ }
+ else {
+ uint64_t fc;
- /* Filtering will be handled by SSC */
- pllSelR = pllSelI = pllSelP = 0;
- bandsel = 0;
- uplimoff = 1;
+ /* Filtering will be handled by SSC */
+ pllSelR = pllSelI = pllSelP = 0;
+ bandsel = 0;
+ uplimoff = 1;
- /* The PLL multiplier will get very close and slightly under the
- desired target frequency. A small fractional component can be
- added to fine tune the frequency upwards to the target. */
- fc = ((uint64_t) (fccoHz % (multFccoDiv * nDivOutHz)) << 11) / (multFccoDiv * nDivOutHz);
+ /* The PLL multiplier will get very close and slightly under the
+ desired target frequency. A small fractional component can be
+ added to fine tune the frequency upwards to the target. */
+ fc = ((uint64_t) (fccoHz % (multFccoDiv * nDivOutHz)) << 11) / (multFccoDiv * nDivOutHz);
- /* MDEC set by SSC */
- pSetup->SYSPLLSSCTRL[0] = 0;
+ /* MDEC set by SSC */
+ pSetup->SYSPLLSSCTRL[0] = 0;
- /* Set multiplier */
- pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) |
- PLL_SSCG1_MD_FRACT_SET((uint32_t) fc);
- }
+ /* Set multiplier */
+ pSetup->SYSPLLSSCTRL[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) |
+ PLL_SSCG1_MD_FRACT_SET((uint32_t) fc);
+ }
- /* Get encoded values for N (prediv) and P (postdiv) */
- pSetup->SYSPLLNDEC = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
- pSetup->SYSPLLPDEC = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
+ /* Get encoded values for N (prediv) and P (postdiv) */
+ pSetup->SYSPLLNDEC = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
+ pSetup->SYSPLLPDEC = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
- /* PLL control */
- pSetup->SYSPLLCTRL =
- (pllSelR << SYSCON_SYSPLLCTRL_SELR_P) | /* Filter coefficient */
- (pllSelI << SYSCON_SYSPLLCTRL_SELI_P) | /* Filter coefficient */
- (pllSelP << SYSCON_SYSPLLCTRL_SELP_P) | /* Filter coefficient */
- (0 << SYSCON_SYSPLLCTRL_BYPASS_P) | /* PLL bypass mode disabled */
- (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P) | /* Extra M / 2 divider? */
- (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_P) | /* SS/fractional mode disabled */
- (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P) | /* Manual bandwidth selection enabled */
- (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_P) | /* Bypass pre-divider? */
- (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_P); /* Bypass post-divider? */
+ /* PLL control */
+ pSetup->SYSPLLCTRL =
+ (pllSelR << SYSCON_SYSPLLCTRL_SELR_P) | /* Filter coefficient */
+ (pllSelI << SYSCON_SYSPLLCTRL_SELI_P) | /* Filter coefficient */
+ (pllSelP << SYSCON_SYSPLLCTRL_SELP_P) | /* Filter coefficient */
+ (0 << SYSCON_SYSPLLCTRL_BYPASS_P) | /* PLL bypass mode disabled */
+ (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASS_FBDIV2_P) | /* Extra M / 2 divider? */
+ (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_P) | /* SS/fractional mode disabled */
+ (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SSCGREG_N_P) | /* Manual bandwidth selection enabled */
+ (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_P) | /* Bypass pre-divider? */
+ (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_P); /* Bypass post-divider? */
- return PLL_ERROR_SUCCESS;
+ return PLL_ERROR_SUCCESS;
}
/* Update local PLL rate variable */
static void Chip_Clock_GetSystemPLLOutFromSetupUpdate(PLL_SETUP_T *pSetup)
{
- curPllRate = Chip_Clock_GetSystemPLLOutFromSetup(pSetup);
+ curPllRate = Chip_Clock_GetSystemPLLOutFromSetup(pSetup);
}
/*****************************************************************************
@@ -658,209 +706,223 @@ static void Chip_Clock_GetSystemPLLOutFromSetupUpdate(PLL_SETUP_T *pSetup)
/* Return System PLL input clock rate */
uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
{
- uint32_t clkRate = 0;
+ uint32_t clkRate = 0;
- switch ((CHIP_SYSCON_PLLCLKSRC_T) (LPC_SYSCON->SYSPLLCLKSEL & 0x3)) {
- case SYSCON_PLLCLKSRC_IRC:
- clkRate = Chip_Clock_GetIntOscRate();
- break;
+ switch ((CHIP_SYSCON_PLLCLKSRC_T) (LPC_SYSCON->SYSPLLCLKSEL & 0x3))
+ {
+ case SYSCON_PLLCLKSRC_IRC:
+ clkRate = Chip_Clock_GetIntOscRate();
+ break;
- case SYSCON_PLLCLKSRC_CLKIN:
- clkRate = Chip_Clock_GetExtClockInRate();
- break;
+ case SYSCON_PLLCLKSRC_CLKIN:
+ clkRate = Chip_Clock_GetExtClockInRate();
+ break;
- case SYSCON_PLLCLKSRC_WDTOSC:
- clkRate = Chip_Clock_GetWDTOSCRate();
- break;
+ case SYSCON_PLLCLKSRC_WDTOSC:
+ clkRate = Chip_Clock_GetWDTOSCRate();
+ break;
- case SYSCON_PLLCLKSRC_RTC:
- clkRate = Chip_Clock_GetRTCOscRate();
- break;
- }
+ case SYSCON_PLLCLKSRC_RTC:
+ clkRate = Chip_Clock_GetRTCOscRate();
+ break;
+ }
- return clkRate;
+ return clkRate;
}
/* Return System PLL output clock rate from setup structure */
uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup)
{
- uint32_t prediv, postdiv, mMult, inPllRate;
- uint64_t workRate;
+ uint32_t prediv, postdiv, mMult, inPllRate;
+ uint64_t workRate;
- inPllRate = Chip_Clock_GetSystemPLLInClockRate();
- if ((pSetup->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_P) == 0) {
- /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
- prediv = findPllPreDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLNDEC);
- postdiv = findPllPostDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLPDEC);
+ inPllRate = Chip_Clock_GetSystemPLLInClockRate();
+ if ((pSetup->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_P) == 0)
+ {
+ /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+ prediv = findPllPreDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLNDEC);
+ postdiv = findPllPostDiv(pSetup->SYSPLLCTRL, pSetup->SYSPLLPDEC);
- /* Adjust input clock */
- inPllRate = inPllRate / prediv;
+ /* Adjust input clock */
+ inPllRate = inPllRate / prediv;
- /* If using the SS, use the multiplier */
- if (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MOD_PD_SSCGCLK_N) {
- /* MDEC used for rate */
- mMult = findPllMMult(pSetup->SYSPLLCTRL, pSetup->SYSPLLSSCTRL[0]);
- workRate = (uint64_t) inPllRate * (uint64_t) mMult;
- }
- else {
- uint64_t fract;
+ /* If using the SS, use the multiplier */
+ if (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MOD_PD_SSCGCLK_N)
+ {
+ /* MDEC used for rate */
+ mMult = findPllMMult(pSetup->SYSPLLCTRL, pSetup->SYSPLLSSCTRL[0]);
+ workRate = (uint64_t) inPllRate * (uint64_t) mMult;
+ }
+ else {
+ uint64_t fract;
- /* SS multipler used for rate */
- mMult = (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P;
- workRate = (uint64_t) inPllRate * (uint64_t) mMult;
+ /* SS multipler used for rate */
+ mMult = (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P;
+ workRate = (uint64_t) inPllRate * (uint64_t) mMult;
- /* Adjust by fractional */
- fract = (uint64_t) (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P;
- workRate = workRate + ((inPllRate * fract) / 0x7FF);
- }
+ /* Adjust by fractional */
+ fract = (uint64_t) (pSetup->SYSPLLSSCTRL[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P;
+ workRate = workRate + ((inPllRate * fract) / 0x7FF);
+ }
- workRate = workRate / ((uint64_t) postdiv);
- }
- else {
- /* In bypass mode */
- workRate = (uint64_t) inPllRate;
- }
+ workRate = workRate / ((uint64_t) postdiv);
+ }
+ else {
+ /* In bypass mode */
+ workRate = (uint64_t) inPllRate;
+ }
- return (uint32_t) workRate;
+ return (uint32_t) workRate;
}
/* Return System PLL output clock rate */
uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute)
{
- PLL_SETUP_T Setup;
- uint32_t rate;
+ PLL_SETUP_T Setup;
+ uint32_t rate;
- if ((recompute) || (curPllRate == 0)) {
- Setup.SYSPLLCTRL = LPC_SYSCON->SYSPLLCTRL;
- Setup.SYSPLLNDEC = LPC_SYSCON->SYSPLLNDEC;
- Setup.SYSPLLPDEC = LPC_SYSCON->SYSPLLPDEC;
- Setup.SYSPLLSSCTRL[0] = LPC_SYSCON->SYSPLLSSCTRL[0];
- Setup.SYSPLLSSCTRL[1] = LPC_SYSCON->SYSPLLSSCTRL[1];
+ if ((recompute) || (curPllRate == 0))
+ {
+ Setup.SYSPLLCTRL = LPC_SYSCON->SYSPLLCTRL;
+ Setup.SYSPLLNDEC = LPC_SYSCON->SYSPLLNDEC;
+ Setup.SYSPLLPDEC = LPC_SYSCON->SYSPLLPDEC;
+ Setup.SYSPLLSSCTRL[0] = LPC_SYSCON->SYSPLLSSCTRL[0];
+ Setup.SYSPLLSSCTRL[1] = LPC_SYSCON->SYSPLLSSCTRL[1];
- Chip_Clock_GetSystemPLLOutFromSetupUpdate(&Setup);
- }
+ Chip_Clock_GetSystemPLLOutFromSetupUpdate(&Setup);
+ }
- rate = curPllRate;
+ rate = curPllRate;
- return rate;
+ return rate;
}
/* Enables and disables PLL bypass mode */
void Chip_Clock_SetBypassPLL(bool bypass)
{
- if (bypass) {
- LPC_SYSCON->SYSPLLCTRL |= SYSCON_SYSPLLCTRL_BYPASS_P;
- }
- else {
- LPC_SYSCON->SYSPLLCTRL &= ~SYSCON_SYSPLLCTRL_BYPASS_P;
- }
+ if (bypass)
+ {
+ LPC_SYSCON->SYSPLLCTRL |= SYSCON_SYSPLLCTRL_BYPASS_P;
+ }
+ else {
+ LPC_SYSCON->SYSPLLCTRL &= ~SYSCON_SYSPLLCTRL_BYPASS_P;
+ }
}
/* Set PLL output based on the passed PLL setup data */
PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup)
{
- uint32_t inRate;
- bool useSS = (bool) ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0);
- PLL_ERROR_T pllError;
+ uint32_t inRate;
+ bool useSS = (bool) ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0);
+ PLL_ERROR_T pllError;
- /* Determine input rate for the PLL */
- if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0) {
- inRate = pControl->InputRate;
- }
- else {
- inRate = Chip_Clock_GetSystemPLLInClockRate();
- }
+ /* Determine input rate for the PLL */
+ if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0)
+ {
+ inRate = pControl->InputRate;
+ }
+ else {
+ inRate = Chip_Clock_GetSystemPLLInClockRate();
+ }
- /* PLL flag options */
- pllError = Chip_Clock_GetPllConfig(inRate, pControl->desiredRate, pSetup, false, useSS);
- if ((useSS) && (pllError == PLL_ERROR_SUCCESS)) {
- /* If using SS mode, then some tweaks are made to the generated setup */
- pSetup->SYSPLLSSCTRL[1] |= (uint32_t) pControl->ss_mf | (uint32_t) pControl->ss_mr |
- (uint32_t) pControl->ss_mc;
- if (pControl->mfDither) {
- pSetup->SYSPLLSSCTRL[1] |= PLL_SSCG1_DITHER;
- }
- }
+ /* PLL flag options */
+ pllError = Chip_Clock_GetPllConfig(inRate, pControl->desiredRate, pSetup, false, useSS);
+ if ((useSS) && (pllError == PLL_ERROR_SUCCESS))
+ {
+ /* If using SS mode, then some tweaks are made to the generated setup */
+ pSetup->SYSPLLSSCTRL[1] |= (uint32_t) pControl->ss_mf | (uint32_t) pControl->ss_mr |
+ (uint32_t) pControl->ss_mc;
+ if (pControl->mfDither)
+ {
+ pSetup->SYSPLLSSCTRL[1] |= PLL_SSCG1_DITHER;
+ }
+ }
- return pllError;
+ return pllError;
}
/* Set PLL output from PLL setup structure */
PLL_ERROR_T Chip_Clock_SetupSystemPLLPrec(PLL_SETUP_T *pSetup)
{
- /* Power off PLL during setup changes */
- Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL);
+ /* Power off PLL during setup changes */
+ Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL);
- /* Write PLL setup data */
- LPC_SYSCON->SYSPLLCTRL = pSetup->SYSPLLCTRL;
- LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC;
- LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC | PLL_NDEC_NREQ;/* latch */
- LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC;
- LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC | PLL_PDEC_PREQ;/* latch */
- LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0];
- LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0] | PLL_SSCG0_MREQ; /* latch */
- LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1];
- LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1] | PLL_SSCG1_MD_REQ; /* latch */
+ /* Write PLL setup data */
+ LPC_SYSCON->SYSPLLCTRL = pSetup->SYSPLLCTRL;
+ LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC;
+ LPC_SYSCON->SYSPLLNDEC = pSetup->SYSPLLNDEC | PLL_NDEC_NREQ;/* latch */
+ LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC;
+ LPC_SYSCON->SYSPLLPDEC = pSetup->SYSPLLPDEC | PLL_PDEC_PREQ;/* latch */
+ LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0];
+ LPC_SYSCON->SYSPLLSSCTRL[0] = pSetup->SYSPLLSSCTRL[0] | PLL_SSCG0_MREQ; /* latch */
+ LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1];
+ LPC_SYSCON->SYSPLLSSCTRL[1] = pSetup->SYSPLLSSCTRL[1] | PLL_SSCG1_MD_REQ; /* latch */
- /* Flags for lock or power on */
- if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) {
- Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_SYS_PLL);
- }
- if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0) {
- while (Chip_Clock_IsSystemPLLLocked() == false) {}
- }
+ /* Flags for lock or power on */
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
+ {
+ Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_SYS_PLL);
+ }
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0)
+ {
+ while (Chip_Clock_IsSystemPLLLocked() == false)
+ {}
+ }
- /* Update current programmed PLL rate var */
- Chip_Clock_GetSystemPLLOutFromSetupUpdate(pSetup);
+ /* Update current programmed PLL rate var */
+ Chip_Clock_GetSystemPLLOutFromSetupUpdate(pSetup);
- /* System voltage adjustment, occurs prior to setting main system clock */
- if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0) {
- Chip_POWER_SetVoltage(POWER_LOW_POWER_MODE, curPllRate);
- }
+ /* System voltage adjustment, occurs prior to setting main system clock */
+ if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0)
+ {
+ Chip_POWER_SetVoltage(POWER_LOW_POWER_MODE, curPllRate);
+ }
- return PLL_ERROR_SUCCESS;
+ return PLL_ERROR_SUCCESS;
}
/* Set System PLL clock based on the input frequency and multiplier */
void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq)
{
- uint32_t cco_freq = input_freq * multiply_by;
- uint32_t pdec = 1;
- uint32_t selr;
- uint32_t seli;
- uint32_t selp;
- uint32_t mdec, ndec;
+ uint32_t cco_freq = input_freq * multiply_by;
+ uint32_t pdec = 1;
+ uint32_t selr;
+ uint32_t seli;
+ uint32_t selp;
+ uint32_t mdec, ndec;
- uint32_t directo = SYS_PLL_DIRECTO;
+ uint32_t directo = SYS_PLL_DIRECTO;
- while (cco_freq < 75000000) {
- multiply_by <<= 1; /* double value in each iteration */
- pdec <<= 1; /* correspondingly double pdec to cancel effect of double msel */
- cco_freq = input_freq * multiply_by;
- }
- selr = 0;
- seli = (multiply_by & 0x3c) + 4;
- selp = (multiply_by >> 1) + 1;
+ while (cco_freq < 75000000)
+ {
+ multiply_by <<= 1; /* double value in each iteration */
+ pdec <<= 1; /* correspondingly double pdec to cancel effect of double msel */
+ cco_freq = input_freq * multiply_by;
+ }
+ selr = 0;
+ seli = (multiply_by & 0x3c) + 4;
+ selp = (multiply_by >> 1) + 1;
- if (pdec > 1) {
- directo = 0; /* use post divider */
- pdec = pdec / 2; /* Account for minus 1 encoding */
- /* Translate P value */
- pdec = (pdec == 1) ? 0x62 : /* 1 * 2 */
- (pdec == 2) ? 0x42 : /* 2 * 2 */
- (pdec == 4) ? 0x02 : /* 4 * 2 */
- (pdec == 8) ? 0x0b : /* 8 * 2 */
- (pdec == 16) ? 0x11 : /* 16 * 2 */
- (pdec == 32) ? 0x08 : 0x08; /* 32 * 2 */
- }
+ if (pdec > 1)
+ {
+ directo = 0; /* use post divider */
+ pdec = pdec / 2; /* Account for minus 1 encoding */
+ /* Translate P value */
+ pdec = (pdec == 1) ? 0x62 : /* 1 * 2 */
+ (pdec == 2) ? 0x42 : /* 2 * 2 */
+ (pdec == 4) ? 0x02 : /* 4 * 2 */
+ (pdec == 8) ? 0x0b : /* 8 * 2 */
+ (pdec == 16) ? 0x11 : /* 16 * 2 */
+ (pdec == 32) ? 0x08 : 0x08; /* 32 * 2 */
+ }
- /* Only support values of 2 to 16 (to keep driver simple) */
- mdec = 0x7fff >> (16 - (multiply_by - 1));
- ndec = 0x202; /* pre divide by 2 (hardcoded) */
+ /* Only support values of 2 to 16 (to keep driver simple) */
+ mdec = 0x7fff >> (16 - (multiply_by - 1));
+ ndec = 0x202; /* pre divide by 2 (hardcoded) */
- LPC_SYSCON->SYSPLLCTRL = SYS_PLL_BANDSEL | directo | (selr << SYSCON_SYSPLLCTRL_SELR_P) |
- (seli << SYSCON_SYSPLLCTRL_SELI_P) | (selp << SYSCON_SYSPLLCTRL_SELP_P);
- LPC_SYSCON->SYSPLLPDEC = pdec | (1 << 7); /* set Pdec value and assert preq */
- LPC_SYSCON->SYSPLLNDEC = ndec | (1 << 10); /* set Pdec value and assert preq */
- LPC_SYSCON->SYSPLLSSCTRL[0] = (1 << 18) | (1 << 17) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
+ LPC_SYSCON->SYSPLLCTRL = SYS_PLL_BANDSEL | directo | (selr << SYSCON_SYSPLLCTRL_SELR_P) |
+ (seli << SYSCON_SYSPLLCTRL_SELI_P) | (selp << SYSCON_SYSPLLCTRL_SELP_P);
+ LPC_SYSCON->SYSPLLPDEC = pdec | (1 << 7); /* set Pdec value and assert preq */
+ LPC_SYSCON->SYSPLLNDEC = ndec | (1 << 10); /* set Pdec value and assert preq */
+ LPC_SYSCON->SYSPLLSSCTRL[0] = (1 << 18) | (1 << 17) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
}
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.lib b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.lib
new file mode 100644
index 0000000000..d6271384a4
--- /dev/null
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/keil/lib_power.lib
Binary files differ
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower.a b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower.a
new file mode 100644
index 0000000000..f5064ec2ef
--- /dev/null
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/power_lib/lpcxpresso/libpower.a
Binary files differ
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h
index e173bd4fb4..68b7e2622a 100644
--- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_5410x/romapi_5410x.h
@@ -63,27 +63,27 @@ extern "C" {
* @brief High level ROM API structure
*/
typedef struct {
- const uint32_t reserved_usb; /*!< Reserved */
- const uint32_t reserved_clib; /*!< Reserved */
- const uint32_t reserved_can; /*!< Reserved */
- const PWRD_API_T *pPWRD; /*!< Power API function table base address */
- const uint32_t reserved_div; /*!< Reserved */
- const uint32_t reserved_i2cd; /*!< Reserved */
- const uint32_t reserved_dmad; /*!< Reserved */
- const uint32_t reserved_spid; /*!< Reserved */
- const uint32_t reserved_adcd; /*!< Reserved */
- const uint32_t reserved_uartd; /*!< Reserved */
- const uint32_t reserved_vfifo; /*!< Reserved */
- const uint32_t reserved_usart; /*!< Reserved */
- /* v2 drivers - only present in some LPC5410x devices */
- const ROM_I2CMD_API_T *pI2CMD; /*!< v2 I2C master only driver API function table base address */
- const ROM_I2CSD_API_T *pI2CSD; /*!< v2 I2C slave only driver API function table base address */
- const ROM_I2CMOND_API_T *pI2CMOND; /*!< v2 I2C bus monitor driver API function table base address */
- const ROM_SPIMD_API_T *pSPIMD; /*!< v2 SPI master only driver API function table base address */
- const ROM_SPISD_API_T *pSPISD; /*!< v2 SPI slave only driver API function table base address */
- const ROM_DMAALTD_API_T *pDMAALT; /*!< v2 abstract DMA driver API function table base address */
- const ROM_ADC_API_T *pADCALT; /*!< v2 ADC driver API function table base address */
- const ROM_UART_API_T *pUARTALT; /*!< v2 UART driver API function table base address */
+ const uint32_t reserved_usb; /*!< Reserved */
+ const uint32_t reserved_clib; /*!< Reserved */
+ const uint32_t reserved_can; /*!< Reserved */
+ const PWRD_API_T *pPWRD; /*!< Power API function table base address */
+ const uint32_t reserved_div; /*!< Reserved */
+ const uint32_t reserved_i2cd; /*!< Reserved */
+ const uint32_t reserved_dmad; /*!< Reserved */
+ const uint32_t reserved_spid; /*!< Reserved */
+ const uint32_t reserved_adcd; /*!< Reserved */
+ const uint32_t reserved_uartd; /*!< Reserved */
+ const uint32_t reserved_vfifo; /*!< Reserved */
+ const uint32_t reserved_usart; /*!< Reserved */
+ /* v2 drivers - only present in some LPC5410x devices */
+ const ROM_I2CMD_API_T *pI2CMD; /*!< v2 I2C master only driver API function table base address */
+ const ROM_I2CSD_API_T *pI2CSD; /*!< v2 I2C slave only driver API function table base address */
+ const ROM_I2CMOND_API_T *pI2CMOND; /*!< v2 I2C bus monitor driver API function table base address */
+ const ROM_SPIMD_API_T *pSPIMD; /*!< v2 SPI master only driver API function table base address */
+ const ROM_SPISD_API_T *pSPISD; /*!< v2 SPI slave only driver API function table base address */
+ const ROM_DMAALTD_API_T *pDMAALT; /*!< v2 abstract DMA driver API function table base address */
+ const ROM_ADC_API_T *pADCALT; /*!< v2 ADC driver API function table base address */
+ const ROM_UART_API_T *pUARTALT; /*!< v2 UART driver API function table base address */
} LPC_ROM_API_T;
/* Pointer to ROM API function address */
@@ -123,9 +123,9 @@ typedef struct {
/**
* @brief LPC5410x IAP_ENTRY API function type
*/
-static INLINE void iap_entry(unsigned int cmd_param[5], unsigned int status_result[4])
+static INLINE void iap_entry(uint32_t cmd_param[5], uint32_t status_result[4])
{
- ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
+ ((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
}
/**
diff --git a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h
index a90e87c9b7..78b167f1e8 100644
--- a/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h
+++ b/bsp/nxp/lpc/lpc5410x/Libraries/lpc_chip/chip_common/iap.h
@@ -78,7 +78,7 @@ extern "C" {
#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */
/* IAP_ENTRY API function type */
-typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]);
+typedef void (*IAP_ENTRY_T)(uint32_t[5], uint32_t[4]);
/**
* @brief Prepare sector for write operation
diff --git a/bsp/nxp/lpc/lpc5410x/applications/board.h b/bsp/nxp/lpc/lpc5410x/applications/board.h
index 03f6a284e7..df35e83732 100644
--- a/bsp/nxp/lpc/lpc5410x/applications/board.h
+++ b/bsp/nxp/lpc/lpc5410x/applications/board.h
@@ -25,21 +25,10 @@
#endif
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
-
// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
#define LPC_EXT_SDRAM_BEGIN 0xA0000000
// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
#define LPC_EXT_SDRAM_END 0xA2000000
-
-// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
-#define RT_USING_UART0
-// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
-//#define RT_USING_UART1
-// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
-#define RT_USING_UART2
-// <string name="RT_CONSOLE_DEVICE_NAME" description="The name of console device" default="" />
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-
// </RDTConfigurator>
#ifdef __CC_ARM
diff --git a/bsp/nxp/lpc/lpc5410x/drivers/drv_uart.c b/bsp/nxp/lpc/lpc5410x/drivers/drv_uart.c
index 826e659eb4..6d981161db 100644
--- a/bsp/nxp/lpc/lpc5410x/drivers/drv_uart.c
+++ b/bsp/nxp/lpc/lpc5410x/drivers/drv_uart.c
@@ -157,6 +157,7 @@ void UART0_IRQHandler(void)
break;
default :
tmp = LPC_USART0->INTSTAT;
+ RT_UNUSED(tmp);
break;
}
/* leave interrupt */
diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.lib b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.lib
new file mode 100644
index 0000000000..304a63f82f
--- /dev/null
+++ b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/arm/keil_lib_power.lib
Binary files differ
diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a
new file mode 100644
index 0000000000..1f40c8ccf6
--- /dev/null
+++ b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a
Binary files differ
diff --git a/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a
new file mode 100644
index 0000000000..c0a587fb0e
--- /dev/null
+++ b/bsp/nxp/lpc/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a
Binary files differ
diff --git a/bsp/nxp/lpc/lpc54114-lite/drivers/drv_spi.c b/bsp/nxp/lpc/lpc54114-lite/drivers/drv_spi.c
index c83aaf03ee..2c3bbdea2c 100644
--- a/bsp/nxp/lpc/lpc54114-lite/drivers/drv_spi.c
+++ b/bsp/nxp/lpc/lpc54114-lite/drivers/drv_spi.c
@@ -128,7 +128,7 @@ static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configurat
return ret;
}
-static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
spi_transfer_t transfer = {0};
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 06:05:02 +0000