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authorguo <[email protected]>2022-12-03 12:07:44 +0800
committerGitHub <[email protected]>2022-12-03 12:07:44 +0800
commitecf2d8215961ca7c539132b62a72df6072cc3e14 (patch)
tree59005f0f74f2593c0435059264f624c862a89f55 /include/rthw.h
parentaaf5462c6d4ae9466a0a8cd2a4bb00cfe1fef2f2 (diff)
sync branch rt-smart. (#6641)
* Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <[email protected]> Co-authored-by: zhkag <[email protected]>
Diffstat (limited to 'include/rthw.h')
-rw-r--r--include/rthw.h40
1 files changed, 30 insertions, 10 deletions
diff --git a/include/rthw.h b/include/rthw.h
index b55d12e2a7..3c1e743279 100644
--- a/include/rthw.h
+++ b/include/rthw.h
@@ -12,6 +12,7 @@
* 2017-10-17 Hichard add some macros
* 2018-11-17 Jesven add rt_hw_spinlock_t
* add smp support
+ * 2019-05-18 Bernard add empty definition for not enable cache case
*/
#ifndef __RT_HW_H__
@@ -52,6 +53,7 @@ enum RT_HW_CACHE_OPS
/*
* CPU interfaces
*/
+#ifdef RT_USING_CACHE
void rt_hw_cpu_icache_enable(void);
void rt_hw_cpu_icache_disable(void);
rt_base_t rt_hw_cpu_icache_status(void);
@@ -61,6 +63,20 @@ void rt_hw_cpu_dcache_enable(void);
void rt_hw_cpu_dcache_disable(void);
rt_base_t rt_hw_cpu_dcache_status(void);
void rt_hw_cpu_dcache_ops(int ops, void* addr, int size);
+#else
+
+/* define cache ops as empty */
+#define rt_hw_cpu_icache_enable(...)
+#define rt_hw_cpu_icache_disable(...)
+#define rt_hw_cpu_icache_ops(...)
+#define rt_hw_cpu_dcache_enable(...)
+#define rt_hw_cpu_dcache_disable(...)
+#define rt_hw_cpu_dcache_ops(...)
+
+#define rt_hw_cpu_icache_status(...) 0
+#define rt_hw_cpu_dcache_status(...) 0
+
+#endif
void rt_hw_cpu_reset(void);
void rt_hw_cpu_shutdown(void);
@@ -119,7 +135,7 @@ void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t t
#else
void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
void rt_hw_context_switch_to(rt_ubase_t to);
-void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
+void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread);
#endif /*RT_USING_SMP*/
void rt_hw_console_output(const char *str);
@@ -138,13 +154,7 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context));
void rt_hw_us_delay(rt_uint32_t us);
#ifdef RT_USING_SMP
-typedef union {
- unsigned long slock;
- struct __arch_tickets {
- unsigned short owner;
- unsigned short next;
- } tickets;
-} rt_hw_spinlock_t;
+#include <cpuport.h> /* for spinlock from arch */
struct rt_spinlock
{
@@ -184,12 +194,22 @@ void rt_hw_secondary_cpu_up(void);
void rt_hw_secondary_cpu_idle_exec(void);
#else
-#define RT_DEFINE_SPINLOCK(x)
-#define RT_DECLARE_SPINLOCK(x) rt_ubase_t x
+#define RT_DEFINE_SPINLOCK(x) rt_ubase_t x
+#define RT_DECLARE_SPINLOCK(x)
#define rt_hw_spin_lock(lock) *(lock) = rt_hw_interrupt_disable()
#define rt_hw_spin_unlock(lock) rt_hw_interrupt_enable(*(lock))
+typedef int rt_spinlock_t;
+
+#endif
+
+#ifdef RT_USING_CACHE
+#include <cpuport.h>
+#else
+#define rt_hw_isb()
+#define rt_hw_dmb()
+#define rt_hw_dsb()
#endif
#ifdef __cplusplus