[bsp][phytium]适配rt-thread5.0.0 版本 (#7441)

Co-authored-by: 朱耿宇 <[email protected]>

4 files changed, 12 insertions, 7 deletions

diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S
index 0a611cbf48..6afc676ae3 100644
--- a/libcpu/aarch64/common/context_gcc.S
+++ b/libcpu/aarch64/common/context_gcc.S
@@ -24,7 +24,7 @@ rt_hw_cpu_id_set:
 /*
 int rt_hw_cpu_id(void)
 */
-.global rt_hw_cpu_id
+.weak rt_hw_cpu_id
 .type rt_hw_cpu_id, @function
 rt_hw_cpu_id:
    mrs x0, tpidr_el1           /* MPIDR_EL1: Multi-Processor Affinity Register */
diff --git a/libcpu/aarch64/common/gicv3.c b/libcpu/aarch64/common/gicv3.c
index 18fdcddc7f..35864fea2f 100644
--- a/libcpu/aarch64/common/gicv3.c
+++ b/libcpu/aarch64/common/gicv3.c
@@ -45,9 +45,9 @@ extern rt_uint64_t rt_cpu_mpidr_early[];
 struct arm_gic
 {
     rt_uint64_t offset;                     /* the first interrupt index in the vector table */
-    rt_uint64_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */
+    rt_uint64_t redist_hw_base[ARM_GIC_CPU_NUM]; /* the pointer of the gic redistributor */
     rt_uint64_t dist_hw_base;               /* the base address of the gic distributor */
-    rt_uint64_t cpu_hw_base[RT_CPUS_NR];    /* the base address of the gic cpu interface */
+    rt_uint64_t cpu_hw_base[ARM_GIC_CPU_NUM];    /* the base address of the gic cpu interface */
 };
 
 /* 'ARM_GIC_MAX_NR' is the number of cores */
@@ -737,7 +737,7 @@ int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base)
 
     if (master_cpu_id < 0)
     {
-        master_cpu_id = cpu_id;
+        master_cpu_id = 0;
         rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &master_cpu_id, sizeof(master_cpu_id));
     }
 
diff --git a/libcpu/aarch64/common/gicv3.h b/libcpu/aarch64/common/gicv3.h
index cdc7720b37..fbcf3fb4d9 100644
--- a/libcpu/aarch64/common/gicv3.h
+++ b/libcpu/aarch64/common/gicv3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,6 +18,11 @@
 
 #if defined(BSP_USING_GIC) && defined(BSP_USING_GICV3)
 
+
+#ifndef ARM_GIC_CPU_NUM
+#define ARM_GIC_CPU_NUM RT_CPUS_NR
+#endif
+
 #define GICV3_ROUTED_TO_ALL   1UL
 #define GICV3_ROUTED_TO_SPEC  0UL
 
diff --git a/libcpu/aarch64/common/interrupt.c b/libcpu/aarch64/common/interrupt.c
index e30223a696..dc142dd9e8 100644
--- a/libcpu/aarch64/common/interrupt.c
+++ b/libcpu/aarch64/common/interrupt.c
@@ -109,11 +109,11 @@ void rt_hw_interrupt_init(void)
 
     /* initialize ARM GIC */
 #ifdef RT_USING_SMART
-    gic_dist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x2000);
+    gic_dist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x40000);
     gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
 #ifdef BSP_USING_GICV3
     gic_rdist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_redist_base(),
-            RT_CPUS_NR * (2 << 16));
+            ARM_GIC_CPU_NUM * (2 << 16));
 #endif
 #else
     gic_dist_base = platform_get_gic_dist_base();