[libcpu][aarch64] 使用设备树对内存进行初始化 (#8320)

1 files changed, 238 insertions, 240 deletions

diff --git a/libcpu/aarch64/cortex-a/entry_point.S b/libcpu/aarch64/cortex-a/entry_point.S
index 08e4b03768..d68f31a89b 100644
--- a/libcpu/aarch64/cortex-a/entry_point.S
+++ b/libcpu/aarch64/cortex-a/entry_point.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,7 +9,46 @@
  * 2023-04-29     GuEe-GUI     support kernel's ARM64 boot header
  */
 
-#include "rtconfig.h"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mmu.h>
+#include <rtconfig.h>
+
+#define ARM64_IMAGE_FLAG_BE_SHIFT           0
+#define ARM64_IMAGE_FLAG_PAGE_SIZE_SHIFT    (ARM64_IMAGE_FLAG_BE_SHIFT + 1)
+#define ARM64_IMAGE_FLAG_PHYS_BASE_SHIFT    (ARM64_IMAGE_FLAG_PAGE_SIZE_SHIFT + 2)
+
+#define ARM64_IMAGE_FLAG_LE                 0
+#define ARM64_IMAGE_FLAG_BE                 1
+#define ARM64_IMAGE_FLAG_PAGE_SIZE_4K       1
+#define ARM64_IMAGE_FLAG_PAGE_SIZE_16K      2
+#define ARM64_IMAGE_FLAG_PAGE_SIZE_64K      3
+#define ARM64_IMAGE_FLAG_PHYS_BASE          1
+
+#define _HEAD_FLAG(field)                   (_HEAD_FLAG_##field << ARM64_IMAGE_FLAG_##field##_SHIFT)
+
+#ifdef ARCH_CPU_BIG_ENDIAN
+#define _HEAD_FLAG_BE                       ARM64_IMAGE_FLAG_BE
+#else
+#define _HEAD_FLAG_BE                       ARM64_IMAGE_FLAG_LE
+#endif
+#define _HEAD_FLAG_PAGE_SIZE                ((ARCH_PAGE_SHIFT - 10) / 2)
+#define _HEAD_FLAG_PHYS_BASE                1
+
+#define _HEAD_FLAGS                         (_HEAD_FLAG(BE) | _HEAD_FLAG(PAGE_SIZE) | _HEAD_FLAG(PHYS_BASE))
+
+.macro get_phy, reg, symbol
+    adrp    \reg, \symbol
+    add     \reg, \reg, #:lo12:\symbol
+.endm
+
+.macro get_pvoff, tmp, out
+    ldr     \tmp, =.boot_cpu_stack_top
+    get_phy \out, .boot_cpu_stack_top
+    sub     \out, \out, \tmp
+.endm
 
     .section ".text.entrypoint","ax"
 
@@ -24,7 +63,7 @@ _head:
     .long   0               /* Executable code */
     .quad   _text_offset    /* Image load offset from start of RAM, little endian */
     .quad   _end - _head    /* Effective Image size, little endian (_end defined in link.lds) */
-    .quad   0xa             /* Kernel flags, little endian */
+    .quad   _HEAD_FLAGS     /* Kernel flags, little endian */
     .quad   0               /* Reserved */
     .quad   0               /* Reserved */
     .quad   0               /* Reserved */
@@ -38,7 +77,7 @@ boot_arg1 .req x23
 boot_arg2 .req x24
 stack_top .req x25
 
-.global _start
+    .global _start
 _start:
 /*
  * Boot CPU general-purpose register settings:
@@ -51,296 +90,255 @@ _start:
     mov     boot_arg0, x1
     mov     boot_arg1, x2
     mov     boot_arg2, x3
-#ifdef ARCH_ARM_BOOTWITH_FLUSH_CACHE
-    bl      __asm_flush_dcache_all
+
+    /* Save cpu stack */
+    get_phy stack_top, .boot_cpu_stack_top
+    /* Save cpu id temp */
+    msr     tpidr_el1, xzr
+
+    bl      init_cpu_el
+    bl      init_kernel_bss
+    bl      init_cpu_stack_early
+
+#ifdef RT_USING_OFW
+    /* Save devicetree info */
+    mov     x0, dtb_paddr
+    bl      rt_hw_fdt_install_early
 #endif
-    bl      rt_hw_cpu_id_set
-    /* read cpu id, stop slave cores */
-    mrs     x0, tpidr_el1
-    cbz     x0, .L__cpu_0           /* .L prefix is the local label in ELF */
 
-#ifndef RT_AMP_SLAVE
-    /* cpu id > 0, stop */
-    /* cpu id == 0 will also goto here after returned from entry() if possible */
-.L__current_cpu_idle:
+    /* Now we are in the end of boot cpu process */
+    ldr     x8, =rtthread_startup
+    b       init_mmu_early
+
+kernel_start:
+    /* jump to the PE's system entry */
+    mov     x29, xzr
+    mov     x30, x8
+    br      x8
+
+cpu_idle:
     wfe
-    b       .L__current_cpu_idle
+    b       cpu_idle
+
+#ifdef RT_USING_SMP
+    .globl _secondary_cpu_entry
+_secondary_cpu_entry:
+#ifdef RT_USING_OFW
+    /* Read cpu id */
+    mrs     x5, mpidr_el1
+    ldr     x1, =rt_cpu_mpidr_table
+    get_pvoff x4 x2
+    add     x1, x1, x2
+    mov     x2, #0
+    ldr     x4, =0xff00ffffff
+    and     x0, x5, x4
+
+.cpu_id_confirm:
+    add     x2, x2, #1              /* Next cpu id inc */
+    ldr     x3, [x1], #8
+    cmp     x3, #0
+    beq     cpu_idle
+    and     x3, x3, x4
+    cmp     x3, x0
+    bne     .cpu_id_confirm
+
+    /* Save this mpidr */
+    str     x5, [x1, #-8]
+
+    /* Get cpu id success */
+    sub     x0, x2, #1
+    msr     tpidr_el1, x0           /* Save cpu id global */
+#else
+    bl      rt_hw_cpu_id_set
+    mrs     x0, tpidr_el1
 #endif
 
-.L__cpu_0:
-    /* set stack before our code, Define stack pointer for current exception level */
-    adr     x1, .el_stack_top
+    /* Set current cpu's stack top */
+    sub     x0, x0, #1
+    mov     x1, #ARCH_SECONDARY_CPU_STACK_SIZE
+    get_phy x2, .secondary_cpu_stack_top
+    msub    stack_top, x0, x1, x2
+
+    bl      init_cpu_el
+    bl      init_cpu_stack_early
+
+    /* secondary cpu start to startup */
+    ldr     x8, =rt_hw_secondary_cpu_bsp_start
+    b       enable_mmu_early
+#endif /* RT_USING_SMP */
 
-    /* set up EL1 */
+init_cpu_el:
     mrs     x0, CurrentEL           /* CurrentEL Register. bit 2, 3. Others reserved */
-    and     x0, x0, #12             /* clear reserved bits */
+    lsr     x0, x0, #2
+    and     x0, x0, #3
 
-    /* running at EL3? */
-    cmp     x0, #12                 /* 1100b. So, EL3 */
-    bne     .L__not_in_el3          /* 11?  !EL3 -> 5: */
+    cmp     x0, #3
+    bne     .init_cpu_hyp
 
-    /* should never be executed, just for completeness. (EL3) */
-    mov     x2, #0x5b1
-    msr     scr_el3, x2             /* SCR_ELn  Secure Configuration Register */
-    mov     x2, #0x3c9
-    msr     spsr_el3, x2            /* SPSR_ELn. Saved Program Status Register. 1111001001 */
-    adr     x2, .L__not_in_el3
-    msr     elr_el3, x2
-    eret                            /* Exception Return: from EL3, continue from .L__not_in_el3 */
+    mov     x1, #(1 << 0)           /* EL0 and EL1 are in Non-Secure state */
+    orr     x1, x1, #(1 << 4)       /* RES1 */
+    orr     x1, x1, #(1 << 5)       /* RES1 */
+    orr     x1, x1, #(1 << 10)      /* The next lower level is AArch64 */
+    msr     scr_el3, x1
 
-.L__not_in_el3:                     /* running at EL2 or EL1 */
-    cmp     x0, #4                  /* 0x04  0100 EL1 */
-    beq     .L__in_el1              /* EL1 -> 5: */
+    mov     x1, #9                  /* Next level is 0b1001->EL2h */
+    orr     x1, x1, #(1 << 6)       /* Mask FIQ */
+    orr     x1, x1, #(1 << 7)       /* Mask IRQ */
+    orr     x1, x1, #(1 << 8)       /* Mask SError */
+    orr     x1, x1, #(1 << 9)       /* Mask Debug Exception */
+    msr     spsr_el3, x1
 
-    mrs     x0, hcr_el2
-    bic     x0, x0, #0xff
-    msr     hcr_el2, x0
+    get_phy x1, .init_cpu_hyp
+    msr     elr_el3, x1
+    eret
 
-    msr     sp_el1, x1              /* in EL2, set sp of EL1 to _start */
+.init_cpu_hyp:
+    cmp     x0, #2                  /* EL1 = 0100  */
+    bne     .init_cpu_sys
 
-    /* enable CNTP for EL1 */
+    /* Enable CNTP for EL1 */
     mrs     x0, cnthctl_el2         /* Counter-timer Hypervisor Control register */
-    orr     x0, x0, #3
+    orr     x0, x0, #(1 << 0)       /* Don't traps NS EL0/1 accesses to the physical counter */
+    orr     x0, x0, #(1 << 1)       /* Don't traps NS EL0/1 accesses to the physical timer */
     msr     cnthctl_el2, x0
     msr     cntvoff_el2, xzr
 
-    /* enable AArch64 in EL1 */
-    mov     x0, #(1 << 31)          /* AArch64 */
-    orr     x0, x0, #(1 << 1)       /* SWIO hardwired on Pi3 */
+    mov     x0, #(1 << 31)          /* Enable AArch64 in EL1 */
+    orr     x0, x0, #(1 << 1)       /* SWIO hardwired */
     msr     hcr_el2, x0
-    mrs     x0, hcr_el2
 
-    /* change execution level to EL1 */
-    mov     x2, #0x3c4
-    msr     spsr_el2, x2            /* 1111000100 */
-    adr     x2, .L__in_el1
-    msr     elr_el2, x2
+    mov     x0, #5                  /* Next level is 0b0101->EL1h */
+    orr     x0, x0, #(1 << 6)       /* Mask FIQ */
+    orr     x0, x0, #(1 << 7)       /* Mask IRQ */
+    orr     x0, x0, #(1 << 8)       /* Mask SError */
+    orr     x0, x0, #(1 << 9)       /* Mask Debug Exception */
+    msr     spsr_el2, x0
 
-    eret                            /* exception return. from EL2. continue from .L__in_el1 */
+    get_phy x0, .init_cpu_sys
+    msr     elr_el2, x0
+    eret
 
-.macro GET_PHY reg, symbol
-    adrp    \reg, \symbol
-    add     \reg, \reg, #:lo12:\symbol
-.endm
+.init_cpu_sys:
+    mrs     x0, sctlr_el1
+    orr     x0, x0, #(1 << 12)      /* Enable Instruction */
+    bic     x0, x0, #(3 << 3)       /* Disable SP Alignment check */
+    bic     x0, x0, #(1 << 1)       /* Disable Alignment check */
+    msr     sctlr_el1, x0
 
-.L__in_el1:
-    mov     sp, x1                  /* in EL1. Set sp to _start */
+    /* Avoid trap from SIMD or float point instruction */
+    mov     x0, #0x00300000         /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
+    msr     cpacr_el1, x0
 
-    /* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */
-    mov     x1, #0x00300000         /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
-    msr     cpacr_el1, x1
-    /* applying context change */
+    /* Applying context change */
     dsb     ish
     isb
 
-    /* clear bss */
-    GET_PHY x1, __bss_start
-    GET_PHY x2, __bss_end
-    sub     x2, x2, x1              /* get bss size */
+    ret
+
+init_kernel_bss:
+    get_phy x1, __bss_start
+    get_phy x2, __bss_end
+    sub     x2, x2, x1              /* Get bss size */
 
     and     x3, x2, #7              /* x3 is < 7 */
     ldr     x4, =~0x7
-    and     x2, x2, x4              /* mask ~7 */
+    and     x2, x2, x4              /* Mask ~7 */
 
-.L__clean_bss_loop:
-    cbz     x2, .L__clean_bss_loop_1
+.clean_bss_loop_quad:
+    cbz     x2, .clean_bss_loop_byte
     str     xzr, [x1], #8
     sub     x2, x2, #8
-    b       .L__clean_bss_loop
+    b       .clean_bss_loop_quad
 
-.L__clean_bss_loop_1:
-    cbz     x3, .L__jump_to_entry
+.clean_bss_loop_byte:
+    cbz     x3, .clean_bss_end
     strb    wzr, [x1], #1
     sub     x3, x3, #1
-    b       .L__clean_bss_loop_1
-
-.L__jump_to_entry:          /* jump to C code, should not return */
-    bl mmu_tcr_init
-
-    bl get_ttbrn_base
-    add x1, x0, #0x1000
-
-    msr ttbr0_el1, x0
-    msr ttbr1_el1, x1
-    dsb sy
-
-#ifdef RT_USING_SMART
-    ldr     x2, =_start
-    GET_PHY x3, _start
-    sub     x3, x3, x2
-#else
-    mov     x3,0
-#endif
+    b       .clean_bss_loop_byte
 
-    ldr x2, =0x10000000     /* map 256M memory for kernel space */
-    bl rt_hw_mem_setup_early
-
-    ldr x30, =after_mmu_enable  /* set LR to after_mmu_enable function, it's a v_addr */
-
-    mrs x1, sctlr_el1
-    bic x1, x1, #(3 << 3)    /* dis SA, SA0 */
-    bic x1, x1, #(1 << 1)    /* dis A */
-    orr x1, x1, #(1 << 12)   /* I */
-    orr x1, x1, #(1 << 2)    /* C */
-    orr x1, x1, #(1 << 0)    /* M */
-    msr sctlr_el1, x1        /* enable MMU */
-
-    dsb ish
-    isb
-    ic ialluis               /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */
-    dsb ish
-    isb
-    tlbi vmalle1             /* Invalidate all stage 1 translations used at EL1 with the current VMID */
-    dsb ish
-    isb
+.clean_bss_end:
     ret
 
-after_mmu_enable:
-#ifdef RT_USING_SMART
-    mrs x0, tcr_el1          /* disable ttbr0, only using kernel space */
-    orr x0, x0, #(1 << 7)
-    msr tcr_el1, x0
-    msr ttbr0_el1, xzr
-    dsb sy
-#endif
-
-    mov     x0, #1
-    msr     spsel, x0
-    adr     x1, .el_stack_top
-    mov     sp, x1           /* sp_el1 set to _start */
-
-#ifdef RT_USING_OFW
-    /* Save devicetree info */
-    mov     x0, dtb_paddr
-    bl      rt_hw_fdt_install_early
-#endif
-    b  rtthread_startup
-
-#ifdef RT_USING_SMP
-/**
- *  secondary cpu
- */
-
-.global _secondary_cpu_entry
-_secondary_cpu_entry:
-    bl      rt_hw_cpu_id_set
-    adr     x1, .el_stack_top
-
-    /* set up EL1 */
-    mrs     x0, CurrentEL           /* CurrentEL Register. bit 2, 3. Others reserved */
-    and     x0, x0, #12             /* clear reserved bits */
-
-    /* running at EL3? */
-    cmp     x0, #12                 /* 1100b. So, EL3 */
-    bne     .L__not_in_el3_cpux          /* 11?  !EL3 -> 5: */
-
-    /* should never be executed, just for completeness. (EL3) */
-    mov     x2, #0x5b1
-    msr     scr_el3, x2             /* SCR_ELn  Secure Configuration Register */
-    mov     x2, #0x3c9
-    msr     spsr_el3, x2            /* SPSR_ELn. Saved Program Status Register. 1111001001 */
-    adr     x2, .L__not_in_el3_cpux
-    msr     elr_el3, x2
-    eret                            /* Exception Return: from EL3, continue from .L__not_in_el3 */
-
-.L__not_in_el3_cpux:                     /* running at EL2 or EL1 */
-    cmp     x0, #4                  /* 0x04  0100 EL1 */
-    beq     .L__in_el1_cpux              /* EL1 -> 5: */
+init_cpu_stack_early:
+    msr     spsel, #1
+    mov     sp, stack_top
 
-    mrs     x0, hcr_el2
-    bic     x0, x0, #0xff
-    msr     hcr_el2, x0
-
-    msr     sp_el1, x1              /* in EL2, set sp of EL1 to _start */
+    ret
 
-    /* enable CNTP for EL1 */
-    mrs     x0, cnthctl_el2         /* Counter-timer Hypervisor Control register */
-    orr     x0, x0, #3
-    msr     cnthctl_el2, x0
-    msr     cntvoff_el2, xzr
+init_mmu_early:
+    get_phy x0, .early_page_array
+    bl      set_free_page
 
-    /* enable AArch64 in EL1 */
-    mov     x0, #(1 << 31)          /* AArch64 */
-    orr     x0, x0, #(1 << 1)       /* SWIO hardwired on Pi3 */
-    msr     hcr_el2, x0
-    mrs     x0, hcr_el2
+    get_phy x0, .early_tbl0_page
+    get_phy x1, .early_tbl1_page
 
-    /* change execution level to EL1 */
-    mov     x2, #0x3c4
-    msr     spsr_el2, x2            /* 1111000100 */
-    adr     x2, .L__in_el1_cpux
-    msr     elr_el2, x2
+    get_pvoff x2 x3
+    ldr     x2, =0x40000000         /* Map 1G memory for kernel space */
+    bl      rt_hw_mem_setup_early
 
-    eret                            /* exception return. from EL2. continue from .L__in_el1 */
+    b       enable_mmu_early
 
-.L__in_el1_cpux:
-    mrs     x0, tpidr_el1
-    /* each cpu init stack is 8k */
-    sub     x1, x1, x0, lsl #13
-    mov     sp, x1                  /* in EL1. Set sp to _start */
+enable_mmu_early:
+    get_phy x0, .early_tbl0_page
+    get_phy x1, .early_tbl1_page
 
-    /* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */
-    mov     x1, #0x00300000         /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
-    msr     cpacr_el1, x1
+    msr     ttbr0_el1, x0
+    msr     ttbr1_el1, x1
+    dsb     sy
 
-.L__jump_to_entry_cpux:                   /* jump to C code, should not return */
+    bl      mmu_tcr_init
 
-    /* init mmu early */
+    /*
+     * OK, now, we don't use sp before jump to kernel, set sp to current cpu's
+     * stack top to visual address
+     */
+    get_pvoff x1 x0
+    mov     x1, stack_top
+    sub     x1, x1, x0
+    mov     sp, x1
 
-    bl mmu_tcr_init
+    ldr     x30, =kernel_start      /* Set LR to kernel_start function, it's virtual addresses */
 
-    bl get_ttbrn_base
-    add x1, x0, #0x1000
+    mrs     x1, sctlr_el1
+    orr     x1, x1, #(1 << 2)       /* Cacheable Normal memory in stage1 */
+    orr     x1, x1, #(1 << 0)       /* MMU Enable */
+    msr     sctlr_el1, x1
 
-    msr ttbr0_el1, x0
-    msr ttbr1_el1, x1
-    dsb sy
+    dsb     ish
+    isb
 
-    ldr x30, =after_mmu_enable_cpux  /* set LR to after_mmu_enable function, it's a v_addr */
+    ic      ialluis     /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */
+    dsb     ish
+    isb
 
-    mrs x1, sctlr_el1
-    bic x1, x1, #(3 << 3)    /* dis SA, SA0 */
-    bic x1, x1, #(1 << 1)    /* dis A */
-    orr x1, x1, #(1 << 12)   /* I */
-    orr x1, x1, #(1 << 2)    /* C */
-    orr x1, x1, #(1 << 0)    /* M */
-    msr sctlr_el1, x1        /* enable MMU */
+    tlbi    vmalle1     /* Invalidate all stage 1 translations used at EL1 with the current VMID */
+    dsb     ish
+    isb
 
-    dsb sy
-    isb sy
-    ic ialluis               /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */
-    dsb sy
-    isb sy
-    tlbi vmalle1             /* Invalidate all stage 1 translations used at EL1 with the current VMID */
-    dsb sy
-    isb sy
     ret
 
-after_mmu_enable_cpux:
-#ifdef RT_USING_SMART
-    mrs x0, tcr_el1          /* disable ttbr0, only using kernel space */
-    orr x0, x0, #(1 << 7)
-    msr tcr_el1, x0
-    msr ttbr0_el1, xzr
-    dsb sy
-#endif
-
-    mov     x0, #1
-    msr     spsel, x0
-    mrs     x0, tpidr_el1
-    /* each cpu init stack is 8k */
-    adr     x1, .el_stack_top
-    sub     x1, x1, x0, lsl #13
-    mov     sp, x1                  /* in EL1. Set sp to _start */
-
-    b rt_hw_secondary_cpu_bsp_start
-#endif
-
-#ifndef RT_CPUS_NR
-#define RT_CPUS_NR 1
+/*
+ * CPU stack builtin
+ */
+    .section ".bss.noclean.cpus_stack"
+    .align 12
+.cpus_stack:
+#if defined(RT_USING_SMP) && RT_CPUS_NR > 1
+    .space (ARCH_SECONDARY_CPU_STACK_SIZE * (RT_CPUS_NR - 1))
+.secondary_cpu_stack_top:
 #endif
+    .space ARCH_SECONDARY_CPU_STACK_SIZE
+.boot_cpu_stack_top:
 
-.align 12
-.el_stack:
-.space (8192 * RT_CPUS_NR)
-.el_stack_top:
+/*
+ * Early page builtin
+ */
+    .section ".bss.noclean.early_page"
+    .align 12
+.early_tbl0_page:
+    .space ARCH_PAGE_SIZE
+.early_tbl1_page:
+    /* Map 4G -> 2M * 512 entries */
+    .space 4 * ARCH_PAGE_SIZE
+.early_page_array:
+    .space 24 * ARCH_PAGE_SIZE