diff options
| author | Meco Man <[email protected]> | 2021-03-27 17:51:56 +0800 |
|---|---|---|
| committer | Meco Man <[email protected]> | 2021-03-27 17:51:56 +0800 |
| commit | 6c907c3a477b1f34ca1adb277748c3306110cabf (patch) | |
| tree | 634037b92c323465d8151778d0a3eb1b04df2271 /libcpu/arm/cortex-m7 | |
| parent | 1ba020f3c89fbf2ac2a5b58424852e501fd59a91 (diff) | |
[libcpu] auto formatted
Diffstat (limited to 'libcpu/arm/cortex-m7')
| -rw-r--r-- | libcpu/arm/cortex-m7/cpu_cache.c | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m7/cpuport.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index 350b819c00..417558e285 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rtdef.h> #include <board.h> -/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) void rt_hw_cpu_icache_enable(void) diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index aeb9f14ac5..dbc42d21cf 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * |