Merge remote-tracking branch 'remotes/gitee/master'

22 files changed, 2308 insertions, 482 deletions

diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript
index 28af7ba651..10977eb3ec 100644
--- a/libcpu/arm/cortex-a/SConscript
+++ b/libcpu/arm/cortex-a/SConscript
@@ -5,9 +5,24 @@ from building import *
 Import('rtconfig')
 
 cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
+src     = Split('''
+cache.c
+cpu.c
+mmu.c
+stack.c
+''')
 CPPPATH = [cwd]
 
+if GetDepend('RT_USING_GIC_V2'):
+    src += ['interrupt.c']
+    src += ['gic.c']
+    src += ['trap.c']
+
+if GetDepend('RT_USING_GIC_V3'):
+    src += ['interrupt.c']
+    src += ['gicv3.c']
+    src += ['trap.c']
+
 if rtconfig.PLATFORM == 'armcc':
     src += Glob('*_rvds.S')
 
@@ -18,6 +33,9 @@ if rtconfig.PLATFORM == 'gcc':
 if rtconfig.PLATFORM == 'iar':
     src += Glob('*_iar.S')
 
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
 group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h
index f284bb5255..325d0ed0ae 100644
--- a/libcpu/arm/cortex-a/armv7.h
+++ b/libcpu/arm/cortex-a/armv7.h
@@ -69,4 +69,10 @@ struct rt_hw_stack
 #define E_Bit       (1<<9)
 #define J_Bit       (1<<24)
 
+#define PABT_EXCEPTION 0x1
+#define DABT_EXCEPTION 0x2
+#define UND_EXCEPTION  0x3
+#define SWI_EXCEPTION  0x4
+#define RESV_EXCEPTION 0xF
+
 #endif
diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c
index 0a7e702dbb..a6b59182a6 100644
--- a/libcpu/arm/cortex-a/cache.c
+++ b/libcpu/arm/cortex-a/cache.c
@@ -58,6 +58,37 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
     asm volatile ("dsb":::"memory");
 }
 
+void rt_hw_cpu_dcache_inv_range(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_dcache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t)addr + size;
+
+    asm volatile ("dmb":::"memory");
+
+    if ((start_addr & (line_size - 1)) != 0)
+    {
+        start_addr &= ~(line_size - 1);
+        asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(start_addr));
+        start_addr += line_size;
+        asm volatile ("dsb":::"memory");
+    }
+
+    if ((end_addr & (line_size - 1)) != 0)
+    {
+        end_addr &= ~(line_size - 1);
+        asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(end_addr));
+        asm volatile ("dsb":::"memory");
+    }
+
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr));  /* dcimvac */
+        start_addr += line_size;
+    }
+    asm volatile ("dsb":::"memory");
+}
+
 void rt_hw_cpu_dcache_clean(void *addr, int size)
 {
     rt_uint32_t line_size = rt_cpu_dcache_line_size();
@@ -75,6 +106,23 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
     asm volatile ("dsb":::"memory");
 }
 
+void rt_hw_cpu_dcache_clean_inv(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_dcache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
+
+    asm volatile ("dmb":::"memory");
+    start_addr &= ~(line_size-1);
+    end_addr &= ~(line_size-1);
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(start_addr));
+        start_addr += line_size;
+    }
+    asm volatile ("dsb":::"memory");
+}
+
 void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
 {
     if (ops == RT_HW_CACHE_INVALIDATE)
diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h
index 6896fd9f71..2bf91ac5ad 100644
--- a/libcpu/arm/cortex-a/cp15.h
+++ b/libcpu/arm/cortex-a/cp15.h
@@ -15,8 +15,7 @@
 #define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
 #define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
 
-unsigned long rt_cpu_get_smp_id(void);
-
+int rt_hw_cpu_id(void);
 void rt_cpu_mmu_disable(void);
 void rt_cpu_mmu_enable(void);
 void rt_cpu_tlb_set(volatile unsigned long*);
diff --git a/libcpu/arm/cortex-a/cp15_gcc.S b/libcpu/arm/cortex-a/cp15_gcc.S
index dd2436ffee..983ae522ef 100644
--- a/libcpu/arm/cortex-a/cp15_gcc.S
+++ b/libcpu/arm/cortex-a/cp15_gcc.S
@@ -8,9 +8,11 @@
  * 2013-07-05     Bernard      the first version
  */
 
-.globl rt_cpu_get_smp_id
-rt_cpu_get_smp_id:
-    mrc     p15, #0, r0, c0, c0, #5
+.weak rt_hw_cpu_id
+rt_hw_cpu_id:
+    mrc     p15, #0, r0, c0, c0, #5         @ read multiprocessor affinity register
+    ldr     r1, =0xFFFF03                   @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2
+    and     r0, r0, r1
     bx      lr
 
 .globl rt_cpu_vector_set_base
diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c
index 9555e01e9c..c95c58a13c 100644
--- a/libcpu/arm/cortex-a/cpu.c
+++ b/libcpu/arm/cortex-a/cpu.c
@@ -15,17 +15,6 @@
 
 #ifdef RT_USING_SMP
 
-int rt_hw_cpu_id(void)
-{
-    int cpu_id;
-    __asm__ volatile (
-            "mrc p15, 0, %0, c0, c0, 5"
-            :"=r"(cpu_id)
-            );
-    cpu_id &= 0xf;
-    return cpu_id;
-};
-
 void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
 {
     lock->slock = 0;
@@ -86,4 +75,21 @@ RT_WEAK void rt_hw_cpu_shutdown()
     }
 }
 
+#ifdef RT_USING_CPU_FFS
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+int __rt_ffs(int value)
+{
+    return __builtin_ffs(value);
+}
+#endif
+
 /*@}*/
diff --git a/libcpu/arm/cortex-a/gicv3.c b/libcpu/arm/cortex-a/gicv3.c
new file mode 100644
index 0000000000..a3fb0e767b
--- /dev/null
+++ b/libcpu/arm/cortex-a/gicv3.c
@@ -0,0 +1,708 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ * 2018-11-22     Jesven       add rt_hw_ipi_send()
+ *                             add rt_hw_ipi_handler_install()
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "gicv3.h"
+#include "cp15.h"
+
+#ifndef RT_CPUS_NR
+#define RT_CPUS_NR 1
+#endif
+
+struct arm_gic_v3
+{
+    rt_uint32_t offset;                     /* the first interrupt index in the vector table */
+    rt_uint32_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */
+    rt_uint32_t dist_hw_base;               /* the base address of the gic distributor */
+    rt_uint32_t cpu_hw_base[RT_CPUS_NR];    /* the base addrees of the gic cpu interface */
+};
+
+/* 'ARM_GIC_MAX_NR' is the number of cores */
+static struct arm_gic_v3 _gic_table[ARM_GIC_MAX_NR];
+static unsigned int _gic_max_irq;
+
+/**
+ * @name: arm_gic_cpumask_to_affval
+ * @msg:
+ * @in param cpu_mask:
+ * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23]
+ * @out param target_list:  Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the
+ *                          PE within a cluster with an Affinity 0 value equal to the bit number.
+ * @return {rt_uint32_t} 0 is finish , 1 is data valid
+ */
+RT_WEAK rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list)
+{
+    return 0;
+}
+
+RT_WEAK rt_uint64_t get_main_cpu_affval(void)
+{
+    return 0;
+}
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    __get_gicv3_reg(ICC_IAR1, irq);
+
+    irq = (irq & 0x1FFFFFF) + _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+    RT_ASSERT(irq >= 0U);
+
+    __asm__ volatile("dsb 0xF" ::
+                         : "memory");
+    __set_gicv3_reg(ICC_EOIR1, irq);
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1U << (irq % 32U);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    if (irq < 32U)
+    {
+        rt_int32_t cpu_id = rt_hw_cpu_id();
+        RT_ASSERT((cpu_id) < RT_CPUS_NR);
+        GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask;
+    }
+    else
+    {
+        GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    }
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1U << (irq % 32U);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    if (irq < 32U)
+    {
+        rt_int32_t cpu_id = rt_hw_cpu_id();
+        RT_ASSERT((cpu_id) < RT_CPUS_NR);
+        GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask;
+    }
+    else
+    {
+        GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+    }
+}
+
+rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq)
+{
+    rt_uint32_t pend;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    if (irq >= 16U)
+    {
+        pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+    }
+    else
+    {
+        /* INTID 0-15 Software Generated Interrupt */
+        pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
+        /* No CPU identification offered */
+        if (pend != 0U)
+        {
+            pend = 1U;
+        }
+        else
+        {
+            pend = 0U;
+        }
+    }
+
+    return (pend);
+}
+
+void arm_gic_set_pending_irq(rt_uint32_t index, int irq)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    if (irq >= 16U)
+    {
+        GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U);
+    }
+    else
+    {
+        /* INTID 0-15 Software Generated Interrupt */
+        /* Forward the interrupt to the CPU interface that requested it */
+        GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U);
+    }
+}
+
+void arm_gic_clear_pending_irq(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    if (irq >= 16U)
+    {
+        mask = 1U << (irq % 32U);
+        GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    }
+    else
+    {
+        mask = 1U << ((irq % 4U) * 8U);
+        GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask;
+    }
+}
+
+void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config)
+{
+    rt_uint32_t icfgr;
+    rt_uint32_t shift;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq);
+    shift = (irq % 16U) << 1U;
+
+    icfgr &= (~(3U << shift));
+    icfgr |= (config << shift);
+
+    GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr;
+}
+
+rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U));
+}
+
+void arm_gic_clear_active(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1U << (irq % 32U);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+/* Set up the cpu mask for the specific interrupt */
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U));
+    old_tgt |= cpumask << ((irq % 4U) * 8U);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
+}
+
+void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority)
+{
+    rt_uint32_t mask;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    if (irq < 32U)
+    {
+        rt_int32_t cpu_id = rt_hw_cpu_id();
+        RT_ASSERT((cpu_id) < RT_CPUS_NR);
+
+        mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq);
+        mask &= ~(0xFFUL << ((irq % 4U) * 8U));
+        mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U));
+        GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask;
+    }
+    else
+    {
+        mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq);
+        mask &= ~(0xFFUL << ((irq % 4U) * 8U));
+        mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U));
+        GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask;
+    }
+}
+
+rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    if (irq < 32U)
+    {
+        rt_int32_t cpu_id = rt_hw_cpu_id();
+
+        RT_ASSERT((cpu_id) < RT_CPUS_NR);
+        return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
+    }
+    else
+    {
+        return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
+    }
+}
+
+void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    value &= 0xFFUL;
+    /* set priority mask */
+    __set_gicv3_reg(ICC_SRE, value);
+    __asm__ volatile ("isb 0xF"::
+                        :"memory");
+}
+
+rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+    rt_uint32_t value;
+
+    __get_gicv3_reg(ICC_SRE, value);
+    return value;
+}
+
+void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    priority &= 0xFFUL;
+    /* set priority mask */
+    __set_gicv3_reg(ICC_PMR, priority);
+}
+
+rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+    rt_uint32_t priority;
+
+    __get_gicv3_reg(ICC_PMR, priority);
+    return priority;
+}
+
+void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point)
+{
+    index = index;
+    binary_point &= 0x7U;
+
+    __set_gicv3_reg(ICC_BPR1, binary_point);
+}
+
+rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index)
+{
+    rt_uint32_t binary_point;
+
+    index = index;
+    __get_gicv3_reg(ICC_BPR1, binary_point);
+    return binary_point;
+}
+
+rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq)
+{
+    rt_uint32_t pending;
+    rt_uint32_t active;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+    pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+
+    return ((active << 1U) | pending);
+}
+
+void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode)
+{
+    rt_uint64_t sgi_val;
+
+    if (routing_mode)
+    {
+        sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self".
+        /*  Write the ICC_SGI1R registers */
+        __asm__ volatile("dsb 0xF" ::
+                            : "memory");
+        __set_cp64(15, 0, sgi_val, 12);
+        __asm__ volatile("isb 0xF" ::
+                            : "memory");
+    }
+    else
+    {
+        rt_uint32_t cluster_id, target_list;
+        while (arm_gic_cpumask_to_affval(&cpu_mask, &cluster_id, &target_list))
+        {
+            sgi_val = ((irq & 0x0FULL) << 24 |
+                       target_list |
+                       ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET |
+                       ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET |
+                       ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET);
+
+            __asm__ volatile("dsb 0xF" ::
+                                : "memory");
+            __set_cp64(15, 0, sgi_val, 12);
+            __asm__ volatile("isb 0xF" ::
+                                : "memory");
+        }
+    }
+}
+
+rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index)
+{
+    rt_uint32_t irq;
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    index = index;
+    __get_gicv3_reg(ICC_HPPIR1, irq);
+    return irq;
+}
+
+rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base);
+}
+
+void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group)
+{
+    uint32_t igroupr;
+    uint32_t shift;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+    RT_ASSERT(group <= 1U);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq);
+    shift = (irq % 32U);
+    igroupr &= (~(1U << shift));
+    igroupr |= ((group & 0x1U) << shift);
+
+    GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr;
+}
+
+rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0U);
+
+    return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+}
+
+static int arm_gicv3_wait_rwp(rt_uint32_t index, rt_uint32_t irq)
+{
+    rt_uint32_t rwp_bit;
+    rt_uint32_t base;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    if (irq < 32u)
+    {
+        rt_int32_t cpu_id = rt_hw_cpu_id();
+
+        RT_ASSERT((cpu_id) < RT_CPUS_NR);
+        base = _gic_table[index].redist_hw_base[cpu_id];
+        rwp_bit = GICR_CTLR_RWP;
+    }
+    else
+    {
+        base = _gic_table[index].dist_hw_base;
+        rwp_bit = GICD_CTLR_RWP;
+    }
+
+    while (__REG32(base) & rwp_bit)
+    {
+        ;
+    }
+
+    return 0;
+}
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    rt_uint64_t cpu0_affval;
+    unsigned int gic_type, i;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020U)
+        _gic_max_irq = 1020U;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+    GIC_DIST_CTRL(dist_base) = 0x0U;
+    /* Wait for register write pending */
+    arm_gicv3_wait_rwp(0, 32);
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32U; i < _gic_max_irq; i += 16U)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0U;
+
+    arm_gicv3_wait_rwp(0, 32);
+
+    cpu0_affval = get_main_cpu_affval();
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32U; i < _gic_max_irq; i++)
+    {
+        GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval;
+        GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32;
+    }
+
+    arm_gicv3_wait_rwp(0, 32);
+
+    /* Set priority on spi interrupts. */
+    for (i = 32U; i < _gic_max_irq; i += 4U)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U;
+
+    arm_gicv3_wait_rwp(0, 32);
+    /* Disable all interrupts. */
+    for (i = 0U; i < _gic_max_irq; i += 32U)
+    {
+        GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU;
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU;
+    }
+
+    arm_gicv3_wait_rwp(0, 32);
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0U; i < _gic_max_irq; i += 32U)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU;
+
+    arm_gicv3_wait_rwp(0, 32);
+
+    /*
+            The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode.
+            Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled.
+            If affinity routing is not enabled, GICv3 can be configured for legacy operation.
+            Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state.
+            Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1:
+            GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts.
+            GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts.
+            GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts.
+      */
+    GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS;
+
+    return 0;
+}
+
+int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+    RT_ASSERT((cpu_id) < RT_CPUS_NR);
+    _gic_table[index].redist_hw_base[cpu_id] = redist_addr;
+
+    return 0;
+}
+
+int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+    RT_ASSERT((cpu_id) < RT_CPUS_NR);
+    _gic_table[index].cpu_hw_base[cpu_id] = interface_addr;
+
+    return 0;
+}
+
+int arm_gic_redist_init(rt_uint32_t index)
+{
+    unsigned int i;
+    rt_uint32_t base;
+    rt_int32_t cpu_id = rt_hw_cpu_id();
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+    RT_ASSERT((cpu_id) < RT_CPUS_NR);
+
+    base = _gic_table[index].redist_hw_base[cpu_id];
+    /* redistributor enable */
+    GIC_RDIST_WAKER(base) &= ~(1U << 1);
+    while (GIC_RDIST_WAKER(base) & (1 << 2))
+    {
+        ;
+    }
+
+    /* Disable all sgi and ppi interrupt */
+    GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF;
+    arm_gicv3_wait_rwp(0, 0);
+
+    /* Clear all inetrrupt pending */
+    GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF;
+
+    /* the corresponding interrupt is Group 1 or Non-secure Group 1. */
+    GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF;
+    GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF;
+
+    /* Configure default priorities for SGI 0:15 and PPI 16:31. */
+    for (i = 0; i < 32; i += 4)
+    {
+        GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U;
+    }
+
+    /* Trigger level for PPI interrupts*/
+    GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive.
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index)
+{
+    rt_uint32_t value;
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    value = arm_gic_get_system_register_enable_mask(index);
+    value |= (1U << 0);
+    arm_gic_set_system_register_enable_mask(index, value);
+    __set_gicv3_reg(ICC_CTLR, 0);
+
+    arm_gic_set_interface_prior_mask(index, 0xFFU);
+
+    /* Enable group1 interrupt */
+    value = 0x1U;
+    __set_gicv3_reg(ICC_IGRPEN1, value);
+
+    arm_gic_set_binary_point(0, 0);
+
+    /* ICC_BPR0_EL1 determines the preemption group for both
+       Group 0 and Group 1 interrupts.
+       */
+    value = 0x1U;
+    __set_gicv3_reg(ICC_CTLR, value);
+
+    return 0;
+}
+
+#ifdef RT_USING_SMP
+void arm_gic_secondary_cpu_init(void)
+{
+    arm_gic_redist_init(0);
+
+    arm_gic_cpu_init(0);
+}
+#endif
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1U << 10U) ? "has" : "no",
+               gic_type);
+}
+
+void arm_gic_dump(rt_uint32_t index)
+{
+    unsigned int i, k;
+
+    k = arm_gic_get_high_pending_irq(0);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0U; i < _gic_max_irq / 32U; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32U));
+    }
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0U; i < _gic_max_irq / 32U; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32U));
+    }
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0U; i < _gic_max_irq / 32U; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32U));
+    }
+    rt_kprintf("\n");
+}
+
+long gic_dump(void)
+{
+    arm_gic_dump_type(0);
+    arm_gic_dump(0);
+
+    return 0;
+}
+MSH_CMD_EXPORT(gic_dump, show gic status);
diff --git a/libcpu/arm/cortex-a/gicv3.h b/libcpu/arm/cortex-a/gicv3.h
new file mode 100644
index 0000000000..813a4f4c8d
--- /dev/null
+++ b/libcpu/arm/cortex-a/gicv3.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_V3_H__
+#define __GIC_V3_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR  \
+                                                 : "=r"(Rt) \
+                                                 :          \
+                                                 : "memory")
+#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \
+                                                 :         \
+                                                 : "r"(Rt) \
+                                                 : "memory")
+
+
+/* AArch32 System register interface to GICv3 */
+#define ICC_IAR0    "p15, 0, %0, c12, c8, 0"
+#define ICC_IAR1    "p15, 0, %0, c12, c12, 0"
+#define ICC_EOIR0   "p15, 0, %0, c12, c8, 1"
+#define ICC_EOIR1   "p15, 0, %0, c12, c12, 1"
+#define ICC_HPPIR0  "p15, 0, %0, c12, c8, 2"
+#define ICC_HPPIR1  "p15, 0, %0, c12, c12, 2"
+#define ICC_BPR0    "p15, 0, %0, c12, c8, 3"
+#define ICC_BPR1    "p15, 0, %0, c12, c12, 3"
+#define ICC_DIR     "p15, 0, %0, c12, c11, 1"
+#define ICC_PMR     "p15, 0, %0, c4, c6, 0"
+#define ICC_RPR     "p15, 0, %0, c12, c11, 3"
+#define ICC_CTLR    "p15, 0, %0, c12, c12, 4"
+#define ICC_MCTLR   "p15, 6, %0, c12, c12, 4"
+#define ICC_SRE     "p15, 0, %0, c12, c12, 5"
+#define ICC_HSRE    "p15, 4, %0, c12, c9, 5"
+#define ICC_MSRE    "p15, 6, %0, c12, c12, 5"
+#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
+#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
+#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7"
+
+#define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x)))
+
+#define ROUTED_TO_ALL (1)
+#define ROUTED_TO_SPEC (0)
+
+/** Macro to access the Distributor Control Register (GICD_CTLR)
+*/
+#define GICD_CTLR_RWP (1<<31)
+#define GICD_CTLR_E1NWF (1<<7)
+#define GICD_CTLR_DS (1<<6)
+#define GICD_CTLR_ARE_NS (1<<5)
+#define GICD_CTLR_ARE_S (1<<4)
+#define GICD_CTLR_ENGRP1S (1<<2)
+#define GICD_CTLR_ENGRP1NS (1<<1)
+#define GICD_CTLR_ENGRP0 (1<<0)
+
+/** Macro to access the Redistributor Control Register (GICR_CTLR)
+*/
+#define GICR_CTLR_UWP (1<<31)
+#define GICR_CTLR_DPG1S (1<<26)
+#define GICR_CTLR_DPG1NS (1<<25)
+#define GICR_CTLR_DPG0 (1<<24)
+#define GICR_CTLR_RWP (1<<3)
+#define GICR_CTLR_IR (1<<2)
+#define GICR_CTLR_CES (1<<1)
+#define GICR_CTLR_EnableLPI (1<<0)
+
+/** Macro to access the Generic Interrupt Controller Interface (GICC)
+*/
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00U)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04U)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08U)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0cU)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10U)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14U)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18U)
+#define GIC_CPU_IIDR(hw_base)               __REG32((hw_base) + 0xFCU)
+
+/** Macro to access the Generic Interrupt Controller Distributor (GICD)
+*/
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000U)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004U)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00U)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
+#define GIC_DIST_SPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8U)
+#define GIC_DIST_IROUTER_LOW(hw_base, n)    __REG32((hw_base) + 0x6000U + (n)*8U)
+#define GIC_DIST_IROUTER_HIGH(hw_base, n)   __REG32((hw_base) + 0x6000U + (n)*8U + 4)
+
+/* SGI base address  is at 64K offset from Redistributor base address */
+#define GIC_RSGI_OFFSET 0x10000
+
+/** Macro to access the Generic Interrupt Controller Redistributor (GICD)
+*/
+#define GIC_RDIST_CTRL(hw_base)              __REG32((hw_base) + 0x000U)
+#define GIC_RDIST_IIDR(hw_base)              __REG32((hw_base) + 0x004U)
+#define GIC_RDIST_TYPER(hw_base)             __REG32((hw_base) + 0x008U)
+#define GIC_RDIST_TSTATUSR(hw_base)          __REG32((hw_base) + 0x010U)
+#define GIC_RDIST_WAKER(hw_base)             __REG32((hw_base) + 0x014U)
+#define GIC_RDIST_SETLPIR(hw_base)           __REG32((hw_base) + 0x040U)
+#define GIC_RDIST_CLRLPIR(hw_base)           __REG32((hw_base) + 0x048U)
+#define GIC_RDIST_PROPBASER(hw_base)         __REG32((hw_base) + 0x070U)
+#define GIC_RDIST_PENDBASER(hw_base)         __REG32((hw_base) + 0x078U)
+#define GIC_RDIST_INVLPIR(hw_base)           __REG32((hw_base) + 0x0A0U)
+#define GIC_RDIST_INVALLR(hw_base)           __REG32((hw_base) + 0x0B0U)
+#define GIC_RDIST_SYNCR(hw_base)             __REG32((hw_base) + 0x0C0U)
+
+#define GIC_RDISTSGI_IGROUPR0(hw_base, n)    __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U)
+#define GIC_RDISTSGI_ISENABLER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U)
+#define GIC_RDISTSGI_ICENABLER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U)
+#define GIC_RDISTSGI_ISPENDR0(hw_base)       __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U)
+#define GIC_RDISTSGI_ICPENDR0(hw_base)       __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U)
+#define GIC_RDISTSGI_ISACTIVER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U)
+#define GIC_RDISTSGI_ICACTIVER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U)
+#define GIC_RDISTSGI_IPRIORITYR(hw_base, n)  __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U)
+#define GIC_RDISTSGI_ICFGR0(hw_base)         __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U)
+#define GIC_RDISTSGI_ICFGR1(hw_base)         __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U)
+#define GIC_RDISTSGI_IGRPMODR0(hw_base, n)   __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4)
+#define GIC_RDISTSGI_NSACR(hw_base)          __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U)
+
+#define GIC_RSGI_AFF1_OFFSET    16
+#define GIC_RSGI_AFF2_OFFSET    32
+#define GIC_RSGI_AFF3_OFFSET    48
+
+rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list);
+rt_uint64_t get_main_cpu_affval(void);
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+
+rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
+void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
+void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
+
+void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config);
+rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
+
+void arm_gic_clear_active(rt_uint32_t index, int irq);
+
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq);
+
+void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority);
+rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq);
+
+void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority);
+rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index);
+
+void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point);
+rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
+
+rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq);
+
+void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode);
+rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index);
+
+rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
+
+void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group);
+rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq);
+
+int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id);
+int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id);
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index);
+int arm_gic_redist_init(rt_uint32_t index);
+
+void arm_gic_dump_type(rt_uint32_t index);
+void arm_gic_dump(rt_uint32_t index);
+
+void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value);
+rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index);
+void arm_gic_secondary_cpu_init(void);
+#endif
+
diff --git a/libcpu/arm/cortex-a/gtimer.c b/libcpu/arm/cortex-a/gtimer.c
deleted file mode 100644
index b193a1593d..0000000000
--- a/libcpu/arm/cortex-a/gtimer.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-03-30     huijie.feng  first version
- */
-
-#include "cp15.h"
-#include <rtdef.h>
-
-/** Set CNTFRQ
- *  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
- *  @param value: CNTFRQ Register value to set
- */
-static inline void __set_cntfrq(rt_uint32_t value)
-{
-    __set_cp(15, 0, value, 14, 0, 0);
-}
-
-/** Get CNTFRQ
- *  This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
- *  return CNTFRQ Register value
- */
-static inline rt_uint32_t __get_cntfrq(void)
-{
-    rt_uint32_t result;
-    __get_cp(15, 0, result, 14, 0 , 0);
-    return result;
-}
-
-/** Set CNTP_TVAL
- *  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
- *  param value: CNTP_TVAL Register value to set
- */
-static inline void __set_cntp_tval(rt_uint32_t value)
-{
-    __set_cp(15, 0, value, 14, 2, 0);
-}
-
-/** Get CNTP_TVAL
- *  This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
- *  return CNTP_TVAL Register value
- */
-static inline rt_uint32_t __get_cntp_tval(void)
-{
-    rt_uint32_t result;
-    __get_cp(15, 0, result, 14, 2, 0);
-    return result;
-}
-
-/** Get CNTPCT
- *  This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
- *  return CNTPCT Register value
- */
-static inline rt_uint64_t __get_cntpct(void)
-{
-    rt_uint64_t result;
-    __get_cp64(15, 0, result, 14);
-    return result;
-}
-
-/** Set CNTP_CVAL
- *  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
- *  param value: CNTP_CVAL Register value to set
-*/
-static inline void __set_cntp_cval(rt_uint64_t value)
-{
-    __set_cp64(15, 2, value, 14);
-}
-
-/** Get CNTP_CVAL
- *  This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
- *  return CNTP_CVAL Register value
- */
-static inline rt_uint64_t __get_cntp_cval(void)
-{
-    rt_uint64_t result;
-    __get_cp64(15, 2, result, 14);
-    return result;
-}
-
-/** Set CNTP_CTL
- *  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
- *  param value: CNTP_CTL Register value to set
- */
-static inline void __set_cntp_ctl(uint32_t value)
-{
-    __set_cp(15, 0, value, 14, 2, 1);
-}
-
-/** Get CNTP_CTL register
- *  return CNTP_CTL Register value
- */
-static inline rt_uint32_t __get_cntp_ctl(void)
-{
-    rt_uint32_t result;
-    __get_cp(15, 0, result, 14, 2, 1);
-    return result;
-}
-
-/** Configures the frequency the timer shall run at.
- *  param value The timer frequency in Hz.
- */
-void gtimer_set_counter_frequency(rt_uint32_t value)
-{
-    __set_cntfrq(value);
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-/** Sets the reset value of the timer.
- *  param value: The value the timer is loaded with.
- */
-void gtimer_set_load_value(rt_uint32_t value)
-{
-    __set_cntp_tval(value);
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-/** Get the current counter value.
- *  return Current counter value.
- */
-rt_uint32_t gtimer_get_current_value(void)
-{
-    return(__get_cntp_tval());
-}
-
-/** Get the current physical counter value.
- *  return Current physical counter value.
- */
-rt_uint64_t gtimer_get_current_physical_value(void)
-{
-    return(__get_cntpct());
-}
-
-/** Set the physical compare value.
- *  param value: New physical timer compare value.
- */
-void gtimer_set_physical_compare_value(rt_uint64_t value)
-{
-    __set_cntp_cval(value);
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-/** Get the physical compare value.
- *  return Physical compare value.
- */
-rt_uint64_t gtimer_get_physical_compare_value(void)
-{
-    return(__get_cntp_cval());
-}
-
-/** Configure the timer by setting the control value.
- *  param value: New timer control value.
- */
-void gtimer_set_control(rt_uint32_t value)
-{
-    __set_cntp_ctl(value);
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-/** Get the control value.
- *  return Control value.
- */
-rt_uint32_t gtimer_get_control(void)
-{
-    return(__get_cntp_ctl());
-}
-
diff --git a/libcpu/arm/cortex-a/gtimer.h b/libcpu/arm/cortex-a/gtimer.h
deleted file mode 100644
index 160d0cefde..0000000000
--- a/libcpu/arm/cortex-a/gtimer.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-03-30     huijie.feng  first version
- */
-
-#ifndef __GTIMER_H__
-#define __GTIMER_H__
-
-#include <rtdef.h>
-
-void gtimer_set_counter_frequency(rt_uint32_t value);
-void gtimer_set_load_value(rt_uint32_t value);
-rt_uint32_t gtimer_get_current_value(void);
-rt_uint64_t gtimer_get_current_physical_value(void);
-void gtimer_set_physical_compare_value(rt_uint64_t value);
-rt_uint64_t gtimer_get_physical_compare_value(void);
-void gtimer_set_control(rt_uint32_t value);
-rt_uint32_t gtimer_get_control(void);
-
-#endif
-
diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c
index 65e51fa3ae..f90f1c0094 100644
--- a/libcpu/arm/cortex-a/interrupt.c
+++ b/libcpu/arm/cortex-a/interrupt.c
@@ -12,8 +12,12 @@
 #include <rthw.h>
 #include <rtthread.h>
 #include "interrupt.h"
-#include "gic.h"
 
+#ifdef RT_USING_GIC_V2
+#include "gic.h"
+#else
+#include "gicv3.h"
+#endif
 
 /* exception and interrupt handler table */
 struct rt_irq_desc isr_table[MAX_HANDLERS];
@@ -23,6 +27,20 @@ struct rt_irq_desc isr_table[MAX_HANDLERS];
 rt_uint32_t rt_interrupt_from_thread        = 0;
 rt_uint32_t rt_interrupt_to_thread          = 0;
 rt_uint32_t rt_thread_switch_interrupt_flag = 0;
+
+#ifdef RT_USING_HOOK
+static void (*rt_interrupt_switch_hook)(void);
+
+void rt_interrupt_switch_sethook(void (*hook)(void))
+{
+    rt_interrupt_switch_hook = hook;
+}
+#endif
+
+void rt_interrupt_hook(void)
+{
+    RT_OBJECT_HOOK_CALL(rt_interrupt_switch_hook, ());
+}
 #endif
 
 const unsigned int VECTOR_BASE = 0x00;
@@ -34,6 +52,7 @@ void rt_hw_vector_init(void)
     rt_cpu_vector_set_base((unsigned int)&system_vectors);
 }
 
+#ifdef RT_USING_GIC_V2
 /**
  * This function will initialize hardware interrupt
  */
@@ -58,6 +77,33 @@ void rt_hw_interrupt_init(void)
     arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
     arm_gic_cpu_init(0, gic_cpu_base);
 }
+#else
+/**
+ * This function will initialize hardware interrupt
+ * Called by the primary cpu(cpu0)
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t gic_dist_base;
+    rt_uint32_t gic_irq_start;
+
+    /* initialize vector table */
+    rt_hw_vector_init();
+
+    /* initialize exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+    /* initialize ARM GIC */
+    gic_dist_base = platform_get_gic_dist_base();
+    gic_irq_start = GIC_IRQ_START;
+
+    arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
+
+    arm_gic_cpu_init(0);
+    arm_gic_redist_init(0);
+}
+
+#endif
 
 /**
  * This function will mask a interrupt.
@@ -245,7 +291,7 @@ unsigned int rt_hw_interrupt_get_prior_group_bits(void)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
+                                         void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 
@@ -269,7 +315,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 #ifdef RT_USING_SMP
 void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
 {
+#ifdef RT_USING_GIC_V2
     arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
+#else
+    arm_gic_send_affinity_sgi(0, ipi_vector, cpu_mask, ROUTED_TO_SPEC);
+#endif
 }
 
 void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c
deleted file mode 100644
index 2b9165cc8b..0000000000
--- a/libcpu/arm/cortex-a/pmu.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#include <rtthread.h>
-#include "pmu.h"
-
-void rt_hw_pmu_dump_feature(void)
-{
-    unsigned long reg;
-
-    reg = rt_hw_pmu_get_control();
-    rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n",
-               reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f);
-    RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f));
-}
diff --git a/libcpu/arm/cortex-a/pmu.h b/libcpu/arm/cortex-a/pmu.h
deleted file mode 100644
index 64a74b5d39..0000000000
--- a/libcpu/arm/cortex-a/pmu.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __PMU_H__
-#define __PMU_H__
-
-#include "board.h"
-
-/* Number of counters */
-#define ARM_PMU_CNTER_NR 4
-
-enum rt_hw_pmu_event_type {
-    ARM_PMU_EVENT_PMNC_SW_INCR      = 0x00,
-    ARM_PMU_EVENT_L1_ICACHE_REFILL  = 0x01,
-    ARM_PMU_EVENT_ITLB_REFILL       = 0x02,
-    ARM_PMU_EVENT_L1_DCACHE_REFILL  = 0x03,
-    ARM_PMU_EVENT_L1_DCACHE_ACCESS  = 0x04,
-    ARM_PMU_EVENT_DTLB_REFILL       = 0x05,
-    ARM_PMU_EVENT_MEM_READ          = 0x06,
-    ARM_PMU_EVENT_MEM_WRITE         = 0x07,
-    ARM_PMU_EVENT_INSTR_EXECUTED    = 0x08,
-    ARM_PMU_EVENT_EXC_TAKEN         = 0x09,
-    ARM_PMU_EVENT_EXC_EXECUTED      = 0x0A,
-    ARM_PMU_EVENT_CID_WRITE         = 0x0B,
-};
-
-/* Enable bit */
-#define ARM_PMU_PMCR_E   (0x01 << 0)
-/* Event counter reset */
-#define ARM_PMU_PMCR_P   (0x01 << 1)
-/* Cycle counter reset */
-#define ARM_PMU_PMCR_C   (0x01 << 2)
-/* Cycle counter divider */
-#define ARM_PMU_PMCR_D   (0x01 << 3)
-
-#ifdef __GNUC__
-rt_inline void rt_hw_pmu_enable_cnt(int divide64)
-{
-    unsigned long pmcr;
-    unsigned long pmcntenset;
-
-    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C;
-    if (divide64)
-        pmcr |= ARM_PMU_PMCR_D;
-    else
-        pmcr &= ~ARM_PMU_PMCR_D;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
-
-    /* enable all the counters */
-    pmcntenset = ~0;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset));
-    /* clear overflows(just in case) */
-    asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset));
-}
-
-rt_inline unsigned long rt_hw_pmu_get_control(void)
-{
-    unsigned long pmcr;
-    asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    return pmcr;
-}
-
-rt_inline unsigned long rt_hw_pmu_get_ceid(void)
-{
-    unsigned long reg;
-    /* only PMCEID0 is supported, PMCEID1 is RAZ. */
-    asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg));
-    return reg;
-}
-
-rt_inline unsigned long rt_hw_pmu_get_cnten(void)
-{
-    unsigned long pmcnt;
-    asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt));
-    return pmcnt;
-}
-
-rt_inline void rt_hw_pmu_reset_cycle(void)
-{
-    unsigned long pmcr;
-
-    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    pmcr |= ARM_PMU_PMCR_C;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
-    asm volatile ("isb");
-}
-
-rt_inline void rt_hw_pmu_reset_event(void)
-{
-    unsigned long pmcr;
-
-    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    pmcr |= ARM_PMU_PMCR_P;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
-    asm volatile ("isb");
-}
-
-rt_inline unsigned long rt_hw_pmu_get_cycle(void)
-{
-    unsigned long cyc;
-    asm volatile ("isb");
-    asm volatile ("mrc  p15, 0, %0, c9, c13, 0" : "=r"(cyc));
-    return cyc;
-}
-
-rt_inline void rt_hw_pmu_select_counter(int idx)
-{
-    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
-
-    asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx));
-    /* Linux add an isb here, don't know why here. */
-    asm volatile ("isb");
-}
-
-rt_inline void rt_hw_pmu_select_event(int idx,
-                                      enum rt_hw_pmu_event_type eve)
-{
-    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
-
-    rt_hw_pmu_select_counter(idx);
-    asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve));
-}
-
-rt_inline unsigned long rt_hw_pmu_read_counter(int idx)
-{
-    unsigned long reg;
-
-    rt_hw_pmu_select_counter(idx);
-    asm volatile ("isb");
-    asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg));
-    return reg;
-}
-
-rt_inline unsigned long rt_hw_pmu_get_ovsr(void)
-{
-    unsigned long reg;
-    asm volatile ("isb");
-    asm ("mrc  p15, 0, %0, c9, c12, 3" : "=r"(reg));
-    return reg;
-}
-
-rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg)
-{
-    asm ("mcr  p15, 0, %0, c9, c12, 3" : : "r"(reg));
-    asm volatile ("isb");
-}
-
-#endif
-
-void rt_hw_pmu_dump_feature(void);
-
-#endif /* end of include guard: __PMU_H__ */
-
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 2e99db7218..908468476e 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -22,21 +22,27 @@
 .equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
 .equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
 
-#ifdef RT_USING_FPU
 .equ UND_Stack_Size,     0x00000400
-#else
-.equ UND_Stack_Size,     0x00000000
-#endif
 .equ SVC_Stack_Size,     0x00000400
-.equ ABT_Stack_Size,     0x00000000
+.equ ABT_Stack_Size,     0x00000400
 .equ RT_FIQ_STACK_PGSZ,  0x00000000
 .equ RT_IRQ_STACK_PGSZ,  0x00000800
 .equ USR_Stack_Size,     0x00000400
 
+.equ SUB_UND_Stack_Size,     0x00000400
+.equ SUB_SVC_Stack_Size,     0x00000400
+.equ SUB_ABT_Stack_Size,     0x00000400
+.equ SUB_RT_FIQ_STACK_PGSZ,  0x00000000
+.equ SUB_RT_IRQ_STACK_PGSZ,  0x00000400
+.equ SUB_USR_Stack_Size,     0x00000400
+
 #define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                  RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
 
-.section .data.share.isr
+#define SUB_ISR_Stack_Size  (SUB_UND_Stack_Size + SUB_SVC_Stack_Size + SUB_ABT_Stack_Size + \
+                 SUB_RT_FIQ_STACK_PGSZ + SUB_RT_IRQ_STACK_PGSZ)
+
+.section .bss.share.isr
 /* stack */
 .globl stack_start
 .globl stack_top
@@ -82,9 +88,40 @@ continue:
 
     /* disable the data alignment check */
     mrc p15, 0, r1, c1, c0, 0
-    bic r1, #(1<<1)
+    bic r1, #(1<<0)             /* Disable MMU */
+    bic r1, #(1<<1)             /* Disable Alignment fault checking */
+    bic r1, #(1<<2)             /* Disable data cache */
+    bic r1, #(1<<11)            /* Disable program flow prediction */
+    bic r1, #(1<<12)            /* Disable instruction cache */
+    bic r1, #(3<<19)            /* bit[20:19] must be zero */
     mcr p15, 0, r1, c1, c0, 0
 
+    @ get cpu id, and subtract the offset from the stacks base address
+    bl rt_hw_cpu_id
+    mov r5, r0
+
+    cmp     r5, #0              @ cpu id == 0
+    beq     normal_setup
+
+    @ cpu id > 0, stop or wait
+#ifdef RT_SMP_AUTO_BOOT
+    ldr r0, =secondary_cpu_entry
+    mov r1, #0
+    str r1, [r0] /* clean secondary_cpu_entry */
+#endif /* RT_SMP_AUTO_BOOT */
+
+secondary_loop:
+    @ cpu core 1 goes into sleep until core 0 wakeup it
+    wfe
+#ifdef RT_SMP_AUTO_BOOT
+    ldr r1, =secondary_cpu_entry
+    ldr r0, [r1]
+    cmp r0, #0
+    blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */
+#endif /* RT_SMP_AUTO_BOOT */
+    b secondary_loop
+
+normal_setup:
     /* setup stack */
     bl      stack_setup
 
@@ -105,6 +142,11 @@ bss_loop:
     mcr p15, 0, r1, c1, c0, 1 //enable smp
 #endif
 
+    /* enable branch prediction */
+    mrc p15, 0, r0, c1, c0, 0
+    orr     r0, r0, #(1<<11)
+    mcr p15, 0, r0, c1, c0, 0
+
     /* initialize the mmu table and enable mmu */
     ldr r0, =platform_mem_desc
     ldr r1, =platform_mem_desc_size
@@ -137,6 +179,7 @@ stack_setup:
 
     @  Set the startup stack for svc
     mov     sp, r0
+    sub     r0, r0, #SVC_Stack_Size
 
     @  Enter Undefined Instruction Mode and set its Stack Pointer
     msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
@@ -298,6 +341,8 @@ rt_hw_context_switch_interrupt_do:
     ldr     r6,  [r6]
     ldr     sp,  [r6]       @ get new task's stack pointer
 
+    bl rt_interrupt_hook
+
 #ifdef RT_USING_FPU
 /* fpu context */
     ldmfd sp!, {r6}
@@ -330,9 +375,18 @@ rt_hw_context_switch_interrupt_do:
     mrs     r6, spsr                @/* Save CPSR                       */
     str     lr, [r0, #15*4]         @/* Push PC                         */
     str     r6, [r0, #16*4]         @/* Push CPSR                       */
-    cps     #Mode_SVC
+    mrs     r5, cpsr                @/* Save CPSR                       */
+
+    and     r4, r6, #0x1F
+    cmp     r4, #Mode_USR
+    moveq   r6, #Mode_SYS
+
+    orr     r6, r6, #0x80           @/* Switch to previous mode, then save SP & PC */
+    msr     cpsr_c, r6
     str     sp, [r0, #13*4]         @/* Save calling SP                 */
     str     lr, [r0, #14*4]         @/* Save calling PC                 */
+
+    msr     cpsr_c, r5              @/* Switch back to current mode */
 .endm
 
     .align  5
@@ -378,16 +432,6 @@ vector_resv:
     b       .
 
 #ifdef RT_USING_SMP
-.global set_secondary_cpu_boot_address
-set_secondary_cpu_boot_address:
-    ldr r0, =secondary_cpu_start
-
-    mvn r1, #0 //0xffffffff
-    ldr r2, =0x10000034
-    str r1, [r2]
-    str r0, [r2, #-4]
-    mov pc, lr
-
 .global secondary_cpu_start
 secondary_cpu_start:
 
@@ -405,38 +449,54 @@ secondary_cpu_start:
     bic r0, #(1<<13)
     mcr p15, 0, r0, c1, c0, 0
 
-#ifdef RT_USING_FPU
+    /* enable branch prediction */
+    mrc p15, 0, r0, c1, c0, 0
+    orr     r0, r0, #(1<<11)
+    mcr p15, 0, r0, c1, c0, 0
+
+    @ get cpu id, and subtract the offset from the stacks base address
+    bl rt_hw_cpu_id
+    sub r5, r0, #1
+
+    ldr r0, =SUB_ISR_Stack_Size
+    mul r0, r0, r5                      @r0 = SUB_ISR_Stack_Size * (cpuid - 1)
+    ldr r1, =sub_stack_top
+    sub r0, r1, r0                      @r0 = sub_stack_top - (SUB_ISR_Stack_Size * (cpuid - 1))
+
+    cps #Mode_SVC
+    mov     sp, r0
+    sub     r0, r0, #SUB_SVC_Stack_Size
+
     cps #Mode_UND
-    ldr sp, =und_stack_2_limit
-#endif
+    mov     sp, r0
+    sub     r0, r0, #SUB_UND_Stack_Size
 
-    cps #Mode_IRQ
-    ldr sp, =irq_stack_2_limit
+    cps #Mode_ABT
+    mov     sp, r0
+    sub     r0, r0, #SUB_ABT_Stack_Size
 
     cps #Mode_FIQ
-    ldr sp, =irq_stack_2_limit
+    mov     sp, r0
+    sub     r0, r0, #SUB_RT_FIQ_STACK_PGSZ
+
+    cps #Mode_IRQ
+    mov     sp, r0
+    sub     r0, r0, #SUB_RT_IRQ_STACK_PGSZ
 
     cps #Mode_SVC
-    ldr sp, =svc_stack_2_limit
 
     /* initialize the mmu table and enable mmu */
     bl rt_hw_mmu_init
 
     b secondary_cpu_c_start
-#endif
 
 .bss
 .align 2   //align to  2~2=4
-svc_stack_2:
-    .space (1 << 10)
-svc_stack_2_limit:
 
-irq_stack_2:
-    .space (1 << 10)
-irq_stack_2_limit:
+.global sub_stack_top /* used for backtrace to calculate stack top of irq mode */
+
+sub_stack_start:
+    .space (SUB_ISR_Stack_Size * (RT_CPUS_NR-1))
+sub_stack_top:
 
-#ifdef RT_USING_FPU
-und_stack_2:
-    .space (1 << 10)
-und_stack_2_limit:
 #endif
diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c
index 3faa136677..b3efe31a64 100644
--- a/libcpu/arm/cortex-a/trap.c
+++ b/libcpu/arm/cortex-a/trap.c
@@ -35,6 +35,18 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
     rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
+void (*rt_trap_hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type);
+
+/**
+ * This function will set a hook function to trap handler.
+ *
+ * @param hook the hook function
+ */
+void rt_hw_trap_set_hook(void (*hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type))
+{
+    rt_trap_hook = hook;
+}
+
 /**
  * When comes across an instruction which it cannot handle,
  * it takes the undefined instruction trap.
@@ -72,12 +84,20 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
         }
     }
 #endif
-    rt_kprintf("undefined instruction:\n");
-    rt_hw_show_register(regs);
+
+    if (rt_trap_hook == RT_NULL)
+    {
+        rt_kprintf("undefined instruction:\n");
+        rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-    list_thread();
+        list_thread();
 #endif
-    rt_hw_cpu_shutdown();
+        rt_hw_cpu_shutdown();
+    }
+    else
+    {
+        rt_trap_hook(regs, "undefined instruction", UND_EXCEPTION);
+    }
 }
 
 /**
@@ -91,12 +111,19 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
 {
-    rt_kprintf("software interrupt:\n");
-    rt_hw_show_register(regs);
+    if (rt_trap_hook == RT_NULL)
+    {
+        rt_kprintf("software interrupt:\n");
+        rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-    list_thread();
+        list_thread();
 #endif
-    rt_hw_cpu_shutdown();
+        rt_hw_cpu_shutdown();
+    }
+    else
+    {
+        rt_trap_hook(regs, "software instruction", SWI_EXCEPTION);
+    }
 }
 
 /**
@@ -109,12 +136,19 @@ void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
 {
-    rt_kprintf("prefetch abort:\n");
-    rt_hw_show_register(regs);
+    if (rt_trap_hook == RT_NULL)
+    {
+        rt_kprintf("prefetch abort:\n");
+        rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-    list_thread();
+        list_thread();
 #endif
-    rt_hw_cpu_shutdown();
+        rt_hw_cpu_shutdown();
+    }
+    else
+    {
+        rt_trap_hook(regs, "prefetch abort", PABT_EXCEPTION);
+    }
 }
 
 /**
@@ -127,12 +161,19 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
 {
-    rt_kprintf("data abort:");
-    rt_hw_show_register(regs);
+    if (rt_trap_hook == RT_NULL)
+    {
+        rt_kprintf("data abort:");
+        rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-    list_thread();
+        list_thread();
 #endif
-    rt_hw_cpu_shutdown();
+        rt_hw_cpu_shutdown();
+    }
+    else
+    {
+        rt_trap_hook(regs, "data abort", DABT_EXCEPTION);
+    }
 }
 
 /**
@@ -144,23 +185,32 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
 {
-    rt_kprintf("reserved trap:\n");
-    rt_hw_show_register(regs);
+    if (rt_trap_hook == RT_NULL)
+    {
+        rt_kprintf("reserved trap:\n");
+        rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-    list_thread();
+        list_thread();
 #endif
-    rt_hw_cpu_shutdown();
+        rt_hw_cpu_shutdown();
+    }
+    else
+    {
+        rt_trap_hook(regs, "reserved trap", RESV_EXCEPTION);
+    }
 }
 
 void rt_hw_trap_irq(void)
 {
     void *param;
+    int int_ack;
     int ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];
 
-    ir = rt_hw_interrupt_get_irq();
+    int_ack = rt_hw_interrupt_get_irq();
 
+    ir = int_ack & GIC_ACK_INTID_MASK;
     if (ir == 1023)
     {
         /* Spurious interrupt */
@@ -181,7 +231,7 @@ void rt_hw_trap_irq(void)
     }
 
     /* end of interrupt */
-    rt_hw_interrupt_ack(ir);
+    rt_hw_interrupt_ack(int_ack);
 }
 
 void rt_hw_trap_fiq(void)
diff --git a/libcpu/arm/cortex-m23/SConscript b/libcpu/arm/cortex-m23/SConscript
index 28af7ba651..a4535c03ea 100644
--- a/libcpu/arm/cortex-m23/SConscript
+++ b/libcpu/arm/cortex-m23/SConscript
@@ -10,6 +10,8 @@ CPPPATH = [cwd]
 
 if rtconfig.PLATFORM == 'armcc':
     src += Glob('*_rvds.S')
+elif rtconfig.PLATFORM == 'armclang':
+    src += Glob('*_rvds.S')
 
 if rtconfig.PLATFORM == 'gcc':
     src += Glob('*_init.S')
diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript
index 28af7ba651..717823339d 100644
--- a/libcpu/arm/cortex-m7/SConscript
+++ b/libcpu/arm/cortex-m7/SConscript
@@ -8,7 +8,7 @@ cwd     = GetCurrentDir()
 src     = Glob('*.c') + Glob('*.cpp')
 CPPPATH = [cwd]
 
-if rtconfig.PLATFORM == 'armcc':
+if rtconfig.PLATFORM == 'armcc' or rtconfig.PLATFORM == 'armclang':
     src += Glob('*_rvds.S')
 
 if rtconfig.PLATFORM == 'gcc':
diff --git a/libcpu/arm/zynqmp-r5/cache.c b/libcpu/arm/zynqmp-r5/cache.c
index d6e7cd2d6d..6053b2fe47 100644
--- a/libcpu/arm/zynqmp-r5/cache.c
+++ b/libcpu/arm/zynqmp-r5/cache.c
@@ -1,11 +1,13 @@
 /*
  * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2014 - 2020 Xilinx, Inc.  All rights reserved.
+ * Copyright (c) 2021 WangHuachen.  All rights reserved.
+ * SPDX-License-Identifier: MIT
  *
  * Change Logs:
  * Date           Author       Notes
  * 2020-03-19     WangHuachen  first version
+ * 2021-05-10     WangHuachen  add more functions
  */
 #include <rthw.h>
 #include <rtdef.h>
@@ -44,41 +46,77 @@ typedef rt_uint32_t u32;
         XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
 #endif
 
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+void Xil_DCacheInvalidateLine(INTPTR adr);
+void Xil_DCacheFlushLine(INTPTR adr);
+void Xil_DCacheStoreLine(INTPTR adr);
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_ICacheInvalidateLine(INTPTR adr);
 
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+void Xil_DCacheEnable(void)
+{
+    register u32 CtrlReg;
+
+    /* enable caches only if they are disabled */
+#if defined (__GNUC__)
+    CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+     mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
+#endif
+    if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
+        /* invalidate the Data cache */
+        Xil_DCacheInvalidate();
+
+        /* enable the Data cache */
+        CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+        mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+    }
+}
+
+void Xil_DCacheDisable(void)
+{
+    register u32 CtrlReg;
+
+    /* clean and invalidate the Data cache */
+    Xil_DCacheFlush();
+
+    /* disable the Data cache */
+#if defined (__GNUC__)
+    CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+     mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
+#endif
+
+    CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+    mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+void Xil_DCacheInvalidate(void)
 {
-    u32 LocalAddr = adr;
-    const u32 cacheline = 32U;
-    u32 end;
     u32 currmask;
 
     currmask = mfcpsr();
     mtcpsr(currmask | IRQ_FIQ_MASK);
-    if (len != 0x00000000U) {
-        /* Back the starting address up to the start of a cache line
-         * perform cache operations until adr+len
-         */
-        end = LocalAddr + len;
-        LocalAddr = LocalAddr & ~(cacheline - 1U);
 
-        /* Select cache L0 I-cache in CSSR */
-        mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
-        while (LocalAddr < end) {
-
-            /* Invalidate L1 I-cache line */
-            asm_inval_ic_line_mva_pou(LocalAddr);
+    mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
 
-            LocalAddr += cacheline;
-        }
-    }
+    /*invalidate all D cache*/
+    mtcp(XREG_CP15_INVAL_DC_ALL, 0);
 
-    /* Wait for invalidate to complete */
-    dsb();
     mtcpsr(currmask);
 }
 
-void Xil_DCacheFlushLine(INTPTR adr)
+void Xil_DCacheInvalidateLine(INTPTR adr)
 {
     u32 currmask;
 
@@ -86,11 +124,11 @@ void Xil_DCacheFlushLine(INTPTR adr)
     mtcpsr(currmask | IRQ_FIQ_MASK);
 
     mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+    mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
 
-    mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
-        /* Wait for flush to complete */
+        /* Wait for invalidate to complete */
     dsb();
+
     mtcpsr(currmask);
 }
 
@@ -135,6 +173,79 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
     mtcpsr(currmask);
 }
 
+void Xil_DCacheFlush(void)
+{
+    register u32 CsidReg, C7Reg;
+    u32 CacheSize, LineSize, NumWays;
+    u32 Way, WayIndex, Set, SetIndex, NumSet;
+    u32 currmask;
+
+    currmask = mfcpsr();
+    mtcpsr(currmask | IRQ_FIQ_MASK);
+
+    /* Select cache level 0 and D cache in CSSR */
+    mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#if defined (__GNUC__)
+    CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+     mfcp(XREG_CP15_CACHE_SIZE_ID,CsidReg);
+#endif
+    /* Determine Cache Size */
+
+    CacheSize = (CsidReg >> 13U) & 0x000001FFU;
+    CacheSize += 0x00000001U;
+    CacheSize *= (u32)128;    /* to get number of bytes */
+
+    /* Number of Ways */
+    NumWays = (CsidReg & 0x000003ffU) >> 3U;
+    NumWays += 0x00000001U;
+
+    /* Get the cacheline size, way size, index size from csidr */
+    LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+    NumSet = CacheSize/NumWays;
+    NumSet /= (0x00000001U << LineSize);
+
+    Way = 0U;
+    Set = 0U;
+
+    /* Invalidate all the cachelines */
+    for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+        for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+            C7Reg = Way | Set;
+            /* Flush by Set/Way */
+            asm_clean_inval_dc_line_sw(C7Reg);
+
+            Set += (0x00000001U << LineSize);
+        }
+        Set = 0U;
+        Way += 0x40000000U;
+    }
+
+    /* Wait for flush to complete */
+    dsb();
+    mtcpsr(currmask);
+
+    mtcpsr(currmask);
+}
+
+void Xil_DCacheFlushLine(INTPTR adr)
+{
+    u32 currmask;
+
+    currmask = mfcpsr();
+    mtcpsr(currmask | IRQ_FIQ_MASK);
+
+    mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+    mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+        /* Wait for flush to complete */
+    dsb();
+    mtcpsr(currmask);
+}
+
 void Xil_DCacheFlushRange(INTPTR adr, u32 len)
 {
     u32 LocalAddr = adr;
@@ -163,6 +274,130 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len)
     mtcpsr(currmask);
 }
 
+void Xil_DCacheStoreLine(INTPTR adr)
+{
+    u32 currmask;
+
+    currmask = mfcpsr();
+    mtcpsr(currmask | IRQ_FIQ_MASK);
+
+    mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+    mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+    /* Wait for store to complete */
+    dsb();
+    isb();
+
+    mtcpsr(currmask);
+}
+
+void Xil_ICacheEnable(void)
+{
+    register u32 CtrlReg;
+
+    /* enable caches only if they are disabled */
+#if defined (__GNUC__)
+    CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+    mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#endif
+    if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
+        /* invalidate the instruction cache */
+        mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+        /* enable the instruction cache */
+        CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+        mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+    }
+}
+
+void Xil_ICacheDisable(void)
+{
+    register u32 CtrlReg;
+
+    dsb();
+
+    /* invalidate the instruction cache */
+    mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+        /* disable the instruction cache */
+#if defined (__GNUC__)
+    CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+    mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
+#endif
+
+    CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+    mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+void Xil_ICacheInvalidate(void)
+{
+    u32 currmask;
+
+    currmask = mfcpsr();
+    mtcpsr(currmask | IRQ_FIQ_MASK);
+
+    mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+
+    /* invalidate the instruction cache */
+    mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+    /* Wait for invalidate to complete */
+    dsb();
+    mtcpsr(currmask);
+}
+
+void Xil_ICacheInvalidateLine(INTPTR adr)
+{
+    u32 currmask;
+
+    currmask = mfcpsr();
+    mtcpsr(currmask | IRQ_FIQ_MASK);
+
+    mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+    mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
+
+        /* Wait for invalidate to complete */
+    dsb();
+    mtcpsr(currmask);
+}
+
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+    u32 LocalAddr = adr;
+    const u32 cacheline = 32U;
+    u32 end;
+    u32 currmask;
+
+    currmask = mfcpsr();
+    mtcpsr(currmask | IRQ_FIQ_MASK);
+    if (len != 0x00000000U) {
+        /* Back the starting address up to the start of a cache line
+         * perform cache operations until adr+len
+         */
+        end = LocalAddr + len;
+        LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+        /* Select cache L0 I-cache in CSSR */
+        mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+        while (LocalAddr < end) {
+
+            /* Invalidate L1 I-cache line */
+            asm_inval_ic_line_mva_pou(LocalAddr);
+
+            LocalAddr += cacheline;
+        }
+    }
+
+    /* Wait for invalidate to complete */
+    dsb();
+    mtcpsr(currmask);
+}
+
 void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
 {
     if (ops == RT_HW_CACHE_INVALIDATE)
diff --git a/libcpu/arm/zynqmp-r5/start_gcc.S b/libcpu/arm/zynqmp-r5/start_gcc.S
index faea0022be..7e99c9e82b 100644
--- a/libcpu/arm/zynqmp-r5/start_gcc.S
+++ b/libcpu/arm/zynqmp-r5/start_gcc.S
@@ -6,6 +6,9 @@
  * Change Logs:
  * Date           Author       Notes
  * 2020-03-19 	  WangHuachen  first version
+ * 2021-05-11 	  WangHuachen  Added call to Xil_InitializeExistingMPURegConfig to
+ *                             initialize the MPU configuration table with the MPU
+ *                             configurations already set in Init_Mpu function.
  */
 
 .equ Mode_USR,        0x10
@@ -234,6 +237,7 @@ ctor_loop:
     b       ctor_loop
 ctor_end:
 
+    bl 	Xil_InitializeExistingMPURegConfig	/* Initialize MPU config */
     /* start RT-Thread Kernel       */
     ldr     pc, _entry
 
diff --git a/libcpu/arm/zynqmp-r5/xil_mmu.h b/libcpu/arm/zynqmp-r5/xil_mmu.h
new file mode 100644
index 0000000000..99e019c6f5
--- /dev/null
+++ b/libcpu/arm/zynqmp-r5/xil_mmu.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+* Copyright (c) 2015 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API
+* defined for MPU in R5. R5 does not have mmu and for usage of similar API
+* the file has been created.
+*
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.0    pkp  2/12/15 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_mpu.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
diff --git a/libcpu/arm/zynqmp-r5/xil_mpu.c b/libcpu/arm/zynqmp-r5/xil_mpu.c
new file mode 100644
index 0000000000..9ab94a488b
--- /dev/null
+++ b/libcpu/arm/zynqmp-r5/xil_mpu.c
@@ -0,0 +1,637 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2021 WangHuachen. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mpu.c
+*
+* This file provides APIs for enabling/disabling MPU and setting the memory
+* attributes for sections, in the MPU translation table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 6.2   mus  01/27/17 Updated to support IAR compiler
+* 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
+*                       user-friendly. The APIs added are: Xil_UpdateMPUConfig,
+*                       Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
+*                       Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
+*                       Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
+*                       Xil_InitializeExistingMPURegConfig.
+*                       Added a new array of structure of type XMpuConfig to
+*                       represent the MPU configuration table.
+* 6.8  aru  07/02/18 Returned the pointer instead of address
+*            of that pointer in Xil_MemMap().
+* </pre>
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm_gcc.h"
+#include "xil_types.h"
+#include "xil_mpu.h"
+// #include "xdebug.h"
+#include "xreg_cortexr5.h"
+#include "xstatus.h"
+
+#include <rtthread.h>
+#define DBG_TAG           "xil_mpu"
+#define DBG_LVL           DBG_INFO
+#include <rtdbg.h>
+
+extern void Xil_DCacheFlush(void);
+extern void Xil_ICacheInvalidate(void);
+extern void Xil_DCacheDisable(void);
+extern void Xil_ICacheDisable(void);
+extern void Xil_DCacheEnable(void);
+extern void Xil_ICacheEnable(void);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+#define MPU_REGION_SIZE_MIN 0x20
+/************************** Variable Definitions *****************************/
+
+static const struct {
+    u64 size;
+    unsigned int encoding;
+}region_size[] = {
+    { 0x20, REGION_32B },
+    { 0x40, REGION_64B },
+    { 0x80, REGION_128B },
+    { 0x100, REGION_256B },
+    { 0x200, REGION_512B },
+    { 0x400, REGION_1K },
+    { 0x800, REGION_2K },
+    { 0x1000, REGION_4K },
+    { 0x2000, REGION_8K },
+    { 0x4000, REGION_16K },
+    { 0x8000, REGION_32K },
+    { 0x10000, REGION_64K },
+    { 0x20000, REGION_128K },
+    { 0x40000, REGION_256K },
+    { 0x80000, REGION_512K },
+    { 0x100000, REGION_1M },
+    { 0x200000, REGION_2M },
+    { 0x400000, REGION_4M },
+    { 0x800000, REGION_8M },
+    { 0x1000000, REGION_16M },
+    { 0x2000000, REGION_32M },
+    { 0x4000000, REGION_64M },
+    { 0x8000000, REGION_128M },
+    { 0x10000000, REGION_256M },
+    { 0x20000000, REGION_512M },
+    { 0x40000000, REGION_1G },
+    { 0x80000000, REGION_2G },
+    { 0x100000000, REGION_4G },
+};
+
+XMpu_Config Mpu_Config;
+
+/************************** Function Prototypes ******************************/
+void Xil_InitializeExistingMPURegConfig(void);
+/*****************************************************************************/
+/**
+* @brief    This function sets the memory attributes for a section covering
+*           1MB, of memory in the translation table.
+*
+* @param    Addr: 32-bit address for which memory attributes need to be set.
+* @param    attrib: Attribute for the given memory region.
+* @return    None.
+*
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
+{
+    INTPTR Localaddr = addr;
+    Localaddr &= (~(0xFFFFFU));
+    /* Setting the MPU region with given attribute with 1MB size */
+    Xil_SetMPURegion(Localaddr, 0x100000, attrib);
+}
+
+/*****************************************************************************/
+/**
+* @brief    Set the memory attributes for a section of memory in the
+*           translation table.
+*
+* @param    Addr: 32-bit address for which memory attributes need to be set..
+* @param    size: size is the size of the region.
+* @param    attrib: Attribute for the given memory region.
+* @return    None.
+*
+*
+******************************************************************************/
+u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
+{
+    u32 Regionsize = 0;
+    INTPTR Localaddr = addr;
+    u32 NextAvailableMemRegion;
+    unsigned int i;
+
+    NextAvailableMemRegion = Xil_GetNextMPURegion();
+    if (NextAvailableMemRegion == 0xFF) {
+        LOG_E("No regions available\r\n");
+        return XST_FAILURE;
+    }
+
+    Xil_DCacheFlush();
+    Xil_ICacheInvalidate();
+
+    mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
+    isb();
+
+    /* Lookup the size.  */
+    for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
+        if (size <= region_size[i].size) {
+            Regionsize = region_size[i].encoding;
+            break;
+        }
+    }
+
+    Localaddr &= ~(region_size[i].size - 1);
+
+    Regionsize <<= 1;
+    Regionsize |= REGION_EN;
+    dsb();
+    mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);    /* Set base address of a region */
+    mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);    /* Set the control attribute */
+    mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);    /* set the region size and enable it*/
+    dsb();
+    isb();
+    Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib);
+    return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+* @brief    Enable MPU for Cortex R5 processor. This function invalidates I
+*           cache and flush the D Caches, and then enables the MPU.
+*
+*
+* @param    None.
+* @return    None.
+*
+******************************************************************************/
+void Xil_EnableMPU(void)
+{
+    u32 CtrlReg, Reg;
+    s32 DCacheStatus=0, ICacheStatus=0;
+    /* enable caches only if they are disabled */
+#if defined (__GNUC__)
+    CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+    mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
+#endif
+    if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
+        DCacheStatus=1;
+    }
+    if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
+        ICacheStatus=1;
+    }
+
+    if(DCacheStatus != 0) {
+        Xil_DCacheDisable();
+    }
+    if(ICacheStatus != 0){
+        Xil_ICacheDisable();
+    }
+#if defined (__GNUC__)
+    Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+     mfcp(XREG_CP15_SYS_CONTROL,Reg);
+#endif
+    Reg |= 0x00000001U;
+    dsb();
+    mtcp(XREG_CP15_SYS_CONTROL, Reg);
+    isb();
+    /* enable caches only if they are disabled in routine*/
+    if(DCacheStatus != 0) {
+        Xil_DCacheEnable();
+    }
+    if(ICacheStatus != 0) {
+        Xil_ICacheEnable();
+    }
+}
+
+/*****************************************************************************/
+/**
+* @brief    Disable MPU for Cortex R5 processors. This function invalidates I
+*           cache and flush the D Caches, and then disabes the MPU.
+*
+* @param    None.
+*
+* @return    None.
+*
+******************************************************************************/
+void Xil_DisableMPU(void)
+{
+    u32 CtrlReg, Reg;
+    s32 DCacheStatus=0, ICacheStatus=0;
+    /* enable caches only if they are disabled */
+
+#if defined (__GNUC__)
+    CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+    mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
+#endif
+    if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
+        DCacheStatus=1;
+    }
+    if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
+        ICacheStatus=1;
+    }
+
+    if(DCacheStatus != 0) {
+        Xil_DCacheDisable();
+    }
+    if(ICacheStatus != 0){
+        Xil_ICacheDisable();
+    }
+
+    mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+#if defined (__GNUC__)
+    Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+    mfcp(XREG_CP15_SYS_CONTROL,Reg);
+#endif
+    Reg &= ~(0x00000001U);
+    dsb();
+    mtcp(XREG_CP15_SYS_CONTROL, Reg);
+    isb();
+    /* enable caches only if they are disabled in routine*/
+    if(DCacheStatus != 0) {
+        Xil_DCacheEnable();
+    }
+    if(ICacheStatus != 0) {
+        Xil_ICacheEnable();
+    }
+}
+
+/*****************************************************************************/
+/**
+* @brief    Update the MPU configuration for the requested region number in
+*             the global MPU configuration table.
+*
+* @param    reg_num: The requested region number to be updated information for.
+* @param    address: 32 bit address for start of the region.
+* @param    size: Requested size of the region.
+* @param    attrib: Attribute for the corresponding region.
+* @return    XST_FAILURE: When the requested region number if 16 or more.
+*             XST_SUCCESS: When the MPU configuration table is updated.
+*
+*
+******************************************************************************/
+u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib)
+{
+    u32 ReturnVal = XST_SUCCESS;
+    u32 Tempsize = size;
+    u32 Index;
+
+    if (reg_num >=  MAX_POSSIBLE_MPU_REGS) {
+        LOG_E("Invalid region number\r\n");
+        ReturnVal = XST_FAILURE;
+        goto exit;
+    }
+
+    if (size & REGION_EN) {
+        Mpu_Config[reg_num].RegionStatus = MPU_REG_ENABLED;
+        Mpu_Config[reg_num].BaseAddress = address;
+        Tempsize &= (~REGION_EN);
+        Tempsize >>= 1;
+        /* Lookup the size.  */
+        for (Index = 0; Index <
+                sizeof region_size / sizeof region_size[0]; Index++) {
+            if (Tempsize <= region_size[Index].encoding) {
+                Mpu_Config[reg_num].Size = region_size[Index].size;
+                break;
+            }
+        }
+        Mpu_Config[reg_num].Attribute = attrib;
+    } else {
+        Mpu_Config[reg_num].RegionStatus = 0U;
+        Mpu_Config[reg_num].BaseAddress = 0U;
+        Mpu_Config[reg_num].Size = 0U;
+        Mpu_Config[reg_num].Attribute = 0U;
+    }
+
+exit:
+    return ReturnVal;
+}
+
+/*****************************************************************************/
+/**
+* @brief    The MPU configuration table is passed to the caller.
+*
+* @param    mpuconfig: This is of type XMpu_Config which is an array of
+*             16 entries of type structure representing the MPU config table
+* @return    none
+*
+*
+******************************************************************************/
+void Xil_GetMPUConfig (XMpu_Config mpuconfig) {
+    u32 Index = 0U;
+
+    while (Index < MAX_POSSIBLE_MPU_REGS) {
+        mpuconfig[Index].RegionStatus = Mpu_Config[Index].RegionStatus;
+        mpuconfig[Index].BaseAddress = Mpu_Config[Index].BaseAddress;
+        mpuconfig[Index].Attribute = Mpu_Config[Index].Attribute;
+        mpuconfig[Index].Size = Mpu_Config[Index].Size;
+        Index++;
+    }
+}
+
+/*****************************************************************************/
+/**
+* @brief    Returns the total number of free MPU regions available.
+*
+* @param    none
+* @return    Number of free regions available to users
+*
+*
+******************************************************************************/
+u32 Xil_GetNumOfFreeRegions (void) {
+    u32 Index = 0U;
+    int NumofFreeRegs = 0U;
+
+    while (Index < MAX_POSSIBLE_MPU_REGS) {
+        if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
+            NumofFreeRegs++;
+        }
+        Index++;
+    }
+    return NumofFreeRegs;
+}
+
+/*****************************************************************************/
+/**
+* @brief    Returns the total number of free MPU regions available in the form
+*           of a mask. A bit of 1 in the returned 16 bit value represents the
+*           corresponding region number to be available.
+*           For example, if this function returns 0xC0000, this would mean, the
+*           regions 14 and 15 are available to users.
+*
+* @param    none
+* @return    The free region mask as a 16 bit value
+*
+*
+******************************************************************************/
+u16 Xil_GetMPUFreeRegMask (void) {
+    u32 Index = 0U;
+    u16 FreeRegMask = 0U;
+
+    while (Index < MAX_POSSIBLE_MPU_REGS) {
+        if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
+            FreeRegMask |= (1U << Index);
+        }
+        Index++;
+    }
+    return FreeRegMask;
+}
+
+/*****************************************************************************/
+/**
+* @brief    Disables the corresponding region number as passed by the user.
+*
+* @param    reg_num: The region number to be disabled
+* @return    XST_SUCCESS: If the region could be disabled successfully
+*             XST_FAILURE: If the requested region number is 16 or more.
+*
+*
+******************************************************************************/
+u32 Xil_DisableMPURegionByRegNum (u32 reg_num) {
+    u32 Temp = 0U;
+    u32 ReturnVal = XST_FAILURE;
+
+    if (reg_num >= 16U) {
+        LOG_E("Invalid region number\r\n");
+        goto exit1;
+    }
+    Xil_DCacheFlush();
+    Xil_ICacheInvalidate();
+
+    mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+#if defined (__GNUC__)
+    Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
+#elif defined (__ICCARM__)
+    mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
+#endif
+    Temp &= (~REGION_EN);
+    dsb();
+    mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
+    dsb();
+    isb();
+    Xil_UpdateMPUConfig(reg_num, 0U, 0U, 0U);
+    ReturnVal = XST_SUCCESS;
+
+exit1:
+    return ReturnVal;
+}
+
+/*****************************************************************************/
+/**
+* @brief    Enables the corresponding region number as passed by the user.
+*
+* @param    reg_num: The region number to be enabled
+* @param    address: 32 bit address for start of the region.
+* @param    size: Requested size of the region.
+* @param    attrib: Attribute for the corresponding region.
+* @return    XST_SUCCESS: If the region could be created successfully
+*             XST_FAILURE: If the requested region number is 16 or more.
+*
+*
+******************************************************************************/
+u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib)
+{
+    u32 ReturnVal = XST_SUCCESS;
+    INTPTR Localaddr = addr;
+    u32 Regionsize = 0;
+    u32 Index;
+
+    if (reg_num >= 16U) {
+        LOG_E("Invalid region number\r\n");
+        ReturnVal = XST_FAILURE;
+        goto exit2;
+    }
+
+    if (Mpu_Config[reg_num].RegionStatus == MPU_REG_ENABLED) {
+        LOG_E("Region already enabled\r\n");
+        ReturnVal = XST_FAILURE;
+        goto exit2;
+    }
+
+    Xil_DCacheFlush();
+    Xil_ICacheInvalidate();
+    mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+    isb();
+
+    /* Lookup the size.  */
+    for (Index = 0; Index <
+            sizeof region_size / sizeof region_size[0]; Index++) {
+        if (size <= region_size[Index].size) {
+            Regionsize = region_size[Index].encoding;
+            break;
+        }
+    }
+
+    Localaddr &= ~(region_size[Index].size - 1);
+    Regionsize <<= 1;
+    Regionsize |= REGION_EN;
+    dsb();
+    mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);
+    mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);
+    mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);
+    dsb();
+    isb();
+    Xil_UpdateMPUConfig(reg_num, Localaddr, Regionsize, attrib);
+exit2:
+    return ReturnVal;
+
+}
+
+/*****************************************************************************/
+/**
+* @brief    Initializes the MPU configuration table that are setup in the
+*             R5 boot code in the Init_Mpu function called before C main.
+*
+* @param    none
+* @return    none
+*
+*
+******************************************************************************/
+void Xil_InitializeExistingMPURegConfig(void)
+{
+    u32 Index = 0U;
+    u32 Index1 = 0U;
+    u32 MPURegSize;
+    INTPTR MPURegBA;
+    u32 MPURegAttrib;
+    u32 Tempsize;
+
+    while (Index < MAX_POSSIBLE_MPU_REGS) {
+        mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
+#if defined (__GNUC__)
+        MPURegSize = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
+        MPURegBA = mfcp(XREG_CP15_MPU_REG_BASEADDR);
+        MPURegAttrib = mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL);
+#elif defined (__ICCARM__)
+        mfcp(XREG_CP15_MPU_REG_SIZE_EN,MPURegSize);
+        mfcp(XREG_CP15_MPU_REG_BASEADDR, MPURegBA);
+        mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL, MPURegAttrib);
+#endif
+        if (MPURegSize & REGION_EN) {
+            Mpu_Config[Index].RegionStatus = MPU_REG_ENABLED;
+            Mpu_Config[Index].BaseAddress = MPURegBA;
+            Mpu_Config[Index].Attribute = MPURegAttrib;
+            Tempsize = MPURegSize & (~REGION_EN);
+            Tempsize >>= 1;
+            for (Index1 = 0; Index1 <
+                (sizeof (region_size) / sizeof (region_size[0])); Index1++) {
+                if (Tempsize <= region_size[Index1].encoding) {
+                    Mpu_Config[Index].Size = region_size[Index1].size;
+                    break;
+                }
+            }
+        }
+        Index++;
+    }
+}
+
+/*****************************************************************************/
+/**
+* @brief    Returns the next available free MPU region
+*
+* @param    none
+* @return    The free MPU region available
+*
+*
+******************************************************************************/
+u32 Xil_GetNextMPURegion(void)
+{
+    u32 Index = 0U;
+    u32 NextAvailableReg = 0xFF;
+    while (Index < MAX_POSSIBLE_MPU_REGS) {
+        if (Mpu_Config[Index].RegionStatus != MPU_REG_ENABLED) {
+            NextAvailableReg = Index;
+            break;
+        }
+        Index++;
+    }
+    return NextAvailableReg;
+}
+
+/*****************************************************************************/
+/**
+* @brief       Memory mapping for Cortex r5.
+*
+* @param       Physaddr is base physical address at which to start mapping.
+*                   NULL in Physaddr masks possible mapping errors.
+* @param       size of region to be mapped.
+* @param       flags used to set translation table.
+*
+* @return      Physaddr on success, NULL on error. Ambiguous if Physaddr==NULL
+*
+* @note:    u32overflow() is defined for readability and (for __GNUC__) to
+*           - force the type of the check to be the same as the first argument
+*           - hide the otherwise unused third argument of the builtin
+*           - improve safety by choosing the explicit _uadd_ version.
+*           Consider __builtin_add_overflow_p() when available.
+*           Use an alternative (less optimal?) for compilers w/o the builtin.
+*
+******************************************************************************/
+#ifdef __GNUC__
+#define u32overflow(a, b) ({typeof(a) s; __builtin_uadd_overflow(a, b, &s); })
+#else
+#define u32overflow(a, b) ((a) > ((a) + (b)))
+#endif /* __GNUC__ */
+void *Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags)
+{
+    size_t Regionsize = MPU_REGION_SIZE_MIN;
+    UINTPTR Basephysaddr = 0, end = Physaddr + size;
+
+    if (!flags)
+        return (void *)Physaddr;
+    if (u32overflow(Physaddr, size))
+        return NULL;
+    for ( ; Regionsize != 0; Regionsize <<= 1) {
+        if (Regionsize >= size) {
+            Basephysaddr = Physaddr & ~(Regionsize - 1);
+            if (u32overflow(Basephysaddr, Regionsize))
+                break;
+            if ((Basephysaddr + Regionsize) >= end)
+                return Xil_SetMPURegion(Basephysaddr,
+                    Regionsize, flags) == XST_SUCCESS ?
+                    (void *)Physaddr : NULL;
+        }
+    }
+    return NULL;
+}
diff --git a/libcpu/arm/zynqmp-r5/xil_mpu.h b/libcpu/arm/zynqmp-r5/xil_mpu.h
new file mode 100644
index 0000000000..1afa6f76f7
--- /dev/null
+++ b/libcpu/arm/zynqmp-r5/xil_mpu.h
@@ -0,0 +1,129 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs
+*
+* MPU functions provides access to MPU operations such as enable MPU, disable
+* MPU and set attribute for section of memory.
+* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU
+* regions are allocated with another 6 being free for users. Overview of the
+* memory attributes for different MPU regions is as given below,
+*
+*|                       | Memory Range            | Attributes of MPURegion     |
+*|-----------------------|-------------------------|-----------------------------|
+*| DDR                   | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
+*| PL                    | 0x80000000 - 0xBFFFFFFF | Strongly Ordered            |
+*| QSPI                  | 0xC0000000 - 0xDFFFFFFF | Device Memory               |
+*| PCIe                  | 0xE0000000 - 0xEFFFFFFF | Device Memory               |
+*| STM_CORESIGHT         | 0xF8000000 - 0xF8FFFFFF | Device Memory               |
+*| RPU_R5_GIC            | 0xF9000000 - 0xF90FFFFF | Device memory               |
+*| FPS                   | 0xFD000000 - 0xFDFFFFFF | Device Memory               |
+*| LPS                   | 0xFE000000 - 0xFFFFFFFF | Device Memory               |
+*| OCM                   | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
+*
+*
+* @note
+* For a system where DDR is less than 2GB, region after DDR and before PL is
+* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is
+* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is
+* allocated for lower LPS slaves.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
+*                       user-friendly. The APIs added are: Xil_UpdateMPUConfig,
+*                       Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
+*                       Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
+*                       Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
+*                       Xil_InitializeExistingMPURegConfig.
+*                       Added a new array of structure of type XMpuConfig to
+*                       represent the MPU configuration table.
+* </pre>
+*
+
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MPU_H
+#define XIL_MPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#include "xil_types.h"
+/***************************** Include Files *********************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MPU_REG_DISABLED        0U
+#define MPU_REG_ENABLED            1U
+#define MAX_POSSIBLE_MPU_REGS    16U
+/**************************** Type Definitions *******************************/
+struct XMpuConfig{
+    u32 RegionStatus; /* Enabled or disabled */
+    INTPTR BaseAddress;/* MPU region base address */
+    u64 Size; /* MPU region size address */
+    u32 Attribute; /* MPU region size attribute */
+};
+
+typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS];
+
+extern XMpu_Config Mpu_Config;
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMPU(void);
+void Xil_DisableMPU(void);
+u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
+u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib);
+void Xil_GetMPUConfig (XMpu_Config mpuconfig);
+u32 Xil_GetNumOfFreeRegions (void);
+u32 Xil_GetNextMPURegion(void);
+u32 Xil_DisableMPURegionByRegNum (u32 reg_num);
+u16 Xil_GetMPUFreeRegMask (void);
+u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib);
+void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MPU_H */
+/**
+* @} End of "addtogroup r5_mpu_apis".
+*/