Merge pull request #1 from RT-Thread/master

同步原有仓库

29 files changed, 72 insertions, 411 deletions

diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c
index 2a46142b54..2e94b88277 100644
--- a/libcpu/arm/cortex-a/gic.c
+++ b/libcpu/arm/cortex-a/gic.c
@@ -74,9 +74,8 @@ void arm_gic_ack(rt_uint32_t index, int irq)
     irq = irq - _gic_table[index].offset;
     RT_ASSERT(irq >= 0);
 
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
     GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
 void arm_gic_mask(rt_uint32_t index, int irq)
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 268cc7ef56..2e99db7218 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -52,6 +52,26 @@ stack_top:
 /* reset entry */
 .globl _reset
 _reset:
+#ifdef ARCH_ARMV8
+    /* Check for HYP mode */
+    mrs r0, cpsr_all
+    and r0, r0, #0x1F
+    mov r8, #0x1A
+    cmp r0, r8
+    beq overHyped
+    b continue
+
+overHyped: /* Get out of HYP mode */
+    adr r1, continue
+    msr ELR_hyp, r1
+    mrs r1, cpsr_all
+    and r1, r1, #0x1f    ;@ CPSR_MODE_MASK
+    orr r1, r1, #0x13    ;@ CPSR_MODE_SUPERVISOR
+    msr SPSR_hyp, r1
+    eret
+
+continue:
+#endif
     /* set the cpu to SVC32 mode and disable interrupt */
     cps #Mode_SVC
 
diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S
index d9993247e2..a504ee076e 100644
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@@ -22,7 +22,7 @@
 	.equ 	SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
 	.equ 	NVIC_INT_CTRL, 0xE000ED04       /* interrupt control state register */
 	.equ 	NVIC_SHPR3, 0xE000ED20          /* system priority register (3) */
-	.equ 	NVIC_PENDSV_PRI, 0x00FF0000     /* PendSV priority value (lowest) */
+	.equ 	NVIC_PENDSV_PRI, 0xFFFF0000     /* PendSV and SysTick priority value (lowest) */
 	.equ 	NVIC_PENDSVSET, 0x10000000      /* value to trigger PendSV exception */
 
 /*
@@ -159,7 +159,7 @@ rt_hw_context_switch_to:
     MOVS    R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =NVIC_SHPR3
     LDR     R1, =NVIC_PENDSV_PRI
     LDR     R2, [R0,#0x00]       /* read */
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index 50d3781359..6f410d1a24 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -163,7 +163,7 @@ rt_hw_context_switch_to:
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index fb9ce9b4bf..072486587c 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -168,7 +168,7 @@ rt_hw_context_switch_to    PROC
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S
index 4fc5a3adbd..48f90413d9 100644
--- a/libcpu/arm/cortex-m23/context_gcc.S
+++ b/libcpu/arm/cortex-m23/context_gcc.S
@@ -23,7 +23,7 @@
 	.equ 	SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
 	.equ 	NVIC_INT_CTRL, 0xE000ED04       /* interrupt control state register */
 	.equ 	NVIC_SHPR3, 0xE000ED20          /* system priority register (3) */
-	.equ 	NVIC_PENDSV_PRI, 0x00FF0000     /* PendSV priority value (lowest) */
+	.equ 	NVIC_PENDSV_PRI, 0xFFFF0000     /* PendSV and SysTick priority value (lowest) */
 	.equ 	NVIC_PENDSVSET, 0x10000000      /* value to trigger PendSV exception */
 
 /*
@@ -137,7 +137,7 @@ pendsv_exit:
     /* restore interrupt */
     MSR     PRIMASK, R2
 
-    MOVS    R0, #0x04
+    MOVS    R0, #0x03
     RSBS    R0, R0, #0x00
     BX      R0
 /*
@@ -160,7 +160,7 @@ rt_hw_context_switch_to:
     MOVS    R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =NVIC_SHPR3
     LDR     R1, =NVIC_PENDSV_PRI
     LDR     R2, [R0,#0x00]       /* read */
diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S
index 4f30c0bc0c..c7d85cc5e2 100644
--- a/libcpu/arm/cortex-m23/context_iar.S
+++ b/libcpu/arm/cortex-m23/context_iar.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -139,7 +139,7 @@ pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    MOVS    r0, #0x04
+    MOVS    r0, #0x03
     RSBS    r0, r0, #0x00
     BX      r0
 
@@ -164,7 +164,7 @@ rt_hw_context_switch_to:
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S
index f243097cc6..ca381d0f8f 100644
--- a/libcpu/arm/cortex-m23/context_rvds.S
+++ b/libcpu/arm/cortex-m23/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -143,7 +143,7 @@ pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    MOVS    r0, #0x04
+    MOVS    r0, #0x03
     RSBS    r0, r0, #0x00
     BX      r0
     ENDP
@@ -169,7 +169,7 @@ rt_hw_context_switch_to    PROC
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S
index d17a8aa12c..2878d20082 100644
--- a/libcpu/arm/cortex-m3/context_gcc.S
+++ b/libcpu/arm/cortex-m3/context_gcc.S
@@ -24,7 +24,7 @@
     .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
     
     .equ    SHPR3, 0xE000ED20               /* system priority register (3) */
-    .equ    PENDSV_PRI_LOWEST, 0x00FF0000   /* PendSV priority value (lowest) */
+    .equ    PENDSV_PRI_LOWEST, 0xFFFF0000   /* PendSV and SysTick priority value (lowest) */
 
 /*
  * rt_base_t rt_hw_interrupt_disable();
@@ -140,7 +140,7 @@ rt_hw_context_switch_to:
     MOV     R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =SHPR3
     LDR     R1, =PENDSV_PRI_LOWEST
     LDR.W   R2, [R0,#0]             /* read */
diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S
index 91645c48b3..7c0e69bf59 100644
--- a/libcpu/arm/cortex-m3/context_iar.S
+++ b/libcpu/arm/cortex-m3/context_iar.S
@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -139,7 +139,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S
index a2a7f41a27..a661430499 100644
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@@ -18,7 +18,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -145,7 +145,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c
index d17d4fdf2e..d58782e2c5 100644
--- a/libcpu/arm/cortex-m3/cpuport.c
+++ b/libcpu/arm/cortex-m3/cpuport.c
@@ -388,13 +388,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S
index 18e97c631e..27596bf787 100644
--- a/libcpu/arm/cortex-m33/context_gcc.S
+++ b/libcpu/arm/cortex-m33/context_gcc.S
@@ -25,7 +25,7 @@
 .equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
-.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
 .equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
 
 /*
@@ -225,7 +225,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR r0, =NVIC_SYSPRI2
     LDR r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       /* read       */
diff --git a/libcpu/arm/cortex-m33/context_iar.S b/libcpu/arm/cortex-m33/context_iar.S
index 4a32c5bcef..67cf2727a2 100644
--- a/libcpu/arm/cortex-m33/context_iar.S
+++ b/libcpu/arm/cortex-m33/context_iar.S
@@ -21,7 +21,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -231,7 +231,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m33/context_rvds.S b/libcpu/arm/cortex-m33/context_rvds.S
index 7ca43933f2..dc22ead7c5 100644
--- a/libcpu/arm/cortex-m33/context_rvds.S
+++ b/libcpu/arm/cortex-m33/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -232,7 +232,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c
index 415f560911..a589ba3462 100644
--- a/libcpu/arm/cortex-m33/cpuport.c
+++ b/libcpu/arm/cortex-m33/cpuport.c
@@ -475,13 +475,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
         "BX      lr                   \n"
 
         : "=r"(value)
diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S
index 420f4f8ae3..f569a35863 100644
--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@@ -25,7 +25,7 @@
 .equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
-.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
 .equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
 
 /*
@@ -182,7 +182,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR r0, =NVIC_SYSPRI2
     LDR r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       /* read       */
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index 06b8c7f884..18d6a3f784 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -21,7 +21,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -186,7 +186,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S
index f6d2447c5e..3f948bc349 100644
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -186,7 +186,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c
index f556ba0c26..dc8a9aab59 100644
--- a/libcpu/arm/cortex-m4/cpuport.c
+++ b/libcpu/arm/cortex-m4/cpuport.c
@@ -472,13 +472,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S
index 420f4f8ae3..f569a35863 100644
--- a/libcpu/arm/cortex-m7/context_gcc.S
+++ b/libcpu/arm/cortex-m7/context_gcc.S
@@ -25,7 +25,7 @@
 .equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
-.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
 .equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
 
 /*
@@ -182,7 +182,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR r0, =NVIC_SYSPRI2
     LDR r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       /* read       */
diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S
index 06b8c7f884..18d6a3f784 100644
--- a/libcpu/arm/cortex-m7/context_iar.S
+++ b/libcpu/arm/cortex-m7/context_iar.S
@@ -21,7 +21,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -186,7 +186,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S
index ea9e9cb8b3..d051f819c1 100644
--- a/libcpu/arm/cortex-m7/context_rvds.S
+++ b/libcpu/arm/cortex-m7/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -186,7 +186,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c
index c22242f140..e701a52307 100644
--- a/libcpu/arm/cortex-m7/cpuport.c
+++ b/libcpu/arm/cortex-m7/cpuport.c
@@ -472,13 +472,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/s3c24x0/serial.c b/libcpu/arm/s3c24x0/serial.c
deleted file mode 100644
index 1eca1b1110..0000000000
--- a/libcpu/arm/s3c24x0/serial.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-03-13     Bernard      first version
- * 2009-04-20     yi.qiu      modified according bernard's stm32 version
- */
-
-#include <rtthread.h>
-
-#include "serial.h"
-
-/**
- * @addtogroup S3C24X0
- */
-/*@{*/
-
-/* RT-Thread Device Interface */
-/**
- * This function initializes serial
- */
-static rt_err_t rt_serial_init(rt_device_t dev)
-{
-    struct serial_device* uart = (struct serial_device*) dev->user_data;
-
-    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-    {
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-        {
-            rt_memset(uart->int_rx->rx_buffer, 0,
-                      sizeof(uart->int_rx->rx_buffer));
-            uart->int_rx->read_index = uart->int_rx->save_index = 0;
-        }
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-        {
-            rt_memset(uart->int_tx->tx_buffer, 0,
-                      sizeof(uart->int_tx->tx_buffer));
-            uart->int_tx->write_index = uart->int_tx->save_index = 0;
-        }
-
-        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-    }
-
-    return RT_EOK;
-}
-
-/* save a char to serial buffer */
-static void rt_serial_savechar(struct serial_device* uart, char ch)
-{
-    rt_base_t level;
-
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
-
-    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
-    uart->int_rx->save_index ++;
-    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
-        uart->int_rx->save_index = 0;
-
-    /* if the next position is read index, discard this 'read char' */
-    if (uart->int_rx->save_index == uart->int_rx->read_index)
-    {
-        uart->int_rx->read_index ++;
-        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-            uart->int_rx->read_index = 0;
-    }
-
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    ptr = buffer;
-    err_code = RT_EOK;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        rt_base_t level;
-
-        /* interrupt mode Rx */
-        while (size)
-        {
-            if (uart->int_rx->read_index != uart->int_rx->save_index)
-            {
-                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-                size --;
-
-                /* disable interrupt */
-                level = rt_hw_interrupt_disable();
-
-                uart->int_rx->read_index ++;
-                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-                    uart->int_rx->read_index = 0;
-
-                /* enable interrupt */
-                rt_hw_interrupt_enable(level);
-            }
-            else
-            {
-                /* set error code */
-                err_code = -RT_EEMPTY;
-                break;
-            }
-        }
-    }
-    else
-    {
-        /* polling mode */
-        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-        {
-            while (uart->uart_device->ustat & USTAT_RCV_READY)
-            {
-                *ptr = uart->uart_device->urxh & 0xff;
-                ptr ++;
-            }
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    err_code = RT_EOK;
-    ptr = (rt_uint8_t*)buffer;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-    {
-        /* interrupt mode Tx */
-        while (uart->int_tx->save_index != uart->int_tx->write_index)
-        {
-            /* save on tx buffer */
-            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-
-            -- size;
-
-            /* move to next position */
-            uart->int_tx->save_index ++;
-
-            /* wrap save index */
-            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
-                uart->int_tx->save_index = 0;
-        }
-
-        /* set error code */
-        if (size > 0)
-            err_code = -RT_EFULL;
-    }
-    else
-    {
-        /* polling mode */
-        while (size)
-        {
-            /*
-             * to be polite with serial console add a line feed
-             * to the carriage return character
-             */
-            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
-            {
-                while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-                uart->uart_device->utxh = '\r';
-            }
-
-            while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-            uart->uart_device->utxh = (*ptr & 0xFF);
-
-            ++ptr;
-            --size;
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_SUSPEND:
-        /* suspend device */
-        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-        break;
-
-    case RT_DEVICE_CTRL_RESUME:
-        /* resume device */
-        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-        break;
-    }
-
-    return RT_EOK;
-}
-
-/*
- * serial register
- */
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
-{
-    RT_ASSERT(device != RT_NULL);
-
-    device->type        = RT_Device_Class_Char;
-    device->rx_indicate = RT_NULL;
-    device->tx_complete = RT_NULL;
-    device->init        = rt_serial_init;
-    device->open        = rt_serial_open;
-    device->close       = rt_serial_close;
-    device->read        = rt_serial_read;
-    device->write       = rt_serial_write;
-    device->control     = rt_serial_control;
-    device->user_data   = serial;
-
-    /* register a character device */
-    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
-}
-
-/* ISR for serial interrupt */
-void rt_hw_serial_isr(rt_device_t device)
-{
-    struct serial_device* uart = (struct serial_device*) device->user_data;
-
-    /* interrupt mode receive */
-    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
-
-    /* save on rx buffer */
-    while (uart->uart_device->ustat & USTAT_RCV_READY)
-    {
-        rt_serial_savechar(uart, uart->uart_device->urxh & 0xff);
-    }
-
-    /* invoke callback */
-    if (device->rx_indicate != RT_NULL)
-    {
-        rt_size_t rx_length;
-
-        /* get rx length */
-        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
-                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
-                    uart->int_rx->save_index - uart->int_rx->read_index;
-
-        device->rx_indicate(device, rx_length);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h
deleted file mode 100644
index 8a647ef35f..0000000000
--- a/libcpu/arm/s3c24x0/serial.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "s3c24x0.h"
-
-#define	USTAT_RCV_READY		0x01   	/* receive data ready */ 
-#define	USTAT_TXB_EMPTY		0x02   	/* tx buffer empty */
-#define BPS					115200	/* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_BUFFER_SIZE		64
-
-struct serial_int_rx
-{
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
-	volatile rt_uint32_t ulcon;
-	volatile rt_uint32_t ucon;
-	volatile rt_uint32_t ufcon;
-	volatile rt_uint32_t umcon;
-	volatile rt_uint32_t ustat;
-	volatile rt_uint32_t urxb;
-	volatile rt_uint32_t ufstat;
-	volatile rt_uint32_t umstat;
-	volatile rt_uint32_t utxh;	
-	volatile rt_uint32_t urxh;	
-	volatile rt_uint32_t ubrd;
-}uartport;
-
-struct serial_device
-{
-	uartport* uart_device;
-	
-	/* rx structure */
-	struct serial_int_rx* int_rx;
-
-	/* tx structure */
-	struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-#endif
diff --git a/libcpu/arm/s3c24x0/start_gcc.S b/libcpu/arm/s3c24x0/start_gcc.S
index 4adc458094..cc2b2f6310 100644
--- a/libcpu/arm/s3c24x0/start_gcc.S
+++ b/libcpu/arm/s3c24x0/start_gcc.S
@@ -191,7 +191,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}			/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}			/* copy to   target address [r1]    */
-	cmp		r0, r2					/* until source end addreee [r2]    */
+	cmp		r0, r2			/* until source end address [r2]    */
 	ble		copy_loop
 
 	/* setup stack */
diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S
index 65b3d422dd..4c448a344f 100644
--- a/libcpu/arm/s3c44b0/start_gcc.S
+++ b/libcpu/arm/s3c44b0/start_gcc.S
@@ -107,7 +107,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}	/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}	/* copy to   target address [r1]    */
-	cmp	r0, r2				/* until source end addreee [r2]    */
+	cmp	r0, r2		/* until source end address [r2]    */
 	ble	copy_loop
 #endif
 	
diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c
index e23a359e6e..76404d4c46 100644
--- a/libcpu/arm/zynq7000/gic.c
+++ b/libcpu/arm/zynq7000/gic.c
@@ -37,7 +37,7 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
 #define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + (n/32) * 4)
 #define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + (n/32) * 4)
 #define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200)
-#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + (n/32) * 4)
 #define GIC_DIST_ACTIVE_BIT(hw_base)        __REG32((hw_base) + 0x300)
 #define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  (n/4) * 4)
 #define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  (n/4) * 4)
@@ -68,9 +68,8 @@ void arm_gic_ack(rt_uint32_t index, int irq)
     irq = irq - _gic_table[index].offset;
     RT_ASSERT(irq >= 0);
 
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
     GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
 void arm_gic_mask(rt_uint32_t index, int irq)