diff options
| author | aozima <[email protected]> | 2013-06-18 11:34:54 +0800 |
|---|---|---|
| committer | aozima <[email protected]> | 2013-06-22 18:59:51 +0800 |
| commit | a2ff85c03f813f24138f58244087ee53d161ab1a (patch) | |
| tree | a97d0f514a196748bf405706c301f0217a6692f5 /libcpu/arm | |
| parent | 4d421cad733dd4abaa4f335f10905643c8ff5737 (diff) | |
update libcpu/arm/cortex-m0: restore MSP.
Diffstat (limited to 'libcpu/arm')
| -rw-r--r-- | libcpu/arm/cortex-m0/context_gcc.S | 9 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m0/context_iar.S | 9 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m0/context_rvds.S | 9 |
3 files changed, 27 insertions, 0 deletions
diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S index bd59a01e53..f875a07fd8 100644 --- a/libcpu/arm/cortex-m0/context_gcc.S +++ b/libcpu/arm/cortex-m0/context_gcc.S @@ -13,6 +13,7 @@ * 2012-06-01 aozima set pendsv priority to 0xFF. * 2012-08-17 aozima fixed bug: store r8 - r11. * 2013-02-20 aozima port to gcc. + * 2013-06-18 aozima add restore MSP feature. */ .cpu cortex-m3 @@ -21,6 +22,7 @@ .thumb .text + .equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */ .equ ICSR, 0xE000ED04 /* interrupt control state register */ .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ @@ -152,6 +154,13 @@ rt_hw_context_switch_to: LDR R1, =PENDSVSET_BIT STR R1, [R0] + /* restore MSP */ + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + CPSIE I /* enable interrupts at processor level */ /* never reach here! */ diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S index 9b8a7dddb1..f1318e552d 100644 --- a/libcpu/arm/cortex-m0/context_iar.S +++ b/libcpu/arm/cortex-m0/context_iar.S @@ -12,6 +12,7 @@ ; * 2010-01-25 Bernard first version ; * 2012-06-01 aozima set pendsv priority to 0xFF. ; * 2012-08-17 aozima fixed bug: store r8 - r11. +; * 2013-06-18 aozima add restore MSP feature. ; */ ;/** @@ -19,6 +20,7 @@ ; */ ;/*@{*/ +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) @@ -178,6 +180,13 @@ rt_hw_context_switch_to: STR r1, [r0] NOP + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + ; enable interrupts at processor level CPSIE I diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S index 1194d8f4ae..9c2f42ac83 100644 --- a/libcpu/arm/cortex-m0/context_rvds.S +++ b/libcpu/arm/cortex-m0/context_rvds.S @@ -12,6 +12,7 @@ ; * 2010-01-25 Bernard first version ; * 2012-06-01 aozima set pendsv priority to 0xFF. ; * 2012-08-17 aozima fixed bug: store r8 - r11. +; * 2013-06-18 aozima add restore MSP feature. ; */ ;/** @@ -19,6 +20,7 @@ ; */ ;/*@{*/ +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) @@ -183,6 +185,13 @@ rt_hw_context_switch_to PROC STR r1, [r0] NOP + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + ; enable interrupts at processor level CPSIE I |