diff options
| author | FrankTan <[email protected]> | 2022-05-13 00:18:13 +0800 |
|---|---|---|
| committer | guo <[email protected]> | 2022-05-13 15:38:17 +0800 |
| commit | d2909eb16ba9b3639320dc00f33506a9d228b600 (patch) | |
| tree | 83b695093f50189da416adb672ea6742ddad9cc1 /libcpu/arm | |
| parent | ea6999a700e3507c7401f0f7397ecfd192b171f0 (diff) | |
[libcpu/arm]: fix typo
Diffstat (limited to 'libcpu/arm')
| -rw-r--r-- | libcpu/arm/cortex-m0/context_gcc.S | 2 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m23/context_gcc.S | 2 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m3/context_gcc.S | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S index 0173b594f6..59a81bc580 100644 --- a/libcpu/arm/cortex-m0/context_gcc.S +++ b/libcpu/arm/cortex-m0/context_gcc.S @@ -90,7 +90,7 @@ PendSV_Handler: LDR R0, =rt_thread_switch_interrupt_flag LDR R1, [R0] CMP R1, #0x00 - BEQ pendsv_exit /* pendsv aLReady handled */ + BEQ pendsv_exit /* pendsv already handled */ /* clear rt_thread_switch_interrupt_flag to 0 */ MOVS R1, #0 diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S index 717da447f3..abec76f934 100644 --- a/libcpu/arm/cortex-m23/context_gcc.S +++ b/libcpu/arm/cortex-m23/context_gcc.S @@ -91,7 +91,7 @@ PendSV_Handler: LDR R0, =rt_thread_switch_interrupt_flag LDR R1, [R0] CMP R1, #0x00 - BEQ pendsv_exit /* pendsv aLReady handled */ + BEQ pendsv_exit /* pendsv already handled */ /* clear rt_thread_switch_interrupt_flag to 0 */ MOVS R1, #0 diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S index 88c25d9e5c..1f4e1063e4 100644 --- a/libcpu/arm/cortex-m3/context_gcc.S +++ b/libcpu/arm/cortex-m3/context_gcc.S @@ -90,7 +90,7 @@ PendSV_Handler: /* get rt_thread_switch_interrupt_flag */ LDR R0, =rt_thread_switch_interrupt_flag LDR R1, [R0] - CBZ R1, pendsv_exit /* pendsv aLReady handled */ + CBZ R1, pendsv_exit /* pendsv already handled */ /* clear rt_thread_switch_interrupt_flag to 0 */ MOV R1, #0 |