diff options
| author | qiuyiuestc <[email protected]> | 2009-12-26 14:47:27 +0000 |
|---|---|---|
| committer | qiuyiuestc <[email protected]> | 2009-12-26 14:47:27 +0000 |
| commit | 4de2f13fcd06e366386089ef2871c4698c786a6e (patch) | |
| tree | 320afbd704a8930d1babf4f1376cd22f90d3ef54 /libcpu/arm | |
| parent | 017d2b766270fd88786a6b8d3dc736bca5e27878 (diff) | |
support GCC compiler for LM3S platform
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@236 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'libcpu/arm')
| -rw-r--r-- | libcpu/arm/lm3s/start_gcc.s | 43 |
1 files changed, 6 insertions, 37 deletions
diff --git a/libcpu/arm/lm3s/start_gcc.s b/libcpu/arm/lm3s/start_gcc.s index 81bca5b719..1d1b8e558d 100644 --- a/libcpu/arm/lm3s/start_gcc.s +++ b/libcpu/arm/lm3s/start_gcc.s @@ -1,32 +1,3 @@ -/**
- ******************************************************************************
- * @file startup_stm32f10x_hd.s
- * @author MCD Application Team
- * @version V3.1.2
- * @date 09/28/2009
- * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address,
- * - Configure external SRAM mounted on STM3210E-EVAL board
- * to be used as data memory (optional, to be enabled by user)
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
- */
.section .bss.init
.equ Stack_Size, 0x00000200
.space Stack_Size
@@ -52,8 +23,6 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */
.word _ebss
-// .equ Initial_spTop, 0x20000200
-.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
@@ -131,17 +100,17 @@ Infinite_Loop: g_pfnVectors:
.word Initial_spTop
.word Reset_Handler
- .word Default_Handler //NMI_Handler
+ .word Default_Handler //NMI_Handler
.word rt_hw_hard_fault
- .word Default_Handler //MemManage_Handler
- .word Default_Handler //BusFault_Handler
- .word Default_Handler //UsageFault_Handler
+ .word Default_Handler //MemManage_Handler
+ .word Default_Handler //BusFault_Handler
+ .word Default_Handler //UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
- .word Default_Handler //SVC_Handler
- .word Default_Handler //DebugMon_Handler
+ .word Default_Handler //SVC_Handler
+ .word Default_Handler //DebugMon_Handler
.word 0
.word rt_hw_pend_sv
.word rt_hw_timer_handler
|