diff options
| author | dzzxzz <[email protected]> | 2010-04-14 00:21:14 +0000 |
|---|---|---|
| committer | dzzxzz <[email protected]> | 2010-04-14 00:21:14 +0000 |
| commit | 02564df01e8bf28dcdd0f664ce010890d4eb3aa3 (patch) | |
| tree | b39d9b959a6327e95ebf4c06f5e6fbd2cd2124ef /libcpu/m16c/context.asm | |
| parent | 190324c7a69d3ab36d4a6f9b6666008f698f67a6 (diff) | |
port rt-thread to M16C
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@619 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'libcpu/m16c/context.asm')
| -rw-r--r-- | libcpu/m16c/context.asm | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/libcpu/m16c/context.asm b/libcpu/m16c/context.asm new file mode 100644 index 0000000000..6a1c1e1490 --- /dev/null +++ b/libcpu/m16c/context.asm @@ -0,0 +1,117 @@ +/*
+ * File : context.asm
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-04-09 fify the first version
+ *
+ * For : Renesas M16C
+ * Toolchain : IAR's EW for M16C v3.401
+*/
+
+;********************************************************************************************************
+; PUBLIC FUNCTIONS
+;********************************************************************************************************
+
+ RSEG CSTACK
+
+ RSEG ISTACK
+
+ RSEG CODE(1)
+
+ EXTERN rt_thread_switch_interrput_flag
+ EXTERN rt_interrupt_from_thread
+ EXTERN rt_interrupt_to_thread
+ EXTERN rt_interrupt_enter
+ EXTERN rt_tick_increase
+ EXTERN rt_interrupt_leave
+ EXTERN u0rec_handler
+
+ PUBLIC rt_hw_interrupt_disable
+ PUBLIC rt_hw_interrupt_enable
+ PUBLIC rt_hw_context_switch_to
+ PUBLIC rt_hw_context_switch
+ PUBLIC rt_hw_context_switch_interrupt
+ PUBLIC rt_hw_timer_handler
+ PUBLIC rt_hw_uart0_receive_handler
+
+rt_hw_interrupt_disable
+ FCLR I
+ RTS
+
+rt_hw_interrupt_enable
+ FSET I
+ RTS
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to
+ MOV.W R0, A0
+ LDC [A0], ISP
+ POPM R0,R1,R2,R3,A0,A1,SB,FB
+ REIT
+
+rt_hw_context_switch
+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB
+ MOV.W R0, A0
+ STC ISP, [A0]
+ MOV.W R1, A0
+ LDC [A0], ISP
+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore all processor registers from the new task's stack
+ REIT
+
+rt_hw_context_switch_interrupt
+ CMP.W #1,rt_thread_switch_interrput_flag
+ JEQ jump
+ MOV.W #1,rt_thread_switch_interrput_flag
+ MOV.W R0, rt_interrupt_from_thread
+jump
+ MOV.W R1, rt_interrupt_to_thread
+ RTS
+
+rt_hw_context_switch_interrupt_do
+ MOV.W #0, rt_thread_switch_interrput_flag
+ MOV.W rt_interrupt_from_thread, A0
+ STC ISP, [A0]
+
+ MOV.W rt_interrupt_to_thread, A0
+ LDC [A0], ISP
+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore all processor registers from the new task's stack
+ RTS ; Normal return
+
+ .EVEN
+rt_hw_timer_handler:
+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers
+ JSR rt_interrupt_enter
+ JSR rt_tick_increase
+ JSR rt_interrupt_leave
+
+ CMP.W #1,rt_thread_switch_interrput_flag
+ JEQ rt_hw_context_switch_interrupt_do
+
+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
+ REIT ; Return from interrup
+
+ .EVEN
+rt_hw_uart0_receive_handler:
+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers
+ JSR rt_interrupt_enter
+ JSR u0rec_handler
+ JSR rt_interrupt_leave
+
+ CMP.W #1, rt_thread_switch_interrput_flag
+ JEQ rt_hw_context_switch_interrupt_do
+
+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
+ REIT ; Return from interrup
+
+ END
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