diff options
| author | dzzxzz <[email protected]> | 2011-02-16 13:47:44 +0000 |
|---|---|---|
| committer | dzzxzz <[email protected]> | 2011-02-16 13:47:44 +0000 |
| commit | fac560d432d21a4aa285fa720893b7aebbbb015e (patch) | |
| tree | a585c59a8cccc2383d56a3e0c75336efba62e0b3 /libcpu/m16c | |
| parent | e01eaabee9b8ca9c4c4236dc37d5131cf3e8fe2e (diff) | |
add context_iar.S for SCONS
actually context_iar.S is the same as context_iar.asm
but context_iar.S is used for SCONS, and context_iar.asm is used for IAR
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1272 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'libcpu/m16c')
| -rw-r--r-- | libcpu/m16c/m16c62p/context_iar.S | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/libcpu/m16c/m16c62p/context_iar.S b/libcpu/m16c/m16c62p/context_iar.S new file mode 100644 index 0000000000..29c8656ba7 --- /dev/null +++ b/libcpu/m16c/m16c62p/context_iar.S @@ -0,0 +1,90 @@ +/*
+ * File : context.asm
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-04-09 fify the first version
+ * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
+ * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
+ *
+ * For : Renesas M16C
+ * Toolchain : IAR's EW for M16C v3.401
+*/
+
+ RSEG CSTACK
+
+ RSEG ISTACK
+
+ RSEG CODE(1)
+
+ EXTERN rt_thread_switch_interrput_flag
+ EXTERN rt_interrupt_from_thread
+ EXTERN rt_interrupt_to_thread
+
+ PUBLIC rt_hw_interrupt_disable
+ PUBLIC rt_hw_interrupt_enable
+ PUBLIC rt_hw_context_switch_to
+ PUBLIC rt_hw_context_switch
+ PUBLIC rt_hw_context_switch_interrupt
+ PUBLIC os_context_switch
+
+rt_hw_interrupt_disable
+ STC FLG, R0 ;fify 20100419
+ FCLR I
+ RTS
+
+rt_hw_interrupt_enable
+ LDC R0, FLG ;fify 20100419
+ RTS
+
+ .EVEN
+os_context_switch:
+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB
+ CMP.W #0,rt_thread_switch_interrput_flag
+ JEQ exit
+ MOV.W #0, rt_thread_switch_interrput_flag
+ MOV.W rt_interrupt_from_thread, A0
+ STC ISP, [A0]
+ MOV.W rt_interrupt_to_thread, A0
+ LDC [A0], ISP
+exit
+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
+ REIT ; Return from interrup
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ * this fucntion is used to perform the first thread switch
+ */
+rt_hw_context_switch_to
+ MOV.W R0, A0
+ LDC [A0], ISP
+ POPM R0,R1,R2,R3,A0,A1,SB,FB
+ REIT
+
+rt_hw_context_switch
+ CMP.W #1,rt_thread_switch_interrput_flag
+ JEQ jump1
+ MOV.W #1,rt_thread_switch_interrput_flag
+ MOV.W R0, rt_interrupt_from_thread
+jump1
+ MOV.W R1, rt_interrupt_to_thread
+ INT #0
+ RTS
+
+rt_hw_context_switch_interrupt
+ CMP.W #1,rt_thread_switch_interrput_flag
+ JEQ jump
+ MOV.W #1,rt_thread_switch_interrput_flag
+ MOV.W R0, rt_interrupt_from_thread
+jump
+ MOV.W R1, rt_interrupt_to_thread
+ RTS
+
+ END
|