diff options
| author | bernard.xiong <[email protected]> | 2010-07-14 09:51:49 +0000 |
|---|---|---|
| committer | bernard.xiong <[email protected]> | 2010-07-14 09:51:49 +0000 |
| commit | e94adf07ca3021d693003cf282f2914ef5cdac98 (patch) | |
| tree | a38c306e49086f937bf07bb627aaf735e20074c1 /libcpu/mips/common/cache.c | |
| parent | 64a7365af5a0793ef9cd2b258f6c9c84a413c6f4 (diff) | |
add init Jz47xx porting.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@792 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'libcpu/mips/common/cache.c')
| -rw-r--r-- | libcpu/mips/common/cache.c | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/libcpu/mips/common/cache.c b/libcpu/mips/common/cache.c new file mode 100644 index 0000000000..de9a112f50 --- /dev/null +++ b/libcpu/mips/common/cache.c @@ -0,0 +1,114 @@ +/*
+ * File : cache.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-05-17 swkyer first version
+ */
+#include <rtthread.h>
+#include "mipscfg.h"
+#include "cache.h"
+
+
+extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
+void r4k_cache_init(void)
+{
+ cache_init(dcache_size, cpu_dcache_line_size());
+}
+
+void r4k_cache_flush_all(void)
+{
+ blast_dcache16();
+ blast_icache16();
+}
+
+void r4k_icache_flush_all(void)
+{
+ blast_icache16();
+}
+
+void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
+{
+ rt_ubase_t end, a;
+
+ if (size > icache_size)
+ {
+ blast_icache16();
+ }
+ else
+ {
+ rt_ubase_t ic_lsize = cpu_icache_line_size();
+
+ a = addr & ~(ic_lsize - 1);
+ end = ((addr + size) - 1) & ~(ic_lsize - 1);
+ while (1)
+ {
+ flush_icache_line(a);
+ if (a == end)
+ break;
+ a += ic_lsize;
+ }
+ }
+}
+
+void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
+{
+ rt_ubase_t end, a;
+ rt_ubase_t ic_lsize = cpu_icache_line_size();
+
+ a = addr & ~(ic_lsize - 1);
+ end = ((addr + size) - 1) & ~(ic_lsize - 1);
+ while (1)
+ {
+ lock_icache_line(a);
+ if (a == end)
+ break;
+ a += ic_lsize;
+ }
+}
+
+void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
+{
+ rt_ubase_t end, a;
+ rt_ubase_t dc_lsize = cpu_dcache_line_size();
+
+ a = addr & ~(dc_lsize - 1);
+ end = ((addr + size) - 1) & ~(dc_lsize - 1);
+ while (1)
+ {
+ invalidate_dcache_line(a);
+ if (a == end)
+ break;
+ a += dc_lsize;
+ }
+}
+
+void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
+{
+ rt_ubase_t end, a;
+
+ if (size >= dcache_size)
+ {
+ blast_dcache16();
+ }
+ else
+ {
+ rt_ubase_t dc_lsize = cpu_dcache_line_size();
+
+ a = addr & ~(dc_lsize - 1);
+ end = ((addr + size) - 1) & ~(dc_lsize - 1);
+ while (1)
+ {
+ flush_dcache_line(a);
+ if (a == end)
+ break;
+ a += dc_lsize;
+ }
+ }
+}
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