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authorlizhirui <[email protected]>2021-05-18 09:54:11 +0800
committerlizhirui <[email protected]>2021-05-18 09:54:11 +0800
commit9a4e270f9770f778128ffdabe94f101416ce8c61 (patch)
tree9df43fbcc25c3f288ed6fdecd65909d4094d849f /libcpu/mips/common
parente7fc0c89d2367533dcd1b77e46acaeea7bc3f876 (diff)
parent4e9e3f79a565bb4fdc1d96deda18f9c771aeb0c9 (diff)
Merge branch 'RT-Thread:master' into master
Diffstat (limited to 'libcpu/mips/common')
-rw-r--r--libcpu/mips/common/asm.h330
-rw-r--r--libcpu/mips/common/exception.c4
-rw-r--r--libcpu/mips/common/exception.h2
-rw-r--r--libcpu/mips/common/mips.h2
-rw-r--r--libcpu/mips/common/mips_addrspace.h140
-rw-r--r--libcpu/mips/common/mips_cache.c34
-rw-r--r--libcpu/mips/common/mips_cache.h114
-rw-r--r--libcpu/mips/common/mips_cfg.h20
-rw-r--r--libcpu/mips/common/mips_fpu.h2
-rw-r--r--libcpu/mips/common/mips_regs.h1344
-rw-r--r--libcpu/mips/common/mips_types.h18
-rw-r--r--libcpu/mips/common/ptrace.h96
-rw-r--r--libcpu/mips/common/stack.c12
-rw-r--r--libcpu/mips/common/stackframe.h234
14 files changed, 1148 insertions, 1204 deletions
diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index 1b39eea05a..355c05ab39 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -1,7 +1,7 @@
/*
* Assembly Macros For MIPS
*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -18,101 +18,101 @@
/*
* LEAF - declare leaf routine
*/
-#define LEAF(symbol) \
- .globl symbol; \
- .align 2; \
- .type symbol,@function; \
- .ent symbol,0; \
-symbol: .frame sp,0,ra
+#define LEAF(symbol) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol,@function; \
+ .ent symbol,0; \
+symbol: .frame sp,0,ra
/*
* NESTED - declare nested routine entry point
*/
-#define NESTED(symbol, framesize, rpc) \
- .globl symbol; \
- .align 2; \
- .type symbol,@function; \
- .ent symbol,0; \
-symbol: .frame sp, framesize, rpc
+#define NESTED(symbol, framesize, rpc) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol,@function; \
+ .ent symbol,0; \
+symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
-#define END(function) \
- .end function; \
- .size function,.-function
+#define END(function) \
+ .end function; \
+ .size function,.-function
/*
* EXPORT - export definition of symbol
*/
-#define EXPORT(symbol) \
- .globl symbol; \
+#define EXPORT(symbol) \
+ .globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
-#define FEXPORT(symbol) \
- .globl symbol; \
- .type symbol,@function; \
+#define FEXPORT(symbol) \
+ .globl symbol; \
+ .type symbol,@function; \
symbol:
/*
* Global data declaration with size.
*/
-#define EXPORTS(name,sz) \
- .globl name; \
- .type name,@object; \
- .size name,sz; \
+#define EXPORTS(name,sz) \
+ .globl name; \
+ .type name,@object; \
+ .size name,sz; \
name:
/*
* Weak data declaration with size.
*/
-#define WEXPORT(name,sz) \
- .weakext name; \
- .type name,@object; \
- .size name,sz; \
+#define WEXPORT(name,sz) \
+ .weakext name; \
+ .type name,@object; \
+ .size name,sz; \
name:
/*
* Global data reference with size.
*/
-#define IMPORT(name, size) \
- .extern name,size
+#define IMPORT(name, size) \
+ .extern name,size
/*
* Global zeroed data.
*/
-#define BSS(name,size) \
- .type name,@object; \
- .comm name,size
+#define BSS(name,size) \
+ .type name,@object; \
+ .comm name,size
/*
* Local zeroed data.
*/
-#define LBSS(name,size) \
- .lcomm name,size
+#define LBSS(name,size) \
+ .lcomm name,size
/*
* ABS - export absolute symbol
*/
-#define ABS(symbol,value) \
- .globl symbol; \
-symbol = value
+#define ABS(symbol,value) \
+ .globl symbol; \
+symbol = value
-#define TEXT(msg) \
- .pushsection .data; \
-8: .asciiz msg; \
+#define TEXT(msg) \
+ .pushsection .data; \
+8: .asciiz msg; \
.popsection;
-#define ENTRY(name) \
- .globl name; \
- .align 2; \
- .ent name,0; \
+#define ENTRY(name) \
+ .globl name; \
+ .align 2; \
+ .ent name,0; \
name##:
/*
@@ -122,185 +122,185 @@ symbol = value
/*
* Size of a register
*/
-#define SZREG 8
+#define SZREG 8
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
-#define REG_S sd
-#define REG_L ld
-#define REG_SUBU dsubu
-#define REG_ADDU daddu
+#define REG_S sd
+#define REG_L ld
+#define REG_SUBU dsubu
+#define REG_ADDU daddu
/*
* How to add/sub/load/store/shift C int variables.
*/
-#define INT_ADD dadd
-#define INT_ADDU daddu
-#define INT_ADDI daddi
-#define INT_ADDIU daddiu
-#define INT_SUB dsub
-#define INT_SUBU dsubu
-#define INT_L ld
-#define INT_S sd
-#define INT_SLL dsll
-#define INT_SLLV dsllv
-#define INT_SRL dsrl
-#define INT_SRLV dsrlv
-#define INT_SRA dsra
-#define INT_SRAV dsrav
+#define INT_ADD dadd
+#define INT_ADDU daddu
+#define INT_ADDI daddi
+#define INT_ADDIU daddiu
+#define INT_SUB dsub
+#define INT_SUBU dsubu
+#define INT_L ld
+#define INT_S sd
+#define INT_SLL dsll
+#define INT_SLLV dsllv
+#define INT_SRL dsrl
+#define INT_SRLV dsrlv
+#define INT_SRA dsra
+#define INT_SRAV dsrav
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
-#define LONG_ADD dadd
-#define LONG_ADDU daddu
-#define LONG_ADDI daddi
-#define LONG_ADDIU daddiu
-#define LONG_SUB dsub
-#define LONG_SUBU dsubu
-#define LONG_L ld
-#define LONG_S sd
-#define LONG_SP sdp
-#define LONG_SLL dsll
-#define LONG_SLLV dsllv
-#define LONG_SRL dsrl
-#define LONG_SRLV dsrlv
-#define LONG_SRA dsra
-#define LONG_SRAV dsrav
+#define LONG_ADD dadd
+#define LONG_ADDU daddu
+#define LONG_ADDI daddi
+#define LONG_ADDIU daddiu
+#define LONG_SUB dsub
+#define LONG_SUBU dsubu
+#define LONG_L ld
+#define LONG_S sd
+#define LONG_SP sdp
+#define LONG_SLL dsll
+#define LONG_SLLV dsllv
+#define LONG_SRL dsrl
+#define LONG_SRLV dsrlv
+#define LONG_SRA dsra
+#define LONG_SRAV dsrav
-#define LONG .dword
-#define LONGSIZE 8
-#define LONGMASK 7
-#define LONGLOG 3
+#define LONG .dword
+#define LONGSIZE 8
+#define LONGMASK 7
+#define LONGLOG 3
/*
* How to add/sub/load/store/shift pointers.
*/
-#define PTR_ADD dadd
-#define PTR_ADDU daddu
-#define PTR_ADDI daddi
-#define PTR_ADDIU daddiu
-#define PTR_SUB dsub
-#define PTR_SUBU dsubu
-#define PTR_L ld
-#define PTR_S sd
-#define PTR_LA dla
-#define PTR_LI dli
-#define PTR_SLL dsll
-#define PTR_SLLV dsllv
-#define PTR_SRL dsrl
-#define PTR_SRLV dsrlv
-#define PTR_SRA dsra
-#define PTR_SRAV dsrav
+#define PTR_ADD dadd
+#define PTR_ADDU daddu
+#define PTR_ADDI daddi
+#define PTR_ADDIU daddiu
+#define PTR_SUB dsub
+#define PTR_SUBU dsubu
+#define PTR_L ld
+#define PTR_S sd
+#define PTR_LA dla
+#define PTR_LI dli
+#define PTR_SLL dsll
+#define PTR_SLLV dsllv
+#define PTR_SRL dsrl
+#define PTR_SRLV dsrlv
+#define PTR_SRA dsra
+#define PTR_SRAV dsrav
-#define PTR_SCALESHIFT 3
+#define PTR_SCALESHIFT 3
-#define PTR .dword
-#define PTRSIZE 8
-#define PTRLOG 3
+#define PTR .dword
+#define PTRSIZE 8
+#define PTRLOG 3
-#define MFC0 dmfc0
-#define MTC0 dmtc0
+#define MFC0 dmfc0
+#define MTC0 dmtc0
#else
/*
* Size of a register
*/
-#define SZREG 4
+#define SZREG 4
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
-#define REG_S sw
-#define REG_L lw
-#define REG_SUBU subu
-#define REG_ADDU addu
+#define REG_S sw
+#define REG_L lw
+#define REG_SUBU subu
+#define REG_ADDU addu
/*
* How to add/sub/load/store/shift C int variables.
*/
-#define INT_ADD add
-#define INT_ADDU addu
-#define INT_ADDI addi
-#define INT_ADDIU addiu
-#define INT_SUB sub
-#define INT_SUBU subu
-#define INT_L lw
-#define INT_S sw
-#define INT_SLL sll
-#define INT_SLLV sllv
-#define INT_SRL srl
-#define INT_SRLV srlv
-#define INT_SRA sra
-#define INT_SRAV srav
+#define INT_ADD add
+#define INT_ADDU addu
+#define INT_ADDI addi
+#define INT_ADDIU addiu
+#define INT_SUB sub
+#define INT_SUBU subu
+#define INT_L lw
+#define INT_S sw
+#define INT_SLL sll
+#define INT_SLLV sllv
+#define INT_SRL srl
+#define INT_SRLV srlv
+#define INT_SRA sra
+#define INT_SRAV srav
/*
* How to add/sub/load/store/shift C long variables.
*/
-#define LONG_ADD add
-#define LONG_ADDU addu
-#define LONG_ADDI addi
-#define LONG_ADDIU addiu
-#define LONG_SUB sub
-#define LONG_SUBU subu
-#define LONG_L lw
-#define LONG_S sw
-#define LONG_SLL sll
-#define LONG_SLLV sllv
-#define LONG_SRL srl
-#define LONG_SRLV srlv
-#define LONG_SRA sra
-#define LONG_SRAV srav
+#define LONG_ADD add
+#define LONG_ADDU addu
+#define LONG_ADDI addi
+#define LONG_ADDIU addiu
+#define LONG_SUB sub
+#define LONG_SUBU subu
+#define LONG_L lw
+#define LONG_S sw
+#define LONG_SLL sll
+#define LONG_SLLV sllv
+#define LONG_SRL srl
+#define LONG_SRLV srlv
+#define LONG_SRA sra
+#define LONG_SRAV srav
-#define LONG .word
-#define LONGSIZE 4
-#define LONGMASK 3
-#define LONGLOG 2
+#define LONG .word
+#define LONGSIZE 4
+#define LONGMASK 3
+#define LONGLOG 2
/*
* How to add/sub/load/store/shift pointers.
*/
-#define PTR_ADD add
-#define PTR_ADDU addu
-#define PTR_ADDI addi
-#define PTR_ADDIU addiu
-#define PTR_SUB sub
-#define PTR_SUBU subu
-#define PTR_L lw
-#define PTR_S sw
-#define PTR_LA la
-#define PTR_SLL sll
-#define PTR_SLLV sllv
-#define PTR_SRL srl
-#define PTR_SRLV srlv
-#define PTR_SRA sra
-#define PTR_SRAV srav
+#define PTR_ADD add
+#define PTR_ADDU addu
+#define PTR_ADDI addi
+#define PTR_ADDIU addiu
+#define PTR_SUB sub
+#define PTR_SUBU subu
+#define PTR_L lw
+#define PTR_S sw
+#define PTR_LA la
+#define PTR_SLL sll
+#define PTR_SLLV sllv
+#define PTR_SRL srl
+#define PTR_SRLV srlv
+#define PTR_SRA sra
+#define PTR_SRAV srav
-#define PTR_SCALESHIFT 2
+#define PTR_SCALESHIFT 2
-#define PTR .word
-#define PTRSIZE 4
-#define PTRLOG 2
+#define PTR .word
+#define PTRSIZE 4
+#define PTRLOG 2
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
-#define MFC0 mfc0
-#define MTC0 mtc0
+#define MFC0 mfc0
+#define MTC0 mtc0
#endif
-#define SSNOP sll zero, zero, 1
+#define SSNOP sll zero, zero, 1
#endif /* end of __ASM_H__ */
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index 3da8ecead6..9c9858f5e1 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -164,7 +164,7 @@ void rt_general_exc_dispatch(struct pt_regs *regs)
{
rt_ubase_t cause, exccode;
cause = read_c0_cause();
- exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
+ exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
if (exccode == 0)
{
diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h
index 68107f6235..af9312b5bc 100644
--- a/libcpu/mips/common/exception.h
+++ b/libcpu/mips/common/exception.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h
index 94f664308c..abe3b73945 100644
--- a/libcpu/mips/common/mips.h
+++ b/libcpu/mips/common/mips.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h
index f3bb60662e..0bc6a5f181 100644
--- a/libcpu/mips/common/mips_addrspace.h
+++ b/libcpu/mips/common/mips_addrspace.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -19,15 +19,15 @@
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
-#define _CONST64_(x) x
+#define _CONST64_(x) x
#else
-#define _ATYPE_ __PTRDIFF_TYPE__
-#define _ATYPE32_ int
-#define _ATYPE64_ __s64
+#define _ATYPE_ __PTRDIFF_TYPE__
+#define _ATYPE32_ int
+#define _ATYPE64_ __s64
#ifdef ARCH_MIPS64
-#define _CONST64_(x) x ## L
+#define _CONST64_(x) x ## L
#else
-#define _CONST64_(x) x ## LL
+#define _CONST64_(x) x ## LL
#endif
#endif
@@ -38,21 +38,21 @@
#define _ACAST32_
#define _ACAST64_
#else
-#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
-#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
+#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
+#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
#endif
/*
* Returns the kernel segment base of a given address
*/
-#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
+#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
/*
* Returns the physical address of a CKSEGx / XKPHYS address
*/
-#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
-#define XPHYSADDR(a) ((_ACAST64_(a)) & \
- _CONST64_(0x000000ffffffffff))
+#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a) ((_ACAST64_(a)) & \
+ _CONST64_(0x000000ffffffffff))
#ifdef ARCH_MIPS64
@@ -61,56 +61,56 @@
* The compatibility segments use the full 64-bit sign extended value. Note
* the R8000 doesn't have them so don't reference these in generic MIPS code.
*/
-#define XKUSEG _CONST64_(0x0000000000000000)
-#define XKSSEG _CONST64_(0x4000000000000000)
-#define XKPHYS _CONST64_(0x8000000000000000)
-#define XKSEG _CONST64_(0xc000000000000000)
-#define CKSEG0 _CONST64_(0xffffffff80000000)
-#define CKSEG1 _CONST64_(0xffffffffa0000000)
-#define CKSSEG _CONST64_(0xffffffffc0000000)
-#define CKSEG3 _CONST64_(0xffffffffe0000000)
+#define XKUSEG _CONST64_(0x0000000000000000)
+#define XKSSEG _CONST64_(0x4000000000000000)
+#define XKPHYS _CONST64_(0x8000000000000000)
+#define XKSEG _CONST64_(0xc000000000000000)
+#define CKSEG0 _CONST64_(0xffffffff80000000)
+#define CKSEG1 _CONST64_(0xffffffffa0000000)
+#define CKSSEG _CONST64_(0xffffffffc0000000)
+#define CKSEG3 _CONST64_(0xffffffffe0000000)
-#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
-#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
-#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
-#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
+#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
-#define KUSEGBASE 0xffffffff00000000
-#define KSEG0BASE 0xffffffff80000000
-#define KSEG1BASE 0xffffffffa0000000
-#define KSEG2BASE 0xffffffffc0000000
-#define KSEG3BASE 0xffffffffe0000000
+#define KUSEGBASE 0xffffffff00000000
+#define KSEG0BASE 0xffffffff80000000
+#define KSEG1BASE 0xffffffffa0000000
+#define KSEG2BASE 0xffffffffc0000000
+#define KSEG3BASE 0xffffffffe0000000
#else
-#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
-#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
-#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
-#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
+#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
+#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
+#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
+#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
/*
* Map an address to a certain kernel segment
*/
-#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
-#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
-#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
-#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
+#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
+#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
+#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
+#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
-#define CKUSEG 0x00000000
-#define CKSEG0 0x80000000
-#define CKSEG1 0xa0000000
-#define CKSEG2 0xc0000000
-#define CKSEG3 0xe0000000
+#define CKUSEG 0x00000000
+#define CKSEG0 0x80000000
+#define CKSEG1 0xa0000000
+#define CKSEG2 0xc0000000
+#define CKSEG3 0xe0000000
/*
* Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe.
*/
-#define KUSEGBASE 0x00000000
-#define KSEG0BASE 0x80000000
-#define KSEG1BASE 0xa0000000
-#define KSEG2BASE 0xc0000000
-#define KSEG3BASE 0xe0000000
+#define KUSEGBASE 0x00000000
+#define KSEG0BASE 0x80000000
+#define KSEG1BASE 0xa0000000
+#define KSEG2BASE 0xc0000000
+#define KSEG3BASE 0xe0000000
#endif
@@ -118,23 +118,23 @@
/*
* Cache modes for XKPHYS address conversion macros
*/
-#define K_CALG_COH_EXCL1_NOL2 0
-#define K_CALG_COH_SHRL1_NOL2 1
-#define K_CALG_UNCACHED 2
-#define K_CALG_NONCOHERENT 3
-#define K_CALG_COH_EXCL 4
-#define K_CALG_COH_SHAREABLE 5
-#define K_CALG_NOTUSED 6
-#define K_CALG_UNCACHED_ACCEL 7
+#define K_CALG_COH_EXCL1_NOL2 0
+#define K_CALG_COH_SHRL1_NOL2 1
+#define K_CALG_UNCACHED 2
+#define K_CALG_NONCOHERENT 3
+#define K_CALG_COH_EXCL 4
+#define K_CALG_COH_SHAREABLE 5
+#define K_CALG_NOTUSED 6
+#define K_CALG_UNCACHED_ACCEL 7
/*
* 64-bit address conversions
*/
-#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
-#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
-#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
- (_CONST64_(cm) << 59) | (a))
+#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
+ (_CONST64_(cm) << 59) | (a))
/*
* Returns the uncached address of a sdram address
@@ -146,20 +146,20 @@
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
* R8000 implements most with its 48-bit physical address space.
*/
-#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
-#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
-#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
+#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
-#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
-#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
+#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
#endif
#ifndef __ASSEMBLY__
-#define REG8( addr ) (*(volatile u8 *) (addr))
-#define REG16( addr ) (*(volatile u16 *)(addr))
-#define REG32( addr ) (*(volatile u32 *)(addr))
-#define REG64( addr ) (*(volatile u64 *)(addr))
+#define REG8( addr ) (*(volatile u8 *) (addr))
+#define REG16( addr ) (*(volatile u16 *)(addr))
+#define REG32( addr ) (*(volatile u32 *)(addr))
+#define REG64( addr ) (*(volatile u64 *)(addr))
#endif
#endif /* _MIPS_ADDRSPACE_H_ */
diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c
index 8c86bb131a..a969f5c751 100644
--- a/libcpu/mips/common/mips_cache.c
+++ b/libcpu/mips/common/mips_cache.c
@@ -1,21 +1,7 @@
/*
- * File : mips_cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@@ -28,7 +14,7 @@
extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
void r4k_cache_init(void)
{
-// cache_init(dcache_size, cpu_dcache_line_size);
+// cache_init(dcache_size, cpu_dcache_line_size);
}
void r4k_cache_flush_all(void)
@@ -45,7 +31,7 @@ void r4k_icache_flush_all(void)
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
{
- rt_ubase_t end, a;
+ rt_ubase_t end, a;
if (size > g_mips_core.icache_size)
{
@@ -53,7 +39,7 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
}
else
{
- rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+ rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
@@ -69,8 +55,8 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
{
- rt_ubase_t end, a;
- rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+ rt_ubase_t end, a;
+ rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
@@ -85,7 +71,7 @@ void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
{
- rt_ubase_t end, a;
+ rt_ubase_t end, a;
rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
a = addr & ~(dc_lsize - 1);
@@ -101,7 +87,7 @@ void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
{
- rt_ubase_t end, a;
+ rt_ubase_t end, a;
if (size >= g_mips_core.dcache_size)
{
@@ -109,7 +95,7 @@ void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
}
else
{
- rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
+ rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
a = addr & ~(dc_lsize - 1);
end = ((addr + size) - 1) & ~(dc_lsize - 1);
diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h
index 438dd76cde..4a459b1ae4 100644
--- a/libcpu/mips/common/mips_cache.h
+++ b/libcpu/mips/common/mips_cache.h
@@ -1,21 +1,7 @@
/*
- * File : mips_cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@@ -116,7 +102,7 @@ enum dma_data_direction
#define INDEX_STORE_DATA_D 0x1d
#define INDEX_STORE_DATA_S 0x1f
-#define cache_op(op, addr) \
+#define cache_op(op, addr) \
__asm__ __volatile__( \
".set push\n" \
".set noreorder\n" \
@@ -126,95 +112,95 @@ enum dma_data_direction
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
-#define cache16_unroll32(base, op) \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " .set mips3 \n" \
- " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
- " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
- " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
- " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
- " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
- " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
- " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
- " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
- " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
- " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
- " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
- " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
- " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
- " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
- " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
- " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
- " .set mips0 \n" \
- " .set reorder \n" \
- : \
- : "r" (base), \
- "i" (op));
+#define cache16_unroll32(base, op) \
+ __asm__ __volatile__( \
+ " .set noreorder \n" \
+ " .set mips3 \n" \
+ " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
+ " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
+ " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
+ " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
+ " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
+ " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
+ " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
+ " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
+ " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
+ " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
+ " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
+ " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
+ " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
+ " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
+ " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
+ " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
+ " .set mips0 \n" \
+ " .set reorder \n" \
+ : \
+ : "r" (base), \
+ "i" (op));
static inline void flush_icache_line_indexed(rt_ubase_t addr)
{
- cache_op(INDEX_INVALIDATE_I, addr);
+ cache_op(INDEX_INVALIDATE_I, addr);
}
static inline void flush_dcache_line_indexed(rt_ubase_t addr)
{
- cache_op(INDEX_WRITEBACK_INV_D, addr);
+ cache_op(INDEX_WRITEBACK_INV_D, addr);
}
static inline void flush_icache_line(rt_ubase_t addr)
{
- cache_op(HIT_INVALIDATE_I, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
static inline void lock_icache_line(rt_ubase_t addr)
{
- cache_op(FETCH_AND_LOCK_I, addr);
+ cache_op(FETCH_AND_LOCK_I, addr);
}
static inline void lock_dcache_line(rt_ubase_t addr)
{
- cache_op(FETCH_AND_LOCK_D, addr);
+ cache_op(FETCH_AND_LOCK_D, addr);
}
static inline void flush_dcache_line(rt_ubase_t addr)
{
- cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
static inline void invalidate_dcache_line(rt_ubase_t addr)
{
- cache_op(HIT_INVALIDATE_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
static inline void blast_dcache16(void)
{
- rt_ubase_t start = KSEG0BASE;
- rt_ubase_t end = start + g_mips_core.dcache_size;
- rt_ubase_t addr;
+ rt_ubase_t start = KSEG0BASE;
+ rt_ubase_t end = start + g_mips_core.dcache_size;
+ rt_ubase_t addr;
- for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
- cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
+ for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+ cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
}
static inline void inv_dcache16(void)
{
- rt_ubase_t start = KSEG0BASE;
- rt_ubase_t end = start + g_mips_core.dcache_size;
- rt_ubase_t addr;
+ rt_ubase_t start = KSEG0BASE;
+ rt_ubase_t end = start + g_mips_core.dcache_size;
+ rt_ubase_t addr;
- for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
- cache16_unroll32(addr, HIT_INVALIDATE_D);
+ for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+ cache16_unroll32(addr, HIT_INVALIDATE_D);
}
static inline void blast_icache16(void)
{
- rt_ubase_t start = KSEG0BASE;
- rt_ubase_t end = start + g_mips_core.icache_size;
- rt_ubase_t addr;
+ rt_ubase_t start = KSEG0BASE;
+ rt_ubase_t end = start + g_mips_core.icache_size;
+ rt_ubase_t addr;
- for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
- cache16_unroll32(addr, INDEX_INVALIDATE_I);
+ for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
+ cache16_unroll32(addr, INDEX_INVALIDATE_I);
}
void r4k_cache_init(void);
diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h
index f7e38b4af4..d5531e35fb 100644
--- a/libcpu/mips/common/mips_cfg.h
+++ b/libcpu/mips/common/mips_cfg.h
@@ -1,21 +1,7 @@
/*
- * File : mips_cfg.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@@ -38,7 +24,7 @@ typedef struct mips32_core_cfg
uint16_t dcache_ways;
uint16_t dcache_size;
- uint16_t max_tlb_entries; /* number of tlb entry */
+ uint16_t max_tlb_entries; /* number of tlb entry */
} mips32_core_cfg_t;
extern mips32_core_cfg_t g_mips_core;
diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h
index 50df3746a5..85aa125fa3 100644
--- a/libcpu/mips/common/mips_fpu.h
+++ b/libcpu/mips/common/mips_fpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index a13e24b539..a2f6053cf5 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -11,129 +11,129 @@
#ifndef _MIPS_REGS_H_
#define _MIPS_REGS_H_
#include <rtconfig.h>
-#define REG_A0 4
-#define REG_SP 29
-#define REG_GP 28
-#define REG_FP 30
-#define REG_RA 31
+#define REG_A0 4
+#define REG_SP 29
+#define REG_GP 28
+#define REG_FP 30
+#define REG_RA 31
#ifndef ARCH_MIPS64
-#define zero $0 /* wired zero */
-#define AT $1 /* assembler temp - uppercase because of ".set at" */
-#define v0 $2 /* return value */
-#define v1 $3
-#define a0 $4 /* argument registers */
-#define a1 $5
-#define a2 $6
-#define a3 $7
-#define t0 $8 /* caller saved */
-#define t1 $9
-#define t2 $10
-#define t3 $11
-#define t4 $12
-#define ta0 $12
-#define t5 $13
-#define ta1 $13
-#define t6 $14
-#define ta2 $14
-#define t7 $15
-#define ta3 $15
-#define s0 $16 /* callee saved */
-#define s1 $17
-#define s2 $18
-#define s3 $19
-#define s4 $20
-#define s5 $21
-#define s6 $22
-#define s7 $23
-#define t8 $24 /* caller saved */
-#define t9 $25
-#define jp $25 /* PIC jump register */
-#define k0 $26 /* kernel scratch */
-#define k1 $27
-#define gp $28 /* global pointer */
-#define sp $29 /* stack pointer */
-#define fp $30 /* frame pointer */
-#define s8 $30 /* same like fp! */
-#define ra $31 /* return address */
+#define zero $0 /* wired zero */
+#define AT $1 /* assembler temp - uppercase because of ".set at" */
+#define v0 $2 /* return value */
+#define v1 $3
+#define a0 $4 /* argument registers */
+#define a1 $5
+#define a2 $6
+#define a3 $7
+#define t0 $8 /* caller saved */
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define ta0 $12
+#define t5 $13
+#define ta1 $13
+#define t6 $14
+#define ta2 $14
+#define t7 $15
+#define ta3 $15
+#define s0 $16 /* callee saved */
+#define s1 $17
+#define s2 $18
+#define s3 $19
+#define s4 $20
+#define s5 $21
+#define s6 $22
+#define s7 $23
+#define t8 $24 /* caller saved */
+#define t9 $25
+#define jp $25 /* PIC jump register */
+#define k0 $26 /* kernel scratch */
+#define k1 $27
+#define gp $28 /* global pointer */
+#define sp $29 /* stack pointer */
+#define fp $30 /* frame pointer */
+#define s8 $30 /* same like fp! */
+#define ra $31 /* return address */
#else
-#define zero $0 /* wired zero */
-#define AT $at /* assembler temp - uppercase because of ".set at" */
-#define v0 $2 /* return value - caller saved */
-#define v1 $3
-#define a0 $4 /* argument registers */
-#define a1 $5
-#define a2 $6
-#define a3 $7
-#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
-#define ta0 $8
-#define a5 $9
-#define ta1 $9
-#define a6 $10
-#define ta2 $10
-#define a7 $11
-#define ta3 $11
-#define t0 $12 /* caller saved */
-#define t1 $13
-#define t2 $14
-#define t3 $15
-#define s0 $16 /* callee saved */
-#define s1 $17
-#define s2 $18
-#define s3 $19
-#define s4 $20
-#define s5 $21
-#define s6 $22
-#define s7 $23
-#define t8 $24 /* caller saved */
-#define t9 $25 /* callee address for PIC/temp */
-#define jp $25 /* PIC jump register */
-#define k0 $26 /* kernel temporary */
-#define k1 $27
-#define gp $28 /* global pointer - caller saved for PIC */
-#define sp $29 /* stack pointer */
-#define fp $30 /* frame pointer */
-#define s8 $30 /* callee saved */
-#define ra $31 /* return address */
+#define zero $0 /* wired zero */
+#define AT $at /* assembler temp - uppercase because of ".set at" */
+#define v0 $2 /* return value - caller saved */
+#define v1 $3
+#define a0 $4 /* argument registers */
+#define a1 $5
+#define a2 $6
+#define a3 $7
+#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
+#define ta0 $8
+#define a5 $9
+#define ta1 $9
+#define a6 $10
+#define ta2 $10
+#define a7 $11
+#define ta3 $11
+#define t0 $12 /* caller saved */
+#define t1 $13
+#define t2 $14
+#define t3 $15
+#define s0 $16 /* callee saved */
+#define s1 $17
+#define s2 $18
+#define s3 $19
+#define s4 $20
+#define s5 $21
+#define s6 $22
+#define s7 $23
+#define t8 $24 /* caller saved */
+#define t9 $25 /* callee address for PIC/temp */
+#define jp $25 /* PIC jump register */
+#define k0 $26 /* kernel temporary */
+#define k1 $27
+#define gp $28 /* global pointer - caller saved for PIC */
+#define sp $29 /* stack pointer */
+#define fp $30 /* frame pointer */
+#define s8 $30 /* callee saved */
+#define ra $31 /* return address */
#endif
-#define fv0 $f0 /* return value */
-#define fv0f $f1
-#define fv1 $f2
-#define fv1f $f3
-#define fa0 $f12 /* argument registers */
-#define fa0f $f13
-#define fa1 $f14
-#define fa1f $f15
-#define ft0 $f4 /* caller saved */
-#define ft0f $f5
-#define ft1 $f6
-#define ft1f $f7
-#define ft2 $f8
-#define ft2f $f9
-#define ft3 $f10
-#define ft3f $f11
-#define ft4 $f16
-#define ft4f $f17
-#define ft5 $f18
-#define ft5f $f19
-#define fs0 $f20 /* callee saved */
-#define fs0f $f21
-#define fs1 $f22
-#define fs1f $f23
-#define fs2 $f24
-#define fs2f $f25
-#define fs3 $f26
-#define fs3f $f27
-#define fs4 $f28
-#define fs4f $f29
-#define fs5 $f30
-#define fs5f $f31
+#define fv0 $f0 /* return value */
+#define fv0f $f1
+#define fv1 $f2
+#define fv1f $f3
+#define fa0 $f12 /* argument registers */
+#define fa0f $f13
+#define fa1 $f14
+#define fa1f $f15
+#define ft0 $f4 /* caller saved */
+#define ft0f $f5
+#define ft1 $f6
+#define ft1f $f7
+#define ft2 $f8
+#define ft2f $f9
+#define ft3 $f10
+#define ft3f $f11
+#define ft4 $f16
+#define ft4f $f17
+#define ft5 $f18
+#define ft5f $f19
+#define fs0 $f20 /* callee saved */
+#define fs0f $f21
+#define fs1 $f22
+#define fs1f $f23
+#define fs2 $f24
+#define fs2f $f25
+#define fs3 $f26
+#define fs3f $f27
+#define fs4 $f28
+#define fs4f $f29
+#define fs5 $f30
+#define fs5f $f31
-#define fcr31 $31 /* FPU status register */
+#define fcr31 $31 /* FPU status register */
/*
@@ -217,157 +217,157 @@
/*
* TX39 Series
*/
-#define CP0_TX39_CACHE $7
+#define CP0_TX39_CACHE $7
/*
* Coprocessor 1 (FPU) register names
*/
-#define CP1_REVISION $0
-#define CP1_UFR $1
-#define CP1_UNFR $4
-#define CP1_FCCR $25
-#define CP1_FEXR $26
-#define CP1_FENR $28
-#define CP1_STATUS $31
+#define CP1_REVISION $0
+#define CP1_UFR $1
+#define CP1_UNFR $4
+#define CP1_FCCR $25
+#define CP1_FEXR $26
+#define CP1_FENR $28
+#define CP1_STATUS $31
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
-#define MIPS_FPIR_S (_ULCAST_(1) << 16)
-#define MIPS_FPIR_D (_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
-#define MIPS_FPIR_W (_ULCAST_(1) << 20)
-#define MIPS_FPIR_L (_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
-#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
-#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
-#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
+#define MIPS_FPIR_S (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
*/
-#define MIPS_FCCR_CONDX_S 0
-#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
-#define MIPS_FCCR_COND0_S 0
-#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
-#define MIPS_FCCR_COND1_S 1
-#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
-#define MIPS_FCCR_COND2_S 2
-#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
-#define MIPS_FCCR_COND3_S 3
-#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
-#define MIPS_FCCR_COND4_S 4
-#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
-#define MIPS_FCCR_COND5_S 5
-#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
-#define MIPS_FCCR_COND6_S 6
-#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
-#define MIPS_FCCR_COND7_S 7
-#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
+#define MIPS_FCCR_CONDX_S 0
+#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S 0
+#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S 1
+#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S 2
+#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S 3
+#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S 4
+#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S 5
+#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S 6
+#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S 7
+#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
*/
-#define MIPS_FENR_FS_S 2
-#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
+#define MIPS_FENR_FS_S 2
+#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
/*
* FPU Status Register Values
*/
-#define FPU_CSR_COND_S 23 /* $fcc0 */
-#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
+#define FPU_CSR_COND_S 23 /* $fcc0 */
+#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
-#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
-#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
+#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
+#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
#define FPU_CSR_FO 0x00400000
#define FPU_CSR_FN 0x00200000
-#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
-#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
-#define FPU_CSR_COND1_S 25 /* $fcc1 */
-#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
-#define FPU_CSR_COND2_S 26 /* $fcc2 */
-#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
-#define FPU_CSR_COND3_S 27 /* $fcc3 */
-#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
-#define FPU_CSR_COND4_S 28 /* $fcc4 */
-#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
-#define FPU_CSR_COND5_S 29 /* $fcc5 */
-#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
-#define FPU_CSR_COND6_S 30 /* $fcc6 */
-#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
-#define FPU_CSR_COND7_S 31 /* $fcc7 */
-#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
+#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
+#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S 25 /* $fcc1 */
+#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S 26 /* $fcc2 */
+#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S 27 /* $fcc3 */
+#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S 28 /* $fcc4 */
+#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S 29 /* $fcc5 */
+#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S 30 /* $fcc6 */
+#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S 31 /* $fcc7 */
+#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
/*
* Bits 22:20 of the FPU Status Register will be read as 0,
* and should be written as zero.
*/
-#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
+#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
-#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
-#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
+#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
/*
* X the exception cause indicator
* E the exception enable
* S the sticky/flag bit
*/
-#define FPU_CSR_ALL_X 0x0003f000
-#define FPU_CSR_UNI_X 0x00020000
-#define FPU_CSR_INV_X 0x00010000
-#define FPU_CSR_DIV_X 0x00008000
-#define FPU_CSR_OVF_X 0x00004000
-#define FPU_CSR_UDF_X 0x00002000
-#define FPU_CSR_INE_X 0x00001000
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X 0x00020000
+#define FPU_CSR_INV_X 0x00010000
+#define FPU_CSR_DIV_X 0x00008000
+#define FPU_CSR_OVF_X 0x00004000
+#define FPU_CSR_UDF_X 0x00002000
+#define FPU_CSR_INE_X 0x00001000
-#define FPU_CSR_ALL_E 0x00000f80
-#define FPU_CSR_INV_E 0x00000800
-#define FPU_CSR_DIV_E 0x00000400
-#define FPU_CSR_OVF_E 0x00000200
-#define FPU_CSR_UDF_E 0x00000100
-#define FPU_CSR_INE_E 0x00000080
+#define FPU_CSR_ALL_E 0x00000f80
+#define FPU_CSR_INV_E 0x00000800
+#define FPU_CSR_DIV_E 0x00000400
+#define FPU_CSR_OVF_E 0x00000200
+#define FPU_CSR_UDF_E 0x00000100
+#define FPU_CSR_INE_E 0x00000080
-#define FPU_CSR_ALL_S 0x0000007c
-#define FPU_CSR_INV_S 0x00000040
-#define FPU_CSR_DIV_S 0x00000020
-#define FPU_CSR_OVF_S 0x00000010
-#define FPU_CSR_UDF_S 0x00000008
-#define FPU_CSR_INE_S 0x00000004
+#define FPU_CSR_ALL_S 0x0000007c
+#define FPU_CSR_INV_S 0x00000040
+#define FPU_CSR_DIV_S 0x00000020
+#define FPU_CSR_OVF_S 0x00000010
+#define FPU_CSR_UDF_S 0x00000008
+#define FPU_CSR_INE_S 0x00000004
/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
-#define FPU_CSR_RM 0x00000003
-#define FPU_CSR_RN 0x0 /* nearest */
-#define FPU_CSR_RZ 0x1 /* towards zero */
-#define FPU_CSR_RU 0x2 /* towards +Infinity */
-#define FPU_CSR_RD 0x3 /* towards -Infinity */
+#define FPU_CSR_RM 0x00000003
+#define FPU_CSR_RN 0x0 /* nearest */
+#define FPU_CSR_RZ 0x1 /* towards zero */
+#define FPU_CSR_RU 0x2 /* towards +Infinity */
+#define FPU_CSR_RD 0x3 /* towards -Infinity */
-#define PM_4K 0x00000000
-#define PM_16K 0x00006000
-#define PM_64K 0x0001e000
-#define PM_256K 0x0007e000
-#define PM_1M 0x001fe000
-#define PM_4M 0x007fe000
-#define PM_16M 0x01ffe000
-#define PM_64M 0x07ffe000
-#define PM_256M 0x1fffe000
+#define PM_4K 0x00000000
+#define PM_16K 0x00006000
+#define PM_64K 0x0001e000
+#define PM_256K 0x0007e000
+#define PM_1M 0x001fe000
+#define PM_4M 0x007fe000
+#define PM_16M 0x01ffe000
+#define PM_64M 0x07ffe000
+#define PM_256M 0x1fffe000
/*
* Values used for computation of new tlb entries
*/
-#define PL_4K 12
-#define PL_16K 14
-#define PL_64K 16
-#define PL_256K 18
-#define PL_1M 20
-#define PL_4M 22
-#define PL_16M 24
-#define PL_64M 26
-#define PL_256M 28
+#define PL_4K 12
+#define PL_16K 14
+#define PL_64K 16
+#define PL_256K 18
+#define PL_1M 20
+#define PL_4M 22
+#define PL_16M 24
+#define PL_64M 26
+#define PL_256M 28
/*
* R4x00 interrupt enable / cause bits
@@ -396,202 +396,202 @@
/*
* Bitfields in the R4xx0 cp0 status register
*/
-#define ST0_IE 0x00000001
-#define ST0_EXL 0x00000002
-#define ST0_ERL 0x00000004
-#define ST0_KSU 0x00000018
-# define KSU_USER 0x00000010
-# define KSU_SUPERVISOR 0x00000008
-# define KSU_KERNEL 0x00000000
-#define ST0_UX 0x00000020
-#define ST0_SX 0x00000040
-#define ST0_KX 0x00000080
-#define ST0_DE 0x00010000
-#define ST0_CE 0x00020000
+#define ST0_IE 0x00000001
+#define ST0_EXL 0x00000002
+#define ST0_ERL 0x00000004
+#define ST0_KSU 0x00000018
+# define KSU_USER 0x00000010
+# define KSU_SUPERVISOR 0x00000008
+# define KSU_KERNEL 0x00000000
+#define ST0_UX 0x00000020
+#define ST0_SX 0x00000040
+#define ST0_KX 0x00000080
+#define ST0_DE 0x00010000
+#define ST0_CE 0x00020000
/*
* Bitfields in the R[23]000 cp0 status register.
*/
#define ST0_IEC 0x00000001
-#define ST0_KUC 0x00000002
-#define ST0_IEP 0x00000004
-#define ST0_KUP 0x00000008
-#define ST0_IEO 0x00000010
-#define ST0_KUO 0x00000020
+#define ST0_KUC 0x00000002
+#define ST0_IEP 0x00000004
+#define ST0_KUP 0x00000008
+#define ST0_IEO 0x00000010
+#define ST0_KUO 0x00000020
/* bits 6 & 7 are reserved on R[23]000 */
-#define ST0_ISC 0x00010000
-#define ST0_SWC 0x00020000
-#define ST0_CM 0x00080000
+#define ST0_ISC 0x00010000
+#define ST0_SWC 0x00020000
+#define ST0_CM 0x00080000
/*
* Bits specific to the R4640/R4650
*/
-#define ST0_UM (_ULCAST_(1) << 4)
-#define ST0_IL (_ULCAST_(1) << 23)
-#define ST0_DL (_ULCAST_(1) << 24)
+#define ST0_UM (_ULCAST_(1) << 4)
+#define ST0_IL (_ULCAST_(1) << 23)
+#define ST0_DL (_ULCAST_(1) << 24)
/*
* Status register bits available in all MIPS CPUs.
*/
-#define ST0_IM 0x0000ff00
-#define STATUSB_IP0 8
-#define STATUSF_IP0 (_ULCAST_(1) << 8)
-#define STATUSB_IP1 9
-#define STATUSF_IP1 (_ULCAST_(1) << 9)
-#define STATUSB_IP2 10
-#define STATUSF_IP2 (_ULCAST_(1) << 10)
-#define STATUSB_IP3 11
-#define STATUSF_IP3 (_ULCAST_(1) << 11)
-#define STATUSB_IP4 12
-#define STATUSF_IP4 (_ULCAST_(1) << 12)
-#define STATUSB_IP5 13
-#define STATUSF_IP5 (_ULCAST_(1) << 13)
-#define STATUSB_IP6 14
-#define STATUSF_IP6 (_ULCAST_(1) << 14)
-#define STATUSB_IP7 15
-#define STATUSF_IP7 (_ULCAST_(1) << 15)
-#define STATUSB_IP8 0
-#define STATUSF_IP8 (_ULCAST_(1) << 0)
-#define STATUSB_IP9 1
-#define STATUSF_IP9 (_ULCAST_(1) << 1)
-#define STATUSB_IP10 2
-#define STATUSF_IP10 (_ULCAST_(1) << 2)
-#define STATUSB_IP11 3
-#define STATUSF_IP11 (_ULCAST_(1) << 3)
-#define STATUSB_IP12 4
-#define STATUSF_IP12 (_ULCAST_(1) << 4)
-#define STATUSB_IP13 5
-#define STATUSF_IP13 (_ULCAST_(1) << 5)
-#define STATUSB_IP14 6
-#define STATUSF_IP14 (_ULCAST_(1) << 6)
-#define STATUSB_IP15 7
-#define STATUSF_IP15 (_ULCAST_(1) << 7)
-#define ST0_CH 0x00040000
-#define ST0_SR 0x00100000
-#define ST0_TS 0x00200000
-#define ST0_BEV 0x00400000
-#define ST0_RE 0x02000000
-#define ST0_FR 0x04000000
-#define ST0_CU 0xf0000000
-#define ST0_CU0 0x10000000
-#define ST0_CU1 0x20000000
-#define ST0_CU1_SHIFT 29
-#define ST0_CU2 0x40000000
-#define ST0_CU3 0x80000000
-#define ST0_XX 0x80000000 /* MIPS IV naming */
+#define ST0_IM 0x0000ff00
+#define STATUSB_IP0 8
+#define STATUSF_IP0 (_ULCAST_(1) << 8)
+#define STATUSB_IP1 9
+#define STATUSF_IP1 (_ULCAST_(1) << 9)
+#define STATUSB_IP2 10
+#define STATUSF_IP2 (_ULCAST_(1) << 10)
+#define STATUSB_IP3 11
+#define STATUSF_IP3 (_ULCAST_(1) << 11)
+#define STATUSB_IP4 12
+#define STATUSF_IP4 (_ULCAST_(1) << 12)
+#define STATUSB_IP5 13
+#define STATUSF_IP5 (_ULCAST_(1) << 13)
+#define STATUSB_IP6 14
+#define STATUSF_IP6 (_ULCAST_(1) << 14)
+#define STATUSB_IP7 15
+#define STATUSF_IP7 (_ULCAST_(1) << 15)
+#define STATUSB_IP8 0
+#define STATUSF_IP8 (_ULCAST_(1) << 0)
+#define STATUSB_IP9 1
+#define STATUSF_IP9 (_ULCAST_(1) << 1)
+#define STATUSB_IP10 2
+#define STATUSF_IP10 (_ULCAST_(1) << 2)
+#define STATUSB_IP11 3
+#define STATUSF_IP11 (_ULCAST_(1) << 3)
+#define STATUSB_IP12 4
+#define STATUSF_IP12 (_ULCAST_(1) << 4)
+#define STATUSB_IP13 5
+#define STATUSF_IP13 (_ULCAST_(1) << 5)
+#define STATUSB_IP14 6
+#define STATUSF_IP14 (_ULCAST_(1) << 6)
+#define STATUSB_IP15 7
+#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define ST0_CH 0x00040000
+#define ST0_SR 0x00100000
+#define ST0_TS 0x00200000
+#define ST0_BEV 0x00400000
+#define ST0_RE 0x02000000
+#define ST0_FR 0x04000000
+#define ST0_CU 0xf0000000
+#define ST0_CU0 0x10000000
+#define ST0_CU1 0x20000000
+#define ST0_CU1_SHIFT 29
+#define ST0_CU2 0x40000000
+#define ST0_CU3 0x80000000
+#define ST0_XX 0x80000000 /* MIPS IV naming */
/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
*
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
*/
-#define CAUSEB_EXCCODE 2
-#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
-#define CAUSEB_IP 8
-#define CAUSEF_IP (_ULCAST_(255) << 8)
-#define CAUSEB_IP0 8
-#define CAUSEF_IP0 (_ULCAST_(1) << 8)
-#define CAUSEB_IP1 9
-#define CAUSEF_IP1 (_ULCAST_(1) << 9)
-#define CAUSEB_IP2 10
-#define CAUSEF_IP2 (_ULCAST_(1) << 10)
-#define CAUSEB_IP3 11
-#define CAUSEF_IP3 (_ULCAST_(1) << 11)
-#define CAUSEB_IP4 12
-#define CAUSEF_IP4 (_ULCAST_(1) << 12)
-#define CAUSEB_IP5 13
-#define CAUSEF_IP5 (_ULCAST_(1) << 13)
-#define CAUSEB_IP6 14
-#define CAUSEF_IP6 (_ULCAST_(1) << 14)
-#define CAUSEB_IP7 15
-#define CAUSEF_IP7 (_ULCAST_(1) << 15)
-#define CAUSEB_IV 23
-#define CAUSEF_IV (_ULCAST_(1) << 23)
-#define CAUSEB_CE 28
-#define CAUSEF_CE (_ULCAST_(3) << 28)
-#define CAUSEB_BD 31
-#define CAUSEF_BD (_ULCAST_(1) << 31)
+#define CAUSEB_EXCCODE 2
+#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
+#define CAUSEB_IP 8
+#define CAUSEF_IP (_ULCAST_(255) << 8)
+#define CAUSEB_IP0 8
+#define CAUSEF_IP0 (_ULCAST_(1) << 8)
+#define CAUSEB_IP1 9
+#define CAUSEF_IP1 (_ULCAST_(1) << 9)
+#define CAUSEB_IP2 10
+#define CAUSEF_IP2 (_ULCAST_(1) << 10)
+#define CAUSEB_IP3 11
+#define CAUSEF_IP3 (_ULCAST_(1) << 11)
+#define CAUSEB_IP4 12
+#define CAUSEF_IP4 (_ULCAST_(1) << 12)
+#define CAUSEB_IP5 13
+#define CAUSEF_IP5 (_ULCAST_(1) << 13)
+#define CAUSEB_IP6 14
+#define CAUSEF_IP6 (_ULCAST_(1) << 14)
+#define CAUSEB_IP7 15
+#define CAUSEF_IP7 (_ULCAST_(1) << 15)
+#define CAUSEB_IV 23
+#define CAUSEF_IV (_ULCAST_(1) << 23)
+#define CAUSEB_CE 28
+#define CAUSEF_CE (_ULCAST_(3) << 28)
+#define CAUSEB_BD 31
+#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
* Bits in the coprocessor 0 config register.
*/
/* Generic bits. */
-#define CONF_CM_CACHABLE_NO_WA 0
-#define CONF_CM_CACHABLE_WA 1
-#define CONF_CM_UNCACHED 2
-#define CONF_CM_CACHABLE_NONCOHERENT 3
-#define CONF_CM_CACHABLE_CE 4
-#define CONF_CM_CACHABLE_COW 5
-#define CONF_CM_CACHABLE_CUW 6
-#define CONF_CM_CACHABLE_ACCELERATED 7
-#define CONF_CM_CMASK 7
-#define CONF_BE (_ULCAST_(1) << 15)
+#define CONF_CM_CACHABLE_NO_WA 0
+#define CONF_CM_CACHABLE_WA 1
+#define CONF_CM_UNCACHED 2
+#define CONF_CM_CACHABLE_NONCOHERENT 3
+#define CONF_CM_CACHABLE_CE 4
+#define CONF_CM_CACHABLE_COW 5
+#define CONF_CM_CACHABLE_CUW 6
+#define CONF_CM_CACHABLE_ACCELERATED 7
+#define CONF_CM_CMASK 7
+#define CONF_BE (_ULCAST_(1) << 15)
/* Bits common to various processors. */
-#define CONF_CU (_ULCAST_(1) << 3)
-#define CONF_DB (_ULCAST_(1) << 4)
-#define CONF_IB (_ULCAST_(1) << 5)
-#define CONF_DC (_ULCAST_(7) << 6)
-#define CONF_IC (_ULCAST_(7) << 9)
-#define CONF_EB (_ULCAST_(1) << 13)
-#define CONF_EM (_ULCAST_(1) << 14)
-#define CONF_SM (_ULCAST_(1) << 16)
-#define CONF_SC (_ULCAST_(1) << 17)
-#define CONF_EW (_ULCAST_(3) << 18)
-#define CONF_EP (_ULCAST_(15)<< 24)
-#define CONF_EC (_ULCAST_(7) << 28)
-#define CONF_CM (_ULCAST_(1) << 31)
+#define CONF_CU (_ULCAST_(1) << 3)
+#define CONF_DB (_ULCAST_(1) << 4)
+#define CONF_IB (_ULCAST_(1) << 5)
+#define CONF_DC (_ULCAST_(7) << 6)
+#define CONF_IC (_ULCAST_(7) << 9)
+#define CONF_EB (_ULCAST_(1) << 13)
+#define CONF_EM (_ULCAST_(1) << 14)
+#define CONF_SM (_ULCAST_(1) << 16)
+#define CONF_SC (_ULCAST_(1) << 17)
+#define CONF_EW (_ULCAST_(3) << 18)
+#define CONF_EP (_ULCAST_(15)<< 24)
+#define CONF_EC (_ULCAST_(7) << 28)
+#define CONF_CM (_ULCAST_(1) << 31)
/* Bits specific to the R4xx0. */
-#define R4K_CONF_SW (_ULCAST_(1) << 20)
-#define R4K_CONF_SS (_ULCAST_(1) << 21)
-#define R4K_CONF_SB (_ULCAST_(3) << 22)
+#define R4K_CONF_SW (_ULCAST_(1) << 20)
+#define R4K_CONF_SS (_ULCAST_(1) << 21)
+#define R4K_CONF_SB (_ULCAST_(3) << 22)
/* Bits specific to the R5000. */
-#define R5K_CONF_SE (_ULCAST_(1) << 12)
-#define R5K_CONF_SS (_ULCAST_(3) << 20)
+#define R5K_CONF_SE (_ULCAST_(1) << 12)
+#define R5K_CONF_SS (_ULCAST_(3) << 20)
/* Bits specific to the R10000. */
-#define R10K_CONF_DN (_ULCAST_(3) << 3)
-#define R10K_CONF_CT (_ULCAST_(1) << 5)
-#define R10K_CONF_PE (_ULCAST_(1) << 6)
-#define R10K_CONF_PM (_ULCAST_(3) << 7)
-#define R10K_CONF_EC (_ULCAST_(15)<< 9)
-#define R10K_CONF_SB (_ULCAST_(1) << 13)
-#define R10K_CONF_SK (_ULCAST_(1) << 14)
-#define R10K_CONF_SS (_ULCAST_(7) << 16)
-#define R10K_CONF_SC (_ULCAST_(7) << 19)
-#define R10K_CONF_DC (_ULCAST_(7) << 26)
-#define R10K_CONF_IC (_ULCAST_(7) << 29)
+#define R10K_CONF_DN (_ULCAST_(3) << 3)
+#define R10K_CONF_CT (_ULCAST_(1) << 5)
+#define R10K_CONF_PE (_ULCAST_(1) << 6)
+#define R10K_CONF_PM (_ULCAST_(3) << 7)
+#define R10K_CONF_EC (_ULCAST_(15)<< 9)
+#define R10K_CONF_SB (_ULCAST_(1) << 13)
+#define R10K_CONF_SK (_ULCAST_(1) << 14)
+#define R10K_CONF_SS (_ULCAST_(7) << 16)
+#define R10K_CONF_SC (_ULCAST_(7) << 19)
+#define R10K_CONF_DC (_ULCAST_(7) << 26)
+#define R10K_CONF_IC (_ULCAST_(7) << 29)
/* Bits specific to the VR41xx. */
-#define VR41_CONF_CS (_ULCAST_(1) << 12)
-#define VR41_CONF_M16 (_ULCAST_(1) << 20)
-#define VR41_CONF_AD (_ULCAST_(1) << 23)
+#define VR41_CONF_CS (_ULCAST_(1) << 12)
+#define VR41_CONF_M16 (_ULCAST_(1) << 20)
+#define VR41_CONF_AD (_ULCAST_(1) << 23)
/* Bits specific to the R30xx. */
-#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
-#define R30XX_CONF_REV (_ULCAST_(1) << 22)
-#define R30XX_CONF_AC (_ULCAST_(1) << 23)
-#define R30XX_CONF_RF (_ULCAST_(1) << 24)
-#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
-#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
-#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
-#define R30XX_CONF_SB (_ULCAST_(1) << 30)
-#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
+#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
+#define R30XX_CONF_REV (_ULCAST_(1) << 22)
+#define R30XX_CONF_AC (_ULCAST_(1) << 23)
+#define R30XX_CONF_RF (_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
+#define R30XX_CONF_SB (_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
/* Bits specific to the TX49. */
-#define TX49_CONF_DC (_ULCAST_(1) << 16)
-#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
-#define TX49_CONF_HALT (_ULCAST_(1) << 18)
-#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
+#define TX49_CONF_DC (_ULCAST_(1) << 16)
+#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
+#define TX49_CONF_HALT (_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
/* Bits specific to the MIPS32/64 PRA. */
-#define MIPS_CONF_MT (_ULCAST_(7) << 7)
-#define MIPS_CONF_AR (_ULCAST_(7) << 10)
-#define MIPS_CONF_AT (_ULCAST_(3) << 13)
-#define MIPS_CONF_M (_ULCAST_(1) << 31)
+#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+#define MIPS_CONF_AR (_ULCAST_(7) << 10)
+#define MIPS_CONF_AT (_ULCAST_(3) << 13)
+#define MIPS_CONF_M (_ULCAST_(1) << 31)
/*
* R10000 performance counter definitions.
@@ -604,50 +604,50 @@
/*
* Events counted by counter #0
*/
-#define CE0_CYCLES 0
-#define CE0_INSN_ISSUED 1
-#define CE0_LPSC_ISSUED 2
-#define CE0_S_ISSUED 3
-#define CE0_SC_ISSUED 4
-#define CE0_SC_FAILED 5
-#define CE0_BRANCH_DECODED 6
-#define CE0_QW_WB_SECONDARY 7
-#define CE0_CORRECTED_ECC_ERRORS 8
-#define CE0_ICACHE_MISSES 9
-#define CE0_SCACHE_I_MISSES 10
-#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
-#define CE0_EXT_INTERVENTIONS_REQ 12
-#define CE0_EXT_INVALIDATE_REQ 13
-#define CE0_VIRTUAL_COHERENCY_COND 14
-#define CE0_INSN_GRADUATED 15
+#define CE0_CYCLES 0
+#define CE0_INSN_ISSUED 1
+#define CE0_LPSC_ISSUED 2
+#define CE0_S_ISSUED 3
+#define CE0_SC_ISSUED 4
+#define CE0_SC_FAILED 5
+#define CE0_BRANCH_DECODED 6
+#define CE0_QW_WB_SECONDARY 7
+#define CE0_CORRECTED_ECC_ERRORS 8
+#define CE0_ICACHE_MISSES 9
+#define CE0_SCACHE_I_MISSES 10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
+#define CE0_EXT_INTERVENTIONS_REQ 12
+#define CE0_EXT_INVALIDATE_REQ 13
+#define CE0_VIRTUAL_COHERENCY_COND 14
+#define CE0_INSN_GRADUATED 15
/*
* Events counted by counter #1
*/
-#define CE1_CYCLES 0
-#define CE1_INSN_GRADUATED 1
-#define CE1_LPSC_GRADUATED 2
-#define CE1_S_GRADUATED 3
-#define CE1_SC_GRADUATED 4
-#define CE1_FP_INSN_GRADUATED 5
-#define CE1_QW_WB_PRIMARY 6
-#define CE1_TLB_REFILL 7
-#define CE1_BRANCH_MISSPREDICTED 8
-#define CE1_DCACHE_MISS 9
-#define CE1_SCACHE_D_MISSES 10
-#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
-#define CE1_EXT_INTERVENTION_HITS 12
-#define CE1_EXT_INVALIDATE_REQ 13
-#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
-#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
+#define CE1_CYCLES 0
+#define CE1_INSN_GRADUATED 1
+#define CE1_LPSC_GRADUATED 2
+#define CE1_S_GRADUATED 3
+#define CE1_SC_GRADUATED 4
+#define CE1_FP_INSN_GRADUATED 5
+#define CE1_QW_WB_PRIMARY 6
+#define CE1_TLB_REFILL 7
+#define CE1_BRANCH_MISSPREDICTED 8
+#define CE1_DCACHE_MISS 9
+#define CE1_SCACHE_D_MISSES 10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
+#define CE1_EXT_INTERVENTION_HITS 12
+#define CE1_EXT_INVALIDATE_REQ 13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
/*
* These flags define in which priviledge mode the counters count events
*/
-#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
-#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
-#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
-#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
#ifndef __ASSEMBLY__
@@ -685,275 +685,275 @@
* Macros to access the system control coprocessor
*/
-#define __read_32bit_c0_register(source, sel) \
-({ int __res; \
- if (sel == 0) \
- __asm__ __volatile__( \
- "mfc0\t%0, " #source "\n\t" \
- : "=r" (__res)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- __res; \
+#define __read_32bit_c0_register(source, sel) \
+({ int __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0\n\t" \
+ : "=r" (__res)); \
+ __res; \
})
-#define __read_64bit_c0_register(source, sel) \
-({ unsigned long __res; \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmfc0\t%0, " #source "\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- __res; \
+#define __read_64bit_c0_register(source, sel) \
+({ unsigned long __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0, " #source "\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res; \
})
-#define __write_32bit_c0_register(register, sel, value) \
-do { \
- if (sel == 0) \
- __asm__ __volatile__( \
- "mtc0\t%z0, " #register "\n\t" \
- : : "Jr" (value)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mtc0\t%z0, " #register ", " #sel "\n\t" \
- ".set\tmips0" \
- : : "Jr" (value)); \
+#define __write_32bit_c0_register(register, sel, value) \
+do { \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mtc0\t%z0, " #register "\n\t" \
+ : : "Jr" (value)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mtc0\t%z0, " #register ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
} while (0)
-#define __write_64bit_c0_register(register, sel, value) \
-do { \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmtc0\t%z0, " #register "\n\t" \
- ".set\tmips0" \
- : : "Jr" (value)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmtc0\t%z0, " #register ", " #sel "\n\t" \
- ".set\tmips0" \
- : : "Jr" (value)); \
+#define __write_64bit_c0_register(register, sel, value) \
+do { \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%z0, " #register "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmtc0\t%z0, " #register ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
} while (0)
-#define __read_ulong_c0_register(reg, sel) \
- ((sizeof(unsigned long) == 4) ? \
- __read_32bit_c0_register(reg, sel) : \
+#define __read_ulong_c0_register(reg, sel) \
+ ((sizeof(unsigned long) == 4) ? \
+ __read_32bit_c0_register(reg, sel) : \
__read_64bit_c0_register(reg, sel))
-#define __write_ulong_c0_register(reg, sel, val) \
-do { \
- if (sizeof(unsigned long) == 4) \
- __write_32bit_c0_register(reg, sel, val); \
- else \
- __write_64bit_c0_register(reg, sel, val); \
+#define __write_ulong_c0_register(reg, sel, val) \
+do { \
+ if (sizeof(unsigned long) == 4) \
+ __write_32bit_c0_register(reg, sel, val); \
+ else \
+ __write_64bit_c0_register(reg, sel, val); \
} while (0)
/*
* These versions are only needed for systems with more than 38 bits of
* physical address space running the 32-bit kernel. That's none atm :-)
*/
-#define __read_64bit_c0_split(source, sel) \
-({ \
- unsigned long long val; \
- unsigned long flags; \
+#define __read_64bit_c0_split(source, sel) \
+({ \
+ unsigned long long val; \
+ unsigned long flags; \
\
- local_irq_save(flags); \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmfc0\t%M0, " #source "\n\t" \
- "dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
- ".set\tmips0" \
- : "=r" (val)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dmfc0\t%M0, " #source ", " #sel "\n\t" \
- "dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
- ".set\tmips0" \
- : "=r" (val)); \
- local_irq_restore(flags); \
+ local_irq_save(flags); \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%M0, " #source "\n\t" \
+ "dsll\t%L0, %M0, 32\n\t" \
+ "dsrl\t%M0, %M0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ ".set\tmips0" \
+ : "=r" (val)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%M0, " #source ", " #sel "\n\t" \
+ "dsll\t%L0, %M0, 32\n\t" \
+ "dsrl\t%M0, %M0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ ".set\tmips0" \
+ : "=r" (val)); \
+ local_irq_restore(flags); \
\
- val; \
+ val; \
})
-#define __write_64bit_c0_split(source, sel, val) \
-do { \
- unsigned long flags; \
+#define __write_64bit_c0_split(source, sel, val) \
+do { \
+ unsigned long flags; \
\
- local_irq_save(flags); \
- if (sel == 0) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dsll\t%L0, %L0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
- "dsll\t%M0, %M0, 32\n\t" \
- "or\t%L0, %L0, %M0\n\t" \
- "dmtc0\t%L0, " #source "\n\t" \
- ".set\tmips0" \
- : : "r" (val)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "dsll\t%L0, %L0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
- "dsll\t%M0, %M0, 32\n\t" \
- "or\t%L0, %L0, %M0\n\t" \
- "dmtc0\t%L0, " #source ", " #sel "\n\t" \
- ".set\tmips0" \
- : : "r" (val)); \
- local_irq_restore(flags); \
+ local_irq_save(flags); \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dsll\t%L0, %L0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ "dsll\t%M0, %M0, 32\n\t" \
+ "or\t%L0, %L0, %M0\n\t" \
+ "dmtc0\t%L0, " #source "\n\t" \
+ ".set\tmips0" \
+ : : "r" (val)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dsll\t%L0, %L0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ "dsll\t%M0, %M0, 32\n\t" \
+ "or\t%L0, %L0, %M0\n\t" \
+ "dmtc0\t%L0, " #source ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "r" (val)); \
+ local_irq_restore(flags); \
} while (0)
-#define read_c0_index() __read_32bit_c0_register($0, 0)
-#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
+#define read_c0_index() __read_32bit_c0_register($0, 0)
+#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
-#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
-#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
+#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
-#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
-#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
+#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
-#define read_c0_conf() __read_32bit_c0_register($3, 0)
-#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
+#define read_c0_conf() __read_32bit_c0_register($3, 0)
+#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
-#define read_c0_context() __read_ulong_c0_register($4, 0)
-#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
+#define read_c0_context() __read_ulong_c0_register($4, 0)
+#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
-#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
-#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
+#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
-#define read_c0_wired() __read_32bit_c0_register($6, 0)
-#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
+#define read_c0_wired() __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
-#define read_c0_info() __read_32bit_c0_register($7, 0)
+#define read_c0_info() __read_32bit_c0_register($7, 0)
-#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
-#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
+#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
-#define read_c0_count() __read_32bit_c0_register($9, 0)
-#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
+#define read_c0_count() __read_32bit_c0_register($9, 0)
+#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
-#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
-#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
+#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
-#define read_c0_compare() __read_32bit_c0_register($11, 0)
-#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
+#define read_c0_compare() __read_32bit_c0_register($11, 0)
+#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
-#define read_c0_status() __read_32bit_c0_register($12, 0)
-#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
+#define read_c0_status() __read_32bit_c0_register($12, 0)
+#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
-#define read_c0_cause() __read_32bit_c0_register($13, 0)
-#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
+#define read_c0_cause() __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
-#define read_c0_prid() __read_32bit_c0_register($15, 0)
+#define read_c0_prid() __read_32bit_c0_register($15, 0)
-#define read_c0_ebase() __read_32bit_c0_register($15, 1)
-#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
+#define read_c0_ebase() __read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
-#define read_c0_config() __read_32bit_c0_register($16, 0)
-#define read_c0_config1() __read_32bit_c0_register($16, 1)
-#define read_c0_config2() __read_32bit_c0_register($16, 2)
-#define read_c0_config3() __read_32bit_c0_register($16, 3)
-#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
-#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
-#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
-#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
+#define read_c0_config() __read_32bit_c0_register($16, 0)
+#define read_c0_config1() __read_32bit_c0_register($16, 1)
+#define read_c0_config2() __read_32bit_c0_register($16, 2)
+#define read_c0_config3() __read_32bit_c0_register($16, 3)
+#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
/*
* The WatchLo register. There may be upto 8 of them.
*/
-#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
-#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
-#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
-#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
-#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
-#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
-#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
-#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
-#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
-#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
-#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
-#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
-#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
-#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
-#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
-#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
+#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
/*
* The WatchHi register. There may be upto 8 of them.
*/
-#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
-#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
-#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
-#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
-#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
-#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
-#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
-#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
+#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
-#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
-#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
-#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
-#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
-#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
-#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
-#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
-#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
+#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
-#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
-#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
+#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
-#define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
+#define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
-#define read_c0_framemask() __read_32bit_c0_register($21, 0)
-#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
+#define read_c0_framemask() __read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
-#define read_c0_debug() __read_32bit_c0_register($23, 0)
-#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
+#define read_c0_debug() __read_32bit_c0_register($23, 0)
+#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
-#define read_c0_depc() __read_ulong_c0_register($24, 0)
-#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
+#define read_c0_depc() __read_ulong_c0_register($24, 0)
+#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
-#define read_c0_ecc() __read_32bit_c0_register($26, 0)
-#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
+#define read_c0_ecc() __read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
-#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
-#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
-#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
+#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
-#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
-#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
-#define read_c0_taglo() __read_32bit_c0_register($28, 0)
-#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
+#define read_c0_taglo() __read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
-#define read_c0_taghi() __read_32bit_c0_register($29, 0)
-#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
+#define read_c0_taghi() __read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
-#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
-#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
+#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
-#define read_c0_epc() __read_ulong_c0_register($14, 0)
-#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
+#define read_c0_epc() __read_ulong_c0_register($14, 0)
+#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
#if 1
/*
@@ -962,20 +962,20 @@ do { \
#define read_32bit_cp0_register(source) \
({ int __res; \
__asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
"mfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
+ ".set\tpop" \
: "=r" (__res)); \
__res;})
#define read_32bit_cp0_set1_register(source) \
({ int __res; \
__asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
"cfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
+ ".set\tpop" \
: "=r" (__res)); \
__res;})
@@ -993,14 +993,14 @@ do { \
#define write_32bit_cp0_register(register,value) \
__asm__ __volatile__( \
- "mtc0\t%0,"STR(register)"\n\t" \
- "nop" \
+ "mtc0\t%0,"STR(register)"\n\t" \
+ "nop" \
: : "r" (value));
#define write_32bit_cp0_set1_register(register,value) \
__asm__ __volatile__( \
- "ctc0\t%0,$"STR(register)"\n\t" \
- "nop" \
+ "ctc0\t%0,$"STR(register)"\n\t" \
+ "nop" \
: : "r" (value));
#define write_64bit_cp0_register(register,value) \
@@ -1018,9 +1018,9 @@ do { \
__asm__ __volatile__( \
".set\tnoreorder\n\t" \
".set\tnoat\n\t" \
- "#.set\tmips64\n\t" \
- "#mfc0\t$1, $16, 1\n\t" \
- "#.set\tmips0\n\t" \
+ "#.set\tmips64\n\t" \
+ "#mfc0\t$1, $16, 1\n\t" \
+ "#.set\tmips0\n\t" \
".word\t0x40018001\n\t" \
"move\t%0,$1\n\t" \
".set\tat\n\t" \
@@ -1035,17 +1035,17 @@ do { \
#define read_32bit_cp1_register(source) \
({ int __res; \
__asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
"cfc1\t%0,$"STR(source)"\n\t" \
- ".set\tpop" \
+ ".set\tpop" \
: "=r" (__res)); \
__res;})
#define write_32bit_cp1_register(register,value) \
__asm__ __volatile__( \
- "ctc1\t%0,$"STR(register)"\n\t" \
- "nop" \
+ "ctc1\t%0,$"STR(register)"\n\t" \
+ "nop" \
: : "r" (value));
/* TLB operations. */
@@ -1084,62 +1084,62 @@ static inline void tlb_write_random(void)
/*
* Manipulate bits in a c0 register.
*/
-#define __BUILD_SET_C0(name,register) \
-static inline unsigned int \
-set_c0_##name(unsigned int set) \
-{ \
- unsigned int res; \
+#define __BUILD_SET_C0(name,register) \
+static inline unsigned int \
+set_c0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
\
- res = read_c0_##name(); \
- res |= set; \
- write_c0_##name(res); \
+ res = read_c0_##name(); \
+ res |= set; \
+ write_c0_##name(res); \
\
- return res; \
-} \
+ return res; \
+} \
\
-static inline unsigned int \
-clear_c0_##name(unsigned int clear) \
-{ \
- unsigned int res; \
+static inline unsigned int \
+clear_c0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
\
- res = read_c0_##name(); \
- res &= ~clear; \
- write_c0_##name(res); \
+ res = read_c0_##name(); \
+ res &= ~clear; \
+ write_c0_##name(res); \
\
- return res; \
-} \
+ return res; \
+} \
\
-static inline unsigned int \
-change_c0_##name(unsigned int change, unsigned int new) \
-{ \
- unsigned int res; \
+static inline unsigned int \
+change_c0_##name(unsigned int change, unsigned int new) \
+{ \
+ unsigned int res; \
\
- res = read_c0_##name(); \
- res &= ~change; \
- res |= (new & change); \
- write_c0_##name(res); \
+ res = read_c0_##name(); \
+ res &= ~change; \
+ res |= (new & change); \
+ write_c0_##name(res); \
\
- return res; \
+ return res; \
}
__BUILD_SET_C0(status,CP0_STATUS)
__BUILD_SET_C0(cause,CP0_CAUSE)
__BUILD_SET_C0(config,CP0_CONFIG)
-#define set_cp0_status(x) set_c0_status(x)
-#define set_cp0_cause(x) set_c0_cause(x)
-#define set_cp0_config(x) set_c0_config(x)
+#define set_cp0_status(x) set_c0_status(x)
+#define set_cp0_cause(x) set_c0_cause(x)
+#define set_cp0_config(x) set_c0_config(x)
-#define read_c1_status() read_32bit_cp1_register(31)
-#define write_c1_status(x) write_32bit_cp1_register(31, x)
+#define read_c1_status() read_32bit_cp1_register(31)
+#define write_c1_status(x) write_32bit_cp1_register(31, x)
-#define readb(reg) (*((volatile unsigned char *) (reg)))
-#define readw(reg) (*((volatile unsigned short *) (reg)))
-#define readl(reg) (*((volatile unsigned int *) (reg)))
+#define readb(reg) (*((volatile unsigned char *) (reg)))
+#define readw(reg) (*((volatile unsigned short *) (reg)))
+#define readl(reg) (*((volatile unsigned int *) (reg)))
-#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
-#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
-#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
+#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
+#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
+#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
#endif /* !__ASSEMBLY__ */
diff --git a/libcpu/mips/common/mips_types.h b/libcpu/mips/common/mips_types.h
index cc12d44391..466a39a40b 100644
--- a/libcpu/mips/common/mips_types.h
+++ b/libcpu/mips/common/mips_types.h
@@ -1,21 +1,7 @@
/*
- * File : mips_types.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h
index 00ce58a085..8b82cca5d6 100644
--- a/libcpu/mips/common/ptrace.h
+++ b/libcpu/mips/common/ptrace.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -23,9 +23,9 @@
#include <rtthread.h>
struct mips_fpu_struct {
- rt_uint64_t fpr[NUM_FPU_REGS];
- rt_uint32_t fcr31;
- rt_uint32_t pad;
+ rt_uint64_t fpr[NUM_FPU_REGS];
+ rt_uint32_t fcr31;
+ rt_uint32_t pad;
};
struct pt_regs {
@@ -68,53 +68,53 @@ struct pt_regs {
/* Note: For call stack o32 ABI has 0x8 shadowsoace Here */
#ifdef ARCH_MIPS64
-#define PT_R0 (0x0 * LONGSIZE) /* 0 */
+#define PT_R0 (0x0 * LONGSIZE) /* 0 */
#else
-#define PT_R0 (0x8 * LONGSIZE) /* 0 */
+#define PT_R0 (0x8 * LONGSIZE) /* 0 */
#endif
-#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
-#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
-#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
-#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */
-#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */
-#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */
-#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */
-#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */
-#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */
-#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */
-#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */
-#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */
-#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */
-#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */
-#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */
-#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */
-#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */
-#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */
-#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */
-#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */
-#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */
-#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */
-#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */
-#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */
-#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */
-#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */
-#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */
-#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */
-#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */
-#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */
-#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */
+#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
+#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
+#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
+#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */
+#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */
+#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */
+#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */
+#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */
+#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */
+#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */
+#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */
+#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */
+#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */
+#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */
+#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */
+#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */
+#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */
+#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */
+#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */
+#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */
+#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */
+#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */
+#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */
+#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */
+#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */
+#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */
+#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */
+#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */
+#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */
+#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */
+#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
-#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
-#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */
-#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */
-#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
-#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
-#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
+#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
+#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */
+#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */
+#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
+#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
+#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
-#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */
+#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */
#ifdef RT_USING_FPU
#define PT_FPU_R0 (PT_REG_END)
@@ -136,10 +136,10 @@ struct pt_regs {
#define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE)
#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4)
-#define PT_FPU_END ((PT_FPU_PAD0) + 4)
-#define PT_SIZE PT_FPU_END
+#define PT_FPU_END ((PT_FPU_PAD0) + 4)
+#define PT_SIZE PT_FPU_END
#else
-#define PT_SIZE PT_REG_END
+#define PT_SIZE PT_REG_END
#endif
-#endif \ No newline at end of file
+#endif
diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c
index b933b184e7..3f9010837a 100644
--- a/libcpu/mips/common/stack.c
+++ b/libcpu/mips/common/stack.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -47,15 +47,15 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
pt->regs[REG_FP] = (rt_ubase_t)0x0;
pt->regs[REG_RA] = (rt_ubase_t)texit;
- pt->hi = 0x0;
- pt->lo = 0x0;
+ pt->hi = 0x0;
+ pt->lo = 0x0;
pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM);
#ifdef RT_USING_FPU
pt->cp0_status |= (ST0_CU1 | ST0_FR);
#endif
- pt->cp0_cause = read_c0_cause();
- pt->cp0_epc = (rt_ubase_t)tentry;
- pt->cp0_badvaddr = 0x0;
+ pt->cp0_cause = read_c0_cause();
+ pt->cp0_epc = (rt_ubase_t)tentry;
+ pt->cp0_badvaddr = 0x0;
return stk;
}
diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h
index bb92a18c9c..ba361acd99 100644
--- a/libcpu/mips/common/stackframe.h
+++ b/libcpu/mips/common/stackframe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -51,69 +51,69 @@
.set pop
.endm
- .macro SAVE_AT
- .set push
- .set noat
- LONG_S $1, PT_R1(sp)
- .set pop
+ .macro SAVE_AT
+ .set push
+ .set noat
+ LONG_S $1, PT_R1(sp)
+ .set pop
.endm
- .macro SAVE_TEMP
- mfhi v1
- LONG_S $8, PT_R8(sp)
- LONG_S $9, PT_R9(sp)
- sw v1, PT_HI(sp)
- mflo v1
- LONG_S $10, PT_R10(sp)
- LONG_S $11, PT_R11(sp)
- sw v1, PT_LO(sp)
- LONG_S $12, PT_R12(sp)
- LONG_S $13, PT_R13(sp)
- LONG_S $14, PT_R14(sp)
- LONG_S $15, PT_R15(sp)
- LONG_S $24, PT_R24(sp)
+ .macro SAVE_TEMP
+ mfhi v1
+ LONG_S $8, PT_R8(sp)
+ LONG_S $9, PT_R9(sp)
+ sw v1, PT_HI(sp)
+ mflo v1
+ LONG_S $10, PT_R10(sp)
+ LONG_S $11, PT_R11(sp)
+ sw v1, PT_LO(sp)
+ LONG_S $12, PT_R12(sp)
+ LONG_S $13, PT_R13(sp)
+ LONG_S $14, PT_R14(sp)
+ LONG_S $15, PT_R15(sp)
+ LONG_S $24, PT_R24(sp)
.endm
- .macro SAVE_STATIC
- LONG_S $16, PT_R16(sp)
- LONG_S $17, PT_R17(sp)
- LONG_S $18, PT_R18(sp)
- LONG_S $19, PT_R19(sp)
- LONG_S $20, PT_R20(sp)
- LONG_S $21, PT_R21(sp)
- LONG_S $22, PT_R22(sp)
- LONG_S $23, PT_R23(sp)
- LONG_S $30, PT_R30(sp)
+ .macro SAVE_STATIC
+ LONG_S $16, PT_R16(sp)
+ LONG_S $17, PT_R17(sp)
+ LONG_S $18, PT_R18(sp)
+ LONG_S $19, PT_R19(sp)
+ LONG_S $20, PT_R20(sp)
+ LONG_S $21, PT_R21(sp)
+ LONG_S $22, PT_R22(sp)
+ LONG_S $23, PT_R23(sp)
+ LONG_S $30, PT_R30(sp)
.endm
- .macro SAVE_SOME
- .set push
- .set noat
- .set reorder
- move k1, sp
- move k0, sp
+ .macro SAVE_SOME
+ .set push
+ .set noat
+ .set reorder
+ move k1, sp
+ move k0, sp
PTR_SUBU sp, k1, PT_SIZE
- LONG_S k0, PT_R29(sp)
- LONG_S $3, PT_R3(sp)
- LONG_S $0, PT_R0(sp)
- MFC0 v1, CP0_STATUS
- LONG_S $2, PT_R2(sp)
- LONG_S v1, PT_STATUS(sp)
- LONG_S $4, PT_R4(sp)
- MFC0 v1, CP0_CAUSE
- LONG_S $5, PT_R5(sp)
- LONG_S v1, PT_CAUSE(sp)
- LONG_S $6, PT_R6(sp)
- MFC0 v1, CP0_EPC
- LONG_S $7, PT_R7(sp)
- LONG_S v1, PT_EPC(sp)
- LONG_S $25, PT_R25(sp)
- LONG_S $28, PT_R28(sp)
- LONG_S $31, PT_R31(sp)
- .set pop
+ LONG_S k0, PT_R29(sp)
+ LONG_S $3, PT_R3(sp)
+ LONG_S $0, PT_R0(sp)
+ MFC0 v1, CP0_STATUS
+ LONG_S $2, PT_R2(sp)
+ LONG_S v1, PT_STATUS(sp)
+ LONG_S $4, PT_R4(sp)
+ MFC0 v1, CP0_CAUSE
+ LONG_S $5, PT_R5(sp)
+ LONG_S v1, PT_CAUSE(sp)
+ LONG_S $6, PT_R6(sp)
+ MFC0 v1, CP0_EPC
+ LONG_S $7, PT_R7(sp)
+ LONG_S v1, PT_EPC(sp)
+ LONG_S $25, PT_R25(sp)
+ LONG_S $28, PT_R28(sp)
+ LONG_S $31, PT_R31(sp)
+ .set pop
.endm
- .macro SAVE_ALL
+ .macro SAVE_ALL
SAVE_SOME
SAVE_AT
SAVE_TEMP
@@ -155,86 +155,86 @@
.set pop
.endm
- .macro RESTORE_AT
- .set push
- .set noat
- LONG_L $1, PT_R1(sp)
- .set pop
+ .macro RESTORE_AT
+ .set push
+ .set noat
+ LONG_L $1, PT_R1(sp)
+ .set pop
.endm
- .macro RESTORE_TEMP
- lw $24, PT_LO(sp)
- LONG_L $8, PT_R8(sp)
- LONG_L $9, PT_R9(sp)
- mtlo $24
- lw $24, PT_HI(sp)
- LONG_L $10, PT_R10(sp)
- LONG_L $11, PT_R11(sp)
- mthi $24
- LONG_L $12, PT_R12(sp)
- LONG_L $13, PT_R13(sp)
- LONG_L $14, PT_R14(sp)
- LONG_L $15, PT_R15(sp)
- LONG_L $24, PT_R24(sp)
+ .macro RESTORE_TEMP
+ lw $24, PT_LO(sp)
+ LONG_L $8, PT_R8(sp)
+ LONG_L $9, PT_R9(sp)
+ mtlo $24
+ lw $24, PT_HI(sp)
+ LONG_L $10, PT_R10(sp)
+ LONG_L $11, PT_R11(sp)
+ mthi $24
+ LONG_L $12, PT_R12(sp)
+ LONG_L $13, PT_R13(sp)
+ LONG_L $14, PT_R14(sp)
+ LONG_L $15, PT_R15(sp)
+ LONG_L $24, PT_R24(sp)
.endm
- .macro RESTORE_STATIC
- LONG_L $16, PT_R16(sp)
- LONG_L $17, PT_R17(sp)
- LONG_L $18, PT_R18(sp)
- LONG_L $19, PT_R19(sp)
- LONG_L $20, PT_R20(sp)
- LONG_L $21, PT_R21(sp)
- LONG_L $22, PT_R22(sp)
- LONG_L $23, PT_R23(sp)
- LONG_L $30, PT_R30(sp)
+ .macro RESTORE_STATIC
+ LONG_L $16, PT_R16(sp)
+ LONG_L $17, PT_R17(sp)
+ LONG_L $18, PT_R18(sp)
+ LONG_L $19, PT_R19(sp)
+ LONG_L $20, PT_R20(sp)
+ LONG_L $21, PT_R21(sp)
+ LONG_L $22, PT_R22(sp)
+ LONG_L $23, PT_R23(sp)
+ LONG_L $30, PT_R30(sp)
.endm
#define STATMASK 0x1f
- .macro RESTORE_SOME
- .set push
- .set reorder
- .set noat
- mfc0 a0, CP0_STATUS
- ori a0, STATMASK
- xori a0, STATMASK
- mtc0 a0, CP0_STATUS
- li v1, (ST0_CU1 | ST0_FR | ST0_IM)
- and a0, v1, a0
- LONG_L v0, PT_STATUS(sp)
- li v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
- and v0, v1
- or v0, a0
+ .macro RESTORE_SOME
+ .set push
+ .set reorder
+ .set noat
+ mfc0 a0, CP0_STATUS
+ ori a0, STATMASK
+ xori a0, STATMASK
+ mtc0 a0, CP0_STATUS
+ li v1, (ST0_CU1 | ST0_FR | ST0_IM)
+ and a0, v1, a0
+ LONG_L v0, PT_STATUS(sp)
+ li v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
+ and v0, v1
+ or v0, a0
li v1, (ST0_KX | ST0_SX | ST0_UX)
or v0, v1
- mtc0 v0, CP0_STATUS
- LONG_L v1, PT_EPC(sp)
- MTC0 v1, CP0_EPC
- LONG_L $31, PT_R31(sp)
- LONG_L $28, PT_R28(sp)
- LONG_L $25, PT_R25(sp)
- LONG_L $7, PT_R7(sp)
- LONG_L $6, PT_R6(sp)
- LONG_L $5, PT_R5(sp)
- LONG_L $4, PT_R4(sp)
- LONG_L $3, PT_R3(sp)
- LONG_L $2, PT_R2(sp)
- .set pop
+ mtc0 v0, CP0_STATUS
+ LONG_L v1, PT_EPC(sp)
+ MTC0 v1, CP0_EPC
+ LONG_L $31, PT_R31(sp)
+ LONG_L $28, PT_R28(sp)
+ LONG_L $25, PT_R25(sp)
+ LONG_L $7, PT_R7(sp)
+ LONG_L $6, PT_R6(sp)
+ LONG_L $5, PT_R5(sp)
+ LONG_L $4, PT_R4(sp)
+ LONG_L $3, PT_R3(sp)
+ LONG_L $2, PT_R2(sp)
+ .set pop
.endm
- .macro RESTORE_SP_AND_RET
- LONG_L sp, PT_R29(sp)
+ .macro RESTORE_SP_AND_RET
+ LONG_L sp, PT_R29(sp)
eret
nop
.endm
- .macro RESTORE_SP
- LONG_L sp, PT_R29(sp)
+ .macro RESTORE_SP
+ LONG_L sp, PT_R29(sp)
.endm
- .macro RESTORE_ALL
+ .macro RESTORE_ALL
RESTORE_TEMP
RESTORE_FPU
RESTORE_STATIC
@@ -243,7 +243,7 @@
RESTORE_SP
.endm
- .macro RESTORE_ALL_AND_RET
+ .macro RESTORE_ALL_AND_RET
RESTORE_TEMP
RESTORE_FPU
RESTORE_STATIC
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 12:41:11 +0000