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authormichael <[email protected]>2020-09-14 11:10:44 +0800
committermichael <[email protected]>2020-09-14 11:10:44 +0800
commita8928c881ed935a1e2a45bb02bd0b2a7fe8d45d4 (patch)
tree9b1f951e4033c30b8a776bb846569b661bb118d9 /libcpu/mips
parentbfebcac4d3a3526d75d1e2d9be11e57bba7506df (diff)
MIPS:fix the RT_EXCEPTION_MAX value
from <see mips run> know that cp0_cause's ExcCode have 5 bit filed and the max exception is 32.
Diffstat (limited to 'libcpu/mips')
-rw-r--r--libcpu/mips/common/exception.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index 94be475878..3da8ecead6 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -74,7 +74,7 @@ void rt_hw_interrupt_enable(rt_base_t level)
/**
* exception handle table
*/
-#define RT_EXCEPTION_MAX 31
+#define RT_EXCEPTION_MAX 32
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**