diff options
| author | michael <[email protected]> | 2021-01-31 22:33:58 +0800 |
|---|---|---|
| committer | michael <[email protected]> | 2021-01-31 22:33:58 +0800 |
| commit | 242530ae7017dbe0b5efae7796d6914c3c57f9ad (patch) | |
| tree | a45c852f83c013869e4f14e4d14f496242ac513a /libcpu/mips | |
| parent | d874ab11098e9384869db6ad4a86c5c5d65ca432 (diff) | |
ls1b: fix the count of GPIO IRQ and improvement the IRQ of UARTS.
from 1b manunal we know it have 64 GPIO IRQ and 12 UARTS
Diffstat (limited to 'libcpu/mips')
| -rw-r--r-- | libcpu/mips/gs232/ls1b.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h index 071a4aeb82..a6f244ef4f 100644 --- a/libcpu/mips/gs232/ls1b.h +++ b/libcpu/mips/gs232/ls1b.h @@ -19,6 +19,15 @@ #define LS1B_UART1_IRQ 3 #define LS1B_UART2_IRQ 4 #define LS1B_UART3_IRQ 5 +#define LS1B_UART4_IRQ 29 +#define LS1B_UART5_IRQ 30 +#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ +#define LS1B_UART7_IRQ 2 +#define LS1B_UART8_IRQ 2 +#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ +#define LS1B_UART10_IRQ 3 +#define LS1B_UART11_IRQ 3 + #define LS1B_CAN0_IRQ 6 #define LS1B_CAN1_IRQ 7 #define LS1B_SPI0_IRQ 8 @@ -49,7 +58,7 @@ #define LS1B_GPIO_IRQ 64 #define LS1B_GPIO_FIRST_IRQ 64 -#define LS1B_GPIO_IRQ_COUNT 96 +#define LS1B_GPIO_IRQ_COUNT 64 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) #define INT_PCI_INTA (1<<6) |