diff options
| author | Yaochenger <[email protected]> | 2022-12-28 14:06:39 +0800 |
|---|---|---|
| committer | Man, Jianting (Meco) <[email protected]> | 2022-12-28 18:47:39 -0500 |
| commit | 882a0af94ed60e181b7d8a509b6d3675286e7305 (patch) | |
| tree | b28d4f1f0fbbf74df303245cd39e9fad39064291 /libcpu/risc-v/common | |
| parent | bc767aa2d8f98900e86054158421dcb133d871d5 (diff) | |
[libcpu][riscv] 添加宏用于区别是否开启FPU，更新ch32v208v-r0 ->ch32v208w-r0，更新注释
Diffstat (limited to 'libcpu/risc-v/common')
| -rw-r--r-- | libcpu/risc-v/common/context_gcc.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index e458268e11..dbb5f8f4b5 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -8,6 +8,7 @@ * 2018/10/28 Bernard The unify RISC-V porting implementation * 2018/12/27 Jesven Add SMP support * 2020/11/20 BalanceTWK Add FPU support + * 2022/12/28 WangShun Add macro to distinguish whether FPU is supported */ #define __ASSEMBLY__ @@ -212,8 +213,11 @@ rt_hw_context_switch_exit: csrw mepc, a0 LOAD x1, 1 * REGBYTES(sp) - + #ifdef ARCH_RISCV_FPU li t0, 0x00007800 + #else + li t0, 0x00001800 + #endif csrw mstatus, t0 LOAD a0, 2 * REGBYTES(sp) csrs mstatus, a0 |