diff options
| author | zhangjun <[email protected]> | 2017-07-30 19:46:28 +0800 |
|---|---|---|
| committer | zhangjun <[email protected]> | 2017-07-30 19:46:28 +0800 |
| commit | b032dff1616fe64a4dfec63e593f0fac634ef3ab (patch) | |
| tree | 0906b0617156a4e898713bea4669a459406c44a3 /libcpu/risc-v/e310/init.c | |
| parent | 2d56a27c20d430f678a77e48f1d00591f4fc4c8b (diff) | |
fix bug in rt_hw_context_switch_interrupt_do
save sp to old thread
clear rt_thread_switch_interrupt_flag
always enable interrupt after rt_hw_context_switch
judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
Diffstat (limited to 'libcpu/risc-v/e310/init.c')
| -rw-r--r-- | libcpu/risc-v/e310/init.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/libcpu/risc-v/e310/init.c b/libcpu/risc-v/e310/init.c index 3a2b39614c..a8db529804 100644 --- a/libcpu/risc-v/e310/init.c +++ b/libcpu/risc-v/e310/init.c @@ -187,26 +187,6 @@ extern void handle_m_ext_interrupt(); extern void handle_m_time_interrupt(); #endif -uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) -{ - if (0){ -#ifdef USE_PLIC - // External Machine-Level interrupt from PLIC - } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { - handle_m_ext_interrupt(); -#endif -#ifdef USE_M_TIME - // External Machine-Level interrupt from PLIC - } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ - handle_m_time_interrupt(); -#endif - } - else { - write(1, "trap\n", 5); - _exit(1 + mcause); - } - return epc; -} void _init() { |