[libcpu] Add JuiceVm SUPPORT.

4 files changed, 200 insertions, 0 deletions

diff --git a/libcpu/risc-v/juicevm/SConscript b/libcpu/risc-v/juicevm/SConscript
new file mode 100755
index 0000000000..20f325b692
--- /dev/null
+++ b/libcpu/risc-v/juicevm/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/juicevm/interrupt.c b/libcpu/risc-v/juicevm/interrupt.c
new file mode 100755
index 0000000000..24b8be7f0c
--- /dev/null
+++ b/libcpu/risc-v/juicevm/interrupt.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021/04/24     Juice      The first version
+ */
+
+#include <rthw.h>
+
+#include <board.h>
+
+typedef void (*irq_handler_t)(void);
+extern const irq_handler_t isrTable[];
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc, uintptr_t *sp)
+{
+    uint32_t intNum;
+    if (mcause & 0x80000000) /* For external interrupt. */
+    {
+    }
+    else
+    {
+        intNum = mcause & 0x1FUL;
+        /* Now call the real irq handler for intNum */
+        if (intNum <= 24)
+        {
+            if (isrTable[intNum])isrTable[intNum]();
+        }
+    }
+}
diff --git a/libcpu/risc-v/juicevm/interrupt_gcc.S b/libcpu/risc-v/juicevm/interrupt_gcc.S
new file mode 100755
index 0000000000..8406926b5f
--- /dev/null
+++ b/libcpu/risc-v/juicevm/interrupt_gcc.S
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021/04/24     Juice      The first version
+ */
+
+#include "cpuport.h"
+
+.section      .text.entry
+.align 2
+.global trap_entry
+trap_entry:
+
+/* save thread context to thread stack */
+addi sp, sp, -32 * REGBYTES
+
+STORE x1,   1 * REGBYTES(sp)
+
+csrr  x1, mstatus
+STORE x1,   2 * REGBYTES(sp)
+
+csrr  x1, mepc
+STORE x1, 0 * REGBYTES(sp)
+
+STORE x4,   4 * REGBYTES(sp)
+STORE x5,   5 * REGBYTES(sp)
+STORE x6,   6 * REGBYTES(sp)
+STORE x7,   7 * REGBYTES(sp)
+STORE x8,   8 * REGBYTES(sp)
+STORE x9,   9 * REGBYTES(sp)
+STORE x10, 10 * REGBYTES(sp)
+STORE x11, 11 * REGBYTES(sp)
+STORE x12, 12 * REGBYTES(sp)
+STORE x13, 13 * REGBYTES(sp)
+STORE x14, 14 * REGBYTES(sp)
+STORE x15, 15 * REGBYTES(sp)
+STORE x16, 16 * REGBYTES(sp)
+STORE x17, 17 * REGBYTES(sp)
+STORE x18, 18 * REGBYTES(sp)
+STORE x19, 19 * REGBYTES(sp)
+STORE x20, 20 * REGBYTES(sp)
+STORE x21, 21 * REGBYTES(sp)
+STORE x22, 22 * REGBYTES(sp)
+STORE x23, 23 * REGBYTES(sp)
+STORE x24, 24 * REGBYTES(sp)
+STORE x25, 25 * REGBYTES(sp)
+STORE x26, 26 * REGBYTES(sp)
+STORE x27, 27 * REGBYTES(sp)
+STORE x28, 28 * REGBYTES(sp)
+STORE x29, 29 * REGBYTES(sp)
+STORE x30, 30 * REGBYTES(sp)
+STORE x31, 31 * REGBYTES(sp)
+
+/* switch to interrupt stack */
+move  s0, sp
+
+/* handle interrupt */
+call  rt_interrupt_enter
+csrr  a0, mcause
+csrr  a1, mepc
+mv    a2, s0
+call  handle_trap
+call  rt_interrupt_leave
+
+
+/* switch to from_thread stack */
+move  sp, s0
+
+/* need to switch new thread */
+la    s0, rt_thread_switch_interrupt_flag
+lw    s2, 0(s0)
+beqz  s2, spurious_interrupt
+sw    zero, 0(s0)
+
+la    s0, rt_interrupt_from_thread
+LOAD  s1, 0(s0)
+STORE sp, 0(s1)
+
+la    s0, rt_interrupt_to_thread
+LOAD  s1, 0(s0)
+LOAD  sp, 0(s1)
+
+spurious_interrupt:
+tail rt_hw_context_switch_exit
diff --git a/libcpu/risc-v/juicevm/startup_gcc.S b/libcpu/risc-v/juicevm/startup_gcc.S
new file mode 100755
index 0000000000..1a41c731fb
--- /dev/null
+++ b/libcpu/risc-v/juicevm/startup_gcc.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021/04/24     Juice      The first version
+ */
+
+
+.global   _start
+.section ".start", "ax"
+_start:
+.align 3
+csrw mideleg, 0
+csrw medeleg, 0
+csrw mie, 0
+csrw mip, 0
+la t0, trap_entry
+csrw mtvec, t0
+
+li x1, 0
+li x2, 0
+li x3, 0
+li x4, 0
+li x5, 0
+li x6, 0
+li x7, 0
+li x8, 0
+li x9, 0
+li x10, 0
+li x11, 0
+li x12, 0
+li x13, 0
+li x14, 0
+li x15, 0
+li x16, 0
+li x17, 0
+li x18, 0
+li x19, 0
+li x20, 0
+li x21, 0
+li x22, 0
+li x23, 0
+li x24, 0
+li x25, 0
+li x26, 0
+li x27, 0
+li x28, 0
+li x29, 0
+li x30, 0
+li x31, 0
+
+/* set to initial state of FPU and disable interrupt */
+li t0, 0
+csrs mstatus, t0
+
+.option push
+.option norelax
+la gp, __global_pointer$
+la   sp, __stack
+call entry
+call exit
+.option pop