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| author | Yunjie Gu <[email protected]> | 2022-10-20 04:41:13 +0100 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-10-19 23:41:13 -0400 |
| commit | 8fa9fde43a2e9cb978b52c0eb536fe2bafcc6e73 (patch) | |
| tree | 467394dde2b65c1ab6274059a1c475e72eefdb1d /libcpu/sim | |
| parent | 65baa8b697ab77e24c9d3f510e601893526e33e2 (diff) | |
[bsp][c28x] add support to not disable global interrupt in context-switch to enable zero-latency isr for critical interrupts.
Diffstat (limited to 'libcpu/sim')
0 files changed, 0 insertions, 0 deletions